Delta-sigma modulator

Abstract

To provide a delta-sigma modulator which controls magnitude of an adjustment signal.SOLUTION: A delta-sigma modulator 200 includes: an integration part for outputting an integration signal AOUT which is integration of an input signal ASIG; a quantization part having an allowable range for an inputted voltage, for outputting a quantized signal DOUTPRE which if a quantized signal of inputted signal; a feedback part 132 for subtracting a feedback signal AFB whose magnitude is according to the quantized signal from the input signal to be inputted to the integration part; an input adjustment part 114 for subtracting an adjustment signal AFBOFS having a voltage within the allowable range from the integration signal to be inputted to the quantization part; and an output correction part 150 for correcting the quantized signal according to the magnitude of the adjustment signal.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a delta-sigma modulator. [Background technology]

[0002] 2. Description of the Related Art Conventionally, incremental type ΔΣ AD converters that convert analog signals into digital codes are known (see, for example, Patent Document 1). [Prior art document] [Patent documents] Patent Document 1: JP 2019-118100 A Summary of the Invention

[0003] One aspect of the present invention provides a delta-sigma modulator. The delta-sigma modulator may include an integrating section that outputs an integrated signal obtained by integrating an input signal. Any of the delta-sigma modulators may include a quantizing section that has a tolerance range for an input voltage and outputs a quantized signal obtained by quantizing the input signal. Any of the delta-sigma modulators may include a feedback section that subtracts a feedback signal having a magnitude corresponding to the quantized signal from the input signal input to the integrating section. Any of the delta-sigma modulators may include an input adjusting section that subtracts an adjustment signal having a voltage within the tolerance range from the integrated signal input to the quantizing section. Any of the delta-sigma modulators may include an output correcting section that corrects the quantized signal according to the magnitude of the adjustment signal.

[0004] Any of the delta-sigma modulators described above may include a control unit that controls the magnitude of the adjustment signal based on the magnitude of the input signal.

[0005] Any of the above delta-sigma modulators may include a feedforward unit that transmits the input signal. Any of the above delta-sigma modulators may include an adder unit that adds the input signal transmitted by the feedforward unit to the integral signal output by the integrator unit and inputs the result to the quantizer unit. In any of the above delta-sigma modulators, the control unit may control a magnitude of the adjustment signal based on the quantized signal output by the quantizer unit in response to the input signal transmitted by the feedforward unit during a period in which the integrator unit is not outputting the integral signal.

[0006] Any of the delta-sigma modulators described above may include a control unit that controls the magnitude of the adjustment signal based on one digital value based on multiple outputs of the quantization unit.

[0007] In any of the delta-sigma modulators described above, the control section may control a magnitude of the adjustment signal further based on one digital value based on multiple outputs of the quantization section.

[0008] In any of the above-mentioned delta-sigma modulators, the control unit may control the magnitude of the adjustment signal based on the digital value when the fluctuation of the digital value is equal to or less than a set value, and may control the magnitude of the adjustment signal based on the input signal when the fluctuation of the digital value is greater than the set value.

[0009] In any of the above delta-sigma modulators, the input adjustment section may generate an adjusted input signal by subtracting the adjustment signal from the input signal, and add the adjusted input signal to the integrated signal input to the quantization section. In any of the above delta-sigma modulators, the control section may adjust a magnitude of the adjustment signal based on a magnitude of the adjusted input signal.

[0010] Any of the delta-sigma modulators described above may further include a monitor section that quantizes the adjusted input signal and inputs the quantized signal to the control section. In any of the delta-sigma modulators described above, the monitor section may have a smaller circuit scale than the quantization section.

[0011] The above summary of the invention does not list all of the necessary features of the present invention. In addition, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0012] [Figure 1] FIG. 2 is a diagram illustrating an example of the configuration of a delta-sigma modulator 300 according to a reference example. [Diagram 2] FIG. 2 is a diagram illustrating an example of the configuration of an integrating section 100. [Diagram 3] FIG. 1 is a diagram illustrating an example of the configuration of a delta-sigma modulator 200 according to an embodiment of the present invention. [Figure 4] FIG. 13 is a diagram illustrating another exemplary configuration of the delta-sigma modulator 200. [Diagram 5] FIG. 2 is a diagram showing a part of the configuration included in a control unit 140. [Figure 6] FIG. 13 is a diagram illustrating another exemplary configuration of the delta-sigma modulator 200. [Figure 7] FIG. 13 is a diagram illustrating another exemplary configuration of the delta-sigma modulator 200. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0014] 1 is a diagram showing a configuration example of a delta-sigma modulator 300 according to a reference example. The delta-sigma modulator 300 receives an input analog signal A SIG The quantized signal D OUT Convert the quantized signal D OUTis a digital signal of one or more bits. The delta-sigma modulator 300 is, for example, an incremental AD converter that resets the integral value of the integrator 100 to an initial value for each period of analog-to-digital conversion (AD conversion). For example, the quantizer 120 generates a quantized signal D OUT When controlling whether to output the quantized signal D, the AD conversion period may be N times the operation period of the quantization unit 120. N is a number equal to or greater than 1. In this case, the quantized signal D for N periods is OUT A digital value can be determined from the number of pulses included in the delta-sigma modulator 300. The delta-sigma modulator 300 alternates between an AD conversion period and a reset period.

[0015] 1 includes a subtraction section 110, an integration section 100, a quantization section 120, and a feedback section 132. The delta-sigma modulator 300 may further include a reset circuit 116, a feed-forward section 112, and an addition section 118.

[0016] The subtraction unit 110 subtracts the analog signal A SIG From feedback signal A FB Input signal A is subtracted IN In this example, the feedback signal A FB and input signal A IN is an analog signal.

[0017] The integrator 100 receives the input signal A IN The integrated signal A is OUT The integrating section 100 may perform an integration operation at the cycle of a clock signal supplied from an external device. A reset circuit 116 resets the output signal A output by the integrating section 100 at the end of each AD conversion period. OUT Resets the value of to its initial value.

[0018] The feedforward unit 112 receives the input signal A SIG The adder 118 transmits the integral signal A OUT , Input signal A SIG Addition signal ASUM The adder 118 generates the sum signal A SUM is input to the quantization unit 120.

[0019] The quantization unit 120 outputs the sum signal A SUM The quantized signal D OUT The quantization unit 120 may be an analog / digital converter (AD converter). The quantization unit 120 converts the binary quantized signal D OUT For example, the quantization unit 120 may output the sum signal A SUM A 1-bit quantizer outputs one pulse when the value of analog signal A is equal to or greater than a preset value, and does not output a pulse when the value is less than the preset value. SIG The magnitude of the quantization signal D OUT may be output.

[0020] The feedback unit 132 receives the quantized signal D OUT The feedback signal A has a magnitude according to FB The input signal A input to the integrator 100 SIG The feedback unit 132 in this example subtracts the feedback signal A FB is input to the subtraction unit 110. The feedback unit 132 receives the quantized signal D OUT Depending on the feedback signal A FB The feedback signal A may include a digital-to-analog converter (DA converter 130) for generating the feedback signal A FB For example, the quantized signal D OUT When the quantization unit 120 is a 1-bit quantizer, the DA converter 130 generates a feedback signal A of a preset magnitude every time the quantization unit 120 outputs a pulse. FB may be generated.

[0021] 2 is a diagram showing an example of the configuration of the integrating section 100. The integrating section 100 of this example has a plurality of integrators 101 connected in series. In the example of FIG. 2, an integrator 101-1, an integrator 101-2, and an integrator 101-3 are connected in series. The first-stage integrator 101-1 converts an input signal A IN The output signal A is the integrated OUT The second and subsequent integrators 101-m output the output signal A of the previous integrator 101-(m-1). OUT Output signal A obtained by integrating [m-1] OUT Outputs [m].

[0022] The integrating section 100 may have a plurality of gain circuits 102. The plurality of gain circuits 102 are provided corresponding to the plurality of integrators 101. Each gain circuit 102-m amplifies an output signal A OUT [m] is amplified with a predetermined gain and output. In the example of FIG. 2, the gain of each gain circuit 102-m is a m For example, the gain a m is a positive or negative value having an absolute value of 1 or more. The adder 118 adds the output signal of each gain circuit 102-m and the input signal A SIG Addition signal A SUM Output.

[0023] Addition signal A in this example SUM is shown in Equation 1.

number

number

[0024] Each component of the delta-sigma modulator 300 has an operable voltage range. The operable voltage range refers to the range of input voltages in which each component can operate normally. The allowable range of the input voltage of each component is determined, for example, by the power supply voltage applied to each component, or the voltage at which each component can operate linearly. The allowable range of the voltage of each component may be a specification value of each component determined by the manufacturer of the delta-sigma modulator 300, etc. If the specification value cannot be determined, the allowable range of the voltage input to each component may be from a low-voltage reference potential such as a ground potential applied to each component to a high-voltage potential such as a power supply voltage. In the quantization unit 120, the allowable range may be a voltage range in which the quantization unit 120 can perform linear AD conversion.

[0025] The quantization unit 120 receives the sum signal A from the addition unit 118. SUM The quantization unit 120 of this example has a tolerance range for the input voltage. SUM However, if the voltage falls outside the allowable range, the quantization unit 120 may not operate normally.

[0026] As an example, the allowable range of the input voltage to the quantization unit 120 is set to -1.5V to 1.5V. The integrating unit 100 in this example is a fully differential integrator, and the common voltage is set to 0V. Consider a case where the output voltage of each integrator 101 (or gain circuit 102) fluctuates within a maximum range of ±0.2V. The voltages input to the quantization unit 120 from the three integrators 101 (or gain circuits 102) fluctuate within a range of -0.6V to 0.6V. For this reason, in order to bring the input voltage to the quantization unit 120 within the allowable range, the input signal A SIG The voltage must be limited to −0.9 V to 0.9 V. This causes the signal-to-noise ratio in the quantization unit 120 to deteriorate.

[0027] 3 is a diagram showing an example of the configuration of a delta-sigma modulator 200 according to an embodiment of the present invention. In the delta-sigma modulator 200, the same components as those in the delta-sigma modulator 300 are denoted by the same reference numerals. The components have the functions described in FIGS. 1 and 2.

[0028] The delta-sigma modulator 200 further includes an input adjustment section 114 and an output correction section 150 in addition to the delta-sigma modulator 300 described in FIG. 1 and FIG. 2. The delta-sigma modulator 200 may further include a control section 140 and a DA converter 142. In this example, the quantized signal output by the quantization section 120 is converted into a D OUTPRE The quantized signal output by the output correction unit 150 is D OUT Let us assume that.

[0029] The input adjustment unit 114 adjusts the integral signal A OUT (In this example, the integral signal A OUT The sum signal A generated from SUM ) to obtain a predetermined adjustment signal A FBOFS Adjusted input signal A with SIG2 The adjustment signal A is generated. FBOFS has a voltage within the allowable range of the input voltage of the quantization unit 120. For example, when the allowable range of the input voltage of the quantization unit 120 is −1.5 V to 1.5 V, the adjustment signal A FBOFS The voltage of the adjustment signal A is in the range of -1.5V to 1.5V. FBOFS The voltage of may be a predetermined fixed voltage, and the input signal A SIG The adjustment signal A may be a variable voltage that changes depending on the magnitude of the signal input to the quantization unit 120. FBOFS By subtracting in advance, it is possible to prevent the voltage input to the quantization unit 120 from falling outside the allowable range of the input voltage to the quantization unit 120.

[0030] The output correction unit 150 corrects the adjusted signal A input to the input adjustment unit 114. FBOFS Depending on the magnitude of OUTPRE The quantized signal D OUT The output correction unit 150 outputs the adjustment signal A FBOFS The digital value that indicates the magnitude of the quantized signal D OUTPRE The quantized signal D is added to the digital value indicated by OUTPRE For example, adjustment signal A FBOFSWhen the magnitude of the quantized signal D is 1V, the output correction unit 150 adjusts the quantized signal D so that a digital value equivalent to 1V is added. OUTPRE The output correction unit 150 corrects the quantized signal D OUTPRE The digital value indicated by may be corrected, and the quantized signal D OUTPRE A pulse may be added to the corrected quantized signal D OUT By increasing the pulse density of the quantized signal D OUT The digital value represented by the quantized signal D during the AD conversion can be increased. OUT When determining one digital value based on FBOFS A digital value according to the magnitude of the signal may be added.

[0031] The control unit 140 outputs the adjustment signal A FBOFS The control unit 140 controls the magnitude of the adjustment signal A FBOFS The control unit 140 may input the digital value to the DA converter 142 and also to the output correction unit 150. The control unit 140 may input a pulse train corresponding to the digital value to the output correction unit 150. The DA converter 142 converts the digital value from the control unit 140 into an analog adjustment signal A. FBOFS and inputs it to the input adjustment unit 114.

[0032] According to the delta-sigma modulator 200 of this embodiment, the input adjustment unit 114 is provided, so that the input signal A SIG This can widen the voltage range of the adjustment signal A. This can improve the signal-to-noise ratio in the quantization unit 120. FBOFS This can offset the decrease in digital value caused by

[0033] The control unit 140 receives the input signal A SIG Based on the magnitude of FBOFS The magnitude of the adjustment signal A may be controlled. FBOFS The voltage value of the input signal A SIGmay be the same as the voltage value of the input signal A SIG The voltage value may be multiplied by a predetermined coefficient. The coefficient may be smaller than 1.

[0034] The control unit 140 of this example utilizes the feedforward unit 112 and the quantization unit 120 to convert the input signal A SIG In this case, the magnitude of the input signal A SIG Therefore, it is possible to suppress an increase in the circuit scale of the delta-sigma modulator 200 and reduce the circuit area. OUT During the period when the input signal A is not being output, SIG The magnitude of the integrated signal A may be measured during this period. This period is the reset period described above. That is, this period is the period from when the reset circuit 116 resets the output of the integrating section 100 until the integrating section 100 outputs a new integrated signal A. OUT This is the period until the device starts outputting.

[0035] The feedforward unit 112 receives the input signal A even during the reset period. SIG During the reset period, the adjustment signal A FBOFS The magnitude of the sum signal A output from the adder 118 during the reset period is controlled to a predetermined value (for example, 0 V). SUM is the input signal A SIG From adjustment signal A FBOFS Even during the reset period, the quantization unit 120 outputs the quantized signal D OUTPRE That is, the quantization unit 120 outputs the quantized signal D OUTPRE is the input signal A SIG and adjustment signal A FBOFS This is a signal obtained by quantizing the difference signal between the adjustment signal A and the adjustment signal B. FBOFS The magnitude of the quantized signal D is known because it is controlled by the control unit 140. OUTPRE Based on the input signal A SIG The control unit 140 can determine the magnitude of the quantized signal D output by the quantization unit 120 during the reset period.OUTPRE Based on this, the adjustment signal A FBOFS This controls the magnitude of the input signal A SIG Adjustment signal A according to the magnitude of FBOFS can be generated.

[0036] During the AD conversion period, the control unit 140 SIG Adjustment signal A according to FBOFS and adjusting signal A FBOFS The digital value according to the input signal A is input to the output correction unit 150. This allows the quantization unit 120 to operate normally. SIG During the reset period, the control unit 140 controls the adjustment signal A FBOFS The magnitude of the quantized signal D output by the quantizer 120 at the end of the AD conversion period is set to a predetermined value, and the digital value input to the output correction unit 150 is set to a value corresponding to the predetermined value. OUTPRE The magnitude of the reset signal may be the same as that of the reset signal, or may be 0 V. The control unit 140 may control the timing at which the reset circuit 116 resets.

[0037] The quantized signal D output by the quantizer 120 during the reset period OUTPRE is the number 3.

number

[0038] The integrating section 100 may have the configuration shown in Fig. 2. In this example, a1 = a2 = 3, and a3 = 1. However, the gain values ​​are not limited to these. In this case, the sum signal during the AD conversion period is expressed by Equation 4.

number

number

[0039] Using number 5, number 4 can be transformed into number 6.

number

[0040] The quantization error E1 generally has a voltage range that depends on the number of quantizers. The voltage range is shown in Equation 7. FS is a predetermined voltage value, for example, 1.5 V. LSB indicates the number of quantizers.

number

[0041] The quantized signal D output by the delta-sigma modulator 200 OUT is expressed by the following equation 8. E2 is the quantization error in the quantization unit 120.

number

[0042] In the formula 8, the adjustment signal A FBOFS quantized signal D OUTPRE is the DA converted signal. Equation 8 can be transformed into Equation 9.

number

[0043] Output signal A of each integrator 101 OUT The initial value of [m] is set to 0, and the input signal A SIG is set as a constant value. The quantized signal output by the quantizer 120 for the i-th time during the AD conversion period is D OUT (i) Input signal A SIG is shown in number 10.

number

[0044] 4 is a diagram showing another example of the configuration of the delta-sigma modulator 200. The delta-sigma modulator 200 of this example further includes a filter 160 in addition to the configuration of the delta-sigma modulator 200 described in FIG. 3. Also, the control unit 140 in the example of FIG. 3 converts the quantized signal D OUTPRE Adjustment signal A based on FBOFS In the present embodiment, the control unit 140 controls the magnitude of the digital signal D SIG Adjustment signal A based on FBOFSThe other structures and functions are similar to those of the example in FIG.

[0045] The filter 160 converts a digital signal D, which indicates one digital value, into a digital signal D, based on multiple outputs of the quantizer 120. SIG For example, the quantization unit 120 generates a quantized signal D OUT In the case of controlling whether or not to output a digital signal D, the multiple outputs of the quantization unit 120 refer to the output of the quantization unit 120 over multiple periods. The multiple outputs of the quantization unit 120 may be the output of the quantization unit 120 in one AD conversion period. For example, the filter 160 outputs a digital signal D SIG In this example, N is a number equal to or greater than 2.

[0046] The control unit 140 receives the digital signal D SIG Adjustment signal A based on FBOFS The control unit 140 controls the magnitude of the digital signal D determined in the previous AD conversion period and also controls the digital value input to the output correction unit 150. SIG Based on this, the adjustment signal A for this AD conversion period is FBOFS In addition, the digital value input to the output correction section 150 may be controlled.

[0047] Digital signal D SIG is the input signal A SIG This shows the magnitude of the digital signal D SIG The control unit 140 operates based on the input signal A SIG Adjustment signal A according to FBOFS In this example, the input signal A can be generated so that the quantizer 120 can operate normally. SIG In addition, by providing the output correction unit 150, the voltage range of the adjustment signal A FBOFS The delta-sigma modulator 200 of this embodiment can cancel the decrease in the digital value due to the AD conversion period. SIG Since we use the input signal A SIGTherefore, it is possible to operate at a higher speed than the delta-sigma modulator 200 in the example of FIG.

[0048] 5 is a diagram showing a part of the configuration included in the control unit 140. The control unit 140 in this example has a bit shift circuit 144. The bit shift circuit 144 shifts an M-bit digital signal D SIG The bit shift circuit 144 inputs the ML-bit digital value to the DA converter 142 and the output correction unit 150. The ML bits match the number of input bits of the DA converter 142. By providing the bit shift circuit 144, the digital signal D SIG Even if the number of bits of the digital signal D SIG Adjustment signal A based on FBOFS can be generated.

[0049] 6 is a diagram showing another example of the configuration of the delta-sigma modulator 200. The configuration of the delta-sigma modulator 200 of this example is similar to that of the delta-sigma modulator 200 shown in FIG. 4. However, the control unit 140 of this example receives a digital signal D SIG and the quantized signal D OUTPRE Both are input, and the digital signal D SIG and the quantized signal D OUTPRE Adjustment signal A based on FBOFS and the digital value to the output correction unit 150.

[0050] The control unit 140 of this example, like the control unit 140 shown in FIG. 3, measures the quantized signal D OUTPRE Adjustment signal A based on FBOFS 4, the control unit 140 controls the magnitude of the digital signal D measured in the previous AD conversion period. SIG Adjustment signal A based on FBOFS The control unit 140 can switch between an operation of controlling the magnitude of the input signal A and an operation of controlling the magnitude of the input signal B. SIG The quantized signal D OUTPRE or operates based on a digital signal DSIG The device may switch between operating based on the

[0051] Input signal A SIG If the frequency of input signal A is greater than the set value (i.e., it is a high-frequency signal), SIG In this case, the control unit 140 determines the magnitude of the quantized signal D measured during the most recent reset period. OUTPRE Based on this, the adjustment signal A during the AD conversion period FBOFS This allows for more accurate adjustment of the adjustment signal A FBOFS can be generated.

[0052] Input signal A SIG When the frequency of input signal A is below the set value (i.e., it is a low-frequency signal), SIG In this case, the control unit 140 determines the magnitude of the digital value D measured in the previous AD conversion period as SIG Based on this, the adjustment signal A FBOFS In this case, the delta-sigma modulator 200 can operate at a higher speed.

[0053] The control unit 140 receives the digital signal D SIG Based on the variation of the digital value of the quantized signal D OUTPRE or operates based on a digital signal D SIG The fluctuation in the digital value is the difference between the digital value in the previous AD conversion period and the digital value in the current AD conversion period.

[0054] The control unit 140 receives the digital signal D SIG When the change in the digital value of input signal A is greater than the set value, SIG (In this example, the quantized signal D measured during the reset period OUTPRE ) based on the adjustment signal A in the next AD conversion period. FBOFS This allows for more accurate adjustment of the adjustment signal A FBOFS can be generated.

[0055] The control unit 140 receives the digital signal D SIG When the fluctuation of the digital value of is less than the set value, the digital signal D SIG Based on the digital value of FBOFS may be controlled, in which case the delta-sigma modulator 200 can operate faster.

[0056] Which operation the control unit 140 performs may be set by a user of the delta-sigma modulator 200 or the like. Also, which operation the control unit 140 performs may be set in advance by a manufacturer of the delta-sigma modulator 200 or the like.

[0057] Fig. 7 is a diagram showing another example of the configuration of the delta-sigma modulator 200. The delta-sigma modulator 200 of this example further includes a monitor unit 170 in addition to the delta-sigma modulator 200 of any of the aspects described with reference to Figs. 3 to 6. The other structures are similar to those of the delta-sigma modulator 200 of any of the aspects described with reference to Figs. 3 to 6.

[0058] The monitor unit 170 receives the adjusted input signal A SIG2 and inputs it to the control unit 140. The monitor unit 170 has a smaller circuit scale than the quantization unit 120. The circuit scale may be the area of ​​the circuit on a circuit board. The circuit scale may be expressed by the number of bits of the quantized signal output by each circuit. In other words, the smaller the number of bits of the output quantized signal, the smaller the circuit scale. The monitor unit 170 of this example quantizes the quantized signal D OUTPRE The number of bits of the signal output by the monitor unit 170 is, for example, 1 bit. The monitor unit 170 outputs a signal having a smaller number of bits than the adjusted input signal A. SIG2 The quantization unit 120 may output a signal indicating the result of comparing the quantized signal D OUTPRE The quantized signal D OUTPRE may be 2 or more bits.

[0059] The control unit 140 outputs the adjusted input signal A SIG2Based on the magnitude of FBOFS The control unit 140 of this example adjusts the magnitude of the adjustment signal A based on the signal output by the monitor unit 170. FBOFS The control unit 140 adjusts the magnitude of the adjusted input signal A SIG2 The larger the value of the adjustment signal A FBOFS Adjust the signal A so that FBOFS For example, the control unit 140 may adjust the adjusted input signal A SIG2 When the adjustment signal A exceeds the set value, FBOFS Adjust it to a larger value.

[0060] Input signal A during AD conversion period SIG When the value of adjustment signal A changes, FBOFS If is a constant value, the sum signal A SUM The control unit 140 of this example increases the possibility that the voltage of the adjusted input signal A will be outside the allowable range of the quantization unit 120. SIG2 Adjustment signal A based on FBOFS This adjusts the magnitude of the input signal A during the AD conversion period. SIG Even if the value fluctuates, the adjustment signal A FBOFS Therefore, the sum signal A SUM This can prevent the voltage from falling outside the allowable range of the quantization unit 120.

[0061] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0062] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0063] 100...integration section, 101...integrator, 102...gain circuit, 110...subtraction section, 112...feedforward section, 114...input adjustment section, 116...reset circuit, 118...addition section, 120...quantization section, 130...DA converter, 132...feedback section, 140...control section, 142...DA converter, 144...bit shift circuit, 150...output correction section, 160...filter, 170...monitor section, 200...delta-sigma modulator, 300...delta-sigma modulator

Claims

1. an integrating section that outputs an integrated signal obtained by integrating an input signal; a quantization unit that has a tolerance range for an input voltage and that quantizes an input signal and outputs a quantized signal; a feedback section that subtracts a feedback signal having a magnitude corresponding to the quantized signal from the input signal that is input to the integrating section; an input adjustment unit that subtracts an adjustment signal having a voltage within the tolerance range from the integral signal that is input to the quantization unit; an output correction unit that corrects the quantized signal in accordance with the magnitude of the adjustment signal; 1. A delta-sigma modulator comprising:

2. a control unit that controls the magnitude of the adjustment signal based on the magnitude of the input signal 2. The delta-sigma modulator of claim 1.

3. a feedforward unit that transmits the input signal; an adder unit that adds the input signal transmitted by the feedforward unit to the integral signal output by the integrator unit and inputs the resultant signal to the quantizer unit; Further comprising: The control unit controls a magnitude of the adjustment signal based on the quantized signal output by the quantization unit in response to the input signal transmitted by the feedforward unit during a period in which the integration unit does not output the integration signal.

3. The delta-sigma modulator of claim 2.

4. A control unit that controls the magnitude of the adjustment signal based on one digital value based on multiple outputs of the quantization unit.

2. The delta-sigma modulator of claim 1.

5. The control unit controls the magnitude of the adjustment signal further based on one digital value based on multiple outputs of the quantization unit.

3. The delta-sigma modulator of claim 2.

6. The control unit controls the magnitude of the adjustment signal based on the digital value when the fluctuation of the digital value is equal to or smaller than a set value, and controls the magnitude of the adjustment signal based on the input signal when the fluctuation of the digital value is greater than the set value.

6. The delta-sigma modulator of claim 5.

7. the input adjustment unit generates an adjusted input signal by subtracting the adjustment signal from the input signal, and adds the adjusted input signal to the integral signal to be input to the quantization unit; The control unit adjusts the magnitude of the adjusted signal based on the magnitude of the adjusted input signal. A delta-sigma modulator according to any one of claims 2 to 6.

8. a monitor unit that quantizes the adjusted input signal and inputs the quantized input signal to the control unit; The monitor unit has a smaller circuit scale than the quantization unit.

8. The delta-sigma modulator of claim 7.

Images