Memory equivalent method of duplex control system

Abstract

To improve the reliability of a duplex control system.SOLUTION: PLCs 2 and 3 include condition change detection mechanisms 10c and 11c that detect condition changes in user data memories 10b and 11b, duplexed tasks 10d and 11d that make equivalent the condition change in the memory 10b to the memory 11b, and BG tasks 10e and 11e that calculate a checksum of the memories 10b and 11b, respectively. On the PLC 3 side, the checksum of the memory 11b is transmitted to the PLC 3 side. The condition change detection mechanism 10c compares checksums with each other, and detects a condition change when pieces of information of the checksums are different from each other. The duplexed task 10d performs equivalent transmission of memory information on a block, where a condition change is detected, as equivalent data to the duplexed task 11d. When receiving the equivalent transmission, the duplexed task 11d updates the information of the memory 11b on the basis of the equivalent data.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present invention relates to a memory equalization method for a dual-system control system having a master controller and a slave controller. [Background technology]

[0002] Programmable logic controllers (hereinafter referred to as PLCs) are primarily used as control devices for connected devices and equipment, and their main operation is sequence calculation.

[0003] For PLCs, duplicated systems are often constructed to continue operation when an abnormality occurs.Duplexed systems have an active PLC (active station) that acts as the control system (master / main system) and a standby PLC (standby station) that acts as the standby system (slave / subsystem), and under normal circumstances, the active PLC controls connected devices based on the calculation results.

[0004] On the other hand, when an abnormality occurs, the control system is switched to the standby PLC, and input / output information from control devices is sent to the standby PLC by performing equivalent processing, which reflects the calculation results of the active PLC in the standby PLC as equivalent data.

[0005] However, because the standby PLC is always performing calculations in order to allow for high-speed switching in the event of an abnormality, there is a risk that the equivalent data may be overwritten during calculations by the standby PLC. Therefore, the equivalent processing cannot be performed during calculations, and is instead performed when calculations are not being performed. Patent Document 1 is a publicly known technology for this equivalent processing. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2021-152855 [Non-patent literature]

[0007] [Non-Patent Document 1] "Checksum calculation tool" Internet URL searched on June 27, 2023<https: / / messy-soft.com / file / binary3> Summary of the Invention [Problem to be solved by the invention]

[0008] In Patent Document 1, the user data memory (equivalent memory) that stores equivalent data is divided into 128 blocks, and only the blocks in which a state change occurs due to the sequence calculations of the active PLC are equivalent to the standby PLC, thereby speeding up the equalization process.

[0009] However, since the active PLC is only equalized to the standby PLC if a state change occurs due to the sequence calculation of the active PLC, there is a risk that the data held between the two PLCs will differ when a specific sequence calculation process is performed, and normal equalization will not be possible.

[0010] An example of a case where equalization is not performed normally will be described with reference to Figures 1 to 6. Figure 1 shows the sequence calculation performed by the active PLC, and Figures 2(a) and (b) show the user data memories of the active PLC and the standby PLC, respectively.

[0011] As shown in Figure 3, when the active PLC executes the sequence calculation of a task, the value of the user data memory 4000H is rewritten from "1000H" to "2000H." Therefore, the active PLC detects the occurrence of a state change and makes the memory data of the user data memory 4000H equivalent to that of the standby PLC, as shown in Figure 4.

[0012] At this time, when the standby PLC executes a sequence operation, the value of user data memory 4000H is rewritten from "2000H" to "3000H" as shown in Figure 5. This makes the condition of rung 2-4 in Figure 1 "TRUE", and bit 0 of user data memory 7FDAH becomes "ON".

[0013] 6, the value of the user data memory 1000H of the active PLC becomes "0" due to communication from a lower device, and the active PLC becomes equivalent to the standby PLC. Here, according to the condition of rung 2-1, if the value of the user data memory 1000H is "1000" or more, rung 2-2 is processed.

[0014] In the situation in Figure 6, because the condition of rung 2-1 is "FALSE", no change occurs in the user data memory 4000H when the active PLC executes a sequence operation. As a result, a difference occurs in the data held by the active PLC and the standby PLC, which may cause a loss of reliability in the redundant system.

[0015] The present invention has been made to solve such problems in the conventional art, and has as its object to improve the reliability of the dual engagement control system. [Means for solving the problem]

[0016] (1) The present invention comprises a master and slave control device, A memory equalization method for a duplicated control system that equalizes a calculation result of the primary system to a secondary system, comprising: The primary system and the secondary system are A data memory for calculations; A state change detection mechanism that detects a change in information in the data memory as a state change; a duplication task for equalizing the state change of the primary system to the data memory of the secondary system; a background task for calculating a checksum of said data memory; Equipped with The state change detection mechanism of the main system is characterized in that it compares the checksums with each other and detects the state change if the information between the two checksums differs.

[0017] (2) In one embodiment of the present invention, The slave system transmits the checksum to the master system at regular intervals, The master system is characterized in that, upon receiving the checksum, it performs the comparison in the abnormality detection mechanism.

[0018] (3) In another embodiment of the present invention, Each of the background tasks calculates the checksum for each block of the data memory divided into a predetermined number of blocks; The slave sets the checksum of each block and the corresponding block number and transmits them to the master. The state change detection mechanism of the master system compares the checksum received from the slave system with the checksum of the corresponding block of the data memory of the master system; If the checksums differ from each other, the abnormality in the state of the corresponding block is detected.

[0019] (4) In yet another embodiment of the present invention, The duplication task of the main system is The memory information of the block in which the state change has been detected is transmitted as equivalent data to the duplicated task of the slave system in an equivalent manner.

[0020] (5) In yet another embodiment of the present invention, The slave duplication task is When the equivalent transfer is received, the information of the corresponding block of the memory data of the device itself is updated based on the equivalent data.

[0021] (6) The background task can calculate the checksum when other tasks are not running. Effect of the Invention

[0022] According to the present invention, it is possible to improve the reliability of a dual-lock control system. [Brief description of the drawings]

[0023] [Figure 1] A diagram of sequence operations performed by an active PLC. [Diagram 2] (a) is a diagram of the user data memory of the active PLC, and (b) is a diagram of the user data memory of the standby PLC. [Diagram 3] (a) is a diagram of the user data memory after the active PLC executes a task, and (b) is a diagram of the user data memory of the standby PLC. [Figure 4] (a) is a diagram of the user data memory of the active PLC after equivalent execution, and (b) is a diagram of the user data memory of the standby PLC. [Diagram 5] (a) is a diagram of the user data memory of the active PLC, and (b) is a diagram of the user data memory of the standby PLC after task execution. [Figure 6] (a) is a state diagram in which the value of 1000H in the user data memory of the active PLC becomes "0" due to the reception of an option, etc., and (b) is a state diagram of the user data memory of the same standby PLC. [Figure 7] FIG. 1 is a configuration diagram of a PLC duplex system according to an embodiment of the present invention. [Figure 8] The same diagram of transmission between active and standby. [Figure 9] A comparison diagram of checksums in the same active PLC. [Figure 10] Equivalent transmission diagram. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The following describes a memory equivalence method for a dual-system control system according to an embodiment of the present invention. In this embodiment, the memory equivalence method is applied to a PLC dual-system, and the active PLC and the standby PLC share information in their respective equivalence areas (user data memory) to improve reliability.

[0025] <System configuration example> In FIG. 7, reference numeral 1 denotes the PLC duplex system, which includes an active PLC (active station) 2 serving as a control system (master / main system) and a standby PLC (standby station) 3 serving as a standby system (slave / subsystem).

[0026] Here, both the active PLC 2 and the standby PLC 3 execute sequence calculations, and if there is a change in the state of the user data memory 10b of the active PLC 2, it is made equivalent to the user data memory 11b of the standby PLC 3 by the memory equivalent function.

[0027] Specifically, each of the PLCs 2 and 3 is configured by a computer. (1) User tasks 10a and 11a (2) the memories 10b and 11b (3) Deformation detection mechanism 10c, 11c (4) Duplication tasks 10d, 11d (5) Background tasks (hereafter referred to as BG tasks) 10e, 11e Implement.

[0028] The user tasks 10a and 11a execute sequence calculations for the PLCs 2 and 3. At this time, the user can freely use the memories 10b and 11b during the sequence calculations.

[0029] The state change detection mechanism units 10c, 11c detect state changes in the memory 10b of the primary system, i.e., detect discrepancies between memory information (memory data). Here, the duplication tasks 10d, 11d execute equalization processing to reflect state changes in the memory 11b if there are state changes in the memory 10b of the primary system. The duplication tasks 10d, 11d execute active-standby transmissions at 20 ms intervals to confirm the survival of each PLC 2, 3 (confirm normal operation).

[0030] The BG tasks 10e and 11e are tasks that operate in the background with the lowest priority, and calculate a checksum (checksum / CSM: error detection code) for each block of the memories 10b and 11b when other tasks are not operating. For the calculation of this checksum, a publicly known tool such as Non-Patent Document 1 can be used.

[0031] <<Operation / Processing>> An example of operation processing (S01 to S03) of the PLC duplex system 1 will be described with reference to Figures 8 to 10. That is, if there is a mismatch in the checksum information of the memories 10b and 11b between the PLCs 2 and 3, a state change is detected and memory equalization is performed.

[0032] Here, the memories 10b, 11b of the PLCs 2, 3 are divided into 128 blocks, and the BG tasks 10e, 11e calculate the checksum of each block of the memories 10b, 11b.

[0033] S01: The duplex tasks 10d and 11d of both PLCs 2 and 3 perform active-standby transmission at 20 ms intervals as described above.

[0034] At this time, the duplication task 11d sets the checksum of each block of the memory 11b in the active-standby transmission in the order of block numbers. That is, (1) Block number (2) The checksum of the block corresponding to the block number is set individually for each transmission between active and standby.

[0035] For example, FIG. 8 shows a state in which the checksum of block number 1 is set in the active-standby transmission and transmitted to the duplication task 10d.

[0036] S02: When the active PLC 2 receives the transmission of S01, the state change detection mechanism 10c compares the received checksum with the checksum of the corresponding block in the memory 10b. For example, in Fig. 9, the checksum of block number 1 set in the active-standby transmission in Fig. 8 is compared with the checksum of block number 1 in the memory 10b.

[0037] S03: If the checksums are different as a result of the comparison in S02, the state change detection mechanism 10c detects the state change in the memory 10b and commands the duplication task 10d to perform equalization processing. At this time, the duplication task 10d transmits the memory information of the state change block in which the state change has been detected to the PLC 3 as state change data (equivalent data).

[0038] The duplication task 11d of the standby PLC 3 that received this equivalent transmission overwrites and updates the block of the corresponding block number in the memory 11b based on the state change data, and reflects the state change data in the memory 11b. On the other hand, if the information in both checksums is not different, the state change is not detected and the equalization process is not commanded.

[0039] By repeatedly performing the processes of S01 to S03 in the order of block numbers 1 to 128, it is possible to match the memory information in the memories 10b, 11b of both PLCs 2, 3. In this respect, the reliability of the PLC duplex system 1 can be improved.

[0040] At this time, the SBG tasks 10e and 11e operate only when other tasks are not operating, as described above, and therefore there is no risk of imposing a load on normal PLC operations.

[0041] Furthermore, when the master / slave roles of PLC2 and PLC3 are switched (PLC3 is active and PLC2 is on standby), the duplex task 10d of PLC2 sets the checksum in the memory 10b to the duplex task 11d of PLC3 for active-standby transmission (S11).

[0042] As a result, the checksum of the memory 10b is transmitted to the PLC 3, a state change is detected by the state change detection mechanism 11c of the PLC 3 (S12), and equivalent transfer is performed by the duplication task 11d (S13).

[0043] The present invention is not limited to the above embodiment, and can be modified within the scope of the claims. For example, the system configuration is not limited to that shown in FIG. 7, and can be modified as appropriate as long as the comparison process between the memories 10b and 11b of the PLCs 2 and 3 using a checksum can be performed. [Explanation of symbols]

[0044] 1. PLC duplex system 2...Active PLC 3…Standby PLC 10a, 11a...User tasks 10b, 11b...User data memory 10c, 11c…Deformation detection mechanism 10d, 11d…Duplex task 10e, 11e...Background tasks

Claims

1. Equipped with a master and slave control device, A memory equalization method for a duplicated control system that equalizes a calculation result of the primary system to a secondary system, comprising: The primary system and the secondary system are A data memory for calculations; A state change detection mechanism that detects a change in information in the data memory as a state change; a duplication task for equalizing the state change of the primary system to the data memory of the secondary system; a background task for calculating a checksum of said data memory; Equipped with The state change detection mechanism of the main system compares the checksums with each other, and detects the state change if the information between the two checksums differs. A memory equalization method for a dual-system control system.

2. The slave system transmits the checksum to the master system at regular intervals, When the main system receives the checksum, the abnormality detection mechanism performs the comparison.

2. The memory equalization method for a dual control system according to claim 1.

3. Each of the background tasks calculates the checksum for each block of the data memory divided into a predetermined number of blocks; The slave sets the checksum of each block and the corresponding block number and transmits them to the master. The state change detection mechanism of the master system compares the checksum received from the slave system with the checksum of the corresponding block of the data memory of the master system; 3. The memory equalization method for a duplicated control system according to claim 2, wherein if the information in said checksums differ from each other, said change in state of the corresponding block is detected.

4. The duplication task of the main system is The memory information of the block in which the change in state is detected is transmitted to the slave system duplication task as equivalent data.

4. The memory equalization method for a duplicated control system according to claim 3.

5. The slave duplication task is When the equivalent transfer is received, the information of the corresponding block of the memory data is updated based on the equivalent data.

5. The memory equalization method for a duplicated control system according to claim 4.

6. The background task calculates the checksum when no other tasks are running.

6. A memory equalization method for a dual control system according to claim 1.

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