Delta sigma type modulator

Abstract

To provide a delta sigma type modulator capable of further reducing a detection error when a resistance element is connected to a pre-stage of an input.SOLUTION: In a delta sigma type modulator 1, a switch 29 for chopping a quantizer is connected to an output side of a quantizer 5, and first and third switches 10, 13 for chopping amplifiers are connected to input and output sides of a capacitive coupling amplifier 2. Signals modulated by chopping operations of the first and third chopping switches are demodulated by a chopping operation of the switch 29 for chopping the quantizer. The chopping operations of the first and third chopping switches are performed at 1 / 2 of an operation frequency of the switch for chopping the quantizer and a timing at which phases are different by 90 degrees from each other.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a delta-sigma modulator. [Background technology]

[0002] For example, Patent Document 1 discloses a configuration in which chopping is performed at the same frequency at the input / output of a portion performing A / D conversion operation and at the input / output of an integral capacitance in an integrator in a delta-sigma modulator. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Publication 2022 / 0263520 Specification Summary of the Invention [Problem to be solved by the invention]

[0004] In the configuration of Patent Document 1, it is assumed that a resistive element constituting an anti-aliasing filter or the like is connected in front of the input. In this case, the switched capacitor operation causes the absorption of electric charge, which causes a voltage drop in the resistive element, and this voltage drop results in a detection error.

[0005] The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a delta-sigma modulator that can further reduce detection errors when a resistive element is connected in the front stage of the input. [Means for solving the problem]

[0006] The delta-sigma modulator according to claim 1 includes a capacitively coupled amplifier (2), a correlated double sampling integrator (3), and a quantizer (5). A quantizer chopping switch (29) is connected to the output side of the quantizer, and at least two amplifier chopping switches (10, 11, 12, 36-38) are connected to the input side or the input side and output side of the capacitively coupled amplifier. A signal modulated by the chopping operation of the amplifier chopping switch is demodulated by the chopping operation of the quantizer chopping switch. The chopping operations of the amplifier chopping switch are performed at a frequency half the operating frequency of the quantizer chopping switch and at timings that are 90 degrees out of phase with each other.

[0007] Even in a configuration in which a resistive element is connected in front of the amplifier chopping switch on the input side of the capacitively coupled amplifier, the amount of charge absorbed by the switched capacitor operation can be reduced by setting the frequency of the chopping operation on the input side of the capacitively coupled amplifier to half that of the chopping operation on the output side of the quantizer. Also, by setting the phases of the chopping by at least two amplifier chopping switches to timings that differ by 90 degrees from each other, the offset caused by the switching of chopping can be reduced. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a delta-sigma modulator according to a first embodiment. [Diagram 2] Diagram showing detailed configuration of chopping switch [Diagram 3] Timing chart showing control signals for main chopping switches [Figure 4] FIG. 11 is a diagram showing a configuration of a delta-sigma modulator according to a second embodiment. [Diagram 5] FIG. 13 is a diagram showing a configuration of a delta-sigma modulator according to a third embodiment. [Figure 6] FIG. 13 is a diagram showing a configuration of a delta-sigma modulator according to a fourth embodiment. [Figure 7]FIG. 13 is a diagram showing a configuration of a delta-sigma modulator according to a fifth embodiment. [Figure 8] Timing chart showing control signals for main chopping switches DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] (First embodiment) As shown in FIG. 1, the delta-sigma modulator 1 of this embodiment is a differential type, and includes a capacitively coupled amplifier 2, a first integrator 3, a second integrator 4, and a quantizer 5. In the figure, the reference characters for each side of the differential configuration are marked with "a, b", but since the configuration is symmetrical, the reference characters are not marked with "a, b" unless there is a need to distinguish them. A capacitor 7 and a series circuit of switches 8 and 9 are connected in parallel between the input terminal and the output terminal of an operational amplifier 6 constituting the capacitively coupled amplifier 2. The common connection point of the switches 8 and 9 is connected to the ground. Voltages Vinp and Vinm are input to the input terminals of the operational amplifier 6 via first and second amplifier chopping switches 10 and 11, and a capacitor 12.

[0010] The chopping switches 10 and 11, which are symbolically shown in Fig. 1, are equipped with four unit switches SW as shown in Fig. 2. The switches are made up of switches SW(+) and SW(-) connected in series to the inverting side and non-inverting side, respectively, and two switches SW(+) and SW(-) connected in a cross-connect state between the inverting side and non-inverting side. Each switch is made up of, for example, an N-channel MOSFET.

[0011] The output terminal of the operational amplifier 6 is connected to the input terminal of an operational amplifier 15 constituting the first integrator 3 via a third amplifier chopping switch 13 and a capacitor 14. A switch 16 and a series circuit of a switch 17, a chopping switch 18, a capacitor 19, and a chopping switch 20 are connected in parallel between the input terminal and the output terminal of the operational amplifier 15. The first integrator 3 is of a correlated double sampling type.

[0012] The output terminal of the operational amplifier 15 is connected to the input terminal of the operational amplifier 24 constituting the second integrator 4 via a switch 21, a capacitor 22, and a switch 23. A common connection point of the switch 21 and the capacitor 22 and a common connection point of the capacitor 22 and the switch 23 are connected to the ground. The input terminal of the operational amplifier 24 is connected to the ground via a switch 25. A series circuit of a chopping switch 26, a capacitor 27, and a chopping switch 28 is connected between the input terminal and the output terminal of the operational amplifier 24. The common connection point of the capacitor 27 and the chopping switch 28 is connected to the ground.

[0013] The output terminal of the operational amplifier 24 is connected to the input terminal of the quantizer 5. A chopping switch 29 for the quantizer is connected to the output terminal of the quantizer 5. An output terminal of a D / A converter 30 that feeds back the output of the quantizer 5 is connected to the input terminal of the operational amplifier 15 via a capacitor 31. The D / A converter 30 is simply indicated by a symbol of a triple switch. Moreover, an output terminal of a D / A converter 32 that similarly feeds back the output of the quantizer 5 is connected to a common connection point of the capacitor 22 and the switch 23 via a capacitor 33.

[0014] Next, the operation of this embodiment will be described. Note that Fig. 1 and Fig. 3 only show the timing of the chopping operation related to the main part of this embodiment. In the capacitively coupled amplifier 2, if the operating frequency of the second amplifier chopping switch 11 is Fs, the operating frequency of the second and third amplifier chopping switches 10 and 13 is Fs / 512. However, the phases of the two differ by 90 degrees, and for example, if the phase of the former is sinωt, the phase of the latter is cosωt. The operating frequencies of chopping switches 18 and 20 in the first integrator 3, chopping switches 26 and 28 in the second integrator 4, and quantizer chopping switch 29 on the output side of the quantizer 5 are all Fs / 256(sinωt).

[0015] As described above, according to this embodiment, the delta-sigma modulator 1 includes the capacitively coupled amplifier 2, the first and second integrators 3 and 4, and the quantizer 5. The quantizer chopping switch 29 is connected to the output side of the quantizer 5, and the first and third amplifier chopping switches 10 and 13 are connected to the input and output sides of the capacitively coupled amplifier 2. A signal modulated by the chopping operation of the amplifier chopping switches 10 and 13 is demodulated by the chopping operation of the quantizer chopping switch 29. The chopping operation of the amplifier chopping switch is performed at a frequency that is half the operating frequency of the quantizer chopping switches 10 and 13, and at timings that are 90 degrees out of phase with each other.

[0016] Even in a configuration in which a resistive element is connected in front of the first amplifier chopping switch 10, the amount of charge absorbed by the switched capacitor operation can be reduced by setting the frequency of the chopping operation performed on the input side of the capacitively coupled amplifier 2 to half that of the chopping performed on the output side of the quantizer 5. In addition, by setting the phases of the chopping by the two amplifier chopping switches 10 and 13 to be 90 degrees different from each other, the offset caused by the switching of chopping can also be reduced.

[0017] Second embodiment Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals and their explanations are omitted, and only the different parts are explained. As shown in Fig. 4, the delta-sigma modulator 31 of the second embodiment has a configuration in which the third amplifier chopping switch 13 is removed from the delta-sigma modulator 1. The first amplifier chopping switch 10 is chopped by a signal obtained by exclusive-ORing a chopping signal with a frequency Fs and a chopping signal with a frequency Fs / 256(cosωt). This makes it possible to further reduce the circuit scale.

[0018] Third embodiment 5, the delta-sigma modulator 32 of the third embodiment is obtained by inserting a fourth amplifier chopping switch 33 between the output terminal of the operational amplifier 6 constituting the capacitively coupled amplifier 2 and the third amplifier chopping switch 13 in the delta-sigma modulator 1. The second amplifier chopping switch 11 is caused to perform chopping operation at a frequency Fs / 2(sinωt), and the fourth amplifier chopping switch 33 is caused to perform chopping operation at a frequency Fs / 2(cosωt). This reduces the operating frequency of the capacitively coupled amplifier 2 to 1 / 2, thereby further reducing errors.

[0019] (Fourth embodiment) As shown in FIG. 6, the delta-sigma modulator 34 of the fourth embodiment has a configuration in which the capacitive coupling amplifier 2 is omitted from the delta-sigma modulator 31 of the second embodiment.

[0020] Fifth embodiment 7, the delta-sigma modulator 35 of the fifth embodiment has a configuration in which fifth to seventh amplifier chopping switches 36 to 38 are added to the stage preceding the first amplifier chopping switch 11 in the delta-sigma modulator 31 of the second embodiment. The first amplifier chopping switch 11 performs chopping operation using a signal obtained by exclusive-ORing a chopping signal with a frequency Fs and a chopping signal with a frequency Fs / 1024(sinωt).

[0021] The operating frequencies of the fifth to seventh amplifier chopping switches 36 to 38 are all Fs / 1024, but as shown in FIG. 8, the following phase differences are applied. 1st amplifier chopping switch 11: Fs / 1024(sinωt) 5th amplifier chopping switch 35: Fs / 1024(sinωt+π / 4) 6th amplifier chopping switch 36: Fs / 1024(sinωt+π / 2) 7th amplifier chopping switch 37: Fs / 1024(sinωt+3π / 4)

[0022] That is, chopping is performed by applying a phase difference of 90 degrees to four chopping switches 11 and 35 to 37 on the input side of the capacitive coupling amplifier 2. This allows chopping to be performed at a lower frequency, Fs / 1024, which is 1 / 4 of the frequency Fs / 256.

[0023] (Other embodiments) In the fourth embodiment, the number of chopping switches arranged on the input side of the capacitively coupled amplifier 2 may be two, three, five or more. Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0024] In the drawing, reference numeral 1 denotes a delta-sigma modulator, 2 denotes a capacitively coupled amplifier, 3 denotes a first integrator, 4 denotes a second integrator, 5 denotes a quantizer, 10 denotes a switch for chopping the first amplifier, 11 denotes a switch for chopping the second amplifier, 13 denotes a switch for chopping the third amplifier, and 29 denotes a switch for chopping the quantizer.

Claims

1. A capacitively coupled amplifier (2); A correlated double sampling integrator (3) connected to the output side of the capacitive coupling amplifier; A quantizer (5) connected to the output side of the integrator; a quantizer chopping switch (29) connected to the output side of the quantizer; At least two amplifier chopping switches (10, 11, 12, 36 to 38) connected to the input side or the input side and the output side of the capacitive coupling amplifier; demodulating the signal modulated by the chopping operation of the amplifier chopping switch by the chopping operation of the quantizer chopping switch; A delta-sigma modulator in which the chopping operation of the amplifier chopping switch is performed at a frequency that is half the operating frequency of the quantizer chopping switch and at timings that are out of phase with each other by 90 degrees.

2. 2. The delta-sigma modulator according to claim 1, wherein the amplifier chopping switches (10, 13) are disposed on the input side and the output side of the capacitively coupled amplifier, respectively.

3. 2. The delta-sigma modulator according to claim 1, wherein the amplifier chopping switches (10, 11) are both arranged on the input side of the capacitively coupled amplifier, and one of them is chopped by a signal that is a logical combination of a signal that operates the capacitively coupled amplifier and a signal for the chopping operation.

4. an input side operation switch and an output side operation switch are disposed between the amplifier chopping switch and an input terminal and an output terminal of the capacitive coupling amplifier, respectively; 3. The delta-sigma modulator according to claim 2, wherein the input side operation switch and the output side operation switch each operate at a frequency of Fs / 2, where Fs is a fundamental operating frequency, and at timings that are out of phase with each other by 90 degrees.

5. An input capacitance (12); A correlated double sampling integrator (3) connected to the input capacitance; A quantizer (5) connected to the output side of the integrator; a quantizer chopping switch (29) connected to the output side of the quantizer; At least two amplifier chopping switches (10, 11) arranged on the input side of the input capacitance, demodulating the signal modulated by the chopping operation of the amplifier chopping switch by the chopping operation of the quantizer chopping switch; A delta-sigma modulator in which the chopping operation of the amplifier chopping switch is performed at a frequency that is half the operating frequency of the quantizer chopping switch and at timings that are out of phase with each other by 90 degrees.

6. The amplifier chopping switch (11, 36 to 38) is provided in a number of three or more, two or more of the amplifier chopping switches are chopped at a frequency lower than half the operating frequency and at different phases; 6. The delta-sigma modulator according to claim 1, wherein a signal modulated by the chopping operation of said amplifier chopping switch is demodulated by the chopping operation of said quantizer chopping switch.

7. 7. The delta-sigma modulator according to claim 6, wherein one of the amplifier chopping switches (11) is chopped by a signal obtained by logically combining a signal for operating the capacitively coupled amplifier and a signal for the chopping operation.

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