Semiconductor device, manufacturing method of semiconductor device, and power converter

Abstract

To provide a technique capable of preventing solder or a wire from peeling off from an electrode layer.SOLUTION: A semiconductor device includes: a top surface structure including multiple trench-type gate electrodes; an interlayer insulating film provided on each gate electrode, and having a gap above the adjacent gate electrodes; a first electrode layer covering the top structure and the interlayer insulating film; a second electrode layer covering the first electrode layer; and a third electrode layer covering the second electrode layer. Holes corresponding to the gaps in the interlayer insulating film are provided from a top surface of the third electrode layer to the second electrode layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, a method for manufacturing a semiconductor device, and a power conversion device. [Background technology]

[0002] A laminated structure of a nickel (Ni) layer several μm thick and a gold (Au) layer for suppressing oxidation of the Ni layer has been proposed as an electrode for a semiconductor device mounted on a semiconductor module such as an inverter. As a film formation process for the Ni layer and the Au layer, a plating process that allows mass processing and has an excellent film formation speed has attracted attention (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2007-5368 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor module equipped with a semiconductor device, an electrode layer, which is a plating film of the semiconductor device, is bonded to solder or wire. However, when a temperature change occurs during a power cycle test, stress is generated at the bonded portion between them due to the difference in linear expansion coefficient, which may cause the solder or wire to peel off from the electrode layer.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a technique capable of suppressing peeling of the solder or wire from the electrode layer. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises a semiconductor layer having a conductivity type, a top surface structure provided on an upper surface of the semiconductor layer and including a plurality of trench-type gate electrodes, an interlayer insulating film provided on each of the gate electrodes and having a gap between adjacent gate electrodes, a first electrode layer covering the top surface structure and the interlayer insulating film, a second electrode layer covering the first electrode layer, and a third electrode layer covering the second electrode layer, and a hole corresponding to the gap in the interlayer insulating film is provided from the upper surface of the third electrode layer to the second electrode layer. Effect of the Invention

[0007] According to the present disclosure, holes corresponding to the gaps in the interlayer insulating film are provided from the top surface of the third electrode layer to the second electrode layer. With this configuration, it is possible to prevent the solder or wire from peeling off from the electrode layer. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. [Diagram 2] 4 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Diagram 3] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 4] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Diagram 5] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 6] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 7] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 8] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 10] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 11] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 12] 4 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 14] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 15] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 16] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 17] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 18] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 19] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 20] FIG. 11 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. [Figure 21] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 22] FIG. 11 is a block diagram illustrating a schematic configuration of a power conversion system according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The features described in each of the following embodiments are merely examples, and not all features are necessarily required. In addition, in the following description, similar components in multiple embodiments are given the same or similar reference numerals, and different components are mainly described. In addition, in the following description, specific positions and directions such as "upper", "lower", "left", "right", "front" or "back" do not necessarily correspond to positions and directions in actual implementation.

[0010] <Embodiment 1> Fig. 1 is a cross-sectional view showing the configuration of a semiconductor device according to the first embodiment. Specifically, Fig. 1 shows the cross-sectional configuration of a SiC-MOSFET with a trench gate structure as an example of a semiconductor device, and in particular shows the cross-sectional configuration of a main cell portion. A semiconductor device having a trench gate structure is expected to reduce loss during current flow in the semiconductor device compared to a semiconductor device having a planar gate structure.

[0011] The semiconductor device according to the first embodiment is not limited to a MOSFET, but may be any of an IGBT, an RC-IGBT (Reverse Conducting - IGBT), an SBD (Schottky Barrier Diode), and a PND (PN junction diode), as long as it has a trench gate structure. The semiconductor device according to the first embodiment may be made of, for example, silicon (Si), or may be made of a wide band gap material other than SiC, such as gallium nitride (GaN) or diamond. A semiconductor device made of a wide band gap semiconductor such as SiC is advantageous for high voltage resistance, low loss, and use in high temperature environments.

[0012] The semiconductor device in FIG. 1 includes a SiC substrate 1, a drift layer 2, a bottom base region 3, a gate insulating film 4, a base region 5, a source region 6, a gate electrode 7, an interlayer insulating film 8, a source electrode 9, and a drain electrode 13.

[0013] The SiC substrate 1, the drift layer 2, and the bottom base region 3 are included in the concept of a semiconductor layer. The semiconductor layer is not limited to the above configuration as long as it has a conductivity type. For example, the semiconductor layer may not include the bottom base region 3, or may include at least one of the SiC substrate 1 and the drift layer 2. Here, in this specification, for example, at least one of A, B, C, ..., and Z means any one of all combinations of one or more selected from the group of A, B, C, ..., and Z.

[0014] The gate insulating film 4, the base region 5, the source region 6, and the gate electrode 7 are included in the concept of the upper surface structure. The upper surface structure is not limited to the above configuration as long as it is provided on the upper surface of the semiconductor layer and includes a plurality of trench-type gate electrodes 7. Here, the upper surface means the upper side of the paper and is also called the front surface.

[0015] The interlayer insulating film 8 is also called an interlayer insulating layer and is provided on each gate electrode 7. The interlayer insulating film 8 has a gap between adjacent gate electrodes 7. There may be a plurality of interlayer insulating films 8, or there may be one interlayer insulating film connected at a portion other than the cross-sectional portion of FIG. 1. In the following, a configuration in which the upper and side portions of the interlayer insulating film 8 are rounded will be described, but this is not essential.

[0016] The source electrode 9 has a laminated structure, and includes a first source electrode 10 which is a first electrode layer, a second source electrode 11 which is a second electrode layer, and a third source electrode 12 which is a third electrode layer.

[0017] The first source electrode 10 covers the upper surface structure and the interlayer insulating film 8, and the upper surface of the first source electrode 10 is provided with a protrusion 10a corresponding to a portion where the interlayer insulating film 8 exists, and a recess 10b corresponding to a gap in the interlayer insulating film 8. In the first embodiment, the first source electrode 10 contains aluminum and silicon.

[0018] A second source electrode 11, which is a second electrode layer, covers the first source electrode 10. In the present embodiment 1, the second source electrode 11 contains nickel (Ni). A third source electrode 12, which is a third electrode layer, covers the second source electrode 11. In the present embodiment 1, the third source electrode 12 contains gold (Au). Here, a recess 14, which is a hole, is provided from the upper surface of the third source electrode 12 to the second source electrode 11.

[0019] The drain electrode 13 is provided on the lower surface of the SiC substrate 1. Here, the lower surface means the lower side of the paper, and is also called the back surface.

[0020] <Manufacturing method> FIG. 2 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment.

[0021] First, in step S1, as shown in FIG. 3, drift layer 2 made of n-type SiC is formed on the upper surface of SiC substrate 1 by epitaxial growth.

[0022] 4, in step S2, a p-type base region 5 is formed in the upper part of the drift layer 2. For example, after a mask such as a resist (not shown) is formed on the drift layer 2, p-type ion implantation is performed on the drift layer 2 to selectively form the p-type base region 5. Generally, boron (B) or aluminum (Al) is used as the impurity implanted by the p-type ion implantation.

[0023] In step S3, as shown in Fig. 5, an n-type source region 6 is formed on the upper part of the base region 5. For example, after forming a mask such as a resist (not shown) on the base region 5, n-type ion implantation is performed on the base region 5 to selectively form the n-type source region 6. Generally, phosphorus (P) or nitrogen (N) is used as the impurity implanted in the n-type ion implantation. Thereafter, in order to electrically activate the implanted impurity, the drift layer 2 and the like are heat-treated at a high temperature using a heat treatment device (not shown).

[0024] In step S4, as shown in Fig. 6, a plurality of trenches are formed from the source region 6 to the drift layer 2. For example, a mask such as a resist (not shown) is formed on the base region 5 and the source region 6, and then plasma etching or the like is performed to form the trenches. Thereafter, in order to relax the electric field at the bottom of the trench, a p-type bottom base region 3 is formed as shown in Fig. 7. However, the formation of the bottom base region 3 is not essential.

[0025] In step S5, as shown in Fig. 8, a plurality of gate insulating films 4 are formed on the inner surfaces of the plurality of trenches. For example, plasma damage caused when forming the trench gates is removed by oxidizing the trenches using a thermal oxidation method. Thereafter, the gate insulating film 4 is formed using a deposition method such as thermal oxidation or chemical vapor deposition.

[0026] In step S6, a plurality of gate electrodes 7 are formed on the inner surfaces of the plurality of gate insulating films 4. For example, as shown in Fig. 9, a conductive layer that becomes the gate electrodes 7 is formed on the gate insulating film 4 and the base region 5, and then, as shown in Fig. 10, an excess conductive layer formed on the base region 5 and the like is removed by etching to form the plurality of gate electrodes 7.

[0027] 11, in step S7, an interlayer insulating film 8 is formed on each gate electrode 7. For example, an insulating layer is formed by chemical vapor deposition (CVD) and then patterned by photolithography and etching to form the interlayer insulating film 8. In the first embodiment, an additive such as B or P is added to the insulating layer that becomes the interlayer insulating film 8, and a heat treatment is performed to provide a roundness between the top and sides of the interlayer insulating film 8.

[0028] In step S8, electrodes are formed, that is, the first source electrode 10, the second source electrode 11, the third source electrode 12, and the drain electrode 13. Details of this step S8 will be described next. Through the above steps S1 to S8, the semiconductor device of FIG. 1 is completed.

[0029] FIG. 12 is a flow chart showing step S8 in FIG. 2, that is, the electrode forming step.

[0030] In step S11, for example, a sputtering device is used as a film forming device to form a front surface AlSi electrode on the base region 5, the source region 6, and the interlayer insulating film 8. Here, the front surface AlSi electrode corresponds to the first source electrode 10 shown in FIG.

[0031] In step S12, the SiC substrate 1 is thinned. For example, machining using a grinding wheel is performed on the back surface of the SiC substrate 1 to thin the SiC substrate 1. Note that thinning of the SiC substrate 1 is not essential and may be performed as necessary.

[0032] In step S13, a back electrode is formed on the back surface of the SiC substrate 1 using, for example, a sputtering device in the same manner as in the formation of the first source electrode 10. For example, a titanium (Ti) film is sputtered on the back surface of the SiC substrate 1, and TiSi / Ti is formed by laser annealing. In addition, a Ni film and an Au film are sputtered on the Ti film in this order using a sputtering device, to form a back electrode made of Ti / Ni / Au. Here, the back electrode corresponds to the drain electrode 13 shown in FIG. 14.

[0033] In step S14, a pre-plating process is performed. For example, a protective tape is attached to the back surface of the SiC substrate 1 on which the electrodes have already been completed in order to protect the back surface. After that, a degreasing process is performed to remove oil and organic residues adhering to the first source electrode 10. Next, the oxide film is removed by etching the upper part of the first source electrode 10 by aluminum etching. Then, residues generated by the aluminum etching are removed by acid washing to promote the reaction in the next process.

[0034] In step S15, a first zincate treatment is performed. The oxide film formed on the first source electrode 10 after the aluminum etching is removed by the first zincate treatment, while a Zn film is formed on the first source electrode 10 by a substitution reaction between Al and zinc (Zn).

[0035] In step S16, the Zn film formed on the first source electrode 10 is peeled off. For example, the Zn film is peeled off using nitric acid. As a result, a uniform oxide film is formed on the first source electrode 10.

[0036] In step S17, a second zincate treatment is performed. The second zincate treatment removes the oxide film on the first source electrode 10, while forming a Zn film on the first source electrode 10 through a substitution reaction between Al and Zn. The Zn film formed here is denser and more uniform than the Zn film formed in the first zincate treatment, and promotes the formation of a Ni plating layer with high adhesion to the first source electrode 10 in the next step.

[0037] In step S18, a Ni plating layer corresponding to the second source electrode 11 shown in FIG. 15 is formed by performing Ni plating. In the present embodiment 1, an electroless Ni plating is used for the Ni plating. In the electroless Ni plating, first, a Ni plating film is formed by replacing the Zn film formed in the previous step S17 with Ni. Then, the second source electrode 11 is formed on the Ni plating film by the action of a reducing agent contained in the electroless Ni plating solution, using the formed Ni plating film as a catalyst. Since hypophosphorous acid is generally used as a reducing agent, P is precipitated as a side reaction of the electroless Ni plating, and the second source electrode 11 becomes a NiP alloy layer in which P is co-deposited. The second source electrode 11 has a thickness of, for example, about 3 μm.

[0038] 16, the upper surface of the second source electrode 11 has a shape corresponding to the uneven shape of the upper surface of the first source electrode 10. Between the recess 10b of the first source electrode 10 and the recess of the second source electrode 11, a sparse region 15 that is easily etched and is not crystallized is formed. In the present embodiment 1, since a roundness is provided between the top and side of the interlayer insulating film 8 in step S7, the sparseness of the sparse region 15 can be increased, and therefore the sparse region 15 becomes even more easily etched.

[0039] In step S19, an Au plating process is performed to form an Au plating layer corresponding to the third source electrode 12 shown in Fig. 17. In the present embodiment 1, an electroless Au plating process is used for the Au plating process. The third source electrode 12 is formed by displacement Au plating, which utilizes the phenomenon that Ni is oxidized due to the potential difference between Ni and Au, releasing electrons, and Au ions react with the electrons to precipitate Au.

[0040] Here, since sparse regions 15 that are easily etched are formed in second source electrode 11, in step S19, sparse regions 15 are selectively etched by electroless Au plating. As a result, as shown in Fig. 17, a recess deeper than the recess of second source electrode 11 in step S17 is formed from the upper surface of third source electrode 12 to second source electrode 11, and recess 14 is formed from the upper surface of third source electrode 12 to second source electrode 11. The depth from the high part of third source electrode 12 to the low part of recess 14 is, for example, about 500 nm.

[0041] The inner surface of the recess 14 is preferably covered with the third source electrode 12. In this configuration, the exposed Ni portion of the second source electrode 11 is covered with Au, so that oxidation of Ni can be suppressed and adhesion can be improved in the bonding between the source electrode 9 and the solder described later. After the Au plating process, the adhesive force of the protective tape on the back surface is reduced by UV irradiation, and the protective tape is peeled off from the back surface of the SiC substrate 1. Through the above steps, step S8 in FIG. 2 is completed, and the semiconductor device shown in FIG. 1 is manufactured.

[0042] 18 and 19 are side views showing a semiconductor module including the semiconductor device manufactured as described above. In Fig. 18 and Fig. 19, the semiconductor device of Fig. 1 is illustrated as semiconductor device 21.

[0043] The source electrode 9 and the drain electrode 13 of the semiconductor device 21 are respectively joined to a lead frame 23 or the like using solder 22 and wire 24 in Fig. 18, or solder 22 in Fig. 19. Thereafter, the semiconductor device 21 and its peripheral parts are sealed with resin to form a semiconductor module.

[0044] <Summary of the first embodiment> Generally, a power cycle test is used to evaluate the bonding reliability of a semiconductor module. The power cycle test evaluates the reliability by repeatedly heating and cooling the semiconductor device through electrical current, generating stress due to differences in the linear expansion coefficients of the components. The stress generated during this test may cause the solder 22 or wire 24 to peel off from the source electrode 9.

[0045] In contrast, in the semiconductor device according to the first embodiment, a corresponding recess 14 is provided between the interlayer insulating film 8 from the upper surface of the third source electrode 12 to the second source electrode 11. According to this configuration, when the source electrode 9 and the solder 22 or the wire 24 are joined, a part of the solder 22 or the wire 24 enters the recess 14 of the source electrode 9, thereby increasing the joining area and generating an anchor effect. This improves the joining property, so that peeling of the solder 22 or the wire 24 from the source electrode 9 due to a power cycle test or the like can be suppressed. Furthermore, according to the first embodiment, the recess 14 can be formed without performing a process for forming the recess 14, such as etching the second source electrode 11 and the third source electrode 12.

[0046] Furthermore, according to the first embodiment, a roundness is provided between the top and sides of the interlayer insulating film 8. With such a configuration, the sparse region 15 is easily etched, and the depth of the recess 14 can be increased. This can further improve the bondability, and can further suppress peeling of the solder 22 or the wire 24 from the source electrode 9 due to a power cycle test or the like.

[0047] <Embodiment 2> 20 is a cross-sectional view showing the configuration of a semiconductor device according to the second embodiment, and corresponds to FIG. 1. In the second embodiment, a groove 26 which is a hole is provided from the upper surface of the third source electrode 12 to the second source electrode 11. The groove 26 penetrates the second source electrode 11 and the third source electrode 12, and the bottom of the groove 26 reaches the first source electrode 10.

[0048] <Manufacturing method> FIG. 21 is a flowchart showing a method for manufacturing a semiconductor device according to the second embodiment.

[0049] Steps S21, S22, S23, S24, S25, S26, S27, and S28 in Fig. 21 are similar to steps S1, S2, S3, S4, S5, S6, S7, and S8 in Fig. 2 described in embodiment 1. For this reason, the following description will mainly focus on step S29.

[0050] Heat treatment is performed in step S29. For example, by performing heat treatment on the semiconductor device using a heat treatment facility such as a heating furnace, grooves 26 are formed in second source electrode 11 and third source electrode 12, starting from recesses 14 and reaching the upper surface of first source electrode 10. Analysis has confirmed that heating at 290° C. or higher for 5 minutes or more results in the formation of grooves 26 that do not extend into first source electrode 10. Through the above steps, the semiconductor device shown in FIG. 20 is manufactured.

[0051] <Summary of the second embodiment> According to the semiconductor device of the second embodiment as described above, a groove 26 is provided that extends from the upper surface of the third source electrode 12 to the second source electrode 11 and has a bottom that reaches the first source electrode 10. According to such a configuration, it is possible to increase the bonding area and enhance the anchor effect more than in the semiconductor device of the first embodiment, and it is possible to further suppress peeling of the solder 22 or the wire 24 from the source electrode 9 due to a power cycle test or the like.

[0052] <Embodiment 3> In the present embodiment 3, the semiconductor device according to the above-mentioned embodiment 1 or 2 is applied to a power conversion device. Although the power conversion device according to the present embodiment 3 is not limited to a specific power conversion device, the following describes a case where the power conversion device according to the present embodiment 3 is applied to a three-phase inverter.

[0053] 22 is a block diagram showing a schematic configuration of a power conversion system to which a power conversion device 200 according to the third embodiment is applied. The power conversion system includes a power source 100, the power conversion device 200, and a load 300.

[0054] The power supply 100 is a DC power supply, and supplies DC power to the power conversion device 200. The power supply 100 can be configured with various power supplies, and may be configured with, for example, a DC system, a solar cell, or a storage battery, or may be configured with a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 100 may also be configured with a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0055] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300. The power conversion device 200 converts DC power supplied from the power source 100 into AC power and supplies it to the load 300. The power conversion device 200 includes a main conversion circuit 201 and a control circuit 203. The main conversion circuit 201 converts input DC power into AC power and outputs the AC power. The control circuit 203 outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201.

[0056] The load 300 is a three-phase motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is a motor mounted on various electric devices, and is used as, for example, a motor for a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioner.

[0057] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and free wheel diodes (not shown). The switching elements switch the main conversion circuit 201 to convert the DC power supplied from the power source 100 into AC power, and supply the AC power to the load 300. There are various specific circuit configurations of the main conversion circuit 201, but the main conversion circuit 201 according to the third embodiment is a two-level three-phase full bridge circuit that can be configured with six switching elements and six free wheel diodes connected in inverse parallel to each switching element. The semiconductor device 21 according to any of the first embodiment, the second embodiment, and the modified examples thereof is applied as at least one of the switching elements and the free wheel diodes of the main conversion circuit 201. The six switching elements are connected in series with two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0058] The main conversion circuit 201 includes a drive circuit 202 that drives each switching element. The drive circuit 202 generates drive signals that drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, the drive circuit 202 outputs, to the control electrodes of each switching element, a drive signal that turns the switching element on and a drive signal that turns the switching element off, in accordance with a control signal from a control circuit 203 (described later). When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) lower than the threshold voltage of the switching element.

[0059] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that a desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) during which each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the control circuit 203 can control the main conversion circuit 201 by pulse width modulation (PWM) control that modulates the on time of the switching elements according to the voltage to be output. Then, the control circuit 203 outputs a control command (control signal) to the drive circuit 202 so that at each point in time, an on signal is output to the switching element that should be in the on state and an off signal is output to the switching element that should be in the off state. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.

[0060] The manufacturing method of the power conversion device 200 includes the following steps. The semiconductor device 21 is manufactured by the manufacturing method described in the above-mentioned embodiment 1, embodiment 2 or their modified examples. A main conversion circuit 201 having this semiconductor device 21 is formed. Also, a control circuit 203 is formed. In this way, the power conversion device 200 is obtained. When the main conversion circuit 201 is formed, a back electrode layer of the semiconductor device 21 is bonded onto a mounting substrate.

[0061] According to the third embodiment, by using the semiconductor device according to the first or second embodiment as the switching element constituting the main conversion circuit 201, peeling due to stress during current flow can be suppressed, thereby improving the reliability of the main conversion circuit 201. As a result, the reliability of the power conversion device 200 can be improved.

[0062] In the third embodiment, the semiconductor device 21 is applied to a two-level three-phase inverter, but the present invention is not limited to this and can be applied to various power conversion devices. In the third embodiment, the power conversion device is a two-level power conversion device, but it may be a multi-level power conversion device such as a three-level power conversion device. When power is supplied to a single-phase load, the semiconductor device 21 may be applied to a single-phase inverter. When power is supplied to a DC load or the like, the semiconductor device 21 can also be applied to a DC / DC converter or an AC / DC converter.

[0063] Furthermore, the power conversion device to which the semiconductor device 21 is applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for any of an electric discharge machine, a laser processing machine, an induction heating cooker, and a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system, etc.

[0064] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0065] Various aspects of the present disclosure are summarized below as appendices.

[0066] (Appendix 1) A semiconductor layer having a conductivity type; an upper surface structure including a plurality of trench-type gate electrodes provided on an upper surface of the semiconductor layer; an interlayer insulating film provided on each of the gate electrodes and having a gap between adjacent gate electrodes; a first electrode layer covering the upper surface structure and the interlayer insulating film; A second electrode layer covering the first electrode layer; a third electrode layer covering the second electrode layer; Equipped with a hole corresponding to the gap in the interlayer insulating film is provided from an upper surface of the third electrode layer to the second electrode layer.

[0067] (Appendix 2) 2. The semiconductor device according to claim 1, A semiconductor device, wherein the bottom of the hole reaches the first electrode layer.

[0068] (Appendix 3) The semiconductor device according to claim 1 or 2, a rounded portion is provided between the top and sides of the interlayer insulating film.

[0069] (Appendix 4) A semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 3, the first electrode layer comprises aluminum and silicon; the second electrode layer comprises nickel; The semiconductor device, wherein the third electrode layer comprises gold.

[0070] (Appendix 5) A method for manufacturing the semiconductor device according to claim 2, comprising the steps of: The hole is formed by a heat treatment.

[0071] (Appendix 6) A method for manufacturing a semiconductor device according to any one of claims 1 to 5, comprising the steps of: The method for manufacturing a semiconductor device, wherein the second electrode layer and the third electrode layer are formed by an electroless plating process.

[0072] (Appendix 7) A conversion circuit having the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 6, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; a control circuit that outputs a control signal to the drive circuit; A power conversion device comprising: [Explanation of symbols]

[0073] REFERENCE SIGNS LIST 1 SiC substrate, 2 drift layer, 3 bottom base region, 4 gate insulating film, 5 base region, 6 source region, 7 gate electrode, 8 interlayer insulating film, 10 first source electrode, 11 second source electrode, 12 third source electrode, 14 recess, 21 semiconductor device, 26 groove portion, 200 power conversion device, 201 main conversion circuit, 202 drive circuit, 203 control circuit.

Claims

1. A semiconductor layer having a conductivity type; an upper surface structure including a plurality of trench-type gate electrodes provided on an upper surface of the semiconductor layer; an interlayer insulating film provided on each of the gate electrodes and having a gap between adjacent gate electrodes; a first electrode layer covering the upper surface structure and the interlayer insulating film; A second electrode layer covering the first electrode layer; a third electrode layer covering the second electrode layer; Equipped with a hole corresponding to the gap in the interlayer insulating film is provided from an upper surface of the third electrode layer to the second electrode layer.

2. 2. The semiconductor device according to claim 1, A semiconductor device, wherein a bottom of the hole reaches the first electrode layer.

3. 3. The semiconductor device according to claim 1, a rounded portion is provided between the top and sides of the interlayer insulating film.

4. 3. The semiconductor device according to claim 1, the first electrode layer comprises aluminum and silicon; the second electrode layer comprises nickel; The third electrode layer comprises gold.

5. 3. The method for manufacturing a semiconductor device according to claim 2, The hole is formed by a heat treatment.

6. 2. The method of manufacturing a semiconductor device according to claim 1, The second electrode layer and the third electrode layer are formed by electroless plating.

7. A conversion circuit having the semiconductor device according to claim 1, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; a control circuit that outputs a control signal to the drive circuit; A power conversion device comprising:

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