Semiconductor device and manufacturing method thereof

Abstract

To improve the performance of a semiconductor device.SOLUTION: A semiconductor substrate SUB comprises a p-type substrate body SB, an n-type buried layer NBL on the p-type substrate body SB, and a p-type semiconductor layer EP on the n-type buried layer NBL. A DTI region 5 penetrates the p-type semiconductor layer EP and the n-type buried layer NBL and reaches the p-type substrate body SB. An n-type semiconductor region CD, which is a cathode region of a Zener diode, and a p-type anode region of the Zener diode are formed in the semiconductor layer EP. A P-type anode region includes a p-type semiconductor region AD1 formed under the n-type semiconductor region CD, and a p-type semiconductor region AD2 formed under the p-type semiconductor region AD1. A PN junction is formed between the p-type semiconductor region AD1 and the n-type semiconductor region CD. Impurity concentration of the p-type semiconductor region AD2 is higher than impurity concentration of the p-type semiconductor region AD1.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and can be suitably used, for example, in a semiconductor device including a Zener diode and a manufacturing method thereof. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2013-183039 (Patent Document 1) describes a semiconductor device including a Zener diode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-183039 A Summary of the Invention [Problem to be solved by the invention]

[0004] It is also desirable to improve the performance of semiconductor devices equipped with Zener diodes.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor device includes a semiconductor substrate and an isolation region. The semiconductor substrate includes a substrate region of a first conductivity type, a first semiconductor layer of a second conductivity type formed on the substrate region, and a second semiconductor layer of the first conductivity type formed on the first semiconductor layer. The isolation region penetrates the second semiconductor layer and the first semiconductor layer to reach the substrate region. A cathode region of a second conductivity type and an anode region of a first conductivity type of a Zener diode are formed in the second semiconductor layer. The anode region includes a first semiconductor region of the first conductivity type formed under the cathode region and a second semiconductor region of the first conductivity type formed under the first semiconductor region. A PN junction is formed between the first semiconductor region and the cathode region. An impurity concentration of the second semiconductor region is higher than an impurity concentration of the first semiconductor region. Effect of the Invention

[0007] According to one embodiment, the performance of a semiconductor device can be improved. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment. [Diagram 2] 2 is a cross-sectional view of a main part of the semiconductor device in the manufacturing process of the first embodiment. FIG. [Diagram 3] 3 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 2; [Figure 4] 4 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 3. [Diagram 5] 5 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 4. [Figure 6] 6 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 5. [Figure 7] 7 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 6. [Figure 8] 8 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 7. [Figure 9] 9 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 8. [Figure 10] 10 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. [Figure 11] 11 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 10. [Figure 12] 12 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 11. [Figure 13] 13 is a cross-sectional view of a main part of the semiconductor device during the manufacturing process continued from FIG. 12. [Figure 14] 1 is a cross-sectional view of a main part of a semiconductor device according to a first studied example. [Figure 15] FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to a second studied example. [Figure 16] FIG. 13 is a cross-sectional view of a main part of a semiconductor device according to a third studied example. [Figure 17] FIG. 1 is an explanatory diagram of a semiconductor device according to a first embodiment. [Figure 18] 13 is a graph showing the operating characteristics of the Zener diode of the first studied example. [Figure 19] 4 is a graph showing the operating characteristics of the Zener diode according to the first embodiment. [Figure 20] FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to a second embodiment. [Figure 21] FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to a third embodiment. [Figure 22] FIG. 11 is a cross-sectional view of a main part of a semiconductor device according to a fourth embodiment. [Diagram 23] 1A and 1B are explanatory diagrams showing examples of use of a semiconductor device; [Figure 24] 1A and 1B are explanatory diagrams showing examples of use of a semiconductor device; [Diagram 25] 1A and 1B are explanatory diagrams showing examples of use of a semiconductor device; [Figure 26] 1A and 1B are explanatory diagrams showing examples of use of a semiconductor device; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. In addition, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, except when specifically specified or when it is clearly limited to a specific number in principle, and it may be more than or less than the specific number. Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential, except when specifically specified or when it is clearly considered to be essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of the components, etc. are mentioned, it includes those that are substantially similar to or similar to the shape, etc., except when specifically specified or when it is clearly considered not to be essential in principle. This also applies to the above numerical values ​​and ranges.

[0010] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations will be omitted. In the following embodiments, the explanations of the same or similar parts will not be repeated as a rule unless it is particularly necessary.

[0011] In the drawings used in the embodiments, hatching may be omitted even in cross-sectional views in order to make the drawings easier to understand, and hatching may be added even in plan views in order to make the drawings easier to understand.

[0012] Moreover, a plan view corresponds to a view from a plane substantially parallel to the main surface or back surface of the semiconductor substrate SUB. Moreover, a bottom surface and a lower surface have the same meaning. Moreover, a height position corresponds to a distance from the back surface of the semiconductor substrate SUB. Moreover, a depth position corresponds to a distance from the main surface of the semiconductor substrate SUB.

[0013] In this application, MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or LDMOSFET (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) includes not only MOSFET using an oxide film as a gate insulating film, but also MOSFET using an insulating film other than an oxide film as a gate insulating film. LDMOSFET is also sometimes called HV-MOSFET (High Voltage Metal Oxide Semiconductor Field Effect Transistor) or DEMOSFET (Drain Extended Metal Oxide Semiconductor Field Effect Transistor).

[0014] (Embodiment 1) <About the structure of semiconductor device> The semiconductor device of the present embodiment will be described with reference to the drawings, in which: Fig. 1 is a cross-sectional view of a main part of the semiconductor device of the present embodiment;

[0015] As shown in FIG. 1, the semiconductor device of this embodiment has a semiconductor substrate SUB, an STI region 3, a DTI region 5, a p-type well PW1, a p-type semiconductor region AD1, a p-type semiconductor region AD2, a p-type semiconductor region PR, and an n-type semiconductor region CD.

[0016] As shown in FIG. 1, the semiconductor substrate SUB has a p-type substrate body SB, an n-type buried layer NBL formed on the upper portion of the p-type substrate body SB, and a p-type semiconductor layer EP formed on the n-type buried layer NBL.

[0017] The p-type substrate body SB is made of p-type single crystal silicon or the like doped with a p-type impurity such as boron (B). The n-type buried layer NBL is an n-type semiconductor layer. The n-type buried layer NBL is formed in a layer shape on the upper part of the p-type substrate body SB. The p-type substrate body SB below the n-type buried layer NBL is a p-type substrate region. The p-type semiconductor layer EP is made of p-type single crystal silicon or the like formed by epitaxial growth on the n-type buried layer NBL.

[0018] Here, the semiconductor substrate SUB has a Zener diode-forming region 1A and a transistor-forming region 1B. The Zener diode-forming region 1A includes a Zener diode. The transistor-forming region 1B includes a transistor element. The Zener diode-forming region 1A and the transistor-forming region 1B are disposed at different positions on the main surface of the semiconductor substrate SUB. FIG. 1 shows a cross-sectional view of the Zener diode-forming region 1A. FIGS. 2 to 13, which will be described later, show cross-sectional views of the Zener diode-forming region 1A and the transistor-forming region 1B.

[0019] The main surface of the semiconductor substrate SUB is synonymous with the main surface of the semiconductor layer EP. The back surface of the semiconductor substrate SUB is synonymous with the back surface of the p-type substrate body SB. The main surface and the back surface of the semiconductor substrate SUB are located on opposite sides to each other.

[0020] An STI (Shallow Trench Isolation) region 3 is formed on the main surface of the semiconductor substrate SUB. The STI region 3 is made of an insulating film such as a silicon oxide film embedded in a trench 2 formed in the semiconductor layer EP.

[0021] Further, a DTI (Deep Trench Isolation) region 5 is formed on the main surface of the semiconductor substrate SUB. The DTI region 5 is made of an insulating film IL on the semiconductor substrate SUB and an insulating film such as a silicon oxide film embedded in a trench 4 formed in the semiconductor substrate SUB. The DTI region 5 functions as an element isolation region.

[0022] The depth of the DTI region 5 is deeper than the depth of the STI region 3. That is, the height position of the bottom surface of the DTI region 5 is lower than the height position of the bottom surface of the STI region 3. The STI region 3 does not reach the n-type buried layer NBL. The DTI region 5 penetrates the semiconductor layer EP and the n-type buried layer NBL and reaches the p-type substrate body SB. The bottom surface of the DTI region 5 is located midway through the thickness of the p-type substrate body SB.

[0023] In this embodiment, the trench 4 and the DTI region 5 penetrate the insulating film IL, with a part of the DTI region 5 located in the trench 4 of the insulating film IL, and the other part of the DTI region 5 located in the trench 4 of the semiconductor substrate SUB. The trench 4 may be formed in the semiconductor substrate SUB without penetrating the insulating film IL. In that case, the DTI region 5 is embedded in the trench 4 of the semiconductor substrate SUB, and the height position of the upper surface of the DTI region 5 is approximately the same as the height position of the main surface of the semiconductor substrate SUB.

[0024] In plan view, the DTI region 5 is disposed so as to surround the Zener diode-forming region 1A. That is, in plan view, the semiconductor layer EP and the n-type buried layer NBL in the Zener diode-forming region 1A are surrounded by the DTI region 5. The DTI region 5 electrically isolates the semiconductor layer EP and the n-type buried layer NBL in the Zener diode-forming region 1A from the semiconductor layer EP and the n-type buried layer NBL located outside the Zener diode-forming region 1A.

[0025] The p-type well region PW1, the p-type semiconductor region AD1, the p-type semiconductor region AD2, the p-type semiconductor region PR, and the n-type semiconductor region CD are formed in the semiconductor substrate SUB. Specifically, in the Zener diode formation region 1A, the p-type well region PW1 is formed in the semiconductor layer EP. In the p-type well region PW1, the p-type semiconductor region AD1, the p-type semiconductor region AD2, the p-type semiconductor region PR, and the n-type semiconductor region CD are formed.

[0026] The p-type well region PW1 is formed in the upper part of the semiconductor layer EP. The p-type semiconductor layer EP interposed between the bottom surface of the p-type well region PW1 and the upper surface of the n-type buried layer NBL is the p-type semiconductor region EP1.

[0027] The n-type semiconductor region CD is formed in an upper portion of the p-type well region PW1. The n-type semiconductor region CD is in contact with the main surface of the semiconductor substrate SUB and is formed to a predetermined depth from the main surface of the semiconductor substrate SUB. The n-type semiconductor region CD functions as an n-type cathode region of the Zener diode.

[0028] The p-type semiconductor region AD1 is formed below the n-type semiconductor region CD. The p-type semiconductor region AD2 is formed below the p-type semiconductor region AD1. The p-type impurity concentration of the p-type semiconductor region AD2 is higher than the p-type impurity concentration of the p-type semiconductor region AD1. The p-type impurity concentration of the p-type semiconductor region AD1 is higher than the p-type impurity concentration of the p-type well region PW1. The p-type impurity concentration of the p-type well region PW1 is higher than the p-type impurity concentration of the p-type semiconductor layer EP below the p-type well region PW1. That is, the p-type impurity concentration of the p-type well region PW1 is higher than the p-type impurity concentration of the p-type semiconductor region EP1. The p-type semiconductor region AD1, the p-type semiconductor region AD2, and the p-type well PW1 are electrically connected to each other.

[0029] In the direction from the main surface toward the back surface of the semiconductor substrate SUB, the n-type semiconductor region CD and the p-type semiconductor region AD1 are adjacent to each other, and a PN junction is formed between the n-type semiconductor region CD and the p-type semiconductor region AD1.

[0030] The p-type semiconductor region AD1 and the p-type semiconductor region AD2 are adjacent to each other in the direction from the main surface to the back surface of the semiconductor substrate SUB. The planar dimensions (area) of the p-type semiconductor region AD1 and the planar dimensions of the p-type semiconductor region AD2 are approximately the same, but may be different. In a plan view, the p-type semiconductor region AD1 and the p-type semiconductor region AD2 overlap each other.

[0031] In addition, in a plan view, the n-type semiconductor region CD contains the p-type semiconductor region AD1, and the planar dimensions of the p-type semiconductor region AD1 are smaller than the planar dimensions of the n-type semiconductor region CD. Therefore, the center of the bottom surface of the n-type semiconductor region CD contacts the p-type semiconductor region AD1, and the outer periphery of the bottom surface of the n-type semiconductor region CD contacts the p-type well region PW1. In other words, the center of the bottom surface of the n-type semiconductor region CD is covered with the p-type semiconductor region AD1, and the outer periphery of the bottom surface of the n-type semiconductor region CD is covered with the p-type well region PW1. A PN junction is also formed between the n-type semiconductor region CD and the p-type well region PW1.

[0032] The depth of the bottom surface of the p-type semiconductor region AD2 is shallower than the depth of the bottom surface of the p-type well region PW1. The side surfaces of the p-type semiconductor region AD1, the side surfaces of the p-type semiconductor region AD2, and the bottom surface of the p-type semiconductor region AD2 are covered with the p-type well region PW1.

[0033] A p-type semiconductor region consisting of the p-type semiconductor region AD1, the p-type semiconductor region AD2, and the p-type well region PW1 functions as a p-type anode region of the Zener diode. A PN junction surface formed at the interface between the n-type cathode region and the p-type anode region is composed of a PN junction surface between the n-type semiconductor region CD and the p-type semiconductor region AD1, and a PN junction surface between the n-type semiconductor region CD and the p-type well region PW1. In a plan view, the PN junction surface between the n-type semiconductor region CD and the p-type semiconductor region AD1 is surrounded by the PN junction surface between the n-type semiconductor region CD and the p-type well region PW1.

[0034] Since the p-type impurity concentration of the p-type semiconductor region AD1 is higher than the p-type impurity concentration of the p-type well region PW1, breakdown of the Zener diode occurs at the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD1. Therefore, the breakdown voltage of the Zener diode is determined by the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD1.

[0035] The p-type semiconductor region PR is formed in an upper portion of the p-type well region PW1. The p-type semiconductor region PR is in contact with the main surface of the semiconductor substrate SUB, and is formed to a predetermined depth from the main surface of the semiconductor substrate SUB. In a plan view, the p-type semiconductor region PR is formed, for example, so as to surround the n-type semiconductor region CD. The p-type semiconductor region PR and the n-type semiconductor region CD are arranged so as not to overlap in a plan view. The depth of the bottom surface of the p-type semiconductor region PR is shallower than the depth of the bottom surface of the p-type well PW1. The bottom surface of the p-type semiconductor region PR is covered with the p-type well PW1. The p-type impurity concentration of the p-type semiconductor region PR is higher than the p-type impurity concentration of the p-type well region PW1.

[0036] In addition, the STI region 3 is disposed between the n-type semiconductor region CD and the p-type semiconductor region PR in a plan view. Therefore, the side surfaces of the n-type semiconductor region CD and the p-type semiconductor region PR are covered with the STI region 3.

[0037] A back electrode (not shown) may be formed on the back surface of the semiconductor substrate SUB. For example, a ground potential can be supplied from the back electrode to the substrate body SB.

[0038] As shown in FIG. 1, the semiconductor device of the present embodiment further includes an insulating film IL, a plurality of plugs PG, and a plurality of wirings M1.

[0039] An insulating film IL1 is formed on the main surface of the semiconductor substrate SUB. The insulating film IL1 is made of, for example, a laminated film of a silicon nitride film and a silicon oxide film on the silicon nitride film. A plurality of contact holes are formed in the insulating film IL, and a plurality of conductive plugs PG are formed in the plurality of contact holes. The plurality of plugs PG include a plug PGA and a plug PGC. The plug PGA is disposed on the p-type semiconductor region PR and is electrically connected to the p-type semiconductor region PR. The plug PGC is disposed on the n-type semiconductor region CD and is electrically connected to the n-type semiconductor region CD.

[0040] Also, a metal silicide layer (not shown) can be formed on the n-type semiconductor region CD and the p-type semiconductor region PR. In that case, the plug PGC contacts the metal silicide layer on the n-type semiconductor region CD and is electrically connected to the n-type semiconductor region CD through the metal silicide layer. Also, the plug PGA contacts the metal silicide layer on the p-type semiconductor region PR and is electrically connected to the p-type semiconductor region PR through the metal silicide layer.

[0041] A plurality of wirings M1 are formed on the insulating film IL. The plurality of wirings M1 include an anode wiring M1A and a cathode wiring M1C. The cathode wiring M1C is electrically connected to the n-type semiconductor region CD via a plug PGC. A cathode potential is supplied from the cathode wiring M1C to the n-type cathode region of the Zener diode via the plug PGC. The anode wiring M1A is electrically connected to the p-type semiconductor region PR via a plug PGA, and is further electrically connected to the p-type well region PW1 via the p-type semiconductor region PR. An anode potential is supplied from the anode wiring M1A to the p-type anode region of the Zener diode via the plug PGA.

[0042] The illustration and description of the structure above the insulating film IL and the wiring M1 will be omitted.

[0043] In this embodiment, an n-type cathode region and a p-type cathode region of the Zener diode are formed in the semiconductor layer EP in the Zener diode formation region 1A surrounded by the DTI region 5 and the n-type buried layer NBL. Therefore, the Zener diode formed in the semiconductor substrate SUB can be electrically isolated from other semiconductor elements formed in the semiconductor substrate SUB. The other semiconductor elements formed in the semiconductor substrate SUB are, for example, transistor elements formed in the transistor formation region 1B.

[0044] <About the manufacturing process of semiconductor devices> The manufacturing process of the semiconductor device of this embodiment will be described with reference to the drawings. Figures 2 to 13 are cross-sectional views of the main part of the semiconductor device during the manufacturing process of this embodiment.

[0045] First, a semiconductor substrate SUB is prepared having a p-type substrate body SB, an n-type buried layer NBL on the p-type substrate body SB, and a p-type semiconductor layer EP on the n-type buried layer NBL, as shown in Fig. 2. The p-type substrate body SB is made of, for example, p-type single crystal silicon.

[0046] As shown in Fig. 2, an n-type buried layer NBL is formed near the interface between the substrate body SB and the semiconductor layer EP. The n-type buried layer NBL can also be formed before the semiconductor layer EP is formed. For example, after the n-type buried layer NBL is formed in the surface layer portion of the p-type substrate body SB by ion implantation, the p-type semiconductor layer EP can be formed on the n-type buried layer NBL by epitaxial growth.

[0047] 3, an n-type drift region DF is formed in the semiconductor layer EP in the transistor formation region 1B by using an ion implantation method etc. The n-type drift region DF is an n-type semiconductor region.

[0048] Next, as shown in FIG. 4, a photoresist pattern RP1 is formed on the main surface of the semiconductor substrate SUB.

[0049] Next, using the photoresist pattern RP1 as a mask layer, a step of ion-implanting p-type impurities into the semiconductor layer EP in the Zener diode formation region 1A is performed twice to form p-type semiconductor regions AD1 and AD2.

[0050] The first ion implantation process forms a p-type semiconductor region AD2, and the second ion implantation process forms a p-type semiconductor region AD1. The implantation energy of the first ion implantation process is greater than that of the second ion implantation process. As an example, the implantation energy of the first ion implantation process is, for example, 200 keV, and the implantation energy of the second ion implantation process is, for example, 50 keV. The dose of the first ion implantation process is greater than that of the second ion implantation process.

[0051] The p-type impurity concentration of the p-type semiconductor region AD2 is higher than the p-type impurity concentration of the p-type semiconductor region AD1, and the p-type semiconductor region AD2 is located below the p-type semiconductor region AD1.

[0052] In this embodiment, the p-type semiconductor region AD2 is formed by the first ion implantation step, and the p-type semiconductor region AD1 is formed by the second ion implantation step, but it is also possible to form the p-type semiconductor region AD1 by the first ion implantation step, and form the p-type semiconductor region AD2 by the second ion implantation step. In that case, the injection energy of the second ion implantation step is larger than the injection energy of the first ion implantation step, and the dose of the second ion implantation step is larger than the dose of the first ion implantation step.

[0053] In this manner, the p-type semiconductor region AD2 is formed by ion implantation with a larger implantation energy and dose amount than those of the ion implantation that forms the p-type semiconductor region AD1. This allows the p-type semiconductor region AD2, which has a higher p-type impurity concentration than the p-type semiconductor region AD1, to be formed at a position deeper than the p-type semiconductor region AD1. As a result, the p-type semiconductor region AD2, which has a higher p-type impurity concentration than the p-type semiconductor region AD1, is located below the p-type semiconductor region AD1.

[0054] Moreover, each of the p-type semiconductor regions AD1 and AD2 is formed by ion implantation using a photoresist pattern RP1 as a mask layer. Therefore, the planar dimensions (area) of the p-type semiconductor region AD1 and the planar dimensions of the p-type semiconductor region AD2 are approximately the same as each other, but may be different. In a plan view, the p-type semiconductor region AD1 and the p-type semiconductor region AD2 overlap each other.

[0055] Thereafter, the photoresist pattern RP1 is removed by ashing or the like.

[0056] Next, as shown in FIG. 5, an STI region 3 is formed by using an STI method.

[0057] After forming the trench 2 in the main surface of the semiconductor substrate SUB, an insulating film made of a silicon oxide film or the like is formed on the main surface of the semiconductor substrate SUB so as to fill the trench 2. Thereafter, the insulating film disposed outside the trench 2 is removed using a CMP (Chemical Mechanical Polishing) method or the like. This makes it possible to form an STI region 3 made of the insulating film buried in the trench 2.

[0058] Next, as shown in FIG. 6, in the transistor formation region 1B, an n-type semiconductor region NW1 is formed in the semiconductor layer EP by using an ion implantation method or the like.

[0059] Next, as shown in Fig. 6, a p-type well region PW1 and a p-type well region PW2 are formed by using an ion implantation method or the like. The p-type well region PW1 and the p-type well region PW2 are each a p-type semiconductor region. In the Zener diode formation region 1A, the p-type well region PW1 is formed in the semiconductor layer EP. In the transistor formation region 1B, the p-type well region PW2 is formed in the semiconductor layer EP.

[0060] The p-type well region PW1 is formed to a predetermined depth from the main surface of the semiconductor substrate SUB. The p-type well region PW1 is formed so as to include the p-type semiconductor regions AD1, AD2 in a plan view. The depth of the bottom surface of the p-type well region PW1 is deeper than the depth of the bottom surface of the p-type semiconductor region AD2. Therefore, each side surface of the p-type semiconductor regions AD1, AD2 and the bottom surface of the p-type semiconductor region AD2 are covered by the p-type well region PW1. The p-type impurity concentrations of each of the p-type semiconductor regions AD1, AD2 are higher than the p-type impurity concentration of the p-type well region PW1.

[0061] The p-type well region PW1 and the p-type well region PW2 can be formed by the same ion implantation step, thereby reducing the number of manufacturing steps, but they can also be formed by separate ion implantation steps.

[0062] In addition, in this embodiment, the p-type well regions PW1, PW2 are formed after the n-type semiconductor region NW1 is formed, but the n-type semiconductor region NW1 can also be formed after the p-type well regions PW1, PW2 are formed.

[0063] 7, in the transistor formation region 1B, a gate electrode GE is formed on the main surface of the semiconductor layer EP via a gate insulating film GF. The gate electrode GE is made of, for example, a polycrystalline silicon film. The gate insulating film GF is made of, for example, a silicon oxide film.

[0064] Next, as shown in Fig. 8, an n-type semiconductor region CD, an n-type source region SR, and an n-type drain region DR are formed by ion implantation or the like. The n-type source region SR is an n-type semiconductor region that functions as the source region of the LDMOSFET. The n-type drain region DR is an n-type semiconductor region that functions as the drain region of the LDMOSFET.

[0065] In the Zener diode forming region 1A, the n-type semiconductor region CD is formed in the semiconductor layer EP. The n-type semiconductor region CD is formed to a predetermined depth from the main surface of the semiconductor substrate SUB. By forming the n-type semiconductor region CD, the p-type semiconductor region AD1 is located below the n-type semiconductor region CD.

[0066] In the transistor formation region 1B, the n-type drain region DR is formed in the semiconductor layer EP, more specifically, in the n-type drift region DF. The n-type impurity concentration of the n-type drain region DR is higher than the n-type impurity concentration of the n-type drift region DF. In the transistor formation region 1B, the n-type source region SR is formed in the semiconductor layer EP, more specifically, in the p-type well region PW2. The n-type semiconductor region CD, the n-type source region SR, and the n-type drain region DR can be formed by the same ion implantation process to reduce the number of manufacturing steps, but they can also be formed by separate ion implantation processes.

[0067] 8, the p-type semiconductor region PR and the p-type semiconductor region PC are formed by using an ion implantation method or the like. The p-type well region PR is formed in the semiconductor layer EP of the Zener diode formation region 1A, more specifically, in the p-type well region PW1. In the transistor formation region 1B, the p-type well region PC is formed in the semiconductor layer EP, more specifically, in the p-type well region PW2. The p-type semiconductor region PR and the p-type semiconductor region PC can be formed by the same ion implantation process to reduce the number of manufacturing steps, but they can also be formed by separate ion implantation processes.

[0068] In this embodiment, the p-type semiconductor regions PC, PR are formed after the n-type source region SR and the n-type drain region DR are formed, but the n-type source region SR and the n-type drain region DR can also be formed after the p-type semiconductor regions PC, PR are formed.

[0069] The n-type source region SR may have an LDD (Lightly doped Drain) structure. In this case, an n-type semiconductor region (not shown) for the LDD structure is formed by ion implantation, and then a sidewall insulating film (not shown) is formed on the sidewall of the gate insulating film GF. Then, the n-type source region SR and the n-type drain region DR are formed by ion implantation. The n-type impurity concentration of the n-type semiconductor region for the LDD structure is lower than the n-type impurity concentrations of the n-type source region SR and the n-type drain region DR.

[0070] Also, after forming the n-type source region SR, the n-type drain region DR, the p-type semiconductor region PR, and the p-type semiconductor region PC, a metal silicide layer (not shown) may be formed on the n-type source region SR, the n-type drain region DR, the p-type semiconductor region PC, the gate electrode GE, the p-type semiconductor region PR, and the n-type semiconductor region CD. The metal silicide layer SL is formed by using a salicide (Self Aligned Silicide) technique.

[0071] 9, an insulating film IL is formed on the main surface of the semiconductor substrate SUB so as to cover the gate electrode GE by using a CVD (Chemical Vapor Deposition) method or the like. After the insulating film IL is formed, the upper surface of the insulating film IL may be polished and planarized by using a CMP method or the like.

[0072] 10, a photoresist pattern (not shown) is used as an etching mask to etch the insulating film IL, the STI region 3, and the semiconductor substrate SUB, thereby forming a trench 4. The trench 4 penetrates the insulating film IL, the STI region 3, the semiconductor layer EP, and the n-type buried layer NBL, and reaches the p-type substrate body SB.

[0073] Next, as shown in FIG. 11, a DTI region 5 is formed in the trench 4 .

[0074] After forming the trench 4, an insulating film made of a silicon oxide film or the like is formed on the insulating film IL so as to fill the trench 4. Thereafter, the insulating film arranged outside the trench 4 is removed by a CMP method or the like. This makes it possible to form a DTI region 5 made of the insulating film buried in the trench 4. A void may be formed in the DTI region 5. Furthermore, in this embodiment, a step of removing the insulating film arranged outside the trench 4 by a CMP method or the like is performed, but this step may not be performed. In that case, the insulating film formed integrally with the DTI region 5 remains on the insulating film IL.

[0075] 12, a photoresist pattern (not shown) formed on the insulating film IL is used as an etching mask to etch the insulating film IL, thereby forming a plurality of contact holes penetrating the insulating film IL. Then, a plurality of conductive plugs PG are formed in the respective contact holes.

[0076] For example, a barrier conductor film is formed on the bottom surface of the contact hole, the side surface of the contact hole, and the upper surface of the insulating film IL. A main conductor film made of tungsten or the like is formed on the barrier conductor film so as to fill the inside of the contact hole. After that, the main conductor film and the barrier conductor film arranged outside the contact hole are removed by a CMP method or the like. This allows multiple plugs PG to be formed.

[0077] Next, as shown in FIG. 13, a plurality of wirings M1 are formed on the insulating film IL. For example, a conductive film is formed on the insulating film IL. Then, the conductive film is patterned using photolithography and etching techniques to form a plurality of wirings M1 made of the conductive film. Although aluminum wiring is suitable for the plurality of wirings M1, wiring using other metal materials, such as tungsten wiring, can also be applied. Also, copper wiring formed using a damascene technique can be applied as the plurality of wirings M1.

[0078] The multiple wirings M1 include an anode wiring M1A, a cathode wiring M1C, a source wiring M1S, and a drain wiring M1D.

[0079] The drain wiring M1D is electrically connected to the n-type drain region DR through a plug PG arranged on the n-type drain region DR. The source wiring M1S is electrically connected to the n-type source region SR through a plug PG arranged on the n-type source region SR, and is also electrically connected to the p-type semiconductor region PC through a plug PG arranged on the p-type semiconductor region PC. Therefore, the source potential supplied from the source wiring M1S to the n-type source region SR through the plug PG is supplied from the source wiring M1S to the p-type semiconductor region PC through the plug PG, and is further supplied from the p-type semiconductor region PC to the p-type well region PW2. The source wiring M1S, the drain wiring M1D, the cathode wiring M1C, and the anode wiring M1A are not connected and are separated from each other.

[0080] Further, the process of forming the upper insulating film and wiring is omitted from the illustration and description.

[0081] <About the process of the review> Fig. 14 is a cross-sectional view of a main part of a semiconductor device of a first study example studied by the present inventors. Fig. 14 shows a cross section corresponding to Fig. 1. Fig. 14 also shows a parasitic NPN bipolar transistor TR101 and a parasitic PNP bipolar transistor TR102 formed in the semiconductor device of the first study example.

[0082] The semiconductor device of the first studied example shown in Fig. 14 has a p-type semiconductor region AD101 instead of the p-type semiconductor regions AD1 and AD2 shown in Fig. 1. As shown in Fig. 14, the p-type semiconductor region AD101 is formed below the n-type semiconductor region CD in the p-type well region PW1. The p-type impurity concentration of the p-type semiconductor region AD101 is higher than the p-type impurity concentration of the p-type well region PW1.

[0083] In the first study example, in the process of Figure 4, the ion implantation process of p-type impurities using the photoresist pattern RP1 as a mask layer is performed only once, and the p-type semiconductor region AD101 is formed by that single ion implantation process.

[0084] 14, the n-type semiconductor region CD functions as an n-type cathode region of the Zener diode, and the p-type semiconductor region consisting of the p-type semiconductor region AD101 and the p-type well region PW1 functions as a p-type anode region of the Zener diode. The breakdown voltage of the Zener diode is determined by the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD101.

[0085] According to the study by the present inventors, it was found that the following problem occurs in the first study example.

[0086] In the semiconductor device of the first studied example shown in FIG. 14, a parasitic thyristor is formed, which is made up of a parasitic NPN bipolar transistor TR101 and a parasitic PNP bipolar transistor TR102.

[0087] The n-type buried layer NBL functions as the n-type collector region of the parasitic NPN bipolar transistor TR101. The p-type semiconductor region consisting of the p-type semiconductor region AD101 and the p-type well region PW1 functions as the p-type base region of the parasitic NPN bipolar transistor TR101. The n-type semiconductor region CD functions as the n-type emitter region of the parasitic NPN bipolar transistor TR101.

[0088] Moreover, the p-type substrate body SB functions as a p-type collector region of the parasitic PNP bipolar transistor TR102. The n-type buried layer NBL functions as an n-type base region of the parasitic PNP bipolar transistor TR102. The p-type semiconductor region consisting of the p-type semiconductor region AD101, the p-type well region PW1, and the p-type semiconductor region PR functions as a p-type emitter region of the parasitic PNP bipolar transistor TR102.

[0089] When a potential lower than the potential of the p-type substrate body SB is supplied to the n-type semiconductor region CD, which is the n-type cathode region of the Zener diode, and the p-type well region PW1, which is the p-type anode region, the above-mentioned parasitic thyristor may operate. This is because when such a potential is supplied to the n-type semiconductor region CD and the p-type well region PW1, the parasitic NPN bipolar transistor TR101 operates first, and then the parasitic PNP bipolar transistor TR102 also operates.

[0090] When the parasitic thyristor operates, electrons flow from the semiconductor layer EP to the p-type substrate body SB in the Zener diode forming region 1A. From another perspective, a current flows from the p-type substrate body SB to the semiconductor layer EP in the Zener diode forming region 1A. Some of the electrons that flow from the semiconductor layer EP to the p-type substrate body SB recombine with holes in the p-type substrate body SB. Another part of the electrons that flow from the semiconductor layer EP to the p-type substrate body SB moves in the p-type substrate body SB and affects other semiconductor elements formed in the semiconductor substrate SUB, resulting in a decrease in the performance of the semiconductor device. In order to improve the performance of the semiconductor device, it is desirable to prevent the parasitic thyristor from operating.

[0091] 14, it is possible to suppress the operation of the parasitic thyristor by increasing the p-type impurity concentration of the p-type semiconductor region AD101. This is because, if the p-type impurity concentration of the p-type semiconductor region AD101 is increased, the p-type impurity concentration of the p-type base region of the parasitic NPN bipolar transistor TR101 becomes high, making it difficult for the parasitic NPN bipolar transistor TR101 to operate.

[0092] The PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD101 determines the breakdown voltage of the Zener diode. The breakdown voltage of the Zener diode is controlled by adjusting the p-type impurity concentration of the p-type semiconductor region AD101 in the vicinity of the interface between the n-type semiconductor region CD and the p-type semiconductor region AD101. For this reason, the p-type impurity concentration of the p-type semiconductor region AD101 in the vicinity of the interface between the n-type semiconductor region CD and the p-type semiconductor region AD101 must be set according to the required breakdown voltage of the Zener diode. The required breakdown voltage of the Zener diode is the design value of the breakdown voltage of the Zener diode. For this reason, the p-type impurity concentration of the p-type semiconductor region AD101 must be set according to the required breakdown voltage of the Zener diode, so it is difficult to increase the p-type impurity concentration of the p-type semiconductor region AD101 to suppress the operation of the parasitic thyristor.

[0093] 15 is a cross-sectional view of a main part of a semiconductor device according to a second study example studied by the present inventors, which corresponds to the cross section shown in FIG.

[0094] The semiconductor device of the second studied example shown in FIG. 15 has an n-type semiconductor region NC1, an n-type semiconductor region NC2, and a plug PGN.

[0095] The n-type semiconductor region NC1 and the n-type semiconductor region NC2 are formed in the semiconductor layer EP. The n-type semiconductor region NC1 and the n-type semiconductor region NC2 are in contact with each other. The n-type semiconductor region NC1 and the n-type buried layer NBL are in contact with each other. The plug PGN is formed on the n-type semiconductor region NC2. The n-type impurity concentration of the n-type semiconductor region NC2 is higher than the n-type impurity concentration of the n-type semiconductor region NC1. The plug PGN is electrically connected to the n-type buried layer NBL via the n-type semiconductor region NC2 and the n-type semiconductor region NC1.

[0096] 15, the same potential as that of the p-type substrate body SB can be supplied from the wiring M1N to the n-type buried layer NBL via the plug PGN, the n-type semiconductor region NC2, and the n-type semiconductor region NC1. Therefore, since the potential of the p-type substrate body SB and the potential of the n-type buried layer NBL are the same, it is possible to prevent the parasitic PNP bipolar transistor TR102 from operating. This makes it possible to prevent the parasitic thyristor from operating.

[0097] 15, it is necessary to form n-type semiconductor regions NC1 and NC2 in the semiconductor layer EP. Therefore, the planar dimensions of the Zener diode-forming region 1A in the second study example are larger than those of the Zener diode-forming region 1A in the first study example, and as a result, the planar dimensions of the semiconductor device are increased. In order to miniaturize the semiconductor device, it is desirable not to form the n-type semiconductor regions NC1 and NC2 in the semiconductor layer EP in the Zener diode-forming region 1A.

[0098] 16 is a cross-sectional view of a main part of a semiconductor device according to a third study example studied by the present inventors, which corresponds to the cross section shown in FIG.

[0099] In the third examined example shown in Fig. 16, the p-type semiconductor region AD101 is formed deeper than in the first examined example. That is, the depth of the bottom surface of the p-type semiconductor region AD101 in the third examined example shown in Fig. 16 is deeper than the depth of the bottom surface of the p-type semiconductor region AD101 in the first examined example shown in Fig. 14. The injection energy of the ion implantation for forming the p-type semiconductor region AD101 in the third examined example is higher than the injection energy of the ion implantation for forming the p-type semiconductor region AD101 in the first examined example.

[0100] 16, the thickness of the p-type semiconductor region AD101 is greater than that of the first study example. Therefore, in the third study example, the p-type impurity concentration of the p-type base region of the parasitic NPN bipolar transistor TR101 is higher than that of the first study example, making it difficult for the parasitic NPN bipolar transistor TR101 to operate. Therefore, in the third study example, it is easier to suppress the operation of the parasitic thyristor than in the first study example.

[0101] 16, it is more difficult to control the p-type impurity concentration of the p-type semiconductor region AD101 in the vicinity of the interface between the n-type semiconductor region CD and the p-type semiconductor region AD101 than in the first studied example, for the following reasons.

[0102] When the p-type semiconductor region AD101 is formed by ion implantation, the p-type impurity concentration of the p-type semiconductor region AD101 near the bottom surface of the p-type semiconductor region AD101 can be easily controlled by adjusting the dose of ion implantation. In comparison, the p-type impurity concentration of the p-type semiconductor region AD101 at a position away from the bottom surface of the p-type semiconductor region AD101 is prone to fluctuate, and it is difficult to control it to a desired concentration. In the case of the third study example, the distance from the interface between the n-type semiconductor region CD and the p-type semiconductor region AD101 to the bottom surface of the p-type semiconductor region AD101 is greater than in the first study example, so that it is difficult to control the p-type impurity concentration of the p-type semiconductor region AD101 near the interface between the n-type semiconductor region CD and the p-type semiconductor region AD101. Therefore, in the third study example, the breakdown voltage of the Zener diode is more likely to fluctuate than in the first study example. In order to improve the reliability of the semiconductor device, it is necessary to prevent the breakdown voltage of the Zener diode from fluctuating.

[0103] <Main features and effects> The semiconductor device of this embodiment has a semiconductor substrate SUB having a p-type substrate region (p-type substrate body SB), an n-type buried layer (n-type semiconductor layer) NBL formed on the p-type substrate region, and a p-type semiconductor layer EP formed on the n-type buried layer NBL. The semiconductor device of this embodiment further has a DTI region (element isolation region) 5 penetrating the semiconductor layer EP and the n-type buried layer NBL to reach the p-type substrate body SB, an n-type cathode region (n-type semiconductor region CD) of a Zener diode formed in the semiconductor layer EP, and a p-type anode region of the Zener diode formed in the semiconductor layer EP.

[0104] One of the main features of this embodiment is that the p-type anode region of the Zener diode includes a p-type semiconductor region AD1 formed below the n-type semiconductor region CD and a p-type semiconductor region AD2 formed below the p-type semiconductor region AD1. A PN junction of the Zener diode is formed between the p-type semiconductor region AD1 and the n-type semiconductor region CD. The p-type impurity concentration of the p-type semiconductor region AD2 is higher than the p-type impurity concentration of the p-type semiconductor region AD1.

[0105] Fig. 17 is an explanatory diagram of the semiconductor device of this embodiment. Fig. 17 shows the same cross section as Fig. 1. Hatching is omitted in Fig. 17. Fig. 17 also shows a parasitic NPN bipolar transistor TR1 and a parasitic PNP bipolar transistor TR2 formed in the semiconductor device of this embodiment.

[0106] In the semiconductor device of this embodiment, a parasitic thyristor is formed, which is composed of a parasitic NPN bipolar transistor TR1 and a parasitic PNP bipolar transistor TR2.

[0107] The n-type buried layer NBL functions as the n-type collector region of the parasitic NPN bipolar transistor TR1. The p-type semiconductor region consisting of the p-type semiconductor region AD1, the p-type semiconductor region AD2, and the p-type well region PW1 functions as the p-type base region of the parasitic NPN bipolar transistor TR1. The n-type semiconductor region CD functions as the n-type emitter region of the parasitic NPN bipolar transistor TR1.

[0108] In addition, the p-type substrate body SB functions as a p-type collector region of the parasitic PNP bipolar transistor TR2. The n-type buried layer NBL functions as an n-type base region of the parasitic PNP bipolar transistor TR2. The p-type semiconductor region consisting of the p-type semiconductor region AD1, the p-type semiconductor region AD2, the p-type well region PW1, and the p-type semiconductor region PR functions as a p-type emitter region of the parasitic PNP bipolar transistor TR2.

[0109] In this embodiment, the p-type semiconductor region AD1 is formed in order to set the p-type impurity concentration of the p-type semiconductor region AD1 in the vicinity of the interface between the n-type semiconductor region CD and the p-type semiconductor region AD1 to a predetermined design concentration, where the design concentration is a concentration that can obtain the required breakdown voltage of the Zener diode.

[0110] Since the depth of the bottom surface of the p-type semiconductor region AD1 is shallower than the depth of the bottom surface of the p-type semiconductor region AD2, the distance from the interface between the n-type semiconductor region CD and the p-type semiconductor region AD1 to the bottom surface of the p-type semiconductor region AD1 is small. Therefore, by adjusting the dose of ion implantation to form the p-type semiconductor region AD1, the p-type impurity concentration of the p-type semiconductor region AD1 in the vicinity of the interface between the n-type semiconductor region CD and the p-type semiconductor region AD1 can be easily set to a predetermined design concentration. Therefore, the withstand voltage of the Zener diode can be set to the required withstand voltage, and fluctuations in the withstand voltage of the Zener diode can be suppressed.

[0111] And, by forming the p-type semiconductor region AD2, which has a higher p-type impurity concentration than the p-type semiconductor region AD1, below the p-type semiconductor region AD1, the p-type impurity concentration of the p-type anode region below the n-type semiconductor region CD becomes high. This increases the p-type impurity concentration of the p-type base region of the parasitic NPN bipolar transistor TR1, making it difficult for the parasitic NPN bipolar transistor TR1 to operate. As a result, it is possible to suppress or prevent the parasitic thyristor from operating.

[0112] That is, in this embodiment, the p-type semiconductor region AD1 is formed below the n-type semiconductor region CD, so that the breakdown voltage of the Zener diode can be set to the required breakdown voltage. The p-type semiconductor region AD2 having a higher p-type impurity concentration than the p-type semiconductor region AD1 is formed below the p-type semiconductor region AD1, so that the operation of the parasitic thyristor can be suppressed. This makes it possible to improve the performance of the semiconductor device including the Zener diode. Also, it makes it possible to improve the reliability of the semiconductor device including the Zener diode.

[0113] Furthermore, when ions are implanted into the semiconductor substrate SUB, if the dose of the ion implantation is large, there is a risk that the semiconductor substrate SUB will be damaged. The dose of the ion implantation to form the p-type semiconductor region AD2 in this embodiment is smaller than the dose of the ion implantation to form the p-type semiconductor region AD101 in the third study example. This is because, in the third study example, the p-type impurity concentration in the vicinity of the interface between the n-type semiconductor region CD and the p-type semiconductor region AD101 needs to be set to a predetermined design concentration, and therefore the dose of the ion implantation to form the p-type semiconductor region AD101 needs to be large. In contrast, in this embodiment, the p-type impurity concentration in the vicinity of the interface between the n-type semiconductor region CD and the p-type semiconductor region AD1 is adjusted by the dose of the ion implantation to form the p-type semiconductor region AD1. Therefore, in this embodiment, the dose of the ion implantation to form the p-type semiconductor region AD1 and the dose of the ion implantation to form the p-type semiconductor region AD2 can each be smaller than the dose of the ion implantation to form the p-type semiconductor region AD101 in the third study example. Therefore, it is possible to suppress or prevent the semiconductor substrate SUB from being damaged by the ion implantation for forming the p-type semiconductor region AD1 and the ion implantation for forming the p-type semiconductor region AD2, thereby improving the reliability of the semiconductor device.

[0114] In addition, in this embodiment, the potential of the n-type buried layer NBL is a floating potential. A structure for supplying power from the wiring M1 and the plug PG to the n-type buried layer NBL is not formed in the semiconductor substrate SUB. That is, the n-type semiconductor regions NC1 and NC2 in the second study example of FIG. 15 are not formed in the Zener diode formation region 1A in this embodiment. Therefore, in this embodiment, the planar dimensions of the Zener diode formation region 1A can be made smaller than those in the second study example. Therefore, the semiconductor device can be made smaller.

[0115] In addition, when a potential lower than the potential of the p-type substrate body SB is supplied to the n-type semiconductor region CD, which is the n-type cathode region of the Zener diode, and the p-type well region PW1, which is the p-type anode region, a parasitic thyristor may operate. In this embodiment, the p-type semiconductor region AD1 is formed under the n-type semiconductor region CD, and the p-type semiconductor region AD2 is formed under the p-type semiconductor region AD1, so that the parasitic thyristor can be suppressed or prevented from operating. Therefore, if the potential supplied from the plug PGC to the n-type semiconductor region CD and the potential supplied from the plug PGA to the p-type well region PW1 during the operation of the Zener diode are lower than the potential of the p-type substrate body SB, the application of the semiconductor device of this embodiment is very effective.

[0116] Moreover, the potential of the p-type substrate body SB is generally the ground potential, so that when the potential supplied from the plug PGC to the n-type semiconductor region CD and the potential supplied from the plug PGA to the p-type well region PW1 during operation of the Zener diode are both negative potentials, application of the semiconductor device of this embodiment is highly effective.

[0117] Furthermore, when the Zener diode operates in the forward direction, the parasitic thyristor is more likely to operate than when the Zener diode operates in the reverse direction. Therefore, when the potential supplied from the plug PGA to the p-type well region PW1 is higher than the potential supplied from the plug PGC to the n-type semiconductor region CD during the operation of the Zener diode, the application of the semiconductor device of the present embodiment is very effective.

[0118] FIG. 18 is a graph showing the operating characteristics of the Zener diode of the first study example. FIG. 19 is a graph showing the operating characteristics of the Zener diode of this embodiment. In each of FIG. 18 and FIG. 19, the voltage VKA on the horizontal axis of the graph indicates the difference between the anode voltage and the cathode voltage, and the vertical axis of the graph indicates the current value. In each of FIG. 18 and FIG. 19, the operating characteristics when the anode potential and the cathode potential are negative potentials and the anode potential is higher than the cathode potential are shown. In each of FIG. 18 and FIG. 19, the anode current of the Zener diode is shown by a solid line, and the substrate current is shown by a dotted line. The anode current is a forward current of the Zener diode. The substrate current flows from the p-type substrate body SB to the semiconductor layer EP.

[0119] In the first example shown in FIG. 18, the parasitic thyristor starts to operate at the operating point P1 shown in the graph. When the voltage VKA becomes larger than the operating point P1, the parasitic thyristor operates and the substrate current flowing from the p-type substrate body SB to the semiconductor layer EP increases rapidly. This causes the anode current of the Zener diode to flow backwards, and no current flows from the anode region to the cathode region. As a result, the normal operation of the Zener diode is hindered.

[0120] On the other hand, in the case of the present embodiment shown in Fig. 19, the parasitic thyristor does not operate. That is, the operating point P1 shown in the graph of Fig. 18 does not exist in the graph of Fig. 19. For this reason, the Zener diode operates normally.

[0121] (Embodiment 2) 20 is a cross-sectional view of a main part of a semiconductor device according to the present embodiment 2. In FIG 20, a cross section corresponding to the above-mentioned FIG 13 is shown.

[0122] As shown in FIG. 20, the semiconductor device of the second embodiment has a p-type semiconductor region PS1 and a p-type RESURF layer RE.

[0123] As shown in FIG. 20, in the Zener diode formation region 1A, the p-type semiconductor region PS1 is formed in the semiconductor layer EP. The p-type semiconductor region PS1 is located below the p-type well PW1. That is, the p-type semiconductor region PS1 is formed in the p-type semiconductor layer EP below the p-type well PW1. In this second embodiment, the p-type well PW1 and the p-type semiconductor region PS1 are adjacent to each other in the direction from the main surface toward the back surface of the semiconductor substrate SUB. The p-type semiconductor region PS1 is away from the n-type buried layer NBL. The impurity concentration of the p-type semiconductor region PS1 is higher than the impurity concentration of the p-type semiconductor layer EP below the p-type semiconductor region PS1.

[0124] In the transistor formation region 1B, the p-type RESURF layer RE is formed in the semiconductor layer EP. The p-type RESURF layer RE is formed below the p-type well region PW2 and below the n-type drift region DF.

[0125] The p-type semiconductor region PS1 and the p-type RESURF layer RE can be formed by the same ion implantation process, thereby reducing the number of manufacturing steps of the semiconductor device. For example, the p-type semiconductor region PS1 and the p-type RESURF layer RE can be formed by ion implantation before the p-type semiconductor regions AD1 and AD2 are formed.

[0126] Other configurations of the semiconductor device of the second embodiment are similar to those of the semiconductor device of the first embodiment.

[0127] In the second embodiment, a p-type semiconductor region PS1 having a higher p-type impurity concentration than the p-type semiconductor layer EP is formed in the p-type semiconductor layer EP below the p-type well region PW1. The formation of the p-type semiconductor region PS1 further increases the p-type impurity concentration of the p-type base region of the parasitic NPN bipolar transistor TR1, making it even more difficult for the parasitic NPN bipolar transistor TR1 to operate. As a result, the operation of the parasitic thyristor can be further suppressed in the Zener diode formation region 1A.

[0128] (Embodiment 3) 21 is a cross-sectional view of a main part of a semiconductor device according to the present embodiment 3. In Fig. 21, a cross section corresponding to Figs. 13 and 20 is shown.

[0129] As shown in FIG. 21, the semiconductor device of the third embodiment has a p-type semiconductor region PS2, a p-type RESURF layer RE, and a p-type well region DPW.

[0130] As shown in FIG. 21, in the Zener diode forming region 1A, the p-type semiconductor region PS2 is formed in the semiconductor layer EP. The p-type semiconductor region PS2 is located below the p-type well PW1. That is, the p-type semiconductor region PS2 is formed in the p-type semiconductor layer EP below the p-type well PW1. In this third embodiment, the p-type semiconductor region PS2 is away from the p-type well PW1 and the n-type buried layer NBL. The impurity concentration of the p-type semiconductor region PS2 is higher than the impurity concentration of the p-type semiconductor layer EP below the p-type semiconductor region PS2. Also, the impurity concentration of the p-type semiconductor region PS2 is higher than the impurity concentration of the p-type semiconductor layer EP between the p-type semiconductor region PS2 and the p-type well PW1.

[0131] In the transistor formation region 1B, a p-type RESURF layer RE and a p-type well region DPW are formed in the semiconductor layer. The p-type RESURF layer RE is formed under the p-type well region PW2 and under the n-type drift region DF. The p-type well region DPW is formed under the p-type RESURF layer RE.

[0132] The p-type semiconductor region PS2 and the p-type well region DPW are formed by the same ion implantation process, thereby reducing the number of manufacturing steps of the semiconductor device. For example, the p-type semiconductor region PS2, the p-type RESURF layer RE, and the p-type well region DPW can be formed by ion implantation before forming the p-type semiconductor regions AD1 and AD2.

[0133] Other configurations of the semiconductor device of the third embodiment are similar to those of the semiconductor device of the first embodiment.

[0134] In the third embodiment, a p-type semiconductor region PS2 having a higher p-type impurity concentration than the p-type semiconductor layer EP is formed in the p-type semiconductor layer EP below the p-type well region PW1. The formation of the p-type semiconductor region PS2 further increases the p-type impurity concentration of the p-type base region of the parasitic NPN bipolar transistor TR1, making it even more difficult for the parasitic NPN bipolar transistor TR1 to operate. As a result, the operation of the parasitic thyristor can be further suppressed in the Zener diode formation region 1A.

[0135] (Embodiment 4) Fig. 22 is a cross-sectional view of a main part of the semiconductor device of the present embodiment 4. A cross section of a Zener diode-forming region 1A and a cross section of a diode-forming region 1C are shown in Fig. 22. The cross section of the Zener diode-forming region 1A in Fig. 22 corresponds to the cross section of the Zener diode-forming region 1A in Fig. 1 and Fig. 13 above.

[0136] As shown in FIG. 22, the semiconductor device of the fourth embodiment has a p-type semiconductor region PS3.

[0137] As shown in FIG. 22, in the Zener diode formation region 1A, the p-type semiconductor region PS3 is formed in the semiconductor layer EP. The p-type semiconductor region PS3 is located below the p-type well PW1. That is, the p-type semiconductor region PS3 is formed in the p-type semiconductor layer EP below the p-type well PW1. In this fourth embodiment, the p-type semiconductor region PS3 and the n-type buried layer NBL are adjacent to each other in the direction from the main surface toward the back surface of the semiconductor substrate SUB. The p-type semiconductor region PS3 is away from the p-type well PW1. The impurity concentration of the p-type semiconductor region PS3 is higher than the impurity concentration of the p-type semiconductor layer EP on the p-type semiconductor region PS3.

[0138] Other configurations of the diode-forming region 1A in the fourth embodiment are similar to those of the diode-forming region 1A in the first embodiment.

[0139] In the present embodiment 4, a diode element is formed in the diode formation region 1C. Specifically, as shown in Fig. 22, the semiconductor device of the present embodiment 4 has an n-type semiconductor region NR1, an n-type semiconductor region NR2, an n-type semiconductor region NC3, an n-type semiconductor region NC4, an n-type semiconductor region NC5, a p-type semiconductor region PA1, a p-type semiconductor region PA2, and a p-type buried layer PBL.

[0140] In the diode formation region 1C, the n-type semiconductor region NR1, the n-type semiconductor region NR2, the n-type semiconductor region NC3, the n-type semiconductor region NC4, the n-type semiconductor region NC5, the p-type semiconductor region PA1, the p-type semiconductor region PA2, and the p-type buried layer PBL are formed in the p-type semiconductor layer EP.

[0141] An n-type semiconductor region consisting of the n-type semiconductor region NR1 and the n-type semiconductor region NR2 functions as an n-type cathode region of the diode. The n-type semiconductor region NR1 is formed below the n-type semiconductor region NR2. The n-type impurity concentration of the n-type semiconductor region NR2 is higher than the n-type impurity concentration of the n-type semiconductor region NR1. A plug PG is disposed on the n-type semiconductor region NR2 and is electrically connected to the n-type semiconductor region NR2.

[0142] A p-type semiconductor region consisting of the p-type semiconductor region PA1, the p-type semiconductor region PA2, and the p-type semiconductor layer EP functions as a p-type anode region of the diode. The p-type semiconductor region PA1 is formed under the p-type semiconductor region PA2. The p-type impurity concentration of the p-type semiconductor region PA2 is higher than the p-type impurity concentration of the p-type semiconductor region PA1, and the p-type impurity concentration of the p-type semiconductor region PA1 is higher than the p-type impurity concentration of the p-type semiconductor layer EP. A plug PG is disposed on the p-type semiconductor region PA2, and the plug PG is electrically connected to the p-type semiconductor region PA2.

[0143] An n-type semiconductor region NC4 is formed below the n-type semiconductor region NC5, and an n-type semiconductor region NC3 is formed below the n-type semiconductor region NC4. The n-type semiconductor region NC3 is in contact with the n-type buried layer NBL. The n-type impurity concentration of the n-type semiconductor region NC5 is higher than that of the n-type semiconductor region NC4, and the n-type impurity concentration of the n-type semiconductor region NC4 is higher than that of the n-type semiconductor region NC3. A plug PG is disposed on the n-type semiconductor region NC5, and the plug PG is electrically connected to the n-type semiconductor region NC5.

[0144] The p-type buried layer PBL is formed on the n-type buried layer NBL. The p-type buried layer PBL and the n-type buried layer NBL are adjacent to each other in the direction from the main surface toward the back surface of the semiconductor substrate SUB. The p-type buried layer PBL has a higher p-type impurity concentration than the p-type semiconductor layer EP.

[0145] A cathode potential is supplied from the wiring M1CN to the n-type semiconductor region NR2 via the plug PG. An anode potential is supplied from the wiring M1AN to the p-type semiconductor region PA2 via the plug PG. Then, an anode potential is supplied from the wiring M1AN to the n-type buried layer NBL via the plug PG, the n-type semiconductor region NC5, the n-type semiconductor region NC4, and the n-type semiconductor region NC3. Therefore, in the diode-forming region 1C, the potential of the p-type anode region and the potential of the n-type buried layer NBL are the same. This makes it possible to prevent a parasitic thyristor from operating in the diode-forming region 1C.

[0146] The p-type semiconductor region PS3 in the Zener diode forming region 1A and the p-type buried layer PBL in the diode forming region 1C are formed in the same ion implantation step, thereby making it possible to reduce the number of steps in manufacturing the semiconductor device.

[0147] In the fourth embodiment, in the Zener diode forming region 1A, a p-type semiconductor region PS3 having a higher p-type impurity concentration than the p-type semiconductor layer EP is formed in the p-type semiconductor layer EP below the p-type well region PW1. By forming the p-type semiconductor region PS3, the p-type impurity concentration of the p-type base region of the parasitic NPN bipolar transistor TR1 becomes even higher, making it even more difficult for the parasitic NPN bipolar transistor TR1 to operate. As a result, it is possible to further suppress the operation of the parasitic thyristor in the Zener diode forming region 1A.

[0148] (Embodiment 5) 23, 24, 25, and 26 are explanatory diagrams showing examples of use of the semiconductor device. Each of FIG. 23 and FIG. 25 shows a circuit example using Zener diodes TD1, TD2, and TD3. Each of FIG. 24 and FIG. 26 shows the connection relationship of the Zener diodes TD1, TD2, and TD3. The connection relationship of the Zener diodes TD1, TD2, and TD3 shown in FIG. 24 is the same as the connection relationship of the Zener diodes TD1, TD2, and TD3 shown in the circuit diagram of FIG. 23. In addition, the connection relationship of the Zener diodes TD1, TD2, and TD3 shown in FIG. 26 is the same as the connection relationship of the Zener diodes TD1, TD2, and TD3 shown in the circuit diagram of FIG. 25. Each of FIG. 23, FIG. 24, FIG. 25, and FIG. 26 also shows an example of voltage when a negative surge voltage occurs.

[0149] As shown in Figures 23 and 25, one end of a series circuit of Zener diodes TD1, TD2, and TD3 is connected to a connection point P2 between the input terminal TE and the circuit CT to be protected. The other end of the series circuit of Zener diodes TD1, TD2, and TD3 is connected to ground potential. In this way, when a negative surge voltage is applied from the input terminal TE to the circuit CT to be protected, the Zener diodes TD1, TD2, and TD3 operate to allow a current to flow from the input terminal TE to the ground via the Zener diodes TD1, TD2, and TD3. As a result, when a negative surge voltage occurs at the input terminal TE, the circuit CT can be protected.

[0150] Of the Zener diodes TD1, TD2, and TD3 connected in series, the Zener diode TD1 is connected to the input terminal TE, the Zener diode TD3 is connected to the ground potential, and the Zener diode TD2 is disposed between the Zener diodes TD1 and TD3.

[0151] 23 and 24, the cathode (cathode wiring M1C) of the Zener diode TD1 is connected to the input terminal TE. The anode (anode wiring M1A) of the Zener diode TD1 is connected to the cathode (cathode wiring M1C) of the Zener diode TD2. The anode (anode wiring M1A) of the Zener diode TD2 is connected to the anode (anode wiring M1A) of the Zener diode TD3. And the cathode (cathode wiring M1C) of the Zener diode TD3 is connected to the ground potential.

[0152] 23 and 24, when a negative surge voltage occurs at the input terminal TE, the negative surge voltage is applied to the cathode (cathode wiring M1C) of the Zener diode TD1 via the connection point P2. As a result, the Zener diodes TD1 and TD2 operate in the forward direction, and the Zener diode TD3 operates in the reverse direction. In the Zener diode TD3 operating in the reverse direction, the difference between the anode voltage VA and the cathode voltage VK is, for example, 6V, and in each of the Zener diodes TD1 and TD2 operating in the forward direction, the difference between the anode voltage VA and the cathode voltage VK is, for example, 0.7V.

[0153] When the anode voltage VA is higher than the cathode voltage VK, the Zener diode operates in the forward direction, and when the anode voltage VA is lower than the cathode voltage VK, the Zener diode operates in the reverse direction.

[0154] In the case of FIG. 25 and FIG. 26, the anode (anode wiring M1A) of the Zener diode TD1 is connected to the input terminal TE. The cathode (cathode wiring M1C) of the Zener diode TD1 is connected to the cathode (cathode wiring M1C) of the Zener diode TD2. The anode (anode wiring M1A) of the Zener diode TD2 is connected to the cathode (cathode wiring M1C) of the Zener diode TD3. And the anode (anode wiring M1A) of the Zener diode TD3 is connected to the ground potential.

[0155] 25 and 26, when a negative surge voltage occurs at the input terminal TE, the negative surge voltage is applied to the anode (anode wiring M1A) of the Zener diode TD1 via the connection point P2. This causes the Zener diode TD1 to operate in the reverse direction, and the Zener diodes TD2 and TD3 to operate in the forward direction. In the Zener diode TD1 operating in the reverse direction, the difference between the anode voltage VA and the cathode voltage VK is, for example, 6V, and in each of the Zener diodes TD2 and TD3 operating in the forward direction, the difference between the anode voltage VA and the cathode voltage VK is, for example, 0.7V.

[0156] In the case of FIGS. 23 and 24, in the Zener diode TD3, the cathode voltage VK and the potential of the p-type substrate body SB are the same, and the anode voltage VA is lower than the cathode voltage VK, so that the parasitic thyristor does not operate.

[0157] In the cases of FIGS. 23 and 24, in the Zener diodes TD1 and TD2, both the anode voltage VA and the cathode voltage VK are negative potentials, and the anode voltage VA is higher than the cathode voltage VK, so that a parasitic thyristor may operate.

[0158] 25 and 26, in the Zener diode TD3, the anode voltage VK and the potential of the p-type substrate body SB are the same, so the parasitic PNP bipolar transistor TR2 does not operate. Therefore, in the Zener diode TD3, the parasitic thyristor does not operate.

[0159] 25 and 26, in the Zener diodes TD1 and TD2, both the anode voltage VA and the cathode voltage VK are negative potentials, so there is a possibility that a parasitic thyristor may operate. However, compared to when the anode voltage VA is higher than the cathode voltage VK, when the anode voltage VA is lower than the cathode voltage VK, the parasitic thyristor is less likely to operate.

[0160] For this reason, there is a concern that a parasitic thyristor may operate in the Zener diodes TD1 and TD2 in the cases of Figures 23 and 24. On the other hand, there is a concern that a parasitic thyristor may operate in the Zener diode TD2 in the cases of Figures 25 and 26.

[0161] The Zener diodes TD1, TD2, and TD3 have the structure of the Zener diode forming region 1A in any one of the above-mentioned embodiments 1, 2, 3, and 4. Therefore, in the cases of Fig. 23 and Fig. 24, the operation of a parasitic thyristor can be suppressed also in the Zener diodes TD1 and TD2. In the cases of Fig. 25 and Fig. 26, the operation of a parasitic thyristor can be suppressed also in the Zener diode TD2.

[0162] Here, the Zener diodes TD1 and TD2 in FIG. 23 and FIG. 24 are compared with the Zener diode TD2 in FIG. 25 and FIG. 26. In the Zener diode TD1 in FIG. 23 and FIG. 24, the potential difference between the p-type substrate body SB and the cathode region is −7.4V. In the Zener diode TD2 in FIG. 23 and FIG. 24, the potential difference between the p-type substrate body SB and the cathode region is −6.7V. In contrast, in the Zener diode TD2 in FIG. 25 and FIG. 26, the potential difference between the p-type substrate body SB and the cathode region is −1.4V. The larger the absolute value of the potential difference between the p-type substrate body SB and the cathode region, the easier it is for the parasitic thyristor to operate. Therefore, compared to the Zener diodes TD1 and TD2 in FIG. 23 and FIG. 24, the parasitic thyristor is less likely to operate in the Zener diode TD2 in FIG. 25 and FIG. 26. As a result, when comparing the Zener diodes TD1, TD2, and TD3 in Figures 23 and 24 with the Zener diodes TD1, TD2, and TD3 in Figures 25 and 26, it is easier to prevent the operation of a parasitic thyristor in the Zener diodes TD1, TD2, and TD3 in Figures 25 and 26. Therefore, by using the circuit configuration shown in Figures 25 and 26, the circuit CT can be reliably protected when a negative surge voltage occurs at the input terminal TE.

[0163] The invention made by the inventor has been specifically described above based on the embodiment thereof. However, it goes without saying that the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. [Explanation of symbols]

[0164] 1A Zener diode forming area 1B Transistor formation area 1C Diode formation area 2 grooves 3 STI area 4 grooves 5 DTI area AD1, AD2, AD101 p-type semiconductor region CD n-type semiconductor region DF n-type drift region DPW p-type well region DR n-type drain region EP Semiconductor Layer GE gate electrode GF Gate insulating film CT circuit IL insulating film M1A, M1AN anode wiring M1C, M1CN cathode wiring M1D drain wiring M1S source wiring M1 Wiring NBL n-type buried layer NC1, NC2, NC3, NC4, NC5, NR1, NR2, NW1 n-type semiconductor region PBL p-type buried layer PC, PR, PS1, PS2, PS3 p-type semiconductor region PG,PG2,PGA,PGC,PGN plug PW1, PW2 p-type well region RE p-type RESURF layer RP1 Photoresist pattern SB Board Body SR n-type source region SUB Semiconductor Substrate TD1, TD2, TD3 Zener diodes TE input terminal TR1, TR101 Parasitic NPN bipolar transistor TR2, TR102 Parasitic PNP bipolar transistor

Claims

1. a semiconductor substrate having a substrate region of a first conductivity type, a first semiconductor layer of a second conductivity type opposite to the first conductivity type formed on the substrate region, and a second semiconductor layer of the first conductivity type formed on the first semiconductor layer; an isolation region that penetrates the second semiconductor layer and the first semiconductor layer and reaches the substrate region; a cathode region of the second conductivity type of a Zener diode formed in the second semiconductor layer; an anode region of the first conductivity type of the Zener diode formed in the second semiconductor layer; having the anode region includes a first semiconductor region of the first conductivity type formed under the cathode region, and a second semiconductor region of the first conductivity type formed under the first semiconductor region; a first PN junction is formed between the first semiconductor region and the cathode region; A semiconductor device, wherein the second semiconductor region has an impurity concentration higher than an impurity concentration of the first semiconductor region.

2. 2. The semiconductor device according to claim 1, the anode region further includes a third semiconductor region of the first conductivity type covering a side surface of the first semiconductor region, a side surface of the second semiconductor region, and a bottom surface of the second semiconductor region; A semiconductor device, wherein the first semiconductor region has an impurity concentration higher than an impurity concentration of the third semiconductor region.

3. 3. The semiconductor device according to claim 2, the cathode region is disposed adjacent to the first semiconductor region and the third semiconductor region; A second PN junction is formed between the third semiconductor region and the cathode region.

4. 4. The semiconductor device according to claim 3, A semiconductor device, wherein the third semiconductor region has an impurity concentration higher than an impurity concentration of the second semiconductor layer.

5. 4. The semiconductor device according to claim 3, a first plug disposed on the cathode region and electrically connected to the cathode region; a second plug electrically connected to the anode region; The semiconductor device further comprises:

6. 6. The semiconductor device according to claim 5, a first potential is supplied to the cathode region from the first plug; a second potential is supplied to the anode region from the second plug; The first potential and the second potential are lower than a potential of the substrate region.

7. 7. The semiconductor device according to claim 6, The first potential and the second potential are negative potentials.

8. 7. The semiconductor device according to claim 6, The second potential is higher than the first potential.

9. 6. The semiconductor device according to claim 5, further comprising a fourth semiconductor region of the first conductivity type formed in the third semiconductor region; the second plug is disposed on the fourth semiconductor region and is electrically connected to the third semiconductor region via the fourth semiconductor region.

10. 2. The semiconductor device according to claim 1, the cathode region and the anode region are surrounded by the element isolation region.

11. 2. The semiconductor device according to claim 1, A semiconductor device, wherein the potential of the first semiconductor layer is a floating potential.

12. 5. The semiconductor device according to claim 4, a fifth semiconductor region of the first conductivity type formed in the second semiconductor layer and located below the third semiconductor region; A semiconductor device, wherein the fifth semiconductor region has an impurity concentration higher than an impurity concentration of the second semiconductor layer.

13. A method for manufacturing a semiconductor device including a Zener diode, comprising the steps of: (a) providing a semiconductor substrate having a substrate region of a first conductivity type, a first semiconductor layer of a second conductivity type opposite to the first conductivity type formed on the substrate region, and a second semiconductor layer of the first conductivity type formed on the first semiconductor layer; (b) forming an anode region of the first conductivity type of the Zener diode in the second semiconductor layer; (c) forming a cathode region of the second conductivity type of the Zener diode in the second semiconductor layer; having The step (b) comprises: (b1) forming a mask layer on the semiconductor substrate; (b2) after the step (b1), forming a first semiconductor region of the first conductivity type of the anode region in the first semiconductor layer by first ion implantation; (b3) after the step (b1), forming a second semiconductor region of the first conductivity type of the anode region in the first semiconductor layer by a second ion implantation; (b4) removing the mask layer after the steps (b2) and (b3); Including, The implantation energy of the second ion implantation is higher than the implantation energy of the first ion implantation; an impurity concentration of the second semiconductor region is higher than an impurity concentration of the first semiconductor region; After the steps (b2) and (b3), the second semiconductor region is located below the first semiconductor region, a first semiconductor region formed on the first insulating layer and a second insulating layer formed on the second insulating layer, the first semiconductor region being located under the cathode region and a first PN junction being formed between the first semiconductor region and the cathode region,

14. 14. The method of manufacturing a semiconductor device according to claim 13, A method for manufacturing a semiconductor device, wherein a dose of the second ion implantation is greater than a dose of the first ion implantation.

15. 14. The method of manufacturing a semiconductor device according to claim 13, (d) forming an isolation region penetrating the second semiconductor layer and the first semiconductor layer and reaching the substrate region; The method for manufacturing a semiconductor device further comprises:

16. 14. The method of manufacturing a semiconductor device according to claim 13, The step (b) comprises: (b5) forming a third semiconductor region of the first conductivity type of the anode region in the first semiconductor layer by a third ion implantation; Further comprising: the third semiconductor region covers a side surface of the first semiconductor region, a side surface of the second semiconductor region, and a bottom surface of the second semiconductor region; A method for manufacturing a semiconductor device, wherein an impurity concentration of the first semiconductor region is higher than an impurity concentration of the third semiconductor region.

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