Semiconductor device

Abstract

To provide a semiconductor device that does not cause deterioration in isolation characteristics even if transmission lines cross each other.SOLUTION: In a semiconductor device, a first chip 2 on which a first transmission line 8a is arranged is implemented on a chip mounting portion 5 so that a first common terminal 6a faces a first lead row 4A and a first individual terminal 7a faces a second lead row 4B, and a second chip 3 on which a second transmission line 8b is arranged is stacked on the first chip 2 so that a second common terminal 6b faces the first lead row 4A, a second individual terminal 7b faces the second lead row 4B, and the second transmission line 8b is arranged so as not to overlap with the first transmission line 8a; and a metal wire 10 which is connected to the second common terminal 6b and the first transmission line 8a are arranged so as to intersect each other.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that switches the transmission of high-frequency signals between a plurality of input terminals and a plurality of output terminals using a semiconductor switch. [Background technology]

[0002] A wireless communication device such as a mobile phone is equipped with multiple communication systems to enable communication according to multiple communication standards (multimodes). Each communication system is assigned a specific frequency band, and communication is carried out using multiple frequency bands (multibands).

[0003] In such a multi-mode, multi-band wireless communication device, in order to switch the transmission paths between the multiple antennas and the multiple high-frequency circuits, a semiconductor switch is arranged on each transmission line connecting each antenna and each high-frequency circuit. For example, Patent Document 1 discloses a semiconductor device that switches the connection paths between two input terminals and four output terminals. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-69562 A Summary of the Invention [Problem to be solved by the invention]

[0005] 8 is an explanatory diagram of a semiconductor device as a DPDT (Double Pole Double Through) switch. The semiconductor device shown in FIG. 8 is configured to include two common terminals 6, two individual terminals 7, and four semiconductor switches 9 arranged between transmission lines 8 connected to each of the common terminals 6 and each of the individual terminals 7. By configuring the semiconductor device with two individual terminals for two common terminals in this way, it may be possible to reduce the size of the semiconductor device in some cases, and the wiring design of the printed circuit board on which the semiconductor device is mounted may be partially facilitated. On the other hand, in the semiconductor device, the transmission line connected to one common terminal 6 and the semiconductor switch 9 and the transmission line connected to the other common terminal 6 and the semiconductor switch 9 are arranged to cross each other, and an intersection a is generated as shown in FIG. 8.

[0006] Generally, at such intersection point a, capacitance occurs between the upper and lower transmission lines, and through this capacitance, a signal transmitted along one transmission line leaks to the other transmission line, degrading the isolation characteristics.

[0007] Therefore, in order to reduce the capacitance between the transmission lines at the intersection point a, a thick interlayer insulating film is placed between the transmission lines, increasing the distance between the intersecting transmission lines and preventing degradation of the isolation characteristics.

[0008] However, the thickness of the interlayer insulating film is usually at most about 10 μm, and there is a limit to how much the isolation characteristics can be improved.

[0009] SUMMARY OF THE PRESENT EMBODIMENTS An object of the present invention is to provide a semiconductor device in which the isolation characteristics are not deteriorated even if the semiconductor device has a configuration in which transmission lines cross each other. [Means for solving the problem]

[0010] One embodiment of the semiconductor device of the present invention comprises: a mounting section including a chip mounting section, a first lead row including a plurality of lead terminals arranged opposite to each other across the chip mounting section, and a second lead row including a plurality of lead terminals; a first chip including at least one first common terminal, a plurality of first individual terminals, and semiconductor switches respectively arranged between first transmission lines connecting the first common terminal and the first individual terminal; and a second chip including at least one second common terminal, a plurality of second individual terminals, and semiconductor switches respectively arranged between second transmission lines connecting the second common terminal and the second individual terminal, the first chip being arranged such that the first common terminal faces the first lead row and the first individual terminal faces the second lead row. and mounted on the chip mounting portion, the second chip is stacked on the first chip such that the second common terminal faces the first lead row, the second individual terminal faces the second lead row, and the second transmission line does not overlap with the first transmission line, the first common terminal and the second common terminal are connected to the lead terminals of the first lead row by metal wires, the first individual terminals and the second individual terminals are connected to the lead terminals of the second lead row by metal wires, and at least one of the metal wire connecting the second common terminal and the lead terminals of the first lead row or the metal wire connecting the second individual terminal and the lead terminals of the second lead row is arranged to cross the first transmission line arranged on the first chip. Effect of the Invention

[0011] According to the semiconductor device of the present invention, the first chip and the second chip are mounted on the mounting section in an arrangement such that the first transmission line arranged on the first chip and the second transmission line arranged on the second chip do not overlap, and the second transmission line is connected to the lead terminal of the mounting section by a metal wire, so that the metal wires that become the first transmission line and the second transmission line intersect with each other, and the spacing between the transmission lines at the intersection is wider by the thickness of the stacked second chip, thereby improving the isolation characteristics. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is an explanatory diagram of a semiconductor device (embodiment 1) serving as a DPDT switch according to one embodiment of the present invention, illustrating a state in which a first chip is mounted on a mounting portion. [Diagram 2] FIG. 2 is an explanatory diagram of the semiconductor device of the first embodiment, illustrating a state in which a second chip is stacked on the first chip of FIG. [Diagram 3] FIG. 2 is an explanatory diagram of the semiconductor device of embodiment 1, showing a state in which a first chip and a second chip are mounted on a mounting portion, and a common terminal and a lead terminal, and an individual terminal and a lead terminal are each connected by a metal wire. [Figure 4] FIG. 2 is an explanatory diagram of the semiconductor device of the first embodiment, and is a diagram for typically explaining the arrangement of metal wires and a first transmission line. [Diagram 5] FIG. 11 is an explanatory diagram of a semiconductor device (embodiment 2) as a DPDT switch, which is another embodiment of the present invention, showing a state in which a first chip is mounted on a mounting section, and the common terminal and lead terminal, and the individual terminals and lead terminals are each connected by metal wires. [Figure 6] FIG. 6 is an explanatory diagram of a semiconductor device of embodiment 2, illustrating a state in which a second chip is stacked on the first chip in FIG. 5, and the common terminal and lead terminal, and the individual terminal and lead terminal are each connected by a metal wire. [Figure 7] FIG. 11 is an explanatory diagram of a semiconductor device according to a second embodiment, and is a diagram for illustrating a schematic arrangement of metal wires and a first transmission line. [Figure 8] FIG. 1 is an explanatory diagram of a semiconductor device as a DPDT switch. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] The semiconductor device of the present invention will be described with reference to the drawings, but the present invention is not limited to these embodiments, and the members, materials, etc. described below can be modified in various ways within the scope of the present invention. Also, the same reference numerals in the drawings indicate the same or equivalent items, and the size and positional relationship between each component are for convenience and may not strictly reflect the actual situation.

[0014] (Embodiment 1) A first embodiment of the present invention will be described. Figures 1 to 4 are explanatory diagrams of a semiconductor device as a DPDT switch according to the first embodiment of the present invention. First, Figure 1 is an explanatory diagram showing a state in which a first chip 2 is mounted on a mounting section 1 of the semiconductor device of this embodiment. The mounting section 1 is formed of a lead frame, an organic substrate, or the like, and in the example shown in Figure 1, a first lead row 4A formed of two lead terminals 4a and a second lead row 4B formed of two lead terminals 4b are arranged opposite each other with a chip mounting section 5 in between.

[0015] The first chip 2 is mounted on the chip mounting section 5 with an adhesive. The first chip 2 includes one first common terminal 6a, two first individual terminals 7a, and two semiconductor switches 9 arranged between first transmission lines 8a connecting the first common terminal 6a and each of the first individual terminals 7a. The semiconductor switches 9 can be formed of, for example, field effect transistors (FETs). In this embodiment, as shown in FIG. 1, the first common terminal 6a is arranged facing the first lead row 4A formed of the lead terminals 4a, and the two first individual terminals 7a are arranged facing the second lead row 4B formed of the lead terminals 4b, and the first chip 2 is mounted on the chip mounting section 5.

[0016] FIG. 2 is an explanatory diagram showing a state in which the second chip 3 is adhered and stacked on the first chip 2 mounted on the mounting section 1 of the semiconductor device of this embodiment by an adhesive. As shown in FIG. 2, in the semiconductor device of this embodiment, the second chip 3 is stacked on the first chip 2 with the first common terminal 6a, the first individual terminal 7a, and the first transmission line 8a of the first chip 2 exposed. The second chip 3 is configured to include one second common terminal 6b, two second individual terminals 7b, and two semiconductor switches 9 arranged between the second transmission lines 8b connecting the second common terminal 6b and each second individual terminal 7b. In this embodiment, as shown in FIG. 2, the second chip 3 has one second common terminal 6b arranged opposite the first lead row 4A consisting of the lead terminals 4a, and two second individual terminals 7b arranged opposite the second lead row 4B consisting of the lead terminals 4b. Furthermore, the second chip 3 is stacked on the first chip 2 so as not to overlap the first transmission line 8a, and the first transmission line 8a arranged on the first chip 2 and the second transmission line 8b arranged on the second chip 3 are arranged so as not to overlap.

[0017] FIG. 3 is an explanatory diagram showing a state in which the first common terminal 6a and the lead terminal 4a, the second common terminal 6b and the lead terminal 4a, the first individual terminal 7a and the lead terminal 4b, and the second individual terminal 7b and the lead terminal 4b of the semiconductor device of the present embodiment shown in FIG. 2 are connected by metal wires 10. As shown in FIG. 3, the first common terminal 6a of the first chip 2 is connected to one lead terminal 4a of the first lead row 4A by the metal wire 10. Also, the first individual terminal 7a of the first chip 2 is connected to each lead terminal 4b of the second lead row 4B by the metal wire 10. On the other hand, the second common terminal 6b of the second chip 3 is connected to one lead terminal 4a that is not connected to the first common terminal 6a of the first lead row 4A by the metal wire 10. Also, the second individual terminal 7b of the second chip 3 is connected to each lead terminal 4b of the second lead row 4B by the metal wire 10. By connecting in this manner, a semiconductor device is configured in which the four semiconductor switches 9 can switch between the transmission of high-frequency signals between the common terminal as two input / output terminals and the individual terminals as two input / output terminals.

[0018] As shown in FIG. 3, in the semiconductor device of this embodiment, the metal wire 10 connecting the second common terminal 6b and the lead terminal 4a and the first transmission line 8a arranged on the first chip 2 are arranged to cross each other, and an intersection A occurs in a plan view. FIG. 4 is a diagram for explaining the arrangement of the metal wire 10 and the first transmission line 8a connecting the second common terminal 6b and the lead terminal 4a of the semiconductor device of this embodiment shown in FIG. 3. As shown in FIG. 4, the first transmission line 8a arranged on the first chip 2 and the metal wire 10 cross each other at a distance exceeding the thickness of the second chip 3. The thickness of the second chip 3 including the semiconductor switch is, for example, about 100 μm to 260 μm, and it can be seen that the intersection A between the first transmission line 8a and the metal wire 10 in a plan view has a large distance that exceeds the thickness of the second chip 3 in the height direction of the semiconductor device.

[0019] As described above, the semiconductor device of this embodiment has a configuration in which the transmission lines (specifically, the first transmission line 8a and the metal wire 10) cross at a large interval, so that signals do not leak between the transmission lines, resulting in a semiconductor device with excellent isolation characteristics. In addition, in the semiconductor device of this embodiment, the second chip 3 is not disposed on the first transmission line 8a disposed on the first chip 2, so that the first individual terminals 7a are exposed, and as a result, the second individual terminals 7b are disposed separately from the first individual terminals 7a, respectively, which has the advantage that the connections between the individual terminals and the lead terminals 4b by the metal wires 10 can be easily formed.

[0020] (Embodiment 2) Next, a second embodiment of the present invention will be described. FIGS. 5 to 7 are explanatory diagrams of a semiconductor device as a DPDT switch according to the second embodiment of the present invention. The semiconductor device described in the first embodiment above has been described as being smaller in size than the first chip 2, but the semiconductor device of the present invention is not limited to this. For example, the first chip 2 and the second chip 3 may be the same in size. FIG. 5 is an explanatory diagram showing a state in which the first chip 2 is mounted on the mounting section 1 of the semiconductor device of this embodiment, and the first common terminal 6a and the lead terminal 4a, and the first individual terminal 7a and the lead terminal 4b are connected by metal wires 10. The mounting section 1 is made of a lead frame, an organic substrate, or the like, and in the example shown in FIG. 5, a first lead row 4A made of two lead terminals 4a and a second lead row 4B made of two lead terminals 4b are arranged opposite each other across the chip mounting section 5.

[0021] The first chip 2 is mounted on the chip mounting section 5 with an adhesive. The first chip 2 is configured to include one first common terminal 6a, two first individual terminals 7a, and two semiconductor switches 9 arranged between first transmission lines 8a connecting the first common terminal 6a and each of the first individual terminals 7a. In this embodiment, as shown in FIG. 5, the first common terminal 6a is arranged facing the first lead row 4A consisting of the lead terminals 4a, and the two first individual terminals 7a are arranged facing the second lead row 4B consisting of the lead terminals 4b, and the first chip 2 is mounted on the chip mounting section 5. In the semiconductor device of this embodiment, a second chip 3A of the same size is stacked on the first chip 2, and the first common terminal 6a and the first individual terminals 7a are covered by the second chip 3A and are not exposed. Therefore, before the second chip 3A is stacked, the first common terminal 6a of the first chip 2 is connected to one lead terminal 4a of the first lead row 4A by a metal wire 10, and the first individual terminals 7a are connected to each of the lead terminals 4b of the second lead row 4B by metal wires 10.

[0022] 6 is an explanatory diagram showing a state in which the second chip 3A is adhered and laminated by an adhesive onto the first chip 2 mounted on the mounting section 1 of the semiconductor device of this embodiment, and the second common terminal 6b and the lead terminal 4a, and the second individual terminal 7b and the lead terminal 4b are connected by metal wires 10. In the semiconductor device of this embodiment, the second chip 3A is laminated on the first chip 2 to which the connection is formed by the metal wires 10. For example, a wire-embedded film-like adhesive is used as the adhesive for laminating the second chip 3A on the first chip 2. As an example of this wire-embedded film-like adhesive, a wire-embedded die attach film can be used.

[0023] As shown in Fig. 6, the second chip 3A is configured to include one second common terminal 6b, two second individual terminals 7b, and two semiconductor switches 9 arranged between second transmission lines 8b connecting the second common terminal 6b and each second individual terminal 7b. In this embodiment, as shown in Fig. 6, one second common terminal 6b is arranged facing the first lead row 4A consisting of the lead terminals 4a, and two second individual terminals 7b are arranged facing the second lead row 4B consisting of the lead terminals 4b, and the second chip 3A is stacked on the first chip 2 described in Fig. 5. In addition, the first transmission line 8a arranged on the first chip 2 and the second transmission line 8b arranged on the second chip 3A are arranged so as not to overlap.

[0024] The second common terminal 6b of the second chip 3A is connected to one lead terminal 4a that is not connected to the first common terminal 6a of the first lead row 4A by a metal wire 10. Also, the second individual terminals 7b of the second chip 3A are connected to each of the lead terminals 4b of the second lead row 4B by metal wires 10. By making such connections, a semiconductor device is configured in which the transmission of high-frequency signals between the common terminal as two input / output terminals and the individual terminals as two input / output terminals can be switched by four semiconductor switches 9.

[0025] FIG. 7 is a diagram for explaining the arrangement of the metal wire 10 and the first transmission line 8a connecting the second common terminal 6b and the lead terminal 4a of the semiconductor device of this embodiment shown in FIG. 6. As shown in FIG. 7, the first transmission line 8a and the metal wire 10 arranged on the first chip 2 cross each other at a distance exceeding the thickness of the second chip 3A. It can be seen that the thickness of the second chip 3A including the semiconductor switch is, for example, about 100 μm to 260 μm, and the first transmission line 8a and the metal wire 10 are configured to have a large distance in the height direction of the semiconductor device that exceeds the thickness of the second chip 3A. Note that FIG. 7 also shows the metal wire 10 connecting the first individual terminal 7a and the lead terminal 4b of the first chip 2, and the wire-embedded film-like adhesive 11.

[0026] In the semiconductor device of this embodiment, the second chip 3A and the like are arranged between the first transmission line 8a and the metal wire 10 arranged on the first chip 2. In this case, the effect of improving the isolation characteristics may be lower than that of the semiconductor device described in the above embodiment 1. Therefore, in order to show that the isolation characteristics of the semiconductor device of this embodiment are improved compared to the semiconductor device in which the transmission lines 8 cross each other with an interlayer insulating film shown in FIG. 8, their isolation characteristics were compared. First, the semiconductor device of this embodiment is configured to be made of gallium arsenide (relative dielectric constant 13) and to have a second chip 3A with a thickness of 130 μm. The semiconductor device of the configuration shown in FIG. 8 is configured to have an interlayer insulating film made of polyimide (relative dielectric constant 4) with a thickness of 10 μm arranged between the transmission lines 8. As a result of simulating the isolation characteristics for each, at a frequency of 7 GHz, the isolation characteristics of the semiconductor device shown in FIG. 8 were 34.0 dB, while the isolation characteristics of the semiconductor device of this embodiment were 40.1 dB, confirming the improvement of the isolation characteristics.

[0027] As described above, the semiconductor device of this embodiment also has a configuration in which the transmission lines (specifically, the first transmission path 8a and the metal wire 10) cross at a large interval, so that signals do not leak between the transmission lines, resulting in a semiconductor device with excellent isolation characteristics. Furthermore, in the semiconductor device of this embodiment, the second chip 3 can be disposed on the first transmission line 8a disposed on the first chip 2, and another circuit constituting a high-frequency circuit connected to the semiconductor device of this embodiment can also be mounted, making it possible to miniaturize the entire device including the semiconductor device.

[0028] Although the embodiment of the semiconductor device of the present invention has been described above as a DPDT switch, it goes without saying that the present invention is not limited to the above embodiment. For example, in the above description, the intersection between the transmission lines connected to the common terminal has been described, but the intersection structure of the present invention can also be applied to the intersection between the transmission lines connected to the individual terminals. In addition, the first chip 2 and the second chip 3, 3A can be configured to be different from each other, for example, the number of common terminals, the number of individual terminals, and the number of semiconductor switches can be configured to be different. Furthermore, the number of chips to be stacked may be three or more, and the transmission lines arranged in the lower chip and the metal wires connecting the upper chip and the lead terminals can be configured to cross each other.

[0029] (summary) (1) One embodiment of the semiconductor device of the present invention comprises: a mounting section including a chip mounting section, a first lead row including a plurality of lead terminals arranged opposite to each other across the chip mounting section, and a second lead row including a plurality of lead terminals; a first chip including at least one first common terminal, a plurality of first individual terminals, and semiconductor switches respectively arranged between first transmission lines connecting the first common terminal and the first individual terminals; and a second chip including at least one second common terminal, a plurality of second individual terminals, and semiconductor switches respectively arranged between second transmission lines connecting the second common terminal and the second individual terminals, the first chip being arranged such that the first common terminal faces the first lead row and the first individual terminals face the second lead row. the second chip is stacked on the first chip such that the second common terminal faces the first lead row, the second individual terminal faces the second lead row, and the second transmission line does not overlap the first transmission line, the first common terminal and the second common terminal are connected to the lead terminals of the first lead row by metal wires, the first individual terminals and the second individual terminals are connected to the lead terminals of the second lead row by metal wires, and at least one of the metal wire connecting the second common terminal and the lead terminals of the first lead row or the metal wire connecting the second individual terminal and the lead terminals of the second lead row is arranged to cross the first transmission line arranged on the first chip.

[0030] According to the semiconductor device of (1) above, the transmission lines (specifically, the first transmission path 8a and the metal wire 10) are configured to cross with a large gap between them, so that signals do not leak between the transmission lines, resulting in a semiconductor device with excellent isolation characteristics.

[0031] (2) According to still another embodiment, in the semiconductor device of (1) above, the second chip is stacked on the first chip so as not to overlap the first transmission line.

[0032] According to the semiconductor device of (2) above, the second chip is not present on the first transmission line, resulting in a semiconductor device with better isolation characteristics.

[0033] (3) According to still another embodiment, in the semiconductor device of (1) above, the second chip is disposed so as to cover the first transmission line and is stacked on the first chip.

[0034] According to the semiconductor device of (3) above, another circuit constituting a high-frequency circuit can be mounted on the second chip, and the entire device including the semiconductor device can be miniaturized. [Explanation of symbols]

[0035] 1 Mounting section 2. First Chip 3. 3A second chip 4A 1st lead column 4B 2nd lead column 4a, 4b Lead terminals 5 Chip mounting area 6 Common Terminal 6a First common terminal 6b Second common terminal 7 individual terminals 7a 1st individual terminal 7b 2nd individual terminal 8 Transmission Lines 8a First transmission line 8b Second transmission line 9. Semiconductor Switches 10 Metal Wire 11 Film-type adhesive

Claims

1. a mounting section including a chip mounting section, and a first lead row including a plurality of lead terminals and a second lead row including a plurality of lead terminals, the first lead row and the second lead row being arranged opposite each other with the chip mounting section therebetween; a first chip including at least one first common terminal, a plurality of first individual terminals, and semiconductor switches respectively disposed between first transmission lines connecting the first common terminal and the first individual terminals; a second chip including at least one second common terminal, a plurality of second individual terminals, and semiconductor switches respectively disposed between second transmission lines connecting the second common terminal and the second individual terminals; the first chip is mounted on the chip mounting portion such that the first common terminal faces the first lead row and the first individual terminal faces the second lead row; the second chip is stacked on the first chip such that the second common terminal faces the first lead row, the second individual terminal faces the second lead row, and the second transmission line does not overlap the first transmission line; the first common terminal and the second common terminal are connected to the lead terminals of the first lead row by metal wires, the first individual terminal and the second individual terminal are connected to lead terminals of the second lead row by metal wires, At least one of a metal wire connecting the second common terminal and a lead terminal of the first lead row and a metal wire connecting the second individual terminal and a lead terminal of the second lead row is disposed so as to intersect with the first transmission line disposed on the first chip. Semiconductor device.

2. the second chip is arranged so as not to overlap the first transmission line and is stacked on the first chip; The semiconductor device according to claim 1.

3. the second chip is disposed so as to cover the first transmission line and is stacked on the first chip; The semiconductor device according to claim 1.

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