Photoelectric conversion device

Abstract

To reduce power consumption while ensuring a wide dynamic range.SOLUTION: A photoelectric conversion device includes: a photodiode that performs avalanche multiplication in response to incidence of photons; a pulse generation circuit that outputs a first control signal for controlling the photodiode to be in a standby state or a recharge state, and a second control signal for controlling a timing of photon detection; and a control circuit that controls the photodiode on the basis of the first control signal. The present technology can be applied to an imaging element.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present technology relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device capable of reducing power consumption while ensuring a wide dynamic range. [Background technology]

[0002] 2. Description of the Related Art Conventionally, photoelectric conversion devices are known that capture images by using an avalanche photodiode and counting incident photons.

[0003] As a technique related to such a photoelectric conversion device, a technique has been proposed in which the dynamic range of the detected luminance is expanded by changing the recharge cycle during the exposure period, that is, by performing recharge at a number of different cycles (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2022-106660 A Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, in a photoelectric conversion device using an avalanche photodiode, a large negative bias must be applied to the avalanche photodiode, and so the power consumption during recharging is large.

[0006] In the technology described in Patent Document 1, if avalanche multiplication occurs during each period in the standby state after recharging the avalanche photodiode, it is necessary to recharge it each time. This increases the number of recharges, resulting in a large amount of power consumption for recharging the avalanche photodiode, i.e., charging the cathode.

[0007] The present technology has been made in consideration of such circumstances, and makes it possible to reduce power consumption while ensuring a wide dynamic range. [Means for solving the problem]

[0008] A photoelectric conversion device according to one aspect of the present technology includes a photodiode that performs avalanche multiplication in response to incidence of photons, a pulse generating circuit that outputs a first control signal for controlling whether the photodiode is in a standby state or a recharge state and a second control signal for controlling a detection timing of the photon, and a control circuit that controls the photodiode based on the first control signal.

[0009] In one aspect of the present technology, there is provided a photodiode that performs avalanche multiplication in response to incidence of photons, a pulse generating circuit that outputs a first control signal for controlling whether the photodiode is in a standby state or a recharge state and a second control signal for controlling a detection timing of the photon, and a control circuit that controls the photodiode based on the first control signal. [Brief description of the drawings]

[0010] [Figure 1] FIG. 4 is a diagram illustrating a configuration example of a detection circuit. [Diagram 2] FIG. 11 is a diagram illustrating an example of driving the detection circuit. [Diagram 3] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 4] FIG. 11 is a diagram illustrating an example of driving the photoelectric conversion device. [Diagram 5] FIG. 1 is a diagram illustrating an expansion of a dynamic range. [Figure 6] FIG. 11 is a diagram illustrating an example of driving the photoelectric conversion device. [Figure 7] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 8] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 9]FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 10] FIG. 11 is a diagram illustrating an example of driving the photoelectric conversion device. [Figure 11] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 12] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 13] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 14] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 15] FIG. 11 is a diagram illustrating an example of driving the photoelectric conversion device. [Figure 16] FIG. 4 is a diagram illustrating generation of a control signal. [Figure 17] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 18] FIG. 11 is a diagram illustrating an example of driving the photoelectric conversion device. [Figure 19] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 20] FIG. 11 is a diagram illustrating an example of driving the photoelectric conversion device. [Figure 21] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 22] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Diagram 23] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 24] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Diagram 25] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Figure 26] FIG. 13 is a diagram illustrating an example of the arrangement of a pulse generating circuit. [Figure 27] FIG. 13 is a diagram illustrating an example of the arrangement of a pulse generating circuit. [Figure 28] FIG. 2 is a diagram illustrating a layer structure of a photoelectric conversion device. [Figure 29] FIG. 2 is a diagram illustrating a layer structure of a photoelectric conversion device. [Diagram 30] FIG. 2 is a diagram illustrating a layer structure of a photoelectric conversion device. [Diagram 31]FIG. 2 is a diagram illustrating a layer structure of a photoelectric conversion device. [Diagram 32] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Diagram 33] FIG. 1 illustrates an example of the configuration of a photoelectric conversion device. [Diagram 34] FIG. 4 is a diagram illustrating a configuration example of a detection circuit. [Diagram 35] FIG. 11 is a diagram illustrating a count value. [Diagram 36] FIG. 2 is a diagram illustrating a configuration of a detection circuit and a counter. [Figure 37] FIG. 11 is a diagram illustrating a count value. [Figure 38] FIG. 1 illustrates an example of the configuration of an imaging device. [Figure 39] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Diagram 40] 4 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit; FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments to which the present technology is applied will be described with reference to the drawings.

[0012] First embodiment <About photon detection and recharging> The present technology can be applied to a photoelectric conversion device that is an imaging element (image sensor) that uses a photodiode that performs avalanche multiplication, an imaging device that includes such a photoelectric conversion device, and other electronic devices, etc. The imaging device referred to here is, for example, a mobile terminal or surveillance camera that has an imaging function, a camera mounted on a vehicle, etc.

[0013] First, the detection of photons using a photodiode will be described.

[0014] Consider the detection circuit shown in Fig. 1. The detection circuit shown in Fig. 1 is provided, for example, for each pixel of a sensor that captures an image.

[0015] In the detection circuit, a recharge switch made of a pMOS (Metal Oxide Semiconductor) transistor is connected to the cathode side of the photodiode that performs avalanche multiplication. Two inverters are connected in series to the cathode side of the photodiode, and a counter is connected to the output side of these inverters.

[0016] In the detection circuit, recharging is performed at a predetermined recharge period. That is, an external control signal CK1 that falls at a predetermined period is supplied to the recharge switch, and this causes the cathode of the photodiode to be periodically connected to the power supply VDD.

[0017] When the photodiode is connected to the power supply VDD, the potential VK on the cathode side of the photodiode becomes a potential corresponding to the power supply VDD. In other words, the cathode of the photodiode is charged and recharging is completed. When the photodiode is charged (recharged), the photodiode enters a standby state.

[0018] When a photodiode is in a standby state, avalanche multiplication occurs when a photon is incident on the photodiode.

[0019] Then, the potential VK on the cathode side of the photodiode drops, and the level that becomes the input to the counter, that is, the potential OUT, becomes L level (low level). Then, when the potential OUT becomes H level (high level) at the next recharge timing, the count value held in the counter is incremented by 1.

[0020] In this way, by periodically recharging the cathode after avalanche multiplication using the external control signal CK1, it is possible to detect whether one or more photons have reached (entered) the photodiode during each of multiple detection periods.

[0021] This makes it possible to extract the number of times that one or more photons are detected to be incident during an exposure period, such as one frame of an image, that includes multiple detection periods, as a pulse. Therefore, it becomes possible to predict the brightness of a pixel in an image from the extracted pulse (number of times) and the Poisson distribution probability that one or more photons will arrive during the detection period.

[0022] By driving the detection circuit as described above, for example as shown in FIG. 2, and performing multiple recharges during the exposure period by combining two different recharge periods τ0+τ1 and τ0, it is possible to expand the dynamic range of the detected brightness.

[0023] In Figure 2, the horizontal direction indicates time, and the vertical direction indicates level (electric potential). For example, in the figure, an upward convex section indicates an H level section, and a downward convex section indicates an L level section.

[0024] In addition, the arrow in the row marked with the letter "photon" indicates that a photon has been incident on the photodiode, the broken line in the row marked with the letter "VK" indicates the electric potential VK, and the broken line in the row marked with the letter "CK1" represents the waveform of the external control signal CK1.

[0025] The broken line in the row marked with the letters "OUT" indicates the potential OUT, and each numerical value in the row marked with the letters "Counter" indicates the count value held in the counter.

[0026] In this example, recharging is performed when the external control signal CK1 falls, that is, when the signal goes to L level.

[0027] Therefore, it can be seen that recharge is performed alternately at recharge periods τ0+τ1 and τ0 during a given exposure period.

[0028] In particular, here τ0+τ1 and τ0 represent the length of the period in which recharges are performed, and the period between recharges is the detection period for photons. Therefore, in this example, the length of the detection period is alternately τ0+τ1 and τ0.

[0029] When such driving is performed, the expected count value N of the counter after the end of the exposure period is count is expressed as the following equation (1).

[0030]

number

[0031] In addition, in formula (1), N τ0 indicates the number of times recharge was performed at the recharge period τ0 during the exposure period (number of recharges), and N τ0+τ1 indicates the number of times recharge was performed at the recharge period τ0+τ1 during the exposure period. Also, f indicates the frequency of the photons incident on the photodiode.

[0032] In equation (1), "1-e -fτ0 " represents the probability that one or more photons will arrive during the detection period of length τ0, and "1-e -f(τ0+τ1) " represents the probability that one or more photons arrive during the detection period of length τ0 + τ1.

[0033] In addition, as shown in the following formula (2), the number of recharges N τ0 and recharge count N τ0+τ1 The sum of these is the maximum number of recharges during the exposure period, N rcg It becomes.

[0034]

number

[0035] Incidentally, it is known that a large negative bias must be applied to a photodiode that performs avalanche multiplication, and therefore a large amount of power is required for recharging.

[0036] In the detection circuit shown in Fig. 1, it is possible to expand the dynamic range of the detected brightness, i.e., the dynamic range of the captured image, but it is necessary to perform recharge each time at the recharge period τ0+τ1 and the recharge period τ0, which results in a large amount of power consumption when charging the cathode of the photodiode.

[0037] Also, to expand the dynamic range to the high illuminance side, it is necessary to shorten the pulse width (pulse interval) of the external control signal CK1 for recharging, but this increases the IR drop when combined with a short-period pulse. This can cause the power supply VDD voltage to drop, which can change the sensitivity of the photodiode.

[0038] Therefore, in this technology, in a photoelectric conversion device, which is an image sensor that operates to expand the dynamic range by using a detection cycle of multiple photons, it is possible to detect whether a photon has arrived (arrived) in the middle of the first cycle in which photon detection is performed.

[0039] This makes it possible to achieve the same effect as in the case of multiple-cycle drive, which combines a first cycle and a second cycle that is shorter than the first cycle, with one recharge. In other words, it is possible to secure a dynamic range on the high-luminance side by combining a short period as the photon detection period.

[0040] According to the present technology, it is possible to reduce the number of recharges and reduce power consumption while ensuring a wide dynamic range.

[0041] In particular, this technology makes it possible to obtain (set) a short period as the photon detection period without recharging, so it is possible to obtain information on the higher luminance side.In addition, since this technology can obtain information on the higher luminance side, it is possible to ensure the dynamic range and SNR (Signal to Noise Ratio) on the higher luminance side.

[0042] <Configuration Example of Photoelectric Conversion Device> FIG. 3 is a diagram showing an example of the configuration of an embodiment of a photoelectric conversion device to which the present technology is applied.

[0043] The photoelectric conversion device 11 shown in Fig. 3 is composed of an imaging element such as an image sensor that captures an image. For ease of explanation, Fig. 3 shows a configuration corresponding to one pixel in the photoelectric conversion device 11.

[0044] The photoelectric conversion device 11 includes a pulse generating circuit 21 and a detecting circuit 22 .

[0045] For example, the detection circuit 22 is provided for each pixel, and the detection circuit 22 includes a photodiode 31, a switch 32, an inverter 33, a NAND gate 34, and a counter 35.

[0046] The pulse generating circuit 21 generates the control signals CK1 and CK2, which are pulse signals, and supplies (outputs) the control signals CK1 and CK2 to the detection circuit 22.

[0047] Here, the control signal CK1 is a signal for controlling the recharging of the photodiode 31, and the control signal CK2 is a signal for controlling the detection timing of photons.

[0048] The photodiode 31 performs avalanche multiplication in response to the incidence of photons.

[0049] For example, the photodiode 31 may be a single photon avalanche diode (SPAD) that detects a single photon, or an avalanche photodiode (APD) that detects a plurality of photons.

[0050] The switch 32 is made of a pMOS transistor, and is disposed between a predetermined power supply VDD and the cathode of the photodiode 31. A control signal CK1 is supplied from the pulse generating circuit 21 to the gate (gate electrode) of the switch 32.

[0051] The switch 32 controls the connection of the photodiode 31 to the power supply VDD by turning on or off in response to a control signal CK1 from the pulse generating circuit 21, that is, by becoming conductive or non-conductive.

[0052] In other words, the switch 32 functions as a control circuit that controls whether the photodiode 31 is in a standby state or a recharge state by controlling the connection between the photodiode 31 and the power supply VDD in response to the control signal CK1.

[0053] Specifically, when the switch 32 is turned on (conductive), the cathode of the photodiode 31 is connected to the power supply VDD, and the photodiode 31 is in a recharge state. In the recharge state, the potential VK of the cathode of the photodiode 31 becomes a potential corresponding to the power supply VDD, and the cathode is charged (recharged).

[0054] On the other hand, when the switch 32 is turned off (non-conducting) after the start of recharging, the cathode of the photodiode 31 is disconnected from the power supply VDD, recharging is completed, and the device enters a standby state. In the standby state, it is possible to detect photons incident on the photodiode 31.

[0055] An input terminal of an inverter 33 is connected between the cathode of the photodiode 31 and the switch 32. The level of the output terminal side of the inverter 33, that is, the potential P1, changes according to the potential VK on the cathode side of the photodiode 31.

[0056] For example, when a photon is incident (reaches) on the photodiode 31 while the photodiode 31 is in a standby state, avalanche multiplication occurs in the photodiode 31, and the potential VK drops, so that the potential P1 becomes H level. In other words, when avalanche multiplication occurs in the photodiode 31, the inverter 33 outputs a pulse signal.

[0057] Such an inverter 33 can be said to function as a first detection circuit that detects avalanche multiplication in the photodiode 31, that is, a first detection circuit that outputs a pulse signal when avalanche multiplication occurs.

[0058] One input terminal of the NAND gate 34 is connected to the output terminal of the inverter 33, the other input terminal of the NAND gate 34 is connected to the pulse generating circuit 21, and the output terminal of the NAND gate 34 is connected to the counter 35.

[0059] The pulse generating circuit 21 supplies the NAND gate 34 with a control signal CK2 for controlling the timing of photon detection in the photodiode 31, that is, for switching the length of the photon detection period (detection cycle).

[0060] The level of the output terminal of the NAND gate 34, that is, the potential OUT, changes in response to the control signal CK2 and the potential P1 which are input to the NAND gate 34.

[0061] In other words, the NAND gate 34 functions as a second detection circuit that distinguishes and detects the incidence of photons, i.e., avalanche multiplication, during a plurality of periods of different lengths by generating and outputting a pulse signal according to the control signal CK2 and the potential P1 (pulse signal).

[0062] For example, the NAND gate 34 distinguishes between avalanche multiplication occurring within a first period included in the recharge cycle of the photodiode 31 and avalanche multiplication occurring within a second period, and generates and outputs a pulse signal according to the detection result. The potential OUT on the output terminal side of the NAND gate 34 changes due to this pulse signal.

[0063] The first and second periods referred to here are counting periods τ0 and τ1, respectively, which will be described later.

[0064] The counter 35 is a counter circuit connected to the output terminal of the NAND gate 34 , and performs a counting operation in response to the potential OUT on the output terminal side of the NAND gate 34 , that is, the pulse signal output from the NAND gate 34 .

[0065] In other words, the counter 35 counts the number of pulse signals output from the NAND gate 34, that is, the number of pulses in the pulse signal, and holds a count value that is the count result.

[0066] This count value corresponds to the number of pulses output from the second detection circuit when photons are incident on the photodiode 31 during an exposure period T for capturing an image for one frame, for example, i.e., the brightness of the pixel of the captured image.

[0067] <Example of driving a photoelectric conversion device> Next, with reference to FIG. 4, a driving example of the photoelectric conversion device 11 shown in FIG. 3 will be described.

[0068] 4, the horizontal direction indicates time, and the vertical direction indicates level (electric potential). The arrows in the row marked with the word "photon" indicate that a photon has been incident on the photodiode 31, and the numerical values ​​in the row marked with the word "counter" indicate the count values ​​held in the counter 35.

[0069] The broken lines L11 to L15 represent the potential VK, the control signal CK1, the potential P1, the control signal CK2, and the potential OUT.

[0070] For example, when the control signal CK1 is set to the L level at time t1, the switch 32 is turned on, the photodiode 31 is connected to the power supply VDD, and recharging is performed.

[0071] The photodiode 31 goes into a standby state, and a counting period during which photon detection is performed starts. More specifically, when the control signal CK1 goes to an L level and then goes to an H level to end the recharge operation, the photodiode 31 goes into a standby state.

[0072] At time t2, the control signal CK2 is set to L level, and then changes to H level.

[0073] When the control signal CK2 is set to L level at time t2, the count period ends. In this example, the period of length τ0 from time t1 to time t2 is one count period. In the count period, photon detection is performed during the period when the photodiode 31 is in a standby state. The standby period is the period when the control signal CK1 is set to H level and the photodiode 31 is disconnected from the power supply VDD.

[0074] Hereinafter, the count period having a length of τ0 will also be referred to as the count period τ0 in particular. This count period τ0 can be said to be a period having a count cycle of τ0.

[0075] During the period from time t1 to time t2, the potential VK remains high because no photons are incident on the photodiode 31. For example, the potential VK is higher than a predetermined determination threshold value.

[0076] Therefore, the potential P1 output from the inverter 33 remains at the L level, i.e., "0", so the potential OUT output from the NAND gate 34 remains at the H level, i.e., "1", and the count value of the counter 35 also remains at "0". Therefore, it can be seen that no incidence (arrival) of photons was detected during the count period τ0.

[0077] When the count period τ0 ends at time t2, the next count period starts at the same time.

[0078] In this example, at time t3, a photon is incident (flys) on the photodiode 31, causing avalanche multiplication, and thus the potential VK on the cathode side of the photodiode 31 drops. For example, the potential VK is equal to or lower than a predetermined determination threshold value.

[0079] Then, the potential P1 which is the output of the inverter 33 becomes H level, that is, "1", and since the control signal CK2 remains at H level, the potential OUT which is the output of the NAND gate 34 changes to L level, that is, "0".

[0080] Thereafter, when the control signal CK1 is set to the L level at time t4, the count period ends.

[0081] In this example, a period of length τ1 from time t2 to time t4 is regarded as one count period. Hereinafter, a count period of length τ1 will also be referred to as count period τ1 in particular.

[0082] This count period τ1 can be said to be a period in which the count cycle is τ1, and the count cycle τ1 is longer than the count cycle τ0.

[0083] When the control signal CK1 is set to the L level at time t4, the photodiode 31 is recharged in the same manner as at time t1.

[0084] At this time, if a photon is incident on the photodiode 31 in the immediately preceding count period τ1, the count value held in the counter 35 is incremented by one.

[0085] That is, when a recharge operation is performed, the potential VK on the cathode side of the photodiode 31 rises, and the photodiode 31 goes into a standby state.

[0086] Then, potential P1, which is the output of inverter 33, becomes L level, and potential OUT, which is the output of NAND gate 34, changes to H level, causing the count value held by counter 35 to change from "0" to "1." In other words, counter 35 increments the count value it holds by 1.

[0087] In the driving example of FIG. 4, the length of the recharge period is τ0+τ1, and within this recharge period τ0+τ1, two count target periods τ0 and τ1 with different lengths (periods) are included.

[0088] At the same time that the count period τ1 ends at time t4, the count period τ0 starts in the same manner as at time t1.

[0089] In this example, after the count period τ0 starts from time t4, more specifically, after the photodiode 31 is recharged, photons are incident on the photodiode 31, causing avalanche multiplication, and the potential VK on the cathode side of the photodiode 31 drops.

[0090] As a result, the potential P1 goes to H level, and the potential OUT which is the output of the NAND gate 34 goes to L level.

[0091] Therefore, when the control signal CK2 is set to L level at time t5 and the count period τ0 ends, the potential OUT, which is the output of the NAND gate 34, changes to H level, causing the count value of the counter 35 to increase by 1 to “2”.

[0092] Furthermore, thereafter, when the control signal CK2 is returned to the H level, the potential P1 which is the output of the inverter 33 remains at the H level, so that the potential OUT which is the output of the NAND gate 34 changes to the L level.

[0093] During the count period τ1 from time t5, photons were incident during the immediately preceding count period τ0, causing the potential VK to drop, and no recharge has been performed since then, so the potential VK remains low during this count period τ1 regardless of whether photons are incident or not. Therefore, the potential OUT of the NAND gate 34 also remains at the L level.

[0094] Therefore, when the control signal CK1 is set to L level at time t6 to perform recharging and the count period τ1 ends, the potential P1 becomes L level, and the potential OUT of the NAND gate 34 changes to H level. As a result, the count value held by the counter 35 changes from "2" to "3."

[0095] In the driving example of FIG. 4, when a photon is incident during count period τ0, the count value is incremented by 1 at the end of count period τ0, and the count value is incremented by another 1 at the subsequent recharge timing.

[0096] That is, when a photon is incident during count period τ0, the count value increases by 2 regardless of whether a photon is incident during the next count period τ1. This is because when a photon is incident during the relatively short count period τ0, it is highly likely that a photon is also incident during the immediately following, longer count period τ1.

[0097] Thus, in the example of FIG. 4, if a photon is incident during the shorter count period τ0, two counts are performed, and if no photon is incident during the count period τ0 and a photon is incident during the longer count period τ1, one count is performed.

[0098] In this example, during an exposure period T, such as one frame of an image, recharging is performed multiple times in a recharge period τ0+τ1, and photons are detected in multiple count periods within the recharge period τ0+τ1.

[0099] In particular, in the photoelectric conversion device 11, by providing a plurality of different count periods with different lengths during the recharge cycle, it is possible to reduce the number of recharges and reduce power consumption while ensuring a wide dynamic range and SNR. In addition, IR Drop can also be suppressed.

[0100] For example, when the driving shown in FIG. 4 is performed, the relationship between the photon frequency and the count value in the counter 35 becomes as shown in FIG.

[0101] In FIG. 5, the horizontal axis indicates the frequency of photons, and the vertical axis indicates the count value (number of counts).

[0102] Curve L31 shows the relationship between the count value and the photon frequency obtained by the photoelectric conversion device 11. In contrast, curve L32 shows the relationship between the count value and the photon frequency when the photoelectric conversion device has the configuration shown in Fig. 1. That is, curve L32 shows an example where the recharge period is τ0+τ1 and the photon detection period is also τ0+τ1.

[0103] In particular, curves L31 and L32 show the relationship between the count value and the photon frequency when the number of recharges is the same and the length of the exposure period T is also the same, that is, when the conditions are the same.

[0104] Comparing curve L31 and curve L32, it can be seen that the frequency at which the count value becomes constant and stops changing is higher in curve L31 than in curve L32, and that photons of higher frequencies can be detected, i.e., a wider dynamic range can be ensured.

[0105] When driving as described with reference to FIG. 4, the expected count value N of the counter 35 after the end of the exposure period T is count is expressed as the following equation (3).

[0106]

number

[0107] In addition, in formula (3), N τ0+τ1 indicates the number of times recharge was performed at the recharge period τ0+τ1 during the exposure period T (the number of recharges), and f indicates the frequency of photons incident on the photodiode 31 (the input photon frequency).

[0108] In formula (3), "1-e -fτ0 " represents the probability that one or more photons will arrive during the counting period τ0, and "e -fτ0 (1-e -fτ1 )" represents the probability that no photons arrive during counting period τ0, and one or more photons arrive during counting period τ1.

[0109] From equation (3), it can be seen that detecting photons by combining counting period τ0 and counting period τ1 means detecting photons in a detection period τ0+τ1 while at the same time detecting photons in a detection period τ0, which has a different length (period) from the detection period τ0+τ1.

[0110] In addition, as shown in the following formula (4), the maximum number of recharges N during the exposure period T rcg is the number of recharges N τ0+τ1 It becomes.

[0111]

number

[0112] In the subsequent stage of the counter 35, the count value obtained by the counter 35 is countA correction process may be performed to convert the count value into an input photon frequency f corresponding to the actual number of incident photons based on equation (3) as follows: In this case, for example, the pixel value of the pixel of the image is calculated based on the input photon frequency f.

[0113] Comparing equation (3) with the above equation (1), the expected value N count is the number of recharges in Eq. (1) τ0 , N τ0+τ1 It can be seen that this is equivalent to the case where

[0114] In the driving example of FIG. 4, photons are detected in a cycle of τ0+τ1 while at the same time detecting photons in a cycle of τ0, and it can be seen that the dynamic range of detected brightness is expanded.

[0115] Also, in the driving example of Fig. 4, since recharging is performed in a cycle of τ0+τ1, it can be seen that the number of recharges can be reduced. That is, from equations (1) to (4), in the driving example of Fig. 4, when obtaining the same maximum count number as in the case of performing the driving shown in Fig. 2, that is, the maximum value of the count value, the number of recharges is half that of the example of Fig. 2 while ensuring the same dynamic range as in the example of Fig. 2. From this, it can be seen that with this technology, the power consumed by recharging can be reduced by half.

[0116] In addition, in Fig. 4, an example in which the cycles of the control signal CK1 and the control signal CK2 are constant has been described. However, this is not limited to this, and the cycles of the control signal CK1 and the control signal CK2 may be changed. In other words, the length of each of the multiple count target periods provided within the recharge cycle may be changed in a time division manner.

[0117] When the cycles of the control signals CK1 and CK2 change, that is, when the control signals CK1 and CK2 have a plurality of cycles, the photoelectric conversion device 11 is driven as shown in FIG. 6, for example.

[0118] 6, the horizontal direction indicates time, and the vertical direction indicates level (electric potential). The arrow in the row marked with the letter "photon" indicates that a photon is incident on the photodiode 31, the broken line in the row marked with the letter "VK" indicates the electric potential VK, and the broken line in the row marked with the letter "CK1" indicates the waveform of the control signal CK1.

[0119] The broken line in the row marked with the character "P1" indicates the potential P1, and the broken line in the row marked with the character "CK2" indicates the waveform of the control signal CK2. The broken line in the row marked with the character "OUT" indicates the potential OUT, and each numerical value in the row marked with the character "Counter" indicates the count value held in the counter 35.

[0120] 6, the cycle of the control signal CK1 changes from τ0+τ1 to τ2+τ3 during the exposure period T. That is, the recharge cycle changes from τ0+τ1 to τ2+τ3. Accordingly, the cycle of the control signal CK2 changes from τ0+τ1 to τ2+τ3.

[0121] Therefore, within the recharge period τ0+τ1, there are provided a count target period in which the count period is τ0 and a count target period in which the count period is τ1.

[0122] Furthermore, within the recharge cycle τ2+τ3, there are provided a count target period in which the count cycle is τ2 and a count target period in which the count cycle is τ3.

[0123] The count period τ0 to the count period τ3 are periods of different lengths. The driving of the photoelectric conversion device 11 during each recharge period is the same as in FIG.

[0124] In order to widen the dynamic range of the detected brightness, it is effective to combine a plurality of short and long photon detection periods (count periods).

[0125] In addition, in the case of the same luminance, it is possible to thin out the count number. In other words, since the count value is appropriately corrected in the latter stage of the counter 35, it is not necessary to count all photons, and it is possible to provide a relatively long counting period during the exposure period T.

[0126] In this example, the counting period τ2 is shorter than the counting period τ0, and there are a total of four possible combinations of effective photon detection periods: the combination of τ0 and the period τ0+τ1, and the combination of τ2 and the period τ2+τ3. This ensures a wider dynamic range.

[0127] As described above, by dynamically changing the cycles of the control signals CK1 and CK2 in the time direction, it is possible to change the length of the recharge cycle, that is, the length of the count period provided in the period between recharges. In other words, the length of the count period can be changed in a time-division manner.

[0128] In addition, in each embodiment and variant thereof, such as the fourth and fifth embodiments described below, the length of each counting period can be dynamically (time-divisionally) changed, as in the first embodiment.

[0129] First Modification of the First Embodiment <Configuration Example of Photoelectric Conversion Device> Other embodiments and modifications to which the present technology is applied will be described below.

[0130] In the figures described below, parts corresponding to those in Fig. 3 are given the same reference numerals, and their explanations will be omitted as appropriate. In the figures described below, parts corresponding to each other are given the same reference numerals, and their explanations will be omitted as appropriate.

[0131] In the detection circuit 22, the first detection circuit that detects avalanche multiplication can also be a combinational circuit that uses the control signal CK1 and the cathode output of the photodiode 31 as inputs.

[0132] In such a case, the photoelectric conversion device 11 is configured as shown in FIG.

[0133] The photoelectric conversion device 11 shown in Fig. 7 has a configuration in which a logic gate 51 is provided instead of the inverter 33 in the configuration shown in Fig. 3. That is, the logic gate 51 functions as a first detection circuit.

[0134] One input end (hereinafter also referred to as a first input terminal) of the logic gate 51 is connected between the cathode of the photodiode 31 and the switch 32.

[0135] The other input terminal (hereinafter also referred to as the second input terminal) of the logic gate 51 is connected to the pulse generating circuit 21, and a control signal CK1 is supplied (input) from the pulse generating circuit 21 to the second input terminal.

[0136] The output terminal of the logic gate 51 is connected to one input terminal of the NAND gate 34, and a potential P1 on the output side of the logic gate 51 becomes an input to the NAND gate 34.

[0137] The logic gate 51 outputs a pulse signal according to the avalanche multiplication in the photodiode 31 based on the potential VK between the cathode of the photodiode 31 and the logic gate 51, which serves as an input, and a control signal CK1.

[0138] Specifically, the potential P1 on the output side of the logic gate 51 becomes H level, i.e., "1", when the input to the first input terminal (potential VK) is at L level and the input to the second input terminal (control signal CK1) is at H level, and becomes L level, i.e., "0" otherwise.

[0139] Therefore, even if the amount of incident photons is large, such as high illuminance, in the photodiode 31 and the potential VK remains low, i.e., at the L level, when the level of the control signal CK1 changes, the potential P1 also changes, making it possible to generate a pulse as the output of the logic gate 51. This allows the counter 35 to perform a counting operation.

[0140] For example, if the control signal CK1 changes from H level to L level when the potential P1 is at H level and the potential VK is at L level at the end of the second count period within the recharge cycle, the potential P1 will change from H level to L level.

[0141] In this case, for example, if the potential OUT on the output side of the NAND gate 34 is at the L level, as the potential P1 changes to the L level, the potential OUT changes from the L level to the H level, thereby increasing the count value of the counter 35 by 1.

[0142] Second Modification of the First Embodiment <Configuration Example of Photoelectric Conversion Device> Furthermore, when the first detection circuit is a combinational circuit using the control signal CK1 and the cathode output of the photodiode 31 as inputs, it can also have the configuration shown in FIG.

[0143] The configuration of the photoelectric conversion device 11 shown in Figure 8 is configured such that, instead of the inverter 33 in the configuration shown in Figure 3, a NOR gate 71 is provided as a first detection circuit, and an inverter 72 is newly provided between the pulse generating circuit 21 and the switch 32.

[0144] In this example, the control signal CK1 output from the pulse generating circuit 21 is inverted by an inverter 72 and then input to the switch 32.

[0145] One input terminal of the NOR gate 71 is connected between the cathode of the photodiode 31 and the switch 32. The other input terminal of the NOR gate 71 is connected to the pulse generating circuit 21, and a control signal CK1 is supplied from the pulse generating circuit 21 to the other input terminal.

[0146] The output terminal of the NOR gate 71 is connected to one input terminal of the NAND gate 34, and a potential P1 on the output side of the NOR gate 71 becomes an input to the NAND gate 34.

[0147] In this example, when a photon is incident on the photodiode 31 and the potential VK becomes the L level, the potential P1 changes to the H level at the timing when the control signal CK1 becomes the L level.

[0148] In the example of Fig. 8, in response to the incidence of photons on the photodiode 31, the counter 35 counts in a manner similar to that of Fig. 3. Moreover, as in the case of Fig. 7, even if the potential VK remains low, a pulse can be generated as the output of the NOR gate 71.

[0149] 3, when the potential VK is an intermediate potential, the clock of the control signal CK1 may cause a through current to flow through the inverter 33. In contrast, in the configuration shown in Fig. 8, the potential VK is directly connected to the NOR gate 71, so that no through current flows through the NOR gate 71 even when the potential VK becomes an intermediate potential.

[0150] Third Modification of the First Embodiment <Configuration Example of Photoelectric Conversion Device> In order to shorten the period during which the photodiode 31 is recharged, the photoelectric conversion device 11 may be configured as shown in FIG.

[0151] The configuration of the photoelectric conversion device 11 shown in Figure 9 is configured such that, instead of the inverter 33 in the configuration shown in Figure 3, a logic gate 91 is provided as a first detection circuit, and a switch 92 is newly provided between the photodiode 31 and the switch 32.

[0152] The switch 92 is made of a pMOS transistor, and is disposed between the switch 32 and the cathode of the photodiode 31. A control signal CK2 is supplied from the pulse generating circuit 21 to the gate (gate electrode) of the switch 92.

[0153] Like the control signal CK1 supplied to the switch 32, this control signal CK2 is a signal for controlling the recharging of the photodiode 31, that is, a signal for controlling the connection between the photodiode 31 and the power supply VDD.

[0154] In this example, a control circuit that controls whether the photodiode 31 is in a standby state or a recharge state is configured by two switches, a switch 32 and a switch 92. That is, the control circuit has a switch 32 that is disposed between the photodiode 31 and a power supply VDD and turns on or off in response to a control signal CK1, and a switch 92 that is disposed between the photodiode 31 and the switch 32 and turns on or off in response to a control signal CK2 that is different from the control signal CK1.

[0155] One input end (hereinafter also referred to as a first input terminal) of the logic gate 91 is connected between the cathode of the photodiode 31 and the switch 92 .

[0156] The other input terminal (hereinafter also referred to as the second input terminal) of the logic gate 91 is connected to the pulse generating circuit 21, and a control signal CK1 is supplied (input) from the pulse generating circuit 21 to the second input terminal.

[0157] The output terminal of the logic gate 91 is connected to one input terminal of the NAND gate 34, and a potential P1 on the output side of the logic gate 91 becomes an input to the NAND gate 34.

[0158] A potential P1 on the output side of logic gate 91 is at H level, i.e., "1", when the input to the first input terminal (potential VK) is at L level and the input to the second input terminal (control signal CK1) is at H level, and is at L level, i.e., "0" in other cases. Logic gate 91 operates in the same manner as logic gate 51 shown in FIG.

[0159] One input terminal of the NAND gate 34 is connected to the output terminal of the logic gate 91 , and the other input terminal of the NAND gate 34 is connected to the pulse generating circuit 21 .

[0160] A control signal CK3 for controlling the timing of photon detection by the photodiode 31 is supplied to the NAND gate 34 from the pulse generating circuit 21. This control signal CK3 corresponds to the control signal CK2 supplied to the NAND gate 34 in the configuration shown in FIG.

[0161] In this example, the control signals CK1 and CK2 are combined to shift the timing at which the switch 32 is turned on and off from the timing at which the switch 92 is turned on and off, thereby achieving recharging in a short time.

[0162] In particular, by combining the control signal CK1 and the control signal CK2, it is not necessary to narrow the pulse width of the control signal CK1 and the control signal CK2. Therefore, even if the wiring for the control signal CK1 and the control signal CK2 is long and the impedance is high, the output (waveform) of the control signal CK1 and the control signal CK2 is less likely to be crushed, and recharging in a short time can be achieved.

[0163] FIG. 10 shows an example of driving the photoelectric conversion device 11 shown in FIG.

[0164] 10, the horizontal direction indicates time, and the vertical direction indicates level (electric potential). The arrows in the row marked with the word "photon" indicate that a photon has been incident on the photodiode 31, and the numerical values ​​in the row marked with the word "counter" indicate the count values ​​held in the counter 35.

[0165] The broken lines L61 to L66 represent the potential VK, the control signal CK1, the control signal CK2, the potential P1, the control signal CK3, and the potential OUT.

[0166] In this example, recharging of the photodiode 31 starts when the control signal CK2 is at L level and the control signal CK1 falls, i.e., when it becomes L level. Recharging of the photodiode 31 ends when the control signal CK1 is at L level and the control signal CK2 rises, i.e., when it becomes H level.

[0167] In FIG. 10, the recharge cycle of the photodiode 31 is τ0+τ1, and the timing at which the control signal CK3 falls during that recharge cycle is the timing at which the count period switches.

[0168] Specifically, the period from the recharge start time to the time the control signal CK3 falls is set as a shorter count target period τ0, and the period from the time the control signal CK3 falls to the next recharge start time is set as a longer count target period τ1.

[0169] In this case, similarly to the case in FIG. 4, the counter 35 counts twice if a photon is incident during the count period τ0, and counts once if a photon is incident during the count period τ1.

[0170] 7, in this example, even if photons are incident on the photodiode 31 at the timing of recharge and the potential VK remains low, the potential P1 also changes when the level of the control signal CK1 changes, so it is possible to generate a pulse as the output (potential P1) of the logic gate 91. This allows the counter 35 to perform a counting operation.

[0171] Fourth Modification of the First Embodiment <Configuration Example of Photoelectric Conversion Device> By configuring the photoelectric conversion device 11 as shown in FIG. 11, for example, it is possible to reduce the amplitude of the control signal CK1 and the like.

[0172] The configuration of the photoelectric conversion device 11 shown in FIG. 11 is configured such that a bias generating circuit 111 and a clamp transistor 112 are newly provided in addition to the configuration shown in FIG.

[0173] In this example, a clamp transistor 112 is provided between the switch 92 and the cathode of the photodiode 31. In particular, the switch 92 and the switch 32 are connected to the source side of the clamp transistor 112.

[0174] For example, the clamp transistor 112 is a thick-film pMOS transistor. That is, the thickness of the gate electrode of the clamp transistor 112 is thicker than the thickness of the gate electrodes of the switches 32 and 92.

[0175] The bias generating circuit 111 applies a predetermined constant voltage to the gate electrode (gate) of the clamp transistor 112 as a bias.

[0176] This ensures the withstand voltage of thin-film transistors such as switch 32 and switch 92 connected to the source side of clamp transistor 112. In other words, switch 32 and switch 92 can be configured as thin-film transistors with thin gate electrodes.

[0177] Therefore, the gate capacitance of the clock, i.e., the gate capacitance of the switch 32 and the switch 92, can be reduced, and the amplitude of the control signal CK1 and the control signal CK2 can be reduced. This makes it possible to realize high-speed clock transmission. In other words, the detection circuit 22 can be driven at a higher speed.

[0178] Fifth Modification of the First Embodiment <Configuration Example of Photoelectric Conversion Device> An active quench circuit may be further provided to the configuration of the photoelectric conversion device 11 shown in Fig. 11, as shown in Fig. 12, for example. Note that the circuit configuration shown in Fig. 12 is merely one example. The active quench circuit provided in the photoelectric conversion device 11 may be any circuit that can temporarily lower the potential on the cathode side of the photodiode 31 to the potential of a predetermined power supply VRL when a photon is detected by the photodiode 31.

[0179] The configuration of the photoelectric conversion device 11 shown in FIG. 12 is configured such that an active quench circuit 131 is newly provided between the drain side of the clamp transistor 112 and the photodiode 31 in the configuration shown in FIG.

[0180] The active quench circuit 131 is connected between the clamp transistor 112 and the photodiode 31, and realizes the function of lowering the potential on the cathode side of the photodiode 31 to a potential at which avalanche multiplication does not occur.

[0181] The active quench circuit 131 includes an inverter 141 , a delay circuit 142 , an AND gate 143 , and a switch 144 .

[0182] The input terminal of the inverter 141 is connected between the drain of the clamp transistor 112 and the photodiode 31 , and the output terminal of the inverter 141 is connected to the delay circuit 142 and the AND gate 143 .

[0183] An input terminal of delay circuit 142 is connected to the output terminal of inverter 141, and an output terminal of delay circuit 142 is connected to AND gate 143. One input terminal of AND gate 143 is connected to the output terminal of inverter 141, the other input terminal of AND gate 143 is connected to the output terminal of delay circuit 142, and an output terminal of AND gate 143 is connected to switch 144.

[0184] The switch 144 is formed of, for example, a thick-film nMOS transistor. The source of the switch 144 is connected to the negative voltage power supply VRL, and the drain of the switch 144 is connected between the drain of the clamp transistor 112 and the photodiode 31.

[0185] Furthermore, the gate electrode of the switch 144 is connected to the output terminal of the AND gate 143, and the switch 144 is turned on and off according to the output of the AND gate 143 to connect the cathode of the photodiode 31 to the power supply VRL.

[0186] For example, the voltage of the power supply VRL is set to about -2V, and the voltage applied to the anode of the photodiode 31 is set to about -20V.

[0187] When the photodiode 31 is recharged and the potential VK is high (H level), the output of the inverter 141 becomes L level, and the inputs to the AND gate 143 and the delay circuit 142 also become L level. Since the output of the AND gate 143 becomes L level, the switch 144 is in the OFF state, and the cathode of the photodiode 31 and the power supply VRL are not connected (disconnected).

[0188] In this state, when photons are incident on the photodiode 31 after recharging and the potential VK drops due to avalanche multiplication, the active quench circuit 131 operates.

[0189] That is, since the input to the inverter 141 is at L level, the input from the inverter 141 to the AND gate 143 is at H level.

[0190] Furthermore, the delay circuit 142 delays and inverts the L level input immediately after recharging, and therefore the output of the delay circuit 142 at this point, that is, the input from the delay circuit 142 to the AND gate 143, is at H level.

[0191] Therefore, the output of the AND gate 143 becomes H level, and the switch 144 is turned on (conducted). As a result, the cathode of the photodiode 31 is connected to the power supply VRL, and the potential VK further decreases to a potential at which avalanche multiplication does not occur.

[0192] Then, in the subsequent exposure period, i.e., the count period, even if further photons are incident on the photodiode 31, the occurrence of avalanche multiplication can be suppressed. In other words, further occurrence of avalanche multiplication can be suppressed until the next recharge. This makes it possible to reduce power consumption.

[0193] Furthermore, instead of the charge on the cathode side of the photodiode 31 flowing (moving) to the anode side of about -20V, the charge can be made to flow to the power supply VRL side of about -2V, thereby realizing power saving.

[0194] Furthermore, since the delay circuit 142 is connected to the AND gate 143 that controls the switch 144, the photodiode 31 is connected to the power supply VRL only when the potential VK drops. Therefore, when recharging is performed by the operation of the pulse generating circuit 21, it is possible to prevent a through current from flowing through the active quench circuit 131.

[0195] Second embodiment <Configuration Example of Photoelectric Conversion Device> In the photoelectric conversion device 11, for example, as shown in FIG. 13, an up-down counter 171 may be provided instead of the counter 35.

[0196] The configuration of the photoelectric conversion device 11 shown in Fig. 13 is configured such that an up-down counter 171 is provided instead of the counter 35 in the configuration shown in Fig. 3. Furthermore, the photoelectric conversion device 11 shown in Fig. 13 basically performs the same operation as the photoelectric conversion device 11 shown in Fig. 3.

[0197] In this example, an up / down counter 171 is connected to the output of the NAND gate 34, so that the difference in count value between frames can be obtained.

[0198] For example, in a given exposure period T corresponding to one frame of an image, the up / down counter 171 performs a count-up operation, and in the next exposure period T, the up / down counter 171 performs a count-down operation. In this way, the difference in count values ​​between adjacent exposure periods T, i.e., the brightness difference value, can be obtained.

[0199] Such a photoelectric conversion device 11 can be used in cases where an event is detected at a certain brightness contrast by, for example, acquiring and outputting a brightness difference value and comparing the output with a certain threshold value.

[0200] Third embodiment <Configuration Example of Photoelectric Conversion Device> For example, by providing a plurality of counters in the detection circuit 22, it may be possible to perform a counting operation for each period of the photon detection cycle (hereinafter also referred to as a detection period).

[0201] In such a case, the photoelectric conversion device 11 is configured as shown in FIG.

[0202] The configuration of the photoelectric conversion device 11 shown in FIG. 14 is configured such that a counter 201 is newly provided in the configuration shown in FIG.

[0203] In this example, not only the NAND gate 34 but also the counter 201 is connected to the output terminal of the inverter 33. Here, the potential on the output terminal side of the inverter 33 is denoted as OUT1, and the potential on the output terminal side of the NAND gate 34 is denoted as OUT2.

[0204] The counter 201 is a counter circuit, and performs a counting operation in response to the potential OUT 1 on the output terminal side of the inverter 33 , that is, the pulse signal output from the inverter 33 .

[0205] In other words, the counter 201 counts the number of pulse signals output from the inverter 33 serving as the first detection circuit, that is, the number of pulses in the pulse signal, and holds a count value that is the count result.

[0206] FIG. 15 shows an example of driving the photoelectric conversion device 11 shown in FIG.

[0207] 15, the horizontal direction indicates time, and the vertical direction indicates level (electric potential). Also, the arrow drawn on the line marked with the word "photon" indicates that a photon is incident on the photodiode 31.

[0208] Each number in the row marked with the letters “COUNTER A” indicates the count value held in counter 201, and each number in the row marked with the letters “COUNTER B” indicates the count value held in counter 35.

[0209] The broken lines L71 to L75 represent the potential VK, the control signal CK1, the potential OUT1, the control signal CK2, and the potential OUT2.

[0210] In this example, recharging of the photodiode 31 starts at the falling edge of the control signal CK1, and ends at the rising edge of the control signal CK1. Therefore, in this example, the recharge period is τ0+τ1.

[0211] Furthermore, the timing at which the control signal CK2 falls during the recharge cycle is the timing at which the count period switches.

[0212] Specifically, the period from the recharge start time to the time when the control signal CK2 falls is set as a shorter count target period τ0, and the period from the time when the control signal CK2 falls to the next recharge start time is set as a longer count target period τ1.

[0213] In this driving example, when recharging is performed, the potential OUT1 becomes L level, and thereafter, when avalanche multiplication occurs, the potential OUT1 changes to H level.

[0214] Therefore, when a photon is incident on the photodiode 31 during the period τ0+τ1 of the recharge cycle, the count value (counter A) held in the counter 201 is incremented by 1. In other words, the detection circuit 22 detects the incidence of a photon during the detection cycle τ0+τ1, and the detection result is counted by the counter 201.

[0215] In this driving example, the control signal CK2 is set to H level during the count period τ0, and the control signal CK2 is set to L level at the timing when the count period τ0 ends.

[0216] During the count period τ0, when a photon is incident on the photodiode 31, the potential OUT1 goes to H level, and the control signal CK2 is also at H level, so that the potential OUT2 on the output side of the NAND gate 34 goes to L level.

[0217] Thereafter, when the count period τ0 ends and the control signal CK2 goes to L level, the potential OUT2 on the output side of the NAND gate 34 changes to H level, so that the count value of the counter 35, which receives the potential OUT2 as an input, is incremented by 1.

[0218] Therefore, when a photon is incident on the photodiode 31 during the count period τ0, the count value (counter B) held in the counter 35 is incremented by 1. In other words, the detection circuit 22 detects the incidence of a photon in the detection cycle τ0, and the detection result is counted by the counter 35.

[0219] When the control signal CK2 is at H level, the counter 35 counts if a photon is incident during the count period τ0, so that the photoelectric conversion device 11 shown in FIG. 14 can be used as a TDC (Time to Digital Converter).

[0220] Moreover, the control signal CK2 can be set without recharging. That is, the potential of the control signal CK2 can be changed independently, regardless of the timing of recharging. Therefore, the cycle of the control signal CK2 can be set shorter than the recharge cycle, and photon detection can be achieved in a short time. That is, the detection cycle τ0 can be shortened.

[0221] Furthermore, in order to prevent the output of the control signal CK2, which is a clock, from being corrupted, that is, to prevent the pulse waveform of the control signal CK2 from becoming dull, the control signal CK2 may be generated using a plurality of clock signals.

[0222] In such a case, for example, an AND gate 211 shown in FIG.

[0223] Two control signals CK2_1 and CK2_2, which are clocks, are input to this AND gate 211, and the AND gate 211 outputs a control signal CK2 in response to the inputs.

[0224] In this case, the control signal CK2 becomes H level only when the control signal CK2_1 and the control signal CK2_2 are both H level, and otherwise the control signal CK2 becomes L level.

[0225] Therefore, for example, if a control signal CK2_1 having a waveform shown in curve L81 and a control signal CK2_2 having a waveform shown in curve L82 are input to an AND gate 211, the waveform of the control signal CK2 output from the AND gate 211 will be as shown in curve L83. In this example, the pulse width τ0 of the control signal CK2 can be narrowed. In other words, it can be seen that the pulse is shortened.

[0226] Fourth embodiment <Configuration Example of Photoelectric Conversion Device> In the second detection circuit, the incidence (arrival) of photons is detected in a number of distinct periods.

[0227] In the above example, the count period τ0 and the count period τ1 are provided as the period for detecting the incidence of photons, that is, the count period.

[0228] However, the present invention is not limited to this, and in addition to the count period τ0 and the count period τ1, a plurality of count periods having mutually different lengths (cycles) may be provided, such as a count period τ2 and a count period τ3.

[0229] In this case, multiple control signals such as the control signal CK2 are used to divide (split) the recharge cycle into any number of count periods. However, to obtain the effect of a high dynamic range, that is, to expand the dynamic range to the high luminance side, it is necessary to make τ0<τ1<τ2<τ3...

[0230] By using multiple control signals to set n count periods within a recharge cycle, it is possible to reduce the power consumed in recharging to 1 / n.

[0231] When three count target periods τ0 to τ2 are provided within a recharge cycle, the photoelectric conversion device 11 is configured as shown in FIG. 17, for example.

[0232] The configuration of the photoelectric conversion device 11 shown in FIG. 17 is configured such that a NOR gate 241 is newly provided in the configuration shown in FIG.

[0233] In this example, the output terminal of the NAND gate 34 is connected to one input terminal of a NOR gate 241, and the control signal CK3 is supplied from the pulse generating circuit 21 to the other input terminal of the NOR gate 241.

[0234] The control signal CK3 is a signal for controlling the timing of photon detection by the photodiode 31, that is, for switching the count period during which photons are detected.

[0235] In addition, the output terminal of the NOR gate 241 is connected to the counter 35, and the counter 35 performs a counting operation in response to the pulse signal output from the NOR gate 241. In other words, the counter 35 counts the number of pulse signals (pulses) output from the NOR gate 241, and holds the count value that is the counting result.

[0236] In this example, a second detection circuit is realized by the NAND gate 34 and the NOR gate 241. In this embodiment, the potential on the output side of the NAND gate 34 is denoted as P2, and the potential on the output side of the NOR gate 241 is denoted as OUT.

[0237] In a second detection circuit consisting of a NAND gate 34 and a NOR gate 241, a pulse signal (potential OUT) is generated as an output based on a pulse signal (potential P1) which is the output of the inverter 33 and a plurality of control signals having different rise and fall timings, i.e., control signal CK2 and control signal CK3.

[0238] At this time, in the second detection circuit, avalanche multiplication occurring in each of three or more periods in the recharge cycle of the photodiode 31 is detected by distinguishing each period, and a pulse signal corresponding to the detection result is generated and output. The multiple periods referred to here are count target periods τ0 to τ2, which will be described later.

[0239] FIG. 18 shows an example of driving the photoelectric conversion device 11 shown in FIG.

[0240] 18, the horizontal direction indicates time, and the vertical direction indicates level (electric potential). The arrow drawn in the row marked with the word "photon" indicates that a photon is incident on the photodiode 31. Each numerical value in the row marked with the word "counter" indicates the count value held in the counter 35.

[0241] The broken lines L101 to L107 represent the potential VK, the control signal CK1, the control signal CK2, the control signal CK3, the potential P1, the potential P2, and the potential OUT.

[0242] In this example, recharging of the photodiode 31 starts when the control signal CK1 falls, and recharging of the photodiode 31 ends when the control signal CK1 rises.

[0243] Furthermore, the timing at which the control signal CK2 falls and the timing at which the control signal CK3 rises during the recharge cycle are the timings at which the count period switches.

[0244] Specifically, the period from the start of recharge to the time when the control signal CK2 falls is set to the shortest count period τ0, and the period from the time when the control signal CK2 falls to the time when the control signal CK3 rises is set to the second shortest count period τ1.

[0245] The period from the time when the control signal CK3 rises to the time when the next recharge starts is set as the longest count period τ2.

[0246] Therefore, in this example, the recharge period is τ0+τ1+τ2.

[0247] In this driving example, the counting operation is performed by distinguishing in which period of counting periods τ0 to τ2, which have mutually different lengths, a photon has been incident.

[0248] For example, when a photon is incident on photodiode 31 during count period τ0, the count value held in counter 35 increases by 3 regardless of whether a photon is incident on photodiode 31 during subsequent count period τ1 or count period τ2.

[0249] That is, when the incidence of a photon is detected during the count period τ0, the counter 35 counts three times, regardless of whether or not a photon is incident until the time of the next recharge.

[0250] Specifically, when a photon is incident during the count period τ0 and avalanche multiplication occurs, the potential P1 on the output side of the inverter 33 becomes H level. At this time, the control signal CK2 is at H level, so the potential P2 on the output side of the NAND gate 34 becomes L level.

[0251] Moreover, since the potential P2 is at the L level and the control signal CK3 is also at the L level, the potential OUT on the output side of the NOR gate 241 changes from the L level to the H level, causing the count value of the counter 35 to increase by one.

[0252] Furthermore, thereafter, until the control signal CK1 falls again, that is, until the next recharge starts, regardless of whether or not a photon is incident, the potential OUT on the output side of the NOR gate 241 changes due to the changes in the control signals CK2 and CK3. That is, the potential OUT changes from the L level to the H level twice.

[0253] This causes the counter 35 to perform two more counting operations (count two), and as a result, when a photon is incident during the count period τ0, the count value is increased by three.

[0254] Similarly, if no photons are incident during counting period τ0 but a photon is incident during the next counting period τ1, the count value of counter 35 will increase by 2 regardless of whether or not a photon is incident during the subsequent counting period τ2.

[0255] That is, when a photon is incident during count period τ1, the same operation as when a photon is incident during count period τ0 is performed, and the count value of the counter 35 is increased by one.

[0256] Furthermore, thereafter, until the next recharge starts, the potential OUT on the output side of the NOR gate 241 changes due to the change in the control signal CK3, regardless of whether or not a photon is incident. That is, the potential OUT changes from the L level to the H level.

[0257] This causes the counter 35 to perform one more counting operation (count by 1), and as a result, when a photon is incident during the count period τ1, the count value is incremented by 2.

[0258] Furthermore, if no photons are incident during count period τ0 and count period τ1, but a photon is incident during the next count period τ2, the count value of the counter 35 is incremented by one.

[0259] That is, when a photon is incident during count period τ2, the same operation as when a photon is incident during count period τ0 is performed, and the count value of the counter 35 is increased by one.

[0260] However, after that, until the next recharge, neither the control signal CK2 nor the control signal CK3 changes, so the potential OUT on the output side of the NOR gate 241 does not change, and no counting operation is performed. As a result, when a photon is incident during the count period τ2, the count value increases by 1.

[0261] As described above, it is possible to provide three or more count periods within a recharge cycle, thereby reducing the number of recharges and power consumption while ensuring a wider dynamic range.

[0262] Fifth embodiment <Configuration Example of Photoelectric Conversion Device> The second detection circuit may have any configuration as long as it is capable of distinguishing between incidence of photons in two or more count periods and outputting pulses in response to incidence of photons in those count periods.

[0263] When the counting operation is performed in response to incidence of photons in each of the count periods τ0 to τ2, the photoelectric conversion device 11 may have a configuration shown in FIG. 19, for example.

[0264] The photoelectric conversion device 11 shown in FIG. 19 has a configuration in which a flip-flop circuit 271 and a delay element 272 are provided instead of the NAND gate 34 in the configuration shown in FIG.

[0265] In this example, a flip-flop circuit 271 and a delay element 272 implement the second detection circuit.

[0266] In the second detection circuit, an output pulse signal (potential OUT) is generated based on a pulse signal (potential P1) which is the output of the inverter 33 and a control signal CK2.

[0267] At this time, in the second detection circuit, avalanche multiplication occurring within each of two or more periods in the recharge cycle of the photodiode 31 is detected by distinguishing between the periods, and a pulse signal corresponding to the detection result is generated and output. The multiple periods referred to here are count target periods τ0 to τ2, which will be described later.

[0268] The flip-flop circuit 271 is made up of a D-Flip Flop circuit with a reset function, and the input terminal (D terminal) of the flip-flop circuit 271 is connected to the output terminal of the inverter 33 .

[0269] A control signal CK2 output from the pulse generating circuit 21 is input to a clock input terminal (CK terminal) of the flip-flop circuit 271. This control signal CK2 is a signal for controlling the detection timing of photons, that is, for switching the count target period.

[0270] An output terminal (Q terminal) of the flip-flop circuit 271 is connected to the counter 35 , and an inverted output terminal of the flip-flop circuit 271 is connected to the delay element 272 .

[0271] The inverting output terminal of the flip-flop circuit 271 is a terminal that inverts and outputs the output from the output terminal of the flip-flop circuit 271. Hereinafter, in this embodiment, the potential on the output terminal side of the flip-flop circuit 271 will be referred to as OUT.

[0272] The input terminal of the delay element 272 is connected to the inverting output terminal of the flip-flop circuit 271 , and the output terminal of the delay element 272 is connected to the reset terminal of the flip-flop circuit 271 .

[0273] The delay element 272 delays the output of the inverting output terminal of the flip-flop circuit 271 and inputs the delayed output to a reset terminal of the flip-flop circuit 271, thereby causing the flip-flop circuit 271 to perform a reset operation. That is, the delay element 272 controls the reset of the pulse signal (potential OUT) which is the output of the flip-flop circuit 271.

[0274] FIG. 20 shows an example of driving the photoelectric conversion device 11 shown in FIG.

[0275] 20, the horizontal direction indicates time, and the vertical direction indicates level (electric potential). The arrow drawn in the row marked with the word "photon" indicates that a photon is incident on the photodiode 31. Each numerical value in the row marked with the word "counter" indicates the count value held in the counter 35.

[0276] The broken lines L121 to L125 represent the potential VK, the control signal CK1, the control signal CK2, the potential P1, and the potential OUT.

[0277] In this example, recharging starts when the control signal CK1 falls, and ends when the control signal CK1 rises.

[0278] Furthermore, the timing at which the control signal CK2 rises during the recharge cycle is the timing at which the count period switches.

[0279] In this example, three count target periods τ0, τ1, and τ2 having different lengths are provided within the recharge period τ0+τ1+τ2.

[0280] In particular, in this example, the number of clocks when photons are incident during each count period can be integrated into one for implementation. In other words, three or more count periods can be set with just one control signal CK2. This makes it possible to reduce the number of wirings for transmitting the control signal (clock) to set the count periods.

[0281] In the driving example shown in FIG. 20, when a photon is incident and avalanche multiplication occurs in the photodiode 31, the potential P1 on the output side of the inverter 33 goes to H level, and then the potential OUT goes to H level at the timing when the control signal CK2 rises.

[0282] As a result, the counter 35 performs a counting operation in response to the change in the potential OUT. That is, the count value of the counter 35 is incremented by one.

[0283] Simultaneously with the count operation, a signal obtained by inverting the potential OUT, i.e., an L level, is input to the delay element 272, delayed by the delay time of the delay element 272, and input to the reset terminal of the flip-flop circuit 271. As a result, in the flip-flop circuit 271, a reset operation is performed after the count operation, and the potential OUT on the output side of the flip-flop circuit 271 becomes an L level.

[0284] By such an operation, when a photon is incident on the photodiode 31 during each count period, the counter 35 performs a count operation for one count.

[0285] For example, in the example of Figure 20, after the first recharge, a photon is incident during counting period τ0, so at the end of that counting period τ0, a counting operation is performed for counting period τ0, and the count value is increased by 1.

[0286] Furthermore, counting operations are also performed for the subsequent count period τ1 and count period τ2, and the count value is increased by a total of 3.

[0287] In contrast to this, after the second recharge, since no photons are incident during the count period τ0, the count operation is not performed during the count period τ0.

[0288] However, since a photon is incident during the subsequent count period τ1, a count operation for the count period τ1 is performed at the end of the count period τ1, and the count value is increased by 1. A count operation is also performed for the next count period τ2, and the count value is increased by 2 in total.

[0289] After the third recharge, since no photons are incident during count period τ0 and count period τ1, the counting operation is not performed during count period τ0 and count period τ1.

[0290] However, since a photon is incident during the subsequent count period τ2, at the end of the count period τ2, a count operation for the count period τ2 is performed and the count value increases by 1. From these facts, it can be seen that the incidence of photons (avalanche multiplication) during each count period is detected separately for each count period.

[0291] <Modification 1 of the fifth embodiment> <Configuration Example of Photoelectric Conversion Device> In the photoelectric conversion device 11 shown in FIG. 19, the reset of the flip-flop circuit 271 is controlled by the delay element 272, but this reset control may be performed by an external control signal.

[0292] In such a case, the photoelectric conversion device 11 is configured as shown in FIG.

[0293] The configuration of the photoelectric conversion device 11 shown in FIG. 21 is a configuration in which the delay element 272 is not provided in the configuration shown in FIG.

[0294] In this example, the pulse generating circuit 21 generates a control signal CK3 for resetting the flip-flop circuit 271, and supplies (inputs) the control signal CK3 to the reset terminal of the flip-flop circuit 271.

[0295] Therefore, the flip-flop circuit 271 performs a reset operation, that is, resets the pulse signal (potential OUT) that is the output, in response to the control signal CK3 supplied from the pulse generating circuit 21 (external).

[0296] Particularly, in this example, the photoelectric conversion device 11 performs driving similarly to the example shown in Fig. 20. At this time, the pulse generating circuit 21 generates a control signal CK3 such that the control signal CK3 falls and a reset operation is executed immediately after the control signal CK2 rises, and supplies the control signal CK3 to the flip-flop circuit 271.

[0297] With this configuration, it becomes unnecessary to provide the delay element 272, and the area of ​​the detection circuit 22 can be reduced by the area of ​​the delay element 272.

[0298] Sixth embodiment <Configuration Example of Photoelectric Conversion Device> In the photoelectric conversion device 11, a detection circuit 22 is provided for each pixel, and the detection circuits 22 are arranged in an array. That is, one detection circuit 22, more specifically, one photodiode 31 forms one pixel.

[0299] In this case, it is sufficient that one or more pulse generating circuits 21 are provided for a plurality of detection circuits 22, that is, for a pixel array portion having a plurality of detection circuits 22.

[0300] For example, as shown in FIG. 22, a control signal CK1 and a control signal CK2 may be supplied from one pulse generating circuit 21 to a plurality of detection circuits 22, respectively.

[0301] The photoelectric conversion device 11 shown in Fig. 22 is provided with a pixel array section 301 in which a plurality of detection circuits 22 corresponding to a plurality of pixels are arranged in the row direction, i.e., the horizontal direction in the figure, and in the column direction, i.e., the vertical direction in the figure. In other words, the pixel array section 301 is provided with a plurality of detection circuits 22 arranged in an array. Note that, in order to make the figure easier to see, only some of the plurality of detection circuits 22 are given reference numerals. This also applies to the figures described below.

[0302] Furthermore, one pulse generating circuit 21 is provided outside the pixel array section 301 in plan view, that is, when viewed from a direction perpendicular to the pixel array section 301 .

[0303] In this example, the pulse generating circuit 21 generates one control signal CK1 or control signal CK2, and supplies the generated control signal CK1 or control signal CK2 at the same timing to all detection circuits 22. Therefore, in each detection circuit 22, recharging and counting operations are performed at the same timing.

[0304] <Modification 1 of the sixth embodiment> <Configuration Example of Photoelectric Conversion Device> In the configuration shown in FIG. 22, since recharging and counting operations are performed simultaneously in all of the detection circuits 22, there is a possibility that the photon detection counting operation will not be performed correctly due to IR Drop.

[0305] Therefore, IR Drop may be suppressed by shifting the timing of supplying the control signal CK1 or the control signal CK2 for each pixel column of pixels corresponding to the detection circuit 22, each pixel row of pixels, or each area of ​​multiple pixels.

[0306] That is, the control signals CK1 and CK2 may be distributed (supplied) so that the supply timings of the control signals CK1 and CK2 differ for each pixel column, each pixel row, or each area.

[0307] Here, a pixel column is made up of a number of pixels (detection circuits 22) arranged in a column direction (vertical direction), and a pixel row is made up of a number of pixels arranged in a row direction (horizontal direction). Also, an area is a region made up of a number of pixels arranged in row and column directions, such as a region of 3 pixels x 3 pixels.

[0308] When the control signals CK1 and CK2 are distributed with the supply timing shifted for each pixel column, the photoelectric conversion device 11 may have a configuration as shown in FIG. 23, for example.

[0309] The configuration of the photoelectric conversion device 11 shown in FIG. 23 differs from the configuration shown in FIG. 22 in that a delay circuit is provided for each pixel column to delay the supply timing of the control signal CK1 or the control signal CK2.

[0310] That is, a delay circuit 311 and a delay circuit 312 are provided between the pulse generating circuit 21 and the detection circuit 22 that constitutes the leftmost pixel column (hereinafter also referred to as pixel column A) of the pixel array section 301 in the figure.

[0311] In addition, for example, delay circuits 311 and 312, and delay circuits 313 and 314 are provided between the pulse generating circuit 21 and the detection circuit 22 constituting the second pixel column from the left in the figure of the pixel array section 301 (hereinafter also referred to as pixel column B).

[0312] The delay circuits 311 to 314 are made up of flip-flop circuits, and operate in response to a clock signal CLK supplied from the outside.

[0313] For example, the pulse generating circuit 21 supplies a control signal CK1 to the delay circuit 311 and also supplies a control signal CK2 to the delay circuit 312.

[0314] The delay circuit 311 delays the supplied control signal CK1 by one clock of the clock signal CLK, and then supplies the delayed control signal CK1 as a control signal CK1_A to each detection circuit 22 and delay circuit 313 that constitutes pixel column A.

[0315] Furthermore, the delay circuit 313 delays the control signal CK1_A supplied from the delay circuit 311 by one clock of the clock signal CLK. The delay circuit 313 then supplies the delayed control signal CK1_A as a control signal CK1_B to each detection circuit 22 constituting pixel column B, and also supplies the control signal CK1_B to a delay circuit provided between the delay circuit 313 and the detection circuit 22 constituting the third pixel column from the left in the drawing of the pixel array unit 301 (hereinafter also referred to as pixel column C).

[0316] Therefore, the control signal CK1_A and the control signal CK1_B are signals (clocks) with a timing difference of one clock. In other words, the supply timing of the control signal CK1 to the detection circuit 22 constituting pixel column A and the supply timing of the control signal CK1 to the detection circuit 22 constituting pixel column B are shifted by one clock.

[0317] In the example of FIG. 23, a delay circuit is provided for each pixel column, so that the timing of supplying the control signal CK1 to each detection circuit 22 is shifted by one clock for each pixel column.

[0318] Like the control signal CK1, the supply timing of the control signal CK2 is shifted by one clock for each pixel column.

[0319] That is, the delay circuit 312 delays the control signal CK2 supplied from the pulse generating circuit 21 by one clock of the clock signal CLK, and then supplies the delayed signal as a control signal CK2_A to each detection circuit 22 and delay circuit 314 constituting pixel column A.

[0320] Furthermore, the delay circuit 314 delays the control signal CK2_A supplied from the delay circuit 312 by one clock of the clock signal CLK, and then supplies the control signal as CK2_B to each detection circuit 22 constituting pixel column B. At this time, the delay circuit 314 also supplies the control signal CK2_B to a delay circuit provided between the delay circuit 314 and the detection circuit 22 constituting pixel column C.

[0321] As described above, by shifting the supply timing of the control signal CK1 and the control signal CK2 for each pixel column by a certain amount, it is possible to shift the timing of the recharge and count operations for each pixel column, and thus it is possible to suppress IR Drop.

[0322] Seventh embodiment <Configuration Example of Photoelectric Conversion Device> In addition, it is sufficient that one or more pulse generating circuits 21 are provided for the pixel array section 301. That is, for example, as shown in FIG.

[0323] In the example shown in FIG. 24, a pulse generating circuit 21 is provided for each pixel row constituting the pixel array section 301.

[0324] In this case, each pulse generating circuit 21 may supply a control signal CK1 or a control signal CK2 to the detection circuits 22 constituting a pixel row at the same timing, or may supply a control signal CK1 or a control signal CK2 at different timings for each pixel row.

[0325] For example, similarly to the example of FIG. 23, the control signals CK1 and the like may be supplied at timings shifted by one clock for each pixel row to suppress IR Drop.

[0326] Eighth embodiment <Configuration Example of Photoelectric Conversion Device> For example, in the photoelectric conversion device 11, the detection circuit 22 and the pulse generation circuit 21 may be formed on a semiconductor substrate having a laminated structure made up of a plurality of layers.

[0327] In such a case, for example, as shown in FIG. 25, a photodiode 31 corresponding to a pixel may be arranged (formed) on a first layer 351 of a semiconductor substrate, and elements other than the photodiode 31 of the detection circuit 22 and the pulse generating circuit 21 may be arranged on a second layer 352 different from the first layer 351.

[0328] In this example, the semiconductor substrate is composed of a first layer 351 provided on the light incident side, and a second layer 352 provided adjacent to the first layer 351.

[0329] The surface of the first layer 351 opposite to the second layer 352 side functions as a light receiving surface that receives light incident from the outside, and the first layer 351 is provided with only photodiodes 31 that function as pixels.

[0330] On the other hand, the second layer 352 is provided with components other than the photodiode 31 of the detection circuit 22, that is, the switch 32 to the counter 35, and the pulse generation circuit 21.

[0331] With this configuration, the pixel aperture can be made wider, and high integration can be achieved.

[0332] Furthermore, when the layer configuration shown in FIG. 25 is used, the pulse generating circuit 21 can be arranged outside the pixel array section 301 in plan view, for example, as shown in FIG. 26 or FIG.

[0333] 26, when viewed in a direction perpendicular to the surface of the semiconductor substrate (in a plan view), the pulse generating circuit 21 is formed along the long side of the pixel array section 301 in the second layer 352. That is, the pulse generating circuit 21 is disposed adjacent to the long side of the pixel array section 301.

[0334] The pulse generating circuit 21 controls the operation of elements formed in the second layer 352 of the detection circuit 22, such as the switch 32 and the NAND gate 34, by supplying a control signal CK1 and a control signal CK2.

[0335] In this way, by disposing the pulse generating circuit 21 on the long side of the pixel array section 301, it is possible to reduce the wiring load impedance for the wiring of the control signal CK1 and the control signal CK2. This makes it possible to form a more uniform detection period (count target period) in each detection circuit 22 in the pixel array section 301.

[0336] 27, when viewed in a direction perpendicular to the surface of the semiconductor substrate (in a plan view), the pulse generating circuit 21 is formed along the short side of the pixel array section 301 in the second layer 352. That is, the pulse generating circuit 21 is disposed adjacent to the short side of the pixel array section 301.

[0337] Even in this case, the pulse generating circuit 21 controls the operations of the elements formed in the second layer 352, such as the switch 32 and the NAND gate 34, by the control signals CK1 and CK2.

[0338] <Modification 1 of the eighth embodiment> <Layer structure of photoelectric conversion device> Furthermore, when the semiconductor substrate constituting the photoelectric conversion device 11 is made up of three layers, the elements of the detection circuit 22 may be disposed on a first layer 351 to a third layer 353, for example, as shown in FIG.

[0339] 28, the photoelectric conversion device 11 has the same configuration as the example shown in Fig. 12, and the semiconductor substrate has a first layer 351 to a third layer 353. In addition, a third layer 353 is a layer provided adjacent to the second layer 352 on the opposite side of the second layer 352 from the first layer 351 side.

[0340] In FIG. 28, among the elements that make up the detection circuit 22, only the photodiode 31 is disposed on the first layer 351.

[0341] In addition, in the second layer 352, the bias generating circuit 111, and the clamp transistor 112 and the active quench circuit 131, which are among the elements that constitute the detection circuit 22, are arranged.

[0342] In the third layer 353, the pulse generating circuit 21 and the switch 32, switch 92, logic gate 91, NAND gate 34, and counter 35, which are elements that constitute the detecting circuit 22, are arranged.

[0343] Furthermore, when viewed from a direction perpendicular to the surface of the semiconductor substrate (when viewed in a plan view), the pulse generating circuit 21 and the bias generating circuit 111 are disposed outside the area of ​​the pixel array section 310.

[0344] In this example, the clamp transistor 112 and the active quench circuit 131 are configured with thick-film transistors, that is, HV (High Voltage) transistors with a withstand voltage of 3.0 V or the like.

[0345] Therefore, by arranging these clamp transistors 112 and active quench circuit 131 together on the second layer 352, thin-film transistors can be used as transistors constituting each element, such as the switch 32 and the switch 92, on the third layer 353. A thin-film transistor is an LV (Low Voltage) transistor with a withstand voltage of 0.8 V or the like.

[0346] In this way, by arranging elements composed of HV transistors on the second layer 352 and elements composed of LV transistors on the third layer 353, it is possible to improve the area efficiency of element arrangement on a semiconductor substrate.

[0347] Although an example in which the bias generation circuit 111 is arranged on the second layer 352 has been described here, the bias generation circuit 111 may be arranged on the third layer 353 as shown in FIG.

[0348] In the example shown in Fig. 29, the bias generation circuit 111 is arranged in the third layer 353. Moreover, the bias generation circuit 111 and the pulse generation circuit 21 are arranged in a region outside the pixel array unit 301 in a planar view, similar to the case in Fig. 28.

[0349] The bias generating circuit 111 applies a bias to the gate electrode of the clamp transistor 112 arranged on the second layer 352 via a wiring from the third layer 353.

[0350] <Modification 2 of the eighth embodiment> <Layer structure of photoelectric conversion device> In addition, when the semiconductor substrate constituting the photoelectric conversion device 11 is composed of three layers, namely, a first layer 351 to a third layer 353, the control circuit, the first detection circuit, and the second detection circuit may be arranged on the second layer 352, for example, as shown in Figures 30 and 31.

[0351] For example, in the example shown in FIG.

[0352] In the second layer 352, the bias generation circuit 111 and the switch 32, switch 92, logic gate 91, NAND gate 34, clamp transistor 112, and active quench circuit 131, which are elements that constitute the detection circuit 22, are arranged.

[0353] In the third layer 353, the pulse generating circuit 21 and the counter 35 out of the elements constituting the detecting circuit 22 are arranged.

[0354] In this example, the second layer 352 is provided with a switch 32 and a switch 92 which function as a control circuit for controlling the recharging of the photodiode 31, a logic gate 91 which functions as a first detection circuit, and a NAND gate 34 which functions as a second detection circuit.

[0355] For example, in the layer configurations shown in FIGS. 28 and 29, capacitance occurs between the logic gate 91 or switch 92 and the clamp transistor 112, that is, between the second layer 352 and the third layer 353, due to the bonding of layers.

[0356] In response to this, the occurrence of such capacitance can be prevented by using the arrangement shown in Fig. 30. In other words, the capacitance between the second layer 352 and the third layer 353 can be reduced, thereby reducing power consumption.

[0357] 30, a capacitance occurs between the NAND gate 34 and the counter 35 between the second layer 352 and the third layer 353, but this capacitance does not adversely affect the timing of the counting operation of the counter 35. That is, the counter 35 in the third layer 353 can count signals with relaxed timing constraints. This makes it possible to determine the layout of each element without the need for wiring care, and improves the area efficiency of the element layout on the semiconductor substrate.

[0358] When the control circuit, the first detection circuit, and the second detection circuit are arranged on the second layer 352, the pulse generating circuit 21 may also be arranged on the second layer 352, as shown in FIG.

[0359] In the example of FIG. 31, the photodiode 31 is disposed on the first layer 351.

[0360] The second layer 352 is arranged with the pulse generating circuit 21, the bias generating circuit 111, and the switch 32, the switch 92, the logic gate 91, the NAND gate 34, the clamp transistor 112, and the active quench circuit 131, which are elements constituting the detection circuit 22. The third layer 353 is arranged with the counter 35, which is one of the elements constituting the detection circuit 22.

[0361] Therefore, in this example, in the second layer 352, the pulse generating circuit 21 supplies the control signal CK1, the control signal CK2, and the like to the switch 32, the switch 92, and the like.

[0362] Ninth embodiment <Configuration Example of Photoelectric Conversion Device> In the above, an example has been described in which the detection of incident photons is performed on the cathode side of the photodiode 31, but the detection may be performed on the anode side of the photodiode 31. In other words, the polarity may be reversed from that in the example shown in FIG.

[0363] In such a case, the photoelectric conversion device 11 is configured as shown in FIG.

[0364] In the example shown in FIG. 32, the photoelectric conversion device 11 has a pulse generating circuit 21 and a detection circuit 22, and the detection circuit 22 detects the incidence of photons on the photodiode 31 based on a change in the potential VA on the anode side of the photodiode 31.

[0365] The detection circuit 22 includes a photodiode 31 , a switch 391 , an inverter 33 , a NOR gate 392 , and a counter 35 .

[0366] In this example, a switch 391 as a control circuit and an inverter 33 as a first detection circuit are connected to the anode side of the photodiode 31. The inverter 33 detects the potential VA on the anode side of the photodiode 31. That is, the inverter 33 outputs a pulse signal according to the potential VA on the anode side.

[0367] In addition, the two input terminals of the NOR gate 392 functioning as a second detection circuit are connected to the output terminal of the inverter 33 and the pulse generating circuit 21, respectively, and the output terminal of the NOR gate 392 is connected to the counter 35.

[0368] The switch 391 is composed of an nMOS transistor, and a control signal CK 1 is supplied to the gate electrode of the switch 391 from the pulse generating circuit 21 .

[0369] The switch 391 controls the connection of the anode of the photodiode 31 to a predetermined constant voltage source by turning on and off in response to a control signal CK1 from the pulse generating circuit 21. In other words, the switch 391 controls the recharging of the photodiode 31 by turning on and off.

[0370] For example, when the photodiode 31 is in a standby state, the anode side potential VA is at L level and the potential P1 output from the inverter 33 is at H level, so that the potential OUT output from the NOR gate 392 is at L level.

[0371] When a photon is incident on the photodiode 31 from this state and avalanche multiplication occurs, the potential VA on the anode side of the photodiode 31 rises, and the potential P1 on the output side of the inverter 33 goes to the L level. When the control signal CK2 supplied to the NOR gate 392 goes to the L level, the potential OUT which is the output of the NOR gate 392 goes to the H level, so that the count value held by the counter 35 is incremented by 1, and the incidence of a photon is detected.

[0372] It should be noted that the configuration of photoelectric conversion device 11 shown in FIG. 32 can also be applied in appropriate combination with other embodiments and modifications described in this specification.

[0373] Tenth embodiment <Configuration Example of Photoelectric Conversion Device> The photoelectric conversion device 11 may have a configuration shown in FIG.

[0374] In the example of FIG. 33, the photoelectric conversion device 11 has a sensor chip 421 made of a semiconductor substrate.

[0375] On the sensor chip 421, a pulse generating circuit 21, a control circuit 431, a pixel array unit 301, an SRAM (Static Random Access Memory) 432, a correction processing circuit 433, and an output interface circuit 434 are provided.

[0376] A plurality of pixels, that is, detection circuits 22 corresponding to the pixels, are arranged in the row and column directions in the pixel array section 301. In other words, a plurality of detection circuits 22 are arranged in an array.

[0377] In a region outside the pixel array section 301 and in the vicinity of the pixel array section 301, a pulse generating circuit 21, a control circuit 431, an SRAM 432, and a correction processing circuit 433 are arranged.

[0378] The pulse generating circuit 21 supplies, to each detection circuit 22, a control signal CK1 for controlling the above-mentioned recharge, and a control signal CK2 for controlling the detection timing of photons.

[0379] The control circuit 431 controls the selection of the detection circuit 22 that reads out the count value (hereinafter also referred to as read selection control), and also controls the resetting of the count value in the detection circuit 22 (hereinafter also referred to as counter reset control).

[0380] That is, the control circuit 431 supplies a control signal for read selection control (hereinafter also referred to as a read selection control signal) and a control signal for counter reset control (hereinafter also referred to as a counter reset control signal) to the detection circuit 22 via a signal line.

[0381] In this example, the control circuit 431 and the detection circuit 22 are connected by signal lines provided for each pixel row arranged in the row direction, making it possible to perform read selection control and counter reset control for each pixel row.

[0382] The SRAM 432 is a frame memory, and is connected to each detection circuit 22 by a read data line.

[0383] The SRAM 432 holds the count values ​​supplied from each detection circuit 22 via the read data lines as read data, and also performs arithmetic processing such as frame addition, that is, addition processing, as appropriate, based on the held read data.

[0384] The correction processing circuit 433 performs an appropriate correction process on the read data (count value) held in the SRAM 432, and supplies the corrected data to the output interface circuit 434 as output data.

[0385] The output interface circuit 434 outputs the output data supplied from the correction processing circuit 433 to a subsequent block or the like.

[0386] In the photoelectric conversion device 11 shown in FIG. 33, the detection circuit 22 is configured as shown in FIG.

[0387] The configuration of the detection circuit 22 shown in Fig. 34 is configured by adding a new read selection circuit 461 to the configuration shown in Fig. 3. This read selection circuit 461 is a circuit for reading out the count value held in the counter 35 outside the detection circuit 22 including the counter 35, that is, outside the pixel in which the detection circuit 22 is provided.

[0388] In the example of FIG. 34, a read selection circuit 461 is connected to the rear stage of the counter 35, and the read selection circuit 461 is connected to the SRAM 432 via a read data line.

[0389] In addition, a read selection control signal is supplied to the read selection circuit 461 via a signal line from the control circuit 431. The read selection circuit 461 reads out the count value held in the counter 35 in response to the supplied read selection control signal, and supplies the read out count value to the SRAM 432 via a read data line.

[0390] The counter 35 resets the count value it holds in response to a counter reset control signal supplied from the control circuit 431 via a signal line.

[0391] 33 and 34, for example, the control circuit 431 simultaneously supplies a counter reset control signal to all pixels, i.e., to the counters 35 provided in all detection circuits 22, at the start of the exposure period T. This causes the counters 35 (count values) of all pixels to be reset collectively.

[0392] Also, for example, the pulse generating circuit 21 can simultaneously supply the control signal CK1 having the same waveform to the switches 32 of the detection circuits 22 of all the pixels, thereby recharging all the pixels at once. In this way, a global shutter operation is realized.

[0393] During the exposure period T, recharging is performed simultaneously in all pixels at a recharge period τ0+τ1, for example, in the same manner as in the example of Fig. 4, and photon detection is performed in counting periods τ0 and τ1 provided within the recharge period. As a result, the counter 35 performs a counting operation in response to the incidence of photons, and the result of the counting operation is held as a count value.

[0394] When the uniform exposure period T for all pixels ends, the control circuit 431 selects each pixel row in turn and supplies a read selection control signal to the read selection circuit 461 provided in the detection circuit 22 of the selected pixel row. Then, the read selection circuit 461 reads out the count value from the counter 35 in response to the supplied read selection control signal, and supplies the count value to the SRAM 432.

[0395] In this manner, the count values ​​are read out in sequence for each pixel row, and are stored as read data in the SRAM 432. At this time, the SRAM 432 appropriately performs frame addition on the read data (addition process of the read data).

[0396] Furthermore, the read data (count value) held in the SRAM 432 is compressed based on the frequency of the photons incident on the photodiode 31, that is, the input photons.

[0397] Specifically, for example, as shown in FIG. 35, in a high-illuminance environment, the number of photons that are incident but not counted increases, causing a discrepancy between the count value stored in SRAM 432 and the count value corresponding to the actual number of incident photons.

[0398] In FIG. 35, the horizontal axis indicates the input photon frequency, and the vertical axis indicates the count value.

[0399] A curve L201 indicates the count value held in the SRAM 432, and a straight line L202 indicates the count value corresponding to the actual number of incident photons.

[0400] As can be seen from the curve L201, when the input photon frequency becomes higher, the difference between the count value obtained by the detection circuit 22 and the count value indicated by the line L202 that should be is increased. In other words, the count value obtained by the detection circuit 22 converges to a predetermined value.

[0401] Therefore, the correction processing circuit 433 performs a correction process, which converts the count value held in the SRAM 432 into the input photon frequency f, as shown by the curve L201. That is, the correction process is performed before the read data (count value) is output to the output interface circuit 434 (outside the image sensor).

[0402] Specifically, for example, the correction processing circuit 433 sets the count value as the read data to N count The count value is corrected by calculating the following equation (5) to obtain the input photon frequency f. In other words, the input photon frequency f is calculated based on the count value.

[0403]

number

[0404] In addition, in formula (5), N rcg indicates the number of times (the number of recharges) that recharges were performed at a recharge period τ0+τ1 during the exposure period T, and τ0 and τ1 indicate the length of the period to be counted.

[0405] The correction processing circuit 433 outputs the input photon frequency f obtained by the correction processing, or a count value (corrected count value) corresponding to the number of photons that would have actually been incident on the photodiode 31 and that is calculated from the input photon frequency f. The correction processing circuit 433 supplies the obtained output data to the output interface circuit 434, which outputs the data to the subsequent stage.

[0406] Eleventh embodiment <Detection circuit configuration example> For example, the counter 35 may be provided outside the detection circuit 22 as shown on the left side of FIG.

[0407] In this example, the detection circuit 22 includes a photodiode 31, a switch 32, an inverter 33, and a NAND gate .

[0408] As shown on the right side of the figure, the counter 35 is connected to a pulse detection circuit 501. Here, for example, the detection circuit 22 shown on the left side of the figure functions as the pulse detection circuit 501.

[0409] The counter 35 performs a counting operation in response to the output of the NAND gate 34, and holds the count value as a result of the counting operation.

[0410] A switch 502, a switch 503, and a control line 504 which is a reset control line are connected to the counter 35, and control such as reading of the count value from the counter 35 is performed according to the on / off state of each switch.

[0411] For example, the switch 502 and the switch 503 are provided in the read selection circuit 461 shown in Fig. 34. In this case, the read selection circuit 461 may be provided in the detection circuit 22 or outside the detection circuit 22.

[0412] The switch 502 is a circuit that reads out, for example, the most significant bit (MSB) of the count value data (bit string) held in the counter 35 as read data, that is, a circuit that selects reading.

[0413] Also, for example, switch 503 is a circuit that reads out bits other than the most significant bit of the count value data (bit string) held in counter 35 as read data, that is, a circuit that selects and reads out bits. The other bits here refer to all bits below the most significant bit of the count value data.

[0414] Furthermore, for example, a frame memory circuit that holds the read data read out via switch 502 or switch 503, i.e., the most significant bit or other bits, and an arithmetic circuit that restores the original count value based on the read data that has been read out may be provided outside the pixel (outside the pixel array unit 301).

[0415] In such a case, the frame memory circuit can be adapted to perform addition processing on the most significant bit data that has been read out.

[0416] In addition, for example, the SRAM 432 and the correction processing circuit 433 shown in FIG. 33 may function as a frame memory circuit and an arithmetic circuit that holds the read data read out via the switch 502 or the switch 503 and restores the count value.

[0417] In the example of Fig. 36, the count value changes, for example, as shown in Fig. 37. In Fig. 37, the vertical axis indicates the count value, and the horizontal axis indicates time. In this example, the count value reaches a maximum of Nmax.

[0418] In the photoelectric conversion device 11, the number of times the photodiode 31 is recharged is linked to the number of times it is counted.

[0419] Therefore, since the maximum count number of counter 35 can be determined from the number of recharges, the state of the MSB may be read out of pixel array unit 301 before the number of recharges at which the MSB transitions. The count value can be restored by counting the transition of the MSB from H(1) to L(0) outside pixel array unit 301 based on the read data and reading all bits when the exposure time T ends. This makes it possible to reduce the read power and the area of ​​counter 35.

[0420] <Application examples to electronic devices> It should be noted that the present technology is not limited to application to imaging elements (solid-state imaging devices). In other words, the present technology is applicable to imaging devices such as digital still cameras and video cameras, portable terminal devices having imaging functions, copiers using solid-state imaging devices in image reading units, and other electronic devices that use solid-state imaging devices in their image capture units (photoelectric conversion units). The solid-state imaging device may be in a form formed as a single chip, or in a form of a module having an imaging function in which the imaging unit and the signal processing unit or the optical system are packaged together.

[0421] FIG. 38 is a block diagram showing an example configuration of an imaging device as an electronic device to which the present technology is applied.

[0422] An imaging device 601 in FIG. 38 includes an optical unit 611 including a group of lenses, a solid-state imaging device (imaging device) 612 employing the configuration of the photoelectric conversion device 11, and a DSP (Digital Signal Processor) circuit 613 which is a camera signal processing circuit.

[0423] The imaging device 601 also includes a frame memory 614, a display unit 615, a recording unit 616, an operation unit 617, and a power supply unit 618. The DSP circuit 613, the frame memory 614, the display unit 615, the recording unit 616, the operation unit 617, and the power supply unit 618 are connected to each other via a bus line 619.

[0424] The optical unit 611 captures incident light (image light) from a subject and forms an image on an imaging surface of the solid-state imaging device 612. The solid-state imaging device 612 converts the amount of incident light imaged on the imaging surface by the optical unit 611 into an electrical signal on a pixel-by-pixel basis and outputs the electrical signal.

[0425] The display unit 615 is composed of a thin display such as an LCD (Liquid Crystal Display) or an organic EL (Electro Luminescence) display, and displays moving images or still images captured by the solid-state imaging device 612. The recording unit 616 records the moving images or still images captured by the solid-state imaging device 612 in a recording medium such as a hard disk or a semiconductor memory.

[0426] An operation unit 617, under the operation of a user, issues operation commands for various functions of the imaging device 601. A power supply unit 618 appropriately supplies various types of power to the DSP circuit 613, the frame memory 614, the display unit 615, the recording unit 616, and the operation unit 617 as operating power sources to these power supply targets.

[0427] <Application to moving objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, etc.

[0428] FIG. 39 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving object control system to which the technology of the present disclosure can be applied.

[0429] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 39, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also, as functional configurations of the integrated control unit 12050, a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated.

[0430] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0431] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as head lamps, back lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves or signals of various switches transmitted from a portable device that replaces a key may be input to the body system control unit 12020. The body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, and the like of the vehicle.

[0432] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for a person, a car, an obstacle, a sign, or characters on a road surface, based on the received image.

[0433] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0434] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing.

[0435] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the outside-of-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0436] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle acquired by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0437] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside-vehicle information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside-vehicle information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0438] The audio / video output unit 12052 transmits at least one output signal of audio and video to an output device capable of visually or audibly notifying information to passengers in the vehicle or the outside of the vehicle. In the example of Fig. 39, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as the output device. The display unit 12062 may include at least one of an on-board display and a head-up display, for example.

[0439] FIG. 40 is a diagram showing an example of the installation position of the imaging unit 12031.

[0440] In FIG. 40, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as an imaging unit 12031.

[0441] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The images of the front acquired by the imaging units 12101 and 12105 are mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

[0442] 40 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, an overhead image of the vehicle 12100 viewed from above is obtained by superimposing the image data captured by the imaging units 12101 to 12104.

[0443] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of a plurality of imaging elements, or may be an imaging element having pixels for detecting a phase difference.

[0444] For example, the microcomputer 12051 can extract, as a preceding vehicle, a three-dimensional object that is the closest three-dimensional object on the travel path of the vehicle 12100 and travels at a predetermined speed (for example, 0 km / h or more) in approximately the same direction as the vehicle 12100, by calculating the distance to each three-dimensional object in the imaging ranges 12111 to 12114 and the change over time of this distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104. Furthermore, the microcomputer 12051 can set a vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving that travels autonomously without relying on the driver's operation.

[0445] For example, the microcomputer 12051 classifies and extracts three-dimensional object data on three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0446] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured images of the imaging units 12101 to 12104. The recognition of such a pedestrian is performed, for example, by a procedure of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras, and a procedure of performing pattern matching processing on a series of feature points that indicate the contour of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.

[0447] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 and the like in the above-described configuration. Specifically, for example, the photoelectric conversion device 11 shown in FIG. 33 can be used as the imaging unit 12031, and power consumption can be reduced while a wide dynamic range is ensured.

[0448] Note that this technology is not limited to application to solid-state imaging devices that detect the distribution of incident visible light and capture an image, but can be applied to solid-state imaging devices in general (physical quantity distribution detection devices), such as solid-state imaging devices that capture the distribution of incident amounts of infrared rays, X-rays, particles, etc., as an image.

[0449] Furthermore, the present technology is not limited to being applicable to solid-state imaging devices, but is also applicable to semiconductor devices in general that have other semiconductor integrated circuits.

[0450] The embodiments of the present technology are not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present technology.

[0451] For example, it is possible to adopt a configuration in which all or part of the above-described multiple embodiments are combined.

[0452] Furthermore, the effects described in this specification are merely examples and are not limiting, and there may be effects other than those described in this specification.

[0453] Furthermore, the present technology can also be configured as follows.

[0454] (1) a photodiode that performs avalanche multiplication in response to incidence of photons; a pulse generating circuit that outputs a first control signal for controlling whether the photodiode is in a standby state or a recharge state, and a second control signal for controlling a detection timing of the photon; a control circuit that controls the photodiode based on the first control signal; A photoelectric conversion device comprising: (2) The photodiode is a SPAD that detects a single photon. The photoelectric conversion device according to (1). (3) The photodiode is an APD that detects a plurality of the photons. The photoelectric conversion device according to (1). (4) The photodiode is provided in a first layer of a semiconductor substrate; The control circuit is provided in a second layer different from the first layer. A photoelectric conversion device according to any one of (1) to (3). (5) The control circuit is disposed between the photodiode and a power supply, and controls a connection between the photodiode and the power supply in response to the first control signal, thereby controlling whether the photodiode is in a standby state or a recharge state. A photoelectric conversion device according to any one of (1) to (3). (6) The control circuit includes: a first switch that is disposed between the photodiode and the power supply and that is turned on or off in response to the first control signal; a second switch that is disposed between the photodiode and the first switch and that is turned on or off in response to a first control signal different from the first control signal; Possesses The photoelectric conversion device according to (5). (7) A clamp transistor is provided between the photodiode and the control circuit. A photoelectric conversion device according to (5) or (6). (8) an active quench circuit connected between the photodiode and the clamp transistor; The photoelectric conversion device according to (7). (9) The photodiode is provided in a first layer of a semiconductor substrate; the clamp transistor and the active quench circuit are provided in a second layer adjacent to the first layer; The control circuit is provided in a third layer adjacent to the second layer on the opposite side to the first layer. The photoelectric conversion device according to (8). (10) The clamp transistor further includes a bias generating circuit that is provided in the second layer or the third layer and applies a constant voltage to the clamp transistor. The photoelectric conversion device according to (9). (11) a first detection circuit connected to the photodiode and configured to output a first pulse signal when the avalanche multiplication occurs while the photodiode is in the standby state; A photoelectric conversion device according to any one of (1) to (8). (12) The first detection circuit is connected to the anode of the photodiode. The photoelectric conversion device according to (11). (13) The first detection circuit outputs the first pulse signal based on a potential between the photodiode and the first detection circuit and the first control signal. The photoelectric conversion device according to (11). (14) The power supply circuit further includes a second detection circuit that generates a second pulse signal based on the first pulse signal output from the first detection circuit and the second control signal. The photoelectric conversion device according to (11). (15) The second detection circuit detects the avalanche multiplication occurring within a first period in a recharge cycle of the photodiode and the avalanche multiplication occurring within a second period, and outputs the second pulse signal according to the detection result. The photoelectric conversion device according to (14). (16) The lengths of the first and second periods are variable. The photoelectric conversion device according to (15). (17) The second detection circuit distinguishes and detects the avalanche multiplication occurring within each of three or more periods in a recharge cycle of the photodiode based on the first pulse signal and the plurality of second control signals, and outputs the second pulse signal according to the detection result. The photoelectric conversion device according to (14). (18) The second detection circuit distinguishes and detects the avalanche multiplication occurring within each of two or more periods in a recharge cycle of the photodiode based on the first pulse signal and the second control signal, and outputs the second pulse signal according to the detection result. The photoelectric conversion device according to (14). (19) The second detection circuit has a delay element that controls resetting of the second pulse signal. The photoelectric conversion device according to (18). (20) The second detection circuit resets the second pulse signal in response to a third control signal supplied from an external device. The photoelectric conversion device according to (18). (twenty one) a first counter that counts the number of pulses of the second pulse signal output from the second detection circuit The photoelectric conversion device according to (14). (twenty two) The first counter is an up-down counter. The photoelectric conversion device according to (21). (twenty three) a second counter that counts the number of pulses of the first pulse signal output from the first detection circuit. The photoelectric conversion device according to (21). (twenty four) The photodiode is provided in a first layer of a semiconductor substrate; the first detection circuit and the second detection circuit are provided on a second layer adjacent to the first layer; The first counter is provided in a third layer adjacent to the second layer on the opposite side to the first layer. The photoelectric conversion device according to (21). (twenty five) a pixel array section provided with a plurality of detection circuits, each of the detection circuits including the photodiode, the control circuit, the first detection circuit, and the second detection circuit; One or more of the pulse generating circuits are provided for the pixel array section. The photoelectric conversion device according to (14). (26) The photodiode is provided in a first layer of a semiconductor substrate; the pulse generating circuit is provided in a second layer adjacent to the first layer; The pulse generating circuit is disposed outside the pixel array unit in a plan view. (25) A photoelectric conversion device according to (25). (27) The first control signal and the second control signal are supplied at different timings for each pixel row of pixels corresponding to the detection circuit, each pixel column of pixels, or each area of ​​a plurality of pixels. The photoelectric conversion device according to (25) or (26). (28) The first counter further includes a read selection circuit for reading out the count value of the second pulse signal held in the first counter. The photoelectric conversion device according to (21). (29) a frame memory that holds the count value read by the read selection circuit and performs an addition process on the count value, The frame memory is disposed outside a pixel array portion in which a plurality of pixels corresponding to the photodiodes are provided. The photoelectric conversion device according to (28). (30) The read selection circuit includes a circuit for reading and selecting the most significant bit of the count value, and a circuit for reading and selecting bits other than the most significant bit of the count value. The photoelectric conversion device according to (28). (31) The read selection circuit further includes a calculation circuit for restoring the count value based on the data read by the read selection circuit. The photoelectric conversion device according to (30). (32) The signal processing circuit further includes a frame memory circuit for performing addition processing on the most significant bit data that has been read out. The photoelectric conversion device according to (30) or (31). (33) a correction processing unit that calculates a frequency of the photons incident on the photodiode based on the count value of the second pulse signal held in the first counter. The photoelectric conversion device according to (21). [Explanation of symbols]

[0455] 11 photoelectric conversion device, 21 pulse generation circuit, 22 detection circuit, 31 photodiode, 32 switch, 33 inverter, 34 NAND gate, 35 counter

Claims

1. a photodiode that performs avalanche multiplication in response to incidence of photons; a pulse generating circuit that outputs a first control signal for controlling whether the photodiode is in a standby state or a recharge state, and a second control signal for controlling a detection timing of the photon; a control circuit that controls the photodiode based on the first control signal; A photoelectric conversion device comprising:

2. The photodiode is a SPAD that detects a single photon. The photoelectric conversion device according to claim 1 .

3. The photodiode is an APD that detects a plurality of the photons. The photoelectric conversion device according to claim 1 .

4. The photodiode is provided in a first layer of a semiconductor substrate, The control circuit is provided in a second layer different from the first layer. The photoelectric conversion device according to claim 1 .

5. The control circuit is disposed between the photodiode and a power supply, and controls a connection between the photodiode and the power supply in response to the first control signal, thereby controlling whether the photodiode is in a standby state or a recharge state. The photoelectric conversion device according to claim 1 .

6. The control circuit includes: a first switch that is disposed between the photodiode and the power supply and that is turned on or off in response to the first control signal; a second switch that is disposed between the photodiode and the first switch and that is turned on or off in response to a first control signal different from the first control signal; Possesses The photoelectric conversion device according to claim 5 .

7. A clamp transistor is provided between the photodiode and the control circuit. The photoelectric conversion device according to claim 5 .

8. an active quench circuit connected between the photodiode and the clamp transistor; The photoelectric conversion device according to claim 7 .

9. The photodiode is provided in a first layer of a semiconductor substrate, the clamp transistor and the active quench circuit are provided in a second layer adjacent to the first layer; The control circuit is provided in a third layer adjacent to the second layer on the opposite side to the first layer. The photoelectric conversion device according to claim 8 .

10. The clamp transistor further includes a bias generating circuit that is provided in the second layer or the third layer and applies a constant voltage to the clamp transistor. The photoelectric conversion device according to claim 9 .

11. a first detection circuit connected to the photodiode and configured to output a first pulse signal when the avalanche multiplication occurs while the photodiode is in the standby state; The photoelectric conversion device according to claim 1 .

12. The first detection circuit is connected to the anode of the photodiode. The photoelectric conversion device according to claim 11 .

13. The first detection circuit outputs the first pulse signal based on a potential between the photodiode and the first detection circuit and the first control signal. The photoelectric conversion device according to claim 11 .

14. The power supply circuit further includes a second detection circuit that generates a second pulse signal based on the first pulse signal output from the first detection circuit and the second control signal. The photoelectric conversion device according to claim 11 .

15. The second detection circuit detects the avalanche multiplication occurring within a first period in a recharge cycle of the photodiode and the avalanche multiplication occurring within a second period, and outputs the second pulse signal according to the detection result. The photoelectric conversion device according to claim 14 .

16. The lengths of the first and second periods are variable. The photoelectric conversion device according to claim 15 .

17. The second detection circuit distinguishes and detects the avalanche multiplication occurring within each of three or more periods in a recharge cycle of the photodiode based on the first pulse signal and the second control signals, and outputs the second pulse signal according to the detection result. The photoelectric conversion device according to claim 14 .

18. The second detection circuit distinguishes and detects the avalanche multiplication occurring within each of two or more periods in a recharge cycle of the photodiode based on the first pulse signal and the second control signal, and outputs the second pulse signal according to the detection result. The photoelectric conversion device according to claim 14 .

19. The second detection circuit has a delay element that controls resetting of the second pulse signal. The photoelectric conversion device according to claim 18.

20. The second detection circuit resets the second pulse signal in response to a third control signal supplied from an external device. The photoelectric conversion device according to claim 18.

21. a first counter that counts the number of pulses of the second pulse signal output from the second detection circuit The photoelectric conversion device according to claim 14 .

22. The first counter is an up-down counter. The photoelectric conversion device according to claim 21 .

23. a second counter that counts the number of pulses of the first pulse signal output from the first detection circuit. The photoelectric conversion device according to claim 21 .

24. The photodiode is provided in a first layer of a semiconductor substrate, the first detection circuit and the second detection circuit are provided on a second layer adjacent to the first layer; The first counter is provided in a third layer adjacent to the second layer on the opposite side to the first layer. The photoelectric conversion device according to claim 21 .

25. a pixel array section provided with a plurality of detection circuits, each of the detection circuits including the photodiode, the control circuit, the first detection circuit, and the second detection circuit; One or more of the pulse generating circuits are provided for the pixel array section. The photoelectric conversion device according to claim 14 .

26. The photodiode is provided in a first layer of a semiconductor substrate, the pulse generating circuit is provided in a second layer adjacent to the first layer; The pulse generating circuit is disposed outside the pixel array unit in a plan view. The photoelectric conversion device according to claim 25 .

27. The first control signal and the second control signal are supplied at different timings for each pixel row of pixels corresponding to the detection circuit, for each pixel column of pixels, or for each area of ​​a plurality of pixels. The photoelectric conversion device according to claim 25 .

28. a read selection circuit for reading out the count value of the second pulse signal held in the first counter. The photoelectric conversion device according to claim 21 .

29. a frame memory that holds the count value read by the read selection circuit and performs an addition process on the count value, The frame memory is disposed outside a pixel array portion in which a plurality of pixels corresponding to the photodiodes are provided. The photoelectric conversion device according to claim 28.

30. The read selection circuit includes a circuit for reading and selecting the most significant bit of the count value, and a circuit for reading and selecting bits other than the most significant bit of the count value. The photoelectric conversion device according to claim 28.

31. The read selection circuit further includes a calculation circuit for restoring the count value based on the data read by the read selection circuit. The photoelectric conversion device according to claim 30.

32. The signal processing circuit further includes a frame memory circuit for performing addition processing on the most significant bit data that has been read out. The photoelectric conversion device according to claim 30.

33. a correction processing unit that calculates a frequency of the photons incident on the photodiode based on the count value of the second pulse signal held in the first counter. The photoelectric conversion device according to claim 21 .

Images