Memory device

Abstract

To provide a memory device with reduced operation time.SOLUTION: A memory device of the embodiment includes a plurality of bit lines, a plurality of strings, first and second wires, a word line, and a sequencer. The plurality of strings are respectively connected to the plurality of bit lines. Each string includes a memory cell and first and second transistors. The first wire is connected to the first transistor of each of the plurality of strings. The second wire is connected to the second transistor of each of the plurality of strings. The word line is connected to the memory cell of each of the plurality of strings. The sequencer applies a first voltage to one of the first and second wires and applies a second voltage higher than the first voltage to the other of the first and second wires in a read operation of N bites (N is an integer equal to or greater than 1) in which the word line is selected. The sequencer applies a third voltage than the first voltage to each of the first and second wires in a read operation of 2×N bites in which the word line is selected.SELECTED DRAWING: Figure 20

Description

[Technical field]

[0001] The embodiments relate to a memory device. [Background technology]

[0002] 2. Description of the Related Art NAND flash memories capable of storing data in a non-volatile manner are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-072313 Summary of the Invention [Problem to be solved by the invention]

[0004] Reduce operation time. [Means for solving the problem]

[0005] A memory device according to an embodiment includes a plurality of bit lines, a plurality of strings, a first wiring, a second wiring, a word line, and a sequencer. One end of each of the plurality of strings is connected to the plurality of bit lines. Each of the plurality of strings includes a memory cell and a first and a second transistor connected in series. The first wiring is connected to a first transistor of each of the plurality of strings. The second wiring is connected to a second transistor of each of the plurality of strings. The word line is connected to a memory cell of each of the plurality of strings. The sequencer applies a first voltage to one of the first wiring and the second wiring and applies a second voltage higher than the first voltage to the other of the first wiring and the second wiring in a read operation of N bytes (N is an integer equal to or greater than 1) in which the word line is selected. The sequencer applies a third voltage higher than the first voltage to each of the first wiring and the second wiring in a read operation of 2×N bytes in which the word line is selected. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of an overall configuration of a memory device according to a first embodiment. [Diagram 2] 1 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in a memory device according to a first embodiment. [Diagram 3] 3 is a circuit diagram showing an example of a circuit configuration of a row decoder module included in the memory device according to the first embodiment. [Figure 4] 3 is a circuit diagram showing an example of a circuit configuration of a data register and a sense amplifier module included in the memory device according to the first embodiment. [Diagram 5] 3 is a circuit diagram showing an example of a circuit configuration of a sense amplifier unit included in a sense amplifier module provided in the memory device according to the first embodiment. [Figure 6] FIG. 1 is a perspective view showing an example of the appearance of a memory device according to a first embodiment. [Figure 7] FIG. 2 is a schematic diagram showing an example of a planar layout of a bonding surface of the memory device according to the first embodiment. [Figure 8] FIG. 2 is a plan view showing an example of a planar layout of a memory layer included in the memory device according to the first embodiment. [Figure 9] 3 is a plan view showing an example of a planar layout of a memory area of ​​a memory layer included in the memory device according to the first embodiment. [Figure 10] 10 is a cross-sectional view taken along line XX in FIG. 9, showing an example of a cross-sectional structure in a memory region of a memory layer included in the memory device according to the first embodiment. [Figure 11] 11 is a cross-sectional view taken along line XI-XI in FIG. 10, showing an example of a cross-sectional structure of a memory pillar included in a memory layer of the memory device according to the first embodiment. [Figure 12] 4 is a plan view showing an example of a planar layout in an extraction region of a memory layer included in the memory device according to the first embodiment. [Figure 13] 13 is a cross-sectional view taken along line XII-XIII in FIG. 12, showing an example of a cross-sectional structure in a lead-out region of a memory layer included in the memory device according to the first embodiment. [Figure 14] 1 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a first embodiment. [Figure 15] 3 is a schematic diagram showing an example of threshold voltage distribution and data allocation of memory cell transistors in the memory device according to the first embodiment. [Figure 16] 3 is a schematic diagram showing an example of a threshold voltage distribution of a select transistor in the memory device according to the first embodiment. [Figure 17] 3 is a schematic diagram showing an example of allocation of threshold voltages of select transistors in the memory device according to the first embodiment; [Figure 18] 6 is a timing chart showing an example of an even / odd bit line read operation of the memory device according to the first embodiment. [Figure 19] 5 is a schematic diagram showing an example of a bit line selection method in an even / odd bit line read operation of the memory device according to the first embodiment. [Figure 20] 6 is a timing chart showing an example of an even bit line read operation of the memory device according to the first embodiment. [Figure 21] 5 is a schematic diagram showing an example of a bit line selection method in an even bit line read operation of the memory device according to the first embodiment. [Figure 22] 6 is a timing chart showing an example of an odd-bit line read operation of the memory device according to the first embodiment. [Diagram 23] 5 is a schematic diagram showing an example of a bit line selection method in an odd-bit line read operation of the memory device according to the first embodiment. [Figure 24] FIG. 11 is a block diagram showing an example of the overall configuration of a memory device according to a second embodiment. [Diagram 25] FIG. 11 is a circuit diagram showing an example of a circuit configuration of a memory cell array included in a memory device according to a second embodiment. [Figure 26] FIG. 11 is a circuit diagram showing an example of a circuit configuration of a row decoder module included in a memory device according to a second embodiment. [Figure 27]13 is a circuit diagram showing an example of a circuit configuration of a sense amplifier unit included in a sense amplifier module provided in a memory device according to a second embodiment. [Figure 28] FIG. 11 is a perspective view showing an example of the appearance of a memory device according to a second embodiment. [Figure 29] FIG. 11 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a second embodiment. [Diagram 30] 13 is a schematic diagram showing an example of allocation of threshold voltages of select transistors in a memory device according to a second embodiment. [Diagram 31] 10 is a timing chart showing an example of a first read operation of the memory device according to the second embodiment. [Diagram 32] 13 is a schematic diagram showing an example of a method for selecting a bit line in a first read operation of the memory device according to the second embodiment. FIG. [Diagram 33] 13 is a schematic diagram showing an example of a method for selecting a bit line in a first read operation of the memory device according to the second embodiment. FIG. [Diagram 34] 10 is a timing chart showing an example of a second read operation of the memory device according to the second embodiment. [Diagram 35] 13 is a timing chart showing an example of a shield read operation of the memory device according to the second embodiment. [Diagram 36] 13 is a schematic diagram showing an example of a method for selecting a bit line in a shield read operation of a memory device according to the second embodiment. [Figure 37] 10 is a timing chart showing an overview of a write operation of a memory device according to a second embodiment. [Figure 38] 10 is a timing chart showing an example of a program operation of a write operation of a memory device according to a second embodiment. [Figure 39] 13 is a schematic diagram showing an example of a method for selecting a bit line in a program operation of a write operation of a memory device according to the second embodiment. [Diagram 40] FIG. 13 is a schematic diagram showing a modified example of bit line group allocation. [Diagram 41] 11 is a cross-sectional view showing a modified example of the structure of a memory device. [Diagram 42] FIG. 4 is a cross-sectional view showing an example of a detailed cross-sectional structure of a bonding portion of a bonding pad. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Each embodiment will be described below with reference to the drawings. Each embodiment illustrates an apparatus or method for embodying the technical idea of ​​the invention. The drawings are schematic or conceptual. The dimensions and ratios of each drawing are not necessarily the same as those in reality. The illustration of the configuration is omitted as appropriate. Hatching added to the drawings does not necessarily relate to the material or characteristics of the components. Components having approximately the same functions and configurations are assigned the same reference symbols. Numbers and the like added to the reference symbols are used to refer to the same reference symbols and to distinguish between similar elements.

[0008] <1> First embodiment The memory device 1 according to the first embodiment is a type of NAND flash memory capable of storing data in a non-volatile manner. In the memory device 1 according to the first embodiment, a plurality of bit lines are classified into two groups. The memory device 1 then performs an operation of individually selecting the two groups by using two types of selection transistors included in a NAND string. Details of the first embodiment will be described below.

[0009] <1-1> Configuration First, the configuration of a memory device 1 according to the first embodiment will be described.

[0010] <1-1-1> Overall configuration of memory device 1 Fig. 1 is a block diagram showing an example of an overall configuration of a memory device 1 according to the first embodiment. As shown in Fig. 1, the memory device 1 is controlled by an external memory controller 2. The memory device 1 includes, for example, a memory cell array 10, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, a data register 17, and a sense amplifier module 18.

[0011] The memory cell array 10 is a set of multiple memory cells. The memory cell array 10 includes multiple blocks BLK0 to BLKn ("n" is an integer equal to or greater than 1). The block BLK corresponds to, for example, a unit of data erasure and includes multiple pages. The page corresponds to a unit in which data is read and written. The memory cell array 10 is provided with multiple bit lines BL0 to BLm ("m" is an integer equal to or greater than 1) and multiple word lines WL (not shown). Each memory cell is associated with a pair of the bit line BL and the word line WL. When multiple memory cells are associated with a pair of the bit line BL and the word line WL, these multiple memory cells are configured to be individually accessible by a selection transistor.

[0012] The input / output circuit 11 is an interface circuit that controls transmission and reception (input / output) of input / output signals with the memory controller 2. The input / output signals include, for example, data DAT, status information, addresses, commands, etc. The input / output circuit 11 can input and output data DAT between the data register 17 and the memory controller 2. The input / output circuit 11 can output status information transferred from the register circuit 13 to the memory controller 2. The input / output circuit 11 can output each of the addresses and commands transferred from the memory controller 2 to the register circuit 13.

[0013] The logic controller 12 is a controller that controls each of the input / output circuit 11 and the sequencer 14 based on a control signal input from the memory controller 2. The logic controller 12 instructs the input / output circuit 11 to input a signal from the memory controller 2 or to output a signal to the memory controller 2. In addition, the logic controller 12 notifies the input / output circuit 11 of the type of the input / output signal received by the input / output circuit 11 (for example, any one of data DAT, a command, and an address).

[0014] The register circuit 13 is a circuit that temporarily stores a status, an address, and a command. The status is information indicating the operating state of the memory device 1. The status is updated based on the control of the sequencer 14, and is transferred to the memory controller 2 via the input / output circuit 11. The address may include a block address, a page address, a column address, etc. The command includes an instruction related to various operations of the memory device 1.

[0015] The sequencer 14 is a controller that controls the overall operation of the memory device 1. The sequencer 14 executes a read operation, a write operation, an erase operation, and the like, based on the commands and addresses stored in the register circuit 13.

[0016] The driver circuit 15 is a circuit that generates voltages used in read operations, write operations, erase operations, etc. The driver circuit 15 supplies the generated voltages to the row decoder module 16, the sense amplifier module 18, and the like.

[0017] The row decoder module 16 is a circuit used to select a block BLK to be subjected to an operation such as a read operation, and to transfer a voltage to wiring such as a word line WL. The row decoder module 16 includes a plurality of row decoders RD0 to RDn. The row decoders RD0 to RDn are associated with the blocks BLK0 to BLKn, respectively. A detailed configuration of the row decoder RD will be described later.

[0018] The data register 17 is a circuit that temporarily stores the data DAT. The data register 17 can input and output the data DAT between the input / output circuit 11 and each of the sense amplifier modules 18. The data register 17 may be called a cache memory.

[0019] The sense amplifier module 18 is a circuit used for transferring a voltage to each bit line BL and reading data. The sense amplifier module 18 includes a plurality of sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are associated with a plurality of bit lines BL0 to BLm, respectively. A detailed configuration of the sense amplifier units SAU will be described later.

[0020] The memory device 1 and the memory controller 2 may be combined to form one semiconductor device. TM Examples of the memory device 1 include a memory card such as a card, and a solid state drive (SSD). A set of the memory cell array 10, the row decoder module 16, and the sense amplifier module 18 is called, for example, a "plane." The memory device 1 may include multiple planes.

[0021] <1-1-2> Circuit configuration of memory device 1 The circuit configuration of the memory device 1 according to the first embodiment will be described below. Hereinafter, a MOS transistor with a high withstand voltage is called an "HV (High-Voltage) transistor." A MOS transistor with a lower withstand voltage than an HV transistor is called an "LV (Low-Voltage) transistor." For example, an LV transistor has a thinner gate insulating film than an HV transistor, and can operate faster than an HV transistor.

[0022] (1: Circuit configuration of memory cell array 10) FIG. 2 is a circuit diagram showing an example of a circuit configuration of a memory cell array 10 included in the memory device 1 according to the first embodiment. FIG. 2 shows one block BLK among a plurality of blocks BLK included in the memory cell array 10. As shown in FIG. 2, select gate lines SGD0 to SGD4, SGe, and SGo, word lines WL0 to WL(k-1) (k is an integer of 2 or more), a select gate line SGS, bit lines BL0 to BLm, and a source line SL are connected to the block BLK. The select gate lines SGD0 to SGD4, select gate lines SGe and SGo, word lines WL0 to WL(k-1), and select gate line SGS are provided for each block BLK. The bit lines BL0 to BLm and the source line SL can be shared by a plurality of blocks BLK.

[0023] The block BLK includes, for example, five string units SU0 to SU4. Each string unit SU includes NAND strings NS0 to NSm. The NAND strings NS0 to NSm are associated with bit lines BL0 to BLm, respectively. Each NAND string NS is connected between the associated bit line BL and a source line SL. Each bit line BL is shared by NAND strings NS to which the same column address is assigned among multiple blocks BLK.

[0024] Each NAND string NS includes, for example, a selection transistor STD, selection transistors STe and STo, k memory cell transistors MT0 to MT(k-1), and a selection transistor STS. In each NAND string NS, the selection transistors STD, STe, and STo, the memory cell transistors MT(k-1) to MT0, and the selection transistor STS are connected in series in this order. In each NAND string NS, the drain of the selection transistor STD is connected to the associated bit line BL, and the source of the selection transistor STS is connected to the source line SL.

[0025] Each memory cell transistor MT has a control gate and a charge storage layer, and holds (stores) data in a non-volatile manner. The memory cell transistor MT may be a charge trap type memory cell or a floating gate type memory cell. The selection transistors STD and STS are used to select the string unit SU. Each of the selection transistors STe and STo may have a structure similar to that of the memory cell transistor MT, and may be called a memory cell. The selection transistors STe and STo are used to select a group of bit lines BL. In the first embodiment, an example will be described in which, among the multiple bit lines BL0 to BLm, an even bit line group including even bit lines BLe (BL0, BL2, BL4, ...) and an odd bit line group including odd bit lines BLo (BL1, BL3, BL5, ...) are configured to be individually selectable.

[0026] The select gate lines SGD0 to SGD4 are associated with the string units SU0 to SU4, respectively. Each select gate line SGD is connected to a gate terminal of each of the select transistors STD included in the associated string unit SU. The select gate line SGe is connected to a gate terminal of each of the select transistors STe included in the block BLK. The select gate line SGo is connected to a gate terminal of each of the select transistors STo included in the block BLK. The select gate line SGS is connected to a gate terminal of each of the select transistors STS included in the block BLK. The word lines WL0 to WL(k-1) are connected to the control gate terminals of each of the memory cell transistors MT0 to MT(k-1) included in the block BLK, respectively.

[0027] A set of multiple memory cell transistors MT included in the same string unit SU and connected to the same word line WL is called, for example, a "cell unit CU." For example, the storage capacity of a cell unit CU when each memory cell transistor MT stores one bit of data is defined as "one page of data." One page of data is, for example, 16 KB (kilobytes). The size of one page of data can be changed as appropriate depending on the design of the memory device 1. Furthermore, the cell unit CU can store two or more pages of data depending on the number of bits of data stored in each memory cell transistor MT.

[0028] The memory cell array 10 may have other circuit configurations. The selection transistors STe and STo may not be adjacent to each other, may be arranged on the selection gate line SGS side, or may be arranged in the middle of the NAND string NS. The selection transistors STe and STo may be designed to have any number, for example, the number of string units SU included in the block BLK, and the number of memory cell transistors MT and selection transistors STD, STS, STe, and STo included in the NAND string NS. In the first embodiment, a case where the number of memory cell transistors MT included in the NAND string NS is six will be described as an example.

[0029] (2: Circuit configuration of row decoder module 16) FIG. 3 is a circuit diagram showing an example of a circuit configuration of the row decoder module 16 included in the memory device 1 according to the first embodiment. FIG. 3 shows the connection relationship between the driver circuit 15 and the memory cell array 10 and the row decoder module 16, and a detailed circuit configuration of one row decoder RD0 included in the row decoder module 16. The circuit configurations of the row decoders RD other than the row decoder RD0 are the same as the row decoder RD0, except for the associated block BLK. As shown in FIG. 3, each row decoder RD is connected to signal lines CG0 to CG5, SGDD0 to SGDD4, SGSD, SGeD, SGoD, USGD, and USGS connected to the driver circuit 15. In addition, each row decoder RD is connected to word lines WL0 to WL5 of the associated block BLK, and select gate lines SGD0 to SGD4, SGe, SGo, and SGS.

[0030] The row decoder RD0 includes, for example, transistors TR0 to TR19, transfer gate lines TG and bTG, and a block decoder BD. Each of the transistors TR0 to TR19 is an N-type HV transistor. The transfer gate line TG is connected to the gate terminal of each of the transistors TR0 to TR13. The transfer gate line bTG is connected to the gate terminal of each of the transistors TR14 to TR19. The drain terminals of the transistors TR0 to TR13 are connected to signal lines SGSD, CG0 to CG5, SGoD, SGeD, and SGDD0 to SGDD4, respectively. The source terminals of the transistors TR0 to TR13 are connected to the select gate line SGS of the block BLK0, the word lines WL0 to WL5, and the select gate lines SGo, SGe, and SGD0 to SGD4, respectively. The drain terminal and the source terminal of the transistor TR14 are connected to the signal line USGS and the select gate line SGS of the block BLK0, respectively. The drain terminals of the transistors TR15 to TR19 are connected to a signal line USGD, and the source terminals of the transistors TR15 to TR19 are connected to the select gate lines SGD0 to SGD4 of the block BLK0, respectively.

[0031] The block decoder BD is a circuit that decodes a block address. Based on the decoded result of the block address, the block decoder BD applies one of a voltage of "H" level and a voltage of "L" level to the transfer gate line TG, and applies the other voltage of "H" level and a voltage of "L" level to the transfer gate line bTG. Specifically, the block decoder BD of a selected block BLK applies a voltage of "H" level and a voltage of "L" level to the transfer gate lines TG and bTG, respectively. The block decoder BD of an unselected block BLK applies a voltage of "L" level and a voltage of "H" level to the transfer gate lines TG and bTG, respectively. As a result, the voltages of the signal lines CG0 to CG5, SGoD and SGeD are transferred to the word lines WL0 to WL5 and select gate lines SGo and SGe, respectively, of the selected block BLK, the voltages of the signal lines SGDD0 to SGDD4 and SGSD are transferred to the select gate lines SGD0 to SGD4 and SGS, respectively, of the selected block BLK, and the voltages of the signal lines USGD and USGS are transferred to the select gate lines SGD and SGS, respectively, of the unselected block BLK.

[0032] The row decoder module 16 may have other circuit configurations. For example, the number of transistors TR included in the row decoder module 16 may be appropriately changed according to the number of wirings in each block BLK. The signal line CG may be called a "global word line" because it is shared by multiple blocks BLK. The word line WL may be called a "local word line" because it is provided for each block. Each of the signal lines SGDD, SGeD, SGoD, and SGSD may be called a "global transfer gate line" because it is shared by multiple blocks BLK. Each of the select gate lines SGD, SGe, SGo, and SGS may be called a "local transfer gate line" because it is provided for each block.

[0033] (3: Circuit configuration of sense amplifier module 18 and data register 17) 4 is a circuit diagram showing an example of a circuit configuration of the sense amplifier module 18 and the data register 17 included in the memory device 1 according to the first embodiment. As shown in FIG. 4, each sense amplifier unit SAU includes, for example, a bit line connection unit BLHU, a sense amplifier unit SA, buses DBUS and LBUS, latch circuits SDL, ADL, BDL and CDL, and a transistor T0. The data register 17 includes, for example, a plurality of latch circuits XDL0 to XDLm. The latch circuits XDL0 to XDLm are associated with the sense amplifier units SAU0 to SAUm, respectively. Each of the latch circuits XDL0 to XDLm is connected to the associated sense amplifier unit SAU via the bus DBUS.

[0034] The bit line connection unit BLHU is, for example, a protection circuit that prevents a high voltage applied to the channel of the NAND string NS during an erase operation from being applied to the sense amplifier unit SA. The bit line connection unit BLHU may be configured to be able to apply a predetermined voltage to unselected bit lines BL.

[0035] The sense amplifier unit SA is a circuit used to determine data based on the voltage of the bit line BL and to apply a voltage to the bit line BL. Each sense amplifier unit SA is connected to the associated bit line BL via a bit line connection unit BLHU. When a control signal STB is asserted during a read operation, the sense amplifier unit SA determines whether the data read from the selected memory cell transistor MT is "0" data or "1" data based on the voltage of the associated bit line BL.

[0036] Each of the latch circuits SDL, ADL, BDL, and CDL is a circuit capable of temporarily holding data. The latch circuits SDL, ADL, BDL, and CDL, and the sense amplifier unit SA are configured to be capable of transmitting and receiving data via a bus LBUS.

[0037] The transistor T0 of each sense amplifier unit SAU controls the transfer of signals between the associated buses DBUS and LBUS. One end of the transistor T0 of each sense amplifier unit SAU is connected to the associated bus DBUS. The other end of the transistor T0 of each sense amplifier unit SAU is connected to the associated bus LBUS. A control signal DSW is input to the gate end of the transistor T0 of each sense amplifier unit. The control signal DSW is generated by, for example, the sequencer 14.

[0038] Each latch circuit XDL is a circuit capable of temporarily holding data. Each latch circuit XDL is configured to be capable of transmitting and receiving data to and from an associated sense amplifier unit SAU via a bus DBUS. Each latch circuit XDL is used for inputting and outputting data DAT between the sense amplifier module 18 and the input / output circuit 11. Each latch circuit XDL may be shared by multiple sense amplifier units SAU.

[0039] (4: Circuit configuration of the sense amplifier unit SAU) FIG. 5 is a circuit diagram showing an example of a circuit configuration of a sense amplifier unit SAU included in a sense amplifier module 18 included in the memory device 1 according to the first embodiment. As shown in FIG. 5, the sense amplifier section SA includes, for example, transistors T1 to T8, a capacitor CP, and nodes ND1, ND2, SEN, and SRC. The bit line connection section BLHU includes, for example, transistors T9 and T10, and a node BLBIAS. The latch circuit SDL includes, for example, inverters IV0 and IV1, transistors T11 and T12, and nodes SINV and SLAT. The transistor T1 is a P-type LV transistor. Each of the transistors T2 to T8, T11, and T12 is an N-type LV transistor. Each of the transistors T9 and T10 is an N-type HV transistor.

[0040] The source terminal, drain terminal, and gate terminal of the transistor T1 are connected to a power line, a node ND1, and a node SINV, respectively. For example, a power supply voltage VDD is applied to the power line. The drain terminal and source terminal of the transistor T2 are connected to nodes ND1 and ND2, respectively. A control signal BLX is input to the gate terminal of the transistor T2. The drain terminal and source terminal of the transistor T3 are connected to nodes ND1 and SEN, respectively. A control signal HLL is input to the gate terminal of the transistor T3. The drain terminal and source terminal of the transistor T4 are connected to nodes SEN and ND2, respectively. A control signal XXL is input to the gate terminal of the transistor T4. The drain terminal of the transistor T5 is connected to the node ND2. A control signal BLC is input to the gate terminal of the transistor T5. The drain terminal, source terminal, and gate terminal of the transistor T6 are connected to nodes ND2, SRC, and SINV, respectively. For example, a ground voltage VSS is applied to the node SRC. The source terminal and gate terminal of the transistor T7 are connected to the ground node and the node SEN, respectively. For example, a ground voltage VSS is applied to the ground node. The drain terminal and source terminal of the transistor T8 are connected to the bus LBUS and the drain terminal of the transistor T7, respectively. A control signal STB is input to the gate terminal of the transistor T8. One electrode of the capacitor CP is connected to the node SEN. A clock signal CLK is input to the other electrode of the capacitor CP.

[0041] The drain and source terminals of transistor T9 are connected to the source terminal of transistor T8 and the associated bit line BL, respectively. A control signal BLS is input to the gate terminal of transistor T9. The drain and source terminals of transistor T10 are connected to node BLBIAS and the associated bit line BL, respectively. A control signal BIAS is input to the gate terminal of transistor T10.

[0042] One end and the other end of the transistor T11 are connected to the bus LBUS and the node SINV, respectively. A control signal STI is input to the gate end of the transistor T11. One end and the other end of the transistor T12 are connected to the bus LBUS and the node SLAT, respectively. A control signal STL is input to the gate end of the transistor T12. An input node and an output node of the inverter IV0 are connected to the nodes SLAT and SINV, respectively. An input node and an output node of the inverter IV1 are connected to the nodes SINV and SLAT, respectively. The latch circuit SDL holds data in the node SLAT and holds inverted data of the data held in the node SLAT in the node SINV. The configurations of the latch circuits ADL, BDL, and CDL are the same as the latch circuit SDL, except that the node for holding data, the node for holding inverted data, and the control signals input to the transistors T11 and T12 are prepared independently of the latch circuit SDL.

[0043] The control signals BLX, HLL, XXL, BLC, STB, BLS, BIAS, STI, and STL, and the clock signal CLK are each generated by, for example, the sequencer 14. The sense amplifier module 18 may have other circuit configurations. For example, the number of latch circuits provided in each sense amplifier unit SAU may be changed as appropriate. The sense amplifier unit SAU may have an arithmetic circuit capable of executing simple logical operations. In a read operation of each page, the sense amplifier module 18 may determine (determine) the data stored in the memory cell transistor MT by appropriately executing an arithmetic process using the latch circuit.

[0044] In the following, the sense amplifier unit SAU connected to the even bit line BLe is referred to as the "sense amplifier unit SAUe". The sense amplifier unit SAU connected to the odd bit line BLo is referred to as the "sense amplifier unit SAUo". In the first embodiment, the sequencer 14 is configured to be able to individually control the control signal BLC used to control the sense amplifier unit SAUe and the control signal BLC used to control the sense amplifier unit SAUo. In the following, the control signal BLC used to control the sense amplifier unit SAUe is referred to as the "control signal BLCe". The control signal BLC used to control the sense amplifier unit SAUo is referred to as the "control signal BLCo".

[0045] <1-1-3> Structure of memory device 1 The structure of the memory device 1 according to the first embodiment will be described below. In the drawings referred to below, a three-dimensional Cartesian coordinate system is used. The X direction corresponds to the extension direction of the word lines WL. The Y direction corresponds to the extension direction of the bit lines BL. The Z direction corresponds to the vertical direction with respect to the surface of the substrate as a reference. The XZ plane corresponds to a plane parallel to each of the X and Z directions. In this specification, "upper and lower" are defined based on the Z direction, and the direction away from the substrate as a reference is the positive direction (upward). As the substrate as a reference, for example, the substrate arranged at the bottom in the drawings is used. The front surface of the substrate corresponds to the surface on the side on which the transistors (CMOS circuits) are formed. The back surface of the substrate corresponds to the surface opposite to the front surface.

[0046] (1: Appearance of memory device 1) Fig. 6 is a perspective view showing an example of the appearance of the memory device 1 according to the first embodiment. As shown in Fig. 6, the memory device 1 has a structure in which, for example, a first substrate W1, a CMOS layer 100, a memory layer 200, a second substrate W2, and a wiring layer 300 are stacked in this order from the bottom.

[0047] The CMOS layer 100 includes a CMOS circuit formed by using the first substrate W1. The CMOS layer 100 includes, for example, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15, a row decoder module 16, a data register 17, and a sense amplifier module 18. The memory layer 200 includes a memory cell array 10 formed by using the second substrate W2. The wiring layer 300 includes, for example, a plurality of pads PD. The plurality of pads PD are used to connect the memory device 1 and the memory controller 2, and are exposed on the surface of the memory device 1.

[0048] Each of the first substrate W1 and the second substrate W2 is a silicon substrate. The first substrate W1 has an impurity diffusion region according to the circuit design of the memory device 1. The memory device 1 has a bonding surface between the CMOS layer 100 and the memory layer 200. The bonding surface corresponds to the boundary portion of the two bonded substrates. In this example, the bonding process of the first substrate W1 and the second substrate W2 bonds the surface of the CMOS layer 100 on the first substrate W1 to the surface of the memory layer 200 on the second substrate W2. The second substrate W2 may be removed after the first substrate W1 and the second substrate W2 are bonded. In this case, the memory device 1 does not have the second substrate W2.

[0049] (2: Planar layout of the joint surface) Fig. 7 is a schematic diagram showing an example of a planar layout of a junction surface of the memory device 1 according to the first embodiment. Fig. 7 shows a planar layout of the junction surface between the CMOS layer 100 and the memory layer 200. As shown in Fig. 7, the memory layer 200 includes, for example, a memory region MR, lead-out regions HR1 and HR2, and an input / output region IOR1. The CMOS layer 100 includes, for example, a sense amplifier region SR, a peripheral circuit region PERI, transfer regions XR1 and XR2, and an input / output region IOR2.

[0050] The memory region MR is used for storing data and includes a plurality of NAND strings NS. The lead-out regions HR1 and HR2 sandwich the memory region MR in the X direction. The lead-out region HR is used for connection between stacked wiring provided in the memory region MR and transistors provided in the transfer region XR opposite to the memory region MR in the Z direction. The input / output region IOR1 is adjacent to the memory region MR and each of the lead-out regions HR1 and HR2 in the Y direction. The input / output region IOR1 includes circuits related to the input / output circuit 11.

[0051] The sense amplifier region SR includes a sense amplifier module 18. The peripheral circuit region PERI includes a sequencer 14 and the like. The sense amplifier region SR and the peripheral circuit region PERI are arranged adjacent to each other in the Y direction and overlap with the memory region MR in the Z direction. The transfer regions XR1 and XR2 include a row decoder module 16. The transfer regions XR1 and XR2 sandwich the set of the sense amplifier region SR and the peripheral circuit region PERI in the X direction, and overlap with the pull-out regions HR1 and HR2, respectively, in the Z direction. The input / output region IOR2 includes an input / output circuit 11 and the like. The input / output region IOR2 overlaps with the input / output region IOR1 in the Z direction.

[0052] The memory layer 200 has a plurality of bonding pads BP in contact with the bonding surface. Similarly, the CMOS layer 100 has a plurality of bonding pads BP in contact with the bonding surface. The plurality of bonding pads BP provided on the bonding surface of the memory layer 200 are disposed opposite the plurality of bonding pads BP provided on the bonding surface of the CMOS layer 100. A pair of two bonding pads BP disposed opposite each other between the memory layer 200 and the CMOS layer 100 are bonded by a bonding process ("bonding" in FIG. 7). This allows electrical connection between the two bonding pads BP disposed opposite each other.

[0053] The planar layout of the bonding surface of the memory device 1 may be other layouts. For example, at least one lead-out region HR may be provided. The memory device 1 may have a plurality of memory regions MR. The arrangement of the memory region MR, lead-out region HR, sense amplifier region SR, peripheral circuit region PERI, transfer region XR, and input / output region IOR may be changed as appropriate. The bonding pad BP may be called a "bonding metal."

[0054] (3: Planar layout of memory layer 200) Fig. 8 is a plan view showing an example of a planar layout of the memory layer 200 included in the memory device 1 according to the first embodiment. Fig. 8 shows areas corresponding to four blocks BLK0 to BLK3 included in the memory cell array 10. As shown in Fig. 8, the memory cell array 10 includes, for example, a plurality of slits SLT and a plurality of slits SHE.

[0055] Each slit SLT has a portion extending along the X direction, and crosses the lead-out region HR1, the memory region MR, and the lead-out region HR2 along the X direction. The multiple slits SLT are aligned in the Y direction. Each slit SLT has a structure in which an insulator is embedded, for example. Each slit SLT divides adjacent wiring (for example, word lines WL0 to WL5 and select gate lines SGD, SGe, SGo, and SGS) through the slit SLT. In the memory cell array 10, each of the regions separated by the slits SLT corresponds to one block BLK.

[0056] Each slit SHE has a portion extending along the X direction and crosses the memory region MR along the X direction. The multiple slits SHE are aligned in the Y direction. In this example, four slits SHE are arranged between each pair of adjacent slits SLT in the Y direction. Each slit SHE has, for example, a structure in which an insulator is embedded. Each slit SHE divides adjacent wiring (at least the selection gate line SGD) via the slit SHE. In the memory cell array 10, each of the regions partitioned by the slits SLT and SHE corresponds to one string unit SU.

[0057] The planar layout of the memory layer 200 may be other layouts. For example, the number of slits SHE arranged between two adjacent slits SLT may be designed to be any number. The number of string units SU included in each block BLK may be changed based on the number of slits SHE arranged between two adjacent slits SLT.

[0058] (4: Planar layout of memory area MR) Fig. 9 is a plan view showing an example of a planar layout in a memory region MR of a memory layer 200 included in the memory device 1 according to the first embodiment. Fig. 9 shows a region including one block BLK (string units SU0 to SU4). As shown in Fig. 9, the memory device 1 includes, for example, a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL in the memory region MR.

[0059] Each memory pillar MP functions as one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 24 rows in the region between two adjacent slits SLT. For example, counting from the top of the page, one slit SHE is arranged to overlap the fifth memory pillar MP, the tenth memory pillar MP, the fifteenth memory pillar MP, and the twentieth memory pillar MP.

[0060] Each bit line BL has a portion extending in the Y direction. The multiple bit lines BL are aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In this example, two bit lines BL are arranged to overlap one memory pillar MP. The memory pillar MP is electrically connected to one bit line BL of the multiple overlapping bit lines BL via a contact CV. Note that the contact CV between the memory pillar MP and the bit line BL in contact with two different selection gate lines SGD may be omitted.

[0061] The planar layout of the memory region MR may be other layouts. For example, the number and arrangement of the memory pillars MP and slits SHE arranged between two adjacent slits SLT may be changed as appropriate. The number of bit lines BL overlapping each memory pillar MP may be designed to be any number.

[0062] (5: Cross-sectional structure of memory area MR) Fig. 10 is a cross-sectional view taken along line XX in Fig. 9, showing an example of a cross-sectional structure in the memory region MR of the memory layer 200 included in the memory device 1 according to the first embodiment. Fig. 10 shows an example of the structure of the memory cell array 10 formed on the second substrate W2 before being bonded to the first substrate W1, and shows coordinate axes based on the second substrate W2. As shown in Fig. 10, the memory region MR includes, for example, conductor layers 20-28, insulator layers 30-37, and contacts V0 and V1.

[0063] The conductor layer 20 is provided on the second substrate W2. An insulator layer 30 and a conductor layer 21 are provided on the conductor layer 20 in this order. An insulator layer 31 and a conductor layer 22 are provided alternately on the conductor layer 21. An insulator layer 32, a conductor layer 23, an insulator layer 33, a conductor layer 24, an insulator layer 34, a conductor layer 25, an insulator layer 35, and a conductor layer 26 are provided on the uppermost conductor layer 22 in this order. A contact V0 is provided on the conductor layer 26. A conductor layer 27 is provided on the contact V0. A contact V1 is provided on the conductor layer 27. A conductor layer 28 is provided on the contact V1. The contact V0, the conductor layer 27, and the contact V1 are covered by an insulator layer 36. The insulator layer 36 may be composed of a plurality of insulator layers. An insulator layer 37 is provided on the insulator layer 36. Hereinafter, the layers at the height where the conductor layers 26 and 27 are provided are referred to as wiring layers M0 and M1, respectively. The layer at the height where the conductor layer 28 and the insulator layer 37 are provided is referred to as a "bonding layer B1."

[0064] Each of the conductive layers 21, 22, 23, 24, and 25 is formed, for example, in a plate shape extending along the XY plane. The conductive layer 26 is formed, for example, in a line shape extending in the Y direction. The conductive layers 20, 21, 23, 24, and 25 are used as the source line SL and the select gate lines SGS, SGo, SGe, and SGD, respectively. The conductive layers 22 are used, in order from the bottom, as the word lines WL0 to WL5, respectively. The conductive layer 26 is used as the bit line BL. The contacts V0 and V1 are provided in a columnar shape. The conductive layers 26 and 27 are connected to each other via the contact V0. The conductive layer 27 and the conductive layer 28 are connected to each other via the contact V1. The conductive layer 28 corresponds to the bonding pad BP. The conductive layer 28 includes, for example, copper.

[0065] The slit SLT has a plate-shaped portion extending along the XZ plane, and divides the insulating layers 30 to 34 and the conductive layers 21 to 25. Each memory pillar MP is provided extending along the Z direction, and penetrates the insulating layers 30 to 34 and the conductive layers 21 to 25. Each memory pillar MP includes, for example, a core member 40, a semiconductor layer 41, and a laminated film 42. The core member 40 is an insulator provided extending along the Z direction. The semiconductor layer 41 covers the core member 40. The lower portion of the semiconductor layer 41 is in contact with the conductive layer 20. The laminated film 42 covers the side surface of the semiconductor layer 41. A contact CV is provided on the semiconductor layer 41. The semiconductor layer 41 and the conductive layer 26 are connected to each other via the contact CV.

[0066] The intersection of the memory pillar MP and the conductive layer 21 functions as a select transistor STS. The intersection of the memory pillar MP and the conductive layer 22 functions as a memory cell transistor MT. The intersection of the memory pillar MP and the conductive layer 23 functions as a select transistor STo. The intersection of the memory pillar MP and the conductive layer 24 functions as a select transistor STe. The intersection of the memory pillar MP and the conductive layer 25 functions as a select transistor STD. In the memory pillar MP, the semiconductor layer 41 is used as a channel (current path) of the memory cell transistors MT0 to MT5 and the select transistors STD, STe, STo, and STS.

[0067] (6: Cross-sectional structure of memory pillar MP) FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 10, showing an example of a cross-sectional structure of a memory pillar MP included in the memory layer 200 of the memory device 1 according to the first embodiment. FIG. 11 shows a cross section including the memory pillar MP and the conductive layer 22 and parallel to the surface of the source line SL. As shown in FIG. 11, the stacked film 42 includes, for example, a tunnel insulating film 43, an insulating film 44, and a block insulating film 45. The tunnel insulating film 43 surrounds the side surface of the semiconductor layer 41. The insulating film 44 surrounds the side surface of the tunnel insulating film 43. The block insulating film 45 surrounds the side surface of the insulating film 44. The conductive layer 22 surrounds the side surface of the block insulating film 45. Each of the tunnel insulating film 43 and the block insulating film 45 includes, for example, silicon oxide. The insulating film 44 is used as a charge storage layer of the memory cell transistor MT. The insulating film 44 includes, for example, silicon nitride.

[0068] (7: Planar layout of pull-out area HR1) Fig. 12 is a plan view showing an example of a planar layout in the lead-out region HR1 of the memory layer 200 included in the memory device 1 according to the first embodiment. Fig. 12 shows a region including the lead-out region HR1 and a part of the memory region MR, and corresponding to the even blocks BLKe (BLK0, BLK2, ...) of the multiple blocks BLK. As shown in Fig. 12, in the lead-out region HR1, the ends of the select gate lines SGS, word lines WL0 to WL5, and select gate lines SGo, SGe, and SGD of the even blocks BLKe have terrace portions.

[0069] The terrace portion corresponds to a portion of the stacked wiring that does not overlap with an upper wiring layer (conductive layer). A structure formed by a plurality of terrace portions is similar to a step, a terrace, a rimstone, etc. In this example, a step structure having steps in the X direction is formed by the select gate line SGS, the word lines WL0 to WL5, and the ends of the select gate lines SGo, SGe, and SGD.

[0070] The memory layer 200 also includes a plurality of contacts CC in the lead-out region HR. The contacts CC are conductors used for connection between the row decoder module 16 and stacked wiring. The plurality of contacts CC associated with the even block BLKe are respectively connected to the select gate lines SGS, SGo, SGe, and SGD and the terrace portions of the word lines WL0 to WL5 provided in the lead-out region HR1.

[0071] (8: Cross-sectional structure of the extraction region HR1) Fig. 13 is a cross-sectional view taken along line XIII-XIII in Fig. 12, showing an example of a cross-sectional structure in the lead-out region HR1 of the memory layer 200 included in the memory device 1 according to the first embodiment. Fig. 13 shows an example of the structure of the memory cell array 10 formed on the second substrate W2 before being bonded to the first substrate W1, and shows coordinate axes based on the second substrate W2. As shown in Fig. 13, the lead-out region HR1 includes, for example, a plurality of contacts CC, a plurality of contacts V0 and V1, a plurality of conductor layers 27-29, and insulator layers 35-37.

[0072] In the lead-out region HR1, each end of the conductor layers 21-25 is provided in a stepped shape and covered with an insulating layer 35. A plurality of contacts CC are provided on the terrace portions of the select gate line SGS, the word lines WL0-WL5, and the select gate lines SGo, SGe, and SGD. Each contact CC penetrates the insulating layer 35. One conductor layer 29 is provided on each of the plurality of contacts CC. The conductor layer 29 is included in the wiring layer M0.

[0073] Each conductive layer 29 is connected to the corresponding conductive layer 28 via a contact V0, a ​​conductive layer 27, and a contact V1. FIG. 13 shows the contacts V0 and V1 corresponding to the select gate line SGS among the multiple contacts V0, and the conductive layers 27 and 28. The pairs of the conductive layers 27, 28, and 29 and the contacts CC, V0, and V1 correspond to wiring and contacts for connecting any of the conductive layers 21 to 25 to the row decoder module 16. Although not shown in the figure, each of the conductive layers 22 to 25 is connected to the row decoder module 16 via the pairs of the corresponding conductive layers 27, 28, and 29 and the contacts CC, V0, and V1, similar to the conductive layer 21.

[0074] In this example, the layout and cross-sectional structure of the overlapping portion between the lead-out region HR2 and the even-numbered blocks BLKo (BLK1, BLK3, ...) among the multiple blocks BLK are the same as the layout and cross-sectional structure of the overlapping portion between the lead-out region HR1 and the even-numbered blocks BLKe, which is inverted in the X direction. The planar layout of the lead-out region HR is not limited to this, and may be changed as appropriate. The lead-out region HR may be arranged to divide the memory region MR. The lead-out region HR may include at least a plurality of contacts CC and wirings that connect the row decoder module 16 and the stacked wiring.

[0075] (9: Cross-sectional structure of memory device 1) 14 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1 according to the first embodiment. FIG. 14 shows a cross section including the memory region MR and the lead-out region HR1 in the memory device 1, and shows coordinate axes based on the first substrate W1. FIG. 14 also shows a configuration corresponding to the transistor T9 in the sense amplifier region SR and a configuration corresponding to the transistor TR1 in the transfer region XR2. As shown in FIG. 14, the memory device 1 has a structure in which the structure of the memory region MR shown in FIG. 10 and the structure of the lead-out region HR1 shown in FIG. 13 are respectively inverted upside down in correspondence with the memory layer 200.

[0076] The first substrate W1 includes a plurality of well regions (not shown). A transistor and the like are formed in each of the plurality of well regions. The plurality of well regions are isolated from each other by, for example, shallow trench isolation (STI).

[0077] The CMOS layer 100 includes, for example, insulator layers 50 and 51, conductor layers GC and 52 to 55, and contacts CS and C0 to C3. The insulator layer 50 is provided on the first substrate W1. The insulator layer 50 covers the circuit provided on the first substrate W1. The insulator layer 50 may be composed of a plurality of insulator layers. The insulator layer 50 includes, in order from the bottom, wiring layers D0, D1, and D2. The insulator layer 51 is provided on the insulator layer 50. The insulator layer 51 is in contact with the insulator layer 35. The boundary between the insulator layers 51 and 35 corresponds to the bonding surface between the first substrate W1 and the second substrate W2. The insulator layer 51 is, for example, a silicon oxide film. Hereinafter, the layer at the height where the insulator layer 51 is provided is referred to as the "bonding layer B2".

[0078] The conductor layer GC is provided on a gate insulating film provided on the first substrate W1. The conductor layer GC in the sense amplifier region SR is used, for example, as a gate electrode of the transistor T9. The conductor layer GC in the transfer region XR2 is used, for example, as a gate electrode of the transistor TR1. A contact C0 is provided on each conductor layer GC. The two contacts CS included in the sense amplifier region SR are connected, for example, to two impurity diffusion regions (not shown) corresponding to the source and drain ends of the transistor T9. Similarly, the two contacts CS included in the transfer region XR1 are connected, for example, to two impurity diffusion regions (not shown) corresponding to the source and drain ends of the transistor TR1.

[0079] A conductor layer 52 is provided on each of the contacts CS and C0. The conductor layer 52 is included in the wiring layer D0. A conductor layer 53 is provided on the conductor layer 52 via a contact C1. The conductor layer 53 is included in the wiring layer D1. A conductor layer 54 is provided on the conductor layer 53 via a contact C2. The conductor layer 54 is included in the wiring layer D2. A conductor layer 55 is provided on the conductor layer 54 via a contact C3. The conductor layer 55 is included in the bonding layer B2 and corresponds to a bonding pad BP used for bonding the first substrate W1 and the second substrate W2. The conductor layer 55 includes, for example, copper. A conductor layer 28 disposed opposite to the CMOS layer 100 and the memory layer 200 contacts the conductor layer 55. This electrically connects the conductor layer 26 (bit line BL) to the transistor T9 provided on the first substrate W1. Similarly, the conductive layer 29 is electrically connected to the transistor TR provided on the first substrate W1 via the conductive layers 52 to 55 and the contacts CS and C1 to C3.

[0080] An insulating layer 70 is provided on the second substrate W2. The insulating layer 70 is included in the wiring layer 300. The wiring layer 300 includes a conductive layer connected to a circuit included in either the CMOS layer 100 or the memory layer 200. The conductive layer is connected to, for example, a pad PD (not shown) provided to penetrate the insulating layer 70.

[0081] <1-1-4>Transistor characteristics An example of the characteristics of each transistor included in the NAND string NS in the memory device 1 according to the first embodiment will be described below.

[0082] (1: Threshold voltage distribution and data allocation of memory cell transistor MT) FIG. 15 is a schematic diagram showing an example of the threshold voltage distribution and data allocation of the memory cell transistors MT in the memory device 1 according to the first embodiment. The vertical axis "NMTs" indicates the number of memory cell transistors MT. The horizontal axis "Vth" indicates the threshold voltage of the memory cell transistors MT. As shown in FIG. 15, when each memory cell transistor MT stores 3-bit data, the threshold voltage distribution of the multiple memory cell transistors MT forms eight states. In this specification, these eight states are called "S0" state, "S1" state, "S2" state, "S3" state, "S4" state, "S5" state, "S6" state, and "S7" state, in order from the lowest threshold voltage. Different 3-bit data is assigned to each of the "S0" to "S7" states. An example of data allocation to the eight states is listed below.

[0083] “S0” state: “111 (high-order bit / middle-order bit / low-order bit)” data “S1” state: “110” data “S2” state: “100” data “S3” state: “000” data “S4” state: “010” data “S5” state: “011” data “S6” state: “001” data “S7” state: “101” data.

[0084] A read voltage and a verify voltage are set between adjacent states. Specifically, a read voltage R1 is set between the "S0" and "S1" states. A read voltage R2 is set between the "S1" and "S2" states. A read voltage R3 is set between the "S2" and "S3" states. A read voltage R4 is set between the "S3" and "S4" states. A read voltage R5 is set between the "S4" and "S5" states. A read voltage R6 is set between the "S5" and "S6" states. A read voltage R7 is set between the "S6" and "S7" states. Verify voltages VS1 to VS7 are set in association with the "S1" to "S7" states, respectively. The verify voltages VS1 to VS7 may be the same as or different from the read voltages R1 to R7, respectively. Also, a read pass voltage VREAD is set to a voltage higher than the state "S7" having the highest threshold voltage. A memory cell transistor MT to which a read pass voltage VREAD is applied is turned on regardless of the data stored therein.

[0085] When the data allocation shown in FIG. 15 is applied, one page of data (lower page data) composed of lower bits is determined by a read operation using read voltages R1 and R5. One page of data (middle page data) composed of middle bits is determined by a read operation using read voltages R2, R4, and R6. One page of data (upper page data) composed of upper bits is determined by a read operation using read voltages R3 and R7. In a page read operation using multiple read voltages, arithmetic processing is appropriately performed in the sense amplifier unit SAU. Each memory cell transistor MT may store one bit, two bits, or four or more bits of data, or other data allocations may be applied.

[0086] (2: Threshold voltage distribution of select transistors STe and STo) FIG. 16 is a schematic diagram showing an example of threshold voltage distribution of the select transistors STe and STo in the memory device 1 according to the first embodiment. "NMTs" on the vertical axis indicates the number of select transistors STe and STo. "Vth" on the horizontal axis indicates the threshold voltage of the select transistors STe and STo. As shown in FIG. 16, the threshold voltage distribution of the multiple select transistors STe and STo forms two states. In this specification, these two states are called the "LS" state and the "HS" state, respectively.

[0087] The "LS" state is set, for example, similar to the "S0" state, which corresponds to an erased state. The "HS" state is set to a voltage higher than that of the "LS" state. The "HS" state may be similar to any of the "S1" to "S7" states. The settings of the "HS" state and the "LS" state may be changed as appropriate according to the threshold voltage distribution of the memory cell transistor MT. The select transistors STe and STo to which the read pass voltage VREAD is applied are turned on regardless of the set state.

[0088] A read voltage VMID is set between the "LS" state and the "HS" state. As the read voltage VMID, a voltage similar to any of the read voltages R1 to R7 may be used depending on the setting of the "LS" state and the "HS" state. A verify voltage associated with the "HS" state may be set in the memory device 1. The "LS" state and the "HS" state are formed, for example, by writing flag data to the selection transistors STe and STo. Writing the flag data may be performed after the data in the block BLK is erased, or may be performed at the time of shipment.

[0089] FIG. 17 is a schematic diagram showing an example of allocation of threshold voltages of the select transistors STe and STo in the memory device 1 according to the first embodiment. FIG. 17 shows some transistors of the NAND string NSe connected to the even bit line BLe and some transistors of the NAND string NSo connected to the odd bit line BLo. As shown in FIG. 17, the threshold voltage of the select transistor STe of the NAND string NSe is set to the "LS" state. The threshold voltage of the select transistor STo of the NAND string NSe is set to the "HS" state. The threshold voltage of the select transistor STe of the NAND string NSo is set to the "HS" state. The threshold voltage of the select transistor STo of the NAND string NSo is set to the "LS" state.

[0090] In the first embodiment, in each NAND string NS, the threshold voltage of the select transistor STe is set to one of the "LS" state and the "HS" state, and the threshold voltage of the select transistor STo is set to the other of the "LS" state and the "HS" state. The threshold voltage of the select transistor STe of the NAND string NSe is set to a state different from the threshold voltage of the select transistor STe of the NAND string NSo, and the threshold voltage of the select transistor STo of the NAND string NSo is set to a state different from the threshold voltage of the select transistor STo of the NAND string NSo. The operation of the first embodiment described below can be changed as appropriate depending on the state to which the select transistors STe and STo of the NAND strings NSe and NSo belong, respectively.

[0091] <1-2> Operation Next, the operation of the memory device 1 according to the first embodiment will be described.

[0092] The memory device 1 can perform an even / odd bit line read operation, an even bit line read operation, and an odd bit line read operation. An even / odd bit line read operation is a read operation that selects both the even bit line group and the odd bit line group. An even bit line read operation is a read operation that selects the even bit line group. An odd bit line read operation is a read operation that selects the odd bit line group.

[0093] For example, the data size read in the even / odd bit line read operation is twice the page size read in the even bit read operation and twice the page size read in the odd bit read operation. The even / odd bit line read operation is, for example, a 16 KB page read operation (16 KB page read). Each of the even bit line read operation and the odd bit line read operation is, for example, an 8 KB page read operation (8 KB page read). The memory device 1 may be configured to perform the even bit read operation when the 8 KB page read is in the first mode and to perform the odd bit read operation when the 8 KB page read is in the second mode.

[0094] In the following, the selected word line WL is referred to as the "word line WLsel." The unselected word lines WL are referred to as the "word lines WLusel." The selected select gate line SGD is referred to as the "select gate line SGDsel." The unselected select gate lines SGD are referred to as the "select gate line SGDusel." The memory cell transistor MT connected to the word line WLsel is referred to as the "memory cell transistor MTsel." The memory cell transistor MT connected to the word line WLusel is referred to as the "memory cell transistor MTusel." Below, the even / odd bit line read operation, even bit line read operation, and odd bit line read operation executed by the memory device 1 will be described using the example of reading lower page data.

[0095] <1-2-1> Even / odd bit line read operation Fig. 18 is a timing chart showing an example of an even / odd bit line read operation of the memory device 1 according to the first embodiment. Fig. 18 shows changes in the voltages of the select gate lines SGDsel, SGDusel, SGe and SGo, the word lines WLsel and WLusel, the select gate line SGS, the control signals BLCe and BLCo, the bit lines BLe and BLo, and the control signal STB in an even / odd bit line read operation for the lower page data. As shown in Fig. 18, in an even / odd bit line read operation for the lower page data, the sequencer 14 executes the processes at times t0 to t5 in order.

[0096] At the start of the even / odd bit line read operation, the voltage applied to each line is the ground voltage VSS, and each control signal is at the "L" level.

[0097] At time t0, the sequencer 14 applies the voltage VSG to each of the select gate lines SGDsel, SGDusel, and SGS, applies the read pass voltage VREAD to each of the select gate lines SGe and SGo and the word line WLusel, and applies the read voltage R1 to the word line WLsel. After that, the sequencer 14 applies the ground voltage VSS to the select gate line SGDusel.

[0098] At time t1, the sequencer 14 sets each of the control signals BLCe and BLCo to the "H" level. Then, the sense amplifier unit SAUe charges the bit line BLe, and the voltage of the bit line BLe rises to the voltage VBL. Similarly, the sense amplifier unit SAUo charges the bit line BLo, and the voltage of the bit line BLo rises to the voltage VBL. Then, the memory cell transistor MTsel to which the read voltage R1 is applied turns on or off depending on the data stored therein.

[0099] Although not shown, between time t1 and time t2, the sequencer 14 charges the node SEN of each sense amplifier unit SAU by setting the control signal HLL to the "H" level for a predetermined period. Then, the sequencer 14 sets the control signal XXL to the "H" level. Then, the voltage of the node SEN of each sense amplifier unit SAU is discharged or maintained according to the state of the memory cell transistor MTsel associated with that sense amplifier unit SAU.

[0100] At time t2, the sequencer 14 sets the control signal STB to the “H” level for a predetermined time. That is, at time t2, the sequencer 14 asserts the control signal STB. Then, the transistor T7 of each sense amplifier unit SAU is turned on or off depending on the voltage of the node SEN of the sense amplifier unit SAU. As a result, the read result using the read voltage R1 is reflected on the bus LBUS, and the read result using the read voltage R1 is stored in a predetermined latch circuit.

[0101] The operations at times t3 and t4 are the same as those described at times t1 and t2, respectively, except that the voltage applied to the word line WLsel is changed from the read voltage R1 to the read voltage R5. Briefly, at time t3, the sequencer 14 applies the read voltage R5 to the word line WLsel. Then, at time t4, the sequencer 14 asserts the control signal STB. As a result, the read result using the read voltage R5 is reflected on the bus LBUS, and the read result using the read voltage R5 is stored in a predetermined latch circuit.

[0102] At time t5, the sequencer 14 transitions the voltages applied to the wirings and the voltages of the control signals to the states at the start of the even / odd bit line read operation. Then, the sequencer 14 determines the lower bit data based on the read result using the read voltage R1 and the read result using the read voltage R5. After that, the memory device 1 transmits the determined set of lower bit data to the memory controller 2 as lower page data, and ends the even / odd bit line read operation for the lower page data.

[0103] Fig. 19 is a schematic diagram showing an example of a method for selecting a bit line BL in an even / odd bit line read operation of the memory device 1 according to the first embodiment. Fig. 19 shows the operating states of some elements of the sense amplifier units SAUe and SAUo and the NAND strings NSe and NSo when the even / odd bit line read operation shown in Fig. 18 is being executed. As shown in Fig. 19, in the even / odd bit line read operation, the control signals BLCe and BLCo are each set to the "H" level, thereby turning on the transistor T5 of each of the sense amplifier units SAUe and SAUo.

[0104] In addition, during a period when each of the control signals BLCe and BLCo is at the "H" level, the control signal BLS is set to the "H" level, thereby turning on the transistors T9 of each of the sense amplifier units SAUe and SAUo. In the NAND string NSe, each of the selection transistors STe and STo to which the read pass voltage VREAD is applied is turned on. In the NAND string NSo, each of the selection transistors STe and STo to which the read pass voltage VREAD is applied is turned on.

[0105] As a result, the sense amplifier unit SAUe and the NAND string NSe are electrically connected via the even bit line BLe (BLe: conductive). Similarly, the sense amplifier unit SAUo and the NAND string NSo are electrically connected via the even bit line BLe (BLo: conductive). Therefore, in the even / odd bit line read operation shown in FIG. 18, the memory device 1 can select each of the memory cell transistors MTsel connected to the even bit line BLe and the memory cell transistors MTsel connected to the odd bit line BLo to read out the lower bit data.

[0106] Incidentally, the memory device 1 can execute the even / odd bit line read operation for the middle page data and the upper page data in the same manner as for the lower page data by changing the read voltage and the number of reads.

[0107] <1-2-2> Even bit line read operation Fig. 20 is a timing chart showing an example of an even bit line read operation of the memory device 1 according to the first embodiment. Fig. 20 shows changes in the voltages of the select gate lines SGDsel, SGDusel, SGe and SGo, the word lines WLsel and WLusel, the select gate line SGS, the control signals BLCe and BLCo, the bit lines BLe and BLo, and the control signal STB in an even bit line read operation for the lower page data. As shown in Fig. 20, in an even bit line read operation for the lower page data, the sequencer 14 executes the processes at times t0 to t5 in order.

[0108] The process from time t0 to t5 in the even bit line read operation differs from the even / odd bit line read operation described with reference to FIG. 18 in the voltages applied to the select gate lines SGe and SGo and the control method of the control signals BLCe and BLCo. Specifically, at time t0 in the even bit line read operation, the sequencer 14 applies a voltage VMID to the select gate line SGe and applies a read pass voltage VREAD to the select gate line SGo. At time t1, the sequencer 14 sets the control signals BLCe and BLCo to the “H” level and the “L” level, respectively. By the operation at time t1, the sense amplifier unit SAUe charges the bit line BLe to the voltage VBL. Also, the bit line BLo is in a floating state during the period from time t1 to time t5. The other operations in the even bit line read operation are the same as those in the even / odd bit line read operation.

[0109] 21 is a schematic diagram showing an example of a method for selecting a bit line BL in an even bit line read operation of the memory device 1 according to the first embodiment. FIG. 21 shows the operating states of some elements of the sense amplifier units SAUe and SAUo and the NAND strings NSe and NSo when the even bit line read operation shown in FIG. 20 is being performed. As shown in FIG. 21, in the even bit line read operation, the control signal BLCe is set to the "H" level, and the control signal BLCo is set to the "L" level. In this case, the transistor T5 of the sense amplifier unit SAUe is turned on, and the transistor T5 of the sense amplifier unit SAUo is turned off.

[0110] Furthermore, during a period in which the control signals BLCe and BLCo are at the "H" level and the "L" level, respectively, the control signal BLS is set to the "H" level, thereby turning on the transistors T9 of the sense amplifier units SAUe and SAUo. In the NAND string NSe, the selection transistor STe to which the voltage VMID is applied and the selection transistor STo to which the read pass voltage VREAD is applied are both turned on. On the other hand, in the NAND string NSo, the selection transistor STe to which the voltage VMID is applied is turned off.

[0111] As a result, the sense amplifier unit SAUe and the NAND string NSe are electrically connected via the even bit line BLe (BLe: conductive). Meanwhile, the odd bit line BLo connecting the sense amplifier unit SAUo and the NAND string NSo is in a floating state (BLo: floating) as the transistor T5 of the sense amplifier unit SAUo and the selection transistor STe of the NAND string NSo are both in an off state. Therefore, in the even bit line read operation shown in FIG. 20, the memory device 1 can read lower bit data from the memory cell transistor MTsel connected to the even bit line BLe while keeping the odd bit line BLo in a floating state.

[0112] Incidentally, the memory device 1 can execute the even bit line read operation for the middle page data and the upper page data in the same manner as for the lower page data by changing the read voltage and the number of reads.

[0113] <1-2-3> Odd bit line read operation Fig. 22 is a timing chart showing an example of an odd-bit line read operation of the memory device 1 according to the first embodiment. Fig. 22 shows changes in the voltages of the select gate lines SGDsel, SGDusel, SGe and SGo, the word lines WLsel and WLusel, the select gate line SGS, the control signals BLCe and BLCo, the bit lines BLe and BLo, and the control signal STB in an odd-bit line read operation for the lower page data. As shown in Fig. 22, in an odd-bit line read operation for the lower page data, the sequencer 14 executes the processes at times t0 to t5 in order.

[0114] The process from time t0 to t5 in the odd bit line read operation differs from the even / odd bit line read operation described with reference to FIG. 18 in the voltages applied to the select gate lines SGe and SGo and the control method of the control signals BLCe and BLCo. Specifically, at time t0 in the odd bit line read operation, the sequencer 14 applies the voltage VMID to the select gate line SGo and applies the read pass voltage VREAD to the select gate line SGe. At time t1, the sequencer 14 sets the control signals BLCe and BLCo to the “L” level and the “H” level, respectively. By the operation at time t1, the sense amplifier unit SAUo charges the bit line BLo to the voltage VBL. Also, the bit line BLe is in a floating state during the period from time t1 to time t5. The other operations in the odd bit line read operation are the same as those in the even / odd bit line read operation.

[0115] Fig. 23 is a schematic diagram showing an example of a method for selecting a bit line BL in an odd-bit line read operation of the memory device 1 according to the first embodiment. Fig. 23 shows the operating states of some elements of the sense amplifier units SAUe and SAUo and the NAND strings NSe and NSo when the odd-bit line read operation shown in Fig. 22 is being performed. As shown in Fig. 23, in the odd-bit line read operation, the control signal BLCo is set to the "H" level, and the control signal BLCe is set to the "L" level. In this case, the transistor T5 of the sense amplifier unit SAUo is turned on, and the transistor T5 of the sense amplifier unit SAUe is turned off.

[0116] Furthermore, in a period in which the control signals BLCe and BLCo are at the "L" level and the "H" level, respectively, the control signal BLS is set to the "H" level, thereby turning on the transistors T9 of the sense amplifier units SAUe and SAUo. In the NAND string NSo, the selection transistor STe to which the read pass voltage VREAD is applied and the selection transistor STo to which the voltage VMID is applied are both turned on. On the other hand, in the NAND string NSe, the selection transistor STo to which the voltage MID is applied is turned off.

[0117] As a result, the sense amplifier unit SAUo and the NAND string NSo are electrically connected via the odd bit line BLo (BLo: conductive). On the other hand, the even bit line BLe connecting the sense amplifier unit SAUe and the NAND string NSe is in a floating state (BLe: floating) as the transistor T5 of the sense amplifier unit SAUe and the selection transistor STo of the NAND string NSe are both in an off state. Therefore, in the odd bit line read operation shown in FIG. 22, the memory device 1 can read lower bit data from the memory cell transistor MTsel connected to the odd bit line BLo while keeping the even bit line BLe in a floating state.

[0118] Incidentally, the memory device 1 can execute the odd bit line read operation for the middle page data and the upper page data in the same manner as for the lower page data by changing the read voltage and the number of reads.

[0119] <1-3> Effects of the first embodiment According to the memory device according to the first embodiment described above, the operation time of the read operation can be reduced. The effects of the first embodiment will be described in detail below.

[0120] In flash memories in which memory cells are stacked in three dimensions, the demand for faster read operations, i.e. shorter operation times, continues to grow with each generation. Memory devices are known that support not only the normal 16KB page read, but also 8KB page read (so-called Fast Read) with improved read operation speed. In 8KB page read, for example, every other bit line BL is set to a floating state, thereby halving the apparent capacitance of the bit line BL. This shortens the charging time of the bit line BL, and the read operation time can be shortened.

[0121] A possible method for floating the bit lines BL is to increase the number of select gate lines SGD in the block BLK and control the select transistors STD connected to the bit lines BL to be floated to an off state. However, in this method, the resistance value of the select gate lines SGD increases as the number of select gate lines SGD in the block BLK increases. As a result, there is a risk that the operation speed of the read operation and the like will decrease. In other words, in order to shorten the operation time, it is preferable to be able to control the bit lines BL to a floating state without increasing the number of select gate lines SGD as much as possible.

[0122] Therefore, in the memory device 1 according to the first embodiment, the NAND string NS has a selection transistor STe in which flag data corresponding to the selection of the even bit line BLe is written, and a selection transistor STo in which flag data corresponding to the selection of the odd bit line BLo is written. These flag data are written in advance to the selection transistors STe and STo before a read operation or the like is performed. For example, the selection transistors STe and STo of the NAND string NSe connected to the even bit line BLe are written to the “LS” state and the “HS” state, respectively, and the selection transistors STe and STo of the NAND string NSo connected to the odd bit line BLo are written to the “HS” state and the “LS” state, respectively.

[0123] During a 16 KB page read, a read pass voltage VREAD is applied to each of the select transistors STe and STo so that both the select transistors written to the "LS" state and the select transistors written to the "HS" state are turned on. On the other hand, during an 8 KB page read, a voltage VMID is applied to one of the select transistors STe and STo depending on whether the even bit line BLe or the odd bit line BLo is selected. As a result, the memory cell transistors MT of the 8 KB are electrically connected to the bit lines BL, and the memory cell transistors MT of the remaining 8 KB are electrically disconnected from the bit lines BL.

[0124] In this way, the memory device 1 according to the first embodiment can control either the selection transistor STe or STo to be in the off state. Furthermore, the memory device 1 can control the bit line BL connected to the selection transistor STe or STo in the off state to be in the floating state by independently controlling the control signals BLSa and BLSb to appropriately turn off the transistor T9.

[0125] As described above, the memory device 1 according to the first embodiment can halve the apparent capacitance of the bit lines BL by controlling every other bit line BL to a floating state. As a result, the memory device 1 according to the first embodiment can shorten the precharge time of the bit lines BL in a read operation and the waiting time until the voltage of the bit lines BL stabilizes, and can improve the speed of the read operation. Therefore, the memory device 1 according to the first embodiment can shorten the operation time of the read operation. In addition, the memory device 1 can halve the total current flowing through the memory cell transistors MT in an 8 KB page read by controlling one of the selection transistors STe and STo to an off state, and can reduce the read current.

[0126] In the first embodiment, the control signal BLC is independently controlled by the sense amplifier units SAUe and SAUo. However, the present invention is not limited to this. The operation described in the first embodiment may be realized by independently controlling the control signal BLS instead of the control signal BLC. Even in this case, the memory device 1 can perform the same operation as in the first embodiment and obtain the same effect as in the first embodiment.

[0127] <2> Second embodiment The memory device 1A according to the second embodiment has a configuration that combines a structure in which memory cell arrays 10 are stacked with the idea described in the first embodiment. Details of the second embodiment will be described below, focusing on the differences from the first embodiment.

[0128] <2-1> Configuration <2-1-1> Overall configuration of memory device 1A Fig. 24 is a block diagram showing an example of the overall configuration of a memory device 1A according to the second embodiment. As shown in Fig. 24, the memory device 1A includes, for example, a memory cell array 10A, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15A, a row decoder module 16A, a data register 17, and a sense amplifier module 18A. The input / output circuit 11, the logic controller 12, the register circuit 13, the sequencer 14, and the data register 17 in the memory device 1A are the same as those in the first embodiment.

[0129] The memory cell array 10A includes subarrays 101a and 101b. Each of the subarrays 101a and 101b has a similar configuration to the memory cell array 10 described in the first embodiment. The subarray 101a includes a plurality of subblocks SBLKa0 to SBLKan ("n" is an integer equal to or greater than 1). The subarray 101b includes a plurality of subblocks SBLKb0 to SBLKbn. The subblocks SBLKa0 to SBLKan are combined with the subblocks SBLKb0 to SBLKbn, respectively. In the memory cell array 10A, a set of combined subblocks SBLKa and SBLKb constitutes one block BLK. The subblocks SBLKa0 to SBLKan are connected to bit lines BLa0 to BLam ("m" is an integer equal to or greater than 1). The subblocks SBLKb0 to SBLKbn are connected to bit lines BLb0 to BLbm.

[0130] The driver circuit 15A has a configuration obtained by modifying the driver circuit 15 of the first embodiment in accordance with the memory cell array 10A. The driver circuit 15A generates voltages to be applied to various wirings provided in the subarrays 101a and 101b.

[0131] The row decoder module 16A has a configuration obtained by modifying the row decoder module 16 of the first embodiment in accordance with the memory cell array 10A. The row decoder module 16A transfers the voltage generated by the driver circuit 15A to various wirings provided in the subarrays 101a and 101b.

[0132] The sense amplifier module 18A has a configuration obtained by modifying the sense amplifier module 18 of the first embodiment in accordance with the memory cell array 10A. Each sense amplifier unit SAU of the sense amplifier module 18A is connected to a pair of bit lines BLa and BLb. Specifically, the sense amplifier units SAU0 to SAUm are connected to the bit lines BLa0 to BLam, respectively, and further connected to the bit lines BLb0 to BLbm, respectively.

[0133] <2-1-2> Circuit configuration of memory device 1A The circuit configuration of the memory device 1A according to the first embodiment will be described below.

[0134] (1: Circuit configuration of memory cell array 10A) FIG. 25 is a circuit diagram showing an example of a circuit configuration of a memory cell array 10A included in a memory device 1A according to the second embodiment. FIG. 25 shows one of a plurality of blocks BLK included in the memory cell array 10A. As shown in FIG. 25, in the block BLK of the second embodiment, for example, a select gate line SGS, word lines WL0 to WL(k-1) (k is an integer of 1 or more), and a source line SL are connected to each of sub-blocks SBLKa and SBLKb. Bit lines BLa0 to BLam and select gate lines SGDa0 to SGDa4, SGae, and SGao are connected to the sub-block SBLKa. Bit lines BLb0 to BLbm and select gate lines SGDb0 to SGDb4, SGbe, and SGbo are connected to the sub-block SBLKb.

[0135] In the block BLK of the second embodiment, the select gate lines SGDa0 to SGDa4, the select gate lines SGDb0 to SGDb4, the select gate lines SGae, SGao, SGbe, and SGbo, the select gate line SGS, and the word lines WL0 to WL(k-1) are provided for each block BLK. The bit lines BLa0 to BLam are shared by multiple sub-blocks SBLKa. The bit lines BLb0 to BLbm are shared by multiple sub-blocks SBLKb. The source line SL is shared by multiple blocks BLK.

[0136] The sub-block SBLKa includes, for example, five string units SUa0 to SUa4. Each string unit SUa includes a plurality of NAND strings NSa0 to NSam. The NAND strings NSa0 to NSam are associated with the bit lines BLa0 to BLam, respectively. The NAND string NSa is connected between the associated bit line BLa and the source line SL. Each NAND string NSa includes, for example, k memory cell transistors MTa0 to MTa(k-1) and select transistors STDa, STae, STao, and STSa. In each NAND string NSa, the select transistors STDa, STae, and STao, the memory cell transistors MTa(k-1) to MTa0, and the select transistor STSa are connected in series in this order from the bit line BLa toward the source line SL. Each of the select transistors STDa and STSa is used to select the string unit SUa. Each of the select transistors STae and STao is used to select a group of the bit lines BLa.

[0137] The sub-block SBLKb includes, for example, five string units SUb0 to SUb4. Each string unit SUb includes a plurality of NAND strings NSb0 to NSbm. The NAND strings NSb0 to NSbm are associated with bit lines BLb0 to BLbm, respectively. The NAND strings NSb are connected between the associated bit line BLb and a source line SL. Each NAND string NSb includes, for example, k memory cell transistors MTb0 to MTb(k-1) and select transistors STDb, STbe, STbo, and STSb. In each NAND string NSb, the select transistors STDb, STbe, and STbo, the memory cell transistors MTb(k-1) to MTb0, and the select transistor STSb are connected in series in this order from the bit line BLb toward the source line SL. Each of the select transistors STDb and STSb is used to select the string unit SUb. Each of the select transistors STbe and STbo is used to select the bit line BLb.

[0138] In the second embodiment, an example will be described in which, among the multiple bit lines BLa0 to BLam connected to the sub-block SBLKa, an even bit line group including even bit lines BLae (BLa0, BLa2, BLa4, ...) and an odd bit line group including odd bit lines BLao (BLa1, BLa3, BLa5, ...) are configured to be individually selectable. In this case, the memory device 1A is configured to allow, among the multiple bit lines BLb0 to BLbm connected to the sub-block SBLKb, an even bit line group including even bit lines BLbe (BLb0, BLb2, BLb4, ...) and an odd bit line group including odd bit lines BLbo (BLb1, BLb3, BLb5, ...) to be individually selectable.

[0139] The select gate lines SGDa0 to SGDa4 are associated with the string units SUa0 to SUa4, respectively. Each select gate line SGDa is connected to a gate terminal of each of the select transistors STDa included in the associated string unit SUa. The select gate line SGae is connected to a gate terminal of each of the select transistors STae included in the sub-block SBLKa. The select gate line SGao is connected to a gate terminal of each of the select transistors STao included in the sub-block SBLKa.

[0140] The select gate lines SGDb0 to SGDb4 are associated with the string units SUb0 to SUb4, respectively. Each select gate line SGDb is connected to a gate terminal of each of the select transistors STDb included in the associated string unit SUb. The select gate line SGbe is connected to a gate terminal of each of the select transistors STbe included in the sub-block SBLKb. The select gate line SGbo is connected to a gate terminal of each of the select transistors STbo included in the sub-block SBLKb.

[0141] The select gate line SGS of the second embodiment is connected to the gate terminals of the select transistors STSa and STSb included in the block BLK. The word line WL(K) (where "K" is an integer greater than or equal to 0 and less than or equal to (k-1)) of the second embodiment is connected to the control gate terminals of the memory cell transistors MTa(K) and MTb(K) included in the block BLK.

[0142] As described above, in the memory cell array 10A, the word lines WL are shared between the pair of sub-blocks SBLKa and SBLKb. A select gate line SGD is provided for each string unit SU. Select gate lines SGa and SGa are provided for each sub-block SBLK. The select gate line SGS may be shared within the block BLK, may be provided for each sub-block SBLK, or may be provided for each string unit SU.

[0143] The memory cell array 10A may have other circuit configurations. For example, the number of string units SUa and SUb included in the block BLK, the number of memory cell transistors MTa and select transistors STDa, STae, STao, and STSa included in the NAND string NSa, and the number of memory cell transistors MTb and select transistors STDb, STbe, STbo, and STSb included in the NAND string NSb may be designed to any number. In the following, an example will be described in which the number of memory cell transistors MTa included in the NAND string NSa is six, and the number of memory cell transistors MTb included in the NAND string NSb is six.

[0144] (2: Circuit configuration of row decoder module 16A) FIG. 26 is a circuit diagram showing an example of a circuit configuration of a row decoder module 16A included in a memory device 1A according to the second embodiment. FIG. 26 shows the connection relationship between the driver circuit 15A and the memory cell array 10A and the row decoder module 16A, and a detailed circuit configuration of one row decoder RD. As shown in FIG. 25, the row decoder RD of the second embodiment is connected to each of the signal lines CG0 to CG5, SGDDa0 to SGDDa4, SGDDb0 to SGDDb4, SGaeD, SGaoD, SGbeD, SGboD, SGSD, USGD, and USGS connected to the driver circuit 15A. In addition, the row decoder RD of the second embodiment is connected to the word lines WL0 to WL5 of the associated block BLK, and the select gate lines SGDa0 to SGDa4, SGDb0 to SGDb4, SGae, SGao, SGbe, SGbo, and SGS.

[0145] The row decoder RD of the second embodiment includes, for example, transistors TR0 to TR6, TR7a to TR13a, TR7b to TR13b, TR14, TR15a to TR19a, TR15b to TR19b, transfer gate lines TG and bTG, and a block decoder BD. The transistors TR0 to TR6 and TR14 and the block decoder BD are similar to those of the row decoder RD of the first embodiment. The transistors TR7a to TR13a, TR15a to TR19a, TR7b to TR13b, and TR15b to TR19b are N-type HV transistors. The transfer gate line TG of the second embodiment is connected to the gate terminals of the transistors TR7a to TR13a and TR7b to TR13b. The transfer gate line bTG of the second embodiment is connected to the gate terminals of the transistors TR15a to TR19a and TR15b to TR19b.

[0146] The drain terminals of the transistors TR7a and TR8a are connected to the signal lines SGaoD and SGaeD, respectively. The source terminals of the transistors TR7a and TR8a are connected to the select gate lines SGao and SGae, respectively, of the associated block BLK. The drain terminals of the transistors TR9a to TR13a are connected to the signal lines SGDDa0 to SGDDa4, respectively. The source terminals of the transistors TR9a to TR13a are connected to the select gate lines SGDa0 to SGDa4, respectively, of the associated block BLK. The drain terminals of the transistors TR15a to TR19a are connected to the signal line USGD. The source terminals of the transistors TR15a to TR19a are connected to the select gate lines SGDa0 to SGDa4, respectively, of the associated block BLK.

[0147] The drain terminals of the transistors TR7b and TR8b are connected to the signal lines SGboD and SGbeD, respectively. The source terminals of the transistors TR7b and TR8b are connected to the select gate lines SGbo and SGbe of the associated block BLK, respectively. The drain terminals of the transistors TR9b to TR13b are connected to the signal lines SGDDb0 to SGDDb4, respectively. The source terminals of the transistors TR9b to TR13b are connected to the select gate lines SGDb0 to SGDb4 of the associated block BLK, respectively. The drain terminals of the transistors TR15b to TR19b are connected to the signal line USGD. The source terminals of the transistors TR15b to TR19b are connected to the select gate lines SGDb0 to SGDb4 of the associated block BLK, respectively.

[0148] It should be noted that the row decoder module 16A may have other circuit configurations. The number of transistors TR included in the row decoder module 16A may be changed as appropriate according to the number of wirings provided in each block BLK.

[0149] (3: Circuit configuration of the sense amplifier unit SAU) 27 is a circuit diagram showing an example of a circuit configuration of a sense amplifier unit SAU included in a sense amplifier module 18A of a memory device 1A according to the second embodiment. The sense amplifier unit SAU of the second embodiment is different from the sense amplifier unit SAU of the first embodiment in the circuit configuration of the bit line connection unit BLHU. The bit line connection unit BLHU of the second embodiment includes, for example, transistors T9a, T10a, T9b, and T10b. The pair of transistors T9a and T10a and the pair of transistors T9b and T10b are similar to the pair of transistors T9 and T10 of the first embodiment and are configured to be individually controllable.

[0150] Specifically, the drain terminals of the transistors T9a and T9b are connected to the source terminal of the transistor T5. The source terminals of the transistors T9a and T9b are connected to the bit lines BLa and BLb, respectively. The drain terminals of the transistors T10a and T10b are connected to the node BLBIAS. The source terminals of the transistors T10a and T10b are connected to the bit lines BLa and BLb, respectively. The control signals BLSa and BLSb are input to the gate terminals of the transistors T9a and T9b, respectively. The control signals BIASa and BIASb are input to the gate terminals of the transistors T10a and T10b, respectively.

[0151] Other configurations of the sense amplifier unit SAU of the second embodiment are the same as those of the sense amplifier unit SAU of the first embodiment. Hereinafter, the sense amplifier unit SAU connected to the pair of even bit lines BLae and BLbe is called the "sense amplifier unit SAUe". The sense amplifier unit SAU connected to the pair of odd bit lines BLao and BLbo is called the "sense amplifier unit SAUo". In the second embodiment, the sequencer 14 is configured to be able to independently control the control signals BLSa, BLSb, BIASa, and BIASb used to control the sense amplifier unit SAUe, and the control signals BLSa, BLSb, BIASa, and BIASb used to control the sense amplifier unit SAUo. Hereinafter, the control signals BLSa, BLSb, BIASa, and BIASb used to control the sense amplifier unit SAUe are called the control signals BLSae, BLSbe, BIASae, and BIASbe, respectively. The control signals BLSa, BLSb, BIASa, and BIASb used to control the sense amplifier unit SAUo are called control signals BLSao, BLSbo, BIASao, and BIASbo, respectively.

[0152] <2-1-3> Structure of memory device 1A The structure of the memory device 1A according to the second embodiment will be described below.

[0153] (1: Appearance of memory device 1A) Fig. 28 is a perspective view showing an example of the appearance of a memory device 1A according to the second embodiment. As shown in Fig. 28, the memory device 1A has a structure in which, for example, a first substrate W1, a CMOS layer 100, a memory layer 200a, a memory layer 200b, a third substrate W3, and a wiring layer 300 are stacked in this order from the bottom.

[0154] The CMOS layer 100 of the second embodiment includes, for example, an input / output circuit 11, a logic controller 12, a register circuit 13, a sequencer 14, a driver circuit 15A, a row decoder module 16A, a data register 17, and a sense amplifier module 18A. The memory layer 200a includes a subarray 101a formed by using a second substrate W2. In this example, the second substrate W2 is removed after the first substrate W1 and the second substrate W2 are bonded. The memory layer 200b includes a subarray 101b formed by using a third substrate W3.

[0155] The third substrate W3 is a silicon substrate. The memory device 1A has a bonding surface between the CMOS layer 100 and the memory layer 200a, and between the memory layers 200a and 200b. In this example, the bonding process of the first substrate W1 and the second substrate W2 bonds the surface of the CMOS layer 100 on the first substrate W1 to the surface of the memory layer 200a on the second substrate W2. The bonding process of the substrate (bonded substrate) after bonding the first substrate W1 and the second substrate W2 to the third substrate W3 bonds the surface of the memory layer 200a on the bonded substrate to the surface of the memory layer 200b on the third substrate W3. The third substrate W3 may be removed after bonding the bonded substrate and the third substrate W3. In this case, the memory device 1A does not have the third substrate W3.

[0156] (2: Cross-sectional structure of memory device 1A) The cross-sectional structure of the memory device 1A according to the second embodiment will be described below. In the memory device 1A, the cross-sectional structure of the CMOS layer 100 is similar to that of the first embodiment. Each of the memory layers 200a and 200b includes, for example, a configuration similar to that of the memory layer 200 of the first embodiment. In the following, for components similar to those in the memory layer 200, "a" is added to the end of the reference symbol when they are included in the memory layer 200a, and "b" is added to the end of the reference symbol when they are included in the memory layer 200b.

[0157] FIG. 29 is a cross-sectional view showing an example of the cross-sectional structure of the memory device 1A according to the second embodiment. FIG. 29 shows a cross-section including the memory region MR and the lead-out region HR1 in the memory device 1A, and displays coordinate axes based on the first substrate W1. As shown in FIG. 29, the memory layer 200a has a configuration in which, for example, the second substrate W2 is omitted from the memory layer 200 of the first embodiment, and insulator layers 80 and 81, a conductor layer 82, and a contact V2 are added. The memory layer 200b has a configuration in which, for example, the second substrate W2 is replaced with a third substrate W3 from the memory layer 200 of the first embodiment. On the third substrate W3, an insulator layer 70 (wiring layer 300) is provided, similarly to the memory layer 200 of the first embodiment.

[0158] In the memory layer 200a, the conductor layer 26a (bit line BLa) is connected to a sense amplifier unit SA (transistor T9a) provided on the first substrate W1 via the conductor layers 27a, 28a, 52-55, contacts V0a, V1a, C1-C3, CS, etc., in the same manner as the memory layer 200 of the first embodiment. Similarly, the conductor layer 22a (for example, the word line WL1) is connected to a row decoder RD (for example, the transistor TR2) on the first substrate W1 via the conductor layers 27a-29a and 52-55, contacts V0a, V1a, C1-C3, CS, etc. The other conductor layers 21a-25a are also connected to the row decoder RD on the first substrate W1, in the same manner as the conductor layer 22a.

[0159] In the memory layer 200a, the insulating layer 80 is provided on the conductive layer 20a. The insulating layer 81 is provided on the insulating layer 80. The insulating layer 81 is in contact with the bonding surfaces of the memory layers 200a and 200b. Hereinafter, the layer at the height where the insulating layer 81 is provided is referred to as the "bonding layer B3". The conductive layer 82 is included in the bonding layer B3 and corresponds to the bonding pad BP. The contact V2 is included in the lead-out region HR1. The contact V2 is provided through the terrace portion of the stacked wiring of the memory layer 200a, and connects between the corresponding conductive layer 29a and the conductive layer 82. The side of the contact V2 is covered by a spacer SP. This spacer SP is made of an insulating material and insulates between the contact V2 and the stacked wiring of the memory layer 200a.

[0160] In the memory layer 200b, the insulating layer 37b is in contact with the bonding surface of the memory layers 200a and 200b. Each conductive layer 28b is included in the bonding layer B1b. Each conductive layer 28b is disposed opposite to and bonded to a conductive layer 82 of the memory layer 200a. Thereby, the conductive layer 22b (for example, the word line WL1) is electrically connected to the corresponding conductive layer 82 in the memory layer 200a via the conductive layers 27b to 29b and the contacts V0b and V1b. As a result, the conductive layers 22a and 22b corresponding to the same word line WL1 are electrically connected to each other. Similarly to the conductive layer 22b, the conductive layers 21b to 25b are also electrically connected to the corresponding conductive layers 21a to 25a, respectively.

[0161] In the memory layer 200b, the conductor layer 26b (bit line BLb) is connected to a sense amplifier unit SA (transistor T9b) provided on the first substrate W1 via conductor layers 27a, 27b, 28a, 28b, 29a, 29b, 52 to 55, and contacts V0a, V0b, V1a, V1b, C1 to C3, and CS, although not shown in the figure. The other structures of the memory device 1A according to the second embodiment are similar to those of the memory device 1 according to the first embodiment.

[0162] <2-1-4>Transistor characteristics 30 is a schematic diagram showing an example of threshold voltage allocation of the select transistors STae, STbe, STao, and STbo in the memory device 1A according to the second embodiment. Fig. 30 shows some transistors of the NAND string NSae connected to the even bit line BLae and some transistors of the NAND string NSao connected to the bit line BLao in the sub-block SBLKa, and some transistors of the NAND string NSbe connected to the even bit line BLbe and some transistors of the NAND string NSbo connected to the odd bit line BLbo in the sub-block SBLKb.

[0163] As shown in FIG. 30, the threshold voltage of the select transistor STae of the NAND string NSae is set to the "LS" state. The threshold voltage of the select transistor STao of the NAND string NSae is set to the "HS" state. The threshold voltage of the select transistor STae of the NAND string NSao is set to the "HS" state. The threshold voltage of the select transistor STao of the NAND string NSao is set to the "LS" state. The threshold voltage of the select transistor STbe of the NAND string NSbe is set to the "LS" state. The threshold voltage of the select transistor STbo of the NAND string NSbo is set to the "LS" state. The threshold voltage of the select transistor STbe of the NAND string NSbo is set to the "LS" state. The threshold voltage of the select transistor STbo of the NAND string NSbo is set to the "HS" state.

[0164] In the second embodiment, in each NAND string NSae of the sub-block SBLKa, the threshold voltage of the select transistor STae is set to one of the “LS” state and the “HS” state, and the threshold voltage of the select transistor STao is set to the other of the “LS” state and the “HS” state. Then, the threshold voltage of the select transistor STae of the NAND string NSao is set to a state different from the threshold voltage of the select transistor STae of the NAND string NSae, and the threshold voltage of the select transistor STao of the NAND string NSao is set to a state different from the threshold voltage of the select transistor STao of the NAND string NSae.

[0165] Similarly, in the second embodiment, in each NAND string NSbe of the sub-block SBLKb, the threshold voltage of the select transistor STbe is set to one of the “LS” state and the “HS” state, and the threshold voltage of the select transistor STbo is set to the other of the “LS” state and the “HS” state. Then, the threshold voltage of the select transistor STbe of the NAND string NSbo is set to a state different from the threshold voltage of the select transistor STbe of the NAND string NSbe, and the threshold voltage of the select transistor STbo of the NAND string NSbo is set to a state different from the threshold voltage of the select transistor STbo of the NAND string NSbe.

[0166] In the second embodiment, the threshold voltage of the select transistor STae of each NAND string NSae is set to a state different from the threshold voltage of the select transistor STbe of the NAND string NSbe, and the threshold voltage of the select transistor STao of the NAND string NSae is set to a state different from the threshold voltage of the select transistor STbo of the NAND string NSbe. The threshold voltage of the select transistor STae of each NAND string NSao is set to a state different from the threshold voltage of the select transistor STbe of the NAND string NSbo, and the threshold voltage of the select transistor STao of the NAND string NSao is set to a state different from the threshold voltage of the select transistor STbo of the NAND string NSbo.

[0167] That is, the threshold voltages of the select transistors ST arranged in the same layer in the NAND strings NSae and NSao are set to different levels. The threshold voltages of the select transistors ST arranged in the same layer in the NAND strings NSbe and NSbo are set to different levels. The threshold voltages of the select transistors ST arranged in the same layer in the NAND strings NSae and NSbe are set to different levels. The threshold voltages of the select transistors ST arranged in the same layer in the NAND strings NSao and NSbo are set to different levels.

[0168] Note that "same layer" indicates that when the sub-blocks SBLK to which the select transistors ST to be compared belong are different, the relative position of the select transistor ST in the sub-block SBLKa and the relative position of the select transistor ST in the sub-block SBLKb are at the same height. The operation of the second embodiment described below can be changed as appropriate depending on the state to which the select transistors STae and STao of the NAND strings NSae and NSao belong, respectively, and the state to which the select transistors STbe and STbo of the NAND strings NSbe and NSbo belong, respectively.

[0169] <2-2> Operation Next, the operation of the memory device 1A according to the second embodiment will be described. The memory device 1A can execute a first read operation, a second read operation, a shield read operation, and a write operation. The first read operation, the second read operation, the shield read operation, and the write operation will be described in detail below in order.

[0170] <2-2-1> First read operation The first read operation is a read operation in which an even bit line group (even bit lines BLae) is selected in the sub-block SBLKa, and an odd bit line group (odd bit lines BLbo) is selected in the sub-block SBLKb. In the first read operation, the memory device 1A performs an operation similar to an even bit line read operation for the sub-block SBLKa, and performs an operation similar to an odd bit line read operation for the sub-block SBLKb. In addition, in the first read operation, one string unit SU is selected in each of the associated sub-blocks SBLKa and SBLKb. That is, in the first read operation, one select gate line SGDa and one select gate line SGDb are selected.

[0171] Fig. 31 is a timing chart showing an example of the first read operation of the memory device 1A according to the second embodiment. Fig. 31 shows the voltage changes of the select gate lines SGDsel and SGDusel, the select gate lines SGae, SGbe, SGao and SGbo, the word lines WLsel and WLusel, the select gate line SGS, the control signals BLC, BLSae, BLSbe, BLSao, BLSbo, BIASae, BIASbe, BIASao and BIASbo, the bit lines BLae, BLbe, BLao and BLbo, and the control signal STB in the first read operation for the lower page data. As shown in Fig. 31, in the first read operation for the lower page data, the sequencer 14 executes the processes at times t0 to t5 in order.

[0172] At the start of the first read operation, the voltage applied to each line is the ground voltage VSS, and each control signal is at the "L" level.

[0173] At time t0, the sequencer 14 applies the voltage VSG to each of the select gate lines SGDsel, SGDusel, and SGS, applies the read pass voltage VREAD to each of the select gate lines SGao, SGbo, and the word line WLusel, applies the voltage VMID to each of the select gate lines SGae and SGbe, and applies the read voltage R1 to the word line WLsel. After that, the sequencer 14 applies the ground voltage VSS to the voltage of the select gate line SGDusel.

[0174] At time t1, the sequencer 14 sets each of the control signals BLC, BLSae, and BLSbo to the "H" level. Then, the sense amplifier unit SAUe charges the bit line BLae, and the voltage of the bit line BLae rises to the voltage VBL. Similarly, the sense amplifier unit SAUo charges the bit line BLbo, and the voltage of the bit line BLbo rises to the voltage VBL. Then, the memory cell transistor MTsel to which the read voltage R1 is applied becomes an on or off state based on the data stored therein. Also, each of the bit lines BLao and BLbe becomes a floating state.

[0175] At time t2, the sequencer 14 asserts the control signal STB. Then, the transistor T7 of each sense amplifier unit SAU is turned on or off depending on the voltage of the node SEN of the sense amplifier unit SAU. As a result, the read result using the read voltage R1 is reflected on the bus LBUS, and the read result using the read voltage R1 is stored in a predetermined latch circuit.

[0176] The operations at times t3 and t4 are the same as those described at times t1 and t2, respectively, except that the voltage applied to the word line WLsel is changed from the read voltage R1 to the read voltage R5. Briefly, at time t3, the sequencer 14 applies the read voltage R5 to the word line WLsel. Then, at time t4, the sequencer 14 asserts the control signal STB. As a result, the read result using the read voltage R5 is reflected on the bus LBUS, and the read result using the read voltage R5 is stored in a predetermined latch circuit.

[0177] At time t5, the sequencer 14 transitions the voltages applied to the wirings and the voltages of the control signals to the states at the start of the first read operation. Then, the sequencer 14 determines the lower bit data based on the read result using the read voltage R1 and the read result using the read voltage R5. After that, the memory device 1 transmits the determined set of lower bit data to the memory controller 2 as lower page data, and ends the first read operation for the lower page data.

[0178] Fig. 32 is a schematic diagram showing an example of a method for selecting a bit line BL in a first read operation of the memory device 1A according to the second embodiment. Fig. 32 shows the operating states of some elements of the sense amplifier unit SAUe and the NAND strings NSae and NSbe when the first read operation shown in Fig. 31 is being executed. As shown in Fig. 32, in the first read operation, the control signal BLC is set to the "H" level, so that the transistor T5 of the sense amplifier unit SAUe is turned on.

[0179] Moreover, when the control signal BLSae is set to the “H” level, the transistor T9a of the sense amplifier unit SAUe is turned on. When each of the control signals BLSbe, BIASae, and BIASbe is set to the “L” level, the transistors T9b, T10a, and T10b of the sense amplifier unit SAUe are turned off. In the NAND string NSae, the selection transistor STae to which the voltage VMID is applied and the selection transistor STao to which the read pass voltage VREAD is applied are turned on. On the other hand, in the NAND string NSbe, the selection transistor STbe to which the voltage VMID is applied is turned off.

[0180] As a result, the sense amplifier unit SAUe and the NAND string NSae are electrically connected via the even bit line BLae (BLae: conductive). On the other hand, the even bit line BLbe connecting the sense amplifier unit SAUe and the NAND string NSbe is in a floating state (BLbe: floating) because the transistors T9b and T10b of the sense amplifier unit SAUe and the selection transistor STbe of the NAND string NSbe are both in an off state.

[0181] Fig. 33 is a schematic diagram showing an example of a method for selecting a bit line BL in a first read operation of the memory device 1A according to the second embodiment. Fig. 33 shows the operating states of some elements of the sense amplifier unit SAUo and the NAND strings NSao and NSbo when the first read operation shown in Fig. 31 is being executed. As shown in Fig. 33, in the first read operation, the control signal BLC is set to the "H" level, so that the transistor T5 of the sense amplifier unit SAUo is turned on.

[0182] Moreover, when the control signal BLSbo is set to the “H” level, the transistor T9b of the sense amplifier unit SAUo is turned on. When each of the control signals BLSao, BIASao, and BIASbo is set to the “L” level, the transistors T9a, T10a, and T10b of the sense amplifier unit SAUo are turned off. In the NAND string NSbo, the selection transistor STbe to which the voltage VMID is applied and the selection transistor STbo to which the read pass voltage VREAD is applied are turned on. On the other hand, in the NAND string NSao, the selection transistor STae to which the voltage VMID is applied is turned off.

[0183] As a result, the sense amplifier unit SAUo and the NAND string NSao are electrically connected via the odd bit line BLbo (BLbo: conductive). Meanwhile, the odd bit line BLao connecting the sense amplifier unit SAUo and the NAND string NSao is in a floating state (BLao: floating) because the transistors T9a and T10a of the sense amplifier unit SAUo and the selection transistor STae of the NAND string NSao are both in the off state.

[0184] As described above, in the first read operation shown in FIG. 31, the memory device 1A can read lower bit data from the memory cell transistor MTsel connected to the even bit line BLae of the sub-block SBLKa while floating the odd bit line BLao of the sub-block SBLKa. Also, the memory device 1A can read lower bit data from the memory cell transistor MTsel connected to the odd bit line BLbo of the sub-block SBLKb while floating the even bit line BLbe of the sub-block SBLKb. That is, in the first read operation, the memory device 1A can execute a read operation targeting the NAND string NSae of the sub-block SBLKa and a read operation targeting the NAND string NSbo of the sub-block SBLKb in parallel. Therefore, the memory device 1A can read (m+1) bits of data at once by the first read operation.

[0185] Incidentally, the memory device 1A can execute the first read operation for the middle page data and the upper page data in the same manner as for the lower page data by changing the read voltage and the number of reads.

[0186] <2-2-2> Second read operation The second read operation is a read operation in which an odd bit line group (odd bit lines BLao) is selected in the sub-block SBLKa and an even bit line group (even bit lines BLbe) is selected in the sub-block SBLKb. In the second read operation, the memory device 1A performs an operation similar to the odd bit line read operation for the sub-block SBLKa and performs an operation similar to the even bit line read operation for the sub-block SBLKb. In the second read operation, similar to the first read operation, one string unit SU is selected in each of the associated sub-blocks SBLKa and SBLKb.

[0187] Fig. 34 is a timing chart showing an example of the second read operation of the memory device 1A according to the second embodiment. Fig. 34 shows the voltage changes of the select gate lines SGDsel, SGDusel, SGae, SGbe, SGao and SGbo, the word lines WLsel and WLusel, the select gate line SGS, the control signals BLC, BLSae, BLSbe, BLSao, BLSbo, BIASae, BIASbe, BIASao and BIASbo, the bit lines BLae, BLbe, BLao and BLbo, and the control signal STB in the second read operation for the lower page data. As shown in Fig. 34, in the second read operation for the lower page data, the sequencer 14 executes the processes at times t0 to t5 in order.

[0188] The process from time t0 to t5 in the second read operation differs from the first read operation described with reference to FIG. 31 in the voltages applied to the select gate lines SGae, SGao, SGbe, and SGbo, and the control method of the control signals BLSae, BLSao, BLSbe, and BLSbo. Specifically, at time t0 in the second read operation, the sequencer 14 applies a voltage VMID to each of the select gate lines SGao and SGbo, and applies a read pass voltage VREAD to each of the select gate lines SGae and SGbe. At time t1, the sequencer 14 sets each of the control signals BLSao and BLSbe to the “H” level, and sets each of the control signals BLSae, BLSbo, BIASae, BIASbe, BIASao, and BIASbo to the “L” level. By the operation at time t1, the sense amplifier unit SAUo charges the bit line BLao to the voltage VBL, and the sense amplifier unit SAUe charges the bit line BLbe to the voltage VBL. Moreover, the bit lines BLae and BLbo are in a floating state during the period from time t1 to time t5. The other operations of the second read operation are similar to those of the first read operation.

[0189] The method of selecting the bit line BL in the second read operation is the same as that in the first read operation, except that the operation related to the sub-block SBLKa and the operation related to the sub-block SBLKb are interchanged. As a result, in the second read operation shown in FIG. 34, the memory device 1A can read lower bit data from the memory cell transistor MTsel connected to the odd bit line BLao for the sub-block SBLKa while floating the even bit line BLae. Also, the memory device 1A can read lower bit data from the memory cell transistor MTsel connected to the even bit line BLbe for the sub-block SBLKb while floating the odd bit line BLbo. That is, in the second read operation, the memory device 1A can execute a read operation targeting the NAND string NSao of the sub-block SBLKa and a read operation targeting the NAND string NSbe of the sub-block SBLKb in parallel. Therefore, the memory device 1A can read (m+1) bits of data at once by the second read operation.

[0190] Incidentally, the memory device 1A can execute the second read operation for the middle page data and the upper page data in the same manner as for the lower page data by changing the read voltage and the number of reads.

[0191] <2-2-3> Shield read operation The shield read operation is a read operation that is executed in a state where a shield voltage is applied to unselected bit lines BL, and can be executed by selecting the bit lines BL in the same manner as the first read operation or the second read operation. The following describes the case where the bit lines BL are selected in the shield read operation for the lower page in the same manner as the first read operation.

[0192] Fig. 35 is a timing chart showing an example of a shield read operation of the memory device 1A according to the second embodiment. Fig. 35 shows changes in the voltages of the select gate lines SGDsel and SGDusel, the select gate lines SGae, SGbe, SGao and SGbo, the word lines WLsel and WLusel, the select gate line SGS, the control signals BLC, BLSae, BLSbe, BLSao, BLSbo, BIASae, BIASbe, BIASao and BIASbo, the bit lines BLae, BLbe, BLao and BLbo, and the control signal STB in the shield read operation for the lower page data. As shown in Fig. 35, in the shield read operation for the lower page data, the sequencer 14 executes the processes at times t0 to t5 in order.

[0193] The process from time t0 to t5 in the shield read operation is different from the first read operation described with reference to FIG. 31 in the control method of the set of the voltages of the select gate lines SGae, SGao, SGbe, and SGbo and the control signals BLSae, BLSao, BLSbe, BLSbo, BIASae, BIASbe, BIASao, and BIASbo, and the voltage of the bit lines BLao and BLbe. Specifically, at time t0 in the shield read operation, the sequencer 14 applies the read pass voltage VREAD to each of the select gate lines SGae, SGao, SGbe, and SGbo. At time t1 in the shield read operation, the sequencer 14 sets each of the control signals BLSae, BLSbo, BIASao, and BIASbo to the “H” level, and sets each of the control signals BLSao, BLSbe, BIASae, and BIASbe to the “L” level. By the operation at time t1, each of the bit lines BLae and BLbo is charged to the voltage VBL. In addition, a shield voltage VSHIELD is applied to each of the bit lines BLae and BLbo based on the voltage of the node BLBIAS. The shield voltage VSHIELD corresponds to, for example, the potential of the source line SL. Other operations of the shield read operation are similar to those of the first read operation.

[0194] FIG. 36 is a schematic diagram showing an example of a method for selecting the bit line BL in the shield read operation of the memory device 1A according to the second embodiment. FIG. 36 shows the operating states of some elements of the sense amplifier unit SAUe and the NAND strings NSae and NSbe when the shield read operation shown in FIG. 35 is performed. As shown in FIG. 36, the shield read operation in this example is different from the first read operation described using FIG. 32 in that the control signal BIASbe is at the “H” level. This causes the transistor T10b of the sense amplifier unit SAUe to be in an on state. As a result, the voltage of the node BLBIAS (shield voltage VSHIELD) is applied to the even bit line BLbe via the transistor T10b (BLbe:shield). On the other hand, in the sense amplifier unit SAUo, the voltage of the node BLBIAS (shield voltage VSHIELD) is applied to the odd bit line BLao via the transistor T10a (not shown).

[0195] 35, the memory device 1A can read lower bit data from the memory cell transistor MTsel connected to the even bit line BLae while shielding the odd bit line BLao for the sub-block SBLKa. Also, the memory device 1A can read lower bit data from the memory cell transistor MTsel connected to the odd bit line BLbo while shielding the even bit line BLbe for the sub-block SBLKb.

[0196] In addition, in the shield read operation for the lower page, the operation when the bit line BL is selected in the same manner as in the second read operation is the same as the above-mentioned shield read operation in which the operation related to the sub-block SBLKa and the operation related to the sub-block SBLKb are interchanged. The memory device 1A can execute the shield read operation for the middle page data and the upper page data in the same manner as for the lower page data by changing the read voltage and the number of reads. In addition, in the shield read operation, the select gate lines SGae, SGao, SGbe, and SGbo may be controlled in the same manner as in the first read operation and the second read operation.

[0197] <2-2-4> Write operation The write operation of the memory device 1A will be described below.

[0198] (1: Overview of write operation) FIG. 37 is a time chart showing an overview of the write operation of the memory device 1A according to the second embodiment. FIG. 37 shows the change in voltage of the word line WLsel in the write operation. As shown in FIG. 37, the memory device 1A executes a loop process (program loop process) including a program operation and a verify operation in the write operation. Note that although FIG. 37 shows three loop processes (1st Loop, 2nd Loop, 3rd Loop), the number of loop processes may change depending on the settings of the write operation, etc.

[0199] A program operation is an operation capable of increasing the threshold voltage of a memory cell transistor MTsel. The sequencer 14 sets each memory cell transistor MTsel as a program target or program inhibit, and executes a program operation. A program target memory cell transistor MTsel is a memory cell transistor MTsel that has not yet reached the threshold voltage of a state (hereinafter referred to as a "target state") corresponding to the data to be written. A program inhibit memory cell transistor MTsel is a memory cell transistor MTsel that has reached the threshold voltage of the target state.

[0200] In a program operation, the sequencer 14 applies a program voltage VPGM to the word line WLsel. VPGM is a high voltage capable of raising the threshold voltage of the memory cell transistor MTsel. Then, in the memory cell transistor MTsel to be programmed, electrons are injected into the charge storage layer based on the voltage difference between the word line WLsel and the channel, and the threshold voltage rises. On the other hand, in the memory cell transistor MTsel that is to be programmed, the select transistor STD is cut off, thereby boosting the channel potential and suppressing the rise in the threshold voltage.

[0201] The verify operation is a read operation that checks whether the threshold voltage of the memory cell transistor MTsel has reached the threshold voltage of the target state. In the verify operation, a read operation is executed using a verify voltage Vvfy. In this example, the verify voltage Vvfy is any one of verify voltages VS1, VS2, VS3, VS4, VS5, VS6, and VS7. In the verify operation, if the threshold voltage of the memory cell transistor MTsel is deemed to have exceeded the verify voltage Vvfy, it is determined as a "verify pass." On the other hand, if the threshold voltage of the memory cell transistor MTsel is deemed to be equal to or lower than the verify voltage Vvfy, it is determined as a "verify fail."

[0202] When the verify operation is completed, the sequencer 14 sets the memory cell transistor MTsel whose threshold voltage has reached the target state to program inhibit based on the result of the verify read in the current loop. Then, the sequencer 14 starts the next loop. The value of the program voltage VPGM is stepped up according to the repetition of the loop. In FIG. 31, the voltage difference corresponding to the step-up width of VPGM for each loop is shown as DVPGM. In each loop, a read operation using multiple verify voltages may be performed.

[0203] Furthermore, the memory device 1A may execute a detection operation after each loop process. In the detection operation, the number of memory cell transistors MTsel that have passed verification is counted for each state. Then, the sequencer 14 determines whether or not writing has been completed for each state. Completion of writing is determined, for example, based on the number of memory cell transistors MTsel that have failed verification falling below a predetermined number. When the sequencer 14 detects that writing has been completed for each of the "S1" to "S7" states during the repetition of the loop process, for example, the sequencer 14 ends the write operation.

[0204] (2: Program operation) Fig. 38 is a timing chart showing an example of a program operation of a write operation of the memory device 1A according to the second embodiment. Fig. 38 illustrates a case where a program operation for the NAND string NSae by the sense amplifier unit SAUe and a program operation for the NAND string NSbo by the sense amplifier unit SAUo are performed in parallel. Fig. 38 shows the voltage changes of the select gate lines SGDsel, SGDusel, SGae, SGao, SGbe, and SGbo, the word lines WLsel and WLusel, the select gate line SGS, the control signals BLC, BLSae, BLSbe, BLSao, BLSbo, BIASae, BIASbe, BIASao, and BIASbo, and the bit lines BLae, BLbe, BLao, and BLbo in the program operation. As shown in Fig. 38, in the program operation, the sequencer 14 executes the processes at times t0 to t5 in order.

[0205] At the start of the program operation, the voltage applied to each line is the ground voltage VSS, and each control signal is at the "L" level.

[0206] At time t0, the sequencer 14 applies a voltage VSGDH to each of the select gate lines SGDsel and SGDusel, and sets each of the control signals BLC, BLSae, BLSbo, BIASao, and BIASbe to the “H” level. Then, a voltage Vinhibit is applied to each of the bit lines BLao and BLbe. A ground voltage VSS is applied to the bit line BLae to be programmed, and a voltage Vinhibit is applied to the bit line BLae that is inhibited from programming. Similarly, a ground voltage VSS is applied to the bit line BLbo to be programmed, and a voltage Vinhibit is applied to the bit line BLbo that is inhibited from programming. Each select transistor STD is turned on by applying the voltage VSGDH.

[0207] At time t1, the sequencer 14 applies the ground voltage VSS to each of the select gate lines SGDsel and SGDusel. Then, each select transistor STD of the selected block BLK is turned off. At this time, the channel voltage of the NAND string NS connected to the bit line BL to be programmed is, for example, the ground voltage VSS. On the other hand, the channel voltage of the NAND string NS connected to the bit line BL to be programmed is maintained in an elevated state based on the voltage Vinhibit.

[0208] At time t2, the sequencer 14 applies a voltage VSGD to the select gate line SGDsel and a write pass voltage VPASS to each of the word lines WLsel and WLusel. The voltage VSGD is higher than the ground voltage VSS and lower than the voltage VSGDH. The write pass voltage VPASS is higher than the voltage VSGDH. At this time, the select transistor STD connected to the bit line BL to be programmed is turned on. On the other hand, the select transistor STD connected to the bit line BL to be inhibited from programming is turned off, and the channel voltage of the floating NAND string NS rises due to coupling with the word lines WLsel and WLusel.

[0209] At time t3, the sequencer 14 applies a program voltage VPGM to the word line WLsel. When the program voltage VPGM is applied to the word line WLsel, electrons are injected into the charge storage layer of the memory cell transistor MTsel to be programmed based on the voltage difference between the channel and the control gate, and the threshold voltage increases. Meanwhile, the increase in the threshold voltage of the memory cell transistors MT in the other NAND strings NS is suppressed by the increase in the channel voltage (self-boosting).

[0210] At time t4, the sequencer 14 reduces the voltage of the word line WLsel to the write pass voltage VPASS.

[0211] At time t5, the sequencer 14 transitions the voltages applied to the respective wirings and the voltages of the respective control signals to the states at the start of the even / odd bit line read operation. After that, the memory device 1A finishes the program operation.

[0212] Fig. 39 is a schematic diagram showing an example of a method for selecting a bit line BL in a program operation of a write operation of the memory device 1A according to the second embodiment. Fig. 39 shows the operating states of some elements of the sense amplifier unit SAUe and the NAND strings NSae and NSbe when the program operation shown in Fig. 38 is being executed. As shown in Fig. 39, in the program operation, the control signal BLC is set to the "H" level, so that the transistor T5 of the sense amplifier unit SAUe is turned on.

[0213] Moreover, the control signals BLSae and BLSbe are set to the “H” level and the “L” level, respectively, so that the transistors T9a and T9b of the sense amplifier unit SAUo are turned on and off, respectively. The control signals BIASae and BIASbe are set to the “L” level and the “H” level, respectively, so that the transistors T10a and T10b of the sense amplifier unit SAUe are turned off and on, respectively. In each of the NAND strings NSae and NSbe, the selection transistors STae, STao, STbe, and STbo to which the write pass voltage VPASS is applied are turned on. As a result, the even bit line BLae is charged in accordance with the write data via the transistor T9a (BLae:(Data(0 / 1)). Furthermore, the even bit line BLbe is charged in accordance with the voltage of the node BLBIAS via the transistor T10b (BLbe:inhibit).

[0214] This allows the sense amplifier unit SAUe to execute a program operation targeted at one of the sub-blocks SBLKa and SBLKb. Similarly, the sense amplifier unit SAUo can execute a program operation targeted at one of the sub-blocks SBLKa and SBLKb (not shown). That is, the memory device 1A can execute a program operation targeted at the NAND string NSae of the sub-block SBLKa and a program operation targeted at the NAND string NSbo of the sub-block SBLKb in parallel. Also, the memory device 1A can execute a program operation targeted at the NAND string NSbe of the sub-block SBLKa and a program operation targeted at the NAND string NSao of the sub-block SBLKb in parallel. Therefore, the memory device 1A can program (m+1) bits of data all at once.

[0215] (3: Verify operation) As a verify operation of the memory device 1A according to the second embodiment, either a first read operation or a second read operation is executed depending on the address. Also, as a verify operation of the memory device 1A, a shield read operation may be executed.

[0216] <2-3> Effects of the second embodiment A memory device having a stacked structure of memory cell arrays 10 (subarrays 101) is known. In such a memory device, the word lines WL are shared by the upper and lower subblocks SBLKa and SBLKb in order to suppress the transistor TR and the step width in the lead-out region HR, which increase with an increase in the number of stacked word lines WL. Then, a configuration is considered in which 16 KB of bit lines BL are provided in each of the subarrays 101a and 101b, and the 16 KB of bit lines BL of each of the subarrays 101a and 101b are connected to 16 KB of sense amplifier units SAU.

[0217] The memory device 1A according to the second embodiment executes a read operation (first read operation and second read operation) that can read 8 KB page data from the sub-array 101a and 8 KB page data from the sub-array 101b, and read a total of 16 KB of data at once. In other words, the memory device 1A can execute a read operation while realizing a 16 KB page read, by setting every other bit line BL to a floating state and halving the apparent capacitance of the bit lines BL.

[0218] As a result, the memory device 1A according to the second embodiment can improve the speed of the read operation and shorten the operation time.

[0219] Furthermore, the memory device 1A according to the second embodiment can realize a 16 KB page read in a shield read operation by putting every other bit line BL into a shield state (for example, a state in which a source line potential is applied). The shield read operation can improve the precharge speed of the bit lines BL compared to the case in which the floating state is used. Therefore, the memory device 1A according to the second embodiment can be operated with the same 16 KB sense amplifier unit SAU as in the conventional case, and can realize a 16 KB page read with a shortened operation time without increasing the circuit area. For example, in Power on Read (POR), the start-up time of the memory device 1A can be shortened by using a shield read of 16 KB page data instead of an 8 KB shield read operation. Furthermore, with the shield read, there is no current drain, so the power consumption of the memory device 1A can be suppressed.

[0220] Furthermore, the method of reading 8 KB page data from each of the sub-arrays 101a and 101b may be used in a verify operation during a write operation. In this case, the speed of the verify operation can be improved, as in the read operation. Also, the precharge time and stabilization time of the bit lines BL can be shortened during a program operation. Therefore, the memory device 1A according to the second embodiment can shorten not only the operation time of the read operation and the verify operation, but also the operation time of the program operation.

[0221] <3> Variations, etc. Below, modifications of the memory device 1 described in the above embodiment will be described.

[0222] In the first embodiment, the read pass voltage VREAD is used as the voltage for turning on the selection transistors SGe and SGo, but this is not limiting. If it is possible to turn on each of the selection transistors STe and STo, a voltage different from the read pass voltage VREAD may be used. Similarly, in the second embodiment, the read pass voltage VREAD is used as the voltage for turning on the selection transistors STae, STao, STbe, and STbo, but this is not limiting. If it is possible to turn on each of the selection transistors STae, STao, STbe, and STbo, a voltage different from the read pass voltage VREAD may be used.

[0223] Fig. 40 is a schematic diagram showing a modified example of the allocation of groups of bit lines BL. Fig. 40(A) corresponds to the grouping of bit lines BL described in the first embodiment. Specifically, a plurality of bit lines BL are classified into an even bit line group (group GR1) consisting of even bit lines BLe (BL0, BL2, ...) and an odd bit line group (group GR2) consisting of odd bit lines BLo (BL1, BL3, ...). In the grouping of bit lines BL in Fig. 40(A), the capacitance of the bit lines BL is reduced to approximately half.

[0224] In contrast, as shown in FIG. 40B, the grouping of the bit lines BL may be changed. Specifically, a plurality of pairs of two bit lines BL adjacent to each other in the X direction are arranged in the X direction. The plurality of pairs of two bit lines BL are classified into a group GR1 including an even number of pairs and a group GR2 including an odd number of pairs. Even in such a case, the memory device 1 can reduce the bit line capacitance and shorten the operation time. Since the capacitance of the bit line BL strongly depends on the capacitance component of the adjacent bit line BL, it is more preferable that the bit line BL set to the floating state and the bit line BL to be operated are adjacent to each other. This modification may be combined with the second embodiment. In the memory device 1A, it is only necessary that the pairs of the bit lines BLa and BLb connected to the same sense amplifier unit SAU are configured to be included in different groups.

[0225] FIG. 41 is a cross-sectional view showing a modified structure of the memory device 1. FIG. 41 shows the same region as FIG. 14 described in the first embodiment. In the modified example shown in FIG. 41, each of the conductor layers 21-25 does not have a terrace portion. In this case, each of the conductor layers 21-25 is provided in a plate shape in each of the lead-out regions HR1 and HR2. Then, each contact CC in the modified example penetrates the conductor layer between the wiring layer M0 and the conductor layer to which it is connected. Then, a spacer SP is provided on the side of each contact CC. This allows each contact CC in the modified example to function in the same way as the contact CC in the first embodiment. In this way, the memory device 1 only needs to have a structure in which a pair of a certain contact CC and an associated wiring is electrically connected to other stacked wiring without shorting even when a terrace portion is not provided in the lead-out region HR. This modified example may be combined with the second embodiment.

[0226] FIG. 42 is a cross-sectional view showing an example of a detailed cross-sectional structure of a bonding portion of a bonding pad BP. FIG. 42 shows a conductive layer 55 (bonding pad BP) of the CMOS layer 100, a conductive layer 28 (bonding pad BP) of the memory layer 200, and some contacts and wirings connected to these bonding pads BP. As shown in FIG. 42, two bonding pads BP arranged opposite to each other may have different taper shapes based on the etching direction during formation. Specifically, the conductive layer 55 formed using the first substrate W1 has, for example, an inverse taper shape that narrows toward the substrate W1. The conductive layer 28 formed using the second substrate W2 has, for example, a taper shape that widens toward the substrate W1. In addition, a pair of two bonding pads BP arranged opposite to each other may be bonded in a misaligned state depending on the alignment during the bonding process. For this reason, a step may be formed between the upper surface of the conductive layer 55 and the lower surface of the conductive layer 28. A pair of two bonding pads BP arranged opposite to each other may have a boundary or may be integrated. The bonding pad BP and a contact connected to the bonding pad BP may be formed integrally. The conductive layer 55 may be connected to the conductive layer 54 via a number of contacts C3. Similarly, the conductive layer 28 may be connected to the conductive layer 27 via a number of contacts V1.

[0227] In the above embodiment, the case where the memory layer 200 is provided above the CMOS layer 100 has been illustrated, but the CMOS layer 100 may be provided above the memory layer 200. In this case, for example, a wiring layer 300 (pads PD) is provided on the CMOS layer 100.

[0228] In the above embodiment, the circuit configuration, planar layout, and cross-sectional structure of the memory device 1 may be appropriately changed. For example, the semiconductor layer 41 of the memory pillar MP and the source line SL may be connected via the side surface of the memory pillar MP. The memory pillar MP may have a structure in which two or more pillars are connected in the Z direction. The memory pillar MP may have a structure in which a pillar corresponding to the select gate line SGD and a pillar corresponding to the word line WL are connected. Each contact may be connected by a plurality of contacts connected in the Z direction. A conductive layer may be inserted in the connection portion of the plurality of contacts. The number of wiring layers and contacts included in the memory device 1 may be appropriately changed.

[0229] In the drawings used in the description of the above embodiment, the memory pillar MP has the same diameter in the Z direction, but is not limited thereto. The memory pillar MP may have a tapered shape, an inverse tapered shape, or a bowing shape. Similarly, each of the slits SLT and SHE may have a tapered shape, an inverse tapered shape, or a bowing shape. Similarly, each of the contacts may have a tapered shape, an inverse tapered shape, or a bowing shape. The cross-sectional structures of the memory pillar MP and the contacts V0 to V3, CC, and C3 may be circular or elliptical.

[0230] In this specification, "connection" refers to being electrically connected, and does not exclude, for example, the presence of another element therebetween. "Electrically connected" may be via an insulator as long as it can operate in the same way as something electrically connected. "Tapered shape" refers to a shape that becomes thinner as it moves away from a reference substrate. "Inverse tapered shape" refers to a shape that becomes thicker as it moves away from a reference substrate. "Columnar" refers to a structure provided in a hole formed in the manufacturing process of the memory device 1. "Semiconductor layer" may be called "conductive layer". Word lines WL, select gate lines SGD, SGS, SGe, and SGo, etc. may be simply called "wiring".

[0231] In this specification, the components that are the references for even and odd numbers do not necessarily have to be components arranged at the ends. Any components may be used as the references for even and odd numbers. In this specification, the NAND string NS may be called a "string." The NAND string NS connected to the even bit line BLe may be called an "even string." The NAND string NS connected to the odd bit line BLo may be called an "odd string." An "H" level voltage is a logic level at which an N-type transistor having a voltage of that level applied to its gate is turned on. An "L" level voltage is a logic level at which an N-type transistor having a voltage of that level applied to its gate is turned off.

[0232] In this specification, application of a voltage to a word line WL corresponds to the driver circuit 15 applying a voltage to the word line WL via the row decoder module 16. Application of a voltage to other stacked wirings also corresponds to the driver circuit 15 applying a voltage to the word line WL via the row decoder module 16, similar to the word line WL. The voltage of the stacked wirings may be estimated based on the voltage of a signal line connecting the driver circuit 15 and the row decoder module 16. In this specification, an "area" may be considered as a configuration included in a reference substrate. For example, when the first substrate W1 is defined to include a memory region MR and a drawing region HR, the memory region MR and the drawing region HR are respectively associated with different regions above the first substrate W1.

[0233] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0234] 1,1A...memory device, 2...memory controller, 10,10A...memory cell array, 11...input / output circuit, 12...logic controller, 13...register circuit, 14...sequencer, 15,15A...driver circuit, 16,16A...row decoder module, 17...data register, 18,18A...sense amplifier module, 20-29...conductor layer, 30-37...insulator layer, 40...core member, 41...semiconductor layer, 42...laminated film, 43...tunnel insulating film, 44...insulator film, 45...block insulating film, 50,51...insulator layer, 52-55...conductor layer, 70,80, 81...insulating layer, 82...conductive layer, 100...CMOS layer, 101a, 101b...subarray, 200...memory layer, 300...wiring layer, BL...bit line, WL...word line, SGD, SGS, SGe, SGo...selection gate line, SL...source line, BLK...block, SU...string unit, NS...NAND string, MT...memory cell transistor, STe, STo...selection transistor, C0 to C3...contact, RD...row decoder, SAU...sense amplifier unit, SBLKa, SBLKb...sub-block, V0 to V3...contact, W1 to W3...substrate

Claims

1. A plurality of bit lines; a plurality of strings each including a memory cell, a first transistor, and a second transistor connected in series, the strings being connected at one end to the plurality of bit lines; a first wiring connected to the first transistor of each of the plurality of strings; a second wiring connected to the second transistor of each of the plurality of strings; a word line connected to the memory cells of each of the plurality of strings; A sequencer, The sequencer includes: In a read operation of N bytes (N is an integer equal to or greater than 1) in which the word line is selected, a first voltage is applied to one of the first wiring and the second wiring, and a second voltage higher than the first voltage is applied to the other of the first wiring and the second wiring; applying a third voltage higher than the first voltage to each of the first wiring and the second wiring in a 2×N byte read operation in which the word line is selected; Memory device.

2. A plurality of sense amplifier units are connected to the plurality of bit lines, respectively, and configured to be able to determine data; each of the plurality of sense amplifier units includes a third transistor connected to any one of the plurality of bit lines; in a read operation of N bytes in which the word line is selected, the third transistors included in the plurality of sense amplifier units and corresponding in number to the N bytes are controlled to an on state, and the remaining third transistors are controlled to an off state; In a read operation of 2×N bytes in which the word line is selected, the third transistors included in the plurality of sense amplifier units and corresponding in number to the 2×N bytes are controlled to be in an on state. The memory device of claim 1 .

3. the N-byte read operation has first and second modes; the sequencer applies the first voltage and the second voltage to the first wiring and the second wiring, respectively, in the first mode, and applies the second voltage and the first voltage to the first wiring and the second wiring, respectively, in the second mode; The memory device of claim 2 .

4. In the N-byte read operation, the sequencer In the first mode, the third transistor connected to an even-numbered bit line included in the plurality of bit lines is controlled to an on state; In the second mode, the third transistor connected to an odd-numbered bit line included in the plurality of bit lines is controlled to an on state. The memory device of claim 3 .

5. In an even-numbered string connected to the even-numbered bit line among the plurality of strings, a threshold voltage of the first transistor is lower than a threshold voltage of the second transistor; In an odd-numbered string connected to the odd-numbered bit line among the plurality of strings, a threshold voltage of the first transistor is higher than a threshold voltage of the second transistor. The memory device of claim 3 .

6. the first voltage is a voltage between a threshold voltage of the first transistor and a threshold voltage of the second transistor in the even string, and a voltage between a threshold voltage of the first transistor and a threshold voltage of the second transistor in the odd string; the second voltage is higher than a threshold voltage of the second transistor in the even string and higher than a threshold voltage of the first transistor in the odd string; The memory device of claim 1 .

7. Further comprising a substrate; In each of the plurality of strings, the first transistor, the second transistor, and the memory cell are arranged in a direction intersecting a surface of the substrate. The memory device of claim 1 .

8. The second voltage is approximately equal to the third voltage. The memory device of claim 1 .

9. a CMOS layer, a first memory layer, and a second memory layer stacked in a first direction; A sequencer, the first memory layer includes a plurality of first bit lines and a plurality of first strings, each of which has one end connected to the plurality of first bit lines, the second memory layer includes a plurality of second bit lines and a plurality of second strings, each of which has one end connected to the plurality of second bit lines, the CMOS layer includes a plurality of sense amplifier units respectively connected to the plurality of first bit lines and to the plurality of second bit lines, and configured to be able to determine data, each of the plurality of sense amplifier units includes a first transistor connected to any one of the plurality of first bit lines, a second transistor connected to any one of the plurality of second bit lines, and a sense node connected to each of the first transistor and the second transistor, the plurality of sense amplifier units include a plurality of first sense amplifier units and a plurality of second sense amplifier units, The sequencer, in a read operation, applying a voltage of a first logic level to the first transistor of each of the plurality of first sense amplifier units, and applying a voltage of a second logic level different from the first logic level to the second transistor of each of the plurality of first sense amplifier units; applying a voltage of the second logic level to the first transistor of each of the plurality of second sense amplifier units, and applying a voltage of the first logic level to the second transistor of each of the plurality of second sense amplifier units; Memory device.

10. The sequencer includes: in the first read operation, the first transistor of the first sense amplifier unit and the second transistor of the second sense amplifier unit are each controlled to an on state, and the second transistor of the first sense amplifier unit and the first transistor of the second sense amplifier unit are each controlled to an off state; in the second read operation, the second transistor of the first sense amplifier unit and the first transistor of the second sense amplifier unit are each controlled to an on state, and the first transistor of the first sense amplifier unit and the second transistor of the second sense amplifier unit are each controlled to an off state; The memory device of claim 9.

11. each of the plurality of first strings includes a first memory cell, a third transistor, and a fourth transistor connected in series; the first memory layer further includes a first wiring connected to the third transistor of each of the plurality of first strings, a second wiring connected to the fourth transistor of each of the plurality of first strings, and a first word line connected to the first memory cell of each of the plurality of first strings; each of the plurality of second strings includes a second memory cell, a fifth transistor, and a sixth transistor connected in series; the second memory layer further includes a third wiring connected to the fifth transistor of each of the plurality of second strings, a fourth wiring connected to the sixth transistor of each of the plurality of second strings, and a second word line connected to the second memory cell of each of the plurality of second strings and electrically connected to the first word line; The sequencer includes: in a first read operation in which the first and second word lines are selected, a first voltage is applied to the first wiring, a second voltage higher than the first voltage is applied to the second wiring, the first voltage is applied to the third wiring, and the second voltage is applied to the fourth wiring; The memory device of claim 9.

12. The sequencer includes: in a second read operation in which the first and second word lines are selected, the second voltage is applied to the first wiring, the first voltage is applied to the second wiring, the second voltage is applied to the third wiring, and the first voltage is applied to the fourth wiring; The memory device of claim 11.

13. In an even-numbered first string connected to an even-numbered first bit line among the plurality of first strings, a threshold voltage of the third transistor is lower than a threshold voltage of the fourth transistor; In an odd-numbered first string connected to an odd-numbered first bit line among the plurality of first strings, a threshold voltage of the third transistor is higher than a threshold voltage of the fourth transistor; In an even-numbered second string connected to an even-numbered second bit line among the plurality of second strings, a threshold voltage of the fifth transistor is higher than a threshold voltage of the sixth transistor; In an odd-numbered second string connected to an odd-numbered second bit line among the plurality of second strings, a threshold voltage of the fifth transistor is lower than a threshold voltage of the sixth transistor. The memory device of claim 11.

14. the first voltage is a voltage between a threshold voltage of the third transistor and a threshold voltage of the fourth transistor in the first even string, a voltage between a threshold voltage of the third transistor and a threshold voltage of the fourth transistor in the first odd string, a voltage between a threshold voltage of the fifth transistor and a threshold voltage of the sixth transistor in the second even string, and a voltage between a threshold voltage of the fifth transistor and a threshold voltage of the sixth transistor in the second odd string; the second voltage is higher than a threshold voltage of the fourth transistor in the even first string, higher than a threshold voltage of the third transistor in the odd first string, higher than a threshold voltage of the fifth transistor in the even second string, and higher than a threshold voltage of the sixth transistor in the odd second string; The memory device of claim 13.

15. each of the plurality of sense amplifier units includes a seventh transistor connected to any one of the plurality of first bit lines, an eighth transistor connected to any one of the plurality of second bit lines, and a first node connected to each of the seventh transistor and the eighth transistor; the sequencer applies a voltage of the second logic level to each of the seventh transistor and the eighth transistor of each of the plurality of sense amplifier units in the read operation; The memory device of claim 9.

16. each of the plurality of sense amplifier units includes a seventh transistor connected to any one of the plurality of first bit lines, an eighth transistor connected to any one of the plurality of second bit lines, and a first node connected to each of the seventh transistor and the eighth transistor; the sequencer applies a voltage of the first logic level to each of the seventh transistor and the eighth transistor of each of the plurality of sense amplifier units, and applies a third voltage to the first node, in the read operation; The memory device of claim 9.

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