Semiconductor device

Abstract

To reduce a clamp voltage and increase a clamp resistant amount and a durability of a high-voltage application.SOLUTION: A semiconductor device 1 includes a switch element 1a, a driving circuit 1b, a drawing circuit 1c, and a voltage control circuit 1d. The switch element 1a is a power semiconductor switch element, and a positive electrode end of a power source part 4 is connected to a high potential terminal p1 of the switch element 1a. The drive circuit 1b drives switching of the switch element 1a by applying a control voltage on a control terminal p2 of the switch element 1a and operates a dielectric load 3 connected to the switch element 1a. The drawing circuit 1c draws a control terminal charge from the control terminal p2 of the switch element 1a in a case where the switch element 1a is shifted from turning-on to turning-off. The voltage control circuit 1d clamps reduction of the voltage in a connection point between a low-potential terminal p3 of the switch element 1a and the dielectric load 3 to a predetermined voltage when the control terminal charge is being drawn.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Among various electronic devices mounted on vehicles, there is a device that drives a switch element in response to a control signal to operate an inductive load, and one-chip semiconductor devices are known. Such semiconductor devices are equipped with an active clamp circuit to prevent the devices in the device from being destroyed when the inductive load is clamped.

[0003] As a related technique, for example, a technique has been proposed in which a clamp voltage determined by an active clamp circuit is set to a first clamp voltage when no positive voltage change is detected at the output terminal, and when a positive voltage change is detected, the clamp voltage is set to a second clamp voltage lower than the first clamp voltage. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2019-165542 A Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to reduce the clamp voltage, improve the clamp withstand capability, and improve the durability against high voltage application. [Means for solving the problem]

[0006] In order to solve the above problems, a semiconductor device is provided. The semiconductor device has a switch element, a drive circuit, an extraction circuit, and a voltage control circuit. The switch element has a positive terminal of a power supply connected to a high potential terminal. The drive circuit applies a control voltage to a control terminal of the switch element to switch-drive the switch element and operate an inductive load connected to the switch element. The extraction circuit extracts charge from the control terminal of the switch element when the switch element transitions from turn-on to turn-off. The voltage control circuit clamps the voltage drop at the connection point between the low potential terminal of the switch element and the inductive load to a predetermined voltage while the control terminal charge is being extracted. Effect of the Invention

[0007] According to one aspect, it is possible to reduce the clamp voltage, improve the clamp withstand capability, and improve the durability against high voltage application. [Brief description of the drawings]

[0008] [Figure 1] 1A and 1B are diagrams illustrating an example of a semiconductor device. [Diagram 2] FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device including an active clamp circuit. [Diagram 3] FIG. 1 is a diagram illustrating an example of a configuration of an active clamp circuit. [Figure 4] FIG. 2 is a diagram showing an example of an operation waveform of the semiconductor device; [Diagram 5] FIG. 13 is a diagram showing the relationship between clamp voltage and clamp withstand voltage. [Figure 6] FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device. [Figure 7] FIG. 2 is a diagram showing an example of an operation waveform of the semiconductor device; [Figure 8] FIG. 13 is a diagram showing the relationship between clamp voltage and clamp withstand voltage. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the present embodiment will be described with reference to the drawings. In this specification and the drawings, elements having substantially the same configuration are denoted by the same reference numerals, and duplicated description may be omitted.

[0010] 1 is a diagram for explaining an example of a semiconductor device. The semiconductor device 1 includes a switch element 1a, a drive circuit 1b, an extraction circuit 1c, and a voltage control circuit 1d. The semiconductor device 1 also includes an output terminal OUT, an input terminal IN, and a power supply terminal Vin. An inductive load 3 is connected to the output terminal OUT. The inductive load 3 is, for example, an inductive load such as a solenoid valve that is widely used in automobiles.

[0011] A control unit such as an ECU (Electronic Control Unit) (not shown) is connected to the input terminal IN, and a control signal output from the control unit is input to the input terminal IN. A power supply unit 4 that outputs a power supply voltage VCC is connected to the power supply terminal Vin.

[0012] The switch element 1a is a power semiconductor switch element having a high potential terminal p1, a control terminal p2, and a low potential terminal p3, and is, for example, a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). The high potential terminal p1 of the switch element 1a is connected to the positive terminal of the power supply unit 4. When the switch element 1a is a power MOSFET, in the configuration of the semiconductor device 1, the high potential terminal p1, the control terminal p2, and the low potential terminal p3 correspond to the drain, gate, and source, respectively.

[0013] The drive circuit 1b applies a control voltage to the control terminal p2 of the switch element 1a based on a control signal input via the input terminal IN, thereby driving the switch element 1a to perform switching operation, and operates the inductive load 3 connected to the switch element 1a via the output terminal OUT.

[0014] The extraction circuit 1c extracts charge from the control terminal p2 of the switch element 1a when the switch element 1a transitions from turn-on to turn-off. The voltage control circuit 1d clamps the voltage drop at the connection point (corresponding to the output terminal OUT) between the low potential terminal p3 of the switch element 1a and the inductive load 3 to a predetermined voltage while the control terminal charge is being extracted.

[0015] Such a configuration of the semiconductor device 1 makes it possible to reduce the clamp voltage, improve the clamp withstand capability, and improve durability against high voltage application. Before describing the details of the present invention, a semiconductor device including an active clamp circuit will be described with reference to Figures 2 to 5. In the following description, the inductive load 3 will be referred to as an L load 3.

[0016] 2 is a diagram showing an example of the configuration of a semiconductor device including an active clamp circuit. The semiconductor device 10a includes an output terminal OUT, an input terminal IN, and a power supply terminal Vin. An L load 3 is connected to the output terminal OUT. A control signal is input from an ECU or the like to the input terminal IN. A power supply unit 4 with VCC=16V, for example, is connected to the power supply terminal Vin.

[0017] The semiconductor device 10a includes a drive circuit 11, an active clamp circuit 2, resistors R1 and R2, an output stage switch M1, and a gate charge extraction MOS transistor M2. The output stage switch M1 and the gate charge extraction MOS transistor M2 are formed using N-channel MOSFETs (NMOS transistors).

[0018] The active clamp circuit 2 includes diodes D1 and D2. The resistor R1 functions as a protective resistor that protects the output stage switch M1 connected in series with the resistor R1 from surge noise, current input exceeding a permissible value, etc. The resistor R2 is a pull-down resistor.

[0019] Regarding the connection relationship of each element, the input terminal IN is connected to the input end of the drive circuit 11. The power supply terminal Vin is connected to the positive terminal of the power supply unit 4, the drain of the output stage switch M1, the cathode of the diode D1, and one of the power supply terminals of the drive circuit 11.

[0020] The anode of diode D1 is connected to the anode of diode D2, and the cathode of diode D2 is connected to one end of resistor R1, one end of resistor R2, the drain of gate charge extraction MOS transistor M2, and the signal output terminal a1 of drive circuit 11. The other end of resistor R1 is connected to the gate of output stage switch M1. The gate of gate charge extraction MOS transistor M2 is connected to signal output terminal a2 of drive circuit 11.

[0021] The output terminal OUT is connected to one end of the L load 3, the source of the output stage switch M1, the other end of the resistor R2, the source of the gate charge extraction MOS transistor M2, and the other power supply terminal of the drive circuit 11. The other end of the L load 3 is connected to the negative terminal of the power supply unit 4 and ground (GND).

[0022] When an H-level control signal is input to the input terminal IN, the drive circuit 11 outputs an H-level signal from the signal output terminal a1 toward the gate of the output stage switch M1 to turn on the output stage switch M1.

[0023] Furthermore, when an L-level control signal is input to the input terminal IN, the drive circuit 11 outputs an L-level signal from the signal output terminal a1 to the gate of the output stage switch M1 to turn off the output stage switch M1. The output stage switch M1 functions as a switch element for controlling the current flowing to the L load 3 based on such switching control by the drive circuit 11.

[0024] When the output stage switch M1 is turned on, the drive circuit 11 outputs an L level signal from the signal output terminal a2 to turn off the gate charge extraction MOS transistor M2, and when the output stage switch M1 transitions to turn off, the drive circuit 11 outputs an H level signal from the signal output terminal a2 to turn on the gate charge extraction MOS transistor M2.

[0025] When the gate charge extracting MOS transistor M2 is turned on, a gate charge equivalent to the control voltage of the output stage switch M1 is extracted via the resistor R1, the gate of the output stage switch M1 becomes the L level, and this prompts the output stage switch M1 to be turned off.

[0026] In this way, by using the gate charge extracting MOS transistor M2 to extract the gate voltage when the output stage switch M1 is turned off, it is possible to keep the switching time of the output stage switch M1 within a predetermined time period and suppress switching loss.

[0027] On the other hand, the active clamp circuit 2 protects the output stage switch M1 from an overvoltage generated by the inductance of the L load 3 when the output stage switch M1 transitions from turn-on to turn-off.

[0028] 3 is a diagram showing an example of the configuration of an active clamp circuit. The diode D1 in the active clamp circuit 2 can be composed of one or more diffusion junction Zener diodes D1-1, . . . , D1-n. The diode D2 in the active clamp circuit 2 can be composed of one or more polysilicon Zener diodes D2-1, . . . , D2-n.

[0029] 4 is a diagram showing an example of operational waveforms of the semiconductor device, which shows operational waveforms when the L load 3 is clamped in the semiconductor device 10a. A waveform g11 shows the waveform of the control signal VIN at the input terminal IN.

[0030] A waveform g12 indicates the waveform of the voltage VOUT at the output terminal OUT. A waveform g13 indicates the waveform of the current IOUT flowing from the output stage switch M1 to the L load 3 via the output terminal OUT.

[0031] [Period t11] When the device is started up, the control signal VIN goes to L level. At this time, the gate of the output stage switch M1 goes to L level, so the output stage switch M1 is turned off. Also, the source of the output stage switch M1 is connected to the output terminal OUT, and because the output stage switch M1 is turned off, the voltage VOUT goes to 0V. Furthermore, because the output stage switch M1 is turned off, the current IOUT does not flow and is 0A.

[0032] [Period t12] The control signal VIN goes to H level (for example, 5V). At this time, the gate of the output stage switch M1 goes to H level, so the output stage switch M1 is turned on. Since the output stage switch M1 is turned on, the current IOUT flows from the output terminal OUT to the L load 3, and the current IOUT increases. Furthermore, when the power supply voltage VCC of the power supply unit 4 is 16V, the output stage switch M1 is turned on, so the voltage VOUT rises to 16V.

[0033] [Period t13] The control signal VIN goes to the L level. At this time, the gate of the output stage switch M1 is at the L level, and the output stage switch M1 is turned off, so the flow of the current IOUT from the output terminal OUT to the L load 3 decreases as it starts to flow away.

[0034] On the other hand, since an L load 3 is connected to the output terminal OUT, when the output stage switch M1 transitions from turn-on to turn-off to attempt to cut off the flow of current IOUT, the current flowing through the L load 3 attempts to maintain its flow, and a back electromotive force is generated in the L load 3 in a direction that attempts to cause the current IOUT to flow.

[0035] For example, if the peak of the potential difference between the power supply terminal Vin and the output terminal OUT during period t13 is 50 V and the power supply unit 4 is set to 16 V, the voltage VOUT will drop to -34 V, and the voltage between VCC and OUT at this time will be the clamp voltage.

[0036] If, during period t13, the breakdown voltage of diode D1 in active clamp circuit 2 is exceeded and diode D1 breaks down, current IOUT flows through diode D1 in the reverse direction from cathode to anode. If the voltage applied between the gate and source of output stage switch M1 at this time exceeds the threshold voltage of output stage switch M1, output stage switch M1 turns on and current IOUT flows through output stage switch M1 to output terminal OUT.

[0037] Furthermore, the remaining current IOUT that did not flow toward the output stage switch M1 flows through diode D2 and resistor R2 toward the output terminal OUT. By performing such control, the energy stored in the inductance of the L load 3 when the L load 3 is clamped is processed (the surge current when the L load 3 is clamped is processed).

[0038] [Period t14] When the energy processing of the L load 3 is completed, the same operation as in period t11 occurs. As described above, when the control signal VIN becomes H level, the output stage switch M1 is turned on and current flows through the L load 3. When the output stage switch M1 is turned off, the back electromotive force generated in the L load 3 causes the voltage VOUT to drop to a negative voltage.

[0039] At this time, if the withstand voltage of the diode D1 inserted between the drain and gate of the output stage switch M1 is exceeded, current flows into the gate of the output stage switch M1, turning the output stage switch M1 on, and current also flows through the pull-down resistor R2, making it possible to dispose of the energy stored in the L load 3.

[0040] 5 is a diagram showing the relationship between clamp voltage and clamp withstand capability. The vertical axis is clamp withstand capability (mJ) and the horizontal axis is clamp voltage (V). The clamp withstand capability j1 when the clamp voltage is 50V is smaller than the clamp withstand capability j2 when the clamp voltage is 30V.

[0041] When the clamp voltage is 50 V, the energy processing of the L load 3 is completed in a shorter time than when the clamp voltage is 30 V. However, when the energy processing is completed in a short time, the output stage switch M1 generates a lot of heat, the clamp withstand capability is smaller than when the clamp voltage is 30 V, and the element is more likely to be destroyed.

[0042] As described above, since the clamp withstand voltage depends on the clamp voltage, the clamp withstand voltage can be improved by lowering the clamp voltage as much as possible. On the other hand, if the clamp voltage is lowered, it becomes difficult to configure an active clamp circuit that can withstand high voltage application. The present invention has been made in view of the above points, and provides a semiconductor device that can reduce the clamp voltage to improve the clamp withstand voltage and improve durability against high voltage application.

[0043] Next, the semiconductor device of the present invention will be described in detail below. FIG. 6 is a diagram showing an example of the configuration of a semiconductor device. A semiconductor device 10 of the present invention controls the high side of a power module such as an IPS (Intelligent Power Switch). The semiconductor device 10 includes an output terminal OUT, an input terminal IN, a power supply terminal Vin, and a ground terminal (GND terminal). An L load 3 is connected to the output terminal OUT. A control signal is input to the input terminal IN. A power supply unit 4 of, for example, VCC=16V is connected to the power supply terminal Vin.

[0044] The semiconductor device 10 includes a drive circuit 11, a voltage control circuit 12, resistors R1 and R2, an output stage switch M1 (switch element), a gate charge extracting MOS transistor M2 (first MOS transistor), and a ground resistor (GND resistor) R4.

[0045] The voltage control circuit 12 includes a resistor R3 and a voltage control MOS transistor M3 (second MOS transistor). The voltage control MOS transistor M3 has a source follower function in which the output voltage follows the input voltage. The resistor R3 also has a protective resistor function that protects the voltage control MOS transistor M3 connected in series to the resistor R3 from surge noise, current input exceeding a tolerance, and the like.

[0046] An NMOS transistor (first NMOS transistor) is used for the gate charge extraction MOS transistor M2, and an NMOS transistor (second NMOS transistor) is used for the voltage control MOS transistor M3. In comparison with the semiconductor device 10a shown in FIG. 2, the semiconductor device 10 does not include the active clamp circuit 2, but includes a voltage control circuit 12.

[0047] Regarding the connection relationship of each element, the input terminal IN is connected to the input terminal of the drive circuit 11. The power supply terminal Vin is connected to the positive terminal of the power supply unit 4, the drain of the output stage switch M1, and one of the power supply terminals of the drive circuit 11. One end of the resistor R1 is connected to one end of the resistor R2, the drain of the gate charge extraction MOS transistor M2, and the signal output terminal a1 of the drive circuit 11.

[0048] The other end of the resistor R1 is connected to the gate of the output stage switch M1. The gate of the gate charge extraction MOS transistor M2 is connected to the drain of the voltage control MOS transistor M3 and the signal output terminal a2 of the drive circuit 11.

[0049] The output terminal OUT is connected to one end of the L load 3, the source of the output stage switch M1, the other end of the resistor R2, the source of the gate charge extraction MOS transistor M2, the source of the voltage control MOS transistor M3, and the other power supply terminal of the drive circuit 11. One end of the resistor R3 is connected to the gate of the voltage control MOS transistor M3. The other end of the resistor R3 is connected to one end of a ground resistor R4. The other end of the ground resistor R4 is connected to the GND terminal, and the GND terminal is connected to the other end of the L load 3, the negative terminal of the power supply unit 4, and GND (reference potential).

[0050] 7 is a diagram showing an example of the operating waveforms of the semiconductor device. The diagram shows the operating waveforms when the L load 3 is clamped in the semiconductor device 10. The waveform g1 is the waveform of the control signal VIN at the input terminal IN, and the waveform g2 is the waveform of the gate voltage VgM1 of the output stage switch M1.

[0051] The waveform g3 is the waveform of the voltage VOUT at the output terminal OUT, and the waveform g4 is the waveform of the gate voltage VgM2 of the gate charge extraction MOS transistor M2. Waveform g5 is the waveform of current IM2 flowing from the drain to the source of gate charge extraction MOS transistor M2, waveform g6 is the waveform of current IM3 flowing from the drain to the source of voltage control MOS transistor M3, and waveform g7 is the waveform of current IOUT flowing from output stage switch M1 to L load 3 via output terminal OUT.

[0052] [Period t1] When the device is turned on, the control signal VIN goes to the L level. At this time, the gate voltage VgM1 of the output stage switch M1 is at the L level, and the output stage switch M1 is turned off. The source of the output stage switch M1 is connected to the output terminal OUT, and since the output stage switch M1 is turned off, the voltage VOUT goes to 0V.

[0053] Furthermore, when the gate voltage VgM1 is 0 V, the gate charge extraction MOS transistor M2 is turned on but the current IM2 does not flow when the device is started up. The voltage control MOS transistor M3 is off so the current IM3 does not flow, and the output stage switch M1 is turned off so the current IOUT does not flow and is 0 A.

[0054] [Period t2] The control signal VIN becomes H level (for example, 5V). At this time, the gate voltage VgM1 of the output stage switch M1 rises, and the output stage switch M1 turns on. Also, when the power supply voltage VCC of the power supply unit 4 is 16V, the output stage switch M1 is on, so the voltage VOUT becomes 16V.

[0055] Furthermore, when the gate voltage VgM1 rises, the gate voltage VgM2 goes to the L level, turning off the gate charge extraction MOS transistor M2 and stopping the extraction of the gate voltage of the output stage switch M1. Since the voltage control MOS transistor M3 is off, the current IM3 does not flow. Furthermore, since the output stage switch M1 is turned on, the current IOUT flows from the output terminal OUT to the L load 3, and the current IOUT increases.

[0056] [Period t3] The control signal VIN becomes L level. The gate voltage VgM1 of the output stage switch M1 decreases, and the output stage switch M1 starts to turn off. The output stage switch M1 transitions from turn-on to turn-off.

[0057] At this time, the gate voltage VgM2 goes to H level, the gate charge extraction MOS transistor M2 turns on, and the gate voltage VgM1 is extracted via the gate charge extraction MOS transistor M2, causing the voltage VOUT to decrease. Also, the gate charge extraction MOS transistor M2 turns on and extracts the gate voltage VgM1, causing a current IM2 to flow. The voltage control MOS transistor M3 is off, so no current IM3 flows.

[0058] [Period t4] When the clamp of the L load 3 is in operation, if the threshold voltage of the voltage control MOS transistor M3 is Vth, when the voltage VOUT falls below the differential voltage (GND-Vth) between GND and the threshold voltage Vth, the voltage control MOS transistor M3 turns on.

[0059] In addition, the gate charge extraction MOS transistor M2 is turned off and stops extracting the gate voltage VgM1, or is kept slightly on to minimize the amount of extraction, so that the gate charge is extracted via resistor R2, decreasing the extraction speed.

[0060] Then, by turning on the voltage control MOS transistor M3, the drop in the voltage VOUT at the output terminal OUT is clamped to the differential voltage (GND-Vth), and the drop in the voltage VOUT stops. That is, the voltage VOUT is determined by the source follower of the voltage control MOS transistor M3, and is clamped at the value of the differential voltage (GND-Vth). Therefore, the clamp voltage becomes -Vth (=GND-Vth), which is -3V in the example of FIG. 7. When the period t4 ends, the same operation as in the period t1 occurs.

[0061] 8 is a diagram showing the relationship between clamp voltage and clamp withstand capability. The vertical axis is clamp withstand capability (mJ), and the horizontal axis is clamp voltage (V). When viewed in terms of the absolute value of the clamp voltage, the clamp voltage is reduced to 3V due to the configuration of semiconductor device 10. Therefore, clamp withstand capability j3 when clamp voltage=3V is greater than clamp withstand capabilities j1 and j2, and the clamp withstand capability can be improved at a low clamp voltage. In addition, since the clamp voltage can be reduced without using active clamp circuit 2, durability against high voltage application can be ensured.

[0062] As described above, according to the present invention, a voltage control MOS transistor M3 is provided between the gate and source of the gate charge extraction MOS transistor M2 that extracts the gate voltage of the output stage switch M1, and the voltage VOUT during L load clamping is controlled by switching the voltage control MOS transistor M3. This makes it possible to lower the clamp voltage and improve the clamp tolerance of the L load 3, and also makes it possible to realize a circuit that can withstand high voltage application.

[0063] Although the embodiments have been described above, the configurations of the parts shown in the embodiments can be replaced with other configurations having similar functions. Any other components or steps may be added. Furthermore, any two or more configurations (features) of the above-described embodiments may be combined. [Explanation of symbols]

[0064] 1 Semiconductor device 1a Switch element 1b Drive circuit 1c Withdrawal circuit 1d Voltage control circuit 3 Inductive load 4 Power supply section p1 High potential terminal p2 control terminal p3 Low potential terminal VCC Power supply voltage IN Input terminal OUT Output terminal Vin power terminal

Claims

1. A switch element having a high potential terminal connected to a positive terminal of a power supply unit; a drive circuit that applies a control voltage to a control terminal of the switch element to switch-drive the switch element and operate an inductive load connected to the switch element; an extraction circuit that extracts a control terminal charge from a control terminal of the switch element when the switch element transitions from turn-on to turn-off; a voltage control circuit that clamps a voltage drop at a connection point between the low potential terminal of the switch element and the inductive load to a predetermined voltage while the charge at the control terminal is being drawn off; A semiconductor device having the above structure.

2. the pull-out circuit includes a first MOS transistor disposed between the control terminal of the switch element and the connection point, and the voltage control circuit is a second MOS transistor disposed between a control terminal of the first MOS transistor and the connection point and functioning as a source follower. The semiconductor device according to claim 1 .

3. The clamping is performed by turning on the second MOS transistor to stop or minimize the extraction of the charge from the control terminal by the first MOS transistor. The semiconductor device according to claim 2 .

4. the first MOS transistor is a first NMOS transistor and the second MOS transistor is a second NMOS transistor; a drain of the first NMOS transistor is connected to a control terminal of the switch element; the drain of the second NMOS transistor is connected to the gate of the first NMOS transistor; The gate of the second NMOS transistor is connected to a reference potential via a resistor; the source of the second NMOS transistor is connected to the source of the first NMOS transistor and to the connection point; The semiconductor device according to claim 3 .

5. the second NMOS transistor is turned on when the voltage at the connection point becomes equal to or lower than a differential voltage obtained by subtracting a threshold voltage of the second NMOS transistor from the reference potential while the first NMOS transistor is drawing out the charge at the control terminal, and clamps the voltage at the connection point to the differential voltage. The semiconductor device according to claim 4.

6. the extraction circuit further includes a pull-down resistor disposed between the control terminal of the switch element and the connection point; The pull-down resistor pulls out the charge of the control terminal of the switch element during the clamping. The semiconductor device according to claim 5 .

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