Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a low-cost semiconductor device.SOLUTION: There is provided a memory cell including a first transistor, a second transistor, and a capacitor. The second transistor is located above the first transistor and the capacitor. In the capacitor, one of a pair of electrodes, a dielectric layer, and the other of the pair of electrodes are provided in this order. A gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and the other of the pair of electrodes of the capacitor are the same conductive layer. A gate insulating layer of the first transistor and the dielectric layer of the capacitor are the same insulating layer. A semiconductor layer of the first transistor and the one of the pair of electrodes of the capacitor are provided along a sidewall of an opening portion included in a first interlayer insulating layer. A semiconductor layer of the second transistor is provided along a sidewall of an opening portion included in a second interlayer insulating layer over the first transistor and the capacitor. The first transistor and the second transistor are vertical transistors, and the capacitor is a trench capacitor.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of a semiconductor device. Also, a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and on which electrodes that serve as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of the components in various electronic devices.

[0006] In addition, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but metal oxides are also attracting attention as other materials.

[0007] It is also known that transistors using metal oxides have an extremely small leakage current in an off state. For example, Patent Document 1 discloses a low-power consumption CPU or the like that utilizes the property of low leakage current of transistors using metal oxides. In addition, for example, Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using metal oxides.

[0008] In addition, in recent years, with the miniaturization and weight reduction of electronic devices, there is an increasing demand for further density of integrated circuits. In addition, there is a demand for improving the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology for increasing density of integrated circuits by stacking a first transistor using a metal oxide film and a second transistor using a metal oxide film to provide multiple memory cells in a superimposed manner. In addition, Patent Document 4 discloses a technology for increasing density of integrated circuits by vertically arranging the channel of a transistor using a metal oxide film. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A [Patent Document 3] International Publication No. 2021 / 053473 [Patent Document 4] JP 2013-211537 A [Non-patent literature]

[0010] [Non-Patent Document 1] M.Oota et.al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp.50-53 Summary of the Invention [Problem to be solved by the invention]

[0011] In the case of stacking a plurality of transistors, the number of manufacturing steps of the semiconductor device increases as compared to the case of providing the transistors in the same layer, which may increase the manufacturing cost of the semiconductor device and the price of the semiconductor device.

[0012] An object of one embodiment of the present invention is to provide a low-cost semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high operation speed. Another object of one embodiment of the present invention is to provide a semiconductor device including a transistor with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device including a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0013] Alternatively, an object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with a small number of steps. Alternatively, an object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with a high yield. Alternatively, an object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device that enables miniaturization or high integration. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high operating speed. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device including a transistor with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device including a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a method for manufacturing a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0014] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description of the specification, drawings, and claims. [Means for solving the problem]

[0015] One embodiment of the present invention is a semiconductor device including a first vertical transistor, a second vertical transistor, and a trench capacitor, in which the first vertical transistor has a first lower electrode functioning as one of a source electrode and a drain electrode, and a first upper electrode located on the first lower electrode and functioning as the other of the source electrode and drain electrode, the second vertical transistor has a second lower electrode functioning as one of the source electrode and drain electrode, and a second upper electrode located on the second lower electrode and functioning as the other of the source electrode and drain electrode, the trench capacitor has a third lower electrode, a dielectric layer on the third lower electrode, and a third upper electrode on the dielectric layer, the gate electrode, the second lower electrode, and the third upper electrode of the first vertical transistor being the same conductive layer, and the gate insulating layer and the dielectric layer of the first vertical transistor being the same insulating layer.

[0016] Alternatively, in the above aspect, the semiconductor device may have an interlayer insulating layer, the interlayer insulating layer having a region located between the first lower electrode and the first upper electrode, the first upper electrode and the interlayer insulating layer having a first opening reaching the first lower electrode, the interlayer insulating layer having a second opening, and the third lower electrode, the insulating layer, and the conductive layer each having a region located inside the first opening and a region located inside the second opening.

[0017] Alternatively, in the above aspect, a channel of the first vertical transistor may be formed along a sidewall of the first opening.

[0018] Alternatively, one embodiment of the present invention includes a first transistor, a second transistor, a capacitor, a first insulating layer, and a second insulating layer, in which the first transistor includes a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a third insulating layer, the second transistor includes a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a fourth insulating layer, and the capacitor includes a third conductive layer, a sixth conductive layer, and a third insulating layer. and an insulating layer, the first insulating layer being located on the first conductive layer, the second conductive layer being located on the first insulating layer, the first insulating layer and the second conductive layer having a first opening reaching the first conductive layer, the first insulating layer having a second opening, the first semiconductor layer having a region in contact with the first conductive layer and a region in contact with the second conductive layer and a region located inside the first opening, and the sixth conductive layer having a region located inside the second opening. the third insulating layer has a region located inside the first semiconductor layer within the first opening and a region located inside the sixth conductive layer within the second opening, the third conductive layer has a region facing the first semiconductor layer with the third insulating layer therebetween within the first opening and a region facing the sixth conductive layer with the third insulating layer therebetween within the second opening, the second insulating layer is located on the third conductive layer, the fourth conductive layer is located on the second insulating layer, the second insulating layer and the fourth conductive layer have a third opening reaching the third conductive layer, the second semiconductor layer has a region in contact with the third conductive layer and a region in contact with the fourth conductive layer and has a region located inside the third opening, the fourth insulating layer has a region located inside the second semiconductor layer within the third opening, and the fifth conductive layer has a region facing the second semiconductor layer with the fourth insulating layer sandwiched between them inside the third opening.

[0019] Alternatively, in the above aspect, the semiconductor device may have a fifth insulating layer, the fifth insulating layer having a region overlapping with the fourth conductive layer via the second semiconductor layer, and a fourth opening at a position overlapping with the third opening, and the fifth conductive layer may have a region located inside the fourth opening.

[0020] Alternatively, in the above aspect, the semiconductor device may have a seventh conductive layer. The seventh conductive layer may be located on the fifth insulating layer so as to have a region in contact with an upper surface of the fifth conductive layer.

[0021] Alternatively, in the above aspect, the fourth insulating layer may be at least partially located inside the fourth opening.

[0022] Alternatively, in the above aspect, the first conductive layer may have a first recess at a position overlapping with the first opening, the third conductive layer may have a second recess at a position overlapping with the third opening, the first semiconductor layer may have a region in contact with the bottom and side surfaces of the first recess, and the second semiconductor layer may have a region in contact with the bottom and side surfaces of the second recess.

[0023] Alternatively, in the above aspect, the semiconductor device may have a seventh conductive layer. The first insulating layer may be located on the seventh conductive layer, the first insulating layer may have a second opening reaching the seventh conductive layer, the seventh conductive layer may have a third recess at a position overlapping with the second opening, and the sixth conductive layer may have an area in contact with a bottom surface and side surfaces of the third recess.

[0024] Alternatively, in the above aspect, the first conductive layer may have a seventh conductive layer and an eighth conductive layer on the seventh conductive layer, the third conductive layer may have a ninth conductive layer and a tenth conductive layer on the ninth conductive layer, the eighth conductive layer may have a first recess, and the tenth conductive layer may have a second recess.

[0025] Alternatively, in the above aspect, the first conductive layer may have an eighth conductive layer and a ninth conductive layer on the eighth conductive layer, the third conductive layer may have a tenth conductive layer and an eleventh conductive layer on the tenth conductive layer, the seventh conductive layer may have a twelfth conductive layer and a thirteenth conductive layer on the twelfth conductive layer, the ninth conductive layer may have a first recess, the eleventh conductive layer may have a second recess, and the thirteenth conductive layer may have a third recess.

[0026] Alternatively, in the above aspect, the first transistor has a seventh conductive layer and a fifth insulating layer, the second transistor has an eighth conductive layer and a sixth insulating layer, the first insulating layer has a seventh insulating layer and an eighth insulating layer on the seventh insulating layer, the second insulating layer has a ninth insulating layer and a tenth insulating layer on the ninth insulating layer, the seventh conductive layer is located on the seventh insulating layer, the eighth conductive layer is located on the ninth insulating layer, and the eighth insulating layer is the seventh the seventh conductive layer has a first opening, the eighth conductive layer has a third opening, the fifth insulating layer is located inside the first opening, the sixth insulating layer is located inside the third opening, the seventh conductive layer and the first semiconductor layer have an opposing region with the fifth insulating layer in between, and the eighth conductive layer and the second semiconductor layer have an opposing region with the sixth insulating layer in between.

[0027] Alternatively, one embodiment of the present invention includes a first transistor, a second transistor, a capacitor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer, the first transistor includes a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fifth insulating layer, the second transistor includes a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a sixth insulating layer, the capacitor includes a seventh conductive layer, an eighth conductive layer, and a seventh insulating layer, the first insulating layer is located over the first conductive layer, and the second conductive layer is located over the first insulating layer. the seventh conductive layer has a region located inside the second opening and a region located on the first insulating layer, the first insulating layer and the second conductive layer having a first opening reaching the first conductive layer, the first insulating layer having a second opening, the first semiconductor layer having a region in contact with an upper surface of the second conductive layer and a region in contact with the first conductive layer inside the first opening, the seventh conductive layer has a region located inside the second opening and a region located on the first insulating layer, and the second insulating layer has a region overlapping with the second conductive layer via the first semiconductor layer and a region overlapping with the first insulating layer via the seventh conductive layer. the second insulating layer has a third opening overlapping with the first opening and a fourth opening overlapping with the second opening; the fifth insulating layer has a region located inside the first opening and on the inside of the first semiconductor layer; the third conductive layer has a region facing the first semiconductor layer with the fifth insulating layer sandwiched therebetween and a region located inside the third opening; the seventh insulating layer has a region located inside the seventh conductive layer within the second opening; the eighth conductive layer has a region facing the seventh conductive layer with the seventh insulating layer sandwiched therebetween and a region located inside the fourth opening. the fourth conductive layer has a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the eighth conductive layer; the third insulating layer is located on the fourth conductive layer, the fifth conductive layer is located on the third insulating layer, the third insulating layer and the fifth conductive layer have a fifth opening reaching the fourth conductive layer; the second semiconductor layer has a region located inside the fifth opening, the second semiconductor layer has a region in contact with an upper surface of the fifth conductive layer and a region in contact with the fourth conductive layer inside the fifth opening, and the fourth insulating layer has a region overlapping with the fifth conductive layer via the second semiconductor layer;The fourth insulating layer has a sixth opening overlapping with the fifth opening, the sixth insulating layer has a region inside the fifth opening and located on the inner side of the second semiconductor layer, and the sixth conductive layer has a region inside the fifth opening facing the second semiconductor layer with the sixth insulating layer therebetween and a region located inside the sixth opening.

[0028] Alternatively, in the above aspect, the semiconductor device may have a ninth conductive layer. The ninth conductive layer may be located on the fourth insulating layer so as to have a region in contact with an upper surface of the sixth conductive layer.

[0029] Alternatively, in the above aspect, the first conductive layer may have a first recess at a position overlapping with the first opening, the fourth conductive layer may have a second recess at a position overlapping with the fifth opening, the first semiconductor layer may have a region in contact with the bottom and side surfaces of the first recess, and the second semiconductor layer may have a region in contact with the bottom and side surfaces of the second recess.

[0030] Alternatively, in the above aspect, the semiconductor device may have a ninth conductive layer, the first insulating layer is located on the ninth conductive layer, the first insulating layer has a second opening reaching the ninth conductive layer, the ninth conductive layer has a third recess at a position overlapping with the second opening, and the seventh conductive layer may have an area in contact with a bottom surface and side surfaces of the third recess.

[0031] Alternatively, in the above aspect, the first conductive layer may have a ninth conductive layer and a tenth conductive layer on the ninth conductive layer, and the tenth conductive layer may have the first recess.

[0032] Alternatively, in the above aspect, the first conductive layer may have a tenth conductive layer and an eleventh conductive layer on the tenth conductive layer, the ninth conductive layer may have a twelfth conductive layer and a thirteenth conductive layer on the twelfth conductive layer, the eleventh conductive layer may have a first recess, and the thirteenth conductive layer may have a third recess.

[0033] Alternatively, in the above embodiment, the first transistor has a ninth conductive layer and an eighth insulating layer, the second transistor has a tenth conductive layer and a ninth insulating layer, the first insulating layer has a tenth insulating layer and an eleventh insulating layer on the tenth insulating layer, the third insulating layer has a twelfth insulating layer and a thirteenth insulating layer on the twelfth insulating layer, the ninth conductive layer is located on the tenth insulating layer, the tenth conductive layer is located on the twelfth insulating layer, and the eleventh insulating layer the thirteenth insulating layer covers an upper surface and a side surface of the tenth conductive layer, the ninth conductive layer has a first opening, the eighth conductive layer has a fifth opening, the eighth insulating layer is located inside the first opening, the ninth insulating layer is located inside the fifth opening, the ninth conductive layer and the first semiconductor layer have an opposing region with the eighth insulating layer in between, and the tenth conductive layer and the second semiconductor layer have an opposing region with the ninth insulating layer in between.

[0034] Alternatively, in the above embodiment, the first semiconductor layer and the second semiconductor layer each have a metal oxide, the metal oxide has two or three selected from indium, an element M, and zinc, and the element M may be one or more selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

[0035] Alternatively, one embodiment of the present invention includes forming a first conductive layer, forming a first insulating layer on the first conductive layer, forming a second conductive layer on the first insulating layer, forming a first opening that reaches the first conductive layer in the second conductive layer and the first insulating layer and forming a second opening in the first insulating layer, forming a first semiconductor layer so as to have a region in contact with the first conductive layer and a region in contact with the second conductive layer and a region located inside the first opening, and processing the first semiconductor layer and the second conductive layer. a third conductive layer is formed so as to expose a portion of an upper surface of the first insulating layer and to have a region located inside the second opening; a second insulating layer is formed so as to have a region located inside the first semiconductor layer inside the first opening and a region located inside the third conductive layer inside the second opening; and a fourth conductive layer is formed so as to have a region facing the first semiconductor layer with the second insulating layer sandwiched between them inside the first opening and a region facing the third conductive layer with the second insulating layer sandwiched between them inside the second opening. forming a third insulating layer on the fourth conductive layer, forming a fifth conductive layer on the third insulating layer, forming a third opening in the fifth conductive layer and the third insulating layer, the third opening reaching the fourth conductive layer, forming a second semiconductor layer having a region in contact with the fourth conductive layer and a region in contact with the fifth conductive layer and a region located inside the third opening, and processing the second semiconductor layer and the fifth conductive layer to expose a portion of an upper surface of the third insulating layer and to expose a portion of a region located inside the third opening. This is a method for manufacturing a semiconductor device, comprising the steps of forming a sacrificial layer, forming a fourth insulating layer to cover the fifth conductive layer, the second semiconductor layer, and the sacrificial layer, performing planarization treatment on the fourth insulating layer and the sacrificial layer to planarize an upper surface of the sacrificial layer, removing the sacrificial layer, forming a fifth insulating layer to cover the third opening, forming a sixth conductive layer on the fifth insulating layer, and performing planarization treatment on the sixth conductive layer to remove a region of the sixth conductive layer and the fifth insulating layer that overlaps with an upper surface of the fourth insulating layer.

[0036] Alternatively, in the above embodiment, a seventh conductive layer may be formed on the fourth insulating layer so as to have a region in contact with the upper surface of the sixth conductive layer.

[0037] Alternatively, in the above embodiment, a seventh conductive layer may be formed in parallel with the formation of the first conductive layer, the first insulating layer may be formed to be located on the seventh conductive layer, the second opening may be formed to reach the seventh conductive layer, and the third conductive layer may be formed to have an area in contact with the seventh conductive layer. Effect of the Invention

[0038] According to one embodiment of the present invention, a low-cost semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a manufacturing method of the above semiconductor device can be provided.

[0039] Alternatively, according to one embodiment of the present invention, a method for manufacturing a semiconductor device with a small number of steps can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a semiconductor device with a high yield can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a semiconductor device that enables miniaturization or high integration can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high operating speed can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a semiconductor device including a transistor with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a semiconductor device including a transistor with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0040] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief description of the drawings]

[0041] [Figure 1] Fig. 1(A) is a circuit diagram showing an example of a memory cell, Fig. 1(B) and Fig. 1(C) are plan views showing an example of a semiconductor device, and Fig. 1(D) is a cross-sectional view showing an example of the semiconductor device. [Diagram 2] 2A and 2B are cross-sectional views showing an example of a semiconductor device. [Diagram 3] Fig. 3(A) is a cross-sectional view showing an example of a semiconductor device, and Fig. 3(B) is a plan view showing an example of the semiconductor device. [Figure 4] 4(A) and 4(B) are cross-sectional views showing an example of a semiconductor device. [Diagram 5] Fig. 5(A) is a plan view showing an example of a semiconductor device, and Fig. 5(B) is a cross-sectional view showing an example of the semiconductor device. [Figure 6] 6(A) and 6(B) are cross-sectional views showing an example of a semiconductor device. [Figure 7] Fig. 7(A) is a plan view showing an example of a semiconductor device, and Fig. 7(B) and Fig. 7(C) are cross-sectional views showing an example of the semiconductor device. [Figure 8] 8(A) and 8(B) are cross-sectional views showing an example of a semiconductor device. [Figure 9] 9A to 9C are cross-sectional views showing an example of a semiconductor device. [Figure 10] 10A to 10C are cross-sectional views showing an example of a semiconductor device. [Figure 11] 11A and 11B are plan views showing an example of a semiconductor device, and Fig. 11C is a cross-sectional view showing an example of the semiconductor device. [Figure 12]12A and 12B are cross-sectional views showing an example of a semiconductor device. [Figure 13] 13A and 13B are cross-sectional views showing an example of a semiconductor device. [Figure 14] 14(A) and 14(B) are cross-sectional views showing an example of a semiconductor device. [Figure 15] FIG. 15 is a cross-sectional view showing an example of a semiconductor device. [Figure 16] FIG. 16 is a cross-sectional view showing an example of a semiconductor device. [Figure 17] FIG. 17 is a cross-sectional view showing an example of a semiconductor device. [Figure 18] FIG. 18 is a cross-sectional view showing an example of a semiconductor device. [Figure 19] FIG. 19 is a cross-sectional view showing an example of a semiconductor device. [Figure 20] 20A to 20F are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 21] 21A to 21D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 22] 22A and 22B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 23] 23A to 23D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 24] Fig. 24(A) is a plan view showing an example of a storage device, and Fig. 24(B) is a cross-sectional view showing an example of the storage device. [Diagram 25] FIG. 25 is a cross-sectional view showing an example of a storage device. [Figure 26] FIG. 26 is a cross-sectional view showing an example of a storage device. [Figure 27] FIG. 27 is a cross-sectional view showing an example of a storage device. [Figure 28] FIG. 28 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 29] 29(A) and 29(B) are perspective views showing an example of a semiconductor device. [Diagram 30] FIG. 30 is a block diagram illustrating the CPU. [Diagram 31] 31(A) and 31(B) are perspective views showing an example of a semiconductor device. [Diagram 32] 32(A) and 32(B) are perspective views showing an example of a semiconductor device. [Diagram 33] 33(A) and 33(B) are diagrams showing various storage devices by hierarchical level. [Diagram 34] 34(A) and 34(B) are diagrams showing an example of an electronic component. [Diagram 35] Fig. 35(A) to Fig. 35(C) are diagrams showing an example of a mainframe computer. Fig. 35(D) is a diagram showing an example of space equipment. Fig. 35(E) is a diagram showing an example of a storage system applicable to a data center. [Diagram 36] 36A to 36D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. [Figure 37] 37A to 37D are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0043] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

[0044] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0045] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). In addition, an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.

[0046] A transistor is a type of semiconductor element and can realize a function of amplifying a current or a voltage, a switching operation of controlling conduction or non-conduction, etc. In this specification, the term "transistor" includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).

[0047] In this specification and the like, a transistor using a metal oxide for a semiconductor layer and a transistor having a metal oxide for a channel formation region may be referred to as an OS transistor, and a transistor having silicon for a channel formation region may be referred to as a Si transistor.

[0048] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region (also called a channel formation region) in which a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) is provided, and a current can flow between the source and the drain through the channel formation region. In this specification and the like, the channel formation region refers to a region through which a current mainly flows.

[0049] In addition, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, or when the direction of current changes during circuit operation, etc. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0050] Note that impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. The inclusion of impurities can, for example, increase the defect level density of the semiconductor or reduce the crystallinity. When the semiconductor is a metal oxide, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the metal oxide. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiency (V O In some cases, a junction (also referred to as a junction) may be formed.

[0051] In this specification and the like, an oxynitride refers to a material having a composition containing more oxygen than nitrogen, and a nitride oxide refers to a material having a composition containing more nitrogen than oxygen.

[0052] For example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used to analyze the content of elements such as hydrogen, oxygen, carbon, or nitrogen contained in the film. When the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more), XPS is suitable. On the other hand, when the content of the target element is low (e.g., 0.5 atomic% or less, or 1 atomic% or less), SIMS is suitable. When comparing the content of elements, it is more preferable to perform a combined analysis using both SIMS and XPS analysis methods.

[0053] In addition, the words "film" and "layer" can be interchanged depending on the case or situation. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer".

[0054] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0055] In this specification, "electrically connected" includes a case where a connection is made via "something having some electrical action." Here, "something having some electrical action" is not particularly limited as long as it enables transmission and reception of an electrical signal between the objects to be connected. For example, "something having some electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements having various functions.

[0056] In this specification, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also called the non-conducting state or cut-off state). Unless otherwise specified, the off-state refers to the voltage V between the gate and the source in an n-channel transistor. gs is the threshold voltage V th (For p-channel transistors, V th The term "higher" refers to a state of being.

[0057] In this specification, the normally-on characteristic refers to a state in which a channel exists and a current flows through a transistor even when no voltage is applied to the gate, whereas the normally-off characteristic refers to a state in which no current flows through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate.

[0058] In this specification, the term "tapered shape" refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side and the substrate surface or the surface to be formed is greater than 0 degrees and less than 90 degrees. The side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0059] In this specification, when it is stated that A is located on B, at least a part of A is located on B. Therefore, for example, it can be rephrased as A has an area located on B. Similarly, when it is stated that A contacts B or A overlaps B, at least a part of A contacts B or overlaps B. Therefore, it can be rephrased as A has an area contacting B or A has an area overlapping B, respectively. Similarly, in this specification, when it is stated that A covers B, at least a part of A covers B. Therefore, for example, it can be rephrased as A has an area covering B.

[0060] In addition, for example, in the drawings related to this specification, arrows indicating the X direction, Y direction, and Z direction may be added. In addition, in this specification, the "X direction" is the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y direction" and the "Z direction." In addition, the X direction, Y direction, and Z direction are directions that intersect with each other. For example, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.

[0061] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention and a manufacturing method thereof will be described with reference to drawings.

[0062] A semiconductor device according to one embodiment of the present invention is a memory device provided with a memory cell having a first transistor, a second transistor, and a capacitor. In the semiconductor device according to one embodiment of the present invention, the second transistor is located above the first transistor and the capacitor. The capacitor includes one of a pair of electrodes, a dielectric layer, and the other of the pair of electrodes, in this order. The semiconductor device according to one embodiment of the present invention includes a first insulating layer and a second insulating layer in addition to the first transistor, the second transistor, and the capacitor. The second insulating layer is located over the first insulating layer, the first transistor, and the capacitor.

[0063] The first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a third insulating layer. The second transistor has a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a fourth insulating layer. The capacitor has a third conductive layer, a sixth conductive layer, and a third insulating layer.

[0064] The first conductive layer functions as one of the source electrode and drain electrode of the first transistor. The second conductive layer functions as the other of the source electrode and drain electrode of the first transistor. The third conductive layer functions as the gate electrode of the first transistor, one of the source electrode and drain electrode of the second transistor, and the other of the pair of electrodes of the capacitor. The fourth conductive layer functions as the other of the source electrode and drain electrode of the second transistor. The fifth conductive layer functions as the gate electrode of the second transistor. The sixth conductive layer functions as one of the pair of electrodes of the capacitor.

[0065] The first and second insulating layers function as interlayer insulating layers, the third insulating layer functions as a gate insulating layer of the first transistor and a dielectric layer of the capacitor, and the fourth insulating layer functions as a gate insulating layer of the second transistor.

[0066] A first insulating layer is located on the first conductive layer, and a second conductive layer is located on the first insulating layer. The first conductive layer can be referred to as a lower electrode of the first transistor, and the second conductive layer can be referred to as an upper electrode of the first transistor. A first opening is provided in the first insulating layer and the second conductive layer, the first opening reaching the first conductive layer. Also, a second opening is provided in the first insulating layer. The first opening and the second opening can be formed in parallel.

[0067] The first semiconductor layer has a region in contact with the first conductive layer and a region in contact with the second conductive layer, and has a region located inside the first opening. The first semiconductor layer can be provided along a sidewall of the first opening. Thus, a channel of the first transistor can be formed along the sidewall of the first opening. The sixth conductive layer has a region located inside the second opening. The sixth conductive layer can be provided along the sidewall of the second opening.

[0068] The third insulating layer has a region located inside the first semiconductor layer within the first opening and a region located inside the sixth conductive layer within the second opening. The third conductive layer has a region facing the first semiconductor layer with the third insulating layer therebetween within the first opening and a region facing the sixth conductive layer with the third insulating layer therebetween within the second opening.

[0069] The third insulating layer is located on the sixth conductive layer, and the third conductive layer is located on the third insulating layer. The sixth conductive layer can be referred to as a lower electrode of the capacitance, and the third conductive layer can be referred to as an upper electrode of the capacitance.

[0070] The second insulating layer is located on the third conductive layer, and the fourth conductive layer is located on the second insulating layer. The third conductive layer can be referred to as a lower electrode of the second transistor, and the fourth conductive layer can be referred to as an upper electrode of the second transistor. The second insulating layer and the fourth conductive layer are provided with a third opening reaching the third conductive layer.

[0071] The second semiconductor layer has a region in contact with the third conductive layer and a region in contact with the fourth conductive layer, and has a region located inside the third opening. The second semiconductor layer can be provided along the sidewall of the third opening. Thus, the channel of the second transistor can be formed along the sidewall of the third opening.

[0072] The fourth insulating layer has a region located inside the third opening and on the inner side of the second semiconductor layer, and the fifth conductive layer has a region facing the second semiconductor layer with the fourth insulating layer interposed therebetween.

[0073] As described above, in the semiconductor device according to one embodiment of the present invention, the gate electrode of the first transistor, one of the source electrode and drain electrode of the second transistor, and the other of the pair of electrodes of the capacitor can be shared as the third conductive layer. In addition, in the semiconductor device according to one embodiment of the present invention, the gate insulating layer of the first transistor and the dielectric layer of the capacitor can be shared as the third insulating layer. Furthermore, as described above, the first opening in which at least a part of the first transistor is provided and the second opening in which at least a part of the capacitor is provided can be formed in parallel. As a result, the number of manufacturing steps of the semiconductor device can be reduced compared to a case in which the layers of the first transistor, the second transistor, and the capacitor are not shared. Therefore, the manufacturing cost of the semiconductor device can be reduced, and a low-cost semiconductor device can be provided.

[0074] In the semiconductor device according to one embodiment of the present invention, the second transistor is provided to overlap with at least a part of the first transistor, the capacitor, and a region between the first transistor and the capacitor. This makes it possible to reduce the area occupied by each memory cell compared to the case where the first transistor, the second transistor, and the capacitor are provided in the same layer. Thus, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0075] Note that in the semiconductor device of one embodiment of the present invention, a groove (slit) may be provided instead of the opening.

[0076] In a transistor included in a semiconductor device of one embodiment of the present invention (also referred to as a transistor of one embodiment of the present invention), a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Thus, the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0077] In the transistor of one embodiment of the present invention, a source electrode, a semiconductor layer, and a drain electrode can be provided in a stacked manner, and therefore the occupation area can be significantly reduced as compared with a so-called planar transistor in which a semiconductor layer is arranged in a planar shape.

[0078] Furthermore, the capacitance of the semiconductor device of one embodiment of the present invention is such that a metal insulator metal (MIM) structure is formed on the sidewall and bottom of an opening provided in an interlayer insulating layer. Thus, the capacitance of the semiconductor device of one embodiment of the present invention is a trench-type capacitance. Therefore, the capacitance of the semiconductor device of one embodiment of the present invention can be increased without increasing the occupied area, as compared with, for example, a planar-type capacitance. Thus, in the semiconductor device of one embodiment of the present invention, the capacitance value can be ensured even if the occupied area of ​​the capacitance is reduced. Therefore, a semiconductor device that can be miniaturized or highly integrated by reducing the occupied area of ​​a memory cell can be provided.

[0079] Here, in order to form a trench-type capacitor, an opening needs to be formed in an interlayer insulating layer. In the semiconductor device of one embodiment of the present invention, the opening can be formed in parallel with an opening in which a semiconductor layer of a transistor is provided. Therefore, even if the capacitance of the semiconductor device of one embodiment of the present invention is a trench-type capacitor, an increase in the number of manufacturing steps of the semiconductor device of one embodiment of the present invention can be suppressed as compared with, for example, a planar-type capacitor. Note that the capacitance of the semiconductor device of one embodiment of the present invention may be a capacitor other than a trench-type capacitor, for example, a planar-type capacitor.

[0080] <Configuration Example 1 of Semiconductor Device> 1A is a circuit diagram illustrating a configuration example of a memory cell 10 included in a semiconductor device of one embodiment of the present invention. The memory cell 10 includes a transistor 11, a transistor 13, and a capacitor 15.

[0081] One of the source and the drain of the transistor 11 is electrically connected to the gate of the transistor 13. The other of the source and the drain of the transistor 11 is electrically connected to a wiring 23. The gate of the transistor 11 is electrically connected to a wiring 21.

[0082] One of the source and the drain of the transistor 13 is electrically connected to a wiring 25. The other of the source and the drain of the transistor 13 is electrically connected to a wiring 27.

[0083] One of a pair of electrodes of the capacitor 15 is electrically connected to the wiring 29. The other of the pair of electrodes of the capacitor 15 is electrically connected to the gate of the transistor 13. Here, a node to which one of the source or drain of the transistor 11, the gate of the transistor 13, and the other of the pair of electrodes of the capacitor 15 are electrically connected is referred to as a node ND.

[0084] The wiring 21 functions as a word line. A signal for controlling the on / off state of the transistor 11 is supplied to the wiring 21.

[0085] The wiring 23 functions as a bit line. A data signal to be supplied to the memory cell 10 is supplied to the wiring 23. When the transistor 11 is on, data corresponding to the potential of the wiring 23 is written to the memory cell 10. When the transistor 11 is off, the data written to the memory cell 10 is held. Specifically, the potential of the node ND is held.

[0086] The wiring 25 functions as a bit line. The wiring 27 and the wiring 29 function as power supply lines and are supplied with a power supply potential. As described above, when data is written to the memory cell 10, the potential of the node ND becomes a potential corresponding to the data. A current having a magnitude corresponding to the potential of the node ND flows between the wiring 27 and the wiring 25. As a result, the potential of the wiring 25 becomes a potential corresponding to the data held in the memory cell 10. In this manner, the data held in the memory cell 10 can be read. The reading can be non-destructive.

[0087] As a result, data is written to the memory cell 10 via the wiring 23, and the data stored in the memory cell 10 is read via the wiring 25. Therefore, the wiring 23 can be called a write bit line, and the wiring 25 can be called a read bit line.

[0088] Fig. 1(B) is a plan view showing an example of the configuration of a transistor 13 and a capacitor 15. Fig. 1(C) is a plan view showing an example of the configuration of a transistor 11. It can also be said that the plan views shown in Fig. 1(B) and Fig. 1(C) show the configuration of the XY plane. Note that in the plan views of Fig. 1(B) and Fig. 1(C), some elements are omitted for clarity of the drawings. The same applies to the subsequent plan views.

[0089] FIG. 1(D) is a cross-sectional view taken along dashed lines A1-A2 in FIG. 1(B) and FIG. 1(C), and shows an example of the configuration of the transistor 11, the transistor 13, and the capacitor 15. FIG. 2(A) is a cross-sectional view taken along dashed lines B1-B2 in FIG. 1(B) and FIG. 1(C), and shows an example of the configuration of the transistor 11 and the capacitor 15. FIG. 2(B) is a cross-sectional view taken along dashed lines B3-B4 in FIG. 1(B) and FIG. 1(C), and shows an example of the configuration of the transistor 13. FIG. 1(D) can also be said to show the configuration of an XZ plane including the transistor 11, the transistor 13, and the capacitor 15. FIG. 2(A) can also be said to show the configuration of a YZ plane including the transistor 11 and the capacitor 15. FIG. 2(B) can also be said to show the configuration of a YZ plane including the transistor 13.

[0090] Fig. 3(A) is a cross-sectional view taken along dashed line A1-A2 in Fig. 1(B) and Fig. 1(C), and is an enlarged view of Fig. 1(D). Fig. 3(B) is a cross-sectional view taken along dashed line A3-A4 in Fig. 3(A).

[0091] 1B to 3B include an insulating layer 110 over a substrate (not shown), a transistor 13 and a conductive layer 121 over the insulating layer 110, a capacitor 15 over the conductive layer 121, an insulating layer 180 over the insulating layer 110 and the conductive layer 121, a transistor 11 and an insulating layer 280 located above the transistor 13, the capacitor 15, and the insulating layer 180, an insulating layer 283 over the insulating layer 280, an insulating layer 285 over the insulating layer 283, and a conductive layer 265 over the transistor 11, the insulating layer 283, and the insulating layer 285. Note that in FIG. 1D, FIG. 2A, and FIG. 3A, an example is shown in which the transistor 11 overlaps with the capacitor 15.

[0092] The insulating layer 110, the insulating layer 180, the insulating layer 280, the insulating layer 283, and the insulating layer 285 function as interlayer insulating layers. The conductive layer 121 includes a conductive layer 121a and a conductive layer 121b over the conductive layer 121a.

[0093] The transistor 13 has a conductive layer 120, a conductive layer 140 on an insulating layer 180, a semiconductor layer 130 having a region overlapping with the conductive layer 120, an insulating layer 150 on the semiconductor layer 130, and a conductive layer 220 on the insulating layer 150. Here, the insulating layer 180 has a region located on the conductive layer 120. As described above, the conductive layer 140 is located on the conductive layer 120 with the insulating layer 180 sandwiched therebetween. Therefore, the conductive layer 120 can be said to be a lower electrode of the transistor 13, and the conductive layer 140 can be said to be an upper electrode of the transistor 13.

[0094] The conductive layer 120 includes a conductive layer 120a and a conductive layer 120b on the conductive layer 120a. The conductive layer 140 includes a conductive layer 140a and a conductive layer 140b on the conductive layer 140a. The conductive layer 220 includes a conductive layer 220a and a conductive layer 220b on the conductive layer 220a.

[0095] Capacitor 15 has conductive layer 141 having an area overlapping with conductive layer 121, insulating layer 150 on conductive layer 141, and conductive layer 220 on insulating layer 150. Conductive layer 141 can be said to be the lower electrode of capacitor 15, and conductive layer 220 can be said to be the upper electrode of capacitor 15.

[0096] The transistor 11 includes a conductive layer 220, a conductive layer 240 on an insulating layer 280, a semiconductor layer 230 having a region overlapping with the conductive layer 220, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250. Here, the insulating layer 280 is provided on the insulating layer 150 so as to have a region located on the conductive layer 220. As described above, the conductive layer 240 is located on the conductive layer 220 with the insulating layer 280 sandwiched therebetween. Therefore, the conductive layer 220 can be said to be a lower electrode of the transistor 11, and the conductive layer 240 can be said to be an upper electrode of the transistor 11.

[0097] The conductive layer 240 includes a conductive layer 240a and a conductive layer 240b over the conductive layer 240a. Note that the conductive layer 120, the conductive layer 121, the conductive layer 140, the conductive layer 220, and the conductive layer 240 may each have a single-layer structure or a stacked structure of three or more layers.

[0098] The conductive layer 120 functions as one of a source electrode and a drain electrode of the transistor 13. The conductive layer 140 functions as the other of the source electrode and the drain electrode of the transistor 13. The conductive layer 141 functions as one of a pair of electrodes of the capacitor 15. The conductive layer 121 functions as a capacitor wiring electrically connected to one of the pair of electrodes of the capacitor 15.

[0099] The conductive layer 220 functions as a gate electrode of the transistor 13, one of the source electrode and drain electrode of the transistor 11, and the other of the pair of electrodes of the capacitor 15. The conductive layer 220 functions as a gate electrode of the transistor 13, a lower electrode of the transistor 11, and an upper electrode of the capacitor 15.

[0100] The conductive layer 240 functions as the other of the source electrode and drain electrode of the transistor 11. The conductive layer 260 functions as the gate electrode of the transistor 11. The insulating layer 150 functions as a gate insulating layer of the transistor 13 and a dielectric layer of the capacitor 15. The insulating layer 250 functions as a gate insulating layer of the transistor 11. The conductive layer 265 functions as a gate wiring electrically connected to the conductive layer 260.

[0101] As described above, the insulating layer 180 is located over the conductive layer 120, and the conductive layer 140 is located over the insulating layer 180. In addition, the conductive layer 120 serves as one of the source and drain electrodes of the transistor 13, and the conductive layer 140 serves as the other of the source and drain electrodes of the transistor 13.

[0102] At least a part of the conductive layer 120 can function as one of the wiring 25 and the wiring 27 shown in FIG. 1(A). At least a part of the conductive layer 140 can function as the other of the wiring 25 and the wiring 27 shown in FIG. 1(A). At least a part of the conductive layer 121 can function as the wiring 29 shown in FIG. 1(A). At least a part of the conductive layer 240 can function as the wiring 23 shown in FIG. 1(A). At least a part of the conductive layer 265 can function as the wiring 21 shown in FIG. 1(A).

[0103] Note that the conductive layer 120 may be electrically connected to another conductive layer that functions as one of the wiring 25 and the wiring 27. The conductive layer 140 may be electrically connected to another conductive layer that functions as the other of the wiring 25 and the wiring 27. The conductive layer 240 may be electrically connected to another conductive layer that functions as the wiring 23. At least a part of the conductive layer 141 may function as the wiring 29, and at least a part of the conductive layer 260 may function as the wiring 21.

[0104] As shown in FIG. 1(D) and FIG. 2(B), an opening 190 reaching the conductive layer 120 is provided in the conductive layer 140 and the insulating layer 180. Here, a recess 191 is provided in the conductive layer 120 at a position overlapping with the opening 190. Specifically, the recess 191 is provided in the conductive layer 120b. The bottom surface of the recess 191 corresponds to the upper surface of the conductive layer 120, specifically the upper surface of the conductive layer 120b. The side surface of the recess 191 corresponds to the side surface of the conductive layer 120, specifically the side surface of the conductive layer 120b.

[0105] Opening 190 includes an opening in insulating layer 180 and an opening in conductive layer 140. In other words, an opening in a region where insulating layer 180 overlaps with conductive layer 120 is a part of opening 190, and an opening in a region where conductive layer 140 overlaps with conductive layer 120 is another part of opening 190. Note that opening 190 may or may not include recess 191.

[0106] As shown in FIG. 1(D) and FIG. 2(A), an opening 192 is provided in the insulating layer 180, reaching the conductive layer 121b. Here, a recess 193 is provided in the conductive layer 121 at a position overlapping with the opening 192. Specifically, the recess 193 is provided in the conductive layer 121b. A bottom surface of the recess 193 corresponds to an upper surface of the conductive layer 121, specifically, an upper surface of the conductive layer 121b. A side surface of the recess 193 corresponds to a side surface of the conductive layer 121, specifically, a side surface of the conductive layer 121b. Note that the opening 192 can be formed in parallel with the opening 190, as will be described in detail later.

[0107] An opening 290 reaching the conductive layer 220 is provided in the conductive layer 240 and the insulating layer 280. FIG. 1(D) and FIG. 2(A) show an example in which the opening 290 overlaps with the opening 192. Here, a recess 291 is provided in the conductive layer 220 at a position overlapping with the opening 290. Specifically, the recess 291 is provided in the conductive layer 220b. The bottom surface of the recess 291 corresponds to the upper surface of the conductive layer 220, specifically the upper surface of the conductive layer 220b. The side surface of the recess 291 corresponds to the side surface of the conductive layer 220, specifically the side surface of the conductive layer 220b.

[0108] The opening 290 includes an opening in the insulating layer 280 and an opening in the conductive layer 240. In other words, the opening in the region where the insulating layer 280 overlaps with the conductive layer 220 is a part of the opening 290, and the opening in the region where the conductive layer 240 overlaps with the conductive layer 220 is another part of the opening 290. Note that the recess 291 may or may not be included in the opening 290.

[0109] The shapes and sizes of the openings 190, 192, and 290 in a plan view may differ depending on the layers. When the top surface shape of the entire opening 190 is circular, the openings in each layer may or may not be concentric. Similarly, when the top surface shape of the entire opening 290 is circular, the openings in each layer may or may not be concentric.

[0110] At least a portion of the components of the transistor 13 is disposed inside the opening 190. Specifically, each of the semiconductor layer 130, the insulating layer 150, and the conductive layer 220 is disposed so that at least a portion of the components is located inside the opening 190. Also, at least a portion of the components of the capacitor 15 is disposed inside the opening 192. Specifically, each of the conductive layer 141, the insulating layer 150, and the conductive layer 220 is disposed so that at least a portion of the components is located inside the opening 192.

[0111] The semiconductor layer 130 is in contact with an upper surface of the conductive layer 140. The semiconductor layer 130 is also in contact with a bottom surface and side surfaces of the recess 191. Furthermore, the semiconductor layer 130 is in contact with a side surface of the conductive layer 140 and a side surface of the insulating layer 180 inside the opening 190. The semiconductor layer 130 can be provided along a side wall of the opening 190.

[0112] The conductive layer 141 contacts the bottom surface and side surfaces of the recess 193. The conductive layer 141 contacts the side surfaces of the insulating layer 180 inside the opening 192. The conductive layer 141 can be provided along the side walls of the opening 192.

[0113] The insulating layer 150 has a region located on the conductive layer 140, a region located inside the semiconductor layer 130 in the opening 190, and a region located inside the conductive layer 141 in the opening 192. The insulating layer 150 can be provided so as to cover the semiconductor layer 130, the conductive layer 140, and the conductive layer 141. The conductive layer 220 has a region facing the semiconductor layer 130 with the insulating layer 150 interposed therebetween in the opening 190, and a region facing the conductive layer 141 with the insulating layer 150 interposed therebetween in the opening 192. The conductive layer 220 also has a region overlapping with the conductive layer 140 via the insulating layer 150 and the semiconductor layer 130.

[0114] Moreover, the regions of the semiconductor layer 130 and the insulating layer 150 arranged inside the opening 190 are provided so as to reflect the shapes of the recess 191 and the opening 190. Similarly, the regions of the conductive layer 141 and the insulating layer 150 arranged inside the opening 192 are provided so as to reflect the shapes of the recess 193 and the opening 192. Specifically, the semiconductor layer 130 is provided so as to cover the bottom and side surfaces of the recess 191 and the sidewalls of the opening 190, and the insulating layer 150 is provided so as to cover the semiconductor layer 130. Moreover, the conductive layer 141 is provided so as to cover the bottom and side surfaces of the recess 193 and the sidewalls of the opening 192, and the insulating layer 150 is provided so as to cover the conductive layer 141. Then, the conductive layer 220 is provided so as to fill at least a part of the recess of the insulating layer 150.

[0115] At least a part of the region of the semiconductor layer 130 in contact with the insulating layer 180 functions as a channel formation region of the transistor 13. As described above, the semiconductor layer 130 can be provided along the side wall of the opening 190 provided in the insulating layer 180. From the above, the channel of the transistor 13 can be formed along the side wall of the opening 190. Therefore, it can be said that the channel length direction of the transistor 13 has a component in the height direction (vertical direction). Therefore, the transistor 13 can also be called a VFET, a vertical transistor, a vertical channel transistor, a vertical channel type transistor, or the like.

[0116] One of the region of the semiconductor layer 130 in contact with the conductive layer 120 and the region of the semiconductor layer 130 in contact with the conductive layer 140 functions as a source region, and the other functions as a drain region. As described above, the insulating layer 180 having the opening 190 is provided over the conductive layer 120. In addition, the conductive layer 140 is provided over the insulating layer 180. As described above, the channel formation region of the transistor 13 is sandwiched between the source region and the drain region.

[0117] At least some of the components of the transistor 11 are disposed inside the opening 290. Specifically, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are each disposed such that at least a portion of each of them is located inside the opening 290.

[0118] The semiconductor layer 230 is in contact with an upper surface of the conductive layer 240. The semiconductor layer 230 is also in contact with a bottom surface and side surfaces of the recess 291. Furthermore, the semiconductor layer 230 is in contact with a side surface of the conductive layer 240 and a side surface of the insulating layer 280 inside the opening 290. The semiconductor layer 230 can be provided along a side wall of the opening 290.

[0119] The insulating layer 250 has a region located inside the opening 290 and on the inner side of the semiconductor layer 230. The conductive layer 260 has a region inside the opening 290 facing the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween.

[0120] Moreover, the regions of the semiconductor layer 230 and the insulating layer 250 that are disposed inside the opening 290 are provided to reflect the shapes of the recess 291 and the opening 290. Specifically, the semiconductor layer 230 is provided so as to cover the bottom and side surfaces of the recess 291 and the sidewall of the opening 290, and the insulating layer 250 is provided so as to cover the semiconductor layer 230. Then, the conductive layer 260 is provided so as to fill at least a portion of the recess of the insulating layer 250.

[0121] At least a part of the region of the semiconductor layer 230 in contact with the insulating layer 280 functions as a channel formation region of the transistor 11. As described above, the semiconductor layer 230 can be provided along the side wall of the opening 290 provided in the insulating layer 280. From the above, the channel of the transistor 11 can be formed along the side wall of the opening 290. Therefore, it can be said that the channel length direction of the transistor 11 has a component in the height direction (vertical direction). Therefore, like the transistor 13, the transistor 11 can also be called a VFET, a vertical transistor, a vertical channel transistor, a vertical channel type transistor, or the like.

[0122] One of the region of the semiconductor layer 230 in contact with the conductive layer 220 and the region of the semiconductor layer 230 in contact with the conductive layer 240 functions as a source region, and the other functions as a drain region. As described above, the insulating layer 280 having the opening 290 is provided on the conductive layer 220. In addition, the conductive layer 240 is provided on the insulating layer 280. As a result, the channel of the transistor 11 is sandwiched between the source region and the drain region.

[0123] As described above, in the semiconductor device of one embodiment of the present invention, the gate electrode of the transistor 13, one of the source electrode and the drain electrode of the transistor 11, and the other of the pair of electrodes of the capacitor 15 can be shared as the conductive layer 220. In addition, in the semiconductor device of one embodiment of the present invention, the gate insulating layer of the transistor 13 and the dielectric layer of the capacitor 15 can be shared as the insulating layer 150. Furthermore, as described above, the opening 190 in which at least a part of the semiconductor layer 130, the insulating layer 150, and the conductive layer 220 of the transistor 13 is provided and the opening 192 in which at least a part of the conductive layer 141, the insulating layer 150, and the conductive layer 220 of the capacitor 15 is provided can be formed in parallel. As a result, the number of manufacturing steps of the semiconductor device can be reduced compared to, for example, a case in which the layers of the transistor 11, the transistor 13, and the capacitor 15 are not shared. Therefore, the manufacturing cost of the semiconductor device can be reduced, and a low-cost semiconductor device can be provided.

[0124] By having the recess 191 in the conductive layer 120, the height of the lower surface of the insulating layer 150 and the height of the lower surface of the conductive layer 220 inside the opening 190 can be lower than the height of at least a part of the upper surface of the conductive layer 120 that contacts the insulating layer 180, as compared to a case where the recess 191 is not present. Furthermore, by having the recess 291 in the conductive layer 220, the height of the lower surface of the insulating layer 250 and the height of the lower surface of the conductive layer 260 inside the opening 290 can be lower than the height of at least a part of the upper surface of the conductive layer 220 that contacts the insulating layer 280, as compared to a case where the recess 291 is not present. Here, the height of each surface can be determined based on the surface on which the transistor is to be formed. Here, the upper surface of the insulating layer 110 can be used as the reference. The surface used as the reference is not limited to the surface on which the transistor is to be formed. For example, the upper surface of a substrate on which a transistor or a semiconductor device is provided may be used as the reference.

[0125] 3A, the shortest distance Tc1 from the upper surface of the insulating layer 110 to the upper surface of the conductive layer 120 that contacts the insulating layer 180 is preferably longer than the shortest distance Ta1 from the upper surface of the insulating layer 110 to the lower surface of the insulating layer 150 in the region overlapping the recess 191. This makes it possible to increase the contact area between the side surface of the conductive layer 120 and the semiconductor layer 130, and to reduce the contact resistance between the conductive layer 120 and the semiconductor layer 130. Therefore, it is possible to suppress a decrease in the on-current of the transistor 13 caused by the contact resistance between the conductive layer 120 and the semiconductor layer 130. The shortest distance Ta1 can be determined based on the lower surface of the insulating layer 150 inside the opening 190.

[0126] Similarly, the shortest distance from the upper surface of insulating layer 110 to the upper surface of conductive layer 121 that contacts insulating layer 180 is preferably longer than the shortest distance from the upper surface of insulating layer 110 to the lower surface of insulating layer 150 in the region overlapping recess 193. This makes it possible to increase the contact area between the side surface of conductive layer 121 and conductive layer 141, thereby reducing the contact resistance between conductive layer 121 and conductive layer 141. Note that the shortest distance from the upper surface of insulating layer 110 to the lower surface of insulating layer 150 in the region overlapping recess 193 can be determined based on the lower surface of insulating layer 150 inside opening 192.

[0127] 3A, the shortest distance Tc2 from the upper surface of the insulating layer 110 to the upper surface of the conductive layer 220 that contacts the insulating layer 280 and overlaps with the conductive layer 140 is preferably longer than the shortest distance Ta2 from the upper surface of the insulating layer 110 to the lower surface of the insulating layer 280 in the region that overlaps with the recess 291. This makes it possible to increase the contact area between the side surface of the conductive layer 220 and the semiconductor layer 230, and to reduce the contact resistance between the conductive layer 220 and the semiconductor layer 230. Therefore, it is possible to suppress a decrease in the on-current of the transistor 11 caused by the contact resistance between the conductive layer 220 and the semiconductor layer 230. The shortest distance Ta2 can be determined based on the lower surface of the insulating layer 250 inside the opening 190.

[0128] As shown in FIG. 3A, the shortest distance Tc1 is preferably equal to or greater than the shortest distance Tb1 from the upper surface of the insulating layer 110 to the lower surface of the conductive layer 220 in the region overlapping the recess 191, and more preferably longer than the shortest distance Tb1. This makes it easier to apply a gate electric field to the channel formation region of the semiconductor layer 130, and improves the electrical characteristics of the transistor 13. Furthermore, the gate electric field is also easier to apply to the region of the semiconductor layer 130 in contact with the conductive layer 120, and therefore the on-current of the transistor 13 can be increased. Furthermore, whether the conductive layer 120 or the conductive layer 140 is used as the drain electrode, the electrical characteristics of the transistor 13 can be improved. The shortest distance Tb1 can be determined based on the lower surface of the conductive layer 220 inside the opening 190.

[0129] Furthermore, as shown in FIG. 3A, the shortest distance Tc2 is more preferably equal to or greater than the shortest distance Tb2 from the upper surface of the insulating layer 110 to the lower surface of the conductive layer 260 in the region overlapping the recess 291, and is even more preferably longer than the shortest distance Tb2. This makes it easier for a gate electric field to be applied to the channel formation region of the semiconductor layer 230, and the electrical characteristics of the transistor 11 can be improved. Furthermore, since a gate electric field is also easier to be applied to the region of the semiconductor layer 230 in contact with the conductive layer 220, the on-current of the transistor 11 can be increased. Moreover, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor 11 can be improved. The shortest distance Tb2 can be determined based on the lower surface of the conductive layer 260 inside the opening 290.

[0130] In addition, it is preferable to use a conductive material containing oxygen for the conductive layer 120b. As a result, even when a metal oxide is used as the semiconductor layer 130, it is possible to suppress the formation of a region with high electrical resistance in the region of the conductive layer 120b in contact with the semiconductor layer 130 and in the region nearby the region, due to oxygen contained in the metal oxide. As a result, it is possible to reduce the contact resistance between the semiconductor layer 130 and the conductive layer 120b. Similarly, it is preferable to use a conductive material containing oxygen for the conductive layer 140a. As a result, when a metal oxide is used as the semiconductor layer 130, it is possible to reduce the contact resistance between the semiconductor layer 130 and the conductive layer 140a. In addition, it is preferable to use a conductive material containing oxygen for the conductive layer 220b. As a result, when a metal oxide is used as the semiconductor layer 230, it is possible to reduce the contact resistance between the semiconductor layer 230 and the conductive layer 220b. Similarly, it is preferable to use a conductive material containing oxygen for the conductive layer 240a. As a result, when a metal oxide is used as the semiconductor layer 230, it is possible to reduce the contact resistance between the semiconductor layer 230 and the conductive layer 240a.

[0131] When the conductive layer 120, the conductive layer 220, and the conductive layer 240 have a stacked structure, a conductive material containing oxygen is used for a layer of the stacked structure that is closest to a channel formation region, and the contact resistance with the semiconductor layer 130 or the semiconductor layer 230 is reduced, whereby the current path between the source and the drain can be shortened. This can increase the on-current of the transistor. As the conductive material containing oxygen, a conductive metal oxide (also referred to as an oxide conductor) is preferably used.

[0132] When the semiconductor layer 130 contacts the upper surface and side surfaces of the conductive layer 140, the contact area with the conductive layer 140 is larger than when the semiconductor layer 130 contacts only the side surfaces of the conductive layer 140. This makes it possible to reduce the contact resistance between the semiconductor layer 130 and the conductive layer 140. Therefore, it is possible to suppress a decrease in the on-current of the transistor 11 caused by the contact resistance. Furthermore, when the semiconductor layer 230 contacts the upper surface and side surfaces of the conductive layer 240, the contact area with the conductive layer 240 is larger than when the semiconductor layer 230 contacts only the side surfaces of the conductive layer 240. This makes it possible to reduce the contact resistance between the semiconductor layer 230 and the conductive layer 240. Therefore, it is possible to suppress a decrease in the on-current of the transistor 11 caused by the contact resistance.

[0133] As shown in FIG. 1D and FIG. 2A, the insulating layer 285 has a region overlapping with the conductive layer 240 via the insulating layer 283 and the semiconductor layer 230. The insulating layer 285 has an opening 270 that reaches the semiconductor layer 230 at a position overlapping with the opening 290. At least a part of the components of the transistor 11 is disposed inside the opening 270. Specifically, the insulating layer 250 and the conductive layer 260 are disposed so that at least a part of them is located inside the opening 270. At least a part of the insulating layer 283 is located inside the opening 270. The insulating layer 283 covers the upper surface and side surface of the semiconductor layer 230 and the side surface of the conductive layer 240. The insulating layer 250 is in contact with the insulating layer 283 inside the opening 270. Note that the opening 270 may be provided in the insulating layer 283.

[0134] A region of insulating layer 250 that is disposed inside opening 270 is provided to reflect the shape of opening 270. Specifically, insulating layer 283 is provided to cover the sidewall of opening 270 (the side surface of insulating layer 285), and insulating layer 250 is provided inside insulating layer 283. Then, conductive layer 260 is provided to fill at least a portion of the recess of insulating layer 250 that reflects the shape of opening 270.

[0135] In the transistor 11, the conductive layer 260 does not overlap with the top surface of the conductive layer 240, and therefore the parasitic capacitance between the conductive layer 240 and the conductive layer 260 can be reduced. As shown in FIG. 3A, in a cross-sectional view, the maximum value of the width of the conductive layer 260 is smaller than the width D of the opening 290. In this manner, when the maximum value of the width of the conductive layer 260 is smaller than the width D of the opening 290, the parasitic capacitance between the conductive layer 260 and the conductive layer 240 can be reduced, which is preferable. Note that, for example, as shown in FIG. 3A, the magnitude relationship between the two widths in the semiconductor device of one embodiment of the present invention can be confirmed by a cross section parallel to the Z direction.

[0136] In this specification, the term "in a cross-sectional view" is used, but may be specifically rephrased as "in a cross-sectional view from the same direction." For example, when explaining the relationship between multiple configurations, the relationship in a cross-sectional view from the same direction is explained. In this case, the relationship between the multiple configurations can be explained using one cross-sectional view.

[0137] Note that the width D of the opening 290 may vary in the depth direction. In particular, the shortest distance between the two side surfaces of the conductive layer 240 on the opening 290 side in a cross-sectional view is used as the width D. In other words, the minimum value of the width of the opening 290 in the conductive layer 240 is used as the width D of the opening 290.

[0138] It is preferable that the height of the top surface of the conductive layer 260 is the same as or approximately the same as the height of the top surface of the insulating layer 285. The conductive layer 265 is located on the insulating layer 285, the insulating layer 283, the insulating layer 250, and the conductive layer 260, and is in contact with the top surface of the conductive layer 260. Furthermore, the conductive layer 265 can be in contact with the top surface of the insulating layer 285, the top surface of the insulating layer 283, and the top surface of the insulating layer 250.

[0139] FIG. 1D shows a structure in which the end of the conductive layer 140a, the end of the conductive layer 140b, and the end of the semiconductor layer 130 are aligned outside the opening 190. FIG. 1D also shows a structure in which the end of the conductive layer 240a, the end of the conductive layer 240b, and the end of the semiconductor layer 230 are aligned outside the opening 290. As in a manufacturing method example described later, the conductive layer 140a, the conductive layer 140b, and the semiconductor layer 130 can be formed by processing using the same mask. Furthermore, the conductive layer 240a, the conductive layer 240b, and the semiconductor layer 230 can be formed by processing using the same mask. Therefore, the number of masks required for manufacturing a semiconductor device can be reduced, which is preferable.

[0140] The conductive layer 140 has an opening 190 in a region overlapping with the conductive layer 120. The conductive layer 140 is preferably not provided inside the opening 190 of the insulating layer 180. That is, the conductive layer 140 preferably does not have a region in contact with the side surface of the insulating layer 180 inside the opening 190. With this configuration, the opening 190 can be formed in the conductive layer 140 and the insulating layer 180 at once. If the side surface of the conductive layer 140 inside the opening 190 and the side surface of the insulating layer 180 inside the opening 190 are aligned, the film thickness distribution of the semiconductor layer 130 provided inside the opening 190 can be made uniform. Also, the semiconductor layer 130 can be prevented from being divided by a step between the conductive layer 140 and the insulating layer 180.

[0141] As described above, the conductive layer 240 has an opening 290 in a region overlapping with the conductive layer 220. Moreover, it is preferable that the conductive layer 240 is not provided inside the opening 290 of the insulating layer 280. In other words, it is preferable that the conductive layer 240 does not have a region in contact with the side surface of the insulating layer 280 inside the opening 290.

[0142] In addition, in FIG. 1(D) and FIG. 2(B), an example is shown in which the inclination of the side surface of the conductive layer 140 inside the opening 190 is equal to the inclination of the side surface of the insulating layer 180 inside the opening 190, but the inclination of these side surfaces may be different. In this case, for example, it is preferable that the taper angle of the side surface of the conductive layer 140 inside the opening 190 is smaller than the taper angle of the side surface of the insulating layer 180 inside the opening 190. By adopting such a configuration, the coverage of the semiconductor layer 130 on the side surface of the conductive layer 140 inside the opening 190 can be improved, and defects such as voids can be reduced. In addition, when the insulating layer 180 has a laminated structure, the inclination of the side surface of each layer inside the opening 190 may be different. Similarly, when the conductive layer 140 has a laminated structure, the inclination of the side surface of each layer inside the opening 190 may be different.

[0143] As described above, Figures 1(D) and 2(A) show an example in which the slope of the side of the conductive layer 240 inside the opening 290 and the slope of the side of the insulating layer 280 inside the opening 290 are equal, but the slopes of these side surfaces may be different.

[0144] The transistor 13 includes a metal oxide (also referred to as an oxide semiconductor) functioning as a semiconductor in the semiconductor layer 130 including a channel formation region. The transistor 11 includes an oxide semiconductor in the semiconductor layer 230 including a channel formation region. Thus, the transistor 11 and the transistor 13 can be considered as OS transistors.

[0145] OS transistors have oxygen vacancies (V O) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. In addition, hydrogen near the oxygen vacancy may become a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V O H) and generate electrons that serve as carriers. For this reason, if the channel formation region in the metal oxide contains oxygen vacancies, the OS transistor is likely to have normally-on characteristics. Therefore, it is preferable that the oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration of the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.

[0146] On the other hand, the source and drain regions of the OS transistor have more oxygen vacancies than the channel formation region. O It is preferable that the region has a high carrier concentration and low resistance due to a high concentration of H or a high concentration of impurities such as hydrogen, nitrogen, or metal elements. That is, the source and drain regions of the OS transistor are preferably n-type regions with a high carrier concentration and low resistance compared to the channel formation region.

[0147] An OS transistor has a small off-state current. Thus, by using an OS transistor as the transistor 13 in particular, data can be held in the memory cell 10 for a long period of time. As a result, a refresh operation is unnecessary. Alternatively, the frequency of the refresh operation can be significantly reduced. As a result, the semiconductor device of one embodiment of the present invention can be a semiconductor device with low power consumption. Here, the transistor 11 can also be an OS transistor like the transistor 13.

[0148] As described above, the semiconductor layer 130 is provided inside the opening 190 of the insulating layer 180. In addition, the transistor 13 has a configuration in which one of the source electrode and the drain electrode (conductive layer 120 here) is located below and the other of the source electrode and the drain electrode (conductive layer 140 here) is located above, so that a current flows in a vertical direction. That is, a channel is formed along the side wall of the opening 190 of the insulating layer 180. Similarly, in the transistor 11, a channel is formed along the side wall of the opening 290 of the insulating layer 280.

[0149] As shown in FIG. 3B, the insulating layer 280 contacts the entire outer periphery of the semiconductor layer 230. Thus, the channel formation region of the transistor 11 can be formed on the entire outer periphery of the semiconductor layer 230 inside the opening 290 (the entire region in contact with the insulating layer 280). Similarly, the insulating layer 180 contacts the entire outer periphery of the semiconductor layer 130. Thus, the channel formation region of the transistor 13 can be formed on the entire outer periphery of the semiconductor layer 130 inside the opening 190 (the entire region in contact with the insulating layer 180). Note that FIG. 3B can also be said to be a cross-sectional view in the XY plane including the channel formation region of the semiconductor layer 230.

[0150] The channel lengths of the transistors 13 and 11 are the distances between the source region and the drain region. The channel length of the transistor 13 can correspond to the length of the side of the insulating layer 180 on the opening 190 side. The channel length of the transistor 11 can correspond to the length of the side of the insulating layer 280 on the opening 290 side. In FIG. 3A, the channel length L1 of the transistor 13 and the channel length L2 of the transistor 11 are indicated by dashed double-headed arrows. Here, an example is shown in which the channel length L1 corresponds to the length of the side of the insulating layer 180 on the opening 190 side. Also, an example is shown in which the channel length L2 corresponds to the length of the side of the insulating layer 280 on the opening 290 side.

[0151] In conventional transistors, the channel length is set by the exposure limit of photolithography, but in one embodiment of the present invention, the channel length can be set by the film thickness of the insulating layer 180 or the insulating layer 280. Thus, the channel lengths of the transistors 13 and 11 can be made to be very fine structures that are equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). As a result, the on-current of the transistors 13 and 11 can be increased, and the frequency characteristics can be improved.

[0152] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed inside the opening 190 and the opening 290. As a result, the area occupied by the transistors 13 and 11 can be reduced compared to a horizontal transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. Thus, the semiconductor device can be highly integrated. Furthermore, when the semiconductor device of one embodiment of the present invention is used for a memory device, the memory capacity per unit area can be increased.

[0153] As shown in FIG. 3B, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 are arranged concentrically. Therefore, the side of the conductive layer 260 arranged at the center faces the side of the semiconductor layer 230 with the insulating layer 250 sandwiched therebetween. That is, in plan view, the entire circumference of the semiconductor layer 230 becomes a channel formation region. At this time, for example, the channel width of the transistor 11 is determined by the length of the outer circumference of the semiconductor layer 230. That is, it can be said that the channel width of the transistor 11 is determined by the width of the opening 290 (the diameter when the opening 290 is circular in plan view). In FIG. 3A and FIG. 3B, the width D of the opening 290 is indicated by a double-headed arrow of a two-dot chain line. In FIG. 3B, the channel width W of the transistor 11 is indicated by a double-headed arrow of a one-dot chain line. By increasing the width D of the opening 290, the channel width per unit area can be increased, and the on-current can be increased. Similarly, in plan view, the entire circumference of the semiconductor layer 130 becomes a channel formation region. In this case, for example, the channel width of the transistor 13 is determined by the outer periphery of the semiconductor layer 130. In other words, it can be said that the channel width of the transistor 13 is determined by the width of the opening 190 (the diameter when the opening 190 is circular in plan view).

[0154] When the opening 290 is formed using a photolithography method, the width D of the opening 290 is set by the exposure limit of photolithography. The width D of the opening 290 is set by the film thickness of each of the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 provided inside the opening 290. The width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 290 is circular in plan view, the width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x π". The above can also be applied to the width of the opening 190 by replacing the opening 290, the semiconductor layer 230, the insulating layer 250, and the conductive layer 260 with the opening 190, the semiconductor layer 130, the insulating layer 150, and the conductive layer 220, respectively.

[0155] Moreover, the channel length L2 of the transistor 11 is preferably at least smaller than the channel width W of the transistor 11. The channel length L2 of the transistor 11 is preferably 0.1 to 0.99 times, and more preferably 0.5 to 0.8 times, the channel width W of the transistor 11. Similarly, the channel length L1 of the transistor 13 is preferably at least smaller than the channel width W of the transistor 13. The channel length L1 of the transistor 13 is preferably 0.1 to 0.99 times, and more preferably 0.5 to 0.8 times, the channel width W of the transistor 13. With this configuration, the transistor 13 and the transistor 11 having good electrical characteristics and high reliability can be realized.

[0156] Moreover, by forming the opening 190 so as to have a circular shape in a plan view, the semiconductor layer 130, the insulating layer 150, and the conductive layer 220 are provided concentrically. This makes the distance between the conductive layer 220 and the semiconductor layer 130 approximately uniform, so that a gate electric field can be applied approximately uniformly to the semiconductor layer 130. Similarly, by forming the opening 290 so as to have a circular shape in a plan view, a gate electric field can be applied approximately uniformly to the semiconductor layer 230.

[0157] By making the shape of the opening 190, the opening 192, the opening 290, and the opening 270 circular in plan view, the processing accuracy when forming the openings can be improved, and openings of a fine size can be formed. The shape of the opening 190, the opening 192, the opening 290, and the opening 270 in plan view is not limited to a circle. For example, it can be a substantially circular shape such as an ellipse, a polygonal shape such as a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a pentagon, a star-shaped polygon, or a shape with rounded corners of these polygons. The polygon can be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).

[0158] In this specification and the like, a circular shape is not limited to a perfect circle.

[0159] As shown in FIGS. 1D, 2A, and 3A, an MIM structure is formed on the sidewall and bottom of the opening 192 as the capacitor 15. Thus, the capacitor 15 is a trench-type capacitor. Therefore, the capacitance value of the capacitor 15 can be increased without increasing the occupied area, as compared with, for example, a planar-type capacitor. In the semiconductor device of one embodiment of the present invention, the capacitance value can be ensured even if the occupied area of ​​the capacitor is reduced. Therefore, a semiconductor device that can reduce the occupied area of ​​a memory cell and enable miniaturization or high integration can be provided.

[0160] Here, in order to form a trench-type capacitor, it is necessary to form an opening in an interlayer insulating layer. In the semiconductor device of one embodiment of the present invention, as described above, the opening 192 can be formed in parallel with the opening 190. Therefore, even if the capacitor 15 is a trench-type capacitor, an increase in the number of manufacturing steps of the semiconductor device of one embodiment of the present invention can be suppressed as compared with, for example, a planar-type capacitor. Note that the capacitor 15 may be a capacitor other than a trench-type capacitor, for example, a planar-type capacitor.

[0161] For example, although FIG. 1D shows an example in which the transistor 11 overlaps with the capacitor 15, one embodiment of the present invention is not limited to this. FIG. 4A shows an example in which the transistor 11 overlaps with the transistor 13. FIG. 4A shows an example in which the opening 290 overlaps with the opening 190. FIG. 4B shows an example in which the transistor 11 is provided so as to overlap with a region between the transistor 13 and the capacitor 15. FIG. 4B shows an example in which the opening 290 overlaps with a region between the opening 190 and the opening 192.

[0162] As described above, in the semiconductor device of one embodiment of the present invention, the transistor 11 is provided to overlap with at least part of the transistor 13, the capacitor 15, and the region between the transistor 13 and the capacitor 15. This makes it possible to reduce the area occupied by each memory cell compared to the case where the transistor 11, the transistor 13, and the capacitor 15 are provided in the same layer, for example. Thus, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0163] <Materials for semiconductor devices> Materials that can be used in the semiconductor device of this embodiment will be described below. Each layer constituting the semiconductor device of this embodiment may have a single-layer structure or a stacked structure. FIGS. 1D, 2A, and 2B show an example in which the conductive layer 120a, the conductive layer 121a, the conductive layer 220a, the semiconductor layer 130, the semiconductor layer 230, and the conductive layer 260 have a single-layer structure. FIG. 3A shows an example in which the conductive layer 120a, the conductive layer 121a, the conductive layer 220a, the semiconductor layer 130, the semiconductor layer 230, and the conductive layer 260 have a stacked structure.

[0164] [Semiconductor layer] As described above, the semiconductor layer 130 and the semiconductor layer 230 have a channel formation region. The channel formation region is i-type (intrinsic) or substantially i-type. The semiconductor layer 130 and the semiconductor layer 230 further have a source region and a drain region. The source region and the drain region are n-type regions (low resistance regions) having a higher carrier concentration than the channel formation region.

[0165] The crystallinity of the semiconductor material used for the semiconductor layer 130 and the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0166] Furthermore, a metal oxide can be used for the semiconductor layer 130 and the semiconductor layer 230. In this case, the semiconductor layer 130 and the semiconductor layer 230 can be called a metal oxide layer.

[0167] The band gap of the oxide semiconductor is preferably 2.0 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a wide band gap, the off-state current of a transistor can be reduced. Since the off-state current of an OS transistor is small, the power consumption of a semiconductor device can be sufficiently reduced. Furthermore, since the frequency characteristics of an OS transistor are high, the semiconductor device can operate at high speed.

[0168] Examples of metal oxides that can be used for the semiconductor layer 130 and the semiconductor layer 230 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). The metal oxide preferably contains two or three elements selected from indium, element M, and zinc. The element M is a metal element or semi-metal element having a high bond energy with oxygen, for example, a metal element or semi-metal element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification and the like may include metalloid elements.

[0169] The semiconductor layer 130 and the semiconductor layer 230 may be formed of, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), or the like. Indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO), etc. can be used. Alternatively, indium tin oxide containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0170] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased, and a transistor with a large on-state current can be realized.

[0171] The metal oxide may have one or more metal elements having a large period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element having a large period number in the periodic table, the field effect mobility of the transistor may be increased. Examples of metal elements having a large period number in the periodic table include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0172] The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the carrier concentration may be increased, the band gap may be narrowed, or the like, and the field effect mobility of the transistor may be increased. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, bromine, and hydrogen.

[0173] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing the fluctuation of the electrical characteristics of the transistor and improving its reliability.

[0174] Moreover, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, a metal oxide having a large band gap can be obtained. Furthermore, formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, a shift in the threshold voltage of the transistor can be suppressed. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0175] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide applied to the semiconductor layer 130 and the semiconductor layer 230. Thus, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of a transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

[0176] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn=1:1:0.5, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:1:2, In:M:Zn=2:1:3, In:M:Zn=3:1:1, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, and compositions in the vicinity thereof. The term "composition in the vicinity" includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, or the like of a transistor can be increased.

[0177] In addition, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, and compositions close to these. By increasing the ratio of the number of M atoms in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0178] When the element M contains a plurality of metal elements, the total proportion of the atomic numbers of the metal elements can be regarded as the proportion of the atomic number of the element M.

[0179] In this specification and the like, the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.

[0180] In addition, when the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements of the In-Zn oxide may be, for example, In:Zn=1:1, In:Zn=2:1, In:Zn=4:1, or a composition close to these. The In-Zn oxide may also contain a trace amount of element M. For example, when the element M is Sn, the atomic ratio of the metal elements of the metal oxide may be, for example, In:Sn:Zn=2:0.1:1, In:Sn:Zn=4:0.1:1, or a composition close to these.

[0181] The composition of the metal oxide used in the semiconductor layer 130 and the semiconductor layer 230 can be analyzed by, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that, for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content. In addition, it may be difficult to quantify element M, or element M may not be detected.

[0182] The metal oxide can be preferably formed by sputtering or ALD. When the metal oxide is formed by sputtering, the composition of the metal oxide after film formation may differ from that of the target. In particular, the content of zinc in the metal oxide after film formation may decrease to about 50% compared to that of the target. The metal oxide may be formed by chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or the like.

[0183] The semiconductor layer 130 and the semiconductor layer 230 may have a stacked structure having two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 130 and the semiconductor layer 230 may have the same or approximately the same composition. By using a stacked structure of metal oxide layers having the same composition, for example, the same sputtering target can be used to form the layers, thereby reducing manufacturing costs.

[0184] The two or more metal oxide layers included in the semiconductor layer 130 and the semiconductor layer 230 may have different compositions.

[0185] 3A shows an example in which the semiconductor layer 130 has a two-layer structure of a metal oxide layer 130a and a metal oxide layer 130b on the metal oxide layer 130a. Also, an example in which the semiconductor layer 230 has a two-layer structure of a metal oxide layer 230a and a metal oxide layer 230b on the metal oxide layer 230a is shown.

[0186] For example, the metal oxide layer 130a and the metal oxide layer 230a are preferably made of a material having higher conductivity than the metal oxide layer 130b and the metal oxide layer 230b. By using a material having high conductivity for the metal oxide layer 130a in contact with the source electrode and drain electrode (conductive layer 120 and conductive layer 140) of the transistor 13, the contact resistance between the semiconductor layer 130 and the conductive layer 120 and the contact resistance between the semiconductor layer 130 and the conductive layer 140 can be reduced. Thus, the transistor 13 can be a transistor with a large on-current. Similarly, by using a material having high conductivity for the metal oxide layer 230a in contact with the source electrode and drain electrode (conductive layer 220 and conductive layer 240) of the transistor 11, the contact resistance between the semiconductor layer 230 and the conductive layer 220 and the contact resistance between the semiconductor layer 230 and the conductive layer 240 can be reduced. Thus, the transistor 11 can be a transistor with a large on-current.

[0187] Here, when a material having high conductivity is used for the metal oxide layer 130b provided on the conductive layer 220 side functioning as the gate electrode of the transistor 13, the threshold voltage of the transistor 13 may shift, and the drain current (hereinafter also referred to as cutoff current) flowing when the gate voltage is 0 V may become large. Specifically, when the transistor 13 is an n-channel transistor, the threshold voltage may be lowered. Similarly, when a material having high conductivity is used for the metal oxide layer 230b provided on the conductive layer 260 side functioning as the gate electrode of the transistor 11, the threshold voltage of the transistor 11 may shift, and the cutoff current may become large. Specifically, when the transistor 11 is an n-channel transistor, the threshold voltage may be lowered. For the above reasons, it is preferable to use a material having lower conductivity than the metal oxide layer 130a and the metal oxide layer 230a for the metal oxide layer 130b and the metal oxide layer 230b. As a result, when the transistor 13 and the transistor 11 are n-channel transistors, the threshold voltage can be increased and the cutoff current can be reduced. Incidentally, a small cutoff current is sometimes referred to as normally-off.

[0188] As described above, by forming the semiconductor layer 130 and the semiconductor layer 230 into a stacked structure and using a material having a higher conductivity than the metal oxide layer 130b and the metal oxide layer 230b for the metal oxide layer 130a and the metal oxide layer 230a, a normally-off transistor with a large on-current can be obtained. Therefore, a semiconductor device that achieves both low power consumption and high performance can be provided.

[0189] The carrier concentration of the metal oxide layer 130a and the metal oxide layer 230a is preferably higher than that of the metal oxide layer 130b and the metal oxide layer 230b. The conductivity is increased by increasing the carrier concentration of the metal oxide layer 130a and the metal oxide layer 230a. Thus, the contact resistance between the semiconductor layer 130 and the conductive layer 120, the contact resistance between the semiconductor layer 130 and the conductive layer 140, the contact resistance between the semiconductor layer 230 and the conductive layer 220, and the contact resistance between the semiconductor layer 230 and the conductive layer 240 can be reduced. Thus, the transistor 13 and the transistor 11 can be transistors with a large on-current. Furthermore, the conductivity is reduced by decreasing the carrier concentration of the metal oxide layer 130b and the metal oxide layer 230b, and the transistor 13 and the transistor 11 can be normally-off transistors.

[0190] The semiconductor layer 130 and the semiconductor layer 230 are not limited to the above-mentioned configuration, and the metal oxide layer 130a and the metal oxide layer 230a may be made of a material having a lower conductivity than the metal oxide layer 130b and the metal oxide layer 230b. The carrier concentration of the metal oxide layer 130a and the metal oxide layer 230a may be lower than the carrier concentration of the metal oxide layer 130b and the metal oxide layer 230b.

[0191] In addition, the band gap of the first metal oxide used in the metal oxide layer 130a and the metal oxide layer 230a is preferably different from the band gap of the second metal oxide used in the metal oxide layer 130b and the metal oxide layer 230b. For example, the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.

[0192] The band gap of the first metal oxide used for the metal oxide layer 130a and the metal oxide layer 230a is preferably smaller than the band gap of the second metal oxide used for the metal oxide layer 130b and the metal oxide layer 230b. This can reduce the contact resistance between the semiconductor layer 130 and the conductive layer 120, the contact resistance between the semiconductor layer 130 and the conductive layer 140, the contact resistance between the semiconductor layer 230 and the conductive layer 220, and the contact resistance between the semiconductor layer 230 and the conductive layer 240. Thus, the transistor 13 and the transistor 11 can be transistors with large on-state current. Furthermore, when the transistor 13 and the transistor 11 are n-channel transistors, the threshold voltage can be increased, and the transistors can be normally-off transistors. In addition, since the second metal oxide has a large band gap, carriers can be suppressed from being generated and induced in the metal oxide layer 130b and the metal oxide layer 230b, at the interface between the metal oxide layer 130b and the insulating layer 150, and at the interface between the metal oxide layer 230b and the insulating layer 250. This can improve the reliability of the transistor.

[0193] For example, the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide. More specifically, for example, metal oxide layers 130a and 230a are preferably made of metal oxides having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition thereabout, and metal oxide layers 130b and 230b are preferably made of metal oxides having a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition thereabout. In this case, it is particularly preferable to use one or more of gallium, aluminum, and tin as element M.

[0194] The semiconductor layer 130 and the semiconductor layer 230 are not limited to the above-mentioned configuration, and the band gap of the first metal oxide may be larger than the band gap of the second metal oxide.

[0195] Moreover, the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide. The first metal oxide may be configured to contain a trace amount of element M or may not contain element M. For example, it is preferable that the first metal oxide used in the metal oxide layer 130a and the metal oxide layer 230a is an In-Zn oxide, and the second metal oxide used in the metal oxide layer 130b and the metal oxide layer 230b is an In-M-Zn oxide. Specifically, the first metal oxide can be an In-Zn oxide, and the second metal oxide can be an In-Ga-Zn oxide.

[0196] For example, it is preferable to use, as the metal oxide layer 130a and the metal oxide layer 230a, a metal oxide having a composition of In:Zn=1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Zn=2:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition close thereto, or an indium oxide. It is also preferable to use, as the metal oxide layer 130b and the metal oxide layer 230b, a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto. This makes it possible to increase the on-state current of the transistor 11 and to provide a highly reliable transistor structure with less variation.

[0197] For example, when a metal oxide is used for the conductive layer 120 or the conductive layer 140 (in the case of a stacked structure, the layer closest to the channel formation region of the semiconductor layer 130), it is preferable to use In-Zn oxide or In-Sn-Zn oxide for the semiconductor layer 130 (or the metal oxide layer 130a) because the contact resistance can be lowered compared to the case of using In-Ga-Zn oxide for the semiconductor layer 130 (or the metal oxide layer 130a). Specifically, it is preferable to use indium tin oxide (also referred to as ITO) or indium tin oxide with silicon added (also referred to as ITSO) for the conductive layer 120b and the conductive layer 140a in FIG. 3(A), use In-Zn oxide or In-Sn-Zn oxide for the metal oxide layer 130a, and use In-Ga-Zn oxide for the metal oxide layer 130b.

[0198] Similarly, when a metal oxide is used for the conductive layer 220 or the conductive layer 240 (in the case of a laminated structure, the layer closest to the channel formation region of the semiconductor layer 230), it is preferable to use In-Zn oxide or In-Sn-Zn oxide for the semiconductor layer 230 (or the metal oxide layer 230a), since this can reduce the contact resistance compared to when In-Ga-Zn oxide is used for the semiconductor layer 230 (or the metal oxide layer 230a). Specifically, it is preferable to use ITO or ITSO for the conductive layer 220b and the conductive layer 240a in FIG. 3(A), use In-Zn oxide or In-Sn-Zn oxide for the metal oxide layer 230a, and use In-Ga-Zn oxide for the metal oxide layer 230b.

[0199] The semiconductor layer 130 and the semiconductor layer 230 are not limited to the above-mentioned configuration, and the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide.

[0200] The crystallinity of the semiconductor materials used for the semiconductor layer 130 and the semiconductor layer 230 is not particularly limited, and any of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0201] The semiconductor layer 130 and the semiconductor layer 230 each preferably have a metal oxide layer having crystallinity. Examples of the structure of the metal oxide having crystallinity include a c-axis aligned crystal (CAAC) structure, a polycrystal (Poly-crystal) structure, and a nanocrystal (nc) structure. By using a metal oxide layer having crystallinity for the semiconductor layer 130 and the semiconductor layer 230, the defect level density in the semiconductor layer 130 and the semiconductor layer 230 can be reduced, and a highly reliable semiconductor device can be realized. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of IGZO microcrystals) have a c-axis orientation, and the plurality of microcrystals are connected without being oriented in the ab plane. In addition, when a cross section of an OS film having a CAAC structure is observed using a high-resolution TEM image, it can be confirmed that metal atoms are arranged in layers in the crystal parts. Therefore, the OS film having a CAAC structure can also be said to have a structure having layered crystal parts.

[0202] The polycrystalline structure has grain boundaries. In addition, when a heat treatment is performed after forming a metal oxide layer having a polycrystalline structure, a minute gap (also called a nanocrack or a microcrack) or a minute space (also called a nanospace or a microspace) may be formed between the crystal parts. When a minute gap or a minute space is formed in the metal oxide layer, the electric resistance of the metal oxide layer increases. This is because the electric resistance of the minute gap or minute space is very high, for example, infinite. When a metal oxide layer having a minute gap or minute space is used in a channel formation region of a transistor, the contact resistance between the metal oxide layer and one or both of the source electrode and the drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. The CAAC structure has fewer grain boundaries in the ab plane than the polycrystalline structure, and therefore can realize a highly reliable semiconductor device.

[0203] The higher the crystallinity of the metal oxide layers used for the semiconductor layer 130 and the semiconductor layer 230, the more the density of defect states in the semiconductor layer 130 and the semiconductor layer 230 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0204] The higher the substrate temperature (stage temperature) during the formation of the metal oxide layer, the higher the crystallinity of the metal oxide layer that can be formed. Also, the higher the ratio of the flow rate of oxygen gas to the total deposition gas used during the formation (hereinafter, also referred to as oxygen flow rate ratio), the higher the crystallinity of the metal oxide layer that can be formed.

[0205] The crystallinity of the semiconductor layer 130 and the semiconductor layer 230 can be analyzed by, for example, X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.

[0206] The semiconductor layer 130 and the semiconductor layer 230 can each have a stacked structure of two or more metal oxide layers with different crystallinity. In this case, the two or more metal oxide layers may have different compositions or may have the same or approximately the same composition. For example, a stacked structure of a first metal oxide layer and a second metal oxide layer located on the first metal oxide layer can be used, and the second metal oxide layer can have a region with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer can have a region with lower crystallinity than the first metal oxide layer. Note that when the second metal oxide layer has a region with lower crystallinity than the first metal oxide layer, the crystallinity of the second metal oxide layer can be increased by performing heat treatment (also referred to as crystallization treatment) after forming the second metal oxide layer.

[0207] For example, it is preferable to use a metal oxide having a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto as the metal oxide layer 130a, or a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto as the metal oxide layer 130b, and to use a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto as the metal oxide layer 130b. When a metal oxide having a high ratio of Zn to In is used for the metal oxide layer 130a, the crystallinity of the metal oxide layer 130a can be improved. Furthermore, by forming the metal oxide layer 130b on the metal oxide layer 130a having high crystallinity, it is also easy to improve the crystallinity of the metal oxide layer 130b. The same can be said about the metal oxide layer 230a and the metal oxide layer 230b. This makes it possible to improve the crystallinity of the entire semiconductor layer 130 and the entire semiconductor layer 230, which is preferable. In this case, it is particularly preferable to use gallium, aluminum, or tin as the element M. For example, two layers of IGZO having different compositions may be stacked.Also, for example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.

[0208] Furthermore, the semiconductor layer 130 and the semiconductor layer 230 may each have a stacked structure of three or more layers. The semiconductor layer 130 may have a three-layer structure having, for example, an oxide layer, a metal oxide layer 130a on the oxide layer, and a metal oxide layer 130b on the metal oxide layer 130a. In the following, an example will be described in which the semiconductor layer 130 has a three-layer structure, but a similar structure can also be applied to the semiconductor layer 230.

[0209] The above-mentioned configurations can be applied to the metal oxide layer 130a and the metal oxide layer 130b. The oxide layer located under the metal oxide layer 130a can have the same configuration as that applicable to the metal oxide layer 130b. In the following, they will be collectively described as a pair of oxide layers sandwiching the metal oxide layer 130a.

[0210] For example, it is preferable to use, as the metal oxide layer 130a, a metal oxide having a composition of In:Zn=1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Zn=2:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Zn=4:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition close thereto, or an indium oxide. Also, it is preferable to use, as the pair of oxide layers sandwiching the metal oxide layer 130a, a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto, or a metal oxide having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto.

[0211] The pair of oxide layers sandwiching the metal oxide layer 130a preferably have a band gap larger than that of the metal oxide layer 130a. As a result, the metal oxide layer 130a is sandwiched between the pair of oxide layers having a larger band gap, and the metal oxide layer 130a mainly functions as a current path (channel). By sandwiching the metal oxide layer 130a between the pair of oxide layers, it is possible to reduce trap levels at the interface of the metal oxide layer 130a and in the vicinity thereof. As a result, a buried channel type transistor in which the channel is kept away from the insulating layer interface can be realized, and the field effect mobility can be increased. In addition, the influence of the interface state that may be formed on the back channel side is reduced, and light deterioration (e.g., negative bias light deterioration) of the transistor can be suppressed, and the reliability of the transistor can be improved.

[0212] The thickness of the semiconductor layer 130 and the semiconductor layer 230 is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, more preferably 10 nm or more and 70 nm or less, more preferably 15 nm or more and 70 nm or less, more preferably 15 nm or more and 50 nm or less, and more preferably 20 nm or more and 50 nm or less. In a transistor used in a finer semiconductor device, the thickness of the semiconductor layer 130 and the semiconductor layer 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.

[0213] In addition, when forming the metal oxide layer, it is preferable to use two types of film formation methods, a sputtering method and an ALD method. For example, if a first metal oxide layer having a CAAC structure is formed by a sputtering method, and then a second metal oxide layer having a lower crystallinity than the CAAC structure is formed by an ALD method, it is expected that the atomic layer of the second metal oxide layer will fill or repair the gaps in the atomic-level crystal parts of the CAAC structure of the first metal oxide layer. In addition, it is preferable to perform a heat treatment (for example, 100°C to 500°C, preferably 200°C to 450°C, more preferably 300°C to 400°C) after forming the second metal oxide layer by the ALD method. It is expected that the heat treatment will repair the gaps in the atomic-level crystal parts of the CAAC structure of the first metal oxide layer by the second metal oxide layer (in other words, each crystal molecule formed by the ALD method). Moreover, a metal oxide layer formed by using the above-mentioned two types of film formation methods may be called a hybrid OS.

[0214] In addition, when a metal oxide layer is formed by both sputtering and ALD, if the thickness of the metal oxide layer formed by ALD is thin, it can be regarded as a single-layered metal oxide layer, not a laminated structure of a metal oxide layer formed by sputtering and a metal oxide layer formed by ALD. For example, when the thickness of the metal oxide layer formed by ALD is more than 0 nm and less than 3 nm, preferably more than 0 nm and less than 2 nm, more preferably more than 0 nm and less than 1 nm, the metal oxide layer formed by two types of film formation methods, sputtering and ALD, can be regarded as a single-layered structure. In such a case, for example, in a cross-sectional TEM image and a cross-sectional STEM image, the boundary between the metal oxide layer formed by sputtering and the metal oxide layer formed by ALD is not observed. On the other hand, when the thickness of the metal oxide layer formed by the ALD method exceeds 3 nm, it may be considered to be a laminated structure, a multilayer structure, or a multiple structure of a metal oxide layer formed by the sputtering method and a metal oxide layer formed by the ALD method.

[0215] In addition, when the metal oxide layer is formed by both the sputtering method and the ALD method, it is preferable to use different compositions. Typically, a metal oxide having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto can be formed by the sputtering method, and then a metal oxide having a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition close thereto can be formed by the ALD method. By forming the metal oxide layer of the above-mentioned composition, a structure having high reliability due to the metal oxide layer of In:Ga:Zn=1:1:1 [atomic ratio] and a high on-current or high field effect mobility due to the metal oxide having a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition close thereto can be formed. Note that instead of a metal oxide having a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition close thereto, a metal oxide having a composition of In:Ga:Zn=1:0:0 [atomic ratio], that is, indium oxide or a metal oxide having a high proportion of In, can be used.

[0216] The metal oxide layer formed by the above two deposition methods can be regarded as a structure in which the gaps in the crystal parts of the CAAC structure are filled with atomic layers formed by the ALD method. This structure can be analyzed by analytical methods such as cross-sectional SEM, cross-sectional STEM, cross-sectional TEM, SIMS, and EDX.

[0217] In addition, the metal oxide layer having the CAAC structure formed by using the above-mentioned two types of film formation methods may have a higher dielectric constant, film density, and film hardness than the metal oxide layer having the CAAC structure formed by using one type of film formation method. In this way, by using the metal oxide layer having the CAAC structure formed by using two types of film formation methods in the channel formation region of a transistor, a transistor having excellent characteristics (for example, a transistor having a large on-current, a transistor having a high field-effect mobility, a transistor having a small S value, a transistor having a high frequency characteristic (also called f characteristic), a highly reliable transistor, etc.) can be realized.

[0218] The hydrogen contained in the metal oxide reacts with the oxygen that bonds with the metal atom to form water, and oxygen vacancies (V O In addition, defects in which hydrogen is inserted into oxygen vacancies (hereafter referred to as V O Hydrogen atoms in metal oxides (H) may function as donors and generate electrons as carriers. Some of the hydrogen atoms may also bond with oxygen that bonds with metal atoms to generate electrons as carriers. Therefore, transistors using metal oxides that contain a lot of hydrogen tend to have normally-on characteristics (i.e., a threshold voltage with a negative value). In addition, hydrogen in metal oxides is easily mobile due to stress such as heat or an electric field, so if a metal oxide contains a lot of hydrogen, the reliability of the transistor may be degraded.

[0219] V in the semiconductor layer 130 and the semiconductor layer 230 O It is preferable to reduce H as much as possible and make the semiconductor layer 130 and the semiconductor layer 230 highly intrinsic or substantially highly intrinsic. O In order to obtain a metal oxide with a sufficiently reduced amount of H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to repair the oxygen vacancies. O Stable electrical characteristics can be imparted by using a metal oxide in which impurities such as H are sufficiently reduced in the channel formation region of a transistor. Note that supplying oxygen to a metal oxide to repair oxygen vacancies is sometimes referred to as oxygen addition treatment.

[0220] The carrier concentration of the metal oxide in the region that functions as the channel formation region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3The lower limit of the carrier concentration of the metal oxide in the region functioning as the channel formation region is not particularly limited, but is, for example, 1×10 -9 cm -3 It can be said that:

[0221] Here, the influence of each impurity in a metal oxide (oxide semiconductor) will be described.

[0222] When a metal oxide contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the metal oxide. Therefore, the carbon concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The silicon concentration in the metal oxide channel formation region obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The following applies.

[0223] Furthermore, when nitrogen is contained in a metal oxide, electrons that act as carriers are generated, the carrier concentration increases, and the metal oxide is likely to become n-type. As a result, a transistor using a nitrogen-containing metal oxide as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in a metal oxide, a trap level may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0224] In addition, hydrogen contained in the metal oxide reacts with oxygen that bonds to metal atoms to form water, which may form oxygen vacancies. Hydrogen entering the oxygen vacancies may generate electrons that serve as carriers. In addition, some of the hydrogen may bond with oxygen that bonds to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using a metal oxide that contains hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the metal oxide as much as possible. Specifically, the hydrogen concentration in the channel formation region of the metal oxide obtained by SIMS is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×1018 atoms / cm 3 Less than.

[0225] In addition, when an alkali metal or an alkaline earth metal is contained in a metal oxide, a defect level may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the metal oxide obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0226] By using a metal oxide with sufficiently reduced impurities for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0227] In addition, the semiconductor device of this embodiment may be applied to a transistor using another semiconductor material in the channel formation region. Examples of the other semiconductor material include a semiconductor made of a single element or a compound semiconductor. Examples of the semiconductor made of a single element include silicon and germanium. Examples of the compound semiconductor include gallium arsenide and silicon germanium. Other examples of the compound semiconductor include organic semiconductors and nitride semiconductors. The above-mentioned metal oxide is also a type of compound semiconductor. These semiconductor materials may include impurities as dopants.

[0228] Silicon that can be used as a semiconductor material for a transistor includes single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low temperature polysilicon (LTPS).

[0229] The semiconductor layer of the transistor may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0230] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (elements belonging to group 16). Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the semiconductor layer of a transistor include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2).

[0231] [Insulation layer] For the insulating layers (insulating layer 110, insulating layer 150, insulating layer 180, insulating layer 250, insulating layer 280, insulating layer 283, insulating layer 285, etc.) of the semiconductor device, an inorganic insulating film is preferably used. Examples of the inorganic insulating film include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An organic insulating film may be used for an insulating layer included in a semiconductor device.

[0232] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current can occur due to thinner gate insulating layers. Using high-k materials for the gate insulating layer makes it possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for the interlayer insulating layer can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength.

[0233] Examples of materials having a high dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0234] Examples of materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Examples of other inorganic insulating materials with a low relative dielectric constant include silicon oxide to which fluorine is added, silicon oxide to which carbon is added, and silicon oxide to which carbon and nitrogen are added. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0235] Furthermore, a material capable of exhibiting ferroelectricity may be used for an insulating layer of a semiconductor device. Examples of the material capable of exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. X(X is a real number greater than 0). Examples of materials that can have ferroelectricity include materials obtained by adding an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 can be set appropriately, for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Examples of materials that can have ferroelectricity include materials obtained by adding an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. Also, the ratio of the number of zirconium atoms to the number of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. In addition, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as lead zirconate titanate (PZT), strontium tantalate bismuthate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0236] In addition, examples of materials that can have ferroelectricity include metal nitrides having an element M1, an element M2, and nitrogen. Here, the element M1 is one or more selected from aluminum, gallium, and indium. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium. The ratio of the number of atoms of the element M1 to the number of atoms of the element M2 can be set appropriately. In addition, metal oxides having the element M1 and nitrogen may have ferroelectricity even if they do not contain the element M2. In addition, examples of materials that can have ferroelectricity include materials in which the element M3 is added to the above metal nitride. In addition, the element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, and the like. Here, the ratio between the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0237] Moreover, examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N or BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0238] In the above description, metal oxides and metal nitrides are exemplified, but the present invention is not limited thereto. For example, metal oxide nitrides in which nitrogen is added to the above-mentioned metal oxides, or metal nitride oxides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.

[0239] As a material capable of having ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulating layer of the semiconductor device can have a laminated structure made of a plurality of materials selected from the materials listed above. However, the crystal structure (characteristics) of the materials listed above may change not only depending on the film formation conditions but also depending on, for example, various processes. Therefore, in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials capable of having ferroelectricity.

[0240] Metal oxides containing hafnium and / or zirconium can have ferroelectricity even in a thin film of a few nm. Metal oxides containing hafnium and / or zirconium can have ferroelectricity even in a small area. Therefore, by using metal oxides containing hafnium and / or zirconium, it is possible to miniaturize semiconductor devices.

[0241] In this specification, a layer of a material that may have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0242] It is believed that ferroelectricity is expressed by displacing oxygen or nitrogen in the crystals contained in the ferroelectric layer due to an external electric field. It is also presumed that the expression of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer to express ferroelectricity, the insulating layer needs to contain crystals. In particular, it is preferable for the insulating layer to contain crystals having an orthorhombic crystal structure, since ferroelectricity is expressed. The crystal structure of the crystals contained in the insulating layer may be one or more selected from a cubic crystal system, a tetragonal crystal system, an orthorhombic crystal system, a monoclinic crystal system, and a hexagonal crystal system. The insulating layer may have an amorphous structure. In this case, the insulating layer may be a composite structure having an amorphous structure and a crystalline structure.

[0243] In addition, by adding a Group 3 element (also called IIIa element) in the periodic table to an oxide having one or both of hafnium and zirconium, the oxygen vacancy concentration in the oxide increases, and crystals having an orthorhombic crystal structure are easily formed. This is preferable because the proportion of crystals having an orthorhombic crystal structure increases, and the remanent polarization amount can be increased. On the other hand, if the amount of the Group 3 element added is too large, the crystallinity of the oxide decreases, and ferroelectricity may not be easily expressed. Therefore, the content of the Group 3 element in the oxide having one or both of hafnium and zirconium is preferably 0.1 atomic% or more and 10 atomic% or less, more preferably 0.1 atomic% or more and 5 atomic% or less, and even more preferably 0.1 atomic% or more and 3 atomic% or less. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0244] The insulating layer 150, at least a part of which functions as a dielectric layer of the capacitor 15, is preferably made of the above-mentioned material that can have ferroelectricity. This allows data to be held for a long period of time in the memory cell 10. Therefore, the semiconductor device of one embodiment of the present invention can be a nonvolatile memory device.

[0245] In addition, the transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer having a function of suppressing the permeation of impurities and oxygen. As the insulating layer having a function of suppressing the permeation of impurities and oxygen, for example, an insulating layer containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer. Specifically, as a material for the insulating layer having a function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0246] Specifically, examples of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating layers having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, and silicon nitride.

[0247] In addition, an insulating layer such as a gate insulating layer that is in contact with a metal oxide layer or that is provided near a metal oxide layer is preferably an insulating layer having a region containing oxygen that is released by heating (hereinafter, may be referred to as excess oxygen). For example, an insulating layer having a region containing excess oxygen is in contact with a metal oxide layer or is located near the metal oxide layer, whereby oxygen vacancies in the metal oxide layer can be reduced. Examples of insulating layers that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0248] Since the insulating layer 110 functions as an interlayer insulating layer, it is preferable that the insulating layer 110 has a low relative dielectric constant. By using a material with a low relative dielectric constant for the interlayer insulating layer, the parasitic capacitance generated between wirings can be reduced. Silicon oxide and silicon oxynitride are both thermally stable, and therefore are suitable for the insulating layer 110.

[0249] In addition, the concentration of impurities such as water and hydrogen in the insulating layer 110 is preferably reduced. This can prevent impurities such as water and hydrogen from entering a channel formation region of the semiconductor layer 130, for example.

[0250] In addition, a barrier insulating layer against hydrogen is preferably used as the insulating layer 110. When the insulating layer 110 provided on the outside of the semiconductor layer 130 has a barrier property against hydrogen, diffusion of hydrogen into the semiconductor layer 130, for example, can be suppressed.

[0251] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0252] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that has low permeability of a corresponding substance, or a function of suppressing the diffusion of a corresponding substance). Note that hydrogen when described as a corresponding substance includes, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. - In addition, impurities when described as a corresponding substance refer to impurities in the channel formation region or the semiconductor layer unless otherwise specified, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. In addition, oxygen when described as a corresponding substance refers to at least one of, for example, oxygen atoms, oxygen molecules, etc.

[0253] For example, it is preferable to use a silicon nitride film as the insulating layer 110.

[0254] The insulating layer 180 and the insulating layer 280 preferably have the above-mentioned barrier insulating layer against hydrogen. The insulating layer 180 is provided so as to surround the semiconductor layer 130. The insulating layer 280 is provided so as to surround the semiconductor layer 230. The insulating layer 180 provided on the outside of the semiconductor layer 130 has a barrier property against hydrogen, so that the diffusion of hydrogen into the semiconductor layer 130 can be suppressed. Similarly, the insulating layer 280 provided on the outside of the semiconductor layer 230 has a barrier property against hydrogen, so that the diffusion of hydrogen into the semiconductor layer 230 can be suppressed. For example, the insulating layer 180 and the insulating layer 280 preferably have one or both of an aluminum oxide film and a silicon nitride film.

[0255] Silicon nitride also has a barrier property against oxygen. Therefore, by using silicon nitride for the insulating layer 180, oxygen is extracted from the semiconductor layer 130, and it is possible to suppress the formation of an excessive amount of oxygen vacancies in the semiconductor layer 130. Similarly, by using silicon nitride for the insulating layer 280, it is possible to suppress the formation of an excessive amount of oxygen vacancies in the semiconductor layer 230, and it is possible to suppress the formation of an excessive amount of oxygen vacancies in the semiconductor layer 230.

[0256] Furthermore, by using silicon nitride for the insulating layer 180, excess oxygen can be prevented from being supplied to the semiconductor layer 130. Therefore, excess oxygen can be prevented from being contained in the channel formation region of the semiconductor layer 130, which can improve the reliability of the transistor 13. Similarly, by using silicon nitride for the insulating layer 280, the reliability of the transistor 11 can be improved.

[0257] Each of the insulating layers 180 and 280 preferably includes the above-described insulating oxide insulating film, the oxynitride insulating film, or the insulating layer including a region containing excess oxygen.

[0258] For example, an insulating layer having a region containing excess oxygen can be formed by deposition using a sputtering method in an atmosphere containing oxygen. In addition, by using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulating layer 180 and the insulating layer 280 can be reduced. By depositing at least a part of the layers constituting the insulating layer 180 in this manner, oxygen can be supplied from the insulating layer 180 to the channel formation region of the semiconductor layer 130, thereby reducing oxygen vacancies and VoH. In addition, by depositing at least a part of the layers constituting the insulating layer 280, oxygen can be supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 230, thereby reducing oxygen vacancies and VoH.

[0259] The concentrations of impurities such as water and hydrogen are preferably reduced in the insulating layer 180 and the insulating layer 280. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the semiconductor layer 130 and the channel formation region of the semiconductor layer 230.

[0260] Since the thickness of the insulating layer 180 on the conductive layer 120 corresponds to the channel length of the transistor 13, the thickness of the insulating layer 180 is appropriately set in accordance with the design value of the channel length of the transistor 13. Similarly, since the thickness of the insulating layer 280 on the conductive layer 220 corresponds to the channel length of the transistor 11, the thickness of the insulating layer 280 is appropriately set in accordance with the design value of the channel length of the transistor 11.

[0261] For example, a single-layer structure of a silicon nitride film, a silicon nitride oxide film, or an aluminum oxide film is preferably used as the insulating layer 180 and the insulating layer 280. Alternatively, for example, a three-layer structure in which a silicon nitride film, a silicon oxide film, and a silicon nitride film are stacked in this order is preferably used as the insulating layer 180 and the insulating layer 280. For example, a three-layer structure in which an aluminum oxide film, a silicon oxide film, and an aluminum oxide film are stacked in this order is preferably used as the insulating layer 180 and the insulating layer 280.

[0262] The insulating layer 150 and the insulating layer 250 preferably have a function of capturing hydrogen and fixing hydrogen. This can reduce the hydrogen concentration in the semiconductor layer 130 and the semiconductor layer 230 (particularly, the hydrogen concentration in the channel formation region of the transistor). Therefore, the V O By reducing H, the channel formation region can be made i-type or substantially i-type.

[0263] Examples of materials for the insulating layer having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, and examples include oxides containing hafnium and zirconium. Here, in metal oxides having an amorphous structure, some oxygen atoms have dangling bonds, so that they have a high ability to capture or fix hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, the amorphous structure may be realized by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Note that the metal oxide may have one or both of a crystalline region and a crystal grain boundary in a part.

[0264] The function of capturing or fixing a corresponding substance can also be said to have a property that makes it difficult for the corresponding substance to diffuse. Therefore, the function of capturing or fixing a corresponding substance can be rephrased as a barrier property.

[0265] In the case where the gate insulating layer has a stacked structure, it is preferable that a layer in contact with the semiconductor layer 130 and a layer in contact with the semiconductor layer 230 have a function of capturing hydrogen and fixing hydrogen. This makes it possible to more effectively capture or fix hydrogen contained in the semiconductor layer 130 and the semiconductor layer 230. Thus, the hydrogen concentrations in the semiconductor layer 130 and the semiconductor layer 230 can be reduced. For example, hafnium silicate or the like is preferably used as the layer of the insulating layer 150 in contact with the semiconductor layer 130 and the layer of the insulating layer 250 in contact with the semiconductor layer 230. In addition, it is preferable that the layer has an amorphous structure.

[0266] By making the layer have an amorphous structure, the formation of crystal grain boundaries can be suppressed. By suppressing the formation of crystal grain boundaries, the flatness of the layer can be improved. This makes the film thickness distribution of the insulating layer 150 and the insulating layer 250 uniform, and the area where the film thickness is extremely thin can be reduced. This makes it possible to improve the withstand voltage of the insulating layer 150 and the insulating layer 250. In addition, the film thickness distribution of the film provided on the insulating layer 150 and the insulating layer 250 can be made uniform.

[0267] Moreover, by suppressing the formation of grain boundaries in the layer, leakage current caused by defect levels in the grain boundaries can be reduced, so that the insulating layer 150 and the insulating layer 250 can function as insulating films with low leakage current.

[0268] In addition, hafnium oxide is a high dielectric constant (high-k) material, so hafnium silicate can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when hafnium oxide or hafnium silicate is used for the gate insulating layer, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating layer. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0269] In view of the above, it is preferable to use an oxide containing one or both of aluminum and hafnium for insulating layer 150 and insulating layer 250, it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and it is even more preferable to use aluminum oxide having an amorphous structure.

[0270] In addition, it is preferable to use the above-mentioned barrier insulating layer against hydrogen as the insulating layer 150 and the insulating layer 250. By using a barrier insulating layer against hydrogen as the insulating layer 150, it is possible to suppress the diffusion of impurities contained in the conductive layer 220 to the semiconductor layer 130. Similarly, by using a barrier insulating layer against hydrogen as the insulating layer 250, it is possible to suppress the diffusion of impurities contained in the conductive layer 220 to the semiconductor layer 230. For example, silicon nitride has high barrier properties against hydrogen, and is therefore suitable as the insulating layer 150 and the insulating layer 250. Furthermore, the insulating layer 150 and the insulating layer 250 may have an insulating layer having a structure stable against heat, such as silicon oxide or silicon oxynitride.

[0271] With such a structure, a semiconductor device having good electrical characteristics, a highly reliable semiconductor device, a semiconductor device with less variation in the electrical characteristics of the transistors, and a semiconductor device with a large on-current can be provided.

[0272] Additionally, the insulating layer 150 and the insulating layer 250 may comprise an insulating layer having a thermally stable structure, such as silicon oxide or silicon oxynitride.

[0273] Furthermore, the insulating layer 150 and the insulating layer 250 may have an insulating layer having a thermally stable structure between a pair of insulating layers having the function of capturing and fixing hydrogen.

[0274] Furthermore, the insulating layer 150 and the insulating layer 250 preferably have a barrier insulating layer against oxygen. This can suppress oxidation of the conductive layer 140, the conductive layer 141, the conductive layer 220, the conductive layer 240, the conductive layer 260, and the like. When the insulating layer 150 and the insulating layer 250 have a stacked structure, a layer in contact with the conductive layer 140 or the conductive layer 240 is preferably a barrier insulating layer against oxygen. In particular, among the layers constituting the insulating layer 150 and the insulating layer 250, a layer in contact with the conductive layer 140, a layer in contact with the conductive layer 220, a layer in contact with the conductive layer 240, and a layer in contact with the conductive layer 260 are preferably barrier insulating layers against oxygen.

[0275] By using a barrier insulating layer against hydrogen and oxygen for the layer of the insulating layer 150 that is in contact with the conductive layer 220, it is possible to suppress oxidation of the conductive layer 220. In addition, it is possible to suppress the formation of oxygen vacancies in the semiconductor layer 130 due to the diffusion of oxygen contained in the semiconductor layer 130 into the conductive layer 220. Similarly, by using a barrier insulating layer against hydrogen and oxygen for the layer of the insulating layer 250 that is in contact with the conductive layer 260, it is possible to suppress oxidation of the conductive layer 260. In addition, it is possible to suppress the formation of oxygen vacancies in the semiconductor layer 230 due to the diffusion of oxygen contained in the semiconductor layer 230 into the conductive layer 260.

[0276] Examples of the barrier insulating layer against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate).

[0277] The layers in the insulating layer 150 that are in contact with the conductive layer 140 and the conductive layer 141 are preferably less permeable to oxygen than at least the insulating layer 180. When the layers have a barrier property against oxygen, the side surfaces of the conductive layer 140 can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 13. In addition, the conductive layer 141 can be prevented from being oxidized and an oxide film can be prevented from being formed.

[0278] Similarly, the layer in the insulating layer 250 that is in contact with the conductive layer 240 is preferably less permeable to oxygen than at least the insulating layer 280. The layer has a barrier property against oxygen, which can prevent the side surface of the conductive layer 240 from being oxidized and an oxide film from being formed on the side surface. This can prevent a decrease in the on-state current or the field-effect mobility of the transistor 11.

[0279] Moreover, each layer constituting the insulating layer 150 and the insulating layer 250 is preferably a thin film. For example, the insulating layer 150 and the insulating layer 250 each have a thickness of 1 nm to 20 nm, preferably 3 nm to 10 nm, so that the subthreshold swing value (also called S value), which is one of the transistor characteristics, can be reduced. Note that the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude with the drain voltage being constant in the subthreshold region.

[0280] Furthermore, the thickness of each layer constituting insulating layer 150 and insulating layer 250 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less.

[0281] In addition, it is preferable to use a three-layer structure in which a first insulating layer having a material with a low relative dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the semiconductor layer 130 side and the semiconductor layer 230 side, respectively, as the insulating layer 150 and the insulating layer 250. As a material with a low relative dielectric constant of the first insulating layer, it is preferable to use silicon oxide or silicon oxynitride. The first insulating layer is a layer in contact with the semiconductor layer 130 or the semiconductor layer 230. By using an oxide for the first insulating layer, oxygen can be supplied to the semiconductor layer 130 and the semiconductor layer 230. In addition, by providing the third insulating layer, it is possible to suppress the diffusion of oxygen contained in the first insulating layer to the conductive layer 220 and the conductive layer 260, and to suppress the oxidation of the conductive layer 220 and the conductive layer 260. In addition, it is possible to suppress a decrease in the amount of oxygen supplied from the first insulating layer to the semiconductor layer 130 and the semiconductor layer 230.

[0282] For the insulating layer 150 and the insulating layer 250, a four-layer structure is preferably used in which a fourth insulating layer having a barrier property against oxygen, a first insulating layer having a material with a low relative dielectric constant, a second insulating layer having a function of capturing or fixing hydrogen, and a third insulating layer having a barrier property against hydrogen and oxygen are stacked in this order from the semiconductor layer 130 side and the semiconductor layer 230 side, respectively. The first insulating layer to the third insulating layer can have a similar structure to that used in the above-mentioned three-layer structure. The fourth insulating layer is a layer in contact with the semiconductor layer 130 or the semiconductor layer 230. The fourth insulating layer has a barrier property against oxygen, so that oxygen can be suppressed from being released from the semiconductor layer 130 and the semiconductor layer 230. For example, aluminum oxide may be used as the fourth insulating layer. Aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the fourth insulating layer in contact with the semiconductor layer 130 or the semiconductor layer 230.

[0283] Typically, the thicknesses of the fourth insulating layer, the first insulating layer, the second insulating layer, and the third insulating layer are 1 nm, 2 nm, 2 nm, and 1 nm, respectively. With such a structure, the transistor can have good electrical characteristics even when miniaturized or highly integrated.

[0284] It is preferable to use a barrier insulating layer against hydrogen for the insulating layer 283. This can suppress diffusion of hydrogen from above the insulating layer 283 to, for example, the semiconductor layer 230. A silicon nitride film and a silicon nitride oxide film each have the characteristics of releasing little impurities (for example, water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulating layer 283.

[0285] It is particularly preferable to use silicon nitride formed by a sputtering method as the insulating layer 283. The sputtering method does not require the use of molecules containing hydrogen in the deposition gas, and therefore can reduce the hydrogen concentration in the insulating layer 283. Furthermore, by forming the insulating layer 283 by a sputtering method, silicon nitride with high density can be formed.

[0286] Moreover, an insulating layer having a function of capturing or fixing hydrogen may be used as the insulating layer 283. With such a structure, it is possible to suppress diffusion of hydrogen from above the insulating layer 283 to, for example, the semiconductor layer 230, and further to capture or fix hydrogen contained in the semiconductor layer 230. Therefore, for example, the hydrogen concentration in the semiconductor layer 230 can be reduced. As the insulating layer 283, aluminum oxide, hafnium oxide, hafnium silicate, or the like can be used.

[0287] Alternatively, the insulating layer 283 may have a stacked structure of an insulating layer having a function of capturing or fixing hydrogen and a barrier insulating layer against hydrogen. For example, the insulating layer 283 may be a stacked film of aluminum oxide and silicon nitride over the aluminum oxide.

[0288] Since the insulating layer 285 functions as an interlayer insulating layer, it is preferable to use the above-mentioned material having a low relative dielectric constant. For example, the insulating layer 285 preferably has a silicon oxide film.

[0289] [Conductive layer] For the conductive layers (conductive layer 120, conductive layer 121, conductive layer 140, conductive layer 141, conductive layer 220, conductive layer 240, conductive layer 260, conductive layer 265, etc.) included in the semiconductor device, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, an alloy combining the above-mentioned metal elements, etc. As the alloy containing the above-mentioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Also, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0290] In addition, conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum, conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel, and materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing oxygen diffusion, or materials that maintain conductivity even when oxygen is absorbed. Note that examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide to which silicon is added, indium zinc oxide (also referred to as IZO (registered trademark)), and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.

[0291] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0292] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0293] In addition, when a metal oxide is used for the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductive layer that functions as a gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0294] Since the conductive layer 120, the conductive layer 140, the conductive layer 220, and the conductive layer 240 are conductive layers in contact with the semiconductor layer 130 or the semiconductor layer 230, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, a metal oxide having conductivity (also referred to as an oxide conductor), or a conductive material that has a function of suppressing oxygen diffusion. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductive layer 120, the conductive layer 140, the conductive layer 220, and the conductive layer 240.

[0295] By using a conductive material containing oxygen as the conductive layer 120, the conductive layer 140, the conductive layer 220, or the conductive layer 240, the conductivity can be maintained even if the conductive layer 120, the conductive layer 140, the conductive layer 220, or the conductive layer 240 absorbs oxygen. In addition, even when an insulating layer containing oxygen such as hafnium oxide is used as the insulating layer 110, the conductive layer 120 is preferable because it can maintain its conductivity. For each of the conductive layer 120, the conductive layer 140, the conductive layer 220, and the conductive layer 240, it is preferable to use, for example, ITO, ITSO, IZO (registered trademark), or the like.

[0296] 3A shows an example in which the conductive layer 120 has a three-layer structure of a conductive layer 120a1, a conductive layer 120a2 on the conductive layer 120a1, and a conductive layer 120b on the conductive layer 120a2. Specifically, the conductive layer 120a has a two-layer structure of a conductive layer 120a1 and a conductive layer 120a2 on the conductive layer 120a1. Also, FIG. 3A shows an example in which the conductive layer 121 has a three-layer structure of a conductive layer 121a1, a conductive layer 121a2 on the conductive layer 121a1, and a conductive layer 121b on the conductive layer 121a2. Specifically, the conductive layer 121a has a two-layer structure of a conductive layer 121a1 and a conductive layer 121a2 on the conductive layer 121a1. 3A shows an example in which the conductive layer 220 has a three-layer structure including a conductive layer 220a1, a conductive layer 220a2 on the conductive layer 220a1, and a conductive layer 220b on the conductive layer 220a2. Specifically, the conductive layer 220b has a two-layer structure including a conductive layer 220a2 and a conductive layer 220b on the conductive layer 220a2.

[0297] For example, it is preferable to use a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the conductive layer 120a1 and the conductive layer 220a1, a material with high conductivity as the conductive layer 120a2 and the conductive layer 220a2, and a conductive material containing oxygen (more preferably an oxide conductor) as the conductive layer 120b and the conductive layer 220b. Specifically, it is preferable to use titanium nitride as the conductive layer 120a1 and the conductive layer 220a1, tungsten as the conductive layer 120a2 and the conductive layer 220a2, and an oxide conductor (for example, ITO, ITSO, or IZO (registered trademark)) as the conductive layer 120b and the conductive layer 220b.

[0298] In this case, in the conductive layer 120, titanium nitride is in contact with the insulating layer 110, and the oxide conductor is in contact with the semiconductor layer 130. In the conductive layer 220, the oxide conductor is in contact with the semiconductor layer 230. Furthermore, an oxide conductor is used in the layers closest to the channel formation regions of the semiconductor layer 130 and the semiconductor layer 230. Compared to tungsten, the oxide conductor has a lower contact resistance with the semiconductor layer 130 and the semiconductor layer 230, and therefore the current path between the source and drain can be shortened, and the on-current of the transistor can be increased.

[0299] With such a structure, the conductive layer 120 can maintain its conductivity even when in contact with the semiconductor layer 130. Furthermore, the conductive layer 220 can maintain its conductivity even when in contact with the semiconductor layer 230. Furthermore, when an oxide insulating layer is used for the insulating layer 110, the insulating layer 110 can suppress excessive oxidation of the conductive layer 120. Furthermore, by using a metal material (here, tungsten) having higher conductivity than an oxide conductor and titanium nitride as the conductive layer 120a2 and the conductive layer 220a2, the conductivity of the conductive layer 120 and the conductive layer 220 can be increased. Note that the conductive layer 121 can be formed in parallel with the conductive layer 120, which will be described in detail later. Specifically, the conductive layer 120 and the conductive layer 121 can be formed by processing the same conductive film. Therefore, the conductive layer 121a1, the conductive layer 121a2, and the conductive layer 121b can have the same material as the conductive layer 120a1, the conductive layer 120a2, and the conductive layer 120b, respectively.

[0300] FIG. 3A shows an example in which the conductive layer 140 has a two-layer structure of a conductive layer 140a and a conductive layer 140b on the conductive layer 140a. FIG. 3A also shows an example in which the conductive layer 240 has a two-layer structure of a conductive layer 240a and a conductive layer 240b on the conductive layer 240a. In this case, for example, it is preferable to use a conductive material containing oxygen for the conductive layer 140a and the conductive layer 240a, and to use a material having higher conductivity than the conductive layer 140a and the conductive layer 240a for the conductive layer 140b and the conductive layer 240b. Specifically, for example, it is preferable to use an oxide conductor (for example, ITO, ITSO, or IZO (registered trademark)) for the conductive layer 140a and the conductive layer 240a, and to use ruthenium, tungsten, titanium nitride, or tantalum nitride for the conductive layer 140b and the conductive layer 240b.

[0301] The conductive layer 141 and the conductive layer 260 are preferably made of a material having high conductivity, such as tungsten. In addition, the conductive layer 260 is preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen. As described above, examples of the conductive material include a conductive material containing nitrogen (for example, titanium nitride or tantalum nitride) and a conductive material containing oxygen (for example, ruthenium oxide). This can suppress a decrease in the conductivity of the conductive layer 260.

[0302] In addition, the conductive layer 260 is preferably made of a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed. Alternatively, the conductive material containing the above-mentioned metal element and nitrogen (for example, titanium nitride, tantalum nitride, etc.) may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an outer insulating layer or the like may be captured.

[0303] 3A shows an example in which the conductive layer 260 has a two-layer structure including a conductive layer 260a and a conductive layer 260b over the conductive layer 260a. In this case, for example, it is preferable to use titanium nitride as the conductive layer 260a and tungsten as the conductive layer 260b. Alternatively, it is preferable to use tantalum nitride as the conductive layer 260a and copper as the conductive layer 260b. With such a structure, the conductivity of the conductive layer 260 can be increased.

[0304] The conductive layer 260 may also have a stacked structure of three or more layers. For example, the conductive layer 260 may have a three-layer structure of tantalum nitride, titanium nitride on the tantalum nitride, and tungsten on the titanium nitride.

[0305] The conductive layer 265 preferably has high conductivity because it functions as a gate wiring. Tungsten is preferably used for the conductive layer 265. The conductive layer 265 may have a structure similar to that of the conductive layer 260. For example, a two-layer structure of titanium nitride and tungsten may be used.

[0306] [substrate] As the substrate on which the transistor is formed, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (for example, an yttria stabilized zirconia substrate), and a resin substrate can be used. As the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be used. Furthermore, there is a semiconductor substrate having an insulating region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. As the conductive substrate, there is a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there is a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there is a substrate in which a conductor or semiconductor is provided on an insulating substrate, a substrate in which a conductor or insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or insulator is provided on a conductive substrate, and the like. Alternatively, a substrate on which an element is provided on these substrates may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0307] <Configuration Example 2 of Semiconductor Device> The structure of a semiconductor device according to another embodiment of the present invention will be described below. Specifically, a modified example of the memory cell 10 will be described. In the following, examples of structures different from those shown in FIGS. 1B to 3B will be mainly described, and descriptions of similar examples of structures will be omitted as appropriate.

[0308] [Memory cell 10A] 5(A), 5(B), 6(A), and 6(B) are diagrams showing a configuration example of a memory cell 10A. FIG. 5(A) shows a planar configuration example of a transistor 13A and a capacitor 15A. FIG. 5(B) shows a cross-sectional configuration example between dashed lines A1-A2 shown in FIG. 5(A). FIG. 6(A) shows a cross-sectional configuration example between dashed lines B1-B2 shown in FIG. 5(A). FIG. 6(B) shows a cross-sectional configuration example between dashed lines B3-B4 shown in FIG. 5(A). Here, the transistor 11, the transistor 13, and the capacitor 15 of the memory cell 10A are respectively referred to as a transistor 11A, a transistor 13A, and a capacitor 15A. Also, for a planar configuration example of the transistor 11A, the planar configuration example of the transistor 11 shown in FIG. 1(C) can be referred to.

[0309] The memory cell 10A has an insulating layer 183 on the insulating layer 180, and an insulating layer 185 on the insulating layer 183. The insulating layer 183 and the insulating layer 185 function as interlayer insulating layers.

[0310] The transistor 13A has a conductive layer 120, a conductive layer 140 on an insulating layer 180, a semiconductor layer 130 having a region overlapping with the conductive layer 120, an insulating layer 153 on the semiconductor layer 130, and a conductive layer 123 on the insulating layer 153. The capacitor 15A has a conductive layer 141 having a region overlapping with the conductive layer 121, an insulating layer 154 on the conductive layer 141, and a conductive layer 124 on the insulating layer 154. The transistor 11A has a conductive layer 225, a conductive layer 240 on an insulating layer 280, a semiconductor layer 230 having a region overlapping with the conductive layer 225, an insulating layer 250 on the semiconductor layer 230, and a conductive layer 260 on the insulating layer 250.

[0311] The conductive layer 123 functions as a gate electrode of the transistor 13A. The conductive layer 141 functions as one of a pair of electrodes of the capacitor 15A. The conductive layer 124 functions as the other of the pair of electrodes of the capacitor 15A. The conductive layer 225 functions as a gate wiring electrically connected to the conductive layers 123 and 124 and one of the source electrode and drain electrode of the transistor 11A.

[0312] At least some of the components of the transistor 13A are disposed inside the opening 190. Specifically, the semiconductor layer 130, the insulating layer 153, and the conductive layer 123 are disposed such that at least a portion of each of them is located inside the opening 190.

[0313] The insulating layer 153 has a region located inside the opening 190 and on the inner side of the semiconductor layer 130. The conductive layer 123 has a region inside the opening 190 facing the semiconductor layer 130 with the insulating layer 153 sandwiched therebetween.

[0314] A region of the insulating layer 153 disposed inside the opening 190 is provided to reflect the shapes of the recess 191 and the opening 190. Specifically, the semiconductor layer 130 is provided so as to cover the bottom and side surfaces of the recess 191 and the sidewall of the opening 190. The insulating layer 153 is also provided so as to cover a portion of the semiconductor layer 130. Then, the conductive layer 123 is provided so as to fill at least a portion of the recess of the insulating layer 153.

[0315] At least a part of a region of the semiconductor layer 130 in contact with the insulating layer 180 functions as a channel formation region of the transistor 13A. As described above, the semiconductor layer 130 can be provided along the side wall of the opening 190 provided in the insulating layer 180. As described above, the channel of the transistor 13A can be formed along the side wall of the opening 190.

[0316] At least some of the components of the capacitor 15A are disposed inside the opening 192. Specifically, the conductive layer 141, the insulating layer 154, and the conductive layer 124 are disposed such that at least a portion of each of them is located inside the opening 192.

[0317] The insulating layer 154 has a region located inside the opening 192 and on the inner side of the conductive layer 141. The conductive layer 124 has a region inside the opening 192 facing the conductive layer 141 with the insulating layer 154 sandwiched therebetween.

[0318] A region of insulating layer 154 disposed inside opening 192 is provided to reflect the shapes of recess 193 and opening 192. Specifically, conductive layer 141 is provided so as to cover the bottom and side surfaces of recess 193 and the sidewall of opening 192. Insulating layer 154 is also provided so as to cover a portion of conductive layer 141. Then, conductive layer 124 is provided so as to fill at least a portion of the recess of insulating layer 154.

[0319] 5(B) and 6(A), the insulating layer 185 has a region overlapping with the conductive layer 141 with the insulating layer 183 interposed therebetween. Also, as shown in FIG. 5(B) and 6(B), the insulating layer 185 has a region overlapping with the conductive layer 140 with the insulating layer 183 and the semiconductor layer 130 interposed therebetween.

[0320] The insulating layer 185 has an opening 170 that reaches the semiconductor layer 130 at a position overlapping with the opening 190. At least a portion of the components of the transistor 13A is disposed inside the opening 170. Specifically, the insulating layer 153 and the conductive layer 123 are disposed such that at least a portion of each of them is located inside the opening 170. The insulating layer 183 covers the upper surface and side surfaces of the semiconductor layer 130 and the side surfaces of the conductive layer 140. The insulating layer 153 contacts the insulating layer 183 inside the opening 170. The opening 170 may be provided in the insulating layer 183.

[0321] A region of insulating layer 153 that is disposed inside opening 170 is provided to reflect the shape of opening 170. Specifically, insulating layer 183 is provided so as to cover the sidewall of opening 170 (the side surface of insulating layer 185), and insulating layer 153 is provided inside insulating layer 183. Then, conductive layer 123 is provided so as to fill at least a portion of the recess of insulating layer 153 that reflects the shape of opening 170.

[0322] In the transistor 13A, the conductive layer 123 does not overlap with the top surface of the conductive layer 140. Therefore, the transistor 13A can have a smaller parasitic capacitance between the gate electrode and the other of the source electrode and the drain electrode than the transistor 13 shown in, for example, FIGS. 1B, 1D, and 2B. Therefore, the transistor 13A can have higher frequency characteristics than the transistor 13 shown in, for example, FIGS. 1B, 1D, and 2B. Therefore, a semiconductor device including the memory cell 10A can be driven at a higher speed than the semiconductor device shown in, for example, FIGS. 1B to 2B. On the other hand, a semiconductor device including the transistor 13 shown in, for example, FIGS. 1D and 2B can have a smaller number of manufacturing steps than a semiconductor device including the transistor 13A. Therefore, the manufacturing cost can be reduced, and a low-cost semiconductor device can be obtained.

[0323] The insulating layer 185 has an opening 172 that reaches the conductive layer 141 at a position overlapping the opening 192. At least some of the components of the capacitor 15A are disposed inside the opening 172. Specifically, the insulating layer 154 and the conductive layer 124 are disposed such that at least some of them are located inside the opening 172. The insulating layer 183 covers the upper surface and side surfaces of the conductive layer 141. The insulating layer 154 contacts the insulating layer 183 inside the opening 172. The opening 172 may be provided in the insulating layer 183.

[0324] A region of insulating layer 154 that is disposed inside opening 172 is provided to reflect the shape of opening 172. Specifically, insulating layer 183 is provided to cover the sidewall of opening 172 (the side surface of insulating layer 185), and insulating layer 154 is provided inside insulating layer 183. Then, conductive layer 124 is provided to fill at least a portion of the recess of insulating layer 154 that reflects the shape of opening 172.

[0325] As will be described in detail later, the opening 170 and the opening 172 can be formed in parallel. Also, the insulating layer 153 and the insulating layer 154 can be formed in parallel. Furthermore, the conductive layer 123 and the conductive layer 124 can be formed in parallel.

[0326] The heights of the top surfaces of the conductive layer 123, the conductive layer 124, and the insulating layer 185 are preferably the same or approximately the same. The conductive layer 225 is located on the insulating layer 185, the insulating layer 183, the insulating layer 153, the insulating layer 154, the conductive layer 123, and the conductive layer 124, and is in contact with the top surface of the conductive layer 123 and the top surface of the conductive layer 124. The conductive layer 225 can also be in contact with the top surface of the insulating layer 185, the top surface of the insulating layer 183, the top surface of the insulating layer 153, and the top surface of the insulating layer 154.

[0327] In memory cell 10A, an opening 290 reaching conductive layer 225 is provided in conductive layer 240 and insulating layer 280. A recess 291 is provided in conductive layer 225 at a position overlapping with opening 290. The bottom surface of recess 291 corresponds to the upper surface of conductive layer 225. The side surface of recess 291 corresponds to the side surface of conductive layer 225.

[0328] The insulating layer 153 and the insulating layer 154 can be formed using a material that can be used for one or both of the insulating layer 150 and the insulating layer 250. The conductive layer 123 and the conductive layer 124 can be formed using a material that can be used for the conductive layer 220, specifically, the conductive layer 220a. The conductive layer 123 and the conductive layer 124 can be formed using a material that can be used for the conductive layer 260. The insulating layer 183 can be formed using a material that can be used for the insulating layer 283. The insulating layer 185 can be formed using a material that can be used for the insulating layer 285. The conductive layer 225 can be formed using a material that can be used for the conductive layer 220, specifically, the conductive layer 220b. Note that the conductive layer 225 may have a stacked structure of two or more layers. The conductive layer 225 can be formed using a stacked structure of, for example, a layer using a material that can be used for the conductive layer 220a and a layer using a material that can be used for the conductive layer 220b on the layer.

[0329] [Memory cell 10B] 7(A), 7(B), and 7(C) are diagrams showing a configuration example of a memory cell 10B. FIG. 7(A) shows a planar configuration example of a transistor 11B. FIG. 7(B) shows a cross-sectional configuration example between dashed lines A1-A2 shown in FIG. 7(A). FIG. 7(C) shows a cross-sectional configuration example between dashed lines B1-B2 shown in FIG. 7(A). Here, the transistor 11, the transistor 13, and the capacitor 15 of the memory cell 10B are respectively referred to as a transistor 11B, a transistor 13B, and a capacitor 15B. In addition, the planar configuration example of the transistor 13B and the capacitor 15B can be referred to the planar configuration example of the transistor 13 and the capacitor 15 shown in FIG. 1(B).

[0330] In the memory cell 10B, the insulating layer 283 and the insulating layer 285 are not provided, and the insulating layer 250 is provided to cover the semiconductor layer 230 and the conductive layer 240. In addition, in the memory cell 10B, the conductive layer 260 is provided to have a region overlapping with the conductive layer 240 with the insulating layer 250 and the semiconductor layer 230 interposed therebetween. At least a part of the conductive layer 260 included in the memory cell 10B can function as the wiring 21 shown in FIG.

[0331] The number of manufacturing steps for a semiconductor device including the transistor 11B can be reduced compared to the semiconductor device including the transistor 11 shown in, for example, Figures 1C, 1D, and 2A. Thus, the manufacturing cost can be reduced, and a low-cost semiconductor device can be obtained. On the other hand, the parasitic capacitance between the gate electrode and the other of the source electrode and the drain electrode of the transistor 11 shown in, for example, Figures 1C, 1D, and 2A can be reduced compared to the transistor 11B.

[0332] [Memory cell 10C] 8(A) and 8(B) are diagrams showing a configuration example of a memory cell 10C. FIG. 8(A) is a cross-sectional view taken along dashed line A1-A2 in FIG. 7(A). FIG. 8(B) is a cross-sectional view taken along dashed line B1-B2 in FIG. 7(A). Here, the transistor 11, the transistor 13, and the capacitor 15 in the memory cell 10C are respectively referred to as a transistor 11C, a transistor 13C, and a capacitor 15C. For a planar configuration example of the transistor 13C and the capacitor 15C, refer to the planar configuration example of the transistor 13 and the capacitor 15 shown in FIG. 1(B).

[0333] The memory cell 10C does not have the conductive layer 265. In the memory cell 10C, the insulating layer 250 has a region located inside the opening 270, a region located on the insulating layer 283, and a region located on the insulating layer 285. Furthermore, the conductive layer 260 has a region located inside the opening 270, a region located on the insulating layer 283, and a region located on the insulating layer 285.

[0334] In the memory cell 10C, the conductive layer 260 has a region overlapping with a top surface of the conductive layer 240, and the insulating layer 250, the insulating layer 283, and the insulating layer 285 are located between the conductive layer 240 and the conductive layer 260. Therefore, the transistor 11C can have a smaller parasitic capacitance between the gate electrode and the other of the source electrode and the drain electrode than the transistor 11B shown in FIGS. 7A to 7C. On the other hand, the semiconductor device including the memory cell 10B shown in FIGS. 7A to 7C can have a smaller number of manufacturing steps than the semiconductor device including the memory cell 10C. Therefore, the manufacturing cost can be reduced, and a low-cost semiconductor device can be obtained.

[0335] [Memory cell 10D] 9(A), 9(B), and 9(C) are diagrams showing a configuration example of a memory cell 10D. FIG. 9(A) is a cross-sectional view taken along dashed lines A1-A2 in FIG. 1(B) and FIG. 1(C). FIG. 9(B) is a cross-sectional view taken along dashed lines B1-B2 in FIG. 1(B) and FIG. 1(C). FIG. 9(C) is a cross-sectional view taken along dashed lines B3-B4 in FIG. 1(B) and FIG. 1(C). Here, the transistor 11, the transistor 13, and the capacitor 15 included in the memory cell 10D are respectively referred to as a transistor 11D, a transistor 13D, and a capacitor 15D.

[0336] The transistor 13D has a conductive layer 155 and an insulating layer 181. The transistor 11D has a conductive layer 255 and an insulating layer 281. In the memory cell 10D, the insulating layer 180 has a two-layer structure of an insulating layer 180a and an insulating layer 180b over the insulating layer 180a. In the memory cell 10D, the insulating layer 280 has a two-layer structure of an insulating layer 280a and an insulating layer 280b over the insulating layer 280a.

[0337] In the transistor 13D, the conductive layer 155 is located on the insulating layer 180a. The insulating layer 180b covers the top and side surfaces of the conductive layer 155. In the transistor 11D, the conductive layer 255 is located on the insulating layer 280a. The insulating layer 280b covers the top and side surfaces of the conductive layer 255.

[0338] An opening 190 is provided in the conductive layer 155. In the memory cell 10D, the opening 190 includes an opening in the insulating layer 180a, an opening in the conductive layer 155, an opening in the insulating layer 180b, and an opening in the conductive layer 140. In other words, an opening in a region where the insulating layer 180a overlaps with the conductive layer 120 is a part of the opening 190, an opening in a region where the conductive layer 155 overlaps with the conductive layer 120 is another part of the opening 190, an opening in a region where the insulating layer 180b overlaps with the conductive layer 120 is another part of the opening 190, and an opening in a region where the conductive layer 140 overlaps with the conductive layer 120 is another part of the opening 190.

[0339] In addition, in memory cell 10D, opening 290 includes an opening in insulating layer 280a, an opening in conductive layer 255, an opening in insulating layer 280b, and an opening in conductive layer 240. In other words, an opening in a region where insulating layer 280a overlaps with conductive layer 220 is a part of opening 290, an opening in a region where conductive layer 255 overlaps with conductive layer 220 is another part of opening 290, an opening in a region where insulating layer 280b overlaps with conductive layer 220 is another part of opening 290, and an opening in a region where conductive layer 240 overlaps with conductive layer 220 is another part of opening 290.

[0340] The insulating layer 181 is located inside the opening 190. The insulating layer 181 can be provided along the side wall of the opening 190. Inside the opening 190, the insulating layer 181 can have a region in contact with the upper surface of the conductive layer 120 (the bottom surface of the recess 191), a region in contact with the side surface of the conductive layer 120 (the side surface of the recess 191), a region in contact with the side surface of the insulating layer 180a, a region in contact with the side surface of the conductive layer 155, a region in contact with the side surface of the insulating layer 180b, and a region in contact with the side surface of the conductive layer 140. The semiconductor layer 130 is provided so as to have a region in contact with the upper surface of the conductive layer 120 (the bottom surface of the recess 191) and a region in contact with the upper surface of the conductive layer 140, and a region located inside the insulating layer 181. The semiconductor layer 130 is provided so as to cover the side surface of the insulating layer 181 inside the opening 190.

[0341] The insulating layer 281 is located inside the opening 290. The insulating layer 281 can be provided along the side wall of the opening 290. Inside the opening 290, the insulating layer 281 can have a region in contact with the upper surface of the conductive layer 220 (the bottom surface of the recess 291), a region in contact with the side surface of the conductive layer 220 (the side surface of the recess 291), a region in contact with the side surface of the insulating layer 280a, a region in contact with the side surface of the conductive layer 255, a region in contact with the side surface of the insulating layer 280b, and a region in contact with the side surface of the conductive layer 240. The semiconductor layer 230 is provided so as to have a region in contact with the upper surface of the conductive layer 220 (the bottom surface of the recess 291) and a region in contact with the upper surface of the conductive layer 240, and a region located inside the insulating layer 281. The semiconductor layer 230 is provided so as to cover the side surface of the insulating layer 281 inside the opening 290.

[0342] The conductive layer 155 and the semiconductor layer 130 have an area facing each other with the insulating layer 181 sandwiched therebetween. The conductive layer 255 and the semiconductor layer 230 have an area facing each other with the insulating layer 281 sandwiched therebetween. The conductive layer 155 and the conductive layer 220 have an area facing each other with the insulating layer 181, the semiconductor layer 130, and the insulating layer 150 located inside the opening 190 sandwiched therebetween. The conductive layer 255 and the conductive layer 260 have an area facing each other with the insulating layer 281, the semiconductor layer 230, and the insulating layer 250 located inside the opening 290 sandwiched therebetween.

[0343] The conductive layer 155 functions as a backgate electrode of the transistor 13D. The insulating layer 181 functions as a backgate insulating layer of the transistor 13D. The conductive layer 255 functions as a backgate electrode of the transistor 11D. The insulating layer 281 functions as a backgate insulating layer of the transistor 11D. The transistor 11D and the transistor 13D each have a backgate electrode, which makes it easy to control the threshold voltage and suppresses fluctuation in the threshold voltage. Thus, the transistor 11D and the transistor 13D can have high electrical characteristics and reliability. Note that the insulating layer 181 and the insulating layer 281 may be referred to as a sidewall, a sidewall insulating layer, a sidewall protective layer, or the like.

[0344] The conductive layer 155 and the conductive layer 255 can be formed using, for example, a material that can be used for the conductive layer 260. The insulating layer 181 and the insulating layer 281 can be formed using, for example, a material that can be used for the insulating layer 283.

[0345] The insulating layer 181 can be formed by forming an insulating film to cover the opening 190 after forming the opening 190, and then performing anisotropic etching on the insulating film. The anisotropic etching can be performed, for example, until the upper surfaces of the conductive layer 120 and the conductive layer 140 are exposed. The insulating layer 281 can be formed by forming an insulating film to cover the opening 290 after forming the opening 290, and then performing anisotropic etching on the insulating film. The anisotropic etching can be performed, for example, until the upper surfaces of the conductive layer 220 and the conductive layer 240 are exposed.

[0346] When the insulating layer 181 and the insulating layer 281 are formed using anisotropic etching, the insulating layer 181 and the insulating layer 281 can be formed without performing pattern formation using, for example, a lithography method. Therefore, the insulating layer 181 and the insulating layer 281 can be formed without considering the alignment accuracy of the mask. Therefore, even if the opening 190 is miniaturized, it is possible to prevent the insulating layer 181 from not being formed inside the opening 190. Similarly, even if the opening 290 is miniaturized, it is possible to prevent the insulating layer 281 from not being formed inside the opening 290. As described above, since the opening 190 and the opening 290 can be miniaturized, the memory cell 10D can be a memory cell that occupies a smaller area in a plan view than when the insulating layer 181 and the insulating layer 281 are formed using, for example, a lithography method. Therefore, the memory cell 10D can be a miniaturized and highly integrated memory cell. As described above, a semiconductor device that can be miniaturized and highly integrated can be provided. Note that the insulating layer 181 and the insulating layer 281 may be formed by a lithography method.

[0347] [Memory cell 10DA] 10(A), 10(B), and 10(C) are diagrams showing a configuration example of a memory cell 10DA. FIG. 10(A) is a cross-sectional view taken along dashed line A1-A2 in FIG. 5(A). FIG. 10(B) is a cross-sectional view taken along dashed line B1-B2 in FIG. 5(A). FIG. 10(C) is a cross-sectional view taken along dashed line B3-B4 in FIG. 5(A). Here, the transistor 11, the transistor 13, and the capacitor 15 in the memory cell 10DA are referred to as a transistor 11DA, a transistor 13DA, and a capacitor 15DA, respectively.

[0348] The transistor 13DA is configured by providing a conductive layer 155 and an insulating layer 181 to the transistor 13A. The transistor 11DA is configured by providing a conductive layer 255 and an insulating layer 281 to the transistor 11A. Similarly to the memory cell 10D, the insulating layer 180 in the memory cell 10DA has a two-layer structure of an insulating layer 180a and an insulating layer 180b on the insulating layer 180a. The insulating layer 280 has a two-layer structure of an insulating layer 280a and an insulating layer 280b on the insulating layer 280a.

[0349] From the above, it can be said that memory cell 10DA has a configuration that combines the configuration of memory cell 10A and the configuration of memory cell 10D. In other words, memory cell 10DA can be said to be a memory cell in which the configuration of memory cell 10D is applied to memory cell 10A, or a memory cell in which the configuration of memory cell 10A is applied to memory cell 10D.

[0350] A semiconductor device having the memory cell 10DA can be a semiconductor device having a memory cell that operates at a higher speed and is miniaturized and highly integrated than the semiconductor device shown in Figures 1(B) to 2(B), for example. On the other hand, the number of manufacturing steps of the semiconductor device shown in Figures 1(B) to 2(B) can be reduced compared to the semiconductor device having the memory cell 10DA. Therefore, the manufacturing cost of the semiconductor device shown in Figures 1(B) to 2(B) can be reduced compared to the semiconductor device having the memory cell 10DA, and the semiconductor device can be a low-cost semiconductor device.

[0351] [Memory cell 10E] 11(A), 11(B), 11(C), 12(A), and 12(B) are diagrams showing an example of the configuration of a memory cell 10E. FIG. 11(A) shows an example of the planar configuration of a transistor 13E. FIG. 11(B) shows an example of the planar configuration of a transistor 11E and a capacitor 15E. FIG. 11(C) shows an example of a cross-sectional configuration between dashed lines A1-A2 shown in FIG. 11(A) and FIG. 11(B). FIG. 12(A) shows an example of a cross-sectional configuration between dashed lines B1-B2 shown in FIG. 11(A) and FIG. 11(B). FIG. 12(B) shows an example of a cross-sectional configuration between dashed lines B3-B4 shown in FIG. 11(A) and FIG. 11(B). Here, the transistor 11, the transistor 13, and the capacitor 15 of the memory cell 10E are respectively referred to as a transistor 11E, a transistor 13E, and a capacitor 15E.

[0352] In the memory cell 10E, the capacitor 15E is provided above the transistor 13E. For example, FIG. 11C shows an example in which the transistor 13E overlaps with the capacitor 15E. Note that the transistor 13E may overlap with the transistor 11E, or may overlap with a region between the transistor 11E and the capacitor 15E. In the memory cell 10E, the transistor 13E is provided so as to overlap with at least a part of the transistor 11E, the capacitor 15E, and a region between the transistor 11E and the capacitor 15E.

[0353] In the memory cell 10E, the conductive layer 121 is not provided. In the memory cell 10E, an insulating layer 271 is provided over the transistor 11E, the capacitor 15E, the insulating layer 283, and the insulating layer 285, and an insulating layer 273 is provided over the insulating layer 271. In the memory cell 10E, a conductive layer 267 is provided so as to be embedded in the insulating layer 271. In the memory cell 10E, a conductive layer 266 is provided so as to be embedded in the insulating layer 271 and the insulating layer 273, and a conductive layer 265 is provided over the conductive layer 266 and the insulating layer 273. The insulating layer 271 and the insulating layer 273 function as interlayer insulating layers.

[0354] The capacitor 15E may have a similar configuration to the capacitor 15A. The capacitor 15E includes a conductive layer 141 having a region overlapping with the conductive layer 220, an insulating layer 154 on the conductive layer 141, and a conductive layer 124 on the insulating layer 154.

[0355] In the memory cell 10E, the conductive layer 220 can function as a gate electrode of the transistor 13E, one of a source electrode and a drain electrode of the transistor 11E, and one of a pair of electrodes of the capacitor 15E. The conductive layer 267 is electrically connected to the conductive layer 124 and functions as a capacitor wiring. At least a part of the conductive layer 267 can function as the wiring 29 shown in FIG. 1A. The conductive layer 265 is electrically connected to the conductive layer 260 through the conductive layer 266 and can function as the wiring 21 shown in FIG. 1A as described above.

[0356] In memory cell 10E, opening 192 is provided in insulating layer 280 to reach conductive layer 220. In addition, recess 193 is provided at a position overlapping opening 192 of conductive layer 220. A bottom surface of recess 193 corresponds to an upper surface of conductive layer 220. A side surface of recess 193 corresponds to a side surface of conductive layer 220. Opening 192 can be formed in parallel with opening 290.

[0357] In the memory cell 10E, the insulating layer 285 has a region overlapping with the conductive layer 141 with the insulating layer 283 interposed therebetween. The insulating layer 285 has an opening 172 reaching the conductive layer 141 at a position overlapping with the opening 192. The insulating layer 283 covers an upper surface and side surfaces of the conductive layer 141. The insulating layer 154 is in contact with the insulating layer 283 inside the opening 172. Note that the opening 172 may be provided in the insulating layer 283.

[0358] In memory cell 10E, opening 172 can be formed in parallel with opening 270. Additionally, insulating layer 154 can be formed in parallel with insulating layer 250. Additionally, conductive layer 124 can be formed in parallel with conductive layer 260.

[0359] The heights of the top surfaces of the conductive layer 124, the conductive layer 260, and the insulating layer 285 are preferably the same or approximately the same. The conductive layer 267 is located on the insulating layer 285, the insulating layer 283, the insulating layer 154, and the conductive layer 124, and is in contact with the top surface of the conductive layer 124. The conductive layer 267 can also be in contact with the top surface of the insulating layer 285, the top surface of the insulating layer 283, and the top surface of the insulating layer 154.

[0360] The insulating layer 273 is located over the insulating layer 271 and the conductive layer 267. The conductive layer 266 is located over the conductive layer 260 and is in contact with the upper surface of the conductive layer 260. For example, the conductive layer 266 can be formed by forming openings in the insulating layer 273 and the insulating layer 271 that reach the upper surface of the conductive layer 260 and forming a conductive film to fill the openings.

[0361] In the memory cell 10E, the conductive layer 265 is located over the insulating layer 273 and the conductive layer 266, and is in contact with the top surface of the conductive layer 266. The conductive layer 265 can also be in contact with the top surface of the insulating layer 273.

[0362] The conductive layer 260 functioning as a gate electrode of the transistor 11E and the conductive layer 265 functioning as a gate wiring can be electrically connected to each other through a conductive layer 266. The conductive layer 266 functions as a plug (also referred to as a connection electrode).

[0363] The conductive layer 266 and the conductive layer 267 can be formed using a material that can be used for the conductive layer 265. The insulating layer 271 and the insulating layer 273 can be formed using a material that can be used for at least one of the insulating layer 110, the insulating layer 180, the insulating layer 280, and the insulating layer 285.

[0364] In the memory cell 10E, the conductive layer 267 functioning as a capacitor wiring can be formed in a process different from that of the conductive layer included in one or both of the transistors 11E and 13E. Therefore, the memory cell 10E can have a higher degree of freedom in selecting a material for the capacitor wiring than the memory cell 10 shown in, for example, FIGS. 1B to 2B. On the other hand, the number of manufacturing steps can be reduced in the semiconductor device including the memory cell 10 shown in, for example, FIGS. 1B to 2B compared to the semiconductor device including the memory cell 10E. Therefore, the manufacturing cost can be reduced, and a low-cost semiconductor device can be obtained.

[0365] Fig. 13(A) is an enlarged view including the conductive layer 220 and the conductive layer 140 included in the transistor 13 shown in Fig. 1(D) and a region therebetween, and illustrates an example in which the configuration of the conductive layer 140 is different from that in Fig. 1(D). Fig. 13(B) is an enlarged view including the conductive layer 260 and the conductive layer 240 included in the transistor 11 shown in Fig. 1(D) and a region therebetween, and illustrates an example in which the configuration of the conductive layer 240 is different from that in Fig. 1(D).

[0366] The side surface of the conductive layer 140b in the opening 190 shown in FIG. 13(A) is located outside the side surface of the conductive layer 140a in the opening 190. Also, the side surface of the conductive layer 240b in the opening 290 shown in FIG. 13(B) is located outside the side surface of the conductive layer 240a in the opening 290. The conductive layer 140 shown in FIG. 13(A) may be formed due to the process of forming the opening 190. Also, the conductive layer 240 shown in FIG. 13(B) may be formed due to the process of forming the opening 290. For example, the conductive layer 140 shown in FIG. 13(A) may be formed by removing a part of the conductive layer 140b after forming the opening 190 by etching. Similarly, the conductive layer 240 shown in FIG. 13(B) may be formed by removing a part of the conductive layer 240b after forming the opening 290 by etching.

[0367] In the example shown in FIG. 13(A), the semiconductor layer 130 contacts the side surface of the conductive layer 140a as well as the top surface of the conductive layer 140a. Therefore, when the conductive layer 140 has the structure shown in FIG. 13(A), the contact area between the semiconductor layer 130 and the conductive layer 140a can be made larger than, for example, the structure shown in FIG. 1(D). As described above, a conductive material containing oxygen can be used for the conductive layer 140a. Therefore, when a metal oxide is used as the semiconductor layer 130, the contact resistance per unit area between the semiconductor layer 130 and the conductive layer 140a can be made lower than the contact resistance per unit area between the semiconductor layer 130 and the conductive layer 140b. Therefore, when the conductive layer 140 has the structure shown in FIG. 13(A), the contact resistance between the semiconductor layer 130 and the conductive layer 140 can be made lower than, for example, the structure shown in FIG. 1(D). Similarly, when the conductive layer 240 has the structure shown in Fig. 13(B), the contact resistance between the semiconductor layer 230 and the conductive layer 240 can be lower than that in the structure shown in Fig. 1(D), for example. On the other hand, when the conductive layer 140 and the conductive layer 240 have the structure shown in Fig. 1(D), for example, the number of manufacturing steps of the semiconductor device can be reduced compared to the structures shown in Fig. 13(A) and Fig. 13(B). Thus, the manufacturing cost can be reduced, and a low-cost semiconductor device can be obtained.

[0368] FIG. 14(A) is a diagram showing an example in which the side surface of the conductive layer 140a shown in FIG. 13(A) in the opening 190 is located outside the side surface of the insulating layer 180 in the opening 190. FIG. 14(A) shows an example in which the side surface of the conductive layer 140a in the opening 190 coincides or approximately coincides with the side surface of the conductive layer 140b in the opening 190. FIG. 14(B) is a diagram showing an example in which the side surface of the conductive layer 240a shown in FIG. 13(B) in the opening 290 is located outside the side surface of the insulating layer 280 in the opening 290. FIG. 14(B) shows an example in which the side surface of the conductive layer 240a in the opening 290 coincides or approximately coincides with the side surface of the conductive layer 240b in the opening 290. The conductive layer 140 shown in FIG. 14(A) may be formed due to the process of forming the opening 190. Also, the conductive layer 240 shown in FIG. 14(B) may be formed due to the process of forming the opening 290.

[0369] [Memory cell 10F] Fig. 15 is a diagram showing a configuration example of a memory cell 10F. Fig. 15 is a cross-sectional view taken along dashed line A1-A2 shown in Fig. 1(B) and Fig. 1(C). Here, the transistor 11, the transistor 13, and the capacitor 15 included in the memory cell 10F are referred to as a transistor 11F, a transistor 13F, and a capacitor 15F, respectively.

[0370] In the memory cell 10F, the opening 190 reaches the conductive layer 120a. The semiconductor layer 130 contacts the upper surface of the conductive layer 120a inside the opening 190. The opening 192 reaches the conductive layer 121a. The conductive layer 141 contacts the upper surface of the conductive layer 121a inside the opening 192. The opening 290 reaches the conductive layer 220a. The semiconductor layer 230 contacts the upper surface of the conductive layer 220a inside the opening 290. Note that although an example in which recesses are not provided in the conductive layer 120a, the conductive layer 121a, and the conductive layer 220a is shown in FIG. 15, recesses may be provided in the conductive layer 120a, the conductive layer 121a, and the conductive layer 220a.

[0371] In the transistor 13F, the conductive layer 120b has an opening 190. Therefore, in the transistor 13F, the difference between the shortest distance Tc1 and the shortest distance Tb1 is larger than, for example, the transistor 13 shown in FIG. 3A. The larger the difference between the shortest distance Tc1 and the shortest distance Tb1, the larger the area of ​​the region where the side surface of the conductive layer 220 and the conductive layer 120 face each other in the opening 190 or the recess 191 of the conductive layer 120b. Therefore, a gate electric field is more easily applied to the channel formation region of the semiconductor layer 130. Similarly, in the transistor 11F, the gate electric field is more easily applied to the channel formation region of the semiconductor layer 130 than, for example, the transistor 11 shown in FIG. 3A.

[0372] On the other hand, for example, the semiconductor layer 130 of the transistor 13 shown in FIG. 3A is in contact with the upper surface of the conductive layer 120b in a region overlapping with the opening 190. Therefore, for example, the transistor 13 shown in FIG. 3A has a larger area where the semiconductor layer 130 and the conductive layer 120b are in contact than the transistor 13F. As described above, a conductive material containing oxygen can be used for the conductive layer 120b. Therefore, when a metal oxide is used as the semiconductor layer 130, the contact resistance per unit area between the semiconductor layer 130 and the conductive layer 120b can be lower than the contact resistance per unit area between the semiconductor layer 130 and the conductive layer 120a. As described above, the transistor 13F can have a lower contact resistance between the semiconductor layer 130 and the conductive layer 120 than the transistor 13 shown in FIG. 3A. Similarly, the transistor 11F can have a lower contact resistance between the semiconductor layer 230 and the conductive layer 220 than the transistor 11 shown in FIG. 3A.

[0373] [Memory cell 10G] Fig. 16 is a diagram showing a configuration example of a memory cell 10G. Fig. 16 is a cross-sectional view taken along dashed line A1-A2 shown in Fig. 1(B) and Fig. 1(C). Here, the transistor 11, the transistor 13, and the capacitor 15 included in the memory cell 10G are respectively referred to as a transistor 11G, a transistor 13G, and a capacitor 15G.

[0374] In the memory cell 10G, the conductive layer 120 does not have a recess 191. In the memory cell 10G, the conductive layer 121 does not have a recess 193. In the memory cell 10G, the conductive layer 220 does not have a recess 291. When the opening 190 is formed by, for example, etching, if the etching selectivity of the insulating layer 180 to the conductive layer 120b is high, the recess 191 may not be formed in the conductive layer 120b. Similarly, if the etching selectivity of the insulating layer 180 to the conductive layer 121b is high, the recess 193 may not be formed in the conductive layer 121b. In addition, if the etching selectivity of the insulating layer 280 to the conductive layer 220b is high, the recess 291 may not be formed in the conductive layer 220b.

[0375] In the memory cell 10G, the semiconductor layer 130 contacts the upper surface of the conductive layer 120b. The conductive layer 141 contacts the upper surface of the conductive layer 121b. The semiconductor layer 230 contacts the upper surface of the conductive layer 220b.

[0376] 3A, the memory cell 10G may be able to improve coverage of the opening 190 of the semiconductor layer 130, coverage of the opening 192 of the conductive layer 141, and coverage of the opening 290 of the semiconductor layer 230. On the other hand, the memory cell 10 shown in FIG 3A, for example, may be able to improve the contact area between the semiconductor layer 130 and the conductive layer 120b, the contact area between the conductive layer 141 and the conductive layer 121b, and the contact area between the semiconductor layer 230 and the conductive layer 220b.

[0377] [Memory cell 10H] Fig. 17 is a diagram showing a configuration example of a memory cell 10H. Fig. 17 is a cross-sectional view taken along dashed line A1-A2 shown in Fig. 1(B) and Fig. 1(C). Here, the transistor 11, the transistor 13, and the capacitor 15 included in the memory cell 10H are referred to as a transistor 11H, a transistor 13H, and a capacitor 15H, respectively.

[0378] In the memory cell 10H, the insulating layer 180 has a three-layered structure of an insulating layer 180c, an insulating layer 180d on the insulating layer 180c, and an insulating layer 180e on the insulating layer 180d. In addition, in the memory cell 10H, the insulating layer 280 has a three-layered structure of an insulating layer 280c, an insulating layer 280d on the insulating layer 280c, and an insulating layer 280e on the insulating layer 280d. Note that the insulating layer 180 and the insulating layer 280 may have a single-layered structure, a two-layered structure, or a four-layered or more stacked structure.

[0379] The insulating layer 180c has a region in contact with the upper surface of the insulating layer 110, a region in contact with the side surface of the conductive layer 120, a region in contact with the upper surface of the conductive layer 120, a region in contact with the side surface of the conductive layer 121, and a region in contact with the upper surface of the conductive layer 121. The insulating layer 180e has a region in contact with the lower surface of the conductive layer 140a, a region in contact with the semiconductor layer 130, a region in contact with the conductive layer 141, and a region in contact with the lower surface of the insulating layer 150.

[0380] The insulating layer 280c has a region in contact with the insulating layer 150, a region in contact with a side surface of the conductive layer 220, and a region in contact with an upper surface of the conductive layer 220. The insulating layer 280e has a region in contact with a lower surface of the conductive layer 240, a region in contact with the semiconductor layer 230, and a region in contact with a lower surface of the insulating layer 283.

[0381] The insulating layer 180d is a layer in contact with a channel formation region of the semiconductor layer 130. By using an insulating layer containing oxygen for the insulating layer 180d, oxygen can be supplied to the semiconductor layer 130. Similarly, the insulating layer 280d is a layer in contact with a channel formation region of the semiconductor layer 230. By using an insulating layer containing oxygen for the insulating layer 280d, oxygen can be supplied to the semiconductor layer 230.

[0382] The insulating layer 180d preferably has a region with a higher oxygen content than at least one of the insulating layer 180c and the insulating layer 180e. In particular, the insulating layer 180d preferably has a region with a higher oxygen content than each of the insulating layer 180c and the insulating layer 180e. By increasing the oxygen content of the insulating layer 180d, it becomes easier to form an i-type region in the semiconductor layer 130 near the insulating layer 180d.

[0383] Similarly, the insulating layer 280d preferably has a region with a higher oxygen content than at least one of the insulating layer 280c and the insulating layer 280e. In particular, the insulating layer 280d preferably has a region with a higher oxygen content than each of the insulating layer 280c and the insulating layer 280e. By increasing the oxygen content of the insulating layer 280d, it becomes easier to form an i-type region in the semiconductor layer 230 near the insulating layer 280d.

[0384] It is more preferable to use a film that releases oxygen when heated for the insulating layer 180d and the insulating layer 280d. For example, the insulating layer 180d releases oxygen due to heat applied during the manufacturing process of the transistor 13H, so that oxygen can be supplied to the semiconductor layer 130. For example, the insulating layer 280d releases oxygen due to heat applied during the manufacturing process of the transistor 11H, so that oxygen can be supplied to the semiconductor layer 230. Supplying oxygen from the insulating layer 180d to the semiconductor layer 130, particularly to the channel formation region of the semiconductor layer 130, reduces oxygen vacancies and V O In addition, by supplying oxygen from the insulating layer 280d to the semiconductor layer 230, particularly to the channel formation region of the semiconductor layer 230, oxygen vacancies and V O It is possible to reduce H. As described above, the transistor 13H and the transistor 11H can be transistors with favorable electrical characteristics and high reliability.

[0385] To improve the electrical characteristics and reliability of an OS transistor, it is important to sufficiently reduce the hydrogen concentration in the metal oxide and then optimize the amount of oxygen supplied to the metal oxide.

[0386] In particular, when the channel length of the transistor 13H and the transistor 11H is short, oxygen vacancies in the channel formation region and V O The influence of H on the electrical characteristics and reliability is particularly large. Therefore, by optimizing the amount of oxygen supplied to the semiconductor layer 130 and the semiconductor layer 230 after sufficiently reducing the hydrogen concentration in the semiconductor layer 130 and the hydrogen concentration in the semiconductor layer 230, a transistor having a short channel length, excellent electrical characteristics, and high reliability can be realized.

[0387] The insulating layer 180d and the insulating layer 280d are preferably formed by a deposition method such as a sputtering method or a plasma enhanced CVD (PECVD) method. In particular, when a sputtering method is used, hydrogen is not required as a deposition gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 130 and the semiconductor layer 230 can be suppressed, and the electrical characteristics of the transistor 13H and the transistor 11H can be stabilized.

[0388] In order to increase the amount of oxygen supplied to the semiconductor layer 130, for example, after the insulating layer 180d is formed, heat treatment in an atmosphere containing oxygen or plasma treatment in an atmosphere containing oxygen may be performed. Alternatively, oxygen may be supplied by forming an oxide film in an oxygen atmosphere on the upper surface of the insulating layer 180d by a sputtering method. The oxide film may then be removed. By performing such treatment, oxygen can be supplied to the insulating layer 180d, and the amount of oxygen supplied to the semiconductor layer 130 can be increased. Alternatively, by performing a similar treatment after the insulating layer 280d is formed, oxygen can be supplied to the insulating layer 280d, and the amount of oxygen supplied to the semiconductor layer 230 can be increased.

[0389] In addition, the amount of oxygen supplied to the region of the semiconductor layer 130 in contact with the insulating layer 180c and the region of the semiconductor layer 130 in contact with the insulating layer 180e is smaller than that to the region of the semiconductor layer 130 in contact with the insulating layer 180d. Therefore, the region of the semiconductor layer 130 in contact with the insulating layer 180c and the region of the semiconductor layer 130 in contact with the insulating layer 180e may have low resistance. That is, by adjusting the thickness of the insulating layer 180c, the range of the region that functions as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulating layer 180e, the range of the region that functions as the other of the source region and the drain region can be controlled. In this way, the thicknesses of the insulating layers 180c and 180e can be appropriately set according to the characteristics required for the transistor.

[0390] Similarly, the amount of oxygen supplied to the region of the semiconductor layer 230 in contact with the insulating layer 280c and the region of the semiconductor layer 230 in contact with the insulating layer 280e is smaller than that to the region of the semiconductor layer 230 in contact with the insulating layer 280d. Therefore, the region of the semiconductor layer 230 in contact with the insulating layer 280c and the region of the semiconductor layer 230 in contact with the insulating layer 280e may become low-resistance. That is, by adjusting the thickness of the insulating layer 280c, the range of the region that functions as one of the source region and the drain region can be controlled. Similarly, by adjusting the thickness of the insulating layer 280e, the range of the region that functions as the other of the source region and the drain region can be controlled. In this way, the thicknesses of the insulating layers 280c and 280e can be appropriately set according to the characteristics required for the transistor.

[0391] In addition, it is preferable to use a material with a low relative dielectric constant for the insulating layer 180d and the insulating layer 280d. This can reduce parasitic capacitance between wirings. For example, silicon oxide or silicon oxynitride can be used for the insulating layer 180d and the insulating layer 280d.

[0392] It is preferable to use a barrier insulating layer against oxygen for each of the insulating layer 180c, the insulating layer 180e, the insulating layer 280c, and the insulating layer 280e. By providing the insulating layer 180c between the insulating layer 180d and the conductive layer 120, it is possible to suppress the conductive layer 120 from being oxidized and the electrical resistance of the conductive layer 120 from increasing. Furthermore, by providing the insulating layer 180e between the insulating layer 180d and the conductive layer 140, it is possible to suppress the conductive layer 140 from being oxidized and the electrical resistance of the conductive layer 140 from increasing. Furthermore, by providing the insulating layer 280c between the insulating layer 280d and the conductive layer 220, it is possible to suppress the conductive layer 220 from being oxidized and the electrical resistance of the conductive layer 220 from increasing. Furthermore, by providing the insulating layer 280e between the insulating layer 280e and the conductive layer 240, it is possible to suppress the conductive layer 240 from being oxidized and the electrical resistance of the conductive layer 240 from increasing.

[0393] Also, an insulating layer having a function of trapping or fixing hydrogen may be used as the insulating layer 180c. With such a configuration, it is possible to suppress diffusion of hydrogen from below the insulating layer 180c to the semiconductor layer 130, and further to trap or fix hydrogen contained in the semiconductor layer 130. Therefore, it is possible to reduce the hydrogen concentration in the semiconductor layer 130. As the insulating layer 180c, magnesium oxide, aluminum oxide, hafnium oxide, or an oxide containing hafnium and silicon, or the like may be used. Also, for example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulating layer 180c. Similarly, an insulating layer having a function of trapping or fixing hydrogen may be used as the insulating layer 180e, the insulating layer 280c, and the insulating layer 280e.

[0394] For example, the insulating layer 180c, the insulating layer 180e, the insulating layer 280c, and the insulating layer 280e can be formed using silicon nitride, and the insulating layer 180d and the insulating layer 280d can be formed using silicon oxide.

[0395] [Memory cell 10I] Fig. 18 is a diagram showing a configuration example of a memory cell 10I. Fig. 18 is a cross-sectional view taken along dashed line A1-A2 shown in Fig. 1B and Fig. 1C. Here, the transistor 11, the transistor 13, and the capacitor 15 included in the memory cell 10I are referred to as a transistor 11I, a transistor 13I, and a capacitor 15I, respectively.

[0396] The memory cell 10I differs from the memory cell 10 shown in FIG.

[0397] In the memory cell 10I, an insulating layer 122 is provided over an insulating layer 110, and a conductive layer 120a, a conductive layer 121a, and an insulating layer 180 are provided over the insulating layer 122.

[0398] An insulating layer having a function of trapping or fixing hydrogen is preferably used for the insulating layer 122. In this manner, hydrogen in the semiconductor layer 130 can be diffused to the insulating layer 122 through the conductive layers 120a and 120b and the hydrogen can be trapped or fixed. As a result, the hydrogen concentration in the semiconductor layer 130 can be reduced.

[0399] For example, it is preferable to use a silicon nitride film as the insulating layer 110 and an oxide film containing hafnium and silicon (hafnium silicate film) as the insulating layer 122.

[0400] [Memory cell 10J] Fig. 19 is a diagram showing a configuration example of a memory cell 10J. Fig. 19 is a cross-sectional view taken along dashed line A1-A2 shown in Fig. 1(B) and Fig. 1(C). Here, the transistor 11, the transistor 13, and the capacitor 15 included in the memory cell 10J are referred to as a transistor 11J, a transistor 13J, and a capacitor 15J, respectively.

[0401] In the memory cell 10J, the insulating layer 180 has a region 180i, and the insulating layer 280 has a region 280i. The region 180i and the region 280i each contain a halogen element. At least a portion of the region 180i is in contact with the semiconductor layer 130, and at least a portion of the region 280i is in contact with the semiconductor layer 230.

[0402] The halogen element is preferably one or more selected from chlorine, fluorine, bromine, and iodine, and more preferably chlorine or fluorine. From the viewpoint of replacing oxygen, it is preferable to use fluorine, which has a higher electronegativity than oxygen.

[0403] The region 180i having a halogen element allows the halogen element to be supplied from the region 180i into the semiconductor layer 130. The region 280i having a halogen element allows the halogen element to be supplied from the region 280i into the semiconductor layer 230. The halogen element (X) becomes a defect (VoX) in which the halogen element enters an oxygen vacancy (Vo) in the semiconductor layer 130 and the semiconductor layer 230, and has a function of generating electrons that become carriers. For example, when chlorine (Cl) is used as the halogen element, Cl exists stably in the state of VoCl in the semiconductor layer 130 (particularly at the interface between the insulating layer 180 and the semiconductor layer 130 and in the vicinity thereof) and in the semiconductor layer 230 (particularly at the interface between the insulating layer 280 and the semiconductor layer 230 and in the vicinity thereof). At this time, Cl can enter the existing Vo, and also become the state of VoCl by replacing it with oxygen.

[0404] On the other hand, oxygen substituted by Cl (also referred to as excess oxygen) has a function of trapping electrons. Moreover, carrier generation by VoCl occurs preferentially with respect to carrier trapping by oxygen. Therefore, negative charges (also referred to as negative fixed charges) are formed at the interface between the insulating layer 180 and the semiconductor layer 130 and in the vicinity thereof. The region 180i is in contact with the channel formation region in the semiconductor layer 130. The presence of negative charges in the channel formation region can shift the threshold voltage of the transistor 13J to the positive side. Therefore, even if the transistor 13J has a fine structure or the channel length of the transistor 13J is extremely short, the transistor 13J can have normally-off characteristics. Similarly, for example, since the insulating layer 280 has the region 280i, the transistor 11J can have normally-off characteristics even if the transistor 11J has a fine structure or the channel length of the transistor 11J is extremely short.

[0405] For example, it is preferable to use an aluminum oxide layer for the insulating layer 180 and the insulating layer 280 and use fluorine as the halogen element. Note that the insulating layer 180 and the insulating layer 280 may have a single-layer structure or a stacked structure. When the insulating layer 180 and the insulating layer 280 have a stacked structure, for example, it is preferable to have one or both of a silicon oxide layer and a silicon nitride layer in addition to an aluminum oxide layer. At this time, it is considered that oxygen bonded to aluminum is replaced with fluorine, and the desorbed oxygen is bonded to hydrogen to become an OH group (Al-O+F→Al-F+O+H→AlF+OH). In this way, the presence of AlF on the back channel side can not only form negative charges in the channel formation region and positively shift the threshold voltages of the transistors 13J and 11J, but also provide a function of capturing or fixing hydrogen (also referred to as gettering). This can reduce the hydrogen concentration in the semiconductor layer 130 and the semiconductor layer 230. In particular, the hydrogen concentration in the channel formation region of the transistor 13J and the hydrogen concentration in the channel formation region of the transistor 11J can be reduced. Therefore, it is possible to reduce VoH in the channel formation region and make the channel formation region i-type or substantially i-type.

[0406] The conductive layer 120, the conductive layer 140, the conductive layer 220, and the conductive layer 240 may also have a halogen element. A halogen element may be supplied from the conductive layer 120 or the conductive layer 140 into the semiconductor layer 130. A halogen element may be supplied from the conductive layer 220 or the conductive layer 240 into the semiconductor layer 230. In FIG. 19, the side surfaces of the conductive layer 120 and the conductive layer 140 on the opening 190 side are also hatched in the same manner as the region 180i. In FIG. 19, the side surfaces of the conductive layer 220 and the conductive layer 240 on the opening 290 side are also hatched in the same manner as the region 280i.

[0407] Furthermore, the semiconductor layer 130 may have a region that is in contact with the insulating layer 180 and that contains a halogen element. Furthermore, the semiconductor layer 230 may have a region that is in contact with the insulating layer 280 and that contains a halogen element.

[0408] The source and drain regions of the semiconductor layer 130 and the source and drain regions of the semiconductor layer 230 preferably contain an impurity element. The impurity element is preferably a first element. Alternatively, the impurity element is preferably both the first element and hydrogen.

[0409] In FIG. 19, the region of the semiconductor layer 130 that contacts the upper surface of the conductive layer 120 in the recess 191 is referred to as region 130n1. The region of the semiconductor layer 130 that contacts the upper surface of the conductive layer 140 is referred to as region 130n2. The region of the semiconductor layer 230 that contacts the upper surface of the conductive layer 220 in the recess 291 is referred to as region 230n1. The region of the semiconductor layer 230 that contacts the upper surface of the conductive layer 240 is referred to as region 230n2. Here, the regions 130n1 and 130n2 are collectively referred to as region 130n, and the regions 230n1 and 230n2 are collectively referred to as region 230n. It is preferable that the regions 130n and 230n contain an impurity element.

[0410] Note that the conductive layer 120, the conductive layer 140, the conductive layer 220, and the conductive layer 240 may also contain an impurity element. In Fig. 19, regions of the conductive layer 120 and the conductive layer 140 in contact with the semiconductor layer 130 are also hatched in the same manner as the region 130n. Furthermore, regions of the conductive layer 220 and the conductive layer 240 in contact with the semiconductor layer 230 are also hatched in the same manner as the region 230n.

[0411] As the first element, it is preferable to use one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0412] The first element is not limited to the above elements, and may be one or more of the first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and elements included in the rare earth elements.

[0413] By supplying the first element to the source region and the drain region, the first element takes away oxygen from these regions, and oxygen vacancies are generated in these regions. Then, the oxygen vacancies are bonded with hydrogen in the film to generate carriers, and the resistance of the source region and the drain region can be reduced. This can reduce the sheet resistance of the semiconductor layer 130, the sheet resistance of the semiconductor layer 230, the contact resistance between the semiconductor layer 130 and the conductive layer 120, the contact resistance between the semiconductor layer 130 and the conductive layer 140, the contact resistance between the semiconductor layer 230 and the conductive layer 220, and the contact resistance between the semiconductor layer 230 and the conductive layer 240. Therefore, the transistor 13J and the transistor 11J can be transistors with a large on-current. By increasing the on-current, the operating voltage of the transistor can be reduced. This can reduce the power consumption of the semiconductor device.

[0414] When an element that is easily bonded to oxygen is used as the first element, the first element exists in a state bonded to oxygen in the semiconductor layer. When an element that is bonded to oxygen for stabilization is used as the first element, the first element in the semiconductor layer exists stably in an oxidized state, so that it is difficult to be desorbed by heat during the manufacturing process of the semiconductor device, for example, and a stable low-resistance region with low electrical resistance can be realized. For this reason, it is preferable to use an element whose oxide can exist as a solid at 25°C and 1 atm as the first element. Specifically, examples of preferred first elements include typical nonmetallic elements other than hydrogen, typical metallic elements, and transition elements (transition metals), and examples of particularly preferred first elements include boron, phosphorus, magnesium, aluminum, and silicon.

[0415] For these reasons, it is preferable to use boron, phosphorus, magnesium, aluminum, or silicon as one of the first elements, and it is particularly preferable to use boron or phosphorus as one of the first elements.

[0416] Moreover, hydrogen is suitable as an impurity element because it has a function of bonding with oxygen vacancies in addition to the function of generating oxygen vacancies described above.

[0417] By using both the first element and hydrogen as impurity elements, the electrical resistance of the source region and the drain region in the semiconductor layer 130 and the semiconductor layer 230 can be easily reduced, and the low electrical resistance can be stably maintained.

[0418] In addition, when both the first element and hydrogen are supplied, the ions generated from the raw material gas can be added without mass separation, which is preferable because it can increase productivity. For example, by using B2H6 gas, boron and hydrogen can be supplied as impurity elements. Also, by using PH3 gas, phosphorus and hydrogen can be supplied as impurity elements. Note that the method of supplying the impurity element is not limited to this. For example, a specific element may be added by ionizing the raw material gas and mass-separating the ions. For example, boron may be added to the region 130n and the region 230n after mass separation using B2H6 gas.

[0419] The regions 130n and 230n have impurity element concentrations of 1×10 19 atoms / cm 3 More than 1×10 23 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 5×10 or more 22 atoms / cm 3 Less than or equal to 1×10 20 atoms / cm 3 More than 1×10 22 atoms / cm 3In the case where a plurality of impurity elements are contained, the concentration of each of the impurity elements is preferably within the above range.

[0420] Note that the impurity element may also be supplied to the channel formation region in the semiconductor layer 130 and the channel formation region in the semiconductor layer 230. Alternatively, due to the influence of heat or the like during the manufacturing process, a part of the impurity element contained in the region 130n and a part of the impurity element contained in the region 230n may diffuse into the channel formation region. The concentration of the impurity element in the channel formation region is preferably 1 / 10 or less, more preferably 1 / 100 or less, of the concentration of the impurity element in the region 130n and the region 230n.

[0421] The concentrations of the impurity elements contained in the semiconductor layer 130 (including the region 130n) and the semiconductor layer 230 (including the region 230n) can be analyzed by, for example, an analysis method such as SIMS or XPS. When using XPS analysis, the concentration distribution in the depth direction can be known by combining ion sputtering from the front side or the back side with XPS analysis.

[0422] In manufacturing the semiconductor device according to one embodiment of the present invention, the source and drain regions of the semiconductor layer 130 and the source and drain regions of the semiconductor layer 230 are preferably doped with the impurity element more easily than the channel formation region. Therefore, the impurity element is preferably doped from a direction perpendicular or substantially perpendicular to the upper surface of the substrate. At this time, the amount of the impurity element doped is smaller in the surfaces of the semiconductor layer 130 and the semiconductor layer 230 that are inclined with respect to the upper surface of the substrate than in the surfaces that are parallel or substantially parallel to the upper surface of the substrate. That is, the amount of the impurity element doped is larger in the source and drain regions of the semiconductor layer 130 and the source and drain regions of the semiconductor layer 230 than in the channel formation region. Therefore, the resistance of the source and drain regions can be preferentially reduced.

[0423] The above-described structures can be appropriately combined. For example, in the memory cell 10D illustrated in FIGS. 9A to 9C, the transistor 11D or the transistor 13D does not need to have a conductive layer functioning as a back gate electrode and an insulating layer functioning as a back gate insulating layer. That is, the semiconductor device of one embodiment of the present invention may include the transistor 11 having the structures illustrated in FIGS. 1D and 2A, for example, and the transistor 13D. The semiconductor device of one embodiment of the present invention may include the transistor 11D and the transistor 13 having the structures illustrated in FIGS. 1D and 2B, for example. Further, the transistor 11B, the transistor 11C, the transistors 11E to 11J, the transistors 13B, the transistors 13C, and the transistors 13E to 13J may include a conductive layer functioning as a back gate electrode and an insulating layer functioning as a back gate insulating layer.

[0424] <Example of a method for manufacturing a semiconductor device> Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to the drawings. Note that, with respect to materials and formation methods of elements, descriptions of parts similar to those described above may be omitted.

[0425] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed by a sputtering method, a CVD method, a vacuum deposition method, a PLD method, an ALD method, or the like.

[0426] There are three types of sputtering: RF sputtering, which uses a high-frequency power source as the sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used when forming insulating films, while DC sputtering is mainly used when forming metal conductive films. Pulsed DC sputtering is mainly used when forming films of compounds such as oxides, nitrides, or carbides by reactive sputtering.

[0427] CVD methods can be further classified into plasma CVD (PECVD) methods that use plasma, thermal CVD (TCVD) methods that use heat, and photo CVD (Photo CVD) methods that use light, etc. They can also be further classified into metal CVD (MCVD) methods and metal organic CVD (MOCVD) methods depending on the source gas used.

[0428] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, and elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0429] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, or a plasma enhanced ALD (PEALD) method in which a plasma excited reactant is used, or the like can be used.

[0430] The CVD method and the ALD method are different from the sputtering method in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent film thickness uniformity, so it is suitable for covering the surface of an opening with a high aspect ratio, for example. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0431] In addition, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming a film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0432] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0433] Furthermore, the thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a wet film formation method such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0434] Furthermore, when processing a thin film constituting a semiconductor device, for example, a photolithography method can be used. Alternatively, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, etc. Furthermore, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0435] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0436] There are two typical photolithography methods. One is a method in which a resist mask is formed on the thin film to be processed, the thin film is processed by, for example, an etching method, and the resist mask is then removed. The other is a method in which a photosensitive thin film is formed, and then exposed and developed to process the thin film into the desired shape.

[0437] In the photolithography method, the light used for exposure may be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like may be used. Exposure may also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays may also be used as the light used for exposure. An electron beam may also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0438] The thin film can be etched by dry etching, wet etching, sandblasting, or the like.

[0439] An example of a method for manufacturing the memory cell 10 shown in FIG.

[0440] 20(A), an insulating layer 110 is formed on a substrate (not shown), a conductive layer 120a and a conductive layer 121a are formed on the insulating layer 110, a conductive layer 120b is formed on the conductive layer 120a, and a conductive layer 121b is formed on the conductive layer 121a, an insulating layer 180 is formed on the conductive layer 120b, the conductive layer 121b, and the insulating layer 110, a conductive layer 140a is formed on the insulating layer 180, and a conductive layer 140b is formed on the conductive layer 140a. Here, the conductive layer 120 and the conductive layer 121 can be formed by, for example, forming a conductive film on the insulating layer 110 and then processing the conductive film. Specifically, a conductive film to become the conductive layer 120a and the conductive layer 121a, and a conductive film to become the conductive layer 120b and the conductive layer 121b are formed in this order, and then processed to form the conductive layer 120a, the conductive layer 120b, the conductive layer 121a, and the conductive layer 121b.

[0441] Note that after the insulating layer 180 is formed, a planarization treatment is preferably performed to planarize the top surface of the insulating layer 180. As the planarization treatment, a planarization treatment (also referred to as a CMP treatment) using a chemical mechanical polishing (CMP) method is preferable. Alternatively, a planarization treatment (also referred to as an etch-back treatment) using etching may be performed. By performing the planarization treatment on the insulating layer 180, the surfaces on which the conductive layers 140a and 240b are to be formed can be flattened, and discontinuity of the conductive layers 140a and 140b can be suppressed. Note that the planarization treatment is not necessarily performed, in which case, the manufacturing cost can be reduced.

[0442] In this specification and the like, a step discontinuity refers to a phenomenon in which a layer, a film, or an electrode is divided due to the shape of the surface on which it is formed (for example, a step).

[0443] When manufacturing the memory cell 10D, the insulating layer 180a is formed on the conductive layer 120b, the conductive layer 121b, and the insulating layer 110, and then a conductive film is formed on the insulating layer 180a and processed to form the conductive layer 155. The conductive layer 155 can be formed to have a region overlapping with the conductive layer 120a and the conductive layer 120b, and not overlapping with the conductive layer 121a and the conductive layer 121b. Then, the insulating layer 180b is formed on the conductive layer 155 and the insulating layer 180a, and the conductive layer 140a and the conductive layer 140b are formed in this order on the insulating layer 180b.

[0444] 20B, an opening 190 reaching the conductive layer 120b and an opening 192 reaching the conductive layer 121b are formed in the conductive layer 140b, the conductive layer 140a, and the insulating layer 180. At this time, a recess 191 is formed in the conductive layer 120b so as to overlap with the opening 190. In addition, a recess 193 is formed in the conductive layer 121b so as to overlap with the opening 192. By forming the recess 191 in the conductive layer 120b, the contact area with the semiconductor layer 130 to be formed later can be increased. Therefore, a decrease in the on-current of the transistor 13 caused by the contact resistance between the conductive layer 120b and the semiconductor layer 130 can be suppressed. In addition, a gate electric field is easily applied to the channel formation region of the semiconductor layer 130, and the electrical characteristics of the transistor 13 can be improved. In addition, by forming the recess 193 in the conductive layer 121b, the contact area with the conductive layer 141 to be formed later can be increased. Therefore, the contact resistance between the conductive layer 121b and the conductive layer 141 can be reduced.

[0445] For microfabrication, when forming the opening 190 and the opening 192, it is preferable to process a part of the conductive layer 120b, a part of the conductive layer 121b, a part of the conductive layer 140a, a part of the conductive layer 140b, and a part of the insulating layer 180 by anisotropic etching. In particular, processing by a dry etching method is preferable because it is suitable for microfabrication. Also, the opening 190 may be formed under different processing conditions depending on the layer. Note that depending on the materials and processing conditions of the conductive layer 120b, the conductive layer 121b, the conductive layer 140a, the conductive layer 140b, and the insulating layer 180, the inclination of the side surface of the conductive layer 120b in the recess 191 and the inclination of the side surface of the insulating layer 180, the conductive layer 140a, and the conductive layer 140b inside the opening 190 may differ from each other. Furthermore, the inclination of the side surface of conductive layer 121b in recess 193, and the inclination of the side surfaces of insulating layer 180, conductive layer 140a, and conductive layer 140b inside opening 192 may differ from one another.

[0446] Furthermore, for example, by the process of forming the openings 190 and 192, a region containing a halogen element may be provided on at least one of the top surface and side surface of the conductive layer 120b in the recess 191, the top surface and side surface of the conductive layer 121b in the recess 193, the side surface of the insulating layer 180, the side surfaces of the conductive layers 140a and 140b, and the top surface of the conductive layer 140b. Examples of such a region include a region containing fluorine, a region containing chlorine, or a region containing fluorine and chlorine. For example, a halogen element derived from an etching gas used in dry etching may remain in such a region.

[0447] Subsequently, a heat treatment may be performed, for example, at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, and more preferably 320° C. or higher and 450° C. or lower.

[0448] The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen. By performing the above-mentioned heat treatment, impurities such as water contained in the insulating layer 180 can be reduced before the semiconductor layer 130 is formed.

[0449] In addition, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, for example, it is possible to prevent moisture from being taken into the insulating layer 180 as much as possible.

[0450] In addition, when the memory cell 10D is manufactured, the opening 190 is formed in the conductive layer 140b, the conductive layer 140a, the insulating layer 180b, the conductive layer 155, and the insulating layer 180a, and the opening 192 is formed in the insulating layer 180b and the insulating layer 180a, respectively, and then an insulating film is formed so as to cover the opening 190 and the opening 192. Then, anisotropic etching is performed on the insulating film. In this manner, the insulating layer 181 can be formed. The anisotropic etching can be performed until, for example, the upper surface of the conductive layer 120b in the recess 191 and the upper surface of the conductive layer 140b are exposed. The anisotropic etching can be performed, for example, by using a dry etching method. As described above, when the insulating layer 181 is formed by using anisotropic etching, the insulating layer 181 can be formed without performing pattern formation using, for example, a lithography method. The insulating layer 181 may be formed by using a lithography method. Here, the step of forming the insulating layer 181 may result in the formation of an insulating layer along the sidewall of the opening 192 .

[0451] 20C, a semiconductor layer 130 is formed to cover the opening 190 and the opening 192. The semiconductor layer 130 is formed to have a region in contact with the conductive layer 120, a region in contact with the conductive layer 121, and a region in contact with the conductive layer 140, and also has a region located inside the opening 190 and a region located inside the opening 192.

[0452] The semiconductor layer 130 is formed so as to be in contact with the upper surface of the conductive layer 140b. The semiconductor layer 130 is also formed so as to be in contact with the bottom and side surfaces of the recess 191 and the bottom and side surfaces of the recess 193. The semiconductor layer 130 is further formed so as to be in contact with the side surfaces of the insulating layer 180, the side surfaces of the conductive layer 140a, and the side surfaces of the conductive layer 140b inside the opening 190 and inside the opening 192.

[0453] The semiconductor layer 130 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0454] The semiconductor layer 130 is preferably formed as a film with a uniform thickness along the upper and side surfaces of the conductive layer 120b in the recess 191, the upper and side surfaces of the conductive layer 121b in the recess 193, the insulating layer 180, the side surfaces of the conductive layer 140a, and the conductive layer 140b in the openings 190 and 192, and the upper surface of the conductive layer 140b. By forming the film using the ALD method, a thin film can be formed with good controllability. Therefore, it is preferable to form the semiconductor layer 130 using the ALD method.

[0455] In addition, when the semiconductor layer 130 has high crystallinity, diffusion of impurities in the semiconductor layer 130 is suppressed, so that the electrical characteristics of the transistor are less likely to fluctuate and the reliability can be improved. When the semiconductor layer 130 is formed by a sputtering method, it is easier to form a layer with high crystallinity than when an ALD method is used, which is preferable.

[0456] When the semiconductor layer 130 is formed by sputtering, oxygen or a mixed gas of oxygen and a noble gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased. When the oxide film is formed by sputtering, for example, an In-M-Zn oxide target can be used.

[0457] When the semiconductor layer 130 is formed by a sputtering method, an oxygen-excess metal oxide is formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%. A transistor using an oxygen-excess metal oxide for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%,. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility. Furthermore, by performing film formation while heating the substrate, the crystallinity of the metal oxide layer can be improved.

[0458] The semiconductor layer 130 preferably has both a layer formed by the ALD method and a layer formed by the sputtering method. This allows the semiconductor layer 130 to be formed with good coverage and to have high crystallinity. The semiconductor layer 130 preferably has, for example, a layer formed by the sputtering method and a layer formed by the ALD method, which are stacked in this order. A metal oxide layer formed by the sputtering method is likely to have crystallinity. Therefore, by providing a metal oxide layer having crystallinity as a lower layer of the semiconductor layer 130, the crystallinity of the upper layer of the semiconductor layer 130 can be improved. Even if pinholes or discontinuities are formed in the metal oxide layer formed by the sputtering method, the regions overlapping with them can be blocked with a metal oxide layer formed by the ALD method, which has good coverage.

[0459] Specifically, the semiconductor layer 130 can be a two-layer structure in which a layer formed by a sputtering method and a layer formed by an ALD method are stacked in this order; a two-layer structure in which a layer formed by an ALD method and a layer formed by a sputtering method are stacked in this order; a three-layer structure in which a layer formed by an ALD method, a layer formed by a sputtering method, and a layer formed by an ALD method are stacked in this order; or a three-layer structure in which a layer formed by a sputtering method, a layer formed by an ALD method, and a layer formed by a sputtering method are stacked in this order.

[0460] Next, heat treatment is preferably performed. The heat treatment is preferably performed within a temperature range in which the semiconductor layer 130 is not polycrystallized. The temperature of the heat treatment is preferably from 100° C. to 650° C., more preferably from 250° C. to 600° C., and further preferably from 350° C. to 550° C. For details of the heat treatment, refer to the above description.

[0461] In addition, it is preferable that a gas used in the heat treatment is highly purified. By performing the heat treatment using a highly purified gas, for example, moisture can be prevented from being taken into the semiconductor layer 130 as much as possible.

[0462] In this embodiment, the heat treatment is performed at a temperature of 450° C. for one hour with a flow rate ratio of nitrogen gas and oxygen gas set to 4:1. By such heat treatment including oxygen gas, impurities such as carbon, water, and hydrogen in the semiconductor layer 130 can be reduced. By reducing the impurities in the film in this manner, the crystallinity of the semiconductor layer 130 can be improved, and a denser and more compact structure can be obtained. This increases the crystalline region in the semiconductor layer 130, and reduces the in-plane variation of the crystalline region in the semiconductor layer 130. Therefore, the in-plane variation of the electrical characteristics of the transistor can be reduced.

[0463] In addition, in the case where the insulating layer 180 contains oxygen, it is preferable to supply oxygen from the insulating layer 180 to a channel formation region of the semiconductor layer 130 by heat treatment, which can reduce oxygen vacancies and VoH.

[0464] In this manner, oxygen (also referred to as excess oxygen) released by heating from an insulating layer in contact with the semiconductor layer 130 or an insulating layer located near the semiconductor layer 130 may be supplied to the semiconductor layer 130. The excess oxygen has a function of trapping electrons, and thus negative charges are likely to be formed. Therefore, the threshold voltage of the transistor is shifted in the positive direction, and a normally-off transistor can be realized.

[0465] 20(D), the semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b are processed into an island shape, and a part of the upper surface of the insulating layer 180 and a part of the upper surface of the conductive layer 121b are exposed. For example, the bottom and side surfaces of the recess 193 are exposed. The semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b can be processed using the same mask. This is preferable because it can reduce the number of masks required to manufacture a semiconductor device.

[0466] In addition, when the memory cell 10D is manufactured, it is preferable to remove a region of the insulating layer 181 that is not located inside the opening 190 in the step shown in FIG. 20(D). For example, the insulating layer 181 is processed using the same mask as that used for processing the semiconductor layer 130, the conductive layer 140a, and the conductive layer 140b, so that the region of the insulating layer 181 that is not located inside the opening 190 can be removed. By removing a region of the insulating layer 181 that is located inside the opening 192, for example, the side surface of the recess 193 can be prevented from being covered by the insulating layer 181. Therefore, it is possible to prevent the contact area between the conductive layer 121 and the conductive layer 141 to be formed later from being reduced.

[0467] 20(E), conductive layer 141 is formed to cover opening 192. Conductive layer 141 is formed to have a region in contact with conductive layer 121 and a region located inside opening 192.

[0468] The conductive layer 141 is formed so as to be in contact with the bottom surface and side surfaces of the recess 193. The conductive layer 141 is formed so as to be in contact with the upper surface of the insulating layer 180 and the side surfaces of the insulating layer 180 in the opening 192.

[0469] 20(F), the insulating layer 150 is formed to have a region located on the conductive layer 140b, a region located on the insulating layer 180, a region located inside the semiconductor layer 130 in the opening 190, and a region located inside the conductive layer 141 in the opening 192. The insulating layer 150 can be formed to cover the semiconductor layer 130, the conductive layer 140a, the conductive layer 140b, and the conductive layer 141. Specifically, the insulating layer 150 can be formed in contact with the semiconductor layer 130, the insulating layer 180, the conductive layer 140a, the conductive layer 140b, and the conductive layer 141.

[0470] Subsequently, a conductive layer 220a is formed on the insulating layer 150, and a conductive layer 220b is formed on the conductive layer 220a. The conductive layer 220a is formed to have a region facing the semiconductor layer 130 with the insulating la...

Claims

1. a first vertical transistor, a second vertical transistor, and a trench capacitor; the first vertical transistor has a first lower electrode functioning as one of a source electrode and a drain electrode, and a first upper electrode located on the first lower electrode and functioning as the other of the source electrode and the drain electrode; the second vertical transistor has a second lower electrode functioning as one of a source electrode and a drain electrode, and a second upper electrode located on the second lower electrode and functioning as the other of the source electrode and the drain electrode; the trench-type capacitor has a third lower electrode, a dielectric layer on the third lower electrode, and a third upper electrode on the dielectric layer; the gate electrode of the first vertical transistor, the second lower electrode, and the third upper electrode are the same conductive layer; A semiconductor device in which the gate insulating layer of the first vertical transistor and the dielectric layer are the same insulating layer.

2. In claim 1, An interlayer insulating layer is provided. the interlayer insulating layer has a region located between the first lower electrode and the first upper electrode; the first upper electrode and the interlayer insulating layer have a first opening reaching the first lower electrode; the interlayer insulating layer has a second opening; The third lower electrode, the insulating layer, and the conductive layer each have a region located inside the first opening and a region located inside the second opening.

3. In claim 2, The semiconductor device further comprises a channel of the first vertical transistor formed along a sidewall of the first opening.

4. a first transistor, a second transistor, a capacitor, a first insulating layer, and a second insulating layer; the first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a third insulating layer; the second transistor includes a second semiconductor layer, the third conductive layer, a fourth conductive layer, a fifth conductive layer, and a fourth insulating layer; the capacitor includes the third conductive layer, a sixth conductive layer, and the third insulating layer; the first insulating layer overlies the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have a first opening reaching the first conductive layer; the first insulating layer has a second opening; the first semiconductor layer has a region in contact with the first conductive layer and a region in contact with the second conductive layer, and has a region located inside the first opening; the sixth conductive layer has a region located within the second opening, the third insulating layer has a region located inside the first semiconductor layer within the first opening, and a region located inside the sixth conductive layer within the second opening, the third conductive layer has a region facing the first semiconductor layer with the third insulating layer interposed therebetween in the first opening, and a region facing the sixth conductive layer with the third insulating layer interposed therebetween in the second opening, the second insulating layer overlies the third conductive layer; the fourth conductive layer is located on the second insulating layer; the second insulating layer and the fourth conductive layer have a third opening reaching the third conductive layer; the second semiconductor layer has a region in contact with the third conductive layer and a region in contact with the fourth conductive layer, and has a region located inside the third opening; the fourth insulating layer has a region located inside the third opening and on the inner side of the second semiconductor layer; The fifth conductive layer has a region facing the second semiconductor layer with the fourth insulating layer interposed therebetween inside the third opening.

5. In claim 4, A fifth insulating layer is provided. the fifth insulating layer has a region overlapping with the fourth conductive layer via the second semiconductor layer, and has a fourth opening at a position overlapping with the third opening; The fifth conductive layer has a region located inside the fourth opening.

6. In claim 5, A seventh conductive layer is provided; A semiconductor device, wherein the seventh conductive layer is located on the fifth insulating layer so as to have a region in contact with an upper surface of the fifth conductive layer.

7. In claim 5, At least a portion of the fourth insulating layer is located inside the fourth opening.

8. In claim 4, the first conductive layer has a first recess at a position overlapping the first opening; the third conductive layer has a second recess at a position overlapping the third opening; the first semiconductor layer has a region in contact with a bottom surface and a side surface of the first recess, The second semiconductor layer has a region in contact with a bottom surface and a side surface of the second recess.

9. In claim 8, A seventh conductive layer is provided; the first insulating layer is located on the seventh conductive layer; the first insulating layer has the second opening reaching the seventh conductive layer; the seventh conductive layer has a third recess at a position overlapping the second opening; The sixth conductive layer has a region in contact with a bottom surface and a side surface of the third recess.

10. In claim 8, the first conductive layer includes a seventh conductive layer and an eighth conductive layer on the seventh conductive layer; the third conductive layer includes a ninth conductive layer and a tenth conductive layer on the ninth conductive layer; the eighth conductive layer has the first recess; The tenth conductive layer has the second recess.

11. In claim 9, the first conductive layer has an eighth conductive layer and a ninth conductive layer on the eighth conductive layer; the third conductive layer includes a tenth conductive layer and an eleventh conductive layer on the tenth conductive layer; the seventh conductive layer includes a twelfth conductive layer and a thirteenth conductive layer on the twelfth conductive layer; the ninth conductive layer has the first recess, the eleventh conductive layer has the second recess; The thirteenth conductive layer has the third recess.

12. In claim 4, the first transistor has a seventh conductive layer and a fifth insulating layer; the second transistor has an eighth conductive layer and a sixth insulating layer; the first insulating layer includes a seventh insulating layer and an eighth insulating layer on the seventh insulating layer; the second insulating layer includes a ninth insulating layer and a tenth insulating layer on the ninth insulating layer; the seventh conductive layer is located on the seventh insulating layer; the eighth conductive layer is located on the ninth insulating layer; the eighth insulating layer covers an upper surface and a side surface of the seventh conductive layer; the tenth insulating layer covers an upper surface and a side surface of the eighth conductive layer; the seventh conductive layer has the first opening; the eighth conductive layer has the third opening, the fifth insulating layer is located within the first opening, the sixth insulating layer is located within the third opening, the seventh conductive layer and the first semiconductor layer have regions that face each other with the fifth insulating layer interposed therebetween, The eighth conductive layer and the second semiconductor layer have regions that face each other with the sixth insulating layer interposed therebetween.

13. a first transistor, a second transistor, a capacitor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer; the first transistor has a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fifth insulating layer; the second transistor has a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and a sixth insulating layer; the capacitor includes a seventh conductive layer, an eighth conductive layer, and a seventh insulating layer; the first insulating layer overlies the first conductive layer; the second conductive layer is located on the first insulating layer; the first insulating layer and the second conductive layer have a first opening reaching the first conductive layer; the first insulating layer has a second opening; the first semiconductor layer has a region located within the first opening, the first semiconductor layer has a region in contact with an upper surface of the second conductive layer and a region in contact with the first conductive layer inside the first opening, the seventh conductive layer has a region located within the second opening and a region located on the first insulating layer; the second insulating layer has a region overlapping with the second conductive layer via the first semiconductor layer and a region overlapping with the first insulating layer via the seventh conductive layer; the second insulating layer has a third opening overlapping the first opening and a fourth opening overlapping the second opening; the fifth insulating layer has a region located inside the first opening and on the inner side of the first semiconductor layer, the third conductive layer has a region facing the first semiconductor layer with the fifth insulating layer interposed therebetween inside the first opening, and a region located inside the third opening; the seventh insulating layer has a region located inside the seventh conductive layer within the second opening, the eighth conductive layer has a region facing the seventh conductive layer with the seventh insulating layer interposed therebetween inside the second opening, and a region located inside the fourth opening, the fourth conductive layer has a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the eighth conductive layer; the third insulating layer is located on the fourth conductive layer; the fifth conductive layer is located on the third insulating layer; the third insulating layer and the fifth conductive layer have a fifth opening reaching the fourth conductive layer; the second semiconductor layer has a region located inside the fifth opening, the second semiconductor layer has a region in contact with an upper surface of the fifth conductive layer and a region in contact with the fourth conductive layer inside the fifth opening, the fourth insulating layer has a region overlapping with the fifth conductive layer via the second semiconductor layer, the fourth insulating layer has a sixth opening overlapping the fifth opening; the sixth insulating layer has a region located inside the fifth opening and on the inner side of the second semiconductor layer, The sixth conductive layer has a region facing the second semiconductor layer inside the fifth opening with the sixth insulating layer therebetween, and a region located inside the sixth opening.

14. In claim 13, a ninth conductive layer; A semiconductor device, wherein the ninth conductive layer is located on the fourth insulating layer so as to have a region in contact with an upper surface of the sixth conductive layer.

15. In claim 13, the first conductive layer has a first recess at a position overlapping the first opening; the fourth conductive layer has a second recess at a position overlapping with the fifth opening, the first semiconductor layer has a region in contact with a bottom surface and a side surface of the first recess, The second semiconductor layer has a region in contact with a bottom surface and a side surface of the second recess.

16. In claim 15, a ninth conductive layer; the first insulating layer is located on the ninth conductive layer; the first insulating layer has the second opening reaching the ninth conductive layer; the ninth conductive layer has a third recess at a position overlapping with the second opening, The seventh conductive layer has a region in contact with a bottom surface and a side surface of the third recess.

17. In claim 15, the first conductive layer includes a ninth conductive layer and a tenth conductive layer on the ninth conductive layer; The tenth conductive layer has the first recess.

18. In claim 16, the first conductive layer includes a tenth conductive layer and an eleventh conductive layer on the tenth conductive layer; the ninth conductive layer includes a twelfth conductive layer and a thirteenth conductive layer on the twelfth conductive layer; the eleventh conductive layer has the first recess; The thirteenth conductive layer has the third recess.

19. In claim 13, the first transistor has a ninth conductive layer and an eighth insulating layer; the second transistor has a tenth conductive layer and a ninth insulating layer; the first insulating layer includes a tenth insulating layer and an eleventh insulating layer on the tenth insulating layer; the third insulating layer includes a twelfth insulating layer and a thirteenth insulating layer on the twelfth insulating layer; the ninth conductive layer is located on the tenth insulating layer; the tenth conductive layer is located on the twelfth insulating layer; the eleventh insulating layer covers an upper surface and a side surface of the ninth conductive layer; the thirteenth insulating layer covers an upper surface and a side surface of the tenth conductive layer; the ninth conductive layer has the first opening, the eighth conductive layer has the fifth opening, the eighth insulating layer is located within the first opening, the ninth insulating layer is located within the fifth opening, the ninth conductive layer and the first semiconductor layer have regions that face each other with the eighth insulating layer interposed therebetween, The tenth conductive layer and the second semiconductor layer have regions that face each other with the ninth insulating layer interposed therebetween.

20. In any one of claims 4 to 19, the first semiconductor layer and the second semiconductor layer each include a metal oxide; The metal oxide has two or three elements selected from indium, an element M, and zinc, The element M is one or more elements selected from aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.

21. forming a first conductive layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a first opening in the second conductive layer and the first insulating layer, the first opening reaching the first conductive layer, and forming a second opening in the first insulating layer; forming a first semiconductor layer having a region in contact with the first conductive layer and a region in contact with the second conductive layer and a region located inside the first opening; processing the first semiconductor layer and the second conductive layer to expose a portion of an upper surface of the first insulating layer; forming a third conductive layer having a region located within the second opening; forming a second insulating layer to have a region located inside the first semiconductor layer within the first opening and a region located inside the third conductive layer within the second opening; forming a fourth conductive layer so as to have a region facing the first semiconductor layer with the second insulating layer interposed therebetween within the first opening, and a region facing the third conductive layer with the second insulating layer interposed therebetween within the second opening; forming a third insulating layer on the fourth conductive layer; forming a fifth conductive layer on the third insulating layer; forming a third opening portion through the fifth conductive layer and the third insulating layer, the third opening portion reaching the fourth conductive layer; forming a second semiconductor layer having a region in contact with the fourth conductive layer and a region in contact with the fifth conductive layer, and having a region located inside the third opening; processing the second semiconductor layer and the fifth conductive layer to expose a portion of an upper surface of the third insulating layer; forming a sacrificial layer such that at least a portion of the sacrificial layer is located within the third opening; forming a fourth insulating layer to cover the fifth conductive layer, the second semiconductor layer, and the sacrificial layer; performing a planarization process on the fourth insulating layer and the sacrificial layer to planarize an upper surface of the sacrificial layer; removing the sacrificial layer; forming a fifth insulating layer so as to cover the third opening; forming a sixth conductive layer on the fifth insulating layer; A method for manufacturing a semiconductor device, comprising the steps of: performing planarization treatment on the sixth conductive layer; and removing a region of the sixth conductive layer and the fifth insulating layer that overlaps with a top surface of the fourth insulating layer.

22. 22. In claim 21, A method for manufacturing a semiconductor device, comprising the steps of: forming a seventh conductive layer over the fourth insulating layer so as to have a region in contact with an upper surface of the sixth conductive layer.

23. 22. In claim 21, forming a seventh conductive layer in parallel with the formation of the first conductive layer; the first insulating layer is formed to be located on the seventh conductive layer; The second opening is formed to reach the seventh conductive layer; a third conductive layer formed on the first conductive layer and a seventh conductive layer formed on the second conductive layer;

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