High-voltage gate driver integrated circuit using galvanic isolator

Abstract

To provide a high-voltage gate driver integrated circuit using a galvanic isolator.SOLUTION: A device includes: a first region including a first integrated circuit on a substrate; a second region including a second integrated circuit on the substrate; and a third region between the first region and the second region on the substrate. At least one of the first region and the second region includes at least one pattern that provides galvanic isolation between the first and second integrated circuits on the substrate.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a junction isolation based high voltage gate driver integrated circuit (IC), and more particularly to a high voltage gate driver IC using a galvanic separator as a level shifter. [Background technology]

[0002] A high-voltage gate driver circuit may be used to drive a switching element that operates at a high voltage with a low driving voltage. The high-voltage gate driver circuit may use a level shifter that generally uses a high-voltage metal-oxide-semiconductor field-effect transistor (MOSFET) element to convert a low-voltage signal into a high-voltage level signal. In order to reduce power consumption, if only rising / falling edge information of an input signal is transmitted using a level shifter and a driving signal is reproduced at a high voltage level from the input signal using a latch circuit, noise may damage the latch information, resulting in serious malfunction.

[0003] By applying a method of driving the galvanic separator with a modulator and receiving the signal with a demodulator, a gate driver circuit that satisfies high reliability can be realized by eliminating the latch circuit. However, the gate driver circuit based on the galvanic separator is not easy to realize on a single wafer because the modulator circuit and the demodulator circuit must be electrically insulated to satisfy the isolation requirement. Summary of the Invention [Problem to be solved by the invention]

[0004] The technical idea of ​​the present disclosure is to provide a highly reliable high-voltage gate drive integrated circuit and a semiconductor package including the same by utilizing semiconductor technology to embody a low-voltage side modulator section and a high-voltage side demodulator section on a single wafer and using a galvanic separator for signal transmission between the two circuits. [Means for solving the problem]

[0005] An apparatus according to one aspect of the technical concept of the present disclosure includes a first region on a substrate including a first integrated circuit, a second region on the substrate including a second integrated circuit, and a third region on the substrate between the first and second regions, at least one of the first and second regions also including at least one pattern on the substrate that provides galvanic isolation between the first and second integrated circuits.

[0006] An exemplary embodiment of the present disclosure also includes, in the first conductive layer, a first pattern and a second pattern corresponding to the first electrode of the first capacitor and the first electrode of the second capacitor, respectively, and, in the second conductive layer, a third pattern and a fourth pattern corresponding to the second electrode of the first capacitor and the second electrode of the second capacitor, respectively.

[0007] According to an exemplary embodiment of the present disclosure, the at least one pattern may further include a fifth pattern and a sixth pattern in the first conductive layer corresponding to a first electrode of the third capacitor and a first electrode of the fourth capacitor, respectively, and a seventh pattern and an eighth pattern in the second conductive layer corresponding to a second electrode of the third capacitor and a second electrode of the fourth capacitor, respectively, wherein the first pattern through the fourth pattern are included in a first region and the fifth pattern through the eighth pattern are included in a second region, the first pattern and the fifth pattern are electrically connected to each other via a pattern crossing the third region, and the second pattern and the sixth pattern are electrically connected to each other via a pattern crossing the third region.

[0008] In accordance with an exemplary embodiment of the present disclosure, the apparatus may further include a first inductor and a second inductor connected in series between a first electrode of the first capacitor and a first electrode of the second capacitor, and a coupled node of the first inductor and the second inductor may be biased to a first voltage.

[0009] In accordance with an exemplary embodiment of the present disclosure, the apparatus also includes a third inductor inductively coupled to the first inductor, and a fourth inductor inductively coupled to the second inductor.

[0010] According to an exemplary embodiment of the present disclosure, the at least one pattern also includes a first pattern and a second pattern in the first conductive layer corresponding to a first electrode of the first capacitor and a second electrode of the second capacitor, respectively, and a third pattern and a fourth pattern in the second conductive layer corresponding to the second electrode of the first capacitor and the second electrode of the second capacitor, respectively.

[0011] According to an exemplary embodiment of the present disclosure, the at least one pattern also includes a first pattern and a second pattern corresponding to a first inductor and a second inductor, respectively, connected in series on the first conductive layer, and a third pattern and a fourth pattern corresponding to a third inductor and a fourth inductor, respectively, connected in series on the second conductive layer and inductively coupled to the first inductor and the second inductor, respectively.

[0012] According to an exemplary embodiment of the present disclosure, a node to which the first inductor and the second inductor are coupled may be biased to a first voltage, and a node to which the third inductor and the fourth inductor are coupled may be biased to a second voltage.

[0013] According to an exemplary embodiment of the present disclosure, the at least one pattern may further include a fifth pattern and a sixth pattern corresponding to a fifth inductor and a sixth inductor, respectively, connected in series in the first conductive layer, and a seventh pattern and an eighth pattern corresponding to a seventh inductor and an eighth inductor, respectively, connected in series in the second conductive layer and inductively coupled to the fifth inductor and the sixth inductor, respectively, wherein the first pattern through the fourth pattern are included in a first region, the fifth pattern through the eighth pattern are included in a second region, the first pattern and the fifth pattern are electrically connected to each other via a pattern crossing a third region, and the second pattern and the sixth pattern are electrically connected to each other via a pattern crossing the third region.

[0014] According to an exemplary embodiment of the present disclosure, a node where the first inductor and the second inductor are coupled may be biased to a first voltage, and a node where the fifth inductor and the sixth inductor are coupled may be biased to a second voltage.

[0015] According to an exemplary embodiment of the present disclosure, the third region can surround the second region on the substrate.

[0016] In accordance with an exemplary embodiment of the present disclosure, the third region may include a first doped region on the substrate surrounding the second region, a second doped region on the substrate surrounding the first doped region, and a third doped region on the substrate surrounding the second doped region, wherein the second doped region and the third doped region are biased to a first potential, and the second doped region may be electrically floating. Effect of the Invention

[0017] According to an apparatus according to an exemplary embodiment of the present disclosure, when a high-voltage gate drive circuit is realized with a single chip, a galvanic separator is used as a level shifter to transmit signals, and malfunction problems are reduced compared to a level shifter circuit using a high-voltage MOSFET, so that the apparatus can be easily adopted in various optical power applications that require high reliability.

[0018] Additionally, the device according to the exemplary embodiment of the present disclosure can prevent malfunction due to sudden changes in signals, thereby providing highly reliable galvanic isolation.

[0019] Effects that can be obtained from the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly derived and understood by a person having ordinary knowledge in the technical field to which the exemplary embodiments of the present disclosure belong from the following description. In other words, unintended effects by implementing the exemplary embodiments of the present disclosure can also be derived from the exemplary embodiments of the present disclosure by a person having ordinary knowledge in the technical field. [Brief description of the drawings]

[0020] [Figure 1] 1 is an illustration of a high voltage gate drive circuit using a high voltage MOSFET level shifter according to an exemplary embodiment of the present disclosure. [Diagram 2] FIG. 1 is a block diagram illustrating an apparatus according to an exemplary embodiment of the present disclosure. [Diagram 3] 3 is a timing diagram illustrating the signals of FIG. 2 in accordance with an exemplary embodiment of the present disclosure. [Figure 4A] FIG. 1 is a circuit diagram illustrating an example of a galvanic separator according to an exemplary embodiment of the present disclosure. [Figure 4B] FIG. 1 is a circuit diagram illustrating an example of a galvanic separator according to an exemplary embodiment of the present disclosure. [Figure 5A] FIG. 1 is a circuit diagram illustrating an example of a galvanic separator according to an exemplary embodiment of the present disclosure. [Figure 5B]FIG. 1 is a circuit diagram illustrating an example of a galvanic separator according to an exemplary embodiment of the present disclosure. [Figure 6] FIG. 1 illustrates an apparatus layout according to an exemplary embodiment of the present disclosure. [Figure 7A] FIG. 1 illustrates an apparatus layout according to an exemplary embodiment of the present disclosure. [Figure 7B] FIG. 1 illustrates an apparatus layout according to an exemplary embodiment of the present disclosure. [Figure 8A] FIG. 1 illustrates an apparatus layout according to an exemplary embodiment of the present disclosure. [Figure 8B] FIG. 1 illustrates an apparatus layout according to an exemplary embodiment of the present disclosure. [Figure 9A] FIG. 1 is a circuit diagram illustrating an example of a galvanic separator according to an exemplary embodiment of the present disclosure. [Figure 9B] FIG. 1 is a circuit diagram illustrating an example of a galvanic separator according to an exemplary embodiment of the present disclosure. [Figure 9C] FIG. 1 is a circuit diagram illustrating an example of a galvanic separator according to an exemplary embodiment of the present disclosure. [Figure 10A] FIG. 1 is a circuit diagram illustrating an example of a galvanic separator according to an exemplary embodiment of the present disclosure. [Figure 10B] FIG. 1 is a circuit diagram illustrating an example of a galvanic separator according to an exemplary embodiment of the present disclosure. [Figure 11] FIG. 1 illustrates an apparatus layout according to an exemplary embodiment of the present disclosure. [Figure 12] FIG. 1 illustrates an apparatus layout according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments of the present invention are provided to more completely explain the present invention to those having average knowledge in the art. Although the present invention can be modified in various ways and can have various forms, specific embodiments are illustrated in the drawings and described in detail. However, it should be understood that the present invention is not limited to the specific disclosed forms, but includes all modifications, equivalents, or alternatives within the spirit and technical scope of the present invention. In the description of each drawing, similar reference numerals are used for similar components. In the accompanying drawings, the dimensions of the structures are illustrated larger or smaller than the actual dimensions in order to clarify the present invention.

[0022] The terms used in this application are merely used to describe specific embodiments and are not intended to limit the present invention. A singular expression includes a plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprise" or "have" specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, and should be understood not to preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0023] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention pertains. Terms commonly used and predefined should be interpreted to have a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted as idealized or overly formal unless expressly defined in this application.

[0024] In this specification, the X-axis direction and the Y-axis direction may be referred to as a first horizontal direction and a second horizontal direction, respectively, and the Z-axis direction may be referred to as a vertical direction. A plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane, and a component arranged in the +Z direction relative to other components may be referred to as being above other components, and a component arranged in the -Z direction relative to other components may be referred to as being below other components. In addition, the area of ​​the component may refer to the size that the component occupies on a plane parallel to the horizontal plane, and the width of the component may refer to the length in a direction perpendicular to the direction in which the component extends. A surface exposed in the +Z direction may be referred to as a top surface, a surface exposed in the -Z direction may be referred to as a bottom surface, and a surface exposed in the ±X direction or ±Y direction may be referred to as a side surface. For convenience of illustration, only some layers are shown in the drawings, and a pattern made of a conductive material, such as a conductive layer pattern such as a wiring layer, may be referred to as a conductive pattern, or simply as a pattern.

[0025] FIG. 1 is a diagram showing a high-voltage gate driver circuit 10 for driving a switching element M1 operating at a high potential with an input pulse signal according to an exemplary embodiment of the present disclosure. A rising edge pulse generator 11 and a falling edge pulse generator 12 provide rising / falling edge information of the input pulse signal to two high-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) MA and MB, which can transmit the signal information to a high-voltage circuit area HSDC. Thus, the two high-voltage MOSFETs MA and MB are utilized as level shifter elements. In the high-voltage circuit area HSDC, a pulse input detector 13 detects signals from the two high-voltage MOSFETs MA and MB connected to two resistors R1 and R2, respectively, and determines the state of an SR latch 14 to be logic level 1 or logic level 0 based on the detected signal using a set signal S or a reset signal R. This allows the input pulse signal to be reproduced in the high voltage circuit domain HSDC, which converts the signal into a signal (Vgate) suitable for driving the switching element M1 using the gate driver 15, thereby driving the switch.

[0026] The high voltage gate driver circuit 10 of FIG. 1 can be realized on a single wafer using semiconductor technology, for example, as shown in FIG. 6. For example, the low voltage driver circuit can be realized as a first integrated circuit IC1 of FIG. 6, and the high voltage driver circuit can be realized as a second integrated circuit IC2 of FIG. 6. The ring structure of the first integrated circuit IC1 and the second integrated circuit IC2 becomes a region for maintaining high voltage between the two regions. Such a method is called an isolation method using a silicon junction, and can generate a drive signal in the high voltage direction or the low voltage direction, for example, with the ground reference of the wafer.

[0027] As a result, all circuits can be implemented on one wafer, making it easy to manufacture and achieving low costs. However, if a very large amount of noise is applied to the high voltage circuit region HSDC, the state of the SR latch 14 changes due to the noise. Since the SR latch 14 is determined by edge information of the input pulse signal, if the SR latch 14 malfunctions, the error cannot be corrected until a new input pulse is applied. However, since the gate drive circuit using the galvanic isolation device described below with reference to FIG. 2 does not require a latch circuit, it is relatively free from such malfunctions, and therefore the switch element can be driven with high reliability, and the switch voltage can be freely set by the isolated drive. However, since the modulator circuit and the demodulator circuit must also be isolated, they are implemented on separate chips, and the assembly process is complicated and expensive.

[0028] It is sufficient that the switching voltage is higher than the input and controlled in only one direction. Therefore, it is advantageous to use the junction isolation technique. As a result, as will be described later with reference to the drawings, a high-voltage gate drive semiconductor chip that satisfies low cost and high reliability can be realized on a single wafer by using the junction isolation technique but using a galvanic isolator as a level shifter.

[0029] Fig. 2 is a block diagram illustrating an example of the present disclosure (apparatus 100). As shown in Fig. 2, apparatus 100 also includes a transmitter 120, a galvanic isolator 140, and a receiver 160. Transmitter 120 and receiver 160 may each have a different reference potential, and galvanic isolator 140 may transmit a signal containing information between transmitter 120 and receiver 160.

[0030] In some embodiments, device 100 may be an electronic device such as a television (TV), a personal computer (PC), a vehicle, a personal mobility (PM), or the like, or may be a component included in any of the above. In some embodiments, device 100 may correspond to a chip (or die) manufactured by a semiconductor process. For example, transmitter 120, galvanic isolator 140, and receiver 160 may be included in a single chip manufactured by dicing a wafer, and the chip may be packaged. As described below with reference to the drawings, galvanic isolation may be provided in a single chip, which may facilitate the adoption of galvanic isolation in a variety of applications.

[0031] The transmitter 120 also includes a modulator 122. The modulator 122 may receive an input signal IN and generate a modulated signal MOD by modulating the input signal IN. In some embodiments, the modulator 122 may generate the modulated signal MOD from the input signal IN based on on / off keying (OOK). The input signal IN includes information to provide to the receiver 160 and may be generated within the transmitter 120 or may be received from outside the transmitter 120. In some embodiments, the galvanic isolator 140 includes an inductor, and the modulator 122 may generate the modulated signal MOD using a resonant frequency based on the inductor included in the galvanic isolator 140. An example of the input signal IN and the modulated signal MOD is described below with reference to FIG. 3.

[0032] The galvanic isolator 140 may receive the modulated signal MOD from the transmitter 120 and generate a derived signal MOD' from the modulated signal MOD. In some embodiments, the derived signal MOD' may correspond to an attenuated signal from the modulated signal MOD. As described below with reference to the figures, the galvanic isolator 140 may include at least one trace, and the at least one trace may form a capacitor and / or an inductor.

[0033] The receiver 160 also includes a demodulator 162. The demodulator 162 may receive the induced signal MOD' and generate an output signal OUT by demodulating the induced signal MOD'. In some embodiments, the demodulator 162 may generate the output signal OUT from the induced signal MOD' based on on / off keying (OOK). The output signal OUT also includes information contained in the input signal IN. In some embodiments, a driver for amplifying the output signal OUT may be included in the receiver 160 or may be included in the apparatus 100 external to the receiver 160.

[0034] The transmitter 120 and the receiver 160 may each be included in separate regions on a chip. For example, the transmitter 120 may be included as an integrated circuit in a first region, and the receiver 160 may be included as an integrated circuit in a second region, and the first and second regions may be separated. In some embodiments, a third region between the first and second regions may have a structure that isolates high voltages between the first and second regions, as described below with reference to FIG. 6. A galvanic isolator 140 between the separated first and second regions provides galvanic isolation, such that the transmitter 120 and the receiver 160 may be embodied in one chip. In this specification, it is assumed that the first region includes the transmitter 120 and the second region includes the receiver 160, but it is noted that the first region may include the receiver 160 and the second region may include the transmitter 120.

[0035] Figure 3 is a timing diagram illustrating the signals of Figure 2 according to an exemplary embodiment of the present disclosure. It is noted that Figure 3 is merely an example, and the signals of Figure 2 are not limited to the example of Figure 3. For convenience of illustration, delays between signals are ignored in Figure 3. In the following, Figure 3 will be described with reference to Figure 2.

[0036] 3, the input signal IN may also be a pulse signal having an active or inactive state. For example, as shown in FIG. 3, the input signal IN may be activated at time t1 and time t3, while being inactivated at time t2 and time t4. The modulator 122 may generate a modulated signal MOD that oscillates in response to the activation of the input signal IN. For example, as shown in FIG. 3, the modulated signal MOD may oscillate from time t1 to time t2 and oscillate from time t3 to time t4.

[0037] The galvanic isolator 140 may generate an oscillating induced signal MOD' from the oscillating modulated signal MOD. For example, as shown in FIG. 3, the induced signal MOD' may oscillate from time t1 to time t2 and from time t3 to time t4. As shown in FIG. 3, the magnitude (i.e., amplitude or peak value) of the induced signal MOD' is smaller than that of the modulated signal MOD. The demodulator 162 may generate an activated output signal OUT in response to the oscillating induced signal MOD'. For example, as shown in FIG. 3, the output signal OUT may be activated from time t1 to time t2 and from time t3 to time t4.

[0038] 4A and 4B are circuit diagrams illustrating an example of a galvanic isolator according to an exemplary embodiment of the present disclosure. For example, the circuit diagrams of FIG. 4A and 4B show an equivalent circuit of the galvanic isolator 140 of FIG. 2. As shown in FIG. 4A and 4B, the galvanic isolator 140 also includes a capacitor having a high withstand voltage. In the following, in the description of FIG. 4A and FIG. 4B, the overlapping contents are omitted.

[0039] In some embodiments, the modulated signal MOD and the induced signal MOD' in FIG. 2 are differential signals, and the galvanic isolators 300a, 300b each include a terminal T11, T12 that receives the modulated signal MOD and a terminal T21, T22 that outputs the induced signal MOD'. In some embodiments, the modulated signal MOD may be applied to the terminals T21, T22, and the induced signal MOD' may be output to the terminals T11, T12. As shown in FIG. 4A and FIG. 4B, the galvanic isolators 300a, 300b may have a balanced structure for differential signals.

[0040] Referring to FIG. 4A, the galvanic isolator 300a may also include a first capacitor C1 and a second capacitor C2. The first capacitor C1 may be coupled between terminals T11 and T21, and the second capacitor C2 may be coupled between terminals T12 and T22. The transmitting side and the receiving side may be isolated from each other by the first capacitor C1 and the second capacitor C2, and each of the first capacitor C1 and the second capacitor C2 may have a required dielectric strength. In some embodiments, the first capacitor C1 and the second capacitor C2 may be formed by a pattern included in one of the first region and the second region, as described below with reference to FIG. 7A.

[0041] Referring to FIG. 4B, the galvanic isolator 300b also includes a first capacitor C1 to a fourth capacitor C4. The first capacitor C1 and the third capacitor C3 may be connected in series between the terminals T11 and T21, and the second capacitor C2 and the fourth capacitor C4 may be connected in series between the terminals T12 and T22. In some embodiments, as described below with reference to FIG. 7B, the first capacitor C1 and the second capacitor C2 may be formed in one of the first region and the second region, and the third capacitor C3 and the fourth capacitor C4 may be formed in the other of the first region and the second region. In addition, the first capacitor C1 and the third capacitor C3 may be interconnected by a pattern that crosses the third region, and the second capacitor C2 and the fourth capacitor C4 may also be interconnected by a pattern that crosses the third region. When compared to galvanic isolator 300a of FIG. 4A, galvanic isolator 300b of FIG. 4B may provide a higher withstand voltage between the first and second regions while occupying a larger area.

[0042] 5A and 5B are circuit diagrams illustrating an example of a galvanic isolator according to an exemplary embodiment of the present disclosure. For example, the circuit diagrams of Fig. 5A and 5B show an equivalent circuit of the galvanic isolator 140 of Fig. 2. As shown in Fig. 5A and 5B, the galvanic isolator 140 also includes a transformer having a high withstand voltage. In the following, in the description of Fig. 5A and Fig. 5B, the contents that overlap with each other will be omitted.

[0043] In some embodiments, the modulated signal MOD and the induced signal MOD' in FIG. 2 are also differential signals, and the galvanic isolators 400a, 400b each include a terminal T11, T12 that receives the modulated signal MOD and a terminal T21, T22 that outputs the induced signal MOD'. In some embodiments, the modulated signal MOD may be applied to the terminals T21, T22, and the induced signal MOD' may be output at the terminals T11, T12. As shown in FIG. 5A and FIG. 5B, the galvanic isolators 400a, 400b may have a balanced structure for differential signals.

[0044] Referring to FIG. 5A, the galvanic separator 400a also includes first inductors L11, L12 connected in series between terminals T11, T12, and second inductors L21, L22 connected in series between terminals T21, T22. The first inductors L11, L12 may be inductively coupled to the second inductors L21, L22 with a coupling coefficient k. The transmitting side and the receiving side are isolated from each other by the first inductors L11, L12 and the second inductors L21, L22, which are insulated from each other, and the first inductors L11, L12 and the second inductors L21, L22 may have a dielectric strength according to requirements. In some embodiments, the first inductors L11, L12 and the second inductors L21, L22 may be formed by a pattern included in one of the first region and the second region, as described below with reference to FIG. 8A.

[0045] 5B, the galvanic separator 400b may also include a plurality of inductors. The first inductors L11 and L12 may be connected in series between the terminals T11 and T12. The second inductors L21 and L22 connected in series with each other and the third inductors L31 and L32 connected in series with each other may be connected in parallel with each other. The fourth inductors L41 and L42 may be connected in series between the terminals T21 and T22. As shown in FIG. 5B, the first inductors L11 and L12 may be inductively coupled to the second inductors L21 and L22 with a coupling coefficient k, and may be inductively coupled to the fourth inductors L41 and L42 and the third inductors L31 and L32 with a coupling coefficient k. In some embodiments, as described below with reference to FIG. 8B, the first inductors L11, L12 and the second inductors L21, L22 may be formed in one of the first and second regions, and the third inductors L31, L32 and the fourth inductors L41, L42 may be formed in the other of the first and second regions. Also, the second inductors L21, L22 and the third inductors L31, L32 may be interconnected by a pattern that crosses the third region. Compared to the galvanic isolator 400a of FIG. 5A, the galvanic isolator 400b of FIG. 5B may provide a higher breakdown voltage between the first and second regions while occupying a larger area.

[0046] 6 is a diagram illustrating a layout 500 of an apparatus according to an exemplary embodiment of the present disclosure. For example, the upper part of FIG. 6 illustrates a plan view of the layout 500, and the lower part of FIG. 6 illustrates a cross-sectional view of the layout 500 taken along line X1'-X1. As described with reference to the drawings, the layout 500 may be manufactured by a semiconductor process and included in one chip (or die). For convenience of illustration, only some components are illustrated in FIG. 6.

[0047] 6, the layout 500 also includes a first region 51, a second region 52, and a third region 53. The first region 51 and the second region 52 are separated by the third region 53, which may surround the second region 52 on the substrate. The first region 51 includes a first integrated circuit IC1, and the second region 52 includes a second integrated circuit IC2. For example, the first integrated circuit IC1 includes the transmitter 120 of FIG. 2, and the second integrated circuit IC2 includes the receiver 160 of FIG. 2. On the other hand, the first integrated circuit IC1 includes the receiver 160 of FIG. 2, and the second integrated circuit IC2 includes the transmitter 120 of FIG. 2. In the following, it is assumed that the first integrated circuit IC1 includes the transmitter 120 of FIG. 2, and the second integrated circuit IC2 includes the receiver 160 of FIG. 2, but it is noted that the exemplary embodiment of the present disclosure is not limited thereto.

[0048] The third region 53 may have a structure that provides a high breakdown voltage between the first region 51 and the second region 52. For example, as shown in Fig. 6, the third region 53 may include a first doping region R1 surrounding the second region 52 on the substrate, a second doping region R2 surrounding the first doping region R1 on the substrate, and a third doping region R3 surrounding the second doping region R2 on the substrate. In some embodiments, the first doping region R1 to the third doping region R3 may have a p-type.

[0049] As shown in FIG. 6, the first doping region R1 may separate n-type regions on the substrate, and the third doping region R3 may also separate n-type regions on the substrate. The second doping region R2 and the third doping region R3 may be electrically connected by vias and metal patterns and biased to a first potential (e.g., ground potential). The second doping region R2 may have a width greater than the first doping region R1 and the third doping region R3. The first doping region R1 may be electrically floating. It is noted that the third region 53 is not limited to what is shown in FIG. 6.

[0050] 7A and 7B are diagrams illustrating layouts of devices according to exemplary embodiments of the present disclosure. For example, FIG. 7A shows a plan view and a cross-sectional view taken along line X2-X2' of a layout 600a corresponding to the galvanic separator 300a of FIG. 4A, and FIG. 7B shows a plan view and a cross-sectional view taken along line X3-X3' of a layout 600b corresponding to the galvanic separator 300b of FIG. 4B. In the following, FIG. 7A and FIG. 7B are described with reference to FIG. 4A, FIG. 4B, and FIG. 6.

[0051] 7A, the layout 600a also includes patterns forming the galvanic isolator 300a. The first and second patterns P1 and P2 of the conductive layer Mx may correspond to the first and second electrodes of the first and second capacitors C1 and C2, respectively, and the third and fourth patterns P3 and P4 of the conductive layer Ma may correspond to the second and second electrodes of the first and second capacitors C1 and C2, respectively. As shown in FIG. 7A, the first and third patterns P1 and P3 may be spaced apart by a first distance D1 to form a first capacitor C1 having a breakdown voltage that depends on the first distance D1.

[0052] The fifth pattern P5 of the conductive layer Mx may be connected to the first pattern P1 and may extend across the third region 63. Also, the sixth pattern P6 of the conductive layer Mx may be connected to the second pattern P2 and may extend across the third region 63. When the first pattern P1 to the fourth pattern P4 are formed in the first region, the third pattern P3 and the fourth pattern P4 may be electrically connected to the first integrated circuit in the first region, and the fifth pattern P5 and the sixth pattern P6 may be electrically connected to the second integrated circuit in the second region. On the other hand, when the first pattern P1 to the fourth pattern P4 are formed in the second region, the third pattern P3 and the fourth pattern P4 may be electrically connected to the second integrated circuit in the second region, and the fifth pattern P5 and the sixth pattern P6 may be electrically connected to the first integrated circuit in the first region. In some embodiments, the conductive layer Mx may correspond to a top wiring layer.

[0053] 7B, the layout 600b also includes a pattern forming the galvanic separator 300b. The first pattern P1 and the second pattern P2 of the conductive layer Mx may correspond to the first electrode of the first capacitor C1 and the first electrode of the second capacitor C2, respectively, and the third pattern P3 and the fourth pattern P4 of the conductive layer Ma may correspond to the second electrode of the first capacitor C1 and the second electrode of the second capacitor C2, respectively. The fifth pattern P5 and the sixth pattern P6 of the conductive layer Mx may correspond to the first electrode of the third capacitor C3 and the first electrode of the fourth capacitor C4, respectively, and the seventh pattern P7 and the eighth pattern P8 of the conductive layer Ma may correspond to the second electrode of the third capacitor C3 and the second electrode of the fourth capacitor C4, respectively. As shown in FIG. 7B, the first pattern P1 and the third pattern P3 are spaced apart by a first distance D1 to form a first capacitor C1 having a withstand voltage that depends on the first distance D1. The fifth pattern P5 and the seventh pattern P7 may be spaced apart by a first distance D1 to form a third capacitor C3 having a withstand voltage that depends on the first distance D1.

[0054] The ninth pattern P9 of the conductive layer Mx may be connected to the first pattern P1 and the fifth pattern P5 and may extend across the third region 63. In addition, the tenth pattern P10 of the conductive layer Mx may be connected to the second pattern P2 and the sixth pattern P6 and may extend across the third region 63. When the first pattern P1 to the fourth pattern P4 are formed in the first region and the fifth pattern P5 to the eighth pattern P8 are formed in the second region, the third pattern P3 and the fourth pattern P4 may be electrically connected to the first integrated circuit in the first region, and the seventh pattern P7 and the eighth pattern P8 may be electrically connected to the second integrated circuit in the second region. On the other hand, when the first pattern P1 through the fourth pattern P4 are formed in the second region and the fifth pattern P5 through the eighth pattern P8 are formed in the first region, the third pattern P3 and the fourth pattern P4 may be electrically connected to the second integrated circuit in the second region, and the seventh pattern P7 and the eighth pattern P8 may be electrically connected to the first integrated circuit in the first region. In some embodiments, the conductive layer Mx may correspond to the top wiring layer.

[0055] 8A and 8B are diagrams illustrating layouts of devices according to exemplary embodiments of the present disclosure. For example, FIG. 8A shows a plan view and a cross-sectional view along line X4-X4' of a layout 700a corresponding to galvanic separator 400a of FIG. 5A, and FIG. 8B shows a plan view and a cross-sectional view along line X5-X5' of a layout 700b corresponding to galvanic separator 400b of FIG. 5B. In the following, FIG. 8A and FIG. 8B are described with reference to FIG. 5A, FIG. 5B, and FIG. 6.

[0056] 8A, the layout 700a also includes patterns forming the galvanic separator 400a. The first and second patterns P1 and P2 of the conductive layer Mx may correspond to the first inductors L11 and L12, respectively, which are connected in series with each other, and the third and fourth patterns P3 and P4 of the conductive layer Ma may correspond to the second inductors L21 and L22, respectively, which are connected in series with each other. As shown in FIG. 8A, the first and third patterns P1 and P3 are overlapped in a vertical direction, so that the first and second inductors L11 and L21 may be inductively coupled. The first and seventh patterns P1 and P7 are spaced apart by a second distance D2, and the first and second inductors L11 and L21 may have a withstand voltage that depends on the second distance D2.

[0057] The fifth pattern P5 of the conductive layer My may be connected to the first pattern P1 through a via and may extend across the third region 73. The sixth pattern P6 of the conductive layer My may be connected to the second pattern P2 through a via and may extend across the third region 73. The seventh pattern P7 of the conductive layer Mb may be connected to the third pattern P3 through a via, and the eighth pattern P8 of the conductive layer Mb may be connected to the fourth pattern P4 through a via. When the first pattern P1 to the fourth pattern P4 are formed in the first region, the seventh pattern P7 and the eighth pattern P8 may be electrically connected to the first integrated circuit in the first region, and the fifth pattern P5 and the sixth pattern P6 may be electrically connected to the second integrated circuit in the second region. On the other hand, when the first pattern P1 to the fourth pattern P4 are formed in the second region, the seventh pattern P7 and the eighth pattern P8 may be electrically connected to the second integrated circuit in the second region, and the fifth pattern P5 and the sixth pattern P6 may be electrically connected to the first integrated circuit in the first region.

[0058] 8B, the layout 700b also includes patterns forming the galvanic separator 400b. The first pattern P1 and the second pattern P2 of the conductive layer Mx may correspond to the first inductors L11 and L12 connected in series, respectively, and the third pattern P3 and the fourth pattern P4 of the conductive layer Ma may correspond to the second inductors L21 and L22 connected in series, respectively. The fifth pattern P5 and the sixth pattern P6 of the conductive layer Mx may correspond to the third inductors L31 and L32 connected in series, respectively, and the seventh pattern P7 and the eighth pattern P8 of the conductive layer Ma may correspond to the fourth inductors L41 and L42 connected in series, respectively. As shown in FIG. 8B, the first pattern P1 and the third pattern P3 are overlapped in the vertical direction, so that the first inductor L11 and the second inductor L21 may be inductively coupled. Also, the fifth pattern P5 and the seventh pattern P7 are vertically overlapped, so that the third inductor L31 and the fourth inductor L41 may be inductively coupled. The first pattern P1 and the eleventh pattern P11 are spaced apart by a second distance D2, so that the first inductor L11 and the second inductor L12 may have a withstand voltage that depends on the second distance D2. Also, the fifth pattern P5 and the seventh pattern P7 are spaced apart by a second distance D2, so that the third inductor L31 and the fourth inductor L41 may have a withstand voltage that depends on the second distance D2.

[0059] The ninth pattern P9 of the conductive layer My may be connected to the first pattern P1 and the fifth pattern P5 through vias and may extend across the third region 73. The tenth pattern P10 of the conductive layer My may be connected to the second pattern P2 and the sixth pattern P6 through vias and may extend across the third region 73. The eleventh pattern P11 of the conductive layer Mb may be connected to the third pattern P3 through a via, and the twelfth pattern P12 of the conductive layer Mb may be connected to the fourth pattern P4 through a via. The thirteenth pattern P13 of the conductive layer Mb may be connected to the seventh pattern P7 through a via, and the fourteenth pattern P14 of the conductive layer Mb may be connected to the eighth pattern P8 through a via. When the first pattern P1 through the fourth pattern P4 are formed in the first region and the fifth pattern P5 through the eighth pattern P8 are formed in the second region, the eleventh pattern P11 and the twelfth pattern P12 may be electrically connected to the first integrated circuit in the first region, and the thirteenth pattern P13 and the fourteenth pattern P14 may be electrically connected to the second integrated circuit in the second region. On the other hand, when the first pattern P1 through the fourth pattern P4 are formed in the second region and the fifth pattern P5 through the eighth pattern P8 are formed in the first region, the eleventh pattern P11 and the twelfth pattern P12 may be electrically connected to the second integrated circuit in the second region, and the thirteenth pattern P13 and the fourteenth pattern P14 may be electrically connected to the first integrated circuit in the first region.

[0060] 9A to 9C are circuit diagrams illustrating examples of galvanic isolators according to exemplary embodiments of the present disclosure. For example, the circuit diagrams of FIG. 9A to 9C show an equivalent circuit of the galvanic isolator 140 of FIG. 2. As illustrated in FIG. 9A to 9C, each of the galvanic isolators 800a, 800b, and 800c also includes a first capacitor C1 and a second capacitor C2 having a high withstand voltage. In the following, in the description of FIG. 9A to 9C, the overlapping contents are omitted.

[0061] If the first capacitor C1 and the second capacitor C2 have high capacitance to improve the signal transfer characteristics, malfunction may occur due to the first capacitor C1 and the second capacitor C2. For example, if a large voltage change (i.e., high dv / dt) occurs in the receiver 160 of Fig. 2 and the driver that operates based on the output of the receiver 160, a large current is transferred to the transmitter 120 of Fig. 2 via the first capacitor C1 and / or the second capacitor C2, which may cause a circuit included in the transmitter 120 to malfunction or even be destroyed.

[0062] 9A, the galvanic isolator 800a may also include first inductors L11 and L12 connected in series between terminals T11 and T12 and second inductors L21 and L22 connected in series between terminals T21 and T22. A node to which the first inductors L11 and L12 are connected may be connected to a terminal T13, and a node to which the second inductors L21 and L22 are connected may be connected to a terminal T23. The terminals T13 and T23 may be referred to as center tap terminals. The terminals T13 and T23 may each be connected to a low impedance node. For example, the terminal T13 may be biased to a first voltage, and the terminal T23 may be biased to a second voltage. Thus, a current flowing in through the terminal T23 due to a large change in the second voltage may be output through the terminal T13, and an excessive current flowing in to the transmitter 120 may be prevented.

[0063] 9B, the galvanic isolator 800b may also include a first capacitor C1, a second capacitor C2, first inductors L11, L12, second inductors L21, L22, third inductors L31, L32, and fourth inductors L41, L42. The first inductors L11, L12 may be connected in series between the terminals T11, T12, and may be inductively coupled to the second inductors L21, L22 with a coupling coefficient k. The second inductors L21, L22 may be connected in series between the first capacitor C1 and the second capacitor C2, and a node to which the second inductors L21, L22 are connected may be connected to the terminal T13. The third inductors L31, L32 may be connected in series between the first capacitor C1 and the second capacitor C2, and a node to which the second inductors L31, L32 are connected may be connected to the terminal T23. The fourth inductors L41 and L42 may be connected in series between the terminals T21 and T22 and inductively coupled to the third inductors L31 and L32 with a coupling coefficient k. The terminals T13 and T23 may be connected to low impedance nodes, respectively. For example, the terminal T13 may be biased to a first voltage, and the terminal T23 may be biased to a second voltage. Thus, a current flowing in through the terminal T23 due to a large change in the second voltage may be output through the terminal T13, and an excessive current may be prevented from flowing in to the transmitter 120.

[0064] 9C, the galvanic isolator 800c may also include a first capacitor C1, a second capacitor C2, first inductors L11 and L12, second inductors L21 and L22, and third inductors L31 and L32. The first inductors L11 and L12 may be connected in series between terminals T11 and T12, and a node to which the first inductors L11 and L12 are connected may be connected to a terminal T13. The second inductors L21 and L22 may be inductively coupled to the third inductors L31 and L32 with a coupling coefficient k, and a node to which the second inductors L21 and L22 are connected may be connected to a terminal T23. The third inductors L31 and L32 may be connected in series between terminals T21 and T22. The terminals T13 and T23 may each be connected to a low impedance node. For example, terminal T13 may be biased to a first voltage and terminal T23 may be biased to a second voltage such that a current flowing in through terminal T23 due to a large change in the second voltage may be output through terminal T13, thereby preventing excessive current from flowing in to transmitter 120. In some embodiments, transmitter 120 may be coupled to terminals T21 and T22, and receiver 160 may be coupled to terminals T11 and T12.

[0065] 10A and 10B are circuit diagrams illustrating an example of a galvanic isolator according to an exemplary embodiment of the present disclosure. For example, the circuit diagrams in Fig. 10A and 10B show an equivalent circuit of the galvanic isolator 140 in Fig. 2. As shown in Fig. 10A and 10B, each of the galvanic isolators 900a and 900b also includes mutually inductively coupled inductors. In the following, in the description of Fig. 10A and Fig. 10B, the overlapping contents are omitted.

[0066] 10A, the galvanic isolator 900a may also include first inductors L11 and L12 connected in series between terminals T11 and T12, and second inductors L21 and L22 connected in series between terminals T21 and T22. The first inductors L11 and L12 may be inductively coupled to the second inductors L21 and L22 with a coupling coefficient k. As shown in FIG. 10A, a node to which the first inductors L11 and L12 are connected may be connected to the terminal T13, and a node to which the second inductors L21 and L22 are connected may be connected to the terminal T23. The terminals T13 and T23 may each be connected to a low impedance node. For example, the terminal T13 may be biased to a first voltage, and the terminal T23 may be biased to a second voltage. As a result, the current flowing in through the terminal T23 due to a large change in the second voltage is output through the terminal T13, and an excessive current flowing in to the transmitter 120 can be prevented.

[0067] 10B, the galvanic separator 900b may also include first inductors L11 and L12, second inductors L21 and L22, third inductors L31 and L32, and fourth inductors L41 and L42. The first inductors L11 and L12 may be connected in series between the terminals T11 and T12, and may be inductively coupled to the second inductors L21 and L22 with a coupling coefficient k. The second inductors L21 and L22 may be connected in parallel with the third inductors L31 and L32, and the third inductors L31 and L32 may be inductively coupled to the fourth inductors L41 and L42 with a coupling coefficient k. The fourth inductors L41 and L42 may be connected in series between the terminals T21 and T22. 10B, a node to which the first inductors L11 and L12 are connected may be connected to a terminal T13, and a node to which the fourth inductors L41 and L42 are connected may be connected to a terminal T23. The terminals T13 and T23 may be respectively connected to low impedance nodes. For example, the terminal T13 may be biased to a first voltage, and the terminal T23 may be biased to a second voltage. Thus, a current flowing in through the terminal T23 due to a large change in the second voltage may be output through the terminal T13, and excessive current may be prevented from flowing in to the transmitter 120.

[0068] Fig. 11 is a diagram showing a layout 1000 of an apparatus according to an exemplary embodiment of the present disclosure. For example, Fig. 11 shows a plan view of a layout 1000 corresponding to the first inductors L11 and L12 of Fig. 9A and Fig. 9C, or the second inductors L21 and L22 of Fig. 9A. In the following, Fig. 11 will be described with reference to Fig. 9A.

[0069] 11, the layout 1000 also includes patterns forming the first inductors L11 and L12 or the second inductors L21 and L22 of the galvanic isolator 800a. The first pattern P1 and the second pattern P2 of the conductive layer Mx may correspond to the first inductors L11 and L12 connected in series with each other, or the second inductors L21 and L22 connected in series with each other, respectively. The third pattern P3 of the conductive layer Mx may be connected to the first pattern P1 and the second pattern P2 and may correspond to the terminal T13 or the terminal T23. The fourth pattern P4 of the conductive layer Mb may be connected to the first pattern P1 of the conductive layer Mx and may be connected to the first capacitor C1 and the terminal T11. The fifth pattern P5 of the conductive layer Mb may be connected to the second pattern P2 of the conductive layer Mx and may be connected to the second capacitor C2 and the terminal T12.

[0070] Fig. 12 is a drawing showing a layout 1100 of an apparatus according to an exemplary embodiment of the present disclosure. For example, Fig. 12 shows a plan view of a layout 1100 corresponding to the first inductors L11, L12 and the second inductors L21, L22 of Fig. 9B, Fig. 10A and Fig. 10B, the third inductors L31, L32 and the fourth inductors L41, L42 of Fig. 9B and Fig. 10B, or the second inductors L21, L22 and the third inductors L31, L32 of Fig. 9C. In the following, Fig. 12 will be described with reference to Fig. 10A.

[0071] 12, the layout 1100 also includes patterns forming the first inductors L11, L12 and the second inductors L21, L22 of the galvanic isolator 900a. The first pattern P1 and the second pattern P2 of the conductive layer Mx may correspond to the first inductors L11, L12, respectively, which are connected in series with each other. The third pattern P3 and the fourth pattern P4 of the conductive layer Ma may correspond to the second inductors L21, L22, respectively, which are connected in series with each other. The fifth pattern P5 of the conductive layer Mx may be connected to the first pattern P1 and the second pattern P2, and may correspond to the terminal T13. The sixth pattern P6 of the conductive layer Ma may be connected to the third pattern P3 and the fourth pattern P4, and may correspond to the terminal T23. The seventh pattern P7 of the conductive layer My may be connected to the first pattern P1, and may correspond to the terminal T11. The eighth pattern P8 of the conductive layer My may be connected to the second pattern P2, and may correspond to the terminal T12. The ninth pattern P9 of the conductive layer Mb may be connected to the third pattern P3 and may correspond to the terminal T21. The tenth pattern P10 of the conductive layer Mb may be connected to the fourth pattern P4 and may correspond to the terminal T22.

[0072] As described above, the exemplary embodiment has been disclosed with the drawings and the specification. In this specification, the present embodiment has been described using specific terms, but these terms are merely used for the purpose of describing the technical idea of ​​the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, a person having ordinary skill in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical scope of protection of the present disclosure is defined by the technical idea of ​​the claims. [Explanation of symbols]

[0073] 10 High voltage gate drive circuit 11 Rising Edge Pulse Generator 12 Falling Edge Pulse Generator 13 Pulse input detector 14 SR Latch 15 Gate Driver 51 First area 52 Second area 53 Third area 100 devices 120 Transmitter 122 Modulator 140 Galvanic Separator 160 Receiver 162 Demodulator

Claims

1. a first region on the substrate, the first region including a first integrated circuit; a second region on the substrate including a second integrated circuit; a third region on the substrate between the first region and the second region, 11. The apparatus of claim 10, wherein at least one of the first region and the second region includes at least one pattern on the substrate that provides galvanic isolation between the first integrated circuit and the second integrated circuit.

2. The at least one pattern is a first pattern and a second pattern in a first conductive layer, the first pattern and the second pattern corresponding to a first electrode of a first capacitor and a first electrode of a second capacitor, respectively; 2. The device of claim 1, further comprising: a third pattern and a fourth pattern in a second conductive layer, the third pattern and the fourth pattern corresponding to a second electrode of the first capacitor and a second electrode of the second capacitor, respectively.

3. The at least one pattern is a fifth pattern and a sixth pattern in the first conductive layer, the fifth pattern and the sixth pattern corresponding to a first electrode of a third capacitor and a first electrode of a fourth capacitor, respectively; the second conductive layer further includes a seventh pattern and an eighth pattern corresponding to a second electrode of the third capacitor and a second electrode of the fourth capacitor, respectively; the first pattern to the fourth pattern are included in the first region, the fifth pattern to the eighth pattern are included in the second region, the first pattern and the fifth pattern are electrically connected to each other via a pattern crossing the third region; The device of claim 2 , wherein the second pattern and the sixth pattern are electrically connected to each other via a pattern that crosses the third region.

4. a first inductor and a second inductor connected in series between the first electrode of the first capacitor and the first electrode of the second capacitor, 3. The apparatus of claim 2, wherein a node to which the first inductor and the second inductor are coupled is biased to a first voltage.

5. a third inductor inductively coupled to the first inductor; 5. The apparatus of claim 4, further comprising a fourth inductor inductively coupled to the second inductor.

6. The at least one pattern is a first pattern and a second pattern in a first conductive layer, the first pattern and the second pattern corresponding to a first electrode of the first capacitor and a second electrode of the second capacitor, respectively; 2. The device of claim 1, further comprising: a third pattern and a fourth pattern in a second conductive layer, the third pattern and the fourth pattern corresponding to a second electrode of the first capacitor and a second electrode of the second capacitor, respectively.

7. The at least one pattern is a first pattern and a second pattern corresponding to a first inductor and a second inductor connected in series in a first conductive layer, respectively; 2. The device of claim 1 , further comprising: a third pattern and a fourth pattern corresponding to a third inductor and a fourth inductor, respectively, connected in series on a second conductive layer and inductively coupled to the first inductor and the second inductor, respectively.

8. a node to which the first inductor and the second inductor are connected is biased to a first voltage; 8. The apparatus of claim 7, wherein a node to which the third inductor and the fourth inductor are coupled is biased to a second voltage.

9. The at least one pattern is a fifth pattern and a sixth pattern corresponding to a fifth inductor and a sixth inductor connected in series in the first conductive layer, respectively; a seventh pattern and an eighth pattern corresponding to a seventh inductor and an eighth inductor, respectively, connected in series in the second conductive layer and inductively coupled to the fifth inductor and the sixth inductor, the first pattern to the fourth pattern are included in the first region, the fifth pattern to the eighth pattern are included in the second region, the first pattern and the fifth pattern are electrically connected to each other via a pattern crossing the third region; The device of claim 7 , wherein the second pattern and the sixth pattern are electrically connected to each other via a pattern that crosses the third region.

10. a node to which the first inductor and the second inductor are connected is biased to a first voltage; 10. The apparatus of claim 9, wherein a node to which the fifth inductor and the sixth inductor are coupled is biased to a second voltage.

11. 2. The device of claim 1, wherein the third region surrounds the second region on the substrate.

12. The third region is a first doping region on the substrate surrounding the second region; a second doped region on the substrate surrounding the first doped region; a third doped region on the substrate surrounding the second doped region; the second doped region and the third doped region are biased to a first potential; 12. The device of claim 11, wherein the second doped region is electrically floating.

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