Semiconductor device

Abstract

To provide a semiconductor device having small circuit area and consuming less power.SOLUTION: The semiconductor device comprises first to fourth cells, a current mirror circuit and first to fourth wires. Each of the first to fourth cells includes a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wire is electrically connected to the first terminals of the second transistors of the first cell and the second cell. The second wire is electrically connected to first terminals of the second transistors of the third cell and the fourth cell. The third wire is electrically connected to second terminals of the capacitors of the first cell and the third cell. The fourth wire is electrically connected to second terminals of the capacitors of the second cell and the fourth cell. The current mirror circuit is electrically connected to the first wire and the second wire.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specific examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, sensors, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] Currently, active development is underway on integrated circuits that mimic the workings of the human brain. These integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with significantly less power consumption than von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network with "neurons" and "synapses" is called an artificial neural network (ANN). By using an artificial neural network, it is possible to make inferences with accuracy comparable to or even exceeding that of humans. In an artificial neural network, the main operation is the weighted sum of neuron outputs, i.e., the sum-of-products operation.

[0005] For example, Patent Document 1 discloses an invention that uses a memory cell that uses an OS transistor (sometimes referred to as an oxide semiconductor transistor) as a circuit that performs a product-sum operation. An OS transistor is a transistor that has a metal oxide semiconductor in its channel formation region, and it has been reported that its off-state current is extremely small (for example, Non-Patent Documents 1 and 2). In addition, various semiconductor devices that use OS transistors have been manufactured (for example, Non-Patent Documents 3 and 4). The manufacturing process of an OS transistor can be incorporated into a CMOS process for a conventional Si transistor (a transistor that contains Si in its channel formation region), and the OS transistor can be stacked on the Si transistor (for example, Non-Patent Document 4). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-168099 [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “Properties of crystalline In-Ga-Zn-oxide semiconductor and its transistor characteristics,” Jpn.J.Appl.Phys.,vol.53,04ED18(2014). [Non-patent document 2] K. Kato et al., “Evaluation of Off-State Current Characteristics of Transistor Using Oxide Semiconductor Material, Indium-Gallium-Zinc Oxide,” Jpn.J.Appl.Phys., vol. 51, 021201 (2012). [Non-patent document 3] S. Amano et al., “Low Power LC Display Using In-Ga-Zn-Oxide TFTs Based on Variable Frame Frequency,” SID Symp. Dig. Papers, vol. 41, pp. 626-629 (2010). [Non-patent document 4] T. Ishizu et al., “Embedded Oxide Semiconductor Memories: A Key Enabler for Low-Power ULSI,” ECS Tran., vol.79, pp.149-156 (2017). Summary of the Invention [Problem to be solved by the invention]

[0008] When a multiply-and-accumulate operation is performed using a digital circuit, a digital multiplier circuit multiplies digital data (multiplier data) that serves as a multiplier by digital data (multiplicand data) that serves as a multiplicand. Then, a digital adder circuit adds the digital data (product data) obtained by the multiplication, and obtains digital data (product-and-accumulate data) as the result of the multiply-and-accumulate operation. It is preferable that the digital multiplier circuit and the digital adder circuit are capable of handling multi-bit operations. However, in this case, the circuit size of each of the digital multiplier circuit and the digital adder circuit may become large, which may lead to an increase in the circuit area and power consumption of the entire operation circuit.

[0009] In addition, in artificial neural networks, in addition to product-sum operations, activation function operations are also performed. If the activation function operations are performed using digital circuits, as described above, this may lead to an increase in the overall circuit area and power consumption of the operation circuit. Furthermore, if the product-sum operations are performed using analog circuits rather than digital multiplication circuits and digital addition circuits, the operation results output by the analog circuits are analog signals. Therefore, the analog signals must be converted to digital signals before being input to the digital circuit that performs the activation function operations. Furthermore, since the digital circuits output the activation function operation results as digital signals, the digital signals must be converted to analog signals before being input to the analog circuit to perform a product-sum operation again. In particular, in artificial neural networks, product-sum operations and activation function operations are repeatedly performed, and therefore, in circuits that combine analog and digital circuits, digital-to-analog signal conversion is frequently performed. This may also increase the power consumption of circuits that convert between digital and analog signals.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device capable of performing a product-sum operation and / or an activation function operation, or to provide a semiconductor device with low power consumption.

[0011] Another object of one embodiment of the present invention is to provide a novel semiconductor device or an electronic device including the semiconductor device.

[0012] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0013] (1) One aspect of the present invention is a semiconductor device having a first cell, a second cell, a third cell, a fourth cell, a current mirror circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring. Each of the first cell, the second cell, the third cell, and the fourth cell has a first transistor, a second transistor, and a capacitor. In each of the first cell, the second cell, the third cell, and the fourth cell, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. A first terminal of the second transistor of the first cell is electrically connected to the first wiring, and a second terminal of the capacitor of the first cell is electrically connected to the third wiring. A first terminal of the second transistor of the second cell is electrically connected to the first wiring, and a second terminal of the capacitor of the second cell is electrically connected to the fourth wiring. A first terminal of the second transistor of the third cell is electrically connected to the second wiring, and a second terminal of the capacitance of the third cell is electrically connected to the third wiring. A first terminal of the second transistor of the fourth cell is electrically connected to the second wiring, and a second terminal of the capacitance of the fourth cell is electrically connected to the fourth wiring. A current mirror circuit is electrically connected to the first wiring and the second wiring, and has a function of flowing a current corresponding to the potential of the first wiring to the second wiring. The first data is determined according to the difference between the first potential and the second potential, and the second data is determined according to the difference between the third potential and the fourth potential. The first cell has a function of holding a first potential at the first terminal of the capacitance of the first cell, the second cell has a function of holding a second potential at the first terminal of the capacitance of the second cell, the third cell has a function of holding a second potential at the first terminal of the capacitance of the third cell, and the fourth cell has a function of holding a first potential at the first terminal of the capacitance of the fourth cell. When a third potential is input to the third wiring and a fourth potential is input to the fourth wiring, the amount of current flowing from the current mirror circuit to the second wiring minus the amount of current flowing from the second wiring to the first terminal of the second transistor of the third cell and the amount of current flowing from the second wiring to the first terminal of the second transistor of the fourth cell is an amount corresponding to the product of the first data and the second data.

[0014] (2) Alternatively, one aspect of the present invention is a semiconductor device including m (m is an integer equal to or greater than 1) first cells, m second cells, m third cells, m fourth cells, a current mirror circuit, a first wiring, a second wiring, m third wirings, and m fourth wirings. Each of the m first cells, the m second cells, the m third cells, and the m fourth cells includes a first transistor, a second transistor, and a capacitor. In each of the m first cells, the m second cells, the m third cells, and the m fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and to a gate of the second transistor. A first terminal of the second transistor of each of the m first cells is electrically connected to the first wiring, and a second terminal of the capacitor of the ith (i is an integer equal to or greater than 1 and equal to or less than m) first cell is electrically connected to the ith third wiring. The first terminal of the second transistor of each of the m second cells is electrically connected to the first wiring, and the second terminal of the capacitance of the i-th second cell is electrically connected to the i-th fourth wiring. The first terminal of the second transistor of each of the m third cells is electrically connected to the second wiring, and the second terminal of the capacitance of the i-th third cell is electrically connected to the i-th third wiring. The first terminal of the second transistor of each of the m fourth cells is electrically connected to the second wiring, and the second terminal of the capacitance of the i-th fourth cell is electrically connected to the i-th fourth wiring. The current mirror circuit is electrically connected to the first wiring and the second wiring, and has the function of flowing a current according to the potential of the first wiring to the second wiring. In each of the first cell and the third cell electrically connected to the i-th third wiring, the first cell connects V to the first terminal of the capacitance of the first cell. Wα The third cell has the function of maintaining the potential of [i], and the first terminal of the third cell's capacitance is V Wβ [i]. In each of the second cell and the fourth cell electrically connected to the i-th fourth wiring, the second cell has a function of connecting V to the first terminal of the capacitance of the second cell. Wβ The fourth cell has the function of maintaining the potential of [i], and the first terminal of the fourth cell's capacitance is V Wα It has the function of maintaining the potential of [i]. VXα The potential of [i] is input, and V is applied to the i-th fourth wire. Xβ When the potential [i] is input, the amount of current flowing from the current mirror circuit to the second wiring minus the sum of the amount of current flowing from the second wiring to the first terminals of the second transistors of each of the m third cells, and the sum of the amount of current flowing from the second wiring to the first terminals of the second transistors of each of the m fourth cells, is an amount corresponding to the value of equation (A1).

[0015]

number

[0016] (3) Another embodiment of the present invention is a semiconductor device including a first cell, a second cell, a third cell, a fourth cell, a first current source, a second current source, a subtraction circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring. Each of the first cell, the second cell, the third cell, and the fourth cell includes a first transistor, a second transistor, and a capacitor. In each of the first cell, the second cell, the third cell, and the fourth cell, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. A first terminal of the second transistor of the first cell is electrically connected to the first wiring, and a second terminal of the capacitor of the first cell is electrically connected to the third wiring. A first terminal of the second transistor of the second cell is electrically connected to the first wiring, and a second terminal of the capacitor of the second cell is electrically connected to the fourth wiring. A first terminal of the second transistor of the third cell is electrically connected to the second wiring, and a second terminal of the capacitor of the third cell is electrically connected to the third wiring. A first terminal of the second transistor of the fourth cell is electrically connected to the second wiring, and a second terminal of the capacitor of the fourth cell is electrically connected to the fourth wiring. A first current source is electrically connected to the first wiring, and a second current source is electrically connected to the second wiring. The amount of current flowing from the first current source to the first wiring is 0.9 to 1.1 times the amount of current flowing from the second current source to the second wiring. A first input terminal of the subtraction circuit is electrically connected to the first wiring, and a second input terminal of the subtraction circuit is electrically connected to the second wiring. The first data is determined according to the difference between the first potential and the second potential, and the second data is determined according to the difference between the third potential and the fourth potential. The first cell has a function of holding a first potential at a first terminal of the capacitance of the first cell, the second cell has a function of holding a second potential at a first terminal of the capacitance of the second cell, the third cell has a function of holding a second potential at a first terminal of the capacitance of the third cell, and the fourth cell has a function of holding a first potential at a first terminal of the capacitance of the fourth cell.By inputting a third potential to the third wiring and a fourth potential to the fourth wiring, the amount of current obtained by subtracting the sum of the amounts of current flowing from the first wiring to the first terminals of the second transistors of the first cell and the second cell from the amount of current flowing from the first current source to the first wiring is input to the first input terminal of the subtraction circuit, and the amount of current obtained by subtracting the sum of the amounts of current flowing from the second wiring to the first terminals of the second transistors of the third cell and the fourth cell from the amount of current flowing from the second current source to the second wiring is input to the second input terminal of the subtraction circuit, thereby outputting a voltage corresponding to the product of the first data and the second data from the output terminal of the subtraction circuit.

[0017] (4) One aspect of the present invention is a semiconductor device having m (m is an integer greater than or equal to 1) first cells, m second cells, m third cells, m fourth cells, a first current source, a second current source, a subtraction circuit, a first wiring, a second wiring, m third wirings, and m fourth wirings. Each of the m first cells, the m second cells, the m third cells, and the m fourth cells has a first transistor, a second transistor, and a capacitor. In each of the first cells, the m second cells, the m third cells, and the m fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first terminal of the second transistor of each of the m first cells is electrically connected to the first wiring, and the second terminal of the capacitor of the i-th first cell (i is an integer greater than or equal to 1 and less than or equal to m) is electrically connected to the i-th third wiring. The first terminal of the second transistor of each of the m second cells is electrically connected to the first wiring, and the second terminal of the capacitor of the i-th second cell is electrically connected to the i-th fourth wiring. The first terminal of the second transistor of each of the m third cells is electrically connected to the second wiring, and the second terminal of the capacitor of the i-th third cell is electrically connected to the i-th third wiring. The first terminal of the second transistor of each of the m fourth cells is electrically connected to the second wiring, and the second terminal of the capacitor of the i-th fourth cell is electrically connected to the i-th fourth wiring. The first current source is electrically connected to the first wiring, and the second current source is electrically connected to the second wiring. The amount of current that the first current source passes through the first wiring is 0.9 to 1.1 times the amount of current that the second current source passes through the second wiring. The first input terminal of the subtraction circuit is electrically connected to the first wiring, and the second input terminal of the subtraction circuit is electrically connected to the second wiring. In each of the first cell and the third cell that are electrically connected to the i-th third wiring, the first cell connects V to the first terminal of the capacitance of the first cell. Wα The third cell has the function of maintaining the potential of [i], and the first terminal of the third cell's capacitance is V Wβ In each of the second cell and the fourth cell electrically connected to the i-th fourth wiring, the second cell has a function of maintaining the potential of [i]. WβThe fourth cell has the function of maintaining the potential of [i], and the first terminal of the fourth cell's capacitance is V Wα It has the function of maintaining the potential of [i]. V Xα The potential of [i] is input, and V is applied to the i-th fourth wire. Xβ By inputting the potential [i], the amount of current obtained by subtracting the sum of the amounts of current flowing from the first wiring from the first current source to the first terminals of the second transistors of the m first cells and the second cell is input to the first input terminal of the subtraction circuit, and the amount of current obtained by subtracting the sum of the amounts of current flowing from the second wiring from the second current source to the first terminals of the m second transistors of the third cell and the fourth cell is input to the second input terminal of the subtraction circuit. As a result, a voltage according to the value of equation (A2) is output from the output terminal of the subtraction circuit.

[0018]

number

[0019] (5) Another aspect of the present invention is a semiconductor device having a first cell, a second cell, a third cell, a fourth cell, a first wiring, a second wiring, and a third wiring. Each of the first cell, the second cell, the third cell, and the fourth cell includes a first transistor, a second transistor, and a capacitor. In each of the first cell, the second cell, the third cell, and the fourth cell, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor, and the gate of the first transistor is electrically connected to the first wiring. In addition, the second wiring is electrically connected to a second terminal of the first transistor of the first cell and a second terminal of the first transistor of the fourth cell, and the third wiring is electrically connected to a second terminal of the first transistor of the second cell and a second terminal of the first transistor of the third cell.

[0020] (6) Alternatively, one embodiment of the present invention is a semiconductor device having a first cell, a second cell, a third cell, a fourth cell, a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a sixth wiring, and a seventh wiring. Each of the first cell, the second cell, the third cell, and the fourth cell includes a first transistor, a second transistor, and a capacitor. In each of the first cell, the second cell, the third cell, and the fourth cell, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. A first terminal of the second transistor of the first cell is electrically connected to the fourth wiring, a second terminal of the capacitor of the first cell is electrically connected to the sixth wiring, a second terminal of the first transistor of the first cell is electrically connected to the second wiring, and a gate of the first transistor of the first cell is electrically connected to the first wiring. A first terminal of the second transistor of the second cell is electrically connected to the fourth wiring, a second terminal of the capacitance of the second cell is electrically connected to the seventh wiring, a second terminal of the first transistor of the second cell is electrically connected to the third wiring, and a gate of the first transistor of the second cell is electrically connected to the first wiring. A first terminal of the second transistor of the third cell is electrically connected to the fifth wiring, a second terminal of the capacitance of the third cell is electrically connected to the sixth wiring, a second terminal of the first transistor of the third cell is electrically connected to the third wiring, and a gate of the first transistor of the third cell is electrically connected to the first wiring. A first terminal of the second transistor of the fourth cell is electrically connected to the fifth wiring, a second terminal of the capacitance of the fourth cell is electrically connected to the seventh wiring, a second terminal of the first transistor of the fourth cell is electrically connected to the second wiring, and a gate of the first transistor of the fourth cell is electrically connected to the first wiring.

[0021] (7) Alternatively, in one embodiment of the present invention, in the above-described (6), a current mirror circuit is preferably provided. The current mirror circuit is preferably electrically connected to the fourth wiring and the fifth wiring. Note that the current mirror circuit has a function of causing a current corresponding to the potential of the fourth wiring to flow to the fifth wiring.

[0022] (8) Alternatively, according to one aspect of the present invention, in the above-mentioned (7), it is preferable that the first data and the second data are multiplied. Note that the first data is determined according to a difference between the first potential and the second potential, and the second data is determined according to a difference between the third potential and the fourth potential. Furthermore, the first cell has a function of holding the first potential at a first terminal of the capacitance of the first cell, the second cell has a function of holding the second potential at a first terminal of the capacitance of the second cell, the third cell has a function of holding the second potential at a first terminal of the capacitance of the third cell, and the fourth cell has a function of holding the first potential at a first terminal of the capacitance of the fourth cell. When the third potential is input to the sixth wiring and the fourth potential is input to the seventh wiring, the amount of current obtained by subtracting the amount of current flowing from the fifth wiring to the first terminal of the second transistor of the third cell and the amount of current flowing from the fifth wiring to the first terminal of the second transistor of the fourth cell from the amount of current flowing from the current mirror circuit to the fifth wiring is an amount corresponding to the product of the first data and the second data.

[0023] (9) Alternatively, in one aspect of the present invention, in the above (6), the circuit preferably includes a first current source, a second current source, and a subtraction circuit. Preferably, the first current source is electrically connected to the fourth wiring, and the second current source is electrically connected to the fifth wiring. Preferably, the first input terminal of the subtraction circuit is electrically connected to the fourth wiring, and the second input terminal of the subtraction circuit is electrically connected to the fifth wiring. Preferably, the amount of current flowing from the first current source to the fourth wiring is 0.9 to 1.1 times the amount of current flowing from the second current source to the fifth wiring.

[0024] (10) Alternatively, according to one embodiment of the present invention, in the above (9), it is preferable that the first data and the second data are multiplied. Note that the first data is determined according to a difference between a first potential and a second potential, and the second data is determined according to a difference between a third potential and a fourth potential. Furthermore, the first cell has a function of holding the first potential at a first terminal of a capacitance of the first cell, the second cell has a function of holding the second potential at a first terminal of a capacitance of the second cell, the third cell has a function of holding the second potential at a first terminal of a capacitance of the third cell, and the fourth cell has a function of holding the first potential at a first terminal of a capacitance of the fourth cell. By inputting the third potential to the sixth wire and the fourth potential to the seventh wire, the amount of current obtained by subtracting the sum of the amounts of current flowing from the fourth wire to the first terminals of the second transistors of the first cell and the second cell from the amount of current flowing from the first current source to the fourth wire is input to the first input terminal of the subtraction circuit, and the amount of current obtained by subtracting the sum of the amounts of current flowing from the fifth wire to the first terminals of the second transistors of the third cell and the fourth cell from the amount of current flowing from the second current source to the fifth wire is input to the second input terminal of the subtraction circuit. As a result, a voltage corresponding to the product of the first data and the second data is output from the output terminal of the subtraction circuit.

[0025] (11) Alternatively, one aspect of the present invention is a semiconductor device having m (m is an integer greater than or equal to 1) first cells, m second cells, m third cells, m fourth cells, a current mirror circuit, m first wirings, second wirings, third wirings, fourth wirings, fifth wirings, m sixth wirings, and m seventh wirings. Each of the m first cells, the m second cells, the m third cells, and the m fourth cells includes a first transistor, a second transistor, and a capacitor. In each of the m first cells, the m second cells, the m third cells, and the m fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. A first terminal of the second transistor of each of the m first cells is electrically connected to the fourth wiring, a second terminal of the capacitor of the i-th first cell (i is an integer greater than or equal to 1 and less than or equal to m) is electrically connected to the i-th sixth wiring, a second terminal of the first transistor of each of the m first cells is electrically connected to the second wiring, and a gate of the first transistor of the i-th first cell is electrically connected to the i-th first wiring. A first terminal of the second transistor of each of the m second cells is electrically connected to the fourth wiring, a second terminal of the capacitor of the i-th second cell is electrically connected to the i-th seventh wiring, a second terminal of the first transistor of each of the m second cells is electrically connected to the third wiring, and a gate of the first transistor of the i-th second cell is electrically connected to the i-th first wiring. A first terminal of the second transistor of each of the m third cells is electrically connected to the fifth wiring, a second terminal of the capacitor of the i-th third cell is electrically connected to the i-th sixth wiring, a second terminal of the first transistor of each of the m third cells is electrically connected to the third wiring, and a gate of the first transistor of the i-th third cell is electrically connected to the i-th first wiring. A first terminal of the second transistor of each of the m fourth cells is electrically connected to the fifth wiring, a second terminal of the capacitor of the i-th fourth cell is electrically connected to the i-th seventh wiring, a second terminal of the first transistor of each of the m fourth cells is electrically connected to the second wiring, and a gate of the first transistor of the i-th fourth cell is electrically connected to the i-th first wiring.Furthermore, the current mirror circuit is electrically connected to the fourth wiring and the fifth wiring. The current mirror circuit has a function of passing a current corresponding to the potential of the fourth wiring to the fifth wiring. In addition, in each of the first cell and the third cell electrically connected to the i-th sixth wiring, the first cell connects V to the first terminal of the capacitance of the first cell. Wα The third cell has the function of maintaining the potential of [i], and the first terminal of the third cell's capacitance is V Wβ [i]. In each of the second cell and the fourth cell electrically connected to the i-th seventh wiring, the second cell has a function of connecting V to the first terminal of the capacitance of the second cell. Wβ The fourth cell has the function of maintaining the potential of [i], and the first terminal of the fourth cell's capacitance is V Wα It has the function of maintaining the potential of [i]. V Xα The potential of [i] is input, and V is applied to the i-th 7th wire. Xβ When the potential [i] is input, the amount of current flowing from the current mirror circuit to the fifth wiring minus the sum of the amount of current flowing from the fifth wiring to the first terminals of the second transistors of each of the m third cells, and the sum of the amount of current flowing from the fifth wiring to the first terminals of the second transistors of each of the m fourth cells, is an amount corresponding to the value of equation (A3).

[0026]

number

[0027] (12) Alternatively, one embodiment of the present invention is a semiconductor device including m (m is an integer equal to or greater than 1) first cells, m second cells, m third cells, m fourth cells, a first current source, a second current source, a subtraction circuit, m first wirings, second wirings, third wirings, fourth wirings, fifth wirings, m sixth wirings, and m seventh wirings. Each of the m first cells, the m second cells, the m third cells, and the m fourth cells includes a first transistor, a second transistor, and a capacitor. In each of the m first cells, the m second cells, the m third cells, and the m fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. A first terminal of the second transistor of each of the m first cells is electrically connected to the fourth wiring, a second terminal of the capacitor of the i-th first cell (i is an integer greater than or equal to 1 and less than or equal to m) is electrically connected to the i-th sixth wiring, a second terminal of the first transistor of each of the m first cells is electrically connected to the second wiring, and a gate of the first transistor of the i-th first cell is electrically connected to the i-th first wiring. A first terminal of the second transistor of each of the m second cells is electrically connected to the fourth wiring, a second terminal of the capacitor of the i-th second cell is electrically connected to the i-th seventh wiring, a second terminal of the first transistor of each of the m second cells is electrically connected to the third wiring, and a gate of the first transistor of the i-th second cell is electrically connected to the i-th first wiring. A first terminal of the second transistor of each of the m third cells is electrically connected to the fifth wiring, a second terminal of the capacitor of the i-th third cell is electrically connected to the i-th sixth wiring, a second terminal of the first transistor of each of the m third cells is electrically connected to the third wiring, and a gate of the first transistor of the i-th third cell is electrically connected to the i-th first wiring. A first terminal of the second transistor of each of the m fourth cells is electrically connected to the fifth wiring, a second terminal of the capacitor of the i-th fourth cell is electrically connected to the i-th seventh wiring, a second terminal of the first transistor of each of the m fourth cells is electrically connected to the second wiring, and a gate of the first transistor of the i-th fourth cell is electrically connected to the i-th first wiring.Furthermore, the first current source is electrically connected to the fourth wiring, and the second current source is electrically connected to the fifth wiring. The amount of current that the first current source passes through the fourth wiring is 0.9 to 1.1 times the amount of current that the second current source passes through the fifth wiring. The first input terminal of the subtraction circuit is electrically connected to the fourth wiring, and the second input terminal of the subtraction circuit is electrically connected to the fifth wiring. In each of the first and third cells electrically connected to the i-th sixth wiring, the first cell connects V to a first terminal of the capacitance of the first cell. Wα The third cell has the function of maintaining the potential of [i], and the first terminal of the third cell's capacitance is V Wβ [i]. In each of the second cell and the fourth cell electrically connected to the i-th seventh wiring, the second cell has a function of connecting V to the first terminal of the capacitance of the second cell. Wβ The fourth cell has the function of maintaining the potential of [i], and the first terminal of the fourth cell's capacitance is V Wα It has the function of maintaining the potential of [i]. V Xα The potential of [i] is input, and V is applied to the i-th 7th wire. Xβ By inputting the potential [i], the amount of current obtained by subtracting the sum of the amounts of current flowing from the fourth wire to the first terminals of the second transistors of the m first cells and the second cell from the amount of current flowing from the first current source to the fourth wire is input to the first input terminal of the subtraction circuit, and the amount of current obtained by subtracting the sum of the amounts of current flowing from the second current source to the fifth wire to the first terminals of the second transistors of the m third cells and the fourth cell from the amount of current flowing from the second current source to the fifth wire is input to the second input terminal of the subtraction circuit. As a result, a voltage according to the value of equation (A4) is output from the output terminal of the subtraction circuit.

[0028]

number

[0029] (13) Another embodiment of the present invention is a semiconductor device including a first cell, a second cell, a third cell, a fourth cell, a first current mirror circuit, a second current mirror circuit, and a third current mirror circuit. Each of the first cell, the second cell, the third cell, and the fourth cell includes a first transistor, a second transistor, and a capacitor. In each of the first cell, the second cell, the third cell, and the fourth cell, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. A gate of the first transistor of the first cell is electrically connected to a gate of the first transistor of the second cell, a gate of the first transistor of the third cell, and a gate of the first transistor of the fourth cell. A first terminal of the first current mirror circuit is electrically connected to a first terminal of the second transistor of the first cell, and a second terminal of the first current mirror circuit is electrically connected to a first terminal of the second transistor of the fourth cell. The first terminal of the second current mirror circuit is electrically connected to the first terminal of the second transistor of the third cell, and the second terminal of the second current mirror circuit is electrically connected to the first terminal of the second transistor of the second cell. The first terminal of the third current mirror circuit is electrically connected to the first terminal of the second transistor of the second cell, and the second terminal of the third current mirror circuit is electrically connected to the first terminal of the second transistor of the fourth cell. The first current mirror circuit has a function of flowing a current corresponding to the potential of the first terminal of the first current mirror circuit from the first and second terminals of the first current mirror circuit to the outside. The second current mirror circuit has a function of flowing a current corresponding to the potential of the first terminal of the second current mirror circuit from the first and second terminals of the second current mirror circuit to the outside. The third current mirror circuit has a function of flowing a current corresponding to the potential of the first terminal of the third current mirror circuit from the first and second terminals of the third current mirror circuit to the inside.

[0030] (14) Alternatively, in one aspect of the present invention, in the above (13), it is preferable that the second terminal of the capacitance of the first cell is electrically connected to the second terminal of the capacitance of the third cell, the second terminal of the first transistor of the first cell is electrically connected to the second terminal of the first transistor of the fourth cell, the second terminal of the capacitance of the second cell is electrically connected to the second terminal of the capacitance of the fourth cell, and the second terminal of the first transistor of the second cell is electrically connected to the second terminal of the first transistor of the third cell.

[0031] (15) Alternatively, according to one embodiment of the present invention, in the above (14), it is preferable that the first data and the second data are multiplied. Note that the first data is determined according to a difference between a first potential and a second potential, and the second data is determined according to a difference between a third potential and a fourth potential. Furthermore, the first cell has a function of holding the first potential at a first terminal of a capacitance of the first cell, the second cell has a function of holding the second potential at a first terminal of a capacitance of the second cell, the third cell has a function of holding the second potential at a first terminal of a capacitance of the third cell, and the fourth cell has a function of holding the first potential at a first terminal of a capacitance of the fourth cell. A third potential is input to each of the second terminal of the capacitance of the first cell and the second terminal of the capacitance of the third cell, and a fourth potential is input to each of the second terminal of the capacitance of the second cell and the second terminal of the capacitance of the fourth cell, so that the amount of current obtained by subtracting the amount of current flowing to the first terminal of the second transistor of the fourth cell and the amount of current flowing to the third terminal of the third current mirror circuit from the amount of current flowing from the second terminal of the first current mirror circuit is an amount corresponding to the product of the first data and the second data.

[0032] (16) Another embodiment of the present invention is a semiconductor device including a first cell, a second cell, a third cell, a fourth cell, a first current mirror circuit, a second current mirror circuit, a third current mirror circuit, and a fourth current mirror circuit. Each of the first cell, the second cell, the third cell, and the fourth cell includes a first transistor, a second transistor, and a capacitor. In each of the first cell, the second cell, the third cell, and the fourth cell, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. A gate of the first transistor of the first cell is electrically connected to a gate of the first transistor of the second cell, a gate of the first transistor of the third cell, and a gate of the first transistor of the fourth cell. The first terminal of the first current mirror circuit is electrically connected to the first terminal of the second transistor of the first cell, and the second terminal of the first current mirror circuit is electrically connected to the first terminal of the second transistor of the fourth cell. The first terminal of the second current mirror circuit is electrically connected to the first terminal of the second transistor of the third cell, and the second terminal of the second current mirror circuit is electrically connected to the first terminal of the third current mirror circuit. The second terminal of the third current mirror circuit is electrically connected to the first terminal of the second transistor of the fourth cell. The first terminal of the fourth current mirror circuit is electrically connected to the first terminal of the second transistor of the second cell, and the second terminal of the fourth current mirror circuit is electrically connected to the first terminal of the second transistor of the fourth cell. The first current mirror circuit has a function of flowing a current corresponding to the potential of the first terminal of the first current mirror circuit from the first and second terminals of the first current mirror circuit to the outside. The second current mirror circuit has a function of causing a current corresponding to the potential of the first terminal of the second current mirror circuit to flow from the first and second terminals of the second current mirror circuit to the outside. The third current mirror circuit has a function of causing a current corresponding to the potential of the first terminal of the third current mirror circuit to flow from the first and second terminals of the third current mirror circuit to the inside. The fourth current mirror circuit has a function of causing a current corresponding to the potential of the first terminal of the fourth current mirror circuit to flow from the first and second terminals of the fourth current mirror circuit to the outside.

[0033] (17) Alternatively, in one aspect of the present invention, in the above (16), it is preferable that the second terminal of the capacitance of the first cell is electrically connected to the second terminal of the capacitance of the third cell, the second terminal of the first transistor of the first cell is electrically connected to the second terminal of the first transistor of the fourth cell, the second terminal of the capacitance of the second cell is electrically connected to the second terminal of the capacitance of the fourth cell, and the second terminal of the first transistor of the second cell is electrically connected to the second terminal of the first transistor of the third cell.

[0034] (18) Alternatively, according to one embodiment of the present invention, in the above (17), it is preferable that the first data and the second data are multiplied. Note that the first data is determined according to a difference between a first potential and a second potential, and the second data is determined according to a difference between a third potential and a fourth potential. Furthermore, the first cell has a function of holding the first potential at a first terminal of a capacitance of the first cell, the second cell has a function of holding the second potential at a first terminal of a capacitance of the second cell, the third cell has a function of holding the second potential at a first terminal of a capacitance of the third cell, and the fourth cell has a function of holding the first potential at a first terminal of a capacitance of the fourth cell. A third potential is input to each of the second terminal of the capacitance of the first cell and the second terminal of the capacitance of the third cell, and a fourth potential is input to each of the second terminal of the capacitance of the second cell and the second terminal of the capacitance of the fourth cell, so that the amount of current obtained by subtracting the amount of current flowing to the first terminal of the second transistor of the fourth cell and the amount of current flowing to the third terminal of the third current mirror circuit from the sum of the amount of current flowing from the second terminal of the first current mirror circuit and the amount of current flowing from the second terminal of the fourth current mirror circuit is an amount corresponding to the product of the first data and the second data.

[0035] (19) Another aspect of the present invention is a semiconductor device including a first cell, a second cell, a third cell, a fourth cell, a first wiring, a second wiring, and a third wiring. Each of the first cell, the second cell, the third cell, and the fourth cell includes a first transistor, a second transistor, and a capacitor. In particular, the capacitor included in the second cell and the third cell includes a material that may exhibit ferroelectricity. In each of the first cell, the second cell, the third cell, and the fourth cell, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor, and the gate of the first transistor is electrically connected to the first wiring. Furthermore, the second wiring is electrically connected to a second terminal of the first transistor of the first cell and a second terminal of the first transistor of the fourth cell, and the third wiring is electrically connected to a second terminal of the first transistor of the second cell and a second terminal of the first transistor of the third cell.

[0036] (20) Alternatively, in one aspect of the present invention, in the above (19), the material that can have ferroelectricity is hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0), yttria-stabilized zirconia, barium titanate, PbTiO X It is preferable that the electrode layer 100 has one or more materials selected from the group consisting of lead zirconate titanate, barium strontium titanate, strontium titanate, and strontium bismuthate tantalate.

[0037] (twenty one) Another aspect of the present invention is a semiconductor device including a first cell, a second cell, a third cell, a fourth cell, a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, a sixth wiring, and a seventh wiring. Each of the first cell, the second cell, the third cell, and the fourth cell includes a first transistor, a second transistor, and a capacitor. In particular, the capacitor included in the second cell and the third cell includes a material that may exhibit ferroelectricity. In each of the first cell, the second cell, the third cell, and the fourth cell, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor, and a second terminal of the first transistor of the first cell is electrically connected to the second wiring. The second terminal of the capacitance of the first cell is electrically connected to the sixth wiring, the first terminal of the second transistor of the first cell is electrically connected to the fourth wiring, and the gate of the first transistor of the first cell is electrically connected to the first wiring. The second terminal of the first transistor of the second cell is electrically connected to the third wiring, the second terminal of the capacitance of the second cell is electrically connected to the seventh wiring, the first terminal of the second transistor of the second cell is electrically connected to the fourth wiring, and the gate of the first transistor of the second cell is electrically connected to the first wiring. The second terminal of the first transistor of the third cell is electrically connected to the third wiring, the second terminal of the capacitance of the third cell is electrically connected to the sixth wiring, the first terminal of the second transistor of the third cell is electrically connected to the fifth wiring, and the gate of the first transistor of the third cell is electrically connected to the first wiring. In addition, the second terminal of the first transistor of the fourth cell is electrically connected to the second wiring, the second terminal of the capacitance of the fourth cell is electrically connected to the seventh wiring, the first terminal of the second transistor of the fourth cell is electrically connected to the fifth wiring, and the gate of the first transistor of the fourth cell is electrically connected to the first wiring.

[0038] (twenty two) Alternatively, in one aspect of the present invention, in the above (21), the material that can have ferroelectricity is hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0), yttria-stabilized zirconia, barium titanate, PbTiO XIt is preferable that the electrode layer 100 has one or more materials selected from the group consisting of lead zirconate titanate, barium strontium titanate, strontium titanate, and strontium bismuthate tantalate.

[0039] (twenty three) Alternatively, in one aspect of the present invention, in the above (21) or (22), it is preferable to have a configuration including a first circuit and a second circuit. In particular, it is preferable that the second wiring is electrically connected to the first circuit, the third wiring is electrically connected to the second circuit, the first circuit has an analog-to-digital conversion circuit, and the second circuit has a voltage source.

[0040] (twenty four) Alternatively, according to one embodiment of the present invention, in any one of the above (21) to (23), a current mirror circuit is preferably included. In particular, the current mirror circuit is preferably electrically connected to the fourth wiring and the fifth wiring, and has a function of causing a current corresponding to the potential of the fourth wiring to flow to the fifth wiring.

[0041] (twenty five) Alternatively, according to one aspect of the present invention, in the above (24), it is preferable that the first data and the second data are multiplied. Note that the first data is determined according to a difference between the first potential and the second potential, and the second data is determined according to a difference between the third potential and the fourth potential. Furthermore, the first cell has a function of holding the first potential at a first terminal of the capacitance of the first cell, the second cell has a function of holding the second potential at a first terminal of the capacitance of the second cell, the third cell has a function of holding the second potential at a first terminal of the capacitance of the third cell, and the fourth cell has a function of holding the first potential at a first terminal of the capacitance of the fourth cell. When the third potential is input to the sixth wiring and the fourth potential is input to the seventh wiring, the amount of current obtained by subtracting the amount of current flowing from the fifth wiring to the first terminal of the second transistor of the third cell and the amount of current flowing from the fifth wiring to the first terminal of the second transistor of the fourth cell from the amount of current flowing from the current mirror circuit to the fifth wiring is an amount corresponding to the product of the first data and the second data.

[0042] (26) Alternatively, in one aspect of the present invention, in the above (21) or (22), the circuit preferably includes a first current source, a second current source, and a subtraction circuit. The first current source is preferably electrically connected to the fourth wiring, and the second current source is preferably electrically connected to the fifth wiring. The first input terminal of the subtraction circuit is preferably electrically connected to the fourth wiring, and the second input terminal of the subtraction circuit is preferably electrically connected to the fifth wiring. The amount of current flowing from the first current source to the fourth wiring is preferably 0.9 to 1.1 times the amount of current flowing from the second current source to the fifth wiring.

[0043] (27) Alternatively, according to one aspect of the present invention, in the above (26), it is preferable to configure the multiplication of the first data and the second data. Note that the first data is determined according to a difference between the first potential and the second potential, and the second data is determined according to a difference between the third potential and the fourth potential. Furthermore, the first cell has a function of holding the first potential at a first terminal of a capacitance of the first cell, the second cell has a function of holding the second potential at a first terminal of a capacitance of the second cell, the third cell has a function of holding the second potential at a first terminal of a capacitance of the third cell, and the fourth cell has a function of holding the first potential at a first terminal of a capacitance of the fourth cell. By inputting the third potential to the sixth wire and the fourth potential to the seventh wire, the amount of current obtained by subtracting the sum of the amounts of current flowing from the fourth wire to the first terminals of the second transistors of the first cell and the second cell from the amount of current flowing from the first current source to the fourth wire is input to the first input terminal of the subtraction circuit, and the amount of current obtained by subtracting the sum of the amounts of current flowing from the fifth wire to the first terminals of the second transistors of the third cell and the fourth cell from the amount of current flowing from the second current source to the fifth wire is input to the second input terminal of the subtraction circuit. As a result, a voltage corresponding to the product of the first data and the second data is output from the output terminal of the subtraction circuit.

[0044] (28) Alternatively, in one embodiment of the present invention, in any one of the above (1) to (27), it is preferable that in the first cell, the second cell, the third cell, and the fourth cell, the first transistor and the second transistor each have a metal oxide in a channel formation region.

[0045] (29) Another embodiment of the present invention is an electronic device including the semiconductor device described in any one of (1) to (28) above and a housing.

[0046] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, an electronic component in which a chip is housed in a package, etc. are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0047] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0048] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0049] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0050] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0051] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0052] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0053] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element, wiring, or the like having a resistance value higher than 0 Ω. Therefore, in this specification and the like, a "resistance element" is intended to include wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value of 1 Ω or more and 1×10 9 It can be made smaller than Ω.

[0054] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, a transistor gate capacitance, etc. Therefore, in this specification, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with terms such as "capacitance." Conversely, the term "capacitance" can sometimes be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," etc. The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. Furthermore, it can be, for example, 1 pF or more and 10 μF or less.

[0055] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0056] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Furthermore, when operating in the saturation region, the multi-gate structure can provide a voltage-current characteristic with a flat slope, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing a voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0057] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series or parallel, with the gates of the transistors electrically connected to each other.

[0058] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0059] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0060] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0061] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current flow and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive or negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0062] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0063] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0064] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0065] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0066] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes," "wirings," and the like are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring," "electrode," and the like, and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," and the like are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0067] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0068] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0069] In this specification and the like, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0070] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0071] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0072] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0073] According to one embodiment of the present invention, a semiconductor device capable of performing a product-sum operation and / or an activation function operation can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0074] According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the semiconductor device can be provided.

[0075] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Note that the other effects are effects not mentioned in this section, which will be described below. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0076] [Figure 1] FIG. 1 is a block diagram showing an example of a semiconductor device. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 3] 3A and 3B are circuit diagrams showing examples of the configuration of circuits included in the semiconductor device. [Figure 4] 4A to 4C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 5] 5A to 5C are circuit diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 6] FIG. 6 is a circuit diagram illustrating an example of a semiconductor device. [Figure 7] FIG. 7 is a timing chart showing an example of the operation of the semiconductor device. [Figure 8]FIG. 8 is a block diagram showing an example of a semiconductor device. [Figure 9] FIG. 9 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 10] FIG. 10 is a block diagram showing an example of a semiconductor device. [Figure 11] FIG. 11 is a block diagram showing an example of a semiconductor device. [Figure 12] FIG. 12 is a block diagram showing an example of a semiconductor device. [Figure 13] FIG. 13 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 14] FIG. 14 is a circuit diagram showing an example of a semiconductor device. [Figure 15] FIG. 15 is a timing chart showing an example of the operation of the semiconductor device. [Figure 16] FIG. 16 is a block diagram showing an example of a semiconductor device. [Figure 17] FIG. 17 is a block diagram showing an example of a semiconductor device. [Figure 18] FIG. 18 is a block diagram showing an example of a semiconductor device. [Figure 19] FIG. 19 is a block diagram showing an example of a semiconductor device. [Figure 20] FIG. 20 is a block diagram showing an example of a semiconductor device. [Figure 21] FIG. 21 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 22] FIG. 22 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 23] FIG. 23 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 24] FIG. 24 is a timing chart showing an example of the operation of the semiconductor device. [Figure 25] FIG. 25 is a timing chart showing an example of the operation of the semiconductor device. [Figure 26]FIG. 26 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 27] FIG. 27 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 28] FIG. 28 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 29] FIG. 29 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 30] FIG. 30 is a circuit diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 31] 31A and 31B are diagrams illustrating a hierarchical neural network. [Figure 32] FIG. 32 is a block diagram showing a configuration example of a semiconductor device. [Figure 33] FIG. 33 is a block diagram showing a configuration example of a semiconductor device. [Figure 34] FIG. 34 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 35] 35A to 35C are cross-sectional views showing examples of the structure of a transistor. [Figure 36] FIG. 36 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 37] 37A and 37B are cross-sectional views showing examples of the structure of a transistor. [Figure 38] FIG. 38 is a schematic cross-sectional view showing a configuration example of a transistor. [Figure 39] FIG. 39A is a diagram illustrating the classification of IGZO crystal structures, FIG. 39B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 39C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 40] FIG. 40A is a perspective view showing an example of a semiconductor wafer, FIG. 40B is a perspective view showing an example of a chip, and FIGS. 40C and 40D are perspective views showing an example of an electronic component. [Figure 41] FIG. 41 is a schematic diagram illustrating an example of an electronic device. [Figure 42] 42A to 42C are schematic diagrams showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0077] In an artificial neural network (hereafter referred to as a neural network), the strength of synaptic connections can be changed by providing existing information to the neural network. This process of providing existing information to a neural network and determining connection strengths is sometimes called "learning."

[0078] Furthermore, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), new information can be output based on the connection strengths. In this way, the process of outputting new information based on the provided information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0079] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are sometimes called "deep neural networks" (DNNs), and machine learning using deep neural networks is sometimes called "deep learning."

[0080] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0081] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0082] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0083] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0084] Note that the content described in the embodiments refers to the content described in each embodiment (or example) using various figures, or the content described using text in the specification.

[0085] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0086] The embodiments described in this specification will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0087] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m,n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0088] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0089] (Embodiment 1) In this embodiment, an example of an arithmetic circuit capable of multiply-and-accumulate and function calculations, which is a semiconductor device of one embodiment of the present invention, will be described.

[0090] <Configuration Example 1 of Semiconductor Device> FIG. 1 shows an example of the configuration of a semiconductor device capable of performing a product-sum operation between a plurality of first data and a plurality of second data.

[0091] The arithmetic circuit MAC1 shown in FIG. 1 illustrates an example of the configuration of an arithmetic circuit capable of performing a product-sum operation and a function operation. The arithmetic circuit MAC1 is a circuit that performs a product-sum operation on a plurality of first data stored in a plurality of memory cells (described later) and a plurality of input second data, and performs an activation function operation using the result of the product-sum operation. The plurality of first data and the plurality of second data may be, for example, analog data or multi-valued data (discrete data). Furthermore, a plurality of first data may be collectively referred to as a first group of first data, etc. Similarly, a plurality of second data may be collectively referred to as a second group of second data, etc.

[0092] The arithmetic circuit MAC1 includes, for example, a memory cell array CA, a circuit CMS, a circuit WDD, a circuit XLD, a circuit WLD, a circuit INT, and a circuit ACTV.

[0093] The memory cell array CA includes memory cells AMx[1] to AMx[m] (m is an integer greater than or equal to 1), memory cells AMw[1] to AMw[m], memory cells AMu[1] to AMu[m], and memory cells AMr[1] to AMr[m].

[0094] In this specification, memory cells AMx[1] to AMx[m] may be described as being included in circuit CSX, memory cells AMu[1] to AMu[m] as being included in circuit CSU, memory cells AMw[1] to AMw[m] as being included in circuit CSW, and memory cells AMr[1] to AMr[m] as being included in circuit CSR.

[0095] In the memory cell array CA, the memory cells are arranged in a matrix of 2m rows and 2 columns. In particular, memory cells AMx[1] to AMx[m] are arranged at addresses from row 1, column 1 to row m, column 1 of the memory cell array CA, memory cells AMw[1] to AMw[m] are arranged at addresses from row m+1, column 1 to row 2m, column 1 of the memory cell array CA, memory cells AMu[1] to AMu[m] are arranged at addresses from row 1, column 2 to row m, column 2 of the memory cell array CA, and memory cells AMr[1] to AMr[m] are arranged at addresses from row m+1, column 2 to row 2m, column 2 of the memory cell array CA.

[0096] Each of the memory cells AMx, AMw, AMu, and AMr has a function of holding a voltage corresponding to first data. Note that the voltage corresponding to the first data can be, for example, the difference between the voltage held in the memory cells AMu[i] and AMw[i] and the voltage held in the memory cells AMx[i] and AMr[i].

[0097] The memory cell AMx[1] is electrically connected to the wiring WAD, the wiring BAL, the wiring WAL[1], and the wiring XAL[1]. The memory cell AMx[m] is electrically connected to the wiring WAD, the wiring BAL, the wiring WAL[m], and the wiring XAL[m]. The memory cell AMw[1] is electrically connected to the wiring WAD, the wiring BAL, the wiring WBL[1], and the wiring XBL[1]. The memory cell AMw[m] is electrically connected to the wiring WAD, the wiring BAL, the wiring WBL[m], and the wiring XBL[m]. The memory cell AMu[1] is electrically connected to the wiring WBD, the wiring BBL, the wiring WAL[1], and the wiring XAL[1]. The memory cell AMu[m] is electrically connected to the wiring WBD, the wiring BBL, the wiring WAL[m], and the wiring XAL[m]. The memory cell AMr[1] is electrically connected to the wiring WBD, the wiring BBL, the wiring WBL[1], and the wiring XBL[1]. The memory cell AMr[m] is electrically connected to the wiring WBD, the wiring BBL, the wiring WBL[m], and the wiring XBL[m].

[0098] Examples of detailed circuit configurations of memory cells AMx[1] to AMx[m], memory cells AMw[1] to AMw[m], memory cells AMu[1] to AMu[m], and memory cells AMr[1] to AMr[m] will be described later.

[0099] For example, the circuit CMS is electrically connected to a wiring BAL and a wiring BBL. The circuit CMS has a function of supplying current from the wiring BAL to each of the memory cells AMx[1] to AMx[m] and the memory cells AMw[1] to AMw[m], and a function of supplying current from the wiring BBL to each of the memory cells AMu[1] to AMu[m] and the memory cells AMr[1] to AMr[m]. Note that the amount of current flowing through the wiring BAL and the amount of current flowing through the wiring BBL by the circuit CMS are preferably equal. Specifically, the amount of current flowing through the wiring BAL is preferably 0.85 times or more, 0.9 times or more, or 0.95 times or more, and preferably 1.05 times or less, 1.1 times or less, or 1.15 times or less, of the amount of current flowing through the wiring BBL. Note that the above-described lower limit and upper limit values ​​can be combined with each other.

[0100] A specific example of the configuration of the circuit CMS will be described later.

[0101] For example, the circuit WDD is electrically connected to the wiring WAD and the wiring WBD. The circuit WDD has a function of transmitting data to be stored in each memory cell of the memory cell array CA. For example, the circuit WDD can transmit first data or reference data as the data to each of the wiring WAD and the wiring WBD.

[0102] For example, the circuit WLD is electrically connected to the wirings WAL[1] to WAL[m] and the wirings WBL[1] to WBL[m]. The circuit WLD has a function of selecting a memory cell to which data is to be written when writing data to a memory cell included in the memory cell array CA. Specifically, for example, when writing data to a memory cell AMx[i] (i is an integer greater than or equal to 1 and less than or equal to m) and a memory cell AMu[i] of the memory cell array CA, the circuit WLD applies a high-level potential to the wiring WAL[i] and a low-level potential to the wirings WAL[1] to WAL[m] and the wirings WBL[1] to WBL[m] other than the wiring WAL[i], thereby selecting the memory cell AMx[i] and the memory cell AMu[i] to which data is to be written. Furthermore, for example, when writing data to memory cells AMw[i] and AMr[i] of the memory cell array CA, the circuit WLD applies a high-level potential to the wiring WBL[i] and also applies a low-level potential to the wirings WAL[1] to WAL[m] and the wirings WBL[1] to WBL[m] other than the wiring WBL[i], thereby enabling the selection of the memory cells AMw[i] and AMr[i] to which data is to be written.

[0103] For example, the circuit XLD is electrically connected to the wirings XAL[1] to XAL[m] and the wirings XBL[1] to XBL[m]. The circuit XLD has a function of transmitting second data for multiplication with the first data to each memory cell in the memory cell array CA. Specifically, for example, the circuit XLD can apply a potential corresponding to the second data to the wirings XAL[1] to XAL[m] and the wirings XBL[1] to XBL[m].

[0104] For example, the circuit INT is electrically connected to the wirings BAL and BBL. The circuit INT has a function of inputting a predetermined voltage to the wirings BAL and BBL. Note that the voltage may be, for example, a low-level potential or a ground potential.

[0105] As a specific configuration example, the circuit INT includes a circuit SCI, and the circuit SCI includes a switch SW5A and a switch SW5B. A first terminal of the switch SW5A is electrically connected to a wiring BAL, and a second terminal of the switch SW5A is electrically connected to a wiring VSL. A first terminal of the switch SW5B is electrically connected to a wiring BBL, and a second terminal of the switch SW5B is electrically connected to a wiring VSL. Control terminals of the switches SW5A and SW5B are electrically connected to a wiring SL5.

[0106] The switches SW5A and SW5B may be, for example, electrical switches such as analog switches or transistors. Alternatively, the switches SW5A and SW5B may be, for example, mechanical switches. When transistors are used as the switches SW5A and SW5B, the transistors may be OS transistors or transistors including Si in a channel formation region (hereinafter referred to as Si transistors).

[0107] In this embodiment, each of the switches SW5A and SW5B is turned on when a high-level potential is input to the control terminal, and turned off when a low-level potential is input to the control terminal.

[0108] For example, the wiring SL5 functions as a wiring that supplies a voltage for switching the switches SW5A and SW5B between a conductive state and a non-conductive state. Therefore, the voltage can be, for example, a high-level potential or a low-level potential.

[0109] The wiring VSL functions as a wiring that applies a constant voltage, for example, a low-level potential, a ground potential, or the like.

[0110] The circuit ACTV is electrically connected to, for example, a wiring BAL and a wiring NIL, and has the functions of outputting a voltage corresponding to the amount of current flowing from the wiring BAL to the circuit ACTV, performing a calculation according to a predefined function system using the voltage, and outputting the result of the calculation of the function to the wiring NIL.

[0111] In particular, the function system in the circuit ACTV can be, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function (ramp function), a threshold function, etc. These functions can also be applied as activation functions in a neural network, for example.

[0112] <<Configuration example of memory cell array CA>> Next, a configuration example of memory cells AMx[1] to AMx[m], memory cells AMu[1] to AMu[m], memory cells AMw[1] to AMw[m], and memory cells AMr[1] to AMr[m] included in the memory cell array CA will be described.

[0113] 2 is a circuit diagram showing an example of the configuration of the memory cell array CA. The memory cell array CA has a function of calculating the sum of products of a plurality of first data and a plurality of second data.

[0114] In the memory cell array CA shown in FIG. 2, each of the memory cells AMx, AMu, AMw, and AMr has a transistor M1, a transistor M2, and a capacitor C1.

[0115] Furthermore, it is preferable that the size of the transistor M1 included in each of the memory cells AMx, AMu, AMw, and AMr is equal to each other.It is also preferable that the size of the transistor M2 included in each of the memory cells AMx, AMu, AMw, and AMr is equal to each other.

[0116] By making the transistors equal in size, the electrical characteristics of each transistor can be made approximately equal. Therefore, by making the size of the transistor M1 included in each of the memory cells AMx, AMu, AMw, and AMr equal, and by making the size of the transistor M2 included in each of the memory cells AMx, AMu, AMw, and AMr equal, each of the memory cells AMx, AMu, AMw, and AMr can perform approximately the same operation under the same conditions. Here, the same conditions refer to, for example, the potentials of the source, drain, gate, etc. of the transistor M1, the potentials of the source, drain, gate, etc. of the transistor M2, and the voltages input to each of the memory cells AMx, AMu, AMw, and AMr.

[0117] Note that unless otherwise specified, the transistor M1 may function as a switching element. That is, the transistor M1 may function as a switching element when a voltage is appropriately input to the gate, source, and drain of the transistor M1 within a range in which the transistor M1 operates as a switching element. However, one embodiment of the present invention is not limited thereto. For example, the transistor M1 may operate in a saturation region or a linear region when on. Alternatively, the transistor M1 may operate in a subthreshold region to reduce the amount of current flowing through the transistor M1. Alternatively, the transistor M1 may operate in a linear region, a saturation region, and a subthreshold region in a mixed manner. Alternatively, the transistor M1 may operate in a linear region and a saturation region in a mixed manner, or in a saturation region and a subthreshold region in a mixed manner, or in a linear region and a subthreshold region in a mixed manner.

[0118] In this specification and elsewhere, the subthreshold region refers to the region in a graph showing the gate voltage (Vg)-drain current (Id) characteristics of a transistor where the gate voltage is lower than the threshold voltage. Alternatively, the subthreshold region refers to the region where current flows due to carrier diffusion, which deviates from the gradual channel approximation (a model that only considers drift current). Alternatively, the subthreshold region refers to the region where the drain current increases exponentially with increasing gate voltage. Alternatively, the subthreshold region includes the regions that can be considered as the regions described above.

[0119] The drain current when a transistor operates in the subthreshold region is called the subthreshold current. The subthreshold current increases exponentially with gate voltage, regardless of drain voltage. Circuit operation using the subthreshold current can reduce the effect of drain voltage variations.

[0120] Furthermore, unless otherwise specified, the transistor M2 is assumed to operate in the saturation region when on. That is, the transistor M2 is assumed to operate in the saturation region when a voltage is appropriately input to the gate, source, and drain of each of the above-described transistors. However, one embodiment of the present invention is not limited thereto. The transistor M2 can operate in the linear region to reduce the amplitude of the supplied voltage. Alternatively, the transistor M2 can operate in the subthreshold region to reduce the amount of current flowing through the transistor M2. Alternatively, the transistor M2 can operate in a combination of the linear region, the saturation region, and the subthreshold region. Alternatively, the transistor M2 can operate in a combination of the linear region and the saturation region. Alternatively, the transistor M2 can operate in a combination of the saturation region and the subthreshold region.

[0121] Note that the transistor M1 is preferably an OS transistor. In addition, a channel formation region of the transistor M1 preferably contains an oxide containing at least one of indium, gallium, and zinc. Alternatively, the channel formation region of the transistor M1 may be an oxide containing at least one of indium, an element M (e.g., aluminum, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like), and zinc. Furthermore, the transistor M1 more preferably has the structure of the transistor described in Embodiment 5.

[0122] By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be suppressed, which may result in realizing a product-sum operation circuit with high calculation accuracy. Furthermore, by using an OS transistor as the transistor M1, the leakage current from the retention node (e.g., node Nx[1], node Nx[m], node Nu[1], node Nu[m], node Nw[1], node Nw[m], node Nr[1], node Nr[m], etc., which will be described later) to the write word line (e.g., wiring WAD, wiring WBD) when the transistor M1 is in a non-conductive state can be made very small. In other words, the number of refresh operations of the potentials of the retention nodes can be reduced, which reduces the power consumption of the product-sum operation circuit.

[0123] Furthermore, by using an OS transistor for the transistor M2, the transistor M2 can be manufactured simultaneously with the transistor M1, which may shorten the manufacturing process of the product-sum operation circuit. The transistor M2 may be a Si transistor instead of an OS transistor. Silicon may be, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like.

[0124] Note that the OS transistor has a gate voltage of 1×10 when the gate voltage is lower than the threshold voltage of the transistor. -20 Less than A, 1 x 10 -22 Less than A or 1 x 10 -24 The drain current per 1 μm of channel width is less than 1.0 × 10 A. When the gate voltage is equal to the threshold voltage of the transistor, the OS transistor has a drain current of 1.0 × 10 -8 A or less, 1.0×10 -12 A or less, or 1.0 x 10 -15 A or less per 1 μm of channel width flows. In other words, OS transistors can operate in the subthreshold region with a wide range of gate voltages. Specifically, the threshold voltage of an OS transistor can be set to V th In the subthreshold region, (V th -1.0V) or more V th Below, or (V th -0.5V) or more V th The circuit can operate using gate voltages in the following voltage ranges:

[0125] On the other hand, Si transistors have a large off-state current and a narrow range of gate voltages for operation in the subthreshold region.When utilizing subthreshold current, OS transistors can operate in circuits over a wider range of gate voltages than Si transistors.

[0126] 2, the back gates of the transistors M1 and M2 are illustrated, but the connection configuration of the back gates is not illustrated. However, the electrical connection destination of the back gates can be determined at the design stage. For example, in a transistor having a back gate, the gate and the back gate may be electrically connected to increase the on-state current of the transistor. That is, for example, the gate and the back gate of the transistor M1 may be electrically connected, or the gate and the back gate of the transistor M2 may be electrically connected. Furthermore, for example, in a transistor having a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring may be provided to electrically connect the back gate of the transistor to an external circuit or the like, and a potential may be applied to the back gate of the transistor from the external circuit or the like.

[0127] 2 includes a back gate, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the transistors M1 and M2 in FIG. 2 may have a structure without a back gate, that is, may have a single-gate structure. Some of the transistors may have a back gate, and other transistors may have a structure without a back gate.

[0128] 2, the transistors M1 and M2 are n-channel transistors, but the semiconductor device of one embodiment of the present invention is not limited to this. For example, some or all of the transistors M1 and M2 may be replaced with p-channel transistors.

[0129] The above-described modifications to the transistor structures and polarities are not limited to the transistors M1 and M2. For example, the same applies to the transistors M3A and M3B described later, as well as transistors included in transistors, switches, circuits, and the like described elsewhere in this specification, and transistors illustrated in other drawings.

[0130] In each of the memory cells AMx, AMu, AMw, and AMr, a first terminal of the transistor M1 is electrically connected to a gate of the transistor M2. A first terminal of the transistor M2 is electrically connected to a wiring VR. A first terminal of the capacitor C1 is electrically connected to the gate of the transistor M2.

[0131] In each of the memory cells AMx[1] to AMx[m], the second terminal of the transistor M1 is electrically connected to the wiring WAD, and the second terminal of the transistor M2 is electrically connected to the wiring BAL. In the memory cell AMx[i], the gate of the transistor M1 is electrically connected to the wiring WAL[i], and the second terminal of the capacitor C1 is electrically connected to the wiring XAL[i]. In the memory cell AMx[1], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nx[1]. In the memory cell AMx[m], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nx[m].

[0132] In each of the memory cells AMu[1] to AMu[m], the second terminal of the transistor M1 is electrically connected to the wiring WBD, and the second terminal of the transistor M2 is electrically connected to the wiring BBL. In the memory cell AMu[i], the gate of the transistor M1 is electrically connected to the wiring WAL[i], and the second terminal of the capacitor C1 is electrically connected to the wiring XAL[i]. In the memory cell AMu[1], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nu[1], and in the memory cell AMu[m], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nu[m].

[0133] In each of the memory cells AMw[1] to AMw[m], the second terminal of the transistor M1 is electrically connected to the wiring WAD, and the second terminal of the transistor M2 is electrically connected to the wiring BAL. In the memory cell AMw[i], the gate of the transistor M1 is electrically connected to the wiring WBL[i], and the second terminal of the capacitor C1 is electrically connected to the wiring XBL[i]. In the memory cell AMw[1], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nw[1]. In the memory cell AMw[m], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nw[m].

[0134] In each of the memory cells AMr[1] to AMr[m], the second terminal of the transistor M1 is electrically connected to the wiring WBD, and the second terminal of the transistor M2 is electrically connected to the wiring BBL. In the memory cell AMr[i], the gate of the transistor M1 is electrically connected to the wiring WBL[i], and the second terminal of the capacitor C1 is electrically connected to the wiring XBL[i]. In the memory cell AMr[1], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nr[1], and in the memory cell AMr[m], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nr[m].

[0135] The above-mentioned nodes Nx[1], Nx[m], Nu[1], Nu[m], Nw[1], Nw[m], Nr[1], and Nr[m] function as retention nodes for the respective memory cells.

[0136] The wiring VR is a wiring for passing current between the first terminal and the second terminal of the transistor M2 of each of the memory cells AMx, AMu, AMw, and AMr. Therefore, the wiring VR functions as a wiring for applying a predetermined potential. In this embodiment, the potential applied by the wiring VR can be, for example, a low-level potential, a ground potential, or a potential lower than the ground potential. The multiple wirings VR shown in FIG. 2 can be the same or different from each other. Alternatively, some of the multiple wirings VR shown in FIG. 2 can be the same, and the remaining wirings can be different. In particular, when all or some of the multiple wirings VR are different, different potentials can be applied to each different wiring. In other words, the same potential or different potentials can be applied to each of the multiple wirings VR shown in FIG. 13.

[0137] <<Circuit CMS configuration example>> Next, an example of the configuration of the circuit CMS will be described.

[0138] Fig. 3A shows an example of a circuit configuration applicable to the circuit CMS of Fig. 1. The circuit CMS of Fig. 3A includes a circuit CM. The circuit CM also includes p-channel transistors M3A and M3B, and switches SW7A and SW7B.

[0139] A first terminal of the transistor M3A is electrically connected to a first terminal of the switch SW7A, and a second terminal of the transistor M3A is electrically connected to the wiring VHE. A second terminal of the switch SW7A is electrically connected to the wiring BAL. A first terminal of the transistor M3B is electrically connected to a first terminal of the switch SW7B, a gate of the transistor M3A, and a gate of the transistor M3B, and a second terminal of the transistor M3B is electrically connected to the wiring VHE. A second terminal of the switch SW7B is electrically connected to the wiring BBL. Control terminals of the switches SW7A and SW7B are electrically connected to the wiring SL7.

[0140] Note that each of the transistors M3A and M3B is preferably a transistor containing silicon in its channel formation region (hereinafter referred to as a Si transistor). The silicon contained in the channel formation region can be, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or single-crystal silicon.

[0141] Furthermore, unless otherwise specified, the transistors M3A and M3B are considered to operate in the saturation region when on. That is, the transistors M3A and M3B are considered to operate in the saturation region when a voltage within the range for operation in the saturation region is appropriately input to the gate, source, and drain of each of the above-described transistors. However, one embodiment of the present invention is not limited to this. To reduce the amplitude of the supplied voltage, the transistors M3A and M3B can operate in the linear region. Alternatively, to reduce the amount of current flowing through the transistors M3A and M3B, the transistors M3A and M3B can operate in the subthreshold region. Alternatively, the transistors M3A and M3B may operate in a linear region, a saturation region, and a subthreshold region in a mixed manner, or may operate in a linear region and a saturation region in a mixed manner, or may operate in a saturation region and a subthreshold region in a mixed manner, or may operate in a linear region and a subthreshold region in a mixed manner.

[0142] Furthermore, switches applicable to the switches SW5A and SW5B can be used as the switches SW7A and SW7B, for example. In this embodiment, the switches SW7A and SW7B are each turned on when a high-level potential is input to a control terminal, and turned off when a low-level potential is input to the control terminal.

[0143] The wiring VHE functions as, for example, a wiring that applies a constant voltage, which is preferably, for example, a high-level potential.

[0144] For example, the wiring SL7 functions as a wiring that supplies a voltage for switching the switches SW7A and SW7B between a conductive state and a non-conductive state. Therefore, the voltage can be, for example, a high-level potential or a low-level potential.

[0145] The circuit CM shown in Fig. 3A functions as a current mirror circuit due to the above-described configuration. Specifically, the circuit CM in Fig. 3A has a function of referencing the potential of the first terminal (wire BBL) of the transistor M3B and causing a current corresponding to the potential to flow between the source and drain of each of the transistors M3A and M3B. In other words, the circuit CMS has a function of causing a current approximately equal in amount to flow between the source and drain of the transistor M3A as the current flowing between the source and drain of the transistor M3B.

[0146] The configuration of the circuit CMS is not limited to the configuration shown in FIG. 3A. The circuit CMS may be configured, for example, as shown in FIG. 3B, in which the transistors M3A and M4A are cascode-connected and the transistors M3B and M4B are cascode-connected. Specifically, the first terminal of the transistor M3A is electrically connected to the first terminal of the transistor M4A, and the second terminal of the transistor M3A is electrically connected to the wiring VHE. The first terminal of the transistor M3B is electrically connected to the first terminal of the transistor M4B, the gate of the transistor M3A, and the gate of the transistor M3B, and the second terminal of the transistor M3B is electrically connected to the wiring VHE. The second terminal of the transistor M4A is electrically connected to the wiring BAL. The second terminal of the transistor M4B is electrically connected to the wiring BBL, the gate of the transistor M4A, and the gate of the transistor M4B. As shown in the circuit CMS in FIG. 3B, by cascode-connecting the transistors included in the circuit CM, the operation of the current mirror circuit by the circuit CM can be made more stable.

[0147] 3A is configured such that the first terminal of the transistor M3A is electrically connected to the wiring BAL via the switch SW7A, and the first terminal of the transistor M3B is electrically connected to the wiring BBL via the switch SW7B. However, the electrical connection positions of the switches SW7A and SW7B are not limited thereto. For example, the circuit CMS of FIG. 3A may be configured such that the second terminal of the transistor M3A is electrically connected to the wiring VHE via the switch SW7A (not shown), and / or the second terminal of the transistor M3B is electrically connected to the wiring VHE via the switch SW7B (not shown). Furthermore, the circuit CMS of FIG. 3B is configured such that the second terminal of the transistor M4A is electrically connected to the wiring BAL via the switch SW7A, and the second terminal of the transistor M4B is electrically connected to the wiring BBL via the switch SW7B. However, the electrical connection positions of the switches SW7A and SW7B are not limited thereto. For example, the circuit CMS in FIG. 3B can be configured such that the second terminal of the transistor M3A is electrically connected to the wiring VHE through the switch SW7A, or the first terminal of the transistor M3A is electrically connected to the first terminal of the transistor M4A through the switch SW7A. Furthermore, for example, the circuit CMS in FIG. 3B can be configured such that the second terminal of the transistor M3B is electrically connected to the wiring VHE through the switch SW7B, or the first terminal of the transistor M3B is electrically connected to the first terminal of the transistor M4B through the switch SW7B. As described above, in FIGS. 3A and 3B, the electrical connection positions of the switches SW7A and SW7B can be freely determined during the design stage. Therefore, in one embodiment of the present invention, the electrical connection positions of the switches SW7A and SW7B are not particularly limited.

[0148] <<Example of ACTV circuit configuration>> Next, a configuration example of a circuit ACTV that can be applied to the arithmetic circuit MAC1 will be described.

[0149] 4A is a circuit diagram showing an example of the configuration of the circuit ACTV. As an example, the circuit ACTV includes a circuit ACP, which includes a circuit IVC, a circuit ACF, and a switch SW4A.

[0150] A first terminal of the switch SW4A is electrically connected to the line BAL, a second terminal of the switch SW4A is electrically connected to a first terminal of the circuit IVC, and a second terminal of the circuit IVC is electrically connected to a first terminal of the circuit ACF. The second terminal of the circuit ACF is electrically connected to the line NIL. Furthermore, a control terminal of the switch SW4A is electrically connected to the line SL4. In the second embodiment described below, the line BAL is replaced with the line BAN.

[0151] The circuit IVC has a function of outputting a voltage corresponding to the amount of current input to the first terminal to the second terminal, that is, the circuit IVC has a function as a current-voltage conversion circuit.

[0152] The circuit ACF has a function of performing a calculation according to a defined function system in response to a voltage input to a first terminal, and a function of outputting the result of the calculation of the function system to a second terminal (wire NIL) of the circuit ACF. Examples of the function system include a sigmoid function, a tanh function, a softmax function, a ReLU function (ramp function), and a threshold function.

[0153] As the switch SW4A, for example, a switch applicable to the switches SW5A and SW5B can be used.

[0154] For example, the wiring SL4 functions as a wiring that supplies a voltage for switching the switch SW4A between a conductive state and a non-conductive state. Therefore, the voltage can be, for example, a high-level potential or a low-level potential.

[0155] Next, a specific configuration example of the circuit IVC will be described. The circuit ACTV shown in FIG. 4B has a circuit configuration applicable to the circuit ACTV of FIG. 4A, and FIG. 4B shows a specific configuration example of the circuit IVC. In FIG. 4B, the circuit IVC has an operational amplifier OP and a load LEA. The inverting input terminal of the operational amplifier OP is electrically connected to a first terminal of the circuit IVC and a first terminal of the load LEA, and the output terminal of the operational amplifier OP is electrically connected to a second terminal of the load LEA and a second terminal of the circuit IVC. The non-inverting input terminal of the operational amplifier OP is electrically connected to a wiring VRPL. Note that the non-inverting input terminal of the operational amplifier OP and the wiring VRPL are connected via a third terminal of the circuit IVC.

[0156] The load LEA can be, for example, a resistor, a diode, a transistor, or the like.

[0157] The wiring VRPL functions as a wiring that applies a constant voltage, for example, which may be a ground potential or a low-level potential.

[0158] In particular, by setting the potential provided by the wiring VRPL to ground potential, the ground potential is input to the non-inverting input terminal of the operational amplifier OP. Also, since the inverting input terminal of the operational amplifier OP is electrically connected to the output terminal of the operational amplifier OP via the load LEA (a negative feedback connection configuration), the potential of the inverting input terminal of the operational amplifier OP can be considered to be virtual ground.

[0159] In addition to the circuit configuration of FIG. 4B, the circuit ACTV of FIG. 4C can also be used as a circuit configuration applicable to the circuit ACTV of FIG. 4A. The circuit ACP shown in FIG. 4C includes a current source CCS in addition to the circuit IVC and the circuit ACF. In FIG. 4C, the circuit IVC includes an operational amplifier OP, a load LEA, and a load LEB. The inverting input terminal of the operational amplifier OP is electrically connected to a first terminal of the circuit IVC and a first terminal of the load LEA, and the output terminal of the operational amplifier OP is electrically connected to a second terminal of the load LEA and a second terminal of the circuit IVC. The non-inverting input terminal of the operational amplifier OP is electrically connected to an output terminal of the current source CCS and a first terminal of the load LEB, the input terminal of the current source CCS is electrically connected to the wiring VDL, and the second terminal of the load LEB is electrically connected to the wiring VSSL. It is assumed that the non-inverting input terminal of the operational amplifier OP and the output terminal of the current source CCS are connected via the third terminal of the circuit IVC.

[0160] The load LEB preferably uses, for example, the same circuit elements as the load LEA.

[0161] The line VDL functions as a line that applies a constant voltage, for example, a high-level potential.

[0162] The wiring VSSL functions as a wiring that applies a constant voltage, for example, which may be a ground potential or a low-level potential.

[0163] 4C functions as a subtraction circuit. Specifically, a voltage corresponding to the difference between the amount of current flowing from the wiring BAL to the first terminal of the circuit IVC and the amount of current flowing from the output terminal of the current source CCS to the third terminal of the circuit IVC can be output to the second terminal of the circuit IVC. Furthermore, when the circuit IVC functions as a subtraction circuit, it is preferable that the loads LEA and LEB included in the circuit IVC have equal resistance values.

[0164] Furthermore, when the current flowing from the output terminal of the current source CCS to the third terminal of the circuit IVC is set to 0 A (it can be said that no current flows) and the potential of the third terminal of the circuit IVC is set to the same potential as that provided by the wiring VRPL in Figure 4B, the circuit ACTV in Figure 4C becomes equivalent to the circuit ACTV in Figure 4B.

[0165] Next, a specific configuration example of the circuit ACF will be described. FIG. 5A shows a circuit configuration applicable to the circuit ACTV of FIG. 4A, and shows a specific configuration example of the circuit ACF. In FIG. 5A, the circuit ACF includes a p-channel transistor M5 and a switch SW4F. A first terminal of the transistor M5 is electrically connected to a first terminal of the circuit ACF, a second terminal of the transistor M5 is electrically connected to a first terminal of the switch SW4F, and a second terminal of the switch SW4F is electrically connected to a second terminal of the circuit ACF. In addition, a gate of the transistor M5 is electrically connected to a wiring VBA, and a control terminal of the switch SW4F is electrically connected to a wiring SL4.

[0166] The wiring VBA functions as, for example, a wiring that applies an arbitrary constant voltage.

[0167] The switch SW4F may be, for example, a switch that can be used for the switches SW5A and SW5B. In addition, since the control terminal of the switch SW4F is electrically connected to the line SL4, the switch SW4F can be switched between an on state and an off state in synchronization with the switch SW4A.

[0168] The transistor M5 functions as a pass transistor between the wiring BAL and the wiring NIL. The voltage output from the second terminal of the transistor M5 is determined by the voltage input to the first terminal of the transistor M5 and the voltage applied to the gate of the transistor M5. Here, the voltage at the first terminal of the transistor M5 is V A The voltage applied to the gate of transistor M5 (the voltage applied by wiring VBA) is V BIAS The threshold voltage of the transistor M5 is Vth Here, V A V BIAS +V th In this case, the second terminal of the transistor M5 is approximately V A Also, V A V BIAS +V th When the voltage is less than V, transistor M5 applies a voltage to the second terminal of the BIAS +V th That is, the voltage output to the second terminal of the transistor M5 can be regarded as the calculation result of the ReLU function (ramp function) with the voltage of the first terminal of the transistor M5 as the input value.

[0169] Another circuit configuration that can be applied to the circuit ACF of the circuit ACTV of Fig. 4A is, for example, the circuit ACF of the circuit ACTV shown in Fig. 5B. The circuit ACF shown in Fig. 5B includes a comparator CMP. Specifically, a first terminal of the comparator CMP is electrically connected to a first terminal of the circuit ACF, a second terminal of the comparator CMP is electrically connected to the wiring VBA, and an output terminal of the comparator CMP is electrically connected to a second terminal of the circuit ACF.

[0170] The line VBA here functions as a line that applies a voltage to be compared with the potential of the first terminal of the comparator CMP, and therefore, this voltage can be set to any constant voltage.

[0171] 5B to the circuit ACTV of the arithmetic circuit MAC1, the circuit ACF of FIG. 5B can output a low-level potential or a high-level potential (binary digital signal) to the line NIL depending on the magnitude of the voltage supplied from the circuit IVC and the voltage applied by the line VBA. In other words, in the circuit ACF of FIG. 5B, the voltage output to the second terminal of the circuit ACF can be regarded as the calculation result of a step function (ramp function) with the voltage of the first terminal of the circuit ACF as an input value.

[0172] Another circuit configuration that can be applied to the circuit ACF of the circuit ACTV of FIG. 4A is, for example, the circuit ACF of the circuit ACTV shown in FIG. 5C. The circuit ACF shown in FIG. 5C includes an analog-to-digital conversion circuit ADC. Specifically, the input terminal of the analog-to-digital conversion circuit ADC is electrically connected to a first terminal of the circuit ACF, and the output terminal of the analog-to-digital conversion circuit ADC is electrically connected to a second terminal of the circuit ACF. In other words, the circuit ACF of FIG. 5C is configured to convert the analog voltage at the first terminal of the circuit ACF into a digital value and output it to the second terminal of the circuit ACF. When the circuit ACTV of FIG. 5C is applied to the circuit ACTV of FIG. 4A, it is preferable that the number of wirings NIL electrically connected to the circuit ACTV corresponds to the number of bits.

[0173] <Example of operation of an arithmetic circuit> Next, an example of the operation of the arithmetic circuit MAC1 will be described.

[0174] As shown in Fig. 6, the arithmetic circuit MAC1 here is an arithmetic circuit MAC1A in which the memory cell array CA of Fig. 2 is used as the memory cell array CA and the circuit CMS of Fig. 3A is used as the circuit CMS. The arithmetic circuit MAC1A shown in Fig. 6 mainly shows the memory cell array CA, the circuit CMS, the circuit XLD, the circuit WLD, and the circuit INT. Although not shown, the circuit ACTV of the arithmetic circuit MAC1A in Fig. 6 is the circuit ACTV of Fig. 4A.

[0175] 7 shows a timing chart of an operation example of the arithmetic circuit MAC1A. The timing chart in FIG. 7 shows fluctuations in the potentials of the wiring WAL[1], wiring WAL[m], wiring WBL[1], wiring WBL[m], wiring SL4, wiring SL5, wiring SL7, wiring WAD, wiring WBD, wiring XAL[1], wiring XAL[m], wiring XBL[1], wiring XBL[m], node Nx[1], node Nx[m], node Nu[1], node Nu[m], node Nw[1], node Nw[m], node Nr[1], and node Nr[m] from time T01 to time T13 and around those times. In FIG. 7, high-level potential is represented as "High" and low-level potential is represented as "Low."

[0176] In this operation example, the voltage applied by the wiring VR is set to the ground potential.

[0177] <<Before time T01>> Before time T01, the potentials of the nodes Nx[1] to Nx[m], the nodes Nu[1] to Nu[m], the nodes Nw[1] to Nw[m], and the nodes Nr[1] to Nr[m] are set to the ground potential. Note that the ground potential is represented as GND in FIG. 15.

[0178] A low-level potential is input to each of the wirings WAD and WBD by a circuit WDD (not shown in FIG. 6).

[0179] Furthermore, the wirings XAL[1] to XAL[m] and the wirings XBL[1] to XBL[m] are connected to a reference potential V RFP is entered. RFP may be higher or lower than ground potential.

[0180] Furthermore, a low-level potential is input to each of the wirings WAL[1] to WAL[m] and the wirings WBL[1] to WBL[m] by the circuit WLD, so that the transistors M1 included in all the memory cells AMx, AMu, AMw, and AMr in the memory cell array CA are turned off.

[0181] A low-level potential is input to each of the wirings SL4, SL5, and SL7, so that each of the switches SW4A, SW5A, SW5B, SW7A, and SW7B is turned off.

[0182] <<From time T01 to time T02>> Between time T01 and time T02, a high-level potential is input to the wiring SL5, which turns on the switches SW5A and SW5B included in the circuit INT.

[0183] When the switches SW5A and SW5B are turned on, electrical continuity is established between the wiring BAL and the wiring BBL and the wiring VSL, and a potential is applied to the wiring BAL and the wiring BBL from the wiring VSL. Note that in this operation example, the wiring VSL is a wiring that applies an initialization potential to the wiring BAL and the wiring BBL, and the initialization potential is set to ground potential. Therefore, the potentials of the wiring BAL and the wiring BBL are set to ground potential between time T01 and time T02.

[0184] Furthermore, since the first terminal of each of the transistors M2 included in all of the memory cells AMx, AMu, AMw, and AMr in the memory cell array CA is supplied with a ground potential from the wiring VR, the voltage between the first terminal and the second terminal of each of the transistors M2 is 0 V. Furthermore, since the potentials of the nodes Nx[1] to Nx[m], the nodes Nu[1] to Nu[m], the nodes Nw[1] to Nw[m], and the nodes Nr[1] to Nr[m] are each set to the ground potential, each of the transistors M2 is turned off.

[0185] <<From time T02 to time T03>> Between time T02 and time T03, a high-level potential is input to the wiring WAL[1], so that in the memory cell array CA, a high-level potential is applied to the gates of the transistors M1 included in the memory cells AMx[1] and AMu[1], turning on the transistors M1.

[0186] In addition, between time T02 and time T03, the potential of the wiring WAD is V Wβ At this time, the transistor M1 of the memory cell AMx[1] is in an on state, so that the line WAD and the node Nx[1] are in a conductive state, and the first terminal (node ​​Nx[1]) of the capacitor C1 of the memory cell AMx[1] is supplied with a potential V higher than the ground potential. Wβ [1] A large voltage is input.

[0187] In addition, between time T02 and time T03, the wiring WBD is at a potential higher than the ground potential V Wα [1] A potential larger than the ground potential is input. At this time, the transistor M1 of the memory cell AMu[1] is in an on state, so that the line WBD and the node Nu[1] are in a conductive state, and the first terminal (node ​​Nu[1]) of the capacitor C1 of the memory cell AMu[1] is supplied with a potential V Wα [1] A large voltage is input.

[0188] Here, as shown in the formula below, V W Define [1].

[0189]

number

[0190] V W [1] is the voltage corresponding to the first of the m first data. Wα [1], and V Wβ Each of [1] can be said to be a voltage corresponding to the first of the m first data. If equation (1.1) is satisfied, V Wα [1], and V Wβ The voltage combinations in [1] can be determined arbitrarily. For example, V Wα [1] is V Wβ [1] may be higher than V Wβ [1] or V Wβ It may be the same voltage as [1]. That is, V W [1] may be a positive voltage, 0, or a negative voltage.

[0191] Since the switch SW5A is in the on state, the ground potential is input to the wiring BAL. Also, in the memory cell AMx[1], the ground potential from the wiring VR is input to the first terminal of the transistor M2, so the voltage between the first terminal and the second terminal of the transistor M2 is approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of the transistor M2 of the memory cell AMx[1].

[0192] Similarly, because switch SW5B is in the on state, the ground potential is input to line BBL. Furthermore, in memory cell AMu[1], the ground potential from line VR is input to the first terminal of transistor M2, so the voltage between the first terminal and the second terminal of transistor M2 is also approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of transistor M2 in memory cell AMu[1].

[0193] Between time T02 and time T03, the wirings WAL[2] to WAL[m] and the wirings WBL[1] to WBL[m] continue to receive a low-level potential from before time T02. Therefore, in the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in the memory cells AMx[2] to AMx[m] and AMu[2] to AMu[m] arranged in the second to mth rows and the memory cells AMw[1] to AMw[m] and AMr[1] to AMr[m] arranged in the m+1th to 2mth rows, and each transistor M1 is turned off. This prevents data input to the wirings WAD and WBD from being written to the nodes Nx[2] to Nx[m], the nodes Nu[2] to Nu[m], the nodes Nw[1] to Nw[m], and the nodes Nr[1] to Nr[m].

[0194] <<From time T03 to time T04>> Between time T03 and time T04, a low-level potential is input to the wiring WAL[1], so that in the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in the memory cells AMx[1] and AMu[1], turning off the transistors M1.

[0195] In the memory cell AMx[1], the transistor M1 is turned off, and thus the first terminal (node ​​Nx[1]) of the capacitor C1 of the memory cell AMx[1] is set to V Wβ [1] A potential higher than the ground potential is maintained. In addition, in the memory cell AMu[1], the transistor M1 is turned off, and therefore a potential higher than the ground potential is maintained at the first terminal (node ​​Nu[1]) of the capacitor C1 of the memory cell AMu[1]. Wα [1] A large potential is maintained.

[0196] Also, between time T03 and time T04, the voltage V Wβ Similar to the write operation of [1], the voltage V is applied to each of the memory cells AMx[2] to AMx[m-1] arranged in the second row to the (m-1)th row of the memory cell array CA. Wβ [2]~V Wβ At the same time as the voltage write operation to each of the memory cells AMx[2] to AMx[m-1], a voltage V is sequentially written to each of the memory cells AMu[2] to AMu[m-1] arranged in the second row to the m-1th row of the memory cell array CA. Wα [2]~V Wα [m-1] is assumed to be written.

[0197] At this time, the memory cell AMx[p] located in the pth row (p is an integer of 2 or more and m-1 or less) is supplied with a voltage V Wβ [p] is held, and the memory cell AMu[p] is held at the voltage V Wα Here, similarly to equation (1.1), the voltage V corresponding to the pth one of the m first data is held. W [p] is defined as follows:

[0198]

number

[0199] V W [p] is the voltage corresponding to the pth one of the m first data. Wα [p] and V Wβ Each of [p] can be said to be a voltage corresponding to the pth one of the m first data. If equation (1.2) is satisfied, V Wα [p] and V Wβ The combination of voltages [p] can be determined arbitrarily. For example, V Wα [p] is V Wβ [p] may be higher than V Wβ[p] or V Wβ It may be the same voltage as [p]. In other words, V W [p] may be a positive voltage, 0, or a negative voltage.

[0200] <<From time T04 to time T05>> Between time T04 and time T05, a high-level potential is input to the wiring WAL[m], so that in the memory cell array CA, a high-level potential is applied to the gates of the transistors M1 included in the memory cells AMx[m] and AMu[m], turning on the transistors M1.

[0201] In addition, between time T04 and time T05, the potential of the wiring WAD is V Wβ At this time, since the transistor M1 of the memory cell AMx[m] is in an on state, the line WAD and the node Nx[m] are in a conductive state, and the first terminal (node ​​Nx[m]) of the capacitor C1 of the memory cell AMx[m] is supplied with a potential V higher than the ground potential. Wβ [m] A large potential is input.

[0202] In addition, between time T04 and time T05, the wiring WBD is at a potential higher than the ground potential V Wα At this time, since the transistor M1 of the memory cell AMu[m] is in an on state, the line WBD and the node Nu[m] are in a conductive state, and a potential V higher than the ground potential is applied to the first terminal (node ​​Nu[m]) of the capacitor C1 of the memory cell AMu[m]. Wα [m] A large potential is input.

[0203] Here, as shown in the formula below, V W Define [m].

[0204]

number

[0205] VW [m] is the voltage corresponding to the mth of the m first data. Wα [m], and V Wβ Each of [m] can be said to be a voltage corresponding to the mth of the m first data. If equation (1.3) is satisfied, V Wα [m], and V Wβ The voltage combinations for [m] can be determined arbitrarily. For example, V Wα [m] is V Wβ [m], V Wβ [m] or V Wβ It may be the same voltage as [m]. In other words, V W [m] may be a positive voltage, 0, or a negative voltage.

[0206] Since the switch SW5A is in the on state, the ground potential is input to the wiring BAL. Also, since the ground potential from the wiring VR is input to the first terminal of the transistor M2 in the memory cell AMx[m], the voltage between the first terminal and the second terminal of the transistor M2 is approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of the transistor M2 in the memory cell AMx[m].

[0207] Similarly, because switch SW5B is in the on state, the ground potential is input to line BBL. Furthermore, in memory cell AMu[m], the ground potential from line VR is input to the first terminal of transistor M2, so the voltage between the first terminal and the second terminal of transistor M2 is also approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of transistor M2 in memory cell AMu[m].

[0208] Between time T04 and time T05, a low-level potential is continuously input to the wirings WAL[1] to WAL[m-1] and the wirings WBL[1] to WBL[m] since before time T04. Therefore, in the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in the memory cells AMx[1] to AMx[m-1] and AMu[1] to AMu[m-1] arranged in the 1st to m-1th rows and the memory cells AMw[1] to AMw[m] and AMr[1] to AMr[m] arranged in the m+1th to 2mth rows, and each of the transistors M1 is in an off state. As a result, the data input to each of the wiring WAD and wiring WBD is not written to nodes Nx[1] to Nx[m-1], nodes Nu[1] to Nu[m-1], nodes Nw[1] to Nw[m], and nodes Nr[1] to Nr[m].

[0209] <<From time T05 to time T06>> Between time T05 and time T06, a low-level potential is input to the wiring WAL[m], so that in the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in the memory cells AMx[m] and AMu[m], turning off the transistors M1.

[0210] In the memory cell AMx[m], when the transistor M1 is turned off, a potential V higher than the ground potential is applied to the first terminal (node ​​Nx[m]) of the capacitor C1 of the memory cell AMx[m]. Wβ In addition, in the memory cell AMu[m], the transistor M1 is turned off, and a potential V Wα [m] A large potential is maintained.

[0211] <<From time T06 to time T07>> Between time T06 and time T07, a high-level potential is input to the wiring WBL[1], so that in the memory cell array CA, a high-level potential is applied to the gates of the transistors M1 included in the memory cells AMw[1] and AMr[1], turning on the transistors M1.

[0212] In addition, between time T06 and time T07, the potential of the wiring WAD is V Wα At this time, the transistor M1 of the memory cell AMw[1] is in the on state, so that the line WAD and the node Nw[1] are in a conductive state, and the first terminal (node ​​Nw[1]) of the capacitor C1 of the memory cell AMw[1] is supplied with a potential V higher than the ground potential. Wα [1] A large voltage is input.

[0213] In addition, between time T06 and time T07, the wiring WBD is charged to a potential V Wβ At this time, the transistor M1 of the memory cell AMr[1] is in the on state, so that the line WBD and the node Nr[1] are in a conductive state, and the first terminal (node ​​Nr[1]) of the capacitor C1 of the memory cell AMr[1] is supplied with a potential V higher than the ground potential. Wβ [1] A large voltage is input.

[0214] Since the switch SW5A is on, the ground potential is input to the line BAL. Also, in the memory cell AMw[1], the ground potential from the line VR is input to the first terminal of the transistor M2, so the voltage between the first terminal and the second terminal of the transistor M2 is approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of the transistor M2 of the memory cell AMw[1].

[0215] Similarly, because switch SW5B is in the on state, the ground potential is input to line BBL. Also, in memory cell AMr[1], the ground potential from line VR is input to the first terminal of transistor M2, so the voltage between the first terminal and the second terminal of transistor M2 is also approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of transistor M2 in memory cell AMr[1].

[0216] Between time T06 and time T07, the wirings WAL[1] to WAL[m] and the wirings WBL[2] to WBL[m] continue to receive a low-level potential since before time T06. Therefore, in the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in the memory cells AMx[1] to AMx[m] and AMu[1] to AMu[m] arranged in the first to mth rows and the memory cells AMw[2] to AMw[m] and AMr[2] to AMr[m] arranged in the m+2th to 2mth rows, and the transistors M1 are turned off. This prevents data input to the wirings WAD and WBD from being written to the nodes Nx[1] to Nx[m], the nodes Nu[1] to Nu[m], the nodes Nw[2] to Nw[m], and the nodes Nr[2] to Nr[m].

[0217] <<From time T07 to time T08>> Between time T07 and time T08, a low-level potential is input to the wiring WBL[1], so that in the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in the memory cells AMw[1] and AMr[1], turning off the transistors M1.

[0218] In the memory cell AMw[1], when the transistor M1 is turned off, a potential V higher than the ground potential is applied to the first terminal (node ​​Nw[1]) of the capacitor C1 of the memory cell AMw[1]. Wα [1] A potential higher than the ground potential is maintained. In addition, in the memory cell AMr[1], the transistor M1 is turned off, and therefore a potential higher than the ground potential is maintained at the first terminal (node ​​Nr[1]) of the capacitor C1 of the memory cell AMr[1]. Wβ [1] A large potential is maintained.

[0219] Furthermore, between time T07 and time T08, the voltage V Wα Similar to the write operation of [1], the voltage V is applied to each of the memory cells AMw[2] to AMw[m-1] arranged in the m+2th row to the 2m-1th row of the memory cell array CA. Wα [2]~V Wα At the same time as the voltage write operation to each of the memory cells AMw[2] to AMw[m-1], a voltage V is sequentially written to each of the memory cells AMr[2] to AMr[m-1] arranged between the 2m+2th row and the 2m-1th row of the memory cell array CA. Wβ [2]~V Wβ [m-1] is assumed to be written.

[0220] <<From time T08 to time T09>> Between time T08 and time T09, a high-level potential is input to the wiring WBL[m], so that in the memory cell array CA, a high-level potential is applied to the gates of the transistors M1 included in each of the memory cells AMw[m] and AMr[m], turning on the transistors M1.

[0221] In addition, between time T08 and time T09, the potential of the wiring WAD is V WαAt this time, since the transistor M1 of the memory cell AMw[m] is in an on state, the line WAD and the node Nw[m] are in a conductive state, and the first terminal (node ​​Nw[m]) of the capacitor C1 of the memory cell AMw[m] is supplied with a potential V higher than the ground potential. Wα [m] A large potential is input.

[0222] In addition, between time T08 and time T09, the wiring WBD is at a potential higher than the ground potential V Wβ At this time, since the transistor M1 of the memory cell AMr[m] is in an on state, the line WBD and the node Nr[m] are in a conductive state, and a potential V higher than the ground potential is applied to the first terminal (node ​​Nr[m]) of the capacitor C1 of the memory cell AMr[m]. Wβ [m] A large potential is input.

[0223] Since the switch SW5A is in the on state, the ground potential is input to the wiring BAL. Also, since the ground potential from the wiring VR is input to the first terminal of the transistor M2 in the memory cell AMw[m], the voltage between the first terminal and the second terminal of the transistor M2 is approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of the transistor M2 in the memory cell AMw[m].

[0224] Similarly, because the switch SW5B is in the on state, the ground potential is input to the wiring BBL. Also, in the memory cell AMr[m], the ground potential from the wiring VR is input to the first terminal of the transistor M2, so the voltage between the first terminal and the second terminal of the transistor M2 is also approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of the transistor M2 of the memory cell AMr[m].

[0225] Between time T08 and time T09, a low-level potential is continuously input to the wirings WAL[1] to WAL[m] and the wirings WBL[1] to WBL[m-1] since before time T08. Therefore, in the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in the memory cells AMx[1] to AMx[m] and AMu[1] to AMu[m] arranged in the 1st to mth rows and the memory cells AMw[1] to AMw[m-1] and AMr[1] to AMr[m-1] arranged in the m+1th to 2m-1th rows, and each of the transistors M1 is in an off state. As a result, the data input to each of the wiring WAD and wiring WBD is not written to nodes Nx[1] to Nx[m], nodes Nu[1] to Nu[m], nodes Nw[1] to Nw[m-1], and nodes Nr[1] to Nr[m-1].

[0226] <<From time T09 to time T10>> Between time T09 and time T10, a low-level potential is input to the wiring WBL[m], so that in the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in each of the memory cells AMw[m] and AMr[m], turning off the transistors M1.

[0227] In the memory cell AMw[m], when the transistor M1 is turned off, a potential V higher than the ground potential is applied to the first terminal (node ​​Nw[m]) of the capacitor C1 of the memory cell AMw[m]. Wα In addition, in the memory cell AMr[m], the transistor M1 is turned off, and thus a potential V higher than the ground potential is held at the first terminal (node ​​Nr[m]) of the capacitor C1 of the memory cell AMr[m]. Wβ [m] A large potential is maintained.

[0228] By the operation from time T01 to time T10, a voltage according to the first data can be written to each of the memory cells AMx, AMu, AMw, and AMr included in the memory cell array CA.

[0229] <<From time T10 to time T11>> Between time T10 and time T11, a low-level potential is input to the wiring SL5, which turns off the switches SW5A and SW5B in the circuit INT.

[0230] <<From time T11 to time T12>> Between time T11 and time T12, potentials corresponding to m pieces of second data are input to the wirings XAL[1] to XAL[m]. Here, for example, the potential input to the wiring XAL[1] from the circuit XLD is set to V Xα [1] The potential input from the circuit XLD to the wiring XAL[p] is V higher than the ground potential. Xα [p] higher potential, and the potential input from the circuit XLD to the wiring XAL[m] is V higher than the ground potential. Xα [m]High potential.

[0231] The potential of the wire XAL[1] is V Xα [1], the second terminal of the capacitor C1 of each memory cell AMx[1] and memory cell AMu[1] is V Xα At this time, since the nodes Nx[1] and Nu[1] are in an electrically floating state, the potentials of the nodes Nx[1] and Nu[1] change due to the capacitive coupling of the capacitor C1.

[0232] In each of memory cells AMx[1] and AMu[1], the increase in the potential of the gate of transistor M2 is the potential obtained by multiplying the change in the potential of wiring XAL[1] by a capacitance coupling coefficient determined by the configuration of the memory cell. The capacitance coupling coefficient is calculated based on the capacitance of capacitor C1, the gate capacitance of transistor M2, parasitic capacitance, etc. In this operation example, the capacitance coupling coefficient of each of memory cells AMx and AMu is set to h.

[0233] Therefore, the potential change of the wiring XAL[1] is V Xα When [1], the potential changes of the nodes Nx[1] and Nu[1] are hV Xα [1]. In other words, the potential of node Nx[1] is V Wβ [1]+hV Xα [1], and the potential of node Nu[1] becomes V Wα [1]+hV Xα [1]

[0234] In this operation example, the capacitive coupling coefficients of memory cells other than the memory cell AMx[1] and the memory cell AMu[1] included in the memory cell array CA will also be described as h.

[0235] Therefore, the potential of the wiring XAL[p] is V Xα [p], the second terminal of the capacitor C1 of each memory cell AMx[p] and memory cell AMu[p] is V Xα At this time, since the nodes Nx[p] and Nu[p] are electrically floating, the potentials of the nodes Nx[p] and Nu[p] change due to the capacitive coupling of the capacitor C1. Specifically, the potential of the node Nx[p] is V Wβ [p]+hV Xα [p], and the potential of node Nu[p] becomes V Wα [p]+hV Xα It becomes [p].

[0236] In addition, the potential of the wiring XAL[m] is VXα [m], the second terminal of the capacitor C1 of each memory cell AMx[m] and memory cell AMu[m] is V Xα At this time, since the nodes Nx[m] and Nu[m] are electrically floating, the potentials of the nodes Nx[m] and Nu[m] change due to the capacitive coupling of the capacitor C1. Specifically, the potential of the node Nx[m] is V Wβ [m]+hV Xα [m], and the potential of node Nu[m] becomes V Wα [m]+hV Xα It becomes [m].

[0237] In addition, between time T11 and time T12, potentials corresponding to m pieces of second data are input to each of the wirings XBL[1] to XBL[m]. Here, for example, the potential input to the wiring XBL[1] from the circuit XLD is set to V Xβ [1] The potential input from the circuit XLD to the wiring XBL[p] is V higher than the ground potential. Xβ [p] higher potential, and the potential input from the circuit XLD to the wiring XBL[m] is V Xβ [m]High potential.

[0238] The potential of the wire XBL[1] is V Xβ [1], the second terminal of the capacitor C1 of each memory cell AMw[1] and memory cell AMr[1] is V Xβ At this time, since the nodes Nw[1] and Nr[1] are in an electrically floating state, the potentials of the nodes Nw[1] and Nr[1] change due to the capacitive coupling of the capacitor C1.

[0239] In this operation example, the capacitive coupling coefficients of the memory cells AMw and AMr included in the memory cell array CA will be described as h, the same as those of the memory cells AMx and AMu.

[0240] Therefore, the potential change of the wiring XBL[1] is V Xβ When [1], the potential changes of the nodes Nw[1] and Nr[1] are hV Xβ [1]. In other words, the potential of node Nw[1] is V Wα [1]+hV Xβ [1], and the potential of node Nr[1] becomes V Wβ [1]+hV Xβ [1]

[0241] In addition, the potential of the wiring XBL[p] is V Xβ [p], the second terminal of the capacitor C1 of each memory cell AMw[p] and memory cell AMr[p] is V Xβ At this time, since the nodes Nw[p] and Nr[p] are electrically floating, the potentials of the nodes Nw[p] and Nr[p] change due to the capacitive coupling of the capacitor C1. Specifically, the potential of the node Nw[p] is V Wα [p]+hV Xβ [p], and the potential of node Nr[p] becomes V Wβ [p]+hV Xβ It becomes [p].

[0242] In addition, the potential of the wiring XBL[m] is V Xβ [m], the second terminal of the capacitor C1 of each memory cell AMw[m] and memory cell AMr[m] is V Xβ At this time, since the nodes Nw[m] and Nr[m] are electrically floating, the potentials of the nodes Nw[m] and Nr[m] change due to the capacitive coupling of the capacitor C1. Specifically, the potential of the node Nw[m] is V Wα [m]+hV Xβ [m], and the potential of node Nu[m] becomes V Wβ [m]+hV Xβ It becomes [m].

[0243] Here, as shown in the formula below, V X [1], VX [p] and V X Define [m].

[0244]

number

[0245] V X [1]~V X Each of [m] is a voltage according to the second data. Xα [1]~V Xα [m], and V Xβ [1]~V Xβ Each of [m] can be said to be a voltage according to the second data. Xα [i] and V Xβ The combination of voltages [i] can be determined arbitrarily. For example, V Xα [i] is V Xβ [i] may be higher than V Xβ [i] or V Xβ It may be the same voltage as [i]. In other words, V X [i] may be a positive voltage, 0, or a negative voltage.

[0246] <<From time T12 to time T13>> Between time T12 and time T13, a high-level potential is input to the wirings SL4 and SL7, which turns on the switches SW7A and SW7B in the circuit CMS and the switch SW4A in the circuit ACTV.

[0247] At this time, the second terminal of the transistor M2 included in each of the memory cells AMx[1] to AMx[m] and the memory cells AMw[1] to AMw[m] is electrically connected to the first terminal of the transistor M3A included in the circuit CM through the wiring BAL. Also, the second terminal of the transistor M2 included in each of the memory cells AMx[1] to AMx[m] and the memory cells AMw[1] to AMw[m] is electrically connected to the first terminal of the circuit IVC included in the circuit ACTV through the wiring BAL. Also, the second terminal of the transistor M2 included in each of the memory cells AMu[1] to AMu[m] and the memory cells AMr[1] to AMr[m] is electrically connected to the first terminal of the transistor M3B included in the circuit CM through the wiring BBL.

[0248] Here, consider the current flowing from the second terminal to the first terminal of the transistor M2 of each of the memory cells AMx, AMu, AMw, and AMr.

[0249] The current flowing from the wiring BAL to the first terminal via the second terminal of the transistor M2 of the memory cell AMx[1] is I AMx[1] When I AMx[1] can be expressed by the following formula:

[0250]

number

[0251] k is a constant determined by the channel length, channel width, mobility, and capacitance of the gate insulating film of the transistor M2. th is the threshold voltage of the transistor M2. Note that the constant k can be applied not only to the memory cell AMx but also to the memory cells AMu, AMw, and AMr. In addition to the memory cell AMx, the threshold voltage of the transistor M2 of the memory cells AMu, AMw, and AMr is also V th Let's say.

[0252] Also, the current flowing from the wiring BAL to the first terminal via the second terminal of the transistor M2 of the memory cell AMx[m] is I AMx[m] When I AMx[m] can be expressed by the following formula:

[0253]

number

[0254] That is, the sum of the amounts of currents flowing from the wiring BAL to the second terminals of the transistors M2 of the memory cells AMx[1] to AMx[m] is I x When I x can be expressed as follows from equations (1.7) and (1.8):

[0255]

number

[0256] Similarly, the current flowing from the wiring BAL to the first terminal via the second terminal of the transistor M2 of the memory cell AMw[1] is I AMw[1] The current flowing from the wiring BAL to the first terminal via the second terminal of the transistor M2 of the memory cell AMw[m] is I AMw[m] When I AMw[1] , and I AMw[m] can be expressed by the following formula:

[0257]

number

[0258] That is, the sum of the amounts of currents flowing from the wiring BAL to the second terminals of the transistors M2 of the memory cells AMw[1] to AMw[m] is I w When I w can be expressed as follows from equations (1.10) and (1.11):

[0259]

number

[0260] Similarly, the current flowing from the wiring BBL to the first terminal via the second terminal of the transistor M2 of the memory cell AMu[1] is I AMu[1] The current flowing from the wiring BBL to the first terminal of the transistor M2 of the memory cell AMu[m] via the second terminal is I AMu[m] When I AMu[1] , and I AMu[m] can be expressed by the following formula:

[0261]

number

[0262] That is, the sum of the amounts of currents flowing from the wiring BBL to the second terminals of the transistors M2 of the memory cells AMu[1] to AMu[m] is I u When I u can be expressed as follows from equations (1.13) and (1.14):

[0263]

number

[0264] Similarly, the current flowing from the wiring BBL to the first terminal via the second terminal of the transistor M2 of the memory cell AMr[1] is I AMr[1] The current flowing from the wiring BBL to the first terminal via the second terminal of the transistor M2 of the memory cell AMr[m] is I AMr[m] When I AMr[1] , and I AMr[m] can be expressed by the following formula:

[0265]

number

[0266] That is, the sum of the amounts of currents flowing from the wiring BBL to the second terminals of the transistors M2 of the memory cells AMr[1] to AMr[m] is I r When I r can be expressed as follows from equations (1.16) and (1.17):

[0267]

number

[0268] Between time T12 and time T13, the switch SW7B included in the circuit CMS is in an on state, and the switch SW5B included in the circuit INT is in an off state. Therefore, the total current I u +I r flows from the wiring VHE via the first terminal of the transistor M3B. At this time, the voltage of the first terminal (gate) of the transistor M3B is u +I r The voltage depends on the

[0269] Furthermore, since the circuit CM is a current mirror circuit, the amount of current flowing between the first and second terminals of the transistor M3B is approximately equal to the amount of current flowing between the first and second terminals of the transistor M3A. Between time T12 and time T13, the switch SW7A included in the circuit CMS is in the on state, so the amount of current flowing from the wiring VHE to the wiring BAL via the transistor M3B is I u +I r This becomes:

[0270] Since the switch SW5B included in the circuit INT is in the OFF state and the switch SW4A included in the circuit ACTV is in the ON state, a current flows from the wiring BAL through the switch SW4A to the first terminal of the circuit IVC included in the circuit ACTV. EV When IEV can be expressed by the following formula:

[0271]

number

[0272] Equation (1.19) can be written as follows by using equations (1.1) to (1.6), (1.9), (1.12), (1.15), and (1.18).

[0273]

number

[0274] From equation (1.20), the amount of current I input from wiring BAL to circuit ACTV EV is the potential V according to the first data W [1]~V W [m] and the potential V according to the second data X [1]~V X In other words, the sum of the products of the first and second data is proportional to the amount of current I EV It can be expressed as:

[0275] Connect I to the first terminal of the circuit IVC included in the circuit ACTV. EV As a result of the current flowing, the third terminal of the circuit IVC is EV Then, the voltage is input to the first terminal of the circuit ACF, and the circuit ACF uses the voltage to perform a calculation of a function system defined in advance, and the calculation result is output from the wiring NIL as a voltage (or a current, etc.).

[0276] By the way, each of the formulas (1.1) to (1.3) is V Wα [i]=V Wβ [i]+V W [i]. That is, the memory cell AMu[i] and the memory cell AMw[i] have V Wβ [i]+VW [i] is retained. V Wβ [i] can be any voltage, so V Wβ [1]~V Wβ [m] may all be set to the same voltage. For example, V Wβ [1]~V Wβ [m] to V PR Then, memory cell AMx[i] has V PR is stored in the memory cell AMu[i], and V PR +V W [i] is held, and memory cell AMw[i] holds V PR +V W [i] is held, and memory cell AMr[i] holds V PR Thus, V Wβ [1]~V Wβ [m] are all V PR By doing so, V PR The calculation of equation (1.20) can also be performed by using as a reference voltage, holding a voltage in memory cells AMu and AMw that is the reference voltage plus a voltage corresponding to the first data, and holding the reference voltage in memory cells AMx and AMr.

[0277] Furthermore, each of the formulas (1.4) to (1.6) is V Xα [i]=V Xβ [i]+V X [i]. That is, between time T11 and time T12, V Xβ [i]+V X [i] is entered. V Xβ [i] can be any voltage, so V Xβ [1]~V Xβ [m] may all be set to the same voltage. For example, V Xβ [1]~V Xβ [m] to V RFP When this is done, the wiring XAL[i] has V RFP +V X [i] is input, and V is input to the wiring XBL[i]. RFPIn this way, V Xβ [1]~V Xβ [m] are all V RFP By doing so, V RFP The calculation of equation (1.20) can also be performed by using as a reference voltage, inputting a voltage obtained by adding a voltage corresponding to the second data to the reference voltage to the wiring XAL, and inputting the reference voltage to the wiring XBL.

[0278] <Configuration Example 2 of Semiconductor Device> Here, a semiconductor device that is different from the arithmetic circuit MAC1 in FIG. 1 and is capable of performing a product-sum operation between a plurality of first data and a plurality of second data will be described.

[0279] The arithmetic circuit MAC2 in Fig. 8 is an example of a semiconductor device capable of performing a product-sum operation between a plurality of first data and a plurality of second data, similar to the arithmetic circuit MAC1 in Fig. 1. The arithmetic circuit MAC2 differs from the arithmetic circuit MAC1 in the circuit configuration of the circuit CMS and in that the wiring BBL is electrically connected to the circuit ACTV.

[0280] The circuit CMS included in the arithmetic circuit MAC2 has a current source CSA and a current source CSB. An input terminal of the current source CSA is electrically connected to the wiring VHE, and an output terminal of the current source CSA is electrically connected to the wiring BAL. An input terminal of the current source CSB is electrically connected to the wiring VHE, and an output terminal of the current source CSB is electrically connected to the wiring BBL.

[0281] It should be noted that the circuit CMS included in the arithmetic circuit MAC2 has the above-described circuit configuration and therefore does not have the function of the current mirror circuit shown in FIGS. 3A and 3B.

[0282] For example, the wiring VHE can be a wiring that applies a constant voltage, similar to the description of the circuit CMS in Figures 3A and 3B. The constant voltage is preferably, for example, a high-level potential.

[0283] Each of the current sources CSA and CSB has a function of outputting a constant current to an output terminal when a power supply potential is input to an input terminal. It is preferable that the amounts of current output from the current sources CSA and CSB to their output terminals are equal to each other. Specifically, the amount of current flowing from the output terminal of the current source CSA to the wiring BAL is preferably 0.85 times or more, 0.9 times or more, or 0.95 times or more, and preferably 1.05 times or less, 1.1 times or less, or 1.15 times or less, of the amount of current flowing from the output terminal of the current source CSB to the wiring BBL. It is also possible to combine the above-mentioned lower and upper limits.

[0284] 8, the circuit ACTV preferably has a function of outputting a voltage corresponding to the difference between the current flowing from the wiring BAL to the circuit ACTV and the current flowing from the wiring BBL to the circuit ACTV, a function of performing a calculation according to a predefined function system using the voltage, and a function of outputting the result of the calculation of the function to the wiring NIL.

[0285] Specifically, the circuit ACTV included in the arithmetic circuit MAC2 in Fig. 8 can be, for example, the circuit ACTV shown in Fig. 9. The circuit ACTV shown in Fig. 9 has a circuit ACP, which has a switch SW4A, a switch SW4B, a circuit IVC, and a circuit ACF.

[0286] The circuit IVC in Fig. 9 includes an operational amplifier OP, a load LEA, and a load LEB, and has the same circuit configuration as the circuit IVC included in the circuit ACTV in Fig. 4C. Therefore, the description of the circuit IVC in Fig. 4C should be referred to for an explanation of the circuit IVC in Fig. 9.

[0287] 9 may be the same as the circuit ACF included in the circuit ACTV described with reference to Fig. 4A to Fig. 4C. Therefore, like the circuit ACF of Fig. 4A to Fig. 4C, the circuit ACF of Fig. 9 may have a function of performing an operation according to a defined function system in response to a voltage input to a first terminal, and a function of outputting the result of the operation of the function system to a second terminal (wire NIL) of the circuit ACF.

[0288] A first terminal of the switch SW4A is electrically connected to the wiring BAL, and a second terminal of the switch SW4A is electrically connected to the inverting input terminal of the operational amplifier OP and the first terminal of the load LEA via a first terminal of the circuit IVC. A first terminal of the circuit ACF is electrically connected to the output terminal of the operational amplifier OP and the second terminal of the load LEA via a second terminal of the circuit IVC. A first terminal of the switch SW4B is electrically connected to the wiring BBL, and a second terminal of the switch SW4B is electrically connected to the non-inverting input terminal of the operational amplifier OP and the first terminal of the load LEB via a third terminal of the circuit IVC. In addition, the control terminals of the switches SW4A and SW4B are electrically connected to the wiring SL4.

[0289] As the switch SW4B, for example, a switch applicable to the switches SW4A, SW5A, and SW5B can be used.

[0290] In the circuit ACTV of Figure 9, for example, by inputting a high-level potential to the wiring SL4 and turning on each of the switches SW4A and SW4B, a current from the wiring BAL can flow to the first terminal of the circuit IVC, and a current from the wiring BBL can flow to the third terminal of the circuit IVC.

[0291] For example, in the arithmetic circuit MAC2 of FIG. 8, the current sources CSA and CSB respectively control the amounts of current flowing through the wiring BAL and wiring BBL. CS The total amount of current flowing from the wiring BAL to the memory cells AMx[1] to AMx[m] is Ix The sum of the currents flowing from the wiring BAL to the memory cells AMw[1] to AMw[m] is I w Then, the amount of current flowing from the wire BAL to the first terminal of the circuit IVC is I CS -I x -I w The sum of the currents flowing from the wiring BBL to the memory cells AMu[1] to AMu[m] is expressed as I u The total amount of current flowing from the wiring BBL to the memory cells AMr[1] to AMr[m] is I r Then, the amount of current flowing from the wire BBL to the third terminal of the circuit IVC is I CS -I u -I r This becomes:

[0292] When the circuit IVC in FIG. 9 is used as a subtraction circuit (for example, when the loads LEA and LEB are resistors), the second terminal of the circuit IVC outputs the difference (-I u -I r +I x +I w ) is output. This difference in current amount is determined by the sum of the products of the multiple first data and the multiple second data according to equations (1.19) and (1.20), so the voltage output from the second terminal of the circuit IVC can be said to be a voltage according to the result of the sum of the products of the multiple first data and the multiple second data.

[0293] The voltage is then input to the first terminal of the circuit ACF, and the circuit ACF uses the voltage to perform a calculation of a function system predefined by the circuit ACF, and the calculation result is output from the wiring NIL as a voltage (or current, etc.).

[0294] <Configuration Example 3 of Semiconductor Device> Next, a semiconductor device that is different from the arithmetic circuit MAC1 in FIG. 1 and the arithmetic circuit MAC2 in FIG. 8 and that is capable of performing a product-sum operation between a plurality of first data and a plurality of second data will be described.

[0295] 10 is an example of a semiconductor device capable of performing a multiply-and-accumulate operation between a plurality of first data and a plurality of second data, similar to the arithmetic circuits MAC1 and MAC2. The arithmetic circuit MAC3 is a modified example of the arithmetic circuit MAC1, and differs from the arithmetic circuit MAC1 in the number of memory cells AMw included in the circuit CSW and the number of memory cells AMr included in the circuit CSR.

[0296] For example, in the arithmetic circuit MAC3, the number of memory cells AMw included in the circuit CSW can be set to g (g is not m and is an integer equal to or greater than 1), and the number of memory cells AMr included in the circuit CSR can be set to g. Therefore, the number of wirings XBL and WBL is set to g.

[0297] First, the case where g is equal to or greater than 1 and less than m will be described.

[0298] The voltage corresponding to the first data is V W [1]~V W [m] and V is set to satisfy the formulas (1.1) to (1.3). Wα [1]~V Wα [m], and V Wβ [1]~V Wβ Also, a voltage V is applied to each of the memory cells AMw[1] to AMw[m] and the memory cells AMu[1] to AMu[m]. Wα [1]~V Wα [m] is held, and V is held in the memory cells AMx[1] to AMx[m] and the memory cells AMr[1] to AMr[m]. Wβ [1]~V Wβ [m] is assumed to be held.

[0299] At this time, when the amount of change in the potentials of the wirings XBL[1] to XBL[m] is small between time T11 and time T12 in the timing chart of FIG. 7, for example, V Xβ [1]~V XβLet us consider the case where each of the voltages at the wiring BAL and the memory cell AMw[i] is set to 0 V. Here, for example, the current I AMw [i] is calculated from equations (1.10) and (1.11) as follows: AMw [i]=k(V Wα [i]-V th ) 2 and the current I flows from the wiring BBL to the memory cell AMr[i]. AMr [i] is calculated from equations (1.16) and (1.17) as follows: AMr [i]=k(V Wβ [i]-V th ) 2 At this time, V W [i]=V Wα [i]-V Wβ If [i] is close to 0, I AMw [i] and I AMr [i] can be considered to be almost the same current amount. Therefore, I AMr [i] is also part of the current that the circuit CMS flows into the wiring BAL, so in the wiring BAL, I AMr [i] is the current flowing through memory cell AMw[i] AMw It is canceled with [i].

[0300] Conversely, the voltages V written to the memory cells AMw[i] and AMr[i] are Wα [i] and V Wβ If it is known in advance that the difference between the memory cells AMw[i] and AMr[i] is close to 0, V Wα [i] and V Wβ [i] does not need to be written. This makes it possible to reduce the number of memory cells AMw included in the circuit CSW and the number of memory cells AMr included in the circuit CSR, thereby reducing the power consumption required for the memory cells AMw included in the circuit CSW and the memory cells AMr included in the circuit CSR.

[0301] Note that, between time T11 and time T12 in the timing chart of FIG. 7, the amount of change in the potential of the wiring XAL[i] is V Xα [i](=V X [i]), the amount of current flowing from the wiring BAL to the memory cell AMx[i] is I AMx [i]=k(V Wβ [i]+hV Xα [i]-V th ) 2 The amount of current flowing from the wiring BBL to the memory cell AMu[i] is I AMu [i]=k(V Wα [i]+hV Xα [i]-V th ) 2 V Xα The larger [i], the greater the AMx [i] and I AMu Since the difference in the amount of current between memory cells AMx[i] and AMr[i] may be large, it is preferable to write a voltage corresponding to the first data to each of memory cells AMx[i] and AMu[i], unlike memory cells AMw[i] and AMr[i].

[0302] Next, the case where g exceeds m, for example, g=m+1, will be described.

[0303] The voltage corresponding to the first data is V W [1]~V W [m] and V is set to satisfy the formulas (1.1) to (1.3). Wα [1]~V Wα [m], and V Wβ [1]~V Wβ Also, a voltage V is applied to each of the memory cells AMw[1] to AMw[m] and the memory cells AMu[1] to AMu[m]. Wα [1]~V Wα [m] is held, and V is held in the memory cells AMx[1] to AMx[m] and the memory cells AMr[1] to AMr[m]. Wβ [1]~V Wβ [m] is assumed to be held.

[0304] Furthermore, the memory cell AMr[m+1] is supplied with an arbitrary voltage V b is written to the memory cell AMw[m+1], and the ground potential is written to the memory cell AMw[m+1]. Also, the voltage of the wiring XBL[m+1] is not changed between time T11 and time T12 in the timing chart of FIG. 7. In this case, the current flowing from the wiring BBL to the memory cell AMr[m+1] is I b When I b , and the current I flowing from the wiring BAL to the circuit ACTV EV Each of these is expressed as follows:

[0305]

number

[0306] Equation (1.22) corresponds to an equation that assigns an arbitrary value to the result of a sum of products. This can be used, for example, in calculations in a hierarchical neural network, to assign an arbitrary bias to the result of a sum of products between weight coefficients and neuron signals.

[0307] In the above example, an arbitrary voltage V b The case where a ground potential is written to the memory cell AMr[m+1] and an arbitrary voltage V b In this case, I can be written from the wiring BAL to the memory cell AMw[m+1]. b Since the current flowing from the wiring BAL to the circuit ACTV is I EV is I in equation (1.21). b Ga-I b In other words, any value given to the result of the sum of products can be negative.

[0308] Also, the voltage V Wα[i] and V Wβ The omission of writing [i] and the addition of an arbitrary value to the result of the sum-of-products operation can be performed simultaneously. In this case, the value of g, which is the number of rows in the memory cell array CA, may be equal to or greater than 1 and less than m, or may exceed m.

[0309] The value of g may be m. In this case, for example, in the arithmetic circuit MAC1 of FIG. 1, the voltages V written to the memory cells AMw[i] and AMr[i] are Wα [i] and V Wβ If it is known in advance that the difference between the memory cells AMw[i] and AMr[i] is close to 0, for example, V Wα [i] and V Wβ [i], and instead write an arbitrary voltage V to either the memory cell AMw[i] or the memory cell AMr[i]. b and writes a ground potential to the other of the memory cells AMw[i] and AMr[i], so that the difference is close to 0. Wα [i] and V Wβ It is possible to omit writing [i] and add any value to the result of the multiply-and-accumulate operation at the same time.

[0310] Note that the semiconductor device of one embodiment of the present invention is not limited to the arithmetic circuits MAC1 to MAC3 described in this embodiment. For example, when multiple multiply-and-accumulate operations are performed simultaneously using the same multiple second data, the arithmetic circuit MAC4 shown in FIG. 11 may be used. The arithmetic circuit MAC4 has a configuration in which n memory cell arrays CA (n is an integer of 1 or more) of the arithmetic circuit MAC1 in FIG. 1 are arranged for each column.

[0311] 11 illustrates memory cell arrays CA[1] to CA[n], and the memory cell arrays CA[1] to CA[n] are collectively referred to as memory cell arrays CAS. Also, since the arithmetic circuit MAC4 has n memory cell arrays CA, in FIG. 11, the circuit CMS has n circuits CM[1] to CM[n] as circuits CM, the circuit INT has n circuits SCI[1] to SCI[n] as circuits SCI, and the circuit ACTV has n circuits ACP[1] to ACP[n] as circuits ACP. In addition, the arithmetic circuit MAC4 has wiring BAL[1] to wiring BAL[n] corresponding to the wiring BAL of the arithmetic circuit MAC1, wiring BBL[1] to wiring BBL[n] corresponding to the wiring BBL of the arithmetic circuit MAC1, wiring WAD[1] to wiring WAD[n] corresponding to the wiring WAD of the arithmetic circuit MAC1, wiring WBD[1] to wiring WBD[n] corresponding to the wiring WBD of the arithmetic circuit MAC1, and wiring NIL[1] to wiring NIL[n] corresponding to the wiring NIL of the arithmetic circuit MAC1.

[0312] The memory cell array CA[1] is electrically connected to wiring BAL[1], wiring BBL[1], wiring WAD[1], wiring WBD[1], wiring XAL[1] to wiring XAL[m], wiring XBL[1] to wiring XBL[m], wiring WAL[1] to wiring WAL[m], and wiring WBL[1] to wiring WBL[m]. The circuit WDD is electrically connected to wiring WAD[1] and wiring WBD[1]. The circuit CM[1] of the circuit CMS is electrically connected to wiring BAL[1] and wiring BBL[1], and the circuit SCI[1] of the circuit INT is electrically connected to wiring BAL[1], wiring BBL[1], and circuit ACP[1] of the circuit ACTV. The circuit ACP[1] is electrically connected to wiring NIL[1].

[0313] Similarly, the memory cell array CA[n] is electrically connected to wirings BAL[n], BBL[n], WAD[n], WBD[n], XAL[1] to XAL[m], XBL[1] to XBL[m], WAL[1] to WAL[m], and WBL[1] to WBL[m]. The circuit WDD is electrically connected to wirings WAD[n] and WBD[n]. The circuit CM[n] of the circuit CMS is electrically connected to wirings BAL[n] and BBL[n], and the circuit SCI[n] of the circuit INT is electrically connected to wirings BAL[n], BBL[n], and ACP[n] of the circuit ACTV. The circuit ACP[n] is electrically connected to wiring NIL[n].

[0314] Similar to the operation of the timing chart of Figure 7, the arithmetic circuit MAC4 of Figure 11 writes voltages corresponding to the first data of the first group to the nth group to each of the memory cell arrays CA[1] to CA[n], and then inputs voltages corresponding to the second data to the wirings XAL[1] to XAL[m] and the wirings XBL[1] to XBL[m], thereby simultaneously outputting the product-sum operation of the first data and the second data of each of the first group to the nth group to the wirings NIL[1] to NIL[n].

[0315] <Configuration Example 4 of Semiconductor Device> Here, a semiconductor device that is different from the above-described arithmetic circuits MAC1, MAC1A, MAC2, and MAC3 and that is capable of performing product-sum operations between a plurality of first data and a plurality of second data will be described.

[0316] 12 shows an example of the configuration of an arithmetic circuit that can perform a product-sum operation and a function operation, similar to the above-mentioned arithmetic circuit MAC1, etc. The arithmetic circuit MAC5 is a circuit that performs a product-sum operation on a plurality of first data held in a plurality of memory cells (to be described later) and a plurality of input second data, and performs a function operation using the result of the product-sum operation.

[0317] The arithmetic circuit MAC5 includes, for example, a memory cell array CA, a circuit CMS, a circuit WDD, a circuit XLD, a circuit WLD, a circuit INT, and a circuit ACTV.

[0318] The memory cell array CA includes circuits CS[1] to CS[m] (where m is an integer equal to or greater than 1). Each of the circuits CS[1] to CS[m] includes a memory cell AMu, a memory cell AMx, a memory cell AMw, and a memory cell AMr. Although not shown in FIG. 12, in this specification and the like, the memory cells AMu, AMx, AMw, and AMr included in the circuit CS[i] (where i is an integer equal to or greater than 1 and equal to or less than m) may be referred to as memory cell AMu[i], memory cell AMx[i], memory cell AMw[i], and memory cell AMr[i], respectively.

[0319] In the memory cell array CA, the memory cells are arranged in a matrix of 2m rows and 2 columns. In Fig. 12, as an example, memory cell AMu[i] is arranged at an address of 2i-1 row and 1st column, memory cell AMw[i] is arranged at an address of 2i row and 1st column, memory cell AMx[i] is arranged at an address of 2i-1 row and 2nd column, and memory cell AMr[i] is arranged at an address of 2i row and 2nd column.

[0320] Each of the memory cells AMx, AMw, AMu, and AMr has a function of holding a voltage corresponding to first data. Note that the voltage corresponding to the first data can be, for example, the difference between the voltage held in the memory cells AMu[i] and AMw[i] and the voltage held in the memory cells AMx[i] and AMr[i].

[0321] The memory cell AMu[1] is electrically connected to the wiring WAD, the wiring BBL, the wiring WL[1], and the wiring XAL[1]. The memory cell AMw[1] is electrically connected to the wiring WAD, the wiring BAL, the wiring WL[1], and the wiring XBL[1]. The memory cell AMx[1] is electrically connected to the wiring WBD, the wiring BAL, the wiring WL[1], and the wiring XAL[1]. The memory cell AMr[1] is electrically connected to the wiring WBD, the wiring BBL, the wiring WL[1], and the wiring XBL[1]. The memory cell AMu[m] is electrically connected to the wiring WAD, the wiring BBL, the wiring WL[m], and the wiring XAL[m]. The memory cell AMw[m] is electrically connected to the wiring WAD, the wiring BAL, the wiring WL[m], and the wiring XBL[m]. The memory cell AMx[m] is electrically connected to the wiring WBD, the wiring BAL, the wiring WL[m], and the wiring XAL[m]. The memory cell AMr[m] is electrically connected to the wiring WBD, the wiring BBL, the wiring WL[m], and the wiring XBL[m].

[0322] An example of a detailed circuit configuration of each of the memory cells AMu, AMw, AMx, and AMr included in each of the circuits CS[1] to CS[m] will be described later.

[0323] For example, the circuit CMS is electrically connected to a wiring BAL and a wiring BBL. The circuit CMS has a function of supplying current to each of the memory cells AMx[1] to AMx[m] and the memory cells AMw[1] to AMw[m] via the wiring BAL, and a function of supplying current to each of the memory cells AMu[1] to AMu[m] and the memory cells AMr[1] to AMr[m] via the wiring BBL. Note that the amount of current flowing through the wiring BAL and the amount of current flowing through the wiring BBL by the circuit CMS are preferably equal.

[0324] For a specific configuration example of the circuit CMS, please refer to the description of the circuit CMS that can be applied to the above-mentioned arithmetic circuit MAC1.

[0325] As for the circuit WDD, the description of the circuit WDD applicable to the arithmetic circuit MAC1 described above will be taken into consideration as an example.

[0326] For example, the circuit WLD is electrically connected to wirings WL[1] to WL[m]. The circuit WLD has a function of selecting a memory cell to which data is to be written when writing data to a memory cell included in the memory cell array CA. Specifically, for example, the wiring WL[i] is electrically connected to the memory cell AMu[i], the memory cell AMw[i], the memory cell AMx[i], and the memory cell AMr[i] included in the circuit CS[i]. Therefore, when the circuit WLD selects one of the circuits CS[1] to CS[m] included in the memory cell array CA, the memory cell AMu, the memory cell AMw, the memory cell AMx, and the memory cell AMr included in the selected circuit CS become memory cells to which data is to be written.

[0327] For example, when writing data to each memory cell included in the circuit CS[i] of the memory cell array CA, the circuit WLD applies a high-level potential to the wiring WL[i] and also applies a low-level potential to the wirings WL[1] to WL[m] other than the wiring WL[i], thereby selecting the memory cells AMu[i], AMw[i], AMx[i], and AMr[i] included in the circuit CS[i] as the destinations for writing data.

[0328] As for the circuit XLD, the description of the circuit XLD applicable to the arithmetic circuit MAC1 described above will be taken into consideration as an example.

[0329] For the circuit INT, the description of the circuit INT applicable to the arithmetic circuit MAC1 described above will be taken into consideration as an example.

[0330] As for the circuit ACTV, the description of the circuit ACTV applicable to the arithmetic circuit MAC1 described above will be taken into consideration as an example.

[0331] <<Configuration example of memory cell array CA>> Next, a description will be given of an example of the configuration of the memory cells AMu, AMw, AMx, and AMr included in each of the circuits CS[1] to CS[m] of the memory cell array CA.

[0332] 13 is a circuit diagram showing an example of the configuration of a memory cell array CA. The memory cell array CA has a function of calculating the sum of products of a plurality of first data and a plurality of second data.

[0333] In the memory cell array CA shown in FIG. 13, each of the memory cells AMx, AMu, AMw, and AMr has a transistor M1, a transistor M2, and a capacitor C1.

[0334] Furthermore, for the transistors M1 and M2 included in the memory cells AMx, AMu, AMw, and AMr, respectively, please refer to the description of the transistors M1 and M2 included in the memory cells AMx, AMu, AMw, and AMr, respectively, of the arithmetic circuit MAC1 described above.

[0335] In each of the memory cells AMx, AMu, AMw, and AMr, a first terminal of the transistor M1 is electrically connected to a gate of the transistor M2. A first terminal of the transistor M2 is electrically connected to a wiring VR. A first terminal of the capacitor C1 is electrically connected to the gate of the transistor M2.

[0336] In each of the memory cells AMu[1] to AMu[m], the second terminal of the transistor M1 is electrically connected to the wiring WAD, and the second terminal of the transistor M2 is electrically connected to the wiring BBL. In the memory cell AMu[i], the gate of the transistor M1 is electrically connected to the wiring WL[i], and the second terminal of the capacitor C1 is electrically connected to the wiring XAL[i]. In the memory cell AMu[1], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nu[1], and in the memory cell AMu[m], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nu[m].

[0337] In each of the memory cells AMw[1] to AMw[m], the second terminal of the transistor M1 is electrically connected to the wiring WAD, and the second terminal of the transistor M2 is electrically connected to the wiring BAL. In the memory cell AMw[i], the gate of the transistor M1 is electrically connected to the wiring WL[i], and the second terminal of the capacitor C1 is electrically connected to the wiring XBL[i]. In the memory cell AMw[1], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nw[1]. In the memory cell AMw[m], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nw[m].

[0338] In each of the memory cells AMx[1] to AMx[m], the second terminal of the transistor M1 is electrically connected to the wiring WBD, and the second terminal of the transistor M2 is electrically connected to the wiring BAL. In the memory cell AMx[i], the gate of the transistor M1 is electrically connected to the wiring WL[i], and the second terminal of the capacitor C1 is electrically connected to the wiring XAL[i]. In the memory cell AMx[1], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nx[1]. In the memory cell AMx[m], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nx[m].

[0339] In each of the memory cells AMr[1] to AMr[m], the second terminal of the transistor M1 is electrically connected to the wiring WBD, and the second terminal of the transistor M2 is electrically connected to the wiring BBL. In the memory cell AMr[i], the gate of the transistor M1 is electrically connected to the wiring WL[i], and the second terminal of the capacitor C1 is electrically connected to the wiring XBL[i]. In the memory cell AMr[1], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nr[1], and in the memory cell AMr[m], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is referred to as a node Nr[m].

[0340] The above-mentioned nodes Nx[1], Nx[m], Nu[1], Nu[m], Nw[1], Nw[m], Nr[1], and Nr[m] function as retention nodes for the respective memory cells.

[0341] For the wiring VR, please refer to the description of the wiring VR included in the arithmetic circuit MAC1 described above.

[0342] <Example of operation of an arithmetic circuit> Next, an example of the operation of the arithmetic circuit MAC5 will be described.

[0343] As shown in Fig. 14, the arithmetic circuit MAC5 here is an arithmetic circuit MAC5A in which the memory cell array CA of Fig. 13 is used as the memory cell array CA and the circuit CMS of Fig. 3A is used as the circuit CMS. The arithmetic circuit MAC5A shown in Fig. 14 mainly shows the memory cell array CA, the circuit CMS, the circuit XLD, the circuit WLD, and the circuit INT. Although not shown, the circuit ACTV of the arithmetic circuit MAC5A in Fig. 14 is the circuit ACTV of Fig. 4A.

[0344] 15 shows a timing chart of an operation example of the arithmetic circuit MAC5A. The timing chart in FIG. 15 shows fluctuations in the potentials of wiring WL[1], wiring WL[m], wiring SL4, wiring SL5, wiring SL7, wiring WAD, wiring WBD, wiring XAL[1], wiring XAL[m], wiring XBL[1], wiring XBL[m], node Nx[1], node Nx[m], node Nu[1], node Nu[m], node Nw[1], node Nw[m], node Nr[1], and node Nr[m] from time T21 to time T29 and thereabouts. In FIG. 15, high-level potential is represented as "High" and low-level potential is represented as "Low."

[0345] In this operation example, the voltage applied by the wiring VR is set to the ground potential.

[0346] <<Before time T21>> Before time T21, the potentials of the nodes Nu[1] to Nu[m], the nodes Nw[1] to Nw[m], the nodes Nx[1] to Nx[m], and the nodes Nr[1] to Nr[m] are set to the ground potential. Note that the ground potential is represented as GND in FIG. 15.

[0347] A low-level potential is input to each of the wirings WAD and WBD by a circuit WDD (not shown in FIG. 14).

[0348] Furthermore, the wirings XAL[1] to XAL[m] and the wirings XBL[1] to XBL[m] are connected to a reference potential V RFP is entered. RFP can be at a potential higher than ground potential or lower than ground potential.

[0349] In addition, a low-level potential is input to each of the wirings WL[1] to WL[m] by the circuit WLD, so that the transistors M1 included in all the memory cells AMx, AMu, AMw, and AMr in the memory cell array CA are turned off.

[0350] A low-level potential is input to each of the wirings SL4, SL5, and SL7, so that each of the switches SW4A, SW5A, SW5B, SW7A, and SW7B is turned off.

[0351] <<From time T21 to time T22>> Between time T21 and time T22, a high-level potential is input to the line SL5, which turns on the switches SW5A and SW5B included in the circuit INT.

[0352] When the switches SW5A and SW5B are turned on, electrical continuity is established between the wiring BAL and the wiring BBL and the wiring VSL, and a potential is applied to the wiring BAL and the wiring BBL from the wiring VSL. Note that in this operation example, the wiring VSL is a wiring that applies an initialization potential to the wiring BAL and the wiring BBL, and the initialization potential is set to ground potential. Therefore, the potentials of the wiring BAL and the wiring BBL are set to ground potential from time T21 to time T22.

[0353] Furthermore, since the first terminal of each of the transistors M2 included in all of the memory cells AMx, AMu, AMw, and AMr in the memory cell array CA is supplied with a ground potential from the wiring VR, the voltage between the first terminal and the second terminal of each of the transistors M2 is 0 V. Furthermore, since the potentials of the nodes Nx[1] to Nx[m], the nodes Nu[1] to Nu[m], the nodes Nw[1] to Nw[m], and the nodes Nr[1] to Nr[m] are each set to the ground potential, each of the transistors M2 is turned off.

[0354] <<From time T22 to time T23>> Between time T22 and time T23, a high-level potential is input to the wiring WL[1], which causes a high-level potential to be applied to the gates of the transistors M1 included in each of the memory cells AMu[1], AMw[1], AMx[1], and AMr[1] in the memory cell array CA, turning on the transistors M1.

[0355] Between time T22 and time T23, the line WAD is at a potential higher than the ground potential V Wα [1] A potential larger than the ground potential is input. At this time, the transistors M1 of the memory cells AMu[1] and AMw[1] are turned on, so that the line WAD and the node Nu[1] are electrically connected, and the line WAD and the node Nw[1] are electrically connected. Therefore, the first terminal (node ​​Nu[1]) of the capacitance C1 of the memory cell AMu[1] and the first terminal (node ​​Nw[1]) of the capacitance C1 of the memory cell AMw[1] are respectively connected to a potential V Wα [1] A large voltage is input.

[0356] Between time T22 and time T23, the wiring WBD is at a potential higher than the ground potential V Wβ[1] A potential larger than the ground potential is input. At this time, the transistors M1 of the memory cell AMx[1] and the memory cell AMr[1] are in the on state, so that the wiring WBD and the node Nx[1] are in a conductive state, and the wiring WBD and the node Nr[1] are in a conductive state. Therefore, the first terminal (node ​​Nx[1]) of the capacitance C1 of the memory cell AMx[1] and the first terminal (node ​​Nr[1]) of the capacitance C1 of the memory cell AMr[1] are each supplied with a potential V Wβ [1] A large voltage is input.

[0357] where V W [1] is defined as in equation (1.1) described in this embodiment.

[0358] In equation (1.1), V W [1] is the voltage corresponding to the first of the m first data. Wα [1], and V Wβ Each of [1] can be said to be a voltage corresponding to the first of the m first data. If equation (1.1) is satisfied, V Wα [1], and V Wβ The voltage combinations in [1] can be determined arbitrarily. For example, V Wα [1] is V Wβ [1] Higher voltage than V Wβ [1] or V Wβ [1] can be set to the same voltage as V W [1] may be a positive voltage, 0, or a negative voltage.

[0359] Since the switch SW5A is in the on state, the ground potential is input to the wiring BAL. Also, in each of the memory cells AMu[1] and AMw[1], the ground potential from the wiring VR is input to the first terminal of the transistor M2, so the voltage between the first terminal and the second terminal of the transistor M2 is approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of the transistor M2 in each of the memory cells AMu[1] and AMw[1].

[0360] Similarly, because the switch SW5B is in the on state, the ground potential is input to the wiring BBL. Also, in each of the memory cells AMx[1] and AMr[1], the ground potential from the wiring VR is input to the first terminal of the transistor M2, so the voltage between the first terminal and the second terminal of the transistor M2 is also approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of the transistor M2 in each of the memory cells AMx[1] and AMr[1].

[0361] Between time T22 and time T23, a low-level potential continues to be input to each of the wirings WL[2] to WL[m] from before time T22. Therefore, in the circuits CS[2] to CS[m] of the memory cell array CA, a low-level potential is applied to the gate of the transistor M1 included in each of the memory cells AMu, AMw, AMx, and AMr, and each transistor M1 is in an off state. As a result, the data input to each of the wirings WAD and WBD is not written to the nodes Nu[2] to Nu[m], the nodes Nw[2] to Nw[m], the nodes Nx[2] to Nx[m], and the nodes Nr[2] to Nr[m].

[0362] <<From time T23 to time T24>> Between time T23 and time T24, a low-level potential is input to the wiring WL[1], which causes a low-level potential to be applied to the gates of the transistors M1 included in each of the memory cells AMu[1], AMw[1], AMx[1], and AMr[1] in the memory cell array CA, turning off the transistors M1.

[0363] In each of the memory cells AMu[1] and AMw[1], the transistor M1 is turned off, so that the first terminal (node ​​Nu[1]) of the capacitance C1 of the memory cell AMu[1] and the first terminal (node ​​Nw[1]) of the capacitance C1 of the memory cell AMw[1] are set to V Wα [1] A potential higher than the ground potential is maintained. In addition, in each of the memory cells AMx[1] and AMr[1], the transistor M1 is turned off, so that the first terminal (node ​​Nx[1]) of the capacitance C1 of the memory cell AMx[1] and the first terminal (node ​​Nr[1]) of the capacitance C1 of the memory cell AMr[1] are held at V Wβ [1] A large potential is maintained.

[0364] Furthermore, between time T23 and time T24, similar to the write operation of potentials to the memory cells AMu[1], AMw[1], AMx[1], and AMr[1] in the circuit CS[1] between time T22 and time T23, the write operation of potentials to the memory cells AMu, AMw, AMx, and AMr in the circuits CS[2] to CS[m-1] is sequentially performed. Specifically, for example, by sequentially inputting signals that are at a high-level potential for a certain period to the wirings WL[2] to WL[m-1] and changing the potentials of the wirings WAD and WBD in accordance with the signals, a predetermined potential can be written to the memory cells AMu, AMw, AMx, and AMr in the circuits CS[2] to CS[m-1]. Here, V Wα [2]~V Wα In parallel with the operation of writing voltages to the memory cells AMu[2] to AMu[m-1] and the memory cells AMw[2] to AMw[m-1], V is written to the memory cells AMx[2] to AMx[m-1] and the memory cells AMr[2] to AMr[m-1].Wβ [2]~V Wβ [m-1] are written sequentially.

[0365] At this time, the memory cell AMx[p] located in the pth row (p is an integer of 2 or more and m-1 or less) is supplied with a voltage V Wβ [p] is held, and the memory cell AMu[p] is held at the voltage V Wα Here, similarly to equation (1.1), the voltage V corresponding to the pth one of the m first data is held. W [p] is defined as in equation (1.2) described in this embodiment.

[0366] In equation (1.2), V W [p] is the voltage corresponding to the pth one of the m first data. Wα [p] and V Wβ Each of [p] can be said to be a voltage corresponding to the pth one of the m first data. If equation (1.2) is satisfied, V Wα [p] and V Wβ The combination of voltages [p] can be determined arbitrarily. For example, V Wα [p] is V Wβ [p] higher than V Wβ Voltage lower than [p], or V Wβ [p] can be set to the same voltage as V W [p] may be a positive voltage, 0, or a negative voltage.

[0367] <<From time T24 to time T25>> Between time T24 and time T25, a high-level potential is input to the wiring WL[m], which causes a high-level potential to be applied to the gates of the transistors M1 included in each of the memory cells AMu[m], AMw[m], AMx[m], and AMu[m] in the memory cell array CA, turning on the respective transistors M1.

[0368] In addition, between time T24 and time T25, the potential of the wiring WAD is V Wα [m] higher potential is input. At this time, the transistors M1 of the memory cells AMu[m] and AMw[m] are turned on, so that the line WAD and the node Nu[m] are electrically connected, and the line WAD and the node Nw[m] are electrically connected. Therefore, the first terminal (node ​​Nu[m]) of the capacitance C1 of the memory cell AMu[m] and the first terminal (node ​​Nw[m]) of the capacitance C1 of the memory cell AMw[m] are both connected to a potential V higher than the ground potential. Wα [m] A large potential is input.

[0369] In addition, between time T24 and time T25, the wiring WBD is at a potential higher than the ground potential V Wβ [m] higher potential is input. At this time, the transistors M1 of the memory cells AMx[m] and AMr[m] are turned on, so that the wiring WBD and the node Nx[m] are electrically connected, and the wiring WBD and the node Nr[m] are electrically connected. Therefore, the first terminal (node ​​Nx[m]) of the capacitance C1 of the memory cell AMx[m] and the first terminal (node ​​Nr[m]) of the capacitance C1 of the memory cell AMr[m] are both connected to a potential V higher than the ground potential. Wβ [m] A large potential is input.

[0370] where V W [m] is defined as in equation (1.3) described in this embodiment.

[0371] In equation (1.3), V W [m] is the voltage corresponding to the mth of the m first data. Wα [m], and V Wβ Each of [m] can be said to be a voltage corresponding to the mth of the m first data. If equation (1.3) is satisfied, V Wα [m], and V Wβ The voltage combinations for [m] can be determined arbitrarily. For example, V Wα [m] is V Wβ[m] higher voltage, V Wβ [m] or V Wβ [m]. In other words, V W [m] may be a positive voltage, 0, or a negative voltage.

[0372] Since the switch SW5A is in the on state, the ground potential is input to the wiring BAL. Furthermore, in the memory cells AMu[m] and AMw[m], the ground potential from the wiring VR is input to the first terminal of the transistor M2, so the voltage between the first terminal and the second terminal of the transistor M2 is approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of the transistor M2 in each of the memory cells AMu[m] and AMw[m].

[0373] Similarly, because the switch SW5B is in the on state, the ground potential is input to the wiring BBL. Furthermore, in each of the memory cells AMx[m] and AMr[m], the ground potential from the wiring VR is input to the first terminal of the transistor M2, so the voltage between the first terminal and the second terminal of the transistor M2 is also approximately 0 V. Therefore, no current flows between the first terminal and the second terminal of the transistor M2 in each of the memory cells AMx[m] and AMr[m].

[0374] Between time T24 and time T25, a low-level potential continues to be input to each of the wirings WL[1] to WL[m-1] since before time T04. Therefore, in the circuits CS[1] to CS[m-1] of the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in each of the memory cells AMu, AMw, AMx, and AMr, and each transistor M1 is in an off state. As a result, the data input to each of the wirings WAD and WBD is not written to the nodes Nu[1] to Nu[m-1], the nodes Nw[1] to Nw[m-1], the nodes Nx[1] to Nx[m-1], and the nodes Nr[1] to Nr[m-1].

[0375] <<From time T25 to time T26>> Between time T25 and time T26, a low-level potential is input to the wiring WL[m], so that in the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in each of the memory cells AMu[m], AMw[m], AMx[m], and AMr[m], turning off the transistors M1.

[0376] In each of the memory cells AMu[m] and AMw[m], the transistor M1 is turned off, and thus the first terminal (node ​​Nu[m]) of the capacitance C1 of the memory cell AMu[m] and the first terminal (node ​​Nw[m]) of the capacitance C1 of the memory cell AMw[m] are set to V Wα Furthermore, in each of the memory cells AMx[m] and AMr[m], the transistor M1 is turned off, so that the first terminal (node ​​Nx[m]) of the capacitance C1 of the memory cell AMx[m] and the first terminal (node ​​Nr[m]) of the capacitance C1 of the memory cell AMr[m] are held at a potential V higher than the ground potential. Wβ [m] A large potential is maintained.

[0377] By the operation from time T21 to time T26, a voltage according to the first data can be written to each of the memory cells AMx, AMu, AMw, and AMr included in the memory cell array CA.

[0378] <<From time T26 to time T27>> Between time T26 and time T27, a low-level potential is input to the wiring SL5, which turns off the switches SW5A and SW5B in the circuit INT.

[0379] <<From time T27 to time T28>> Between time T27 and time T28, potentials corresponding to m pieces of second data are input to the wirings XAL[1] to XAL[m]. Here, for example, the potential input to the wiring XAL[1] from the circuit XLD is set to V Xα [1] The potential input from the circuit XLD to the wiring XAL[p] is V higher than the ground potential. Xα [p] higher potential, and the potential input from the circuit XLD to the wiring XAL[m] is V higher than the ground potential. Xα [m]High potential.

[0380] The potential of the wire XAL[1] is V Xα [1], the second terminal of the capacitor C1 of each memory cell AMu[1] and memory cell AMx[1] is V Xα At this time, since the nodes Nu[1] and Nx[1] are in an electrically floating state, the potentials of the nodes Nu[1] and Nx[1] change due to the capacitive coupling of the capacitor C1.

[0381] In each of memory cells AMu[1] and AMx[1], the increase in the potential of the gate of transistor M2 is the potential obtained by multiplying the change in the potential of wiring XAL[1] by a capacitance coupling coefficient determined by the configuration of the memory cell. The capacitance coupling coefficient is calculated based on the capacitance of capacitor C1, the gate capacitance of transistor M2, parasitic capacitance, etc. In this operation example, the capacitance coupling coefficient of each of memory cells AMu and AMx is set to h.

[0382] Therefore, the potential change of the wiring XAL[1] is V Xα When [1], the potential changes of the nodes Nu[1] and Nx[1] are hV Xα [1]. In other words, the potential of node Nu[1] is V Wα [1]+hV Xα [1], and the potential of node Nx[1] becomes V Wβ [1]+hV Xα [1]

[0383] In this operation example, the capacitive coupling coefficients of the memory cells other than the memory cell AMu[1] and the memory cell AMx[1] included in the memory cell array CA will also be described as h.

[0384] Therefore, the potential of the wiring XAL[p] is V Xα [p], the second terminal of the capacitor C1 of each memory cell AMu[p] and memory cell AMx[p] is V Xα At this time, since the nodes Nu[p] and Nx[p] are electrically floating, the potentials of the nodes Nu[p] and Nx[p] change due to the capacitive coupling of the capacitor C1. Specifically, the potential of the node Nu[p] is V Wα [p]+hV Xα [p], and the potential of node Nx[p] becomes V Wβ [p]+hV Xα It becomes [p].

[0385] In addition, the potential of the wiring XAL[m] is VXα [m], the second terminal of the capacitor C1 of each memory cell AMu[m] and memory cell AMx[m] is V Xα At this time, since the nodes Nu[m] and Nx[m] are electrically floating, the potentials of the nodes Nu[m] and Nx[m] change due to the capacitive coupling of the capacitor C1. Specifically, the potential of the node Nu[m] changes to V Wα [m]+hV Xα [m], and the potential of node Nx[m] is V Wβ [m]+hV Xα It becomes [m].

[0386] In addition, between time T27 and time T28, potentials corresponding to m pieces of second data are input to each of the wirings XBL[1] to XBL[m]. Here, for example, the potential input to the wiring XBL[1] from the circuit XLD is set to V Xβ [1] The potential input from the circuit XLD to the wiring XBL[p] is V higher than the ground potential. Xβ [p] higher potential, and the potential input from the circuit XLD to the wiring XBL[m] is V Xβ [m]High potential.

[0387] The potential of the wire XBL[1] is V Xβ [1], the second terminal of the capacitor C1 of each memory cell AMw[1] and memory cell AMr[1] is V Xβ At this time, since the nodes Nw[1] and Nr[1] are in an electrically floating state, the potentials of the nodes Nw[1] and Nr[1] change due to the capacitive coupling of the capacitor C1.

[0388] In this operation example, the capacitive coupling coefficients of the memory cells AMw and AMr included in the memory cell array CA will be described as h, similarly to the memory cells AMx and AMu.

[0389] Therefore, the potential change of the wiring XBL[1] is V Xβ When [1], the potential changes of the nodes Nw[1] and Nr[1] are hV Xβ [1]. In other words, the potential of node Nw[1] is V Wα [1]+hV Xβ [1], and the potential of node Nr[1] becomes V Wβ [1]+hV Xβ [1]

[0390] In addition, the potential of the wiring XBL[p] is V Xβ [p], the second terminal of the capacitor C1 of each memory cell AMw[p] and memory cell AMr[p] is V Xβ At this time, since the nodes Nw[p] and Nr[p] are electrically floating, the potentials of the nodes Nw[p] and Nr[p] change due to the capacitive coupling of the capacitor C1. Specifically, the potential of the node Nw[p] is V Wα [p]+hV Xβ [p], and the potential of node Nr[p] becomes V Wβ [p]+hV Xβ It becomes [p].

[0391] In addition, the potential of the wiring XBL[m] is V Xβ [m], the second terminal of the capacitor C1 of each memory cell AMw[m] and memory cell AMr[m] is V Xβ At this time, since the nodes Nw[m] and Nr[m] are electrically floating, the potentials of the nodes Nw[m] and Nr[m] change due to the capacitive coupling of the capacitor C1. Specifically, the potential of the node Nw[m] is V Wα [m]+hV Xβ [m], and the potential of node Nu[m] becomes V Wβ [m]+hV Xβ It becomes [m].

[0392] where V X [1], V X[p] and V X Each of [m] is defined as in equations (1.4) to (1.6) described in this embodiment.

[0393] In each of the formulas (1.4) to (1.6), V X [1]~V X Each of [m] is a voltage according to the second data. Xα [1]~V Xα [m], and V Xβ [1]~V Xβ Each of [m] can be said to be a voltage according to the second data. Xα [i] and V Xβ The combination of voltages [i] can be determined arbitrarily. For example, V Xα [i] is V Xβ [i] is higher than V Xβ Voltage lower than [i], or V Xβ [i] can be set to the same voltage as V X [i] may be a positive voltage, 0, or a negative voltage.

[0394] <<From time T28 to time T29>> Between time T28 and time T29, a high-level potential is input to the wirings SL4 and SL7, which turns on the switches SW7A and SW7B in the circuit CMS and the switch SW4A in the circuit ACTV.

[0395] At this time, the second terminal of the transistor M2 included in each of the memory cells AMx[1] to AMx[m] and the memory cells AMw[1] to AMw[m] is electrically connected to the first terminal of the transistor M3A included in the circuit CM through the wiring BAL. Also, the second terminal of the transistor M2 included in each of the memory cells AMx[1] to AMx[m] and the memory cells AMw[1] to AMw[m] is electrically connected to the first terminal of the circuit IVC included in the circuit ACTV through the wiring BAL. Also, the second terminal of the transistor M2 included in each of the memory cells AMu[1] to AMu[m] and the memory cells AMr[1] to AMr[m] is electrically connected to the first terminal of the transistor M3B included in the circuit CM through the wiring BBL.

[0396] Here, consider the current flowing from the second terminal to the first terminal of the transistor M2 of each of the memory cells AMx, AMu, AMw, and AMr.

[0397] The current flowing from the wiring BAL to the first terminal via the second terminal of the transistor M2 of the memory cell AMx[1] is I AMx[1] When I AMx[1] can be expressed in the same way as equation (1.7) described in this embodiment.

[0398] In equation (1.7), k is a constant determined by the channel length, channel width, mobility, and capacitance of the gate insulating film of the transistor M2. th is the threshold voltage of the transistor M2. Note that the constant k can be applied not only to the memory cell AMx but also to the memory cells AMu, AMw, and AMr. In addition to the memory cell AMx, the threshold voltage of the transistor M2 of the memory cells AMu, AMw, and AMr is also V th Let's say.

[0399] Also, the current flowing from the wiring BAL to the first terminal via the second terminal of the transistor M2 of the memory cell AMx[m] is I AMx[m] When I AMx[m] can be expressed in the same way as equation (1.7) described in this embodiment.

[0400] That is, the sum of the amounts of currents flowing from the wiring BAL to the second terminals of the transistors M2 of the memory cells AMx[1] to AMx[m] is I x When I x can be expressed in the same way as equation (1.9) described in this embodiment from equations (1.7) and (1.8).

[0401] Similarly, the current flowing from the wiring BAL to the first terminal via the second terminal of the transistor M2 of the memory cell AMw[1] is I AMw[1] The current flowing from the wiring BAL to the first terminal via the second terminal of the transistor M2 of the memory cell AMw[m] is I AMw[m] When I AMw[1] , and I AMw[m] can be expressed in the same way as equations (1.10) and (1.11) described in this embodiment.

[0402] That is, the sum of the amounts of currents flowing from the wiring BAL to the second terminals of the transistors M2 of the memory cells AMw[1] to AMw[m] is I w When I w can be expressed in the same way as equation (1.12) described in this embodiment from equations (1.10) and (1.11).

[0403] Similarly, the current flowing from the wiring BBL to the first terminal via the second terminal of the transistor M2 of the memory cell AMu[1] is I AMu[1] The current flowing from the wiring BBL to the first terminal of the transistor M2 of the memory cell AMu[m] via the second terminal is I AMu[m] When I AMu[1] , and I AMu[m] can be expressed in the same way as equations (1.13) and (1.14) described in this embodiment.

[0404] That is, the sum of the amounts of currents flowing from the wiring BBL to the second terminals of the transistors M2 of the memory cells AMu[1] to AMu[m] is I u When I u can be expressed in the same way as equation (1.15) described in this embodiment from equations (1.13) and (1.14).

[0405] Similarly, the current flowing from the wiring BBL to the first terminal via the second terminal of the transistor M2 of the memory cell AMr[1] is I AMr[1] The current flowing from the wiring BBL to the first terminal via the second terminal of the transistor M2 of the memory cell AMr[m] is I AMr[m] When I AMr[1] , and I AMr[m] can be expressed by the following equations, similar to equations (1.16) and (1.17) described in this embodiment.

[0406] That is, the sum of the amounts of currents flowing from the wiring BBL to the second terminals of the transistors M2 of the memory cells AMr[1] to AMr[m] is I r When I r can be expressed in the same way as equation (1.18) described in this embodiment from equations (1.16) and (1.17).

[0407] Between time T28 and time T29, the switch SW7B included in the circuit CMS is in an on state, and the switch SW5B included in the circuit INT is in an off state. Therefore, the total current I u +I r flows from the wiring VHE via the first terminal of the transistor M3B. At this time, the voltage of the first terminal (gate) of the transistor M3B is u +I r The voltage depends on the

[0408] Furthermore, since the circuit CM is a current mirror circuit, the amount of current flowing between the first and second terminals of the transistor M3B is approximately equal to the amount of current flowing between the first and second terminals of the transistor M3A. Between time T12 and time T13, the switch SW7A included in the circuit CMS is in the on state, so the amount of current flowing from the wiring VHE to the wiring BAL via the transistor M3A is I u +I r This becomes:

[0409] Furthermore, since the memory cells AMx[1] to AMx[m] and the memory cells AMw[1] to AMw[m] are electrically connected to the wiring BAL, I x A current of I flows from the wiring BAL to the memory cells AMw[1] to AMw[m]. w A current of flows.

[0410] The switches SW5A and SW5B included in the circuit INT are in the OFF state, and the switch SW4A included in the circuit ACTV is in the ON state, so that a current flows from the wiring BAL through the switch SW4A to the first terminal of the circuit IVC included in the circuit ACTV. EV When I EV can be expressed in the same way as equation (1.19) described in this embodiment.

[0411] Therefore, by using equations (1.1) to (1.6), (1.9), (1.12), (1.15), and (1.18), equation (1.19) can be written as follows, similar to equation (1.20):

[0412]

number

[0413] From equation (1.23), the amount of current I input from wiring BAL to circuit ACTVEV is the potential V according to the first data W [1]~V W [m] and the potential V according to the second data X [1]~V X In other words, the sum of the products of the first and second data is proportional to the amount of current I EV It can be expressed as:

[0414] Connect I to the first terminal of the circuit IVC included in the circuit ACTV. EV As a result of the current flowing, the third terminal of the circuit IVC is EV Then, the voltage is input to the first terminal of the circuit ACF, and the circuit ACF uses the voltage to perform a calculation of a function system defined in advance, and the calculation result is output from the wiring NIL as a voltage (or a current, etc.).

[0415] By the way, each of the formulas (1.1) to (1.3) is V Wα [i]=V Wβ [i]+V W [i]. That is, the memory cell AMu[i] and the memory cell AMw[i] have V Wβ [i]+V W [i] is retained. V Wβ [i] can be any voltage, so V Wβ [1]~V Wβ [m] may all be set to the same voltage. For example, V Wβ [1]~V Wβ [m] to V PR Then, memory cell AMu[i] and memory cell AMw[i] each have V PR +V W [i] is held, and V is held in each of the memory cells AMx[i] and AMr[i]. PR Thus, V Wβ [1]~V Wβ [m] are all V PR By doing so, V PRThe calculation of equation (1.23) can also be performed by using as a reference voltage, holding a voltage in memory cells AMu and AMw that is the reference voltage plus a voltage corresponding to the first data, and holding the reference voltage in memory cells AMx and AMr.

[0416] Furthermore, each of the formulas (1.4) to (1.6) is V Xα [i]=V Xβ [i]+V X [i]. That is, between time T11 and time T12, V Xβ [i]+V X [i] is entered. V Xβ [i] can be any voltage, so V Xβ [1]~V Xβ [m] may all be set to the same voltage. For example, V Xβ [1]~V Xβ [m] to V RFP When this is done, the wiring XAL[i] has V RFP +V X [i] is input, and V is input to the wiring XBL[i]. RFP In this way, V Xβ [1]~V Xβ [m] are all V RFP By doing so, V RFP The calculation of equation (1.23) can also be performed by using as a reference voltage, inputting a voltage obtained by adding a voltage corresponding to the second data to the reference voltage to the line XAL, and inputting the reference voltage to the line XBL.

[0417] <Configuration Example 5 of Semiconductor Device> Here, a semiconductor device that is different from the arithmetic circuit MAC5 in FIG. 12 and is capable of performing a product-sum operation between a plurality of first data and a plurality of second data will be described.

[0418] The arithmetic circuit MAC6 in Fig. 16 is an example of a semiconductor device capable of performing a product-sum operation between a plurality of first data and a plurality of second data, similar to the arithmetic circuit MAC5 in Fig. 12. The arithmetic circuit MAC6 differs from the arithmetic circuit MAC5 in the circuit configuration of the circuit CMS and in that the wiring BBL is electrically connected to the circuit ACTV.

[0419] The circuit CMS included in the arithmetic circuit MAC6 has a current source CSA and a current source CSB. An input terminal of the current source CSA is electrically connected to the wiring VHE, and an output terminal of the current source CSA is electrically connected to the wiring BAL. An input terminal of the current source CSB is electrically connected to the wiring VHE, and an output terminal of the current source CSB is electrically connected to the wiring BBL.

[0420] It should be noted that the circuit CMS included in the arithmetic circuit MAC6 has the above-mentioned circuit configuration and therefore does not have the function as a current mirror circuit shown in FIGS. 3A and 3B.

[0421] For example, the wiring VHE can be a wiring that applies a constant voltage, similar to the description of the circuit CMS in Figures 3A and 3B. The constant voltage is preferably, for example, a high-level potential.

[0422] Each of the current sources CSA and CSB has a function of outputting a constant current to an output terminal when a power supply potential is input to an input terminal. It is preferable that the amounts of current output from the current sources CSA and CSB to their output terminals are equal to each other. Specifically, the amount of current flowing from the output terminal of the current source CSA to the wiring BAL is preferably 0.85 times or more, 0.9 times or more, or 0.95 times or more, and preferably 1.05 times or less, 1.1 times or less, or 1.15 times or less, of the amount of current flowing from the output terminal of the current source CSB to the wiring BBL. It is also possible to combine the above-mentioned lower and upper limits.

[0423] 16, the circuit ACTV preferably has a function of outputting a voltage corresponding to the difference between the current flowing from the wiring BAL to the circuit ACTV and the current flowing from the wiring BBL to the circuit ACTV, a function of performing a calculation according to a predefined function system using the voltage, and a function of outputting the result of the calculation of the function to the wiring NIL.

[0424] Specifically, the circuit ACTV included in the arithmetic circuit MAC6 in FIG. 16 can be, for example, the circuit ACTV shown in FIG.

[0425] In the circuit ACTV of Figure 9, for example, by inputting a high-level potential to the wiring SL4 and turning on each of the switches SW4A and SW4B, a current from the wiring BAL can flow to the first terminal of the circuit IVC, and a current from the wiring BBL can flow to the third terminal of the circuit IVC.

[0426] For example, in the arithmetic circuit MAC6 of FIG. 16, the current sources CSA and CSB respectively control the amounts of current flowing through the wiring BAL and wiring BBL. CS The total amount of current flowing from the wiring BAL to the memory cells AMx[1] to AMx[m] is I x The sum of the currents flowing from the wiring BAL to the memory cells AMw[1] to AMw[m] is I w Then, the amount of current flowing from the wire BAL to the first terminal of the circuit IVC is I CS -I x -I w The sum of the currents flowing from the wiring BBL to the memory cells AMu[1] to AMu[m] is expressed as I u The total amount of current flowing from the wiring BBL to the memory cells AMr[1] to AMr[m] is I r Then, the amount of current flowing from the wire BBL to the third terminal of the circuit IVC is I CS -I u -I r This becomes:

[0427] When the circuit IVC in FIG. 9 is used as a subtraction circuit (for example, when the loads LEA and LEB are resistors), the second terminal of the circuit IVC outputs the difference (-I u -I r +I x +I w ) is output. This difference in current amount is determined by the sum of the products of the multiple first data and the multiple second data according to equations (1.19) and (1.20), so the voltage output from the second terminal of the circuit IVC can be said to be a voltage according to the result of the sum of the products of the multiple first data and the multiple second data.

[0428] The voltage is then input to the first terminal of the circuit ACF, and the circuit ACF uses the voltage to perform a calculation of a function system predefined by the circuit ACF, and the calculation result is output from the wiring NIL as a voltage (or current, etc.).

[0429] <Configuration Example 6 of Semiconductor Device> Next, a semiconductor device that is different from the arithmetic circuit MAC5 in FIG. 12 and the arithmetic circuit MAC6 in FIG. 16 and that is capable of performing a product-sum operation between a plurality of first data and a plurality of second data will be described.

[0430] The arithmetic circuit MAC7 of FIG. 17 is an example of a semiconductor device capable of performing a multiply-and-accumulate operation between a plurality of first data and a plurality of second data, similar to the arithmetic circuits MAC5 and MAC6. The arithmetic circuit MAC7 is a modified example of the arithmetic circuit MAC5, and differs from the arithmetic circuit MAC5 in that the wiring XBL[1] and the wiring XBL[2] in the arithmetic circuit MAC5 are combined into a single wiring XBL[1,2], and the wiring XBL[m-1] and the wiring XBL[m] in the arithmetic circuit MAC5 are combined into a single wiring XBL[m-1,m]. In other words, the number of wirings XBL in the arithmetic circuit MAC7 of FIG. 17 is m / 2. However, in the arithmetic circuit MAC7 of FIG. 17, m is an even number equal to or greater than 2.

[0431] Therefore, the arithmetic circuit MAC7 shown in Figure 17 is configured such that the memory cells AMw[1], AMr[1], AMw[2], and AMr[2] are electrically connected to the wiring XBL[1,2], and the memory cells AMw[m-1], AMr[m-1], AMw[m], and AMr[m] are electrically connected to the wiring XBL[m-1,m].

[0432] 17, each memory cell is arranged in a matrix of 2m rows and 2 columns, similar to the arithmetic circuit MAC5. In FIG. 17, as an example, memory cell AMu[i] is arranged at an address of 2i-1 row, 1st column, memory cell AMw[i] is arranged at an address of 2i row, 1st column, memory cell AMx[i] is arranged at an address of 2i-1 row, 2nd column, memory cell AMr[i] is arranged at an address of 2i row, 2nd column, memory cell AMu[i+1] is arranged at an address of 2i+2 row, 1st column, memory cell AMw[i+1] is arranged at an address of 2i+1 row, 1st column, memory cell AMx[i+1] is arranged at an address of 2i+2 row, 2nd column, and memory cell AMr[i+1] is arranged at an address of 2i+1 row, 2nd column. In the arithmetic circuit MAC7 of FIG. 17, i is an odd number between 1 and m.

[0433] For this reason, although not shown in Figure 17, memory cells AMw[i], AMr[i], AMw[i+1], and AMr[i+1] are electrically connected to wiring XBL[i, i+1].

[0434] Next, an example of the operation of the arithmetic circuit MAC7 in Fig. 17 will be described. Note that the example of the operation of the arithmetic circuit MAC7 will be explained with reference to the example of the operation in the timing chart in Fig. 15, and the explanation will mainly focus on the parts not shown in the timing chart.

[0435] The voltage corresponding to the first data is V W [1]~V W [m] and V is set to satisfy the formulas (1.1) to (1.3). Wα[1]~V Wα [m], and V Wβ [1]~V Wβ Also, a voltage V is applied to each of the memory cells AMw[1] to AMw[m] and the memory cells AMu[1] to AMu[m]. Wα [1]~V Wα [m] is held, and V is held in the memory cells AMx[1] to AMx[m] and the memory cells AMr[1] to AMr[m]. Wβ [1]~V Wβ [m] is assumed to be held.

[0436] In addition, the voltages corresponding to the second data are V X [1]~V X [m] and V is set to satisfy equations (1.4) to (1.6). Xα [1]~V Xα [m], and V Xβ [1]~V Xβ Define [m], where V Xβ [i] and V Xβ [i+1] is assumed to be the same voltage, V Xβ [i]=V Xβ [i+1]=V Xβ [i, i+1]. In this way, the voltage V according to the plurality of second data X [1]~V X By defining [m], in the arithmetic circuit MAC7, a voltage V Xα [1]~V Xα [m] can be input, and V can be input to each of the wirings XBL[1,2] to XBL[m-1,m]. Xβ [1,2] to V Xβ You can enter [m-1,m].

[0437] Between time T27 and time T28, the arithmetic circuit MAC7 applies a voltage V Xα [1]~V Xα [m] and V is input to each of the wirings XBL[1,2] to XBL[m-1,m].Xβ [1,2] to V Xβ By inputting [m-1, m], it is possible to perform a product-sum operation between a plurality of first data and a plurality of second data, and to perform a function operation, similar to the arithmetic circuit MAC5.

[0438] The arithmetic circuit MAC7 has a configuration in which the number of wirings XBL is smaller than that of the arithmetic circuit MAC5, so the circuit area of ​​the arithmetic circuit MAC7 can be made smaller than that of the arithmetic circuit MAC5. Also, the number of voltage signals input to the wirings XBL of the arithmetic circuit MAC7 is smaller than that of the arithmetic circuit MAC5, so the power consumption of the arithmetic circuit MAC7 can be made smaller than that of the arithmetic circuit MAC5.

[0439] In the above, V Xβ [i] and V Xβ [i+1] is assumed to be the same voltage, but as explained in the operation example of the arithmetic circuit MAC5, V Xβ [1]~V Xβ [m] are all at the same voltage (for example, V RFP ) may be used.

[0440] <Configuration Example 7 of Semiconductor Device> Next, a semiconductor device capable of performing a multiply-and-accumulate operation between a plurality of first data and a plurality of second data, which is different from the arithmetic circuit MAC5 in FIG. 12, the arithmetic circuit MAC6 in FIG. 16, and the arithmetic circuit MAC7 in FIG. 17, will be described.

[0441] 18 is an example of a semiconductor device capable of performing a product-sum operation between a plurality of first data and a plurality of second data, similar to the arithmetic circuits MAC5, MAC6, and MAC7. The arithmetic circuit MAC8 is a modified example of the arithmetic circuit MAC5, and differs from the arithmetic circuit MAC5 in that a circuit CSb is provided in the memory cell array CA.

[0442] 18, the circuit CSb has memory cells AMub, AMwb, AMxb, and AMrb. Note that the memory cell AMub corresponds to the memory cell AMu in each of the circuits CS[1] to CS[m], the memory cell AMwb corresponds to the memory cell AMw in each of the circuits CS[1] to CS[m], the memory cell AMxb corresponds to the memory cell AMx in each of the circuits CS[1] to CS[m], and the memory cell AMrb corresponds to the memory cell AMr in each of the circuits CS[1] to CS[m].

[0443] Next, an example of the operation of the arithmetic circuit MAC8 will be described. Note that the example of the operation of the arithmetic circuit MAC8 will be explained with reference to the example of operation in the timing chart of Fig. 15, and the explanation will mainly focus on the parts not shown in the timing chart.

[0444] The voltage corresponding to the first data is V W [1]~V W [m] and V is set to satisfy the formulas (1.1) to (1.3). Wα [1]~V Wα [m], and V Wβ [1]~V Wβ Also, a voltage V is applied to each of the memory cells AMw[1] to AMw[m] and the memory cells AMu[1] to AMu[m]. Wα [1]~V Wα [m] is held, and V is held in the memory cells AMx[1] to AMx[m] and the memory cells AMr[1] to AMr[m]. Wβ [1]~V Wβ [m] is assumed to be held.

[0445] Also, for example, between time T25 and time T26 in the timing chart of FIG. 15, the memory cells AMub and AMwb are at the voltage V Wbα The memory cells AMxb and AMrb are held at the voltage V Wbβ Also, V Wb =VWbα -V Wbβ Voltage V Wb Define

[0446] Also, for example, between time T27 and time T28 in the timing chart of FIG. 15, the line XALb is supplied with a voltage V Xbα is input, and the voltage V Xbβ is input. Also, V Xb =V Xbα -V Xbβ Voltage V Xb Define

[0447] At this time, between time T28 and time T29 in the timing chart of FIG. 15, the amount of current flowing through the wiring BAL of each of the memory cells AMwb and AMxb is I AMwb , I AMxb When I AMwb , and I AMxb Each of the AMwb =k(V Wbα +V Xbβ -V th ) 2 , I AMxb =k(V Wbβ +V Xbα -V th ) 2 In addition, the amount of current flowing through the wiring BBL of each of the memory cells AMub and AMrb can be expressed as I AMub , I AMrb When I AMub , and I AMrb Each of the AMub =k(V Wbα +V Xbα -V th ) 2 , I AMrb =k(V Wbβ +V Xbβ -V th ) 2 It can be expressed as:

[0448] In addition, between time T28 and time T29 in the timing chart of FIG. 15, the amount of current I flowing from the wiring BAL to the circuit ACTV EV is expressed as follows. Here, I b =I AMub +I AMrb +I AMxb +I AMwb It states that:

[0449]

number

[0450] Equation (1.24), like equation (1.22), is an equation that assigns an arbitrary value to the result of a sum of products. This can be used, for example, in calculations in a hierarchical neural network, to assign an arbitrary bias to the result of a sum of products between weight coefficients and neuron signals.

[0451] In addition, for example, the sum I of the currents flowing from the wiring BBL to the memory cells AMub and AMrb AMub +I AMrb Therefore, the sum I of the currents flowing from the wiring BAL to the memory cell AMxb and the memory cell AMwb AMxb +I AMwb By increasing I in equation (1.24), b can be less than 0. That is, any value given to the result of the sum of products can be negative.

[0452] In at least one of the memory cells AMub, AMwb, AMxb, and AMrb, the amount of current flowing between the first terminal and the second terminal of the transistor M2 may be set to 0. For example, by setting the amount of current flowing between the first terminal and the second terminal of the transistor M2 in each of the memory cells AMwb, AMxb, and AMrb to 0, the amount of current I b I b =I AMubIn addition, by setting the amount of current flowing between the first terminal and the second terminal of the transistor M2 of each of the memory cells AMub, AMxb, and AMrb to 0, the amount of current I b I b =I AMwb can be replaced with . In other words, when setting an arbitrary value to be given to the result of a multiply-and-accumulate operation, it is not necessary to use all of the currents flowing between the first and second terminals of the transistors M2 of the memory cells AMub, AMwb, AMxb, and AMrb. Therefore, the arithmetic circuit MAC8 may be configured such that at least one of the memory cells AMub, AMwb, AMxb, and AMrb is not provided in the circuit CSb. For example, the circuit CSb may be configured to include only the memory cells AMub and AMxb, or to include only the memory cells AMwb and AMrb, or to include only the memory cells AMub and AMwb, or to include only the memory cells AMxb and AMrb. Furthermore, for example, the circuit CSb may be configured to include any one of the memory cells AMub, AMwb, AMxb, and AMrb, and may be configured such that only one memory cell selected from the memory cells AMub, AMwb, AMxb, and AMrb is not provided.

[0453] Note that the semiconductor device of one embodiment of the present invention is not limited to the arithmetic circuits MAC5 to MAC8 described in this embodiment. For example, when multiple multiply-and-accumulate operations are performed simultaneously using the same multiple second data, the arithmetic circuit MAC9 shown in Figure 19 can be used. The arithmetic circuit MAC9 has a configuration in which n memory cell arrays CA (n is an integer of 1 or more) of the arithmetic circuit MAC5 in Figure 12 are arranged for each column.

[0454] 19 illustrates memory cell arrays CA[1] to CA[n], and the memory cell arrays CA[1] to CA[n] are collectively referred to as memory cell arrays CAS. Also, since the arithmetic circuit MAC9 has n memory cell arrays CA, in FIG. 19, the circuit CMS has circuits CM[1] to CM[n] as n circuits CM, the circuit INT has circuits SCI[1] to SCI[n] as n circuits SCI, and the circuit ACTV has circuits ACP[1] to ACP[n] as n circuits ACP. In addition, the arithmetic circuit MAC9 has wiring BAL[1] to wiring BAL[n] corresponding to the wiring BAL of the arithmetic circuit MAC5, wiring BBL[1] to wiring BBL[n] corresponding to the wiring BBL of the arithmetic circuit MAC5, wiring WAD[1] to wiring WAD[n] corresponding to the wiring WAD of the arithmetic circuit MAC5, wiring WBD[1] to wiring WBD[n] corresponding to the wiring WBD of the arithmetic circuit MAC5, and wiring NIL[1] to wiring NIL[n] corresponding to the wiring NIL of the arithmetic circuit MAC5.

[0455] The memory cell array CA[1] is electrically connected to the wiring BAL[1], the wiring BBL[1], the wiring WAD[1], the wiring WBD[1], the wiring XAL[1] to the wiring XAL[m], the wiring XBL[1] to the wiring XBL[m], and the wiring WL[1] to the wiring WL[m]. The circuit WDD is electrically connected to the wiring WAD[1] and the wiring WBD[1]. The circuit CM[1] of the circuit CMS is electrically connected to the wiring BAL[1] and the wiring BBL[1], and the circuit SCI[1] of the circuit INT is electrically connected to the wiring BAL[1], the wiring BBL[1], and the circuit ACP[1] of the circuit ACTV. The circuit ACP[1] is electrically connected to the wiring NIL[1].

[0456] Similarly, the memory cell array CA[n] is electrically connected to wirings BAL[n], BBL[n], WAD[n], WBD[n], XAL[1] to XAL[m], XBL[1] to XBL[m], and WL[1] to WL[m]. The circuit WDD is electrically connected to wirings WAD[n] and WBD[n]. The circuit CM[n] of the circuit CMS is electrically connected to wirings BAL[n] and BBL[n], and the circuit SCI[n] of the circuit INT is electrically connected to wirings BAL[n], BBL[n], and ACP[n] of the circuit ACTV. The circuit ACP[n] is electrically connected to wiring NIL[n].

[0457] Similar to the operation of the timing chart of Figure 15, the arithmetic circuit MAC9 of Figure 19 writes voltages corresponding to the multiple first data included in the first group to the nth group to each of the memory cell arrays CA[1] to CA[n], and then inputs voltages corresponding to the second data to the wirings XAL[1] to XAL[m] and the wirings XBL[1] to XBL[m], thereby simultaneously outputting the product-sum operations of the multiple first data and multiple second data of each of the first group to the nth group to the wirings NIL[1] to NIL[n].

[0458] Although the transistors included in the arithmetic circuits MAC5 to MAC9 are OS transistors or Si transistors in this embodiment, one embodiment of the present invention is not limited thereto. The transistors included in the arithmetic circuits MAC5 to MAC9 may be, for example, transistors including Ge or the like in a channel formation region, transistors including a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe in a channel formation region, transistors including a carbon nanotube in a channel formation region, or transistors including an organic semiconductor in a channel formation region.

[0459] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0460] (Embodiment 2) In this embodiment, an example of an arithmetic circuit that can simultaneously perform a plurality of product-sum operations, which is a semiconductor device of one embodiment of the present invention, will be described.

[0461] <Configuration Example 1 of Semiconductor Device> Fig. 20 shows a configuration example of a semiconductor device capable of performing a multiply-and-accumulate operation between a plurality of first data and a plurality of second data. The semiconductor device shown in Fig. 20 can, for example, simultaneously perform a plurality of multiply-and-accumulate operations. The semiconductor device in Fig. 20 can also perform a function operation using the result of the multiply-and-accumulate operation as an input value. The semiconductor device in Fig. 20 can also simultaneously perform a plurality of function operations.

[0462] 20 is a circuit that performs a multiply-and-accumulate operation on a plurality of first data stored in a plurality of memory cells and a plurality of input second data, and performs a function operation using the result of the multiply-and-accumulate operation, similar to the arithmetic circuit MAC5 described in the above embodiment. Note that the plurality of first data and the plurality of second data can be, for example, analog data or multi-valued data (discrete data).

[0463] The arithmetic circuit MAC10 includes, for example, a memory cell array CA, a circuit CMS1, a circuit CMS2, a circuit WDD, a circuit XLD, a circuit WLD, a circuit INT, and a circuit ACTV.

[0464] The memory cell array CA includes circuits CUW[1,1] to CUW[m,n] (where m and n are integers equal to or greater than 1) and circuits CXR[1] to CXR[m]. Each of the circuits CUW[1,1] to CUW[m,n] includes a memory cell AMu and a memory cell AMw, and each of the circuits CXR[1] to CXR[m] includes a memory cell AMx and a memory cell AMr. Although not shown in FIG. 20 , in this specification and the like, the memory cells AMu and AMw included in the circuit CUW[i,j] (where i is an integer equal to or greater than 1 and m, and j is an integer equal to or greater than 1 and n) may be referred to as memory cells AMu[i,j] and memory cells AMw[i,j], respectively. Also, in this specification and the like, the memory cells AMx and AMr included in the circuit CXR[i] may be referred to as memory cells AMx[j] and memory cells AMr[j], respectively.

[0465] In the memory cell array CA, the memory cells are arranged in a matrix of 2m rows and n+1 columns. In Fig. 20, for example, the memory cell AMu[i,j] is arranged at an address of 2i-1 rows and j columns, the memory cell AMw[i,j] is arranged at an address of 2i rows and j columns, the memory cell AMx[i] is arranged at an address of 2i-1 rows and n+1 columns, and the memory cell AMr[i] is arranged at an address of 2i rows and n+1 columns.

[0466] Each of the memory cells AMx, AMw, AMu, and AMr has a function of holding a voltage corresponding to first data. Note that the voltage corresponding to the first data can be, for example, the difference between the voltage held in the memory cells AMu[i,j] and AMw[i,j] and the voltage held in the memory cells AMx[i] and AMr[i].

[0467] In particular, the memory cells in the first to nth columns of the memory cell array CA each hold a voltage corresponding to a plurality of first data items in the first to nth groups. Specifically, for example, the voltages corresponding to the plurality of first data items included in the first group are held in the memory cells AMu[1,1] to AMu[m,1] and the memory cells AMw[1,1] to AMw[m,1] located in the first column, and the voltages corresponding to the plurality of first data items included in the nth group are held in the memory cells AMu[1,n] to AMu[m,n] and the memory cells AMw[1,n] to AMw[m,n] located in the nth column. In this way, the voltages corresponding to the plurality of first data items included in the jth group are held in the memory cells AMu[1,j] to AMu[m,j] and the memory cells AMw[1,j] to AMw[m,j] located in the jth column.

[0468] The memory cell AMu[1,1] is electrically connected to the wiring WAD[1], the wiring BAP[1], the wiring WL[1], and the wiring XAL[1]. The memory cell AMw[1,1] is electrically connected to the wiring WAD[1], the wiring BAN[1], the wiring WL[1], and the wiring XBL[1]. The memory cell AMu[1,n] is electrically connected to the wiring WAD[n], the wiring BAP[n], the wiring WL[1], and the wiring XAL[1]. The memory cell AMw[1,n] is electrically connected to the wiring WAD[n], the wiring BAN[n], the wiring WL[1], and the wiring XBL[1]. The memory cell AMx[1] is electrically connected to the wiring WBD, the wiring BBP, the wiring WL[1], and the wiring XAL[1]. Furthermore, the memory cell AMr[1] is electrically connected to the wiring WBD, the wiring BBN, the wiring WL[1], and the wiring XBL[1]. The memory cell AMu[m,1] is electrically connected to the wiring WAD[1], the wiring BAP[1], the wiring WL[m], and the wiring XAL[m]. The memory cell AMw[m,1] is electrically connected to the wiring WAD[1], the wiring BAN[1], the wiring WL[m], and the wiring XBL[m]. The memory cell AMu[m,n] is electrically connected to the wiring WAD[n], the wiring BAP[n], the wiring WL[m], and the wiring XAL[m]. The memory cell AMw[m,n] is electrically connected to the wiring WAD[n], the wiring BAN[n], the wiring WL[m], and the wiring XBL[m]. The memory cell AMx[m] is electrically connected to the wiring WBD, the wiring BBP, the wiring WL[m], and the wiring XAL[m]. The memory cell AMr[m] is electrically connected to the wiring WBD, the wiring BBN, the wiring WL[m], and the wiring XBL[m].

[0469] The detailed circuit configurations of the memory cells AMu and AMw included in each of the circuits CUW[1,1] to CUW[m,n], and the memory cells AMx and AMr included in each of the circuits CXR[1] to CXR[m], can be similar to those of the memory cells AMu, AMw, AMx, and AMr that can be applied to the arithmetic circuit MAC5 described in the above embodiment.

[0470] The circuit CMS1 includes, for example, circuits CMA[1] to CMA[n] and a circuit CMB. The circuit CMA[1] is electrically connected to wirings BAN[1] and BAP[1], the circuit CMA[n] is electrically connected to wirings BAN[n] and BAP[n], and the circuit CMB is electrically connected to wirings BBN and BBP.

[0471] The circuit CMA[j] has, for example, a function of supplying current to the memory cells AMu[1,j] to AMu[m,j] through the wiring BAP[j] and a function of supplying current to the memory cells AMw[1,j] to AMw[m,j] through the wiring BAN[j]. Note that the amount of current flowing through the wiring BAP[j] by the circuit CMA[j] is preferably equal to the amount of current flowing through the wiring BAN[j]. Specifically, for example, the amount of current flowing from the circuit CMA[j] to the wiring BAP[j] is preferably 0.85 times or more, 0.9 times or more, or 0.95 times or more, and preferably 1.05 times or less, 1.1 times or less, or 1.15 times or less, of the amount of current flowing from the circuit CMA[j] to the wiring BAN[j]. Note that the above-mentioned lower limit and upper limit values ​​can be combined with each other.

[0472] The circuit CMB has, for example, a function of supplying current to the memory cells AMx[1] to AMx[m] via the wiring BBP and a function of supplying current to the memory cells AMr[1] to AMr[m] via the wiring BBN. ​​Note that the amount of current flowing through the wiring BBP by the circuit CMB is preferably equal to the amount of current flowing through the wiring BBN. ​​Specifically, the amount of current flowing from the circuit CMB to the wiring BBP is preferably 0.85 times or more, 0.9 times or more, or 0.95 times or more, and preferably 1.05 times or less, 1.1 times or less, or 1.15 times or less, of the amount of current flowing from the circuit CMB to the wiring BBN. ​​Note that the above-described lower limit and upper limit values ​​can be combined with each other.

[0473] A specific example of the configuration of the circuit CMS1 will be described later.

[0474] For example, the circuit WDD is electrically connected to the wirings WAD[1] to WAD[n] and the wiring WBD. The circuit WDD has a function of transmitting data to be stored in each memory cell of the memory cell array CA. For the circuit WDD, refer to the description of the circuit WDD included in the arithmetic circuit MAC5 described in Embodiment 1.

[0475] For the circuit WLD, the description of the circuit WLD included in the arithmetic circuit MAC5 described in the first embodiment is to be taken into consideration.

[0476] For the circuit XLD, the description of the circuit XLD included in the arithmetic circuit MAC5 described in the first embodiment is to be referred to.

[0477] For example, the circuit INT is electrically connected to the wirings BAP[1] to BAP[n], the wirings BAN[1] to BAN[n], the wirings BBP, and the wirings BBN. ​​The circuit INT has a function of inputting a predetermined voltage to each of the wirings BAP[1] to BAP[n], the wirings BAN[1] to BAN[n], the wirings BBP, and the wirings BBN. ​​Note that the voltage may be, for example, a low-level potential or a ground potential.

[0478] As a specific configuration example, the circuit INT includes circuits SCIA[1] to SCIA[n] and a circuit SCIB. Each of the circuits SCIA[1] to SCIA[n] and the circuit SCIB can have the same configuration as the circuit SCI included in the circuit INT of the arithmetic circuit MAC5. Specifically, in FIG. 20, the circuit INT includes the circuits SCIA[1] to SCIA[n] and the circuit SCIB, each of which includes a switch SW5A and a switch SW5B. In the circuit SCIA[j], the first terminal of the switch SW5A is electrically connected to the wiring BAN[j], the second terminal of the switch SW5A is electrically connected to the wiring VSL, the first terminal of the switch SW5B is electrically connected to the wiring BAP[j], and the second terminal of the switch SW5B is electrically connected to the wiring VSL. The control terminals of the switches SW5A and SW5B are electrically connected to the wiring SL5. Similarly, in the circuit SCIB, a first terminal of the switch SW5A is electrically connected to the wiring BBN, a second terminal of the switch SW5A is electrically connected to the wiring VSL, a first terminal of the switch SW5B is electrically connected to the wiring BBP, and a second terminal of the switch SW5B is electrically connected to the wiring VSL. Also, the control terminals of the switches SW5A and SW5B are electrically connected to the wiring SL5.

[0479] In this embodiment, each of the switches SW5A and SW5B is turned on when a high-level potential is input to the control terminal, and turned off when a low-level potential is input to the control terminal.

[0480] For example, the wiring SL5 functions as a wiring that supplies a voltage for switching the switches SW5A and SW5B between a conductive state and a non-conductive state. Therefore, the voltage can be, for example, a high-level potential or a low-level potential.

[0481] The wiring VSL functions as a wiring that applies a constant voltage, for example, a low-level potential, a ground potential, or the like.

[0482] As an example, the circuit CMS2 is electrically connected to the wirings BAN[1] to BAN[n] and the wiring BBN. ​​The circuit CMS2 has, for example, a function of draining the current flowing through the wiring BBN and a function of draining the current flowing through each of the wirings BAN[1] to BAN[n]. Note that the amount of current drained from the wiring BBN by the circuit CMS2 is preferably equal to the amount of current drained from each of the wirings BAN[1] to BAN[n]. Specifically, for example, the amount of current flowing from the wiring BBN to the circuit CMS2 is preferably 0.85 times or more, 0.9 times or more, or 0.95 times or more, and preferably 1.05 times or less, 1.1 times or less, or 1.15 times or less, of the amount of current flowing from the wiring BAN[j] to the circuit CMS2. Note that the above-mentioned lower limit and upper limit values ​​can be combined with each other.

[0483] The circuit ACTV includes, for example, circuits ACP[1] to ACP[n]. The circuit ACP[1] is electrically connected to the wiring BAN[1] and the wiring NIL[1], and the circuit ACP[n] is electrically connected to the wiring BAN[n] and the wiring NIL[n]. The circuits ACP[1] to ACP[n] may have the same configuration as the circuit ACP included in the circuit ACTV of the arithmetic circuit MAC5 described in the first embodiment. Note that while each of FIGS. 4A to 4C and 5A to 5C illustrates a configuration in which the first terminal of the switch SW4A is electrically connected to the wiring BAL, in this embodiment, the wiring BAL shown in FIGS. 4A to 4C and 5A to 5C will be replaced with the wiring BAN.

[0484] <<Configuration example of memory cell array CA>> Next, configuration examples of the memory cells AMu and AMw included in each of the circuits CUW[1,1] to CUW[m,n] of the memory cell array CA, and the memory cells AMx and AMr included in each of the circuits CXR[1] to CXR[m] will be described.

[0485] 21 is a circuit diagram showing an example of the configuration of a memory cell array CA. Like the arithmetic circuit MAC5 described in the above embodiment, the memory cell array CA has a function of calculating the sum of products of multiple first data and multiple second data.

[0486] 21 are similar to the memory cells AMu, AMw, AMx, and AMr shown in Fig. 13. Therefore, the description of the circuit elements included in the memory cells AMw, AMx, and AMr should refer to the respective contents of the memory cells AMu, AMw, AMx, and AMr described in the above embodiments.

[0487] In each of the memory cells AMu[i,1] to AMu[i,n], the gate of the transistor M1 is electrically connected to the wiring WL[i], and the second terminal of the capacitor C1 is electrically connected to the wiring XAL[i]. In the memory cell AMu[i,1], the second terminal of the transistor M1 is electrically connected to the wiring WAD[1], and the second terminal of the transistor M2 is electrically connected to the wiring BAP[1]. In the memory cell AMu[i,n], the second terminal of the transistor M1 is electrically connected to the wiring WAD[n], and the second terminal of the transistor M2 is electrically connected to the wiring BAP[n]. Note that, although not shown in FIG. 21 , in the memory cell AMu[i,j], the second terminal of the transistor M1 is electrically connected to the wiring WAD[j], and the second terminal of the transistor M2 is electrically connected to the wiring BAP[j]. In the memory cell AMu[i,j], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is defined as a node Nu[i,j].

[0488] In each of the memory cells AMw[i,1] to AMw[i,n], the gate of the transistor M1 is electrically connected to the wiring WL[i], and the second terminal of the capacitor C1 is electrically connected to the wiring XBL[i]. In the memory cell AMw[i,1], the second terminal of the transistor M1 is electrically connected to the wiring WAD[1], and the second terminal of the transistor M2 is electrically connected to the wiring BAN[1]. In the memory cell AMw[i,n], the second terminal of the transistor M1 is electrically connected to the wiring WAD[n], and the second terminal of the transistor M2 is electrically connected to the wiring BAN[n]. Note that, although not shown in FIG. 21 , in the memory cell AMw[i,j], the second terminal of the transistor M1 is electrically connected to the wiring WAD[j], and the second terminal of the transistor M2 is electrically connected to the wiring BAN[j]. In the memory cell AMw[i,j], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is defined as a node Nw[i,j].

[0489] In the memory cell AMx[i], the gate of the transistor M1 is electrically connected to the wiring WL[i], the second terminal of the capacitor C1 is electrically connected to the wiring XAL[i], the second terminal of the transistor M1 is electrically connected to the wiring WBD, and the second terminal of the transistor M2 is electrically connected to the wiring BBP. In the memory cell AMx[i], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is defined as a node Nx[i].

[0490] In the memory cell AMr[i], the gate of the transistor M1 is electrically connected to the wiring WL[i], the second terminal of the capacitor C1 is electrically connected to the wiring XBL[i], the second terminal of the transistor M1 is electrically connected to the wiring WBD, and the second terminal of the transistor M2 is electrically connected to the wiring BBN. ​​In the memory cell AMr[i], the electrical connection point between the first terminal of the transistor M1, the gate of the transistor M2, and the first terminal of the capacitor C1 is defined as a node Nr[i].

[0491] <<Example of circuit CMS1 configuration>> Next, an example of a circuit configuration that can be applied to the circuits CMA[1] to CMA[n] and the circuit CMB included in the circuit CMS1 in FIG. 20 will be described.

[0492] The circuit CMS1 in Fig. 21 illustrates an example of a circuit configuration that can be applied to the circuits CMA[1] to CMA[n] and the circuit CMB. Specifically, the configuration of the circuit CM in Fig. 3A is applied to the circuits CMA[1] to CMA[n] and the circuit CMB shown in Fig. 21. Therefore, the description of the circuit CM described in the above embodiment should be taken into consideration for the circuit configurations of the circuits CMA[1] to CMA[n] and the circuit CMB shown in Fig. 21 and the circuit elements included therein.

[0493] In the circuit CMA[1], the second terminal of the switch SW7A is electrically connected to the wiring BAN[1], and the second terminal of the switch SW7B is electrically connected to the wiring BAP[1]. In the circuit CMA[n], the second terminal of the switch SW7A is electrically connected to the wiring BAN[n], and the second terminal of the switch SW7B is electrically connected to the wiring BAP[n]. Although not shown in FIG. 21, in the circuit CMA[j], the second terminal of the switch SW7A is electrically connected to the wiring BAN[j], and the second terminal of the switch SW7B is electrically connected to the wiring BAP[j]. In the circuit CMB, the second terminal of the switch SW7A is electrically connected to the wiring BBN, and the second terminal of the switch SW7B is electrically connected to the wiring BBP.

[0494] <<Example of circuit CMS2 configuration>> Next, an example of the circuit configuration of the circuit CMS2 in FIG. 20 will be described.

[0495] As the circuit CMS2 in Fig. 20, for example, the circuit configuration of the circuit CMS2 shown in Fig. 21 can be applied. As an example, the circuit CMS2 in Fig. 21 includes switches SW8A[1] to SW8A[n], a switch SW8B, transistors M6A[1] to M6A[n], and a transistor M6B.

[0496] A first terminal of the switch SW8A[1] is electrically connected to the wiring BAN[1] and the circuit ACP[1] (illustrated in FIG. 20 but not shown in FIG. 21), and a second terminal of the switch SW8A[1] is electrically connected to the first terminal of the transistor M6A[1]. The second terminal of the transistor M6A[1] is electrically connected to the wiring VLL. A first terminal of the switch SW8A[n] is electrically connected to the wiring BAN[n] and the circuit ACP[n] (illustrated in FIG. 20 but not shown in FIG. 21), and a second terminal of the switch SW8A[n] is electrically connected to the first terminal of the transistor M6A[n]. The second terminal of the transistor M6A[n] is electrically connected to the wiring VLL. A first terminal of the switch SW8B is electrically connected to the wiring BBN, and a second terminal of the switch SW8B is electrically connected to the first terminal of the transistor M6B. A second terminal of the transistor M6B is electrically connected to the wiring VLL. A gate of the transistor M6B is electrically connected to a second terminal of the switch SW8B, a first terminal of the transistor M6B, and gates of the transistors M6A[1] to M6A[n]. A wiring SL8 is electrically connected to control terminals of the switches SW8A[1] to SW8A[n] and the switch SW8B.

[0497] Note that, for example, switches applicable to the switches SW5A and SW5B can be used as the switches SW8A[1] to SW8A[n] and the switch SW8B. In the present embodiment, the switches SW8A and SW8B are each turned on when a high-level potential is input to a control terminal, and turned off when a low-level potential is input to the control terminal.

[0498] For example, the wiring SL8 functions as a wiring that supplies a voltage for switching the switches SW8A[1] to SW8A[n] and the switch SW8B between a conductive state and a non-conductive state. Therefore, the voltage can be, for example, a high-level potential or a low-level potential.

[0499] The wiring VLL functions as a wiring that applies a constant voltage, for example, which is preferably a low-level potential, a ground potential, or the like.

[0500] Furthermore, each of the transistors M6A[1] to M6A[n] and the transistor M6B is preferably, for example, an n-channel transistor. Each of the transistors M6A[1] to M6A[n] and the transistor M6B can be, for example, an OS transistor or a Si transistor. The OS transistor can be a transistor applicable to the transistor M1 or the transistor M2. When the transistors M6A[1] to M6A[n] and the transistor M6B are Si transistors, the silicon contained in the channel formation region of the Si transistor can be, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like.

[0501] Unless otherwise specified, the transistors M6A[1] to M6A[n] and M6B may operate in a saturation region when on. That is, the transistors M6A[1] to M6A[n] and M6B may operate in a saturation region when on. That is, the transistors M6A[1] to M6A[n] and M6B may operate in a saturation region when their gates, sources, and drains are appropriately supplied with voltages within the ranges required for operation in the saturation region. However, one embodiment of the present invention is not limited to this. To reduce the amplitude of the supplied voltage, the transistors M6A[1] to M6A[n] and M6B may operate in a linear region. Alternatively, to reduce the amount of current flowing through the transistors M6A[1] to M6A[n] and M6B, the transistors M6A[1] to M6A[n] and M6B may operate in a subthreshold region. Alternatively, the transistors M6A[1] to M6A[n] and the transistor M6B may operate in a linear region, a saturation region, and a subthreshold region in a mixed manner, or may operate in a linear region and a saturation region in a mixed manner, or may operate in a saturation region and a subthreshold region in a mixed manner, or may operate in a linear region and a subthreshold region in a mixed manner.

[0502] 21 functions as a current mirror circuit due to the above-described configuration. Specifically, the circuit CMS2 in FIG. 21 has a function of referring to the potential of the first terminal (wiring BBN) of the transistor M6B and causing a current corresponding to the potential to flow between the source and drain of each of the transistors M6A[1] to M6A[n] and the transistor M6B. In other words, the circuit CMS2 has a function of causing a current approximately equal in amount to the current flowing between the source and drain of the transistor M6B to flow between the source and drain of each of the transistors M6A[1] to M6A[n].

[0503] The configuration of the circuit CMS2 is not limited to the configuration shown in Fig. 21. The configuration of the circuit CMS2 may be, for example, as shown in Fig. 22, in which the transistors M6A[1] to M6A[n] and the transistors M7A[1] to M7A[n] are cascode-connected, and the transistor M6B and the transistor M7B are cascode-connected. Specifically, the second terminal of the transistor M6A[1] is electrically connected to the first terminal of the transistor M7A[1], and the second terminal of the transistor M7A[1] is electrically connected to the wiring VLL. The second terminal of the transistor M6A[n] is electrically connected to the first terminal of the transistor M7A[n], and the second terminal of the transistor M7A[n] is electrically connected to the wiring VLL. 22, by cascode-connecting the transistors included in the circuit CMS2, the operation of the current mirror circuit by the circuit CMS2 can be made more stable.

[0504] The configuration of the circuit CMS2 may be changed, for example, as shown in the circuit CMS2 in FIG. 23, by changing the electrical connection points of the switches SW8A[1] to SW8A[n]. Note that FIG. 23 also illustrates the circuit ACTV of FIG. 4A as an example, in addition to the circuit CMS2. The circuit ACTV of FIG. 23 includes n circuits ACP. In the circuit CMS2 of FIG. 23, the first terminal of the switch SW8A[1] is electrically connected to the wiring BAN[1], and the second terminal of the switch SW8A[1] is electrically connected to the circuit ACP[1] and the first terminal of the transistor M6A[1]. The first terminal of the switch SW8A[n] is electrically connected to the wiring BAN[n], and the second terminal of the switch SW8A[n] is electrically connected to the circuit ACP[n] and the first terminal of the transistor M6A[n]. By applying the circuit CMS2 of FIG. 23 to the circuit CMS2 of the arithmetic circuit MAC10, the circuits ACP[1] to ACP[n] of the circuit ACTV of FIG. 4A can be configured without the switch SW4A. That is, the functions of the switches SW4A included in the circuits ACP[1] to ACP[n] of the circuit ACTV of FIG. 4A can be performed by the switches SW8A[1] to SW8A[n] included in the circuit CMS2 of FIG. 23. Therefore, by applying the circuit CMS2 of FIG. 23 to the circuit CMS2 of the arithmetic circuit MAC10, the number of circuit elements can be reduced, thereby reducing the circuit area of ​​the arithmetic circuit MAC10 and / or the power consumption of the arithmetic circuit MAC10. Note that while FIG. 23 illustrates the circuit ACF of FIG. 4A, the circuit ACF shown in FIG. 23 may be the circuit ACF of FIG. 4B, FIG. 4C, FIG. 5A to FIG. 5C, etc.

[0505] <Example of operation of an arithmetic circuit> Next, an example of the operation of the arithmetic circuit MAC10 will be described.

[0506] In this case, the memory cell array CA, the circuit CMS1, the circuit INT, and the circuit CMS2 of the arithmetic circuit MAC10 are respectively the memory cell array CA, the circuit CMS1, the circuit INT, and the circuit CMS2 shown in Fig. 21. Although not shown, the circuit ACTV of the arithmetic circuit MAC10 in Fig. 20 is the circuit ACTV of Fig. 4A.

[0507] 24 and 25 show timing charts of an example of the operation of the arithmetic circuit MAC10. The timing chart of Figure 24 shows the fluctuations in the potential of wiring WL[1], wiring WL[m], wiring SL4, wiring SL5, wiring SL7, and wiring SL8 from time T31 to time T39 and around there, and the timing chart of Figure 25 shows the fluctuations in the potential of wiring WAD[1], wiring WAD[n], wiring WBD, wiring XAL[1], wiring XAL[m], wiring XBL[1], wiring XBL[m], node Nu[1,1], node Nw[1,1], node Nu[1,n], node Nw[1,n], node Nx[1], node Nr[1], node Nu[m,1], node Nw[m,1], node Nu[m,n], node Nw[m,n], node Nx[m], and node Nr[m] from time T31 to time T39 and around there. 24, a high level potential is represented as "High" and a low level potential is represented as "Low." Also, in FIG. 25, a ground potential is represented as "GND."

[0508] In this operation example, the voltage applied by the wiring VR is set to the ground potential, the voltage applied by the wiring VHE is set to the high-level potential, and the voltage applied by the wiring VLL is set to the ground potential.

[0509] First, a plurality of first data held in the arithmetic circuit MAC10 and a plurality of second data input to the arithmetic circuit MAC10 will be described using an operation example.

[0510] In this operation example, for example, in the arithmetic circuit MAC10, each of the memory cells AMu and AMw included in the circuits CUW[1,j] to CUW[m,j] located in the jth column of the memory cell array CA holds a voltage corresponding to the m first data included in the jth group.

[0511] Here, the voltage according to the m first data of the jth group is V W [1,j] to V W Define [m,j]. Also, V is set to satisfy the following equation. Wα Define [i,j]. Note that V Wβ can be any reference voltage.

[0512]

number

[0513] V W [i,j] is the voltage corresponding to the i-th one of the m first data included in the j-th group. Wα [i,j] can also be said to be a voltage corresponding to the i-th one of the m first data included in the j-th group.

[0514] As will be described in detail later, each of the memory cells AMu and AMw included in the circuits CUW[1,j] to CUW[m,j] located in the j-th column of the memory cell array CA stores m pieces of first data included in the j-th group, such as V Wα [1,j] to V Wα [m, j] is held in each of the memory cells AMx and AMr included in the circuits CXR[1] to CXR[m] located in the n+1th column of the memory cell array CA. Wβ is maintained.

[0515] Next, V is set as a voltage according to m pieces of second data. X [1]~V X Specifically, V is defined so that the following equation is satisfied.Xα Define [i]. Note that V Xβ can be any reference voltage.

[0516]

number

[0517] V X [i] is the voltage corresponding to the i-th of the m second data. Xα [i] can also be said to be a voltage corresponding to the i-th of the m pieces of second data.

[0518] Although the details will be described later, when m pieces of second data are input to the memory cell array CA, V Xα [1]~V Xα [m], and V is input to each of the wiring XBL[1] to wiring XBL[m]. Xβ The following is to be input.

[0519] <<Before time T31>> At times prior to time T31, the potentials of nodes Nu[1,1] to Nu[m,n], nodes Nw[1,1] to Nw[m,n], nodes Nx[1] to Nx[m], and nodes Nr[1] to Nr[m] are assumed to be at ground potential.

[0520] Further, a low-level potential is input to each of the wirings WAD[1] to WAD[n] and the wiring WBD by the circuit WDD (not shown in FIG. 21).

[0521] Further, the wirings XAL[1] to XAL[m] and the wirings XBL[1] to XBL[m] are connected to a reference potential V RFP is entered. RFP can be at a potential higher than ground potential or lower than ground potential.

[0522] In addition, a low-level potential is input to each of the wirings WL[1] to WL[m] by the circuit WLD (not shown in FIG. 21), so that the transistors M1 included in all the memory cells AMx, AMu, AMw, and AMr in the memory cell array CA are turned off.

[0523] A low-level potential is input to each of the wirings SL4, SL5, SL7, and SL8, so that each of the switches SW4A, SW5A, SW5B, SW7A, SW7B, SW8A[1] to SW8A[n], and SW8B is turned off.

[0524] <<From time T31 to time T32>> Between time T31 and time T32, a high-level potential is input to the line SL5, which turns on the switches SW5A and SW5B included in the circuit INT.

[0525] When the switches SW5A and SW5B are turned on, the wirings BAN[1] to BAN[n], BAP[1] to BAP[n], BBN, and BBP are electrically connected to the wiring VSL, and a potential from the wiring VSL is applied to the wirings BAN[1] to BAN[n], BAP[1] to BAP[n], BBN, and BBP. Note that in this operation example, the wiring VSL applies an initialization potential to the wirings BAN[1] to BAN[n], BAP[1] to BAP[n], BBN, and BBP, and the initialization potential is set to ground potential. Therefore, between time T31 and time T32, the potentials of the wirings BAN[1] to BAN[n], BAP[1] to BAP[n], BBN, and BBP are set to ground potential.

[0526] Furthermore, since the first terminal of each of the transistors M2 included in all of the memory cells AMx, AMu, AMw, and AMr in the memory cell array CA is supplied with a ground potential from the wiring VR, the voltage between the first terminal and the second terminal of each of the transistors M2 is 0 V. Furthermore, since the potentials of the nodes Nu[1,1] to Nu[m,n], the nodes Nw[1,1] to Nw[m,n], the nodes Nx[1] to Nx[m], and the nodes Nr[1] to Nr[m] are each set to the ground potential, each of the transistors M2 is turned off.

[0527] <<From time T32 to time T33>> Between time T32 and time T33, a high-level potential is input to the wiring WL[1]. As a result, in the memory cell array CA, a high-level potential is applied to the gates of the transistors M1 included in each of the memory cells AMu[1,1] to AMu[1,n], the memory cells AMw[1,1] to AMw[1,n], the memory cells AMx[1], and the memory cells AMr[1], and each of the transistors M1 is turned on.

[0528] Between time T32 and time T33, V Wα [1,1] to V Wα [1,n] is input. Now, focusing on the j-th column of the memory cell array CA, the transistors M1 of the memory cells AMu[1,j] and AMw[1,j] are in the on state, so that the line WAD[j] and the node Nu[m,j] are in a conductive state, and the line WAD[j] and the node Nw[1,j] are in a conductive state. Therefore, the first terminal (node ​​Nu[1,j]) of the capacitance C1 of the memory cell AMu[1,j] and the first terminal (node ​​Nw[1,j]) of the capacitance C1 of the memory cell AMw[1,j] are respectively connected to V WαFor example, when j=1, the potential of V is input to the first terminal (node ​​Nu[1,1]) of the capacitance C1 of the memory cell AMu[1,1] and the first terminal (node ​​Nw[1,1]) of the capacitance C1 of the memory cell AMw[1,1]. Wα [1,1] is input, and when j=n, for example, the first terminal (node ​​Nu[1,n]) of the capacitance C1 of the memory cell AMu[1,n] and the first terminal (node ​​Nw[1,n]) of the capacitance C1 of the memory cell AMw[1,n] are respectively supplied with V Wα A potential of [1,n] is input.

[0529] Between time T32 and time T33, the wiring WBD is connected to V Wβ At this time, the transistors M1 of the memory cell AMx[1] and the memory cell AMr[1] are turned on, so that the wiring WBD and the node Nx[1] are electrically connected, and the wiring WBD and the node Nr[1] are electrically connected. Therefore, the first terminal (node ​​Nx[1]) of the capacitor C1 of the memory cell AMx[1] and the first terminal (node ​​Nr[1]) of the capacitor C1 of the memory cell AMr[1] are respectively connected to V Wβ The potential is input.

[0530] Between time T32 and time T33, a low-level potential continues to be input to each of the wirings WL[2] to WL[m] since before time T22. Therefore, in the circuits CUW[2] to CUW[m] and circuits CXR[2] to CXR[m] of the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in the memory cells AMu, AMw, AMx, and AMr, respectively, and each transistor M1 is in an off state. As a result, the data input to each of the wirings WAD[1] to WAD[n] and wiring WBD is not written to the retention nodes of the memory cells included in each of the circuits CUW[2] to CUW[m] and circuits CXR[2] to CXR[m].

[0531] <<From time T33 to time T34>> Between time T33 and time T34, a low-level potential is input to the wiring WL[1]. As a result, in the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in each of the memory cells AMu[1,1] to AMu[1,n], the memory cells AMw[1,1] to AMw[1,n], the memory cells AMx[1], and the memory cells AMr[1], and each of the transistors M1 is turned off.

[0532] When focusing on the j-th column of the memory cell array CA, in each of the memory cells AMu[1,j] and AMw[1,j], the transistor M1 is turned off, and V is applied to the first terminal (node ​​Nu[1,j]) of the capacitance C1 of the memory cell AMu[1,j] and the first terminal (node ​​Nw[1,j]) of the capacitance C1 of the memory cell AMw[1,j]. Wα For example, when j=1, the potential of V is maintained at the first terminal (node ​​Nu[1,1]) of the capacitance C1 of the memory cell AMu[1,1] and the first terminal (node ​​Nw[1,1]) of the capacitance C1 of the memory cell AMw[1,1]. Wα For example, when j=n, the potential of V is applied to the first terminal (node ​​Nu[1,n]) of the capacitance C1 of the memory cell AMu[1,n] and the first terminal (node ​​Nw[1,n]) of the capacitance C1 of the memory cell AMw[1,n]. Wα In addition, in each of the memory cells AMx[1] and AMr[1], the transistor M1 is turned off, so that the first terminal (node ​​Nx[1]) of the capacitance C1 of the memory cell AMx[1] and the first terminal (node ​​Nr[1]) of the capacitance C1 of the memory cell AMr[1] are held at the potential V Wβ The potential is maintained at .

[0533] Furthermore, between time T33 and time T34, similar to the operation of writing potentials to the memory cells AMu and AMw in circuits CUW[1,1] to circuit CUW[1,n] and the memory cells AMx and AMr in circuit CXR[1] between time T32 and time T33, the operation of writing potentials to the memory cells AMu, AMw, AMx, and AMr in circuits CUW[2,1] to circuit CUW[m-1,n] and circuits CXR[2] to circuit CXR[m-1] is performed sequentially. Specifically, for example, by sequentially inputting signals that are at a high-level potential for a certain period to the wirings WL[2] to WL[m-1] and changing the potentials of the wirings WAD[1] to WAD[n] and the wiring WBD in accordance with the signals, a predetermined potential can be written to the memory cells AMu and AMw in the circuits CUW[2,1] to CUW[m-1,n] and the memory cells AMx and AMr in the circuits CXR[2] to CXR[m-1]. Wα [2,1] to V Wα In parallel with the voltage write operation to each of the memory cells AMu[2,1] to AMu[m-1,n] and the memory cells AMw[2,1] to AMw[m-1,n], V is written to each of the memory cells AMx[2] to AMx[m-1] and the memory cells AMr[2] to AMr[m-1]. Wβ are written sequentially.

[0534] <<From time T34 to time T35>> Between time T34 and time T35, a high-level potential is input to the wiring WL[m], so that in the memory cell array CA, a high-level potential is applied to the gates of the transistors M1 included in each of the memory cells AMu[m,1] to AMu[m,n], the memory cells AMw[m,1] to AMw[m,n], the memory cells AMx[m], and the memory cells AMr[m], and each of the transistors M1 is turned on.

[0535] Between time T34 and time T35, V Wα [m,1] to V Wα [m,n] is input. Now, focusing on the j-th column of the memory cell array CA, the transistors M1 of the memory cells AMu[m,j] and AMw[m,j] are in the on state, so that the line WAD[j] and the node Nu[m,j] are in a conductive state, and the line WAD[j] and the node Nw[m,j] are in a conductive state. Therefore, the first terminal (node ​​Nu[m,j]) of the capacitance C1 of the memory cell AMu[m,j] and the first terminal (node ​​Nw[m,j]) of the capacitance C1 of the memory cell AMw[m,j] are respectively connected to V Wα For example, when j=1, the potential of V is input to the first terminal (node ​​Nu[m,1]) of the capacitance C1 of the memory cell AMu[m,1] and the first terminal (node ​​Nw[m,1]) of the capacitance C1 of the memory cell AMw[m,1]. Wα [m, 1] is input, and when j=n, for example, the first terminal (node ​​Nu[m, n]) of the capacitance C1 of the memory cell AMu[m, n] and the first terminal (node ​​Nw[m, n]) of the capacitance C1 of the memory cell AMw[m, n] are respectively supplied with V Wα The potential of [m, n] is input.

[0536] In addition, between time T34 and time T35, V WβAt this time, the transistors M1 of the memory cells AMx[m] and AMr[m] are turned on, so that the wiring WBD and the node Nx[m] are electrically connected, and the wiring WBD and the node Nr[m] are electrically connected. Therefore, the first terminal (node ​​Nx[m]) of the capacitor C1 of the memory cell AMx[m] and the first terminal (node ​​Nr[m]) of the capacitor C1 of the memory cell AMr[m] are respectively connected to the potential V Wβ The potential is input.

[0537] Between time T34 and time T35, a low-level potential continues to be input to each of the wirings WL[1] to WL[m-1] from before time T34. Therefore, in the circuits CUW[1] to CUW[m-1] and circuits CXR[1] to CXR[m-1] of the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in the memory cells AMu, AMw, AMx, and AMr, respectively, and each transistor M1 is in an off state. As a result, the data input to each of the wirings WAD[1] to WAD[n] and wiring WBD is not written to the retention nodes of the memory cells included in each of the circuits CUW[1] to CUW[m-1] and circuits CXR[1] to CXR[m-1].

[0538] <<From time T35 to time T36>> Between time T35 and time T36, a low-level potential is input to the wiring WL[m], so that in the memory cell array CA, a low-level potential is applied to the gates of the transistors M1 included in each of the memory cells AMu[m,1] to AMu[m,n], memory cells AMw[m,1] to AMw[m,n], memory cells AMx[m], and memory cells AMr[m], turning off the transistors M1.

[0539] When focusing on the j-th column of the memory cell array CA, in each of the memory cells AMu[m,j] and AMw[m,j], the transistor M1 is turned off, and V is applied to the first terminal (node ​​Nu[m,j]) of the capacitance C1 of the memory cell AMu[m,j] and the first terminal (node ​​Nw[m,j]) of the capacitance C1 of the memory cell AMw[m,j]. Wα For example, when j=1, the potential of the first terminal (node ​​Nu[m,1]) of the capacitance C1 of the memory cell AMu[m,1] and the potential of the first terminal (node ​​Nw[m,1]) of the capacitance C1 of the memory cell AMw[m,1] are maintained. Wα For example, when j=n, the potential of V is applied to the first terminal (node ​​Nu[m,n]) of the capacitance C1 of the memory cell AMu[m,n] and the first terminal (node ​​Nw[m,n]) of the capacitance C1 of the memory cell AMw[m,n]. Wα In addition, in each of the memory cells AMx[m] and AMr[m], the transistor M1 is turned off, so that the first terminal (node ​​Nx[m]) of the capacitance C1 of the memory cell AMx[m] and the first terminal (node ​​Nr[m]) of the capacitance C1 of the memory cell AMr[m] are held at the potential V Wβ The potential of [m] is maintained.

[0540] By the operation from time T31 to time T36, a voltage according to the first data can be written to each of the memory cells AMx, AMu, AMw, and AMr included in the memory cell array CA.

[0541] <<From time T36 to time T37>> Between time T36 and time T37, a low-level potential is input to the wiring SL5, which turns off the switches SW5A and SW5B in the circuit INT.

[0542] <<From time T37 to time T38>> Between time T37 and time T38, the wirings XAL[1] to XAL[m] are supplied with V as potentials according to the m pieces of second data. Xα [1]~V Xα For example, when focusing on the i-th row of the memory cell array CA, the wiring XAL[i] is connected to the circuit XLD and V Xα The potential of [i] is input.

[0543] The potential of the wire XAL[i] is V Xα [i], the second terminal of the capacitor C1 of each of the memory cells AMu[i,1] to AMu[i,n] and the memory cell AMx[i] is V Xα At this time, since each of the nodes Nu[i,1] to Nu[i,n] and the node Nx[i] is in an electrically floating state, the potentials of each of the nodes Nu[i,1] to Nu[i,n] and the node Nx[i] change due to the capacitive coupling of the capacitor C1.

[0544] In each of the memory cells AMu[i,1] to AMu[i,n] and AMx[i], the increase in the gate potential of the transistor M2 is equal to the potential obtained by multiplying the change in the potential of the wiring XAL[i] by a capacitive coupling coefficient determined by the configuration of the memory cell. The capacitive coupling coefficient is calculated based on the capacitance of the capacitor C1, the gate capacitance of the transistor M2, parasitic capacitance, etc. In this operation example, the capacitive coupling coefficient of each of the memory cells AMu and AMx is denoted by h.

[0545] Therefore, the potential change of the wiring XAL[i] is V Xα When the node Nx[i,1] is in the non-zero state, the potential changes of the nodes Nu[i,1] to Nu[i,n] and the node Nx[i] are hV Xα At this time, the potential of node Nu[i,j] is V Wα [i,j]+hV Xα [i], and the potential of node Nx[i] becomes V Wβ +hV Xα It becomes [i].

[0546] For example, when i=1 and j=1, the potential of node Nu[1,1] is V Wα [1,1]+hV Xα [1], and when i=1 and j=n, the potential of node Nu[1,n] is V Wα [1,n]+hV Xα [1], and when i=m and j=1, the potential of node Nu[m,1] is V Wα [m,1]+hV Xα [m], and when i=m and j=n, the potential of node Nu[m,n] is V Wα [m,n]+hV Xα [m]. For example, when i=1, the potential of node Nx[1] is V Wβ +hV Xα [1], and when i=m, the potential of node Nx[n] is V Wβ +hV Xα It becomes [n].

[0547] In this operation example, the capacitive coupling coefficients of not only the memory cells AMu and AMx but also the memory cells AMw and AMr included in the memory cell array CA will be described as h.

[0548] Between time T37 and time T38, the potentials of the wirings XBL[1] to XBL[m] are V Xβ Here, when i is an integer between 1 and m, the wiring XBL[i] has a line from the circuit XLD to V Xβ The potential is input.

[0549] The potential of the wire XBL[i] is V Xβ [i], the second terminal of the capacitor C1 of each of the memory cells AMw[i,1] to AMw[i,n] and the memory cell AMr[i] is V XβAt this time, since the nodes Nw[i,1] to Nw[i,n] and the node Nr[i] are each in an electrically floating state, the potentials of the nodes Nw[i,1] to Nw[i,n] and the node Nr[i] change due to the capacitive coupling of the capacitor C1.

[0550] Therefore, the potential change of the wiring XBL[i] is V Xβ When this is the case, the potential changes of the nodes Nw[i,1] to Nw[i,n] and the node Nr[i] are hV Xβ At this time, the potential of the node Nw[i,j] is V Wα [i,j]+hV Xβ The potential of node Nr[i] is V Wβ +hV Xβ This becomes:

[0551] For example, when i=1 and j=1, the potential of the node Nw[1,1] is V Wα [1,1]+hV Xβ When i=1 and j=n, the potential of the node Nw[1,n] is V Wα [1,n]+hV Xβ When i=m and j=1, the potential of node Nw[m,1] is V Wα [m,1]+hV Xβ When i=m and j=n, the potential of node Nw[m,n] is V Wα [m,n]+hV Xβ For example, when i=1, the potential of node Nr[1] is V Wβ +hV Xβ When i=m, the potential of node Nr[n] is also V Wβ +hV Xβ This becomes:

[0552] <<From time T38 to time T39>> Between time T38 and time T39, a high-level potential is input to the wirings SL4, SL7, and SL8, which turns on the switches SW7A and SW7B in the circuit CMS1, the switch SW4A in the circuit ACTV, and the switches SW8A[1] to SW8A[n] and SW8B in the circuit CMS2.

[0553] At this time, the second terminal of the transistor M2 included in each of the memory cells AMx[1] to AMx[m] is electrically connected to the first terminal of the transistor M3B included in the circuit CMB via the wiring BBP. Also, the second terminal of the transistor M2 included in each of the memory cells AMr[1] to AMr[m] is electrically connected to the first terminal of the transistor M3A included in the circuit CMB and the first terminal of the transistor M6B of the circuit CMS2 via the wiring BBN.

[0554] Therefore, the total amount of current flowing from the wiring BBP to the second terminal of each of the transistors M2 of the memory cells AMx[1] to AMx[m] is I x can be expressed as follows from equation (1.9):

[0555]

number

[0556] In addition, the sum I of the amount of current flowing from the wiring BBN to the second terminal of each of the transistors M2 of the memory cells AMr[1] to AMr[m] r can be expressed as follows from equation (1.18):

[0557]

number

[0558] Since the wiring BBP is in a state of electrical continuity with the first terminal of the transistor M3B of the circuit CMB, the circuit CMB supplies a current amount I x In addition, since the circuit CMB is configured as a current mirror circuit, the circuit CMB passes a current of I x A current of is passed through.

[0559] At this time, since the line BBN and the first terminal of the transistor M6B of the circuit CMS2 are in a conductive state, a current of I x -I r In this case, I x -I r must be a value greater than or equal to 0.

[0560] Now, let's focus on the memory cell in the j-th column of the memory cell array CA. Between time T38 and time T39, the second terminal of the transistor M2 included in each of memory cells AMu[1,j] to AMu[m,j] is electrically connected to the first terminal of the transistor M3B included in the circuit CMA[j] via the wiring BAP[j]. The second terminal of the transistor M2 included in each of memory cells AMw[1,j] to AMw[m,j] is electrically connected to the first terminal of the transistor M3A included in the circuit CMA[j] and the first terminal of the transistor M6A[j] included in the circuit CMS2 via the wiring BAN[j].

[0561] Therefore, the sum of the amounts of currents flowing from the wiring BAP[j] to the second terminals of the transistors M2 of the memory cells AMu[1,j] to AMx[m,j] is I u When [j] is used, I u [j] can be expressed as follows from equation (1.15):

[0562]

number

[0563] Furthermore, the sum of the amounts of currents flowing from the wiring BAN[j] to the second terminals of the transistors M2 of the memory cells AMw[1,j] to AMw[m,j] is I w When [j] is used, I w [j] can be expressed as follows from equation (1.12):

[0564]

number

[0565] Since the wiring BAP[j] is in a conductive state with the first terminal of the transistor M3B of the circuit CMA[j], the circuit CMA[j] supplies a current amount I u In addition, since the circuit CMA[j] is configured as a current mirror circuit, the circuit CMA[j] passes a current of I u A current of [j] is passed through.

[0566] In addition, the wiring BAN[j] is in a conductive state with the first terminal of the transistor M6A[j] of the circuit CMS2. Since the circuit CMS2 is configured as a current mirror circuit, the current amount I x -I r A current of flows.

[0567] At this time, the amount of current flowing from the wiring BAN[j] to the circuit ACP[j] is I EV When [j] is used, I EV [j] can be expressed as follows using equations (2.1) to (2.6):

[0568]

number

[0569] From equation (2.7), the amount of current I input from wiring BAN[j] to circuit ACP[j] of circuit ACTV EV [j] is the potential V corresponding to each of the plurality of first data in the j-th group. W ...

Claims

[Claim 1] a first cell, a second cell, a third cell, a fourth cell, a current mirror circuit, a first wiring, a second wiring, a third wiring, and a fourth wiring; each of the first cell, the second cell, the third cell, and the fourth cell includes a first transistor, a second transistor, and a capacitance; In each of the first cell, the second cell, the third cell, and the fourth cell, a first terminal of the first transistor is electrically connected to a first terminal of the capacitance and a gate of the second transistor; a first terminal of the second transistor of the first cell is electrically connected to the first wiring; a second terminal of the capacitance of the first cell is electrically connected to the third wiring; a first terminal of the second transistor of the second cell is electrically connected to the first wiring; a second terminal of the capacitance of the second cell is electrically connected to the fourth wiring; a first terminal of the second transistor of the third cell is electrically connected to the second wiring; a second terminal of the capacitance of the third cell is electrically connected to the third wiring; a first terminal of the second transistor of the fourth cell is electrically connected to the second wiring; a second terminal of the capacitance of the fourth cell is electrically connected to the fourth wiring; the current mirror circuit is electrically connected to the first wiring and the second wiring, the current mirror circuit has a function of causing a current corresponding to a potential of the first wiring to flow through the second wiring; the first data is determined according to a difference between the first potential and the second potential; The first cell has a function of holding the first potential at a first terminal of the capacitance of the first cell, The second cell has a function of holding the second potential at a first terminal of the capacitance of the second cell, The third cell has a function of holding the second potential at a first terminal of the capacitance of the third cell, The fourth cell has a function of holding the first potential at a first terminal of the capacitance of the fourth cell, the second data is determined according to a difference between the third potential and the fourth potential; When the third potential is input to the third wiring and the fourth potential is input to the fourth wiring, an amount of current obtained by subtracting an amount of current flowing from the second wiring to the first terminal of the second transistor of the third cell and an amount of current flowing from the second wiring to the first terminal of the second transistor of the fourth cell from an amount of current flowing from the current mirror circuit to the second wiring is an amount corresponding to the product of the first data and the second data. Semiconductor device.

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