Semiconductor device

Abstract

To provide a storage device capable of enhancing storage capacity per unit area without complicating processes.SOLUTION: A storage device has a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. Each of the plurality of memory cells has a switching element, and a capacitive element having a first electrode and a second electrode. In at least one of the plurality of memory cells, the switching element controls connection between one bit line of the plurality of bit lines and the first electrode according to a potential given to one word line of the plurality of word lines, and the second electrode is connected with another word line different from the one word line of the plurality of word lines.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a memory device and a semiconductor device using the memory device. [Background technology]

[0002] DRAM (Dynamic Random Access Memory), a type of semiconductor memory device (hereinafter simply referred to as a memory device), Random Access Memory (RAM) is a memory that uses transistors and capacitors. It has a simple structure in which memory cells are made up of multiple quantum dots (also called quantum dots). (Static Random Access Memory) and other storage devices. Since the number of semiconductor elements required to configure a memory cell is small, the memory capacity per unit area is This can increase the capacity and reduce costs.

[0003] Although DRAM has the advantage of being larger in capacity than other memory devices, it is becoming increasingly difficult to increase the chip size. In order to increase the density of LSIs while keeping the size of the LSIs small, the number of LSIs per unit area must be increased, just like other memory devices. To achieve this, the area of ​​the memory cell needs to be reduced. However, when the capacitance value becomes smaller due to the reduction in the area of ​​the capacitive element, each digital value Because the difference in charge between the two cells becomes smaller, the frequency of refresh operations must be increased. Therefore, when increasing the memory capacity per unit area of ​​DRAM, It is necessary to reduce the area of ​​the memory cell while maintaining a certain capacitance value in the capacitive element. There is.

[0004] In the following Patent Document 1, a transistor of a different conductivity type is provided in a first memory cell and a second memory cell. By using a resistor, the bit line and word line are shared, reducing the area of ​​the memory cell. The RAM configuration is disclosed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 7-312392 Summary of the Invention [Problem to be solved by the invention]

[0006] The DRAM described in Patent Document 1 requires the use of transistors of different conductivity types. Therefore, the number of manufacturing steps is increased compared to DRAM using single-conductivity transistors. In addition, transistors of different conductivity types have different on-currents, threshold voltages, etc. It is difficult to make the transistor characteristics uniform. This results in a decrease in data retention time and writing time. In this case, the voltage to be applied to the transistors tends to differ between memory cells. To achieve uniform transistor characteristics, process conditions and transistor layouts must be carefully considered. Therefore, it is necessary to precisely control the thickness, which makes the manufacturing process complicated.

[0007] In view of the above problems, the present invention provides a method for increasing the memory capacity per unit area without complicating the process. Another object of the present invention is to propose a storage device capable of increasing the capacity. By increasing the storage capacity per unit area of ​​storage devices without complicating the process, A semiconductor device using a memory device that can be made small and highly functional while keeping costs low. One of the objects of the present invention is to propose a semiconductor device. [Means for solving the problem]

[0008] Each memory cell of the DRAM has a switching element for controlling switching. A word line supplies a signal to the memory cell, and a data write / read circuit is provided for the memory cell. In addition to the bit line for reading and writing, a common potential is supplied to one of a pair of electrodes of the capacitor. The present inventors have proposed a method of providing the function of the capacitance line to the word line. By doing so, we thought it might be possible to reduce the number of wires in the cell array.

[0009] In view of this, in a memory device according to one embodiment of the present invention, a switching element is switched on and off using a word line. The switching control and the supply of potential to the capacitor element are performed. When focusing on the memory cell, the switching of the switching element in the memory cell is controlled. and a word line for supplying a potential to a capacitive element in the memory cell. That is, in the memory device according to one embodiment of the present invention, one word line are connected to the switching elements in one row of memory cells, and The recell has a structure that is connected to a capacitance element.

[0010] Specifically, a memory device according to one embodiment of the present invention includes a plurality of memory cells and a plurality of word lines. Each of the memory cells includes a switching element and a The word lines are connected to the memory cell, and the charge inflow, retention, and outflow are controlled by the word lines. Of these, one is connected to the switching element, and the other is connected to a part of the capacitance element. It is connected to one of the pair of electrodes.

[0011] In addition, in a memory device according to one embodiment of the present invention, a transistor used as the switching element is The transistor has a wider band gap than silicon and a lower intrinsic carrier density than silicon. The channel forming region may include a semiconductor such as , oxide semiconductors, silicon carbide, which have a band gap more than twice that of silicon, The transistors using the above semiconductors are similar to those using ordinary silicon or Compared to transistors made of semiconductors such as germanium, the off-state current is extremely low. Therefore, the transistor having the above structure can be used to circulate the charge flowing into the capacitor. By using it as a switching element to hold the charge, it is possible to prevent the charge from leaking from the capacitance element. It is possible to do so. Effect of the Invention

[0012] In the memory device according to one embodiment of the present invention, the word line is provided with a function as a capacitance line, The number of wirings in the cell array can be reduced. Since it is not necessary to change the polarity of the stator, the number of electrodes per unit area can be increased without complicating the process. It is possible to realize a storage device capable of increasing the storage capacity.

[0013] In addition, in one embodiment of the present invention, it is possible to reduce the number of layers per unit area of ​​a storage device without complicating the process. By increasing the memory capacity, it is possible to reduce the size and improve the functionality while keeping costs low. It is possible to realize a semiconductor device using the memory device. [Brief description of the drawings]

[0014] [Figure 1] FIG. 2 is a circuit diagram showing the configuration of a cell array. [Diagram 2] FIG. 2 is a diagram illustrating an operation of a memory cell. [Diagram 3]FIG. 2 is a diagram illustrating an operation of a memory cell. [Figure 4] 4 is a timing chart of a potential applied to a cell array. [Diagram 5] 3A and 3B are an enlarged top view and cross-sectional view of a part of a cell array. [Figure 6] 3A and 3B are an enlarged top view and cross-sectional view of a part of a cell array. [Figure 7] 3A and 3B are an enlarged top view and cross-sectional view of a part of a cell array. [Figure 8] 3A and 3B are an enlarged top view and cross-sectional view of a part of a cell array. [Figure 9] FIG. 2 is a circuit diagram showing the configuration of a cell array. [Figure 10] 3A and 3B are an enlarged top view and cross-sectional view of a part of a cell array. [Figure 11] 3A and 3B are an enlarged top view and cross-sectional view of a part of a cell array. [Figure 12] 1A to 1C are diagrams illustrating a method for manufacturing a memory device. [Figure 13] FIG. 1 is a block diagram showing the configuration of a storage device. [Figure 14] FIG. [Figure 15] 1A to 1C are diagrams illustrating a structure of an oxide semiconductor. [Figure 16] 1A to 1C are diagrams illustrating a structure of an oxide semiconductor. [Figure 17] 1A to 1C are diagrams illustrating a structure of an oxide semiconductor. [Figure 18] FIG. 13 is a graph for explaining the gate voltage dependence of mobility obtained by calculation. [Figure 19] FIG. 1 is a graph showing the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 20] FIG. 1 is a graph showing the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 21] FIG. 1 is a graph showing the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 22] 1A and 1B are diagrams illustrating cross-sectional structures of transistors used in calculation. [Diagram 23] 13 is a graph showing characteristics of a transistor including an oxide semiconductor film. [Figure 24] FIG. 13 shows Vg-Id characteristics of the transistor of Sample 1 after a BT test. [Diagram 25] FIG. 13 shows Vg-Id characteristics of a transistor of Sample 2 after a BT test. [Figure 26] FIG. 1 shows the Vg dependence of Id and mobility. [Figure 27] 1A and 1B are graphs showing the relationship between the substrate temperature and the threshold voltage, and the relationship between the substrate temperature and the mobility. [Figure 28] FIG. 2 shows XRD spectra of sample A and sample B. [Figure 29] 13 is a graph showing the relationship between the off-state current of a transistor and the substrate temperature during measurement. [Diagram 30] 1A to 1C are diagrams illustrating a structure of a transistor. [Diagram 31] 1A to 1C are diagrams illustrating a structure of a transistor. [Diagram 32] Electronic devices illustration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and the embodiments and aspects of the present invention may be modified without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. However, the present invention should not be construed as being limited to the description of the following embodiment.

[0016] In addition, the microprocessor, image processing circuit, DSP (Digital Signal Processor) processor), integrated circuits such as microcontrollers, RF tags, memory cards Various semiconductor devices that can use the storage device, such as storage media, semiconductor display devices, etc., The semiconductor display device is included in the scope of the present invention. Light-emitting devices with light-emitting elements such as LEDs in each pixel, electronic paper, DMDs (Di digital Micromirror Device), PDP (Plasma Dis) play panel), FED (Field Emission Display), etc. and other semiconductor display devices having circuit elements using semiconductor films in their driver circuits. Included in the category.

[0017] (Embodiment 1) FIG. 1 is a circuit diagram showing an example of a configuration of a cell array 100 of a memory device according to one embodiment of the present invention. The cell array 100 shown in FIG. 01, a plurality of word lines WL, and a plurality of bit lines BL. The signal from the driving circuit is , are supplied to each memory cell 101 via a plurality of word lines WL and a plurality of bit lines BL.

[0018] The number of word lines WL and bit lines BL is determined by the number and arrangement of memory cells 101. The cell array 100 shown in FIG. 1 has x rows and y columns (x and y are both natural numbers) of memory cells. The optical fiber 101 has word lines WL1 to WLy and bit lines BL1 to BLx.

[0019] Each memory cell 101 has a transistor 102 that functions as a switching element. The memory cell 101 may include a transistor, a die, and a capacitor element 103 as necessary. The semiconductor device may further include circuit elements such as an electrode, a resistive element, a capacitive element, and an inductor. The switching element using the transistor 102 is a switching element that controls the flow of charge to the capacitor 103, The charge amount stored in the capacitor 103 is controlled to be different from that stored in the capacitor 103. The digital value of the stored data can be identified.

[0020] The transistor 102 functioning as a switching element has a gate electrode and a A semiconductor film that functions as a gate electrode, a gate insulating film that is located between the gate electrode and the semiconductor film, and a gate insulating film that is connected to the semiconductor film. A gate electrode of the transistor 102, and a source electrode and a drain electrode connected to the gate electrode of the transistor 102. The operation of the memory device can be controlled by applying a potential to the source and drain electrodes. .

[0021] Note that the semiconductor film of the transistor 102 is formed using a wide-gap semiconductor such as an oxide semiconductor. Silicon, germanium, which may be amorphous, microcrystalline, polycrystalline or single crystalline, may be used. or silicon germanium, or single crystal silicon carbide, or other semiconductors. For example, when silicon is used for the semiconductor film, a silicon single crystal semiconductor substrate, SO Silicon thin films produced by the I method and vapor phase epitaxy are The semiconductor film can be used.

[0022] A semiconductor with a wider band gap than silicon semiconductors and a lower intrinsic carrier density than silicon. Examples of conductors include oxide semiconductors, silicon carbide (SiC), gallium nitride (Ga Examples of oxide semiconductors include compound semiconductors such as silicon carbide and gallium nitride. Unlike compound semiconductors such as cerium, they are produced by sputtering or wet methods (printing methods, etc.). The advantage of this method is that it is easy to manufacture and has excellent mass productivity. The process temperature for GaN is about 1500°C, and that for gallium nitride is about 1100°C. The deposition of oxide semiconductors can be performed at room temperature. It is possible to form a film on the substrate, and it is resistant to heat treatment at high temperatures of 1500℃ to 2000℃. A semiconductor element made of an oxide semiconductor is stacked on an integrated circuit made of a non-functional semiconductor. It is also possible to accommodate larger substrates. Compared to silicon or gallium nitride, oxide semiconductors have the advantage of being more easily mass-produced. In addition, crystalline oxide semiconductors are used to improve the performance (e.g., mobility) of transistors. Even when trying to obtain a conductor, it is easy to obtain a crystalline oxide by heat treatment at 250 to 800 degrees Celsius. A compound semiconductor can be obtained.

[0023] In addition, impurities such as moisture and hydrogen, which act as electron donors, are reduced, and oxygen is eliminated. By reducing defects, a highly purified oxide semiconductor (Purified Oxide Semiconductor) Semiconductors are either i-type (intrinsic semiconductors) or very close to i-type. Therefore, the transistor including the oxide semiconductor has the characteristic of having an extremely low off-state current. Specifically, the highly purified oxide semiconductor was analyzed by secondary ion mass spectrometry (SIMS: Measurement of hydrogen concentration by condary ion mass spectrometry The value is 5 x 10 19 / cm 3 Less than or equal to 5×10 18 / cm 3 The following is more preferable: is 5 x 10 17 / cm 3 In addition, the oxide semiconductor that can be measured by the Hall effect measurement is The carrier density of the membrane is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 Not yet More preferably, 1×10 11 / cm 3 In addition, the band gap of the oxide semiconductor is The gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. The concentration of impurities such as oxygen or hydrogen is sufficiently reduced, and oxygen vacancies are also reduced, resulting in high The off-state current of a transistor can be reduced by using a purified oxide semiconductor film. can be done.

[0024] Here, an analysis of the hydrogen concentration in an oxide semiconductor film will be described. The measurement is performed using SIMS. SIMS, by its very nature, is unable to measure the area near the sample surface or the area where a film made of a different material is formed. It is known that it is difficult to obtain accurate data on the vicinity of the lamination interface with the When analyzing the distribution of hydrogen concentration in the thickness direction of a film by SIMS, The average value in the range where there are no extreme fluctuations and where a nearly constant value is obtained is used as the hydrogen concentration. Due to the influence of the hydrogen concentration in the film, it may not be possible to find a region where a nearly constant value is obtained. In this case, the maximum or minimum value of the hydrogen concentration in the region where the film exists is determined as the hydrogen concentration in the film. The hydrogen concentration is adopted as the maximum value in the region where the film exists. If there is no peak or a valley-shaped peak with a minimum value, the value at the inflection point is taken as the hydrogen concentration. To hire.

[0025] Specifically, the off-state current of a transistor using a highly purified oxide semiconductor film as an active layer The low value of can be proved by various experiments. For example, when the channel width is 1×10 6 μm Even if the channel length of the device is 10 μm, the voltage between the source and drain electrodes (drain When the on-state voltage is in the range of 1V to 10V, the off-state current is Below the measurement limit, i.e. 1×10 -13 In this case, the characteristic of A or less can be obtained. The off-current density, which is the off-current divided by the channel width of the transistor, is 100 It can be seen that the capacitance is less than zA / μm. A circuit that controls the charge flowing into or out of a capacitor using the transistor is used. The off-state current density was measured. A semiconductor film is used for the channel formation region, and the charge amount per unit time of the capacitance element is calculated. The off-state current density of the transistor was measured. As a result, the source and drain electrodes of the transistor When the voltage between the gate electrodes is 3 V, an even lower off-state current density of several tens of yA / μm is obtained. Therefore, it was found that the transistor using the highly purified oxide semiconductor film as the active layer The off-state current of the transistor is significantly lower than that of a transistor using crystalline silicon. stomach.

[0026] Unless otherwise specified, in this specification, the off-state current is In this case, the drain electrode is set at a higher potential than the source and gate electrodes. When the potential of the gate electrode is 0 or less with respect to the potential of the source electrode, The off-state current in this specification refers to the current that flows between the drain electrode and the p In a channel type transistor, the drain electrode is lower than the source electrode and the gate electrode. When the potential of the gate electrode is set to a reference potential, the potential of the gate electrode is less than 0. This refers to the current that flows between the source and drain electrodes when the potential is above the threshold.

[0027] The oxide semiconductor used is at least indium (In) or zinc (Zn It is particularly preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors using In addition to these, it is preferable to have gallium (Ga). It is preferable to use hafnium (Hf) as a stabilizer. It is preferable that the stabilizer contains aluminum (Al). is preferred.

[0028] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0029] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. There can be.

[0030] In this case, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than a and Zn may be present.

[0031] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) In addition, M may be selected from Ga, Fe, Mn, and Co. It indicates one or more metal elements. In addition, as an oxide semiconductor, In3SnO5 (ZnO) n A material expressed as (n>0, and n is an integer) may be used.

[0032] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Alternatively, In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In--Sn--Zn-based oxide having an atomic ratio or an oxide having a composition close to that.

[0033] However, the present invention is not limited to these, and can be applied to any semiconductor characteristics (mobility, threshold, variation, etc.) required. In order to obtain the required semiconductor characteristics, the appropriate composition should be used. Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to make the above appropriate.

[0034] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. Therefore, in the case of In-Ga-Zn oxides, the mobility can be increased by reducing the defect density in the bulk. It can be done.

[0035] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with the atomic ratio of In:Ga:Zn=A:B:C (A+B+C = 1), a, b, and c are in the vicinity of the oxide composition (a-A). 2 +(b-B) 2 + (c-C) 2 ≦r 2 The above condition is satisfied, and r can be set to, for example, 0.05. The same is true for compounds.

[0036] The oxide semiconductor may be single-crystalline or non-single-crystalline. In the latter case, it may be amorphous or polycrystalline. In addition, the structure may include a portion having crystallinity in the amorphous state, or a non-amorphous structure. That's fine too.

[0037] Since it is relatively easy to obtain a flat surface for an amorphous oxide semiconductor, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high quality. Therefore, high mobility can be obtained.

[0038] In addition, in a crystalline oxide semiconductor, defects in the bulk can be reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility equal to or higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form the surface of the film on the substrate with a thickness of 0.1 nm or less.

[0039] In addition, Ra is the center line average roughness defined in JIS B0601 that can be applied to the surface. This is a three-dimensional extension of the method, which is based on the principle of averaging the absolute value of the deviation from the reference surface to the specified surface. This can be expressed as the "value obtained by dividing the total number of bits by the number of bits" and is defined by the following Equation 1.

[0040]

number

[0041] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y1 )(x2,y2) is the rectangular area bounded by the four points, and Z0 is It refers to the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). It can be evaluated using a microscope.

[0042] Also, the c-axis is oriented and has a triangular or hexagonal shape when viewed from the ab-plane, surface or interface direction. When viewed from the direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. The a-axis and b-axis are arranged in layers, and the orientation of the a-axis and b-axis is different on the ab plane (centered on the c-axis). CAAC: C-Axis Aligned Crystal This article describes oxides containing .

[0043] In a broad sense, oxides containing CAAC are non-single crystals that are not crystalline when viewed from a direction perpendicular to the ab plane. The atomic arrangement is a triangle, a hexagon, an equilateral triangle, or an equilateral hexagon, and is perpendicular to the c-axis direction. From the viewpoint of the direction, it is an acid containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to a monster.

[0044] CAAC is not a single crystal, but it is not composed of only amorphous matter. AC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is not clearly defined. Sometimes it is not possible to determine with certainty.

[0045] When oxygen is contained in CAAC, a part of the oxygen may be replaced with nitrogen. The c-axes of the individual crystals that make up the CAAC are aligned in a certain direction (e.g., the substrate surface supporting the CAAC, C The CAAC may be aligned in a direction perpendicular to the surface of the AAC. The normal to the ab plane of the crystal part of the CAAC is in a certain direction (for example, the substrate plane supporting the CAAC, The direction may be perpendicular to the surface of the substrate.

[0046] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Depending on the composition, the material may or may not be transparent to visible light. Sometimes they are not there.

[0047] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from the direction, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, When the metal atoms are mixed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Crystals may also be mentioned.

[0048] An example of a crystal structure contained in CAAC will be described in detail with reference to FIGS. 15 to 17, the upward direction is the c-axis direction, and the The plane that is the boundary between the two is called the ab plane. The upper half and the lower half.

[0049] In Figure 15(A), one hexacoordinate In atom and six tetracoordinate oxygen atoms (hereafter referred to as 4) adjacent to the In atom are shown. The structure shown here has one metal atom and one nearby oxygen atom. The structure shown in Fig. 15(A) is an octahedral structure, but it is easy to For simplicity, the structure is shown in a plan view. There are three O atoms in each group that are 4-coordinated. The small group shown in Figure 15(A) has a zero charge.

[0050] In Figure 15(B), one pentagonal Ga atom and three trigonal oxygen atoms (hereafter referred to as 3) adjacent to the Ga atom are shown. The structure shows a structure having a 4-coordinated O atom and two 4-coordinated O atoms adjacent to Ga. The 3-coordinated O atom is Both exist on the ab plane. There are four of them, one each in the upper and lower halves of Figure 15(B). In addition, since In also has a 5-coordination, the structure shown in Figure 15(B) can be formed. The small group shown in FIG. 15(B) has a charge of 0.

[0051] FIG. 15(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 15(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. Or, in the upper half of Fig. 15(C), there are three 4-coordinate Os, and in the lower half, there is one There may be four-coordinated O. The small group shown in Figure 15(C) has a zero charge.

[0052] FIG. 15(D) shows a structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. The upper half of Figure 15(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 15(D) has a charge of +1.

[0053] Figure 15(E) shows a small group containing two Zn atoms. The upper half of Figure 15(E) shows one Zn atom. The small group shown in Figure 15(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0054] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a These are called large groups (also called unit cells).

[0055] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the 6-coordinate In have three adjacent In atoms downward, and the lower half Each of the three O atoms has three neighboring In atoms in the upward direction. One O atom in the upper half of the five-coordinate Ga atom has one adjacent Ga in the downward direction, and one O in the lower half has one adjacent Ga in the upward direction. One O atom in the upper half of the 4-coordinated Zn has one neighboring Zn atom downward, and the three O atoms in the lower half Each O has three neighboring Zn atoms in the upward direction. Thus, the four-coordinated structure of the metal atom in the upward direction The number of O atoms is equal to the number of adjacent metal atoms below the O atoms. The number of 4-coordinated O atoms is equal to the number of adjacent metal atoms above the O atoms. Since O is 4-coordinated, Therefore, the sum of the number of adjacent metal atoms below and the number of adjacent metal atoms above is 4. Therefore, the number of 4-coordinated O atoms above a metal atom and the number of 4-coordinated O atoms below another metal atom are When the sum of the number of O and metal atoms is 4, two small groups containing metal atoms can bond together. For example, a hexacoordinated metal atom (In or Sn) can be bonded to the lower half of the tetracoordinated O atom. In this case, since there are three tetracoordinated O atoms, a pentagonal coordinated metal atom (Ga or In) or It will bond to one of the four-coordinate metal atoms (Zn).

[0056] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinate oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0057] Figure 16(A) shows a model diagram of the middle group that constitutes the layered structure of In-Sn-Zn oxide. FIG. 16B shows a large group consisting of three medium groups. FIG. 16C shows the atomic arrangement when the layer structure of FIG. 16B is observed from the c-axis direction.

[0058] In FIG. 16(A), for simplicity, the tricoordinate O is omitted, and only the number of the tetracoordinate O is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate O atoms, as shown in the circle. Similarly, in FIG. 16(A), the upper and lower halves of In are Each has one 4-coordinate O atom, which is indicated by the circle 1. Similarly, in Figure 16 In (A), there is one tetracoordinate O in the lower half and three tetracoordinate O in the upper half. Zn with one tetrahedral O atom in the upper half and three tetrahedral O atoms in the lower half. This shows that:

[0059] In FIG. 16(A), the middle group, which is made up of a layer structure of In-Sn-Zn oxide, is Sn has three tetrahedral O atoms in the upper half and one tetrahedral O atom in the lower half. It bonds to In in the upper and lower halves, and the In has three tetracoordinate O in the upper half. It bonds to Zn, and three tetracoordinate O atoms are bonded to the upper half of the Zn via one tetracoordinate O atom in the lower half of the Zn. The In is bonded to a Zn atom with one tetracoordinated O in the upper half. It bonds to a small group of two via a tetracoordinate O in the lower half of this small group. The structure is such that three tetracoordinate O atoms are bonded to the Sn atoms in the upper and lower halves. Multiple groups combine to form larger groups.

[0060] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6, respectively. 67, -0.5. For example, In (6 or 5 coordinates), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, a layer structure containing Sn is formed. To do this, a charge of -1 is required to cancel out the charge of +1. The structure shown in Figure 1 shows a structure that can take a charge of -1. 5(E), a small group containing two Zn atoms. For example, Sn-containing If there is one small group with two Zn atoms per small group, the charges are cancelled out. Therefore, the total charge of the layer structure can be set to zero.

[0061] Specifically, the large group shown in FIG. 16(B) is repeated to form the In-Sn-Zn The resulting In-S system oxide crystals (In2SnZn3O8) can be obtained. The layer structure of n-Zn oxide is In2SnZn2O7(ZnO) m (m is 0 or a natural number It can be expressed by the formula:

[0062] In addition, there are oxides of four-component metals, such as In-Sn-Ga-Zn oxides and trimetallic oxides. In-Ga-Zn oxide (also written as IGZO), which is an oxide of the elemental metal, In- Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-A l-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-C e-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm -Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb- Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Z n-type oxides, In-Tm-Zn-type oxides, In-Yb-Zn-type oxides, In-Lu-Zn In-Zn oxides, Sn-Zn oxides, and Al oxides are binary metal oxides. -Zn-based oxides, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, and I The same applies when n-Ga-based oxides are used.

[0063] For example, in Figure 17(A), a middle group model consisting of a layered structure of In-Ga-Zn oxide is shown. A diagram of the data is shown.

[0064] In FIG. 17(A), the middle group, which is made up of a layer structure of In-Ga-Zn oxide, is In the upper half and lower half, there are three tetracoordinate O atoms, and in the lower half, there is one tetracoordinate O atom. It bonds to the Zn in the molecule, and the tetracoordinate O atom is connected to the Zn via the three tetracoordinate O atoms in the lower half of the Zn. Each of them bonds to Ga in the upper and lower halves, and one 4-coordinate O in the lower half of the Ga is The structure is such that three tetracoordinate O atoms are bonded to the In atoms in the upper and lower halves via the Several of these medium groups combine to form large groups.

[0065] Figure 17(B) shows a large group consisting of three medium groups. 17(B) shows the atomic arrangement when the layer structure of FIG. 17(B) is observed from the c-axis direction.

[0066] Here, the charges of In (6 or 5 coordinates), Zn (4 coordinates), and Ga (5 coordinates) are Since the valence numbers are +3, +2, and +3, respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge will always be zero.

[0067] The middle group, which is made up of a layer structure of In-Ga-Zn oxide, is shown in FIG. The combination of middle groups with different arrangements of In, Ga, and Zn is not limited to the same middle group. Large groups are also possible.

[0068] The source terminal and the drain terminal of the transistor are connected to each other. The name changes depending on the potential applied to the electrodes. Generally, n-channel In a transistor, the electrode to which a low potential is applied is called the source terminal, and the electrode to which a high potential is applied is called the The electrode that is connected to the drain terminal is called the drain terminal. The electrode to which the high potential is applied is called the drain terminal, and the electrode to which the high potential is applied is called the source terminal. In the following, either the source terminal or the drain terminal is referred to as the first terminal, and the other is referred to as the second terminal. The connection relationship between the transistor 102 and the capacitor 103 in the memory cell 101 will be described. .

[0069] The source terminal of a transistor is a source region that is a part of the active layer, or a Similarly, the drain terminal of a transistor refers to the connected source electrode of the active layer. The term "drain electrode" refers to a drain region that is a part of the active layer, or a drain electrode that is connected to the active layer.

[0070] In this specification, the term "connection" means electrical connection, and the current, voltage, or potential is This corresponds to a state where the signal can be supplied or transmitted. Therefore, the connected state is a direct connection. does not necessarily refer to the state in which a current, voltage or potential is available or transferable. To make it possible to transmit signals, the devices must be wired, conductive, resistors, diodes, transistors, etc. This also includes situations where the connection is indirectly made via another means.

[0071] In addition, even if components that are independent on the circuit diagram are connected, For example, when a part of a wiring functions as an electrode, one conductive film is a In this specification, the term "connection" refers to such a single conductive film. However, cases where the functions of multiple components are combined are also included in this category.

[0072] In the memory cell 101 shown in FIG. 1, the gate electrode of the transistor 102 is connected to the word line W The first terminal of the transistor 102 is connected to one of the bit lines BL. The first terminal is connected to one electrode of the capacitor 103. The other electrode of the capacitance element 103 is connected to another word line WL different from one of the word lines. are connected to one another.

[0073] Specifically, in the cell array 100 shown in FIG. 1, in the memory cell 101 in the first row and first column, The gate electrode of the transistor 102 is connected to the word line WL1. The first terminal of the capacitor 102 is connected to the bit line BL1, and the second terminal of the capacitor 103 is connected to one of the bit lines BL1 and BL2. The other electrode of the capacitor 103 is connected to the word line WL2. is connected.

[0074] In the cell array 100 shown in FIG. 1, the capacitance element The other electrode of the terminal 103 is connected to a capacitance line CL.

[0075] In the cell array shown in FIG. 1, any memory cell 101 is connected to two adjacent word lines. However, one aspect of the present invention is not limited to this configuration. The two word lines connected to any one memory cell 101 may be separated from each other and not adjacent to each other. stomach.

[0076] In addition, in FIG. 1, the memory cell 101 includes a transistor 10 functioning as a switching element. 2, the present invention is not limited to this configuration. In the embodiment, at least one transistor that functions as a switching element is provided in each memory cell. The number of the transistors may be more than one. In the case where the switching element is composed of a plurality of transistors, The transistors may be connected in parallel, in series, or in a combination of series and parallel. may be connected in combination.

[0077] In this specification, the state in which transistors are connected in series refers to, for example, a first Only one of the first terminal and the second terminal of the first transistor is connected to the first terminal of the second transistor. This means that the transistor is connected to only one of the terminals. A state in which transistors are connected in parallel is when the first terminal of a first transistor is connected to the a second terminal of the first transistor connected to a first terminal of the second transistor; It means that it is connected to a child.

[0078] Next, the cell array 100 shown in FIG. 1 will be used as an example to describe the structure of a memory device according to one embodiment of the present invention. The operation of the cell array shown in FIG. A write period Ta, a data retention period Ts, and a read period Ts. The potentials applied to the cell array 100 during each of the above periods are different. A timing chart is shown as an example.

[0079] In FIG. 4, the memory cell 101 in the i-th row and the j-th column and the memory cell 101 in the i-th row and the j+1-th column are The memory cell 101 in the i+1th row and jth column and the memory cell 101 in the i+1th row and j+1th column The following four examples are given for writing, storing, and reading data. The memory cell 101 is assumed to be included in the memory cell 101 located in x rows and y columns.

[0080] First, the operation of the cell array 100 in the write period Ta will be described. In FIG. 4, the memory cell 101 in the i-th row and the j-th column and the memory cell 102 in the i-th row and the j+1 The data is written to the memory cell 101 in the i+1th row and the jth column first. Data is written to the memory cell 101 and the memory cell 101 in the (i+1)th row and the (j+1)th column. This example illustrates a case in which:

[0081] First, the word line WLi connected to the memory cell 101 in the i-th row to be written is selected. Specifically, in FIG. 4, a high-level potential VH is applied to the word line WLi. The ground potential GND is applied to the word lines other than the word line WLi including WLi+1. Then, only the transistor 102 whose gate electrode is connected to the word line WLi is selectively turned on. It becomes.

[0082] During the period when the word line WLi is selected, the bit lines BLj and BL A potential of a signal including data is applied to bit line BLj, bit line BLj+1. The level of the potential applied to the bit line B naturally differs depending on the data content. A high-level potential VDD is applied to Lj, and a ground potential GND is applied to the bit line BLj+1. The potential applied to the bit lines BLj and BLj+1 is The potential is applied to one of the electrodes of the capacitor 103 via the transistor 102 .

[0083] The potential VH is equal to or higher than the potential VDD. The potential difference of the potential VDD is equal to or greater than the threshold voltage of the transistor 102. do.

[0084] FIG. 2A shows each memory cell when data is written to the memory cell 101 in the i-th row. 2A, the second terminal of the transistor 102 is connected to the second terminal of the transistor 101. A node to which one of the electrodes of the capacitor 103 is connected is denoted as a node FG. According to the above potential, the potential of the node FG becomes the potential V The potential becomes DD, and the potential becomes ground potential GND in the memory cell 101 in the i-th row and j+1-th column. The amount of charge flowing into the capacitor 103 is controlled in accordance with the potential of the node FG. Write data to the memory cell 101 in the jth column and the memory cell 101 in the ith row and j+1th column. will be carried out.

[0085] Next, the ground potential GND is applied to the word line WLi. The transistor 102 to which the output electrode is connected is turned off, and a charge is transferred to the capacitor 103. is retained.

[0086] When an oxide semiconductor is used for the semiconductor film of the transistor 102, the transistor 102 has the characteristic of having an extremely low off-state current. The charge is less likely to leak, and compared to when a semiconductor such as silicon is used for the transistor 102, , data can be retained for a long period of time.

[0087] Next, the word line WLi+ connected to the memory cell 101 in the (i+1)th row to be written Specifically, in FIG. 4, a high-level potential VH is applied to the word line WLi+1. The word lines other than the word line WLi+1 including the word line WLi are supplied with the ground potential GND. Therefore, the transistor 10 whose gate electrode is connected to the word line WLi+1 Only 2 is selectively turned on.

[0088] During the period when the word line WLi+1 is selected, the bit line BLj, A potential of a signal including data is applied to bit line BLj+1. The level of potential given to +1 will of course differ depending on the contents of the data. The line BLj is applied with a ground potential GND, and the bit line BLj+1 is applied with a high-level potential VDD. The potential applied to the bit lines BLj and BLj+1 is ON. The voltage Vcc is applied to one of the electrodes of the capacitor 103 through the transistor 102. (B) shows each memory cell when writing data to the memory cell 101 in the i+1th row. 2B, the operation of the node FG The potential of the memory cell 101 in the (i+1)th row and the (j)th column is the ground potential GND, The potential of the memory cell 101 in the j+1th column is VDD. Therefore, by controlling the amount of charge flowing into the capacitance element 103, the memory cell in the (i+1)th row and the jth column Then, data is written to the memory cell 101 in the (i+1)th row and the (j+1)th column.

[0089] In the cell array 100 shown in FIG. 1, the word line WLi+1 corresponds to the memory cell in the i+1th row. 101, and is also connected to the memory cell 101 in the i-th row. WLi+1 is connected to the other electrode of the capacitor 103 in the memory cell 101 in the i-th row. The other electrode of the capacitor 103 is connected to a potential Vpp during a period when the word line WLi is selected. In the example shown in FIG. 2B, the word line WLi+ A potential VH is applied during the period in which the capacitance element 103 is selected. Since the potential difference between the pair of electrodes is maintained by the law of conservation of charge, the word line WLi+1 is selected. During the period in which the potential difference between the potential VH and the ground potential GND is As a result, the voltage Vcc in the memory cell 101 in the i-th row and j-th column is The node FG is at a potential VDD+VH, and the memory cell 101 in the i-th row and j+1-th column The node FG is at the potential VH.

[0090] Next, the ground potential GND is applied to the word line WLi+1. The transistor 102 having a gate electrode connected to the capacitor 103 is turned off. Note that the potential difference between the pair of electrodes of the capacitor 103 satisfies the law of conservation of charge. Therefore, when the ground potential GND is applied to the word line WLi+1, the i-th row j The node FG in the memory cell 101 in the i-th row and j+1-th column is at the potential VDD. A node FG in the memory cell 101 is at the ground potential GND.

[0091] In order to prevent erroneous data from being written to the memory cell 101, each word line WL After the selection of the bit line BL is completed, it is desirable to stop the supply of the potential including the data to the bit line BL. I wish.

[0092] Next, the operation of the cell array 100 during the data retention period Ts will be described.

[0093] During the hold period Ts, all the word lines WL are supplied with a voltage at a level that turns off the transistors 102. A potential of the memory cell in the i-th row, specifically, a ground potential GND, is applied. When data is stored in the memory cell 101 in the i+1th row and the memory cell 1 3A, the charge flowing into the capacitor 103 is During the time that it is being held, the data is retained.

[0094] Next, the operation of the cell array 100 in the data read period Tr will be described.

[0095] First, during the read period Tr, the bit line B connected to the memory cell 101 to be read A high-level potential VR is applied to the memory cell 10 in the j-th column in FIG. 1, and the bit line BLj connected to the memory cell 101 in the j+1th column. A high-level potential VR is applied to the potentials VDD and BLj+1. The potential is the same as or lower than the potential VDD and higher than the ground potential GND. After the potential VR is applied, the bit line BLj and the bit line BLj+1 are both The system is in a loading state.

[0096] Next, a word line WLi connected to the memory cell 101 in the i-th row from which data is to be read is selected. Specifically, in FIG. 4, a high-level potential VH is applied to the word line WLi, and the word The other word lines, including the line WLi+1, are supplied with the ground potential GND. Only the transistor 102 having a gate electrode connected to the gate line WLi is selectively turned on. .

[0097] When the transistor 102 is turned on, the charge held in the capacitor 103 is read out. The charge flows to the bit line BL where the data is read, or the charge flows from the bit line BL where the data is read. The charge flows into the capacitance element 103. The above operation is determined by the potential of the node FG during the hold period. .

[0098] FIG. 3B shows the state of each memory cell 101 when data is read from the memory cell 101 in the i-th row. 4. Specifically, in the case of the timing chart shown in FIG. During the retention period, the node FG in the memory cell 101 in the i-th row and j-th column is at the potential VDD. Therefore, as shown in FIG. 3B, the transistor 102 is turned on during the read period. Then, a current flows from the capacitance element 103 in the memory cell 101 in the i-th row and j-th column to the bit line BLj. Since the charge flows out, the potential of the bit line BLj rises to a potential VR+α. During the retention period, the node FG in the memory cell 101 in the i-th row and j+1-th column is at the ground potential GND Therefore, when the transistor 102 is turned on during the readout period, the i-th row j+ A charge flows from the bit line BLj+1 to the capacitance element 103 in the memory cell 101 in the first column. As a result, the potential of the bit line BLj+1 drops to the potential VR-β.

[0099] Therefore, the potentials of the bit lines BLj and BLj+1 are the same as those of the memory cell 101 in the i-th row and j-th column and the A height according to the amount of charge held in the capacitance element 103 of the memory cell 101 in the j+1th column Then, by reading the difference in the amount of charge from the potential, the memory in the i-th row and j-th column is Data can be read from cell 101 and memory cell 101 in row i, column j+1. .

[0100] Next, the data from the memory cell 101 in the i-th row and j-th column and the memory cell 101 in the i-th row and j+1-th column are When the data readout is completed, the bit lines BLj and BLj+1 are set to high level again. After applying the potential VR to the bit line BLj, the bit line BLj+1 is set in a floating state. To be in a certain state.

[0101] Then, the word line WLi+1 connected to the memory cell 101 in the i-th row from which data is to be read is Specifically, in FIG. 4, a high-level potential VH is applied to the word line WLi+1. The other word lines, including the word line WLi, are supplied with the ground potential GND. Only the transistor 102 whose gate electrode is connected to the word line WLi+1 is selectively turned on. It becomes.

[0102] When the transistor 102 is turned on, the charge held in the capacitor 103 is read out. The charge flows to the bit line BL where the data is read, or the charge flows from the bit line BL where the data is read. The charge flows into the capacitance element 103. The above operation is determined by the potential of the node FG during the hold period. .

[0103] Specifically, in the case of the timing chart shown in FIG. 4, in the immediately preceding retention period, The node FG in the memory cell 101 is at the ground potential GND. When the transistor 102 is turned on, the memory cell 101 in the (i+1)th row and the jth column Since charges flow from the bit line BLj into the capacitance element 103 in the bit line BLj, the potential of the bit line BLj The potential becomes low and becomes VR-β. Also, in the previous hold period, the memory cell in the i+1th row and j+1th column The node FG in the memory cell 101 is at the potential VDD. When the transistor 102 is turned on, the memory cell 101 in the (i+1)th row and the (j+1)th column Since the charge flows from the capacitance element 103 to the bit line BLj+1, the charge of the bit line BLj+1 The potential increases and becomes VR+α.

[0104] Therefore, the potentials of the bit lines BLj and BLj+1 are the same as those of the memory cell 101 in the (i+1)th row and the jth column. Depending on the amount of charge stored in the capacitance element 103 of the memory cell 101 in the (i+1)th row and the (j+1)th column, Then, by reading the difference in the amount of charge from the potential, the height of the i+1th row j Data is read from the memory cell 101 in the i+1th row and the j+1th column. It can be put out.

[0105] A read circuit is connected to the tip of each bit line BL, and the output signal of the read circuit is contains the data read from the cell array 100.

[0106] In this embodiment, four adjacent memory cells 101 are taken as an example, and the write, hold, read, and Although the above description is directed to each operation of the read operation, one aspect of the present invention is not limited to this configuration. The above operation can be performed in the memory cell 101 at any address that has been set.

[0107] The capacitance line CL is maintained at a fixed potential such as the ground potential GND throughout the entire period. .

[0108] In a memory device according to one embodiment of the present invention, one word line is connected to memory cells in one row. and connected to the switching element, and connected to the capacitance element in the memory cells of another row. Therefore, the number of wirings connected to the memory cells is reduced. However, as described above, when a word line connected to a capacitance element is selected, The potential of the node FG increases as the potential of the word line increases. For example, Before writing the data, the high-level potential VDD has already been applied to the node FG. In this case, as shown in FIG. 2B, as the potential of the word line WLi+1 rises, In the i-th memory cell 101, the node FG becomes high at a potential VDD+VH. The transistor 102 in the jth column memory cell 101 has a source terminal and a drain terminal The potential difference between the transistors is large, so the off-state current is likely to be large. In order to significantly reduce the off-current of 02, a wide-gap semiconductor such as an oxide semiconductor is used. It is preferable to use a semiconductor film of the transistor 102. By dramatically reducing the current, the memory can be This can prevent the charge from leaking from the recell 101 and ensure the data retention period.

[0109] Next, an example of a specific structure of each memory cell 101 will be described.

[0110] FIG. 5A shows an enlarged top view of a part of the cell array 100 shown in FIG. 5(B) shows a cross-sectional view taken along dashed line A1-A2 in FIG. 5(A). In the example shown in FIG. 1, a transistor 102 and a capacitor 103 are formed on a substrate 104 having an insulating surface. It has been done.

[0111] The transistor 102 includes a semiconductor film 105 and a A conductive film 106 functioning as a source electrode or a drain electrode on the semiconductor film 105 and a conductive The insulating film 107, the semiconductor film 105, the conductive film 106, and the insulating film 108 on the conductive film 107, The gate electrode 104 is provided at a position overlapping the semiconductor film 105 with the film 108 sandwiched therebetween. The transistor 102 further includes a conductive film 109 covering the conductive film 109. The insulating film 110 may be included as a component. The transistor 102 has a top-gate, top-contact structure.

[0112] The capacitor 103 includes a conductive film 107 formed on a substrate 104 having an insulating surface, An insulating film 108 on the conductive film 107 and a conductive film 107 overlapping the conductive film 107 with the insulating film 108 sandwiched therebetween The conductive film 107, the insulating film 108, and the conductive film 111 overlap each other. functions as the capacitor 103 .

[0113] Note that the conductive film 106 functions as a source electrode or a drain electrode of the transistor 102. The conductive film 109 also functions as a bit line. The conductive film 107 functions as an electrode and also as a word line. The source electrode or drain electrode of the capacitor 102 is also an electrode of the capacitor 103. The conductive film 111 functions as an electrode of the capacitor 103 and also functions as a word line It also functions as a

[0114] FIG. 6A shows another example of an enlarged top view of a part of the cell array 100 shown in FIG. FIG. 6B is a cross-sectional view taken along the dashed line B1-B2 in FIG. 6A. In FIG. 6B, a transistor 102 and a capacitor 103 are formed on a substrate 104 having an insulating surface. 03 is formed.

[0115] The transistor 102 has a source electrode or a drain electrode on a substrate 104 having an insulating surface. The conductive film 116 and the conductive film 117 function as a drain electrode, and the conductive film 116 and the conductive film 1 A semiconductor film 115 on the substrate 17, a conductive film 116, a conductive film 117, and an insulating film on the semiconductor film 115 118 and a gate electrode 119 provided at a position overlapping the semiconductor film 115 with the insulating film 118 interposed therebetween. The transistor 102 further includes a conductive film 119 that functions as an electrode. The insulating film 120 covering the film 119 may be included as a component. The transistor 102 shown in B) has a top-gate, bottom-contact structure. .

[0116] The capacitor 103 includes a conductive film 117 formed on a substrate 104 having an insulating surface, An insulating film 118 on the conductive film 117 and a conductive film overlapping the conductive film 117 with the insulating film 118 sandwiched therebetween The conductive film 117, the insulating film 118, and the conductive film 121 overlap each other. functions as the capacitor 103 .

[0117] Note that the conductive film 116 functions as a source electrode or a drain electrode of the transistor 102. The conductive film 119 also functions as a bit line. The conductive film 117 functions as an electrode and also as a word line. The source electrode or drain electrode of the capacitor 102 is also an electrode of the capacitor 103. The conductive film 121 functions as an electrode of the capacitor 103 and also functions as a word line It also functions as a

[0118] FIG. 7A shows another example of an enlarged top view of a part of the cell array 100 shown in FIG. FIG. 7B is a cross-sectional view taken along the dashed line C1-C2 in FIG. In FIG. 7B, a transistor 102 and a capacitor 103 are formed on a substrate 104 having an insulating surface. 03 is formed.

[0119] The transistor 102 is provided on a substrate 104 having an insulating surface. The conductive film 129 is a conductive film having a function of insulating film 128 on the conductive film 129, and the insulating film 128 is sandwiched between the conductive film 129 and the insulating film 128. A semiconductor film 125 provided at a position overlapping the conductive film 129, and a source electrode on the semiconductor film 125. Alternatively, the conductive film 126 and the conductive film 127 function as a drain electrode. In addition, the transistor 102 includes a semiconductor film 125, a conductive film 126, and a conductive film 127. The insulating film 130 may be included as a component. The transistor 102 has a bottom-gate, top-contact structure.

[0120] In addition, in the transistor 102, the semiconductor film 125 is disposed between the conductive film 126 and the conductive film 127. The present invention relates to a channel etch structure in which the insulating film 130 is in contact with the exposed surface of the semiconductor substrate 110. The transistor 102 is not limited to the above structure. A channel protection film formed of an insulating film may be provided on the semiconductor film 125. By providing the protective film, when the conductive film 126 and the conductive film 127 are formed, etching is prevented. Damage such as film loss caused by plasma or etching agents during etching may occur in the channel of the semiconductor film 125. Therefore, the transistor 102 can be prevented from being applied to the region that will become the formation region. The reliability can be improved.

[0121] The capacitor 103 includes a conductive film 131 formed on a substrate 104 having an insulating surface, The insulating film 128 on the conductive film 131 and the conductive film 131 overlapping the insulating film 128 are sandwiched between the insulating film 128 and the conductive film 131. A portion where the conductive film 131, the insulating film 128, and the conductive film 127 overlap each other. functions as the capacitor 103 .

[0122] Note that the conductive film 126 functions as a source electrode or a drain electrode of the transistor 102. The conductive film 129 also functions as a bit line. The conductive film 127 functions as an electrode and also as a word line. The source electrode or drain electrode of the capacitor 102 is also an electrode of the capacitor 103. The conductive film 131 functions as an electrode of the capacitor 103 and also functions as a word line It also functions as a

[0123] FIG. 8A shows another example of an enlarged top view of a part of the cell array 100 shown in FIG. FIG. 8B is a cross-sectional view taken along the dashed line D1-D2 in FIG. In FIG. 8B, a transistor 102 and a capacitor 103 are formed on a substrate 104 having an insulating surface. 03 is formed.

[0124] The transistor 102 is provided on a substrate 104 having an insulating surface. A conductive film 139 that functions as a gate electrode, an insulating film 138 on the conductive film 139, and a source electrode on the insulating film 138. Alternatively, the conductive film 136 and the conductive film 137 function as drain electrodes, and the conductive film 136 and A conductive film 139 is provided over the conductive film 137 with an insulating film 138 interposed therebetween. The transistor 102 further includes a semiconductor film 135. The conductive film 136 and the conductive film 137 may include an insulating film 140 that covers the conductive film 136 and the conductive film 137 as a component. The transistor 102 shown in FIGS. 8A and 8B is a bottom-gate type It has a tact structure.

[0125] The capacitor 103 includes a conductive film 141 formed on a substrate 104 having an insulating surface, The insulating film 138 on the conductive film 141 and the conductive film 141 overlapping the conductive film 141 with the insulating film 138 sandwiched therebetween. A portion where the conductive film 141, the insulating film 138, and the conductive film 137 overlap each other. functions as the capacitor 103 .

[0126] Note that the conductive film 136 functions as a source electrode or a drain electrode of the transistor 102. The conductive film 139 also functions as a bit line. The conductive film 137 functions as an electrode and also as a word line. The source electrode or drain electrode of the capacitor 102 is also an electrode of the capacitor 103. The conductive film 141 functions as an electrode of the capacitor 103 and also functions as a word line It also functions as a

[0127] 5 to 8, the transistor 102 has a single-gate structure. However, the transistor 102 has a plurality of gate electrodes electrically connected to each other. Alternatively, the semiconductor device may have a multi-gate structure having a plurality of channel forming regions.

[0128] 5 to 8, the transistor 102 has a gate electrode that is located on only one side of the active layer. The transistor 102 has an active layer and a A back gate electrode may be provided on the opposite side of the gate electrode. The gate electrode may be in an electrically insulated floating state, or may be in a state where a potential is applied. In the latter case, the back gate electrode may have the same height as the gate electrode. A low potential may be applied, or a fixed potential such as ground may be applied. By controlling the level of the potential applied to the back gate electrode, the threshold voltage of the transistor 102 can be adjusted. The pressure can be controlled.

[0129] As described in this embodiment, in the memory device according to one embodiment of the present invention, By providing the function of a capacitance line, the number of wires in the cell array can be reduced. This makes it possible to increase the memory capacity per unit area without complicating the process. It is possible to realize a storage device capable of doing the above.

[0130] (Embodiment 2) In this embodiment, a storage device according to one embodiment of the present invention having a configuration different from that shown in FIG. The configuration of the filter array 200 will be described.

[0131] FIG. 9 is a circuit diagram showing an example of the configuration of the cell array 200 according to the present embodiment. In the cell array 200, a plurality of memory cells 201 are arranged in a first block 290 and a second block 291. The first block 290 is divided into four blocks 291. The first block 290 includes a memory cell 201. On the top of the memory cell 201, which is included in the second block 291, is provided. That is, The cell array 200 shown in this embodiment has a structure in which memory cells 201 are stacked. do.

[0132] In FIG. 9, the memory cells 201 are divided into a first block 290 and a second block 291. In the illustrated example, the signal processing unit 1 is divided into two blocks. However, one aspect of the present invention is that the signal processing unit 1 is divided into two blocks. The present invention is not limited to the above. A storage device according to one embodiment of the present invention has three or more stacked blocks. It's fine if it is.

[0133] Each of the blocks includes a plurality of memory cells 201 arranged in a matrix and a plurality of word lines. Each block has a line WL and a plurality of bit lines BL. The number of word lines WL and bit lines BL to be connected is determined by the number and arrangement of memory cells 201. The signal from the driving circuit is applied to a plurality of word lines WL and a plurality of bit lines B. L to each memory cell 201.

[0134] Specifically, in FIG. 9, a first block 290 has memory cells 201 arranged in x rows and y columns, In addition, in the case where the first word lines WLa1 to WLay and the first bit lines BLa1 to BLax are provided, In FIG. 9, the second block 291 is a block of memory cells 2 01, and the second word lines WLb1 to WLby and the second bit lines BLb1 to BL The example shows a case where bx is included.

[0135] Each memory cell 201 is connected to a switch in the same manner as in the cell array 100 shown in FIG. The semiconductor memory device includes a transistor 202 that functions as a switching element and a capacitor 203. The gate electrode of the transistor 202 is connected to one of the word lines WL. The first terminal of the transistor 202 is connected to one of the bit lines BL, and the second terminal is connected to a capacitance element 9. However, in the cell array 200 shown in FIG. The other electrode of element 203 is formed on one of the word lines of a different block or on a different layer. The capacitor is connected to one of the capacitance lines.

[0136] Specifically, in the cell array 200 shown in FIG. 9, for example, one of the second blocks 291 has In the memory cell 201 in the first column of the row, the gate electrode of the transistor 202 is connected to the second word line The first terminal of the transistor 202 is connected to the second bit line BLb1. 1, and the second terminal is connected to one electrode of the capacitance element 203. The other electrode of the capacitor 203 is connected to the first word line WLa1 of the first block 290. is connected to

[0137] In the cell array 200 shown in FIG. 9, a capacitance line CL is provided below the first block 290. Specifically, in the cell array 200 shown in FIG. In this example, the capacitance lines CL1 to CLy are provided below the first block 290. For example, in the memory cell 201 in the first row and first column of the first block 290, The gate electrode of the transistor 202 is connected to the first word line WLa1. The first terminal of the transistor 202 is connected to the first bit line BLa1, and the second terminal is The other electrode of the capacitor 203 is connected to , is connected to a capacitance line CL 1 provided below the first block 290 .

[0138] In the cell array 200 shown in FIG. 9, in addition to the capacitive element 203 included in any one block, The electrode of the block is connected to the word line or the capacitance line of the block below the block. However, one embodiment of the present invention is not limited to this configuration. The other electrode of the capacitor 203 is connected to a word line or a capacitor of a block above the block. It may be connected to a line.

[0139] The memory cell 201 may include transistors, diodes, resistors, capacitors, etc., as necessary. The transistor 202 may further include a circuit element such as a transistor, an inductor, etc. The switching element controls the inflow, retention, and outflow of charges in the capacitance element 203 . The digital representation of the stored data is determined by the difference in the amount of charge held in the capacitance element 203. The tal value can be identified.

[0140] Next, an example of a specific structure of each memory cell 201 will be described.

[0141] 10(A) to 10(C) are enlarged views of parts of each layer of the cell array 200 shown in FIG. An example of a top view is shown. The top views of the layers overlap at the dashed line E1-E2. FIG. 10(D) shows a cross-sectional view taken along dashed line E1-E2 in FIG. 10(A) to FIG. 10(C).

[0142] The first layer of the cell array 200 is formed on a substrate 204 having an insulating surface. In the first layer of the cell array 200, a conductive film 231 that functions as a capacitance line is formed. .

[0143] The second layer of the cell array 200 is formed on an insulating film 232 that covers the conductive film 231. In the second layer of the cell array 200, the transistors of the first block 290 are arranged. A transistor 202a and a transistor 202b are formed.

[0144] The transistor 202a includes a semiconductor film 205a and a semiconductor film 205b formed over the insulating film 232. The conductive film 206a functioning as a source electrode or a drain electrode and the conductive film 2005a are 7a, the insulating film 208 on the semiconductor film 205a, the conductive film 206a and the conductive film 207a, The insulating film 208 is sandwiched between the gate electrode 204 and the semiconductor film 205a. The transistor 202b has a semiconductor layer over an insulating film 232. A semiconductor film 205b and a conductive film functioning as a source electrode or a drain electrode on the semiconductor film 205b. The conductive film 206b and the conductive film 207b, the semiconductor film 205b, the conductive film 206b and the conductive film 20 7b and the insulating film 208 on the semiconductor film 205b. The transistor further includes a conductive film 209 that functions as a gate electrode. The transistor 202a and the transistor 202b form an insulating film 230 that covers the conductive film 209. The transistor 202a and the transistor 202b shown in FIG. The transistor 202b has a top-gate, top-contact structure.

[0145] The overlapping portion of the conductive film 207a, the insulating film 232, and the conductive film 231 forms a capacitance element. The conductive film 207b, the insulating film 232, and the conductive film 231 function as the insulating film 203a. The overlapping portion functions as the capacitive element 203b. is included in the first block 290.

[0146] The conductive film 206a serves as a source electrode or a drain electrode of the transistor 202a. The conductive film 206b serves as a source electrode or a drain electrode of the transistor 202b. The conductive film 209 functions as a first bit line. 2a and serves as the gate electrode of transistor 202b, and also serves as the first word line. The conductive film 207a functions as a source electrode or a drain electrode of the transistor 202a. As described above, the conductive layer 203 functions as an electrode of the capacitor 203a. The film 207b functions as a source electrode or a drain electrode of the transistor 202b. In addition, as described above, it functions as an electrode of the capacitor 203b.

[0147] The third layer of the cell array 200 is formed on the insulating film 240 that covers the insulating film 230. In the third layer of the cell array 200, the transistors of the second block 291 are arranged. A transistor 202c and a transistor 202d are formed.

[0148] The transistor 202c has a semiconductor film 205c and a semiconductor film 206c formed on the insulating film 240. The conductive film 206c functioning as a source electrode or a drain electrode and the conductive film 20 7c, the insulating film 241 on the semiconductor film 205c, the conductive film 206c, and the conductive film 207c, The insulating film 241 is sandwiched between the gate electrode 205 and the semiconductor film 205c. The transistor 202d has a semiconductor layer over the insulating film 240 and a conductive film 242 that functions as a gate insulating film. A semiconductor film 205d and a conductive film functioning as a source electrode or a drain electrode on the semiconductor film 205d. The conductive film 206d and the conductive film 207d, the semiconductor film 205d, the conductive film 206d and the conductive film 20 7d and the insulating film 241 is provided at a position overlapping the semiconductor film 205d with the insulating film 241 therebetween. The transistor has a conductive film 242 that functions as a gate electrode. The transistor 202c and the transistor 202d constitute an insulating film 243 that covers a conductive film 242. The transistor 202c shown in FIG. 10(A) and FIG. 10(D) may be included in the element. The transistor 202d is a top-type transistor, similar to the transistors 202a and 202b. It has a gate-type top contact structure.

[0149] The conductive film 207c, the insulating film 230, the insulating film 240, and the conductive film 209 are overlapped with each other. The conductive film 207d, the insulating film 230, and the The portion where the insulating film 240 and the conductive film 209 overlap functions as a capacitor 203d. The capacitance element 203 c and the capacitance element 203 d are included in the second block 291 .

[0150] The conductive film 206c and the conductive film 206d are the transistors 202c and 202 d and also functions as a second bit line. The conductive film 242 serves as gate electrodes of the transistor 202c and the transistor 202d. The conductive film 207c functions as a second word line. 2c as a source or drain electrode, and as described above, The conductive film 207d functions as an electrode of the transistor 202d. The gate electrode and drain electrode of the capacitor 203d are also provided as described above. It functions as a pole.

[0151] In FIG. 10, a parasitic capacitance formed between the first word line and the second word line is reduced. In order to separate the conductive film 209 and the conductive film 242, in other words, the substrate 204 The conductive film 209 and the conductive film 242 are arranged so as not to overlap in the vertical direction. However, one aspect of the present invention is not limited to this configuration, and in the vertical direction of the substrate 204, The film 209 and the conductive film 242 may be disposed so as to overlap each other.

[0152] In addition, in FIG. 10, the uppermost surface of the insulating film 232 is a region where the transistor 2 It is desirable that the transistors 202a and 202b are planarized to match the characteristics of the transistors 202a and 202b. Therefore, after forming the insulating film 232, the transistors 202a and 202b are formed. It is preferable to planarize the surface of the insulating film 232 by a CMP method or the like before forming the insulating film 232. Similarly, in FIG. 10, the top surface of insulating film 240 is a dielectric layer that is used to form transistors thereon. It is preferable that the transistor 202c is planarized to match the characteristics of the transistor 202d. Therefore, after forming the insulating film 240, the transistors 202c and 202d are Before forming the insulating film 240, it is preferable to flatten the surface of the insulating film 240 by a method such as CMP. .

[0153] Next, a specific example of each memory cell 201 in the case where the transistor structure is different from that shown in FIG. An example of the structure will be described.

[0154] 11(A) to 11(C) are enlarged views of parts of each layer of the cell array 200 shown in FIG. An example of a top view is shown. The top views of the layers overlap at the dashed line F1-F2. 11(D) shows a cross-sectional view taken along dashed line F1-F2 in FIG. 11(A) to FIG. 11(C).

[0155] The cell array 200 shown in FIG. 11(A) to FIG. 11(D) includes a transistor 202a, a transistor The structures of the transistors 202b, 202c, and 202d are different from those in FIG. do.

[0156] In the cell array 200 shown in FIG. 11(A) to FIG. 11(D), the first layer of the cell array 200 is The cell array 200 is formed on a substrate 204 having an insulating surface. A conductive film 236 that functions as a capacitance line is formed on the first insulating film 231 .

[0157] The second layer of the cell array 200 is formed on the insulating film 234 that covers the conductive film 236. In the second layer of the cell array 200, the transistors of the first block 290 are arranged. A transistor 202a and a transistor 202b are formed.

[0158] Specifically, the transistors 202a and 202b are provided with a source The conductive film 216a and the conductive film 217a functioning as an electrode or a drain electrode, and the conductive film 21 6b and conductive film 217b, conductive film 216a and conductive film 217a, conductive film 216b and conductive film The semiconductor film 215a and the semiconductor film 215b on the conductive film 217b, the conductive film 216a and the conductive film 217b are 17a, the conductive film 216b, the conductive film 217b, the semiconductor film 215a, and the semiconductor film 215b The insulating film 218 is sandwiched between the semiconductor film 215a and the semiconductor film 215b. A conductive film 219 that functions as a gate electrode is provided at a position corresponding to the gate electrode. The transistor 202a and the transistor 202b are formed by insulating film 235 covering the conductive film 219. In the cell array 200 shown in FIG. 11(A) to FIG. 11(D), The transistor 202a and the transistor 202b are top-gate bottom-contact It has a tetrahydrofuran structure.

[0159] 10, the conductive film 217a, the insulating film 234, and the conductive film 236 are The overlapping portion functions as a capacitor 203a. The portion where the conductive film 236 overlaps with the insulating film 204 functions as the capacitor 203b. 3a and the capacitive element 203b are included in a first block 290.

[0160] Specifically, the transistors 202c and 202d are provided over the insulating film 244 as follows: The conductive film 216c and the conductive film 217c function as a source electrode and a drain electrode, The conductive film 216d and the conductive film 217d, and the conductive film 216c and the conductive film 217c and the conductive film 216d The semiconductor film 215c on the conductive film 217d, the semiconductor film 215d, the conductive film 216c and the conductive The conductive film 217c, the conductive film 216d and the conductive film 217d, the semiconductor film 215c, and the semiconductor film 215 d, and the insulating film 245 is sandwiched between the semiconductor film 215c and the semiconductor film 215d. and a conductive film 246 which functions as a gate electrode and is provided in a position overlapping with the gate electrode. The transistors 202c and 202d are formed of an insulating film covering the conductive film 246. 247 may be included as a component. In 00, transistor 202c and transistor 202d are transistors 202a and Like the transistor 202b, it has a top-gate, bottom-contact structure.

[0161] 10, the conductive film 216c, the insulating film 235, and the insulating film 244 are The portion overlapping the conductive film 219 functions as a capacitor 203c. d, and the insulating film 235, the insulating film 244, and the conductive film 219 overlap each other, forming the capacitance element 20 The capacitance element 203c and the capacitance element 203d are in the second block 291. Included.

[0162] In FIG. 11, in order to reduce the parasitic capacitance formed between the first word line and the second word line, In order to separate the conductive film 219 and the conductive film 246, in other words, the vertical The conductive film 219 and the conductive film 246 are arranged so as not to overlap in the perpendicular direction. However, one embodiment of the present invention is not limited to this structure. The conductive film 219 and the conductive film 246 may be disposed so as to overlap each other.

[0163] In addition, in FIG. 11, the uppermost surface of the insulating film 234 is the surface of the transistor 2 It is desirable that the transistors 202a and 202b are planarized to match the characteristics of the transistors 202a and 202b. Therefore, after forming the insulating film 234, the transistors 202a and 202b are formed. It is preferable to planarize the surface of the insulating film 234 by a CMP method or the like before forming the insulating film 234. Similarly, in FIG. 11, the top surface of insulating film 244 is a dielectric layer that is used to form transistors thereon. It is preferable that the transistor 202c is planarized to match the characteristics of the transistor 202d. Therefore, after the insulating film 244 is formed, the transistors 202c and 202d are Before forming the insulating film 244, it is preferable to flatten the surface of the insulating film 244 by a method such as CMP. .

[0164] In addition, in FIG. 10, all the transistors have a top-gate top-contact structure. In FIG. 11, all the transistors have a top-gate bottom-contact structure. However, the present invention is not limited to the configuration, and the transistor is a bottom gate type. That's fine.

[0165] This embodiment mode can be implemented in combination with the above embodiment modes.

[0166] (Embodiment 3) In this embodiment, a method for manufacturing a transistor constituting a cell array will be described. In this embodiment, a transistor including an oxide semiconductor is taken as an example to describe the transistor.

[0167] First, as shown in FIG. 12A, an insulating film 701 is formed on a substrate 700. A conductive film 702 and a conductive film 703 are formed on the transistor 712. It functions as a gate electrode of the transistor 713 and also as a word line. The conductive film 703 functions as a word line different from the word line described above.

[0168] There is no particular limitation on the material that can be used for the substrate 700, but at least the material that can be used for subsequent processing should be The substrate 700 must have sufficient heat resistance to withstand heat treatment. Glass substrates manufactured by the fusion method or float method, quartz substrates, semiconductor substrates, ceramic A glass substrate can be used if the temperature of the subsequent heat treatment is high. For this purpose, it is advisable to use a material with a strain point of 730°C or higher. Generally, substrates made of synthetic resin tend to have a lower heat resistance than the above-mentioned substrates. Any material can be used as long as it can withstand the processing temperatures in the process.

[0169] The insulating film 701 is made of a material that can withstand the temperature of a heat treatment in a later manufacturing process. The insulating film 701 may be made of silicon oxide, silicon nitride, silicon nitride oxide, silicon oxynitride, or aluminum nitride. It is preferable to use aluminum, aluminum oxide, etc.

[0170] In this specification, an oxynitride is a material having a composition in which oxygen is more abundant than nitrogen. Nitrogen oxide is a substance that contains more nitrogen than oxygen. It means substance.

[0171] The thickness of the conductive film 702 and the conductive film 703 is 10 nm to 400 nm, preferably 100 nm to In this embodiment, the thickness is set to 200 nm by sputtering using a tungsten target. After forming a 150 nm conductive film, the conductive film is etched to obtain the desired shape. The conductive films 702 and 703 are patterned. When the conductive films 702 and 703 have tapered ends, the gate insulating film laminated thereon can be formed in a thin film. This is preferable because it improves the coating property of the film. If the resist mask is formed by the inkjet method, a photomask is not required. This reduces manufacturing costs.

[0172] Next, as shown in FIG. 12B, a gate insulating film 70 is formed on the conductive film 702 and the conductive film 703. After forming the conductive film 702, an oxide semiconductor film is formed on the gate insulating film 704 at a position where the conductive film 702 overlaps the oxide semiconductor film 702. A semiconductor film 705 and an oxide semiconductor film 706 are formed.

[0173] The gate insulating film 704 is formed by depositing silicon oxide using a plasma CVD method or a sputtering method. Silicon nitride oxide, silicon oxynitride, silicon nitride, hafnium oxide, gallium oxide, aluminum oxide tantalum oxide, yttrium oxide, hafnium silicate (HfSi x O y (x >0, y>0), nitrogen-doped hafnium silicate (HfSi x O y (x>0, y>0), nitrogen-doped hafnium aluminate (HfAl x Oy (x>0, y> The layer can be formed by laminating a single film or a plurality of films containing the compound (I) or the like.

[0174] It is desirable that the gate insulating film 704 contains as little impurities as possible, such as moisture and hydrogen. When forming a silicon oxide film by sputtering, a silicon target is used. A quartz target or a quartz target is used, and oxygen or a mixture of oxygen and argon is used as the sputtering gas. A mixture of gases is used.

[0175] By removing impurities and reducing oxygen defects, the i-type or substantially i-type structure is obtained. The purified oxide semiconductor (highly purified oxide semiconductor) is extremely sensitive to interface states. Therefore, the oxide semiconductor films 705 and 706 are highly purified in a later process. As a result, the oxide semiconductor film 705 and the oxide semiconductor film 706 are Therefore, it is important to reduce the interface state at the gate insulating film 704. For example, high-density plastics using μ-waves (frequency 2.45 GHz) are required. Zuma CVD is preferred because it can form a dense, high-quality insulating film with high dielectric strength. The intimate contact between the oxidized oxide semiconductor and the high-quality gate insulating film reduces the interface state. As a result, the interface characteristics can be improved.

[0176] Of course, if a high-quality insulating film can be formed as the gate insulating film 704, the sputtering method can be used. Other deposition methods such as deposition and plasma CVD can be applied. The insulating film may be one whose film quality and interface characteristics with an oxide semiconductor are improved by the heat treatment. In any case, it goes without saying that the gate insulating film must be of high quality, and the gate insulating film and the oxide Any material may be used as long as it can reduce the interface state with the solid semiconductor and form a good interface.

[0177] Insulating films made of materials with high barrier properties, silicon oxide films with low nitrogen content, and silicon oxynitride films Alternatively, a gate insulating film 704 having a structure in which an insulating film such as a silicon oxide film is laminated may be formed. In this case, insulating films such as silicon oxide films and silicon oxynitride films are classified into insulating films with high barrier properties and oxide semi-insulating films. The insulating film is formed between the conductive film 705 and the oxide semiconductor film 706. For example, a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, or an aluminum oxynitride film. By using an insulating film with high barrier properties, it is possible to prevent moisture or hydrogen from entering the atmosphere. Impurities in the substrate 700, such as alkali metals and heavy metals, are oxidized. In the oxide semiconductor film 705, the oxide semiconductor film 706, the gate insulating film 704, or the oxide semiconductor Preventing the conductive film 705, the oxide semiconductor film 706, and other insulating films from penetrating into the interfaces and their vicinity. In addition, a nitrogen oxide film can be formed in contact with the oxide semiconductor film 705 and the oxide semiconductor film 706. By forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low content of In order to prevent the insulating film having a high thermal conductivity from being in direct contact with the oxide semiconductor film 705 and the oxide semiconductor film 706, can be done.

[0178] For example, the first gate insulating film is formed by sputtering to a thickness of 50 nm to 200 nm. The following silicon nitride films (SiN y (y>0) is formed, and a second gate insulating film is formed on the first gate insulating film. The insulating film is a silicon oxide film (SiO x (x>0) The gate insulating film 704 may be layered to a thickness of 100 nm. may be appropriately set depending on the characteristics required for the transistor.

[0179] In this embodiment, a silicon nitride film having a thickness of 50 nm is formed by sputtering. The gate insulating film 70 has a structure in which a silicon oxide film having a thickness of 100 nm formed by the above method is laminated. Form 4.

[0180] Note that the gate insulating film 704 is formed over the oxide semiconductor film 705 and the oxide semiconductor film 70 When hydrogen is contained in the oxide semiconductor film 705 and the oxide semiconductor film 706, Since the gate insulating film 704 is degraded by hydrogen, hydroxyl groups, and water, the electrical characteristics of the transistor are adversely affected. It is preferable that the gate insulating film 704 does not contain hydrogen, hydroxyl groups, or moisture. In order to prevent this, the pre-heating chamber of the sputtering device is used as a pre-treatment for film formation. The substrate 700 on which the conductive film 702 and the conductive film 703 are formed is preheated, and the conductive film 702 is adhered to the substrate 700. It is preferable to desorb and exhaust impurities such as moisture and hydrogen that have been absorbed in the preheating temperature. The temperature is 100°C or higher and 400°C or lower, preferably 150°C or higher and 300°C or lower. The exhaust means provided in the preheating chamber is preferably a cryopump. It can also be omitted.

[0181] The oxide semiconductor films 705 and 706 are formed on an oxide semiconductor film formed over the gate insulating film 704. The oxide semiconductor film can be formed by processing the oxide semiconductor film into a desired shape. The thickness of the film is 2 nm or more and 200 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably The oxide semiconductor film is formed by depositing an oxide semiconductor on the substrate. The oxide semiconductor film is formed by sputtering using a rare gas (e.g., argon). ) atmosphere, oxygen atmosphere, or a mixture of rare gas (e.g. argon) and oxygen atmosphere. The film can be formed by a sputtering method.

[0182] Note that before the oxide semiconductor film is formed by a sputtering method, argon gas is introduced to the plasma The reverse sputtering is performed to generate a mask, and the dust adhering to the surface of the gate insulating film 704 is removed. In reverse sputtering, the target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power source under atmospheric pressure to form plasma near the substrate and modify the surface. It is to be noted that nitrogen, helium, or the like may be used in place of the argon atmosphere. Alternatively, the treatment may be carried out in an atmosphere in which oxygen, nitrous oxide, etc. are added to an argon atmosphere. Alternatively, the treatment may be carried out in an atmosphere in which chlorine, carbon tetrafluoride, etc. have been added to the argon atmosphere.

[0183] The oxide semiconductor film is made of the above-mentioned quaternary metal oxide In-Sn-Ga-Z n-type oxide semiconductors, In-Ga-Zn-type oxide semiconductors, which are oxides of ternary metals, In -Sn-Zn oxide semiconductor, In-Al-Zn oxide semiconductor, Sn-Ga-Zn oxide Semiconductors made of gallium nitride, Al-Ga-Zn oxide semiconductors, Sn-Al-Zn oxide semiconductors, and In-Zn oxide semiconductors, Sn-Zn oxide semiconductors, and Al- Zn-based oxide semiconductor, Zn-Mg-based oxide semiconductor, Sn-Mg-based oxide semiconductor, In-M In-based oxide semiconductors, In-Ga-based oxide semiconductors, In-based oxide semiconductors, Sn-based oxide semiconductors A conductor, a Zn-based oxide semiconductor, etc. can be used.

[0184] In this embodiment, a tantalum containing In (indium), Ga (gallium), and Zn (zinc) is used. A 30 nm thick In-Ga-Zn oxide semiconductor was obtained by sputtering using a Zn-type target. A thin film of a conductor is used as an oxide semiconductor film. When the film is formed by the ion-spraying method, the atomic ratio of In:Ga:Zn is preferably 1:1:1. In-, indicated as 4:2:3, 3:1:2, 1:1:2, 2:1:3, or 3:1:4 A target of Ga-Zn oxide is used. In-Ga-Zn oxide with the above-mentioned atomic ratio is used. By forming an oxide semiconductor film using an oxide target, a polycrystalline or CAAC film can be obtained. In addition, the filling rate of the target containing In, Ga, and Zn is 90% or more. The filling rate is preferably 95% or more and less than 100%. By using such a material, the formed oxide semiconductor film becomes a dense film.

[0185] When an In-Zn oxide material is used as the oxide semiconductor, the target to be used is The composition ratio is In:Zn=50:1 to 1:2 in atomic ratio (InO 3:ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (molar ratio In terms of the ratio, In2O3:ZnO=10:1 to 1:2), and more preferably In:Zn= 1.5:1 to 15:1 (converted to a molar ratio of In2O3:ZnO=3:4 to 15:2) For example, the target used for forming an oxide semiconductor film made of an In-Zn oxide is When the atomic ratio is In:Zn:O=X:Y:Z, Z>1.5X+Y. The ratio of Zn Within the above range, it is possible to improve the mobility.

[0186] In addition, when forming an In-Sn-Zn oxide, the composition ratio of the target used is set to In :Sn:Zn atomic ratio is 1:2:2, 2:1:3, 1:1:1, or 20:45: Let's say it's 35.

[0187] In this embodiment, the substrate is held in a processing chamber that is maintained in a reduced pressure state, and residual moisture in the processing chamber is removed. While removing the hydrogen and moisture, a sputtering gas from which hydrogen and moisture have been removed is introduced, and the above target is used. During the deposition, the substrate temperature is set to 100° C. or higher and 600° C. or lower, preferably. The deposition temperature may be 200° C. or more and 400° C. or less. In addition, the concentration of impurities in the oxide semiconductor film can be reduced. To remove residual moisture in the processing chamber, a suction-type vacuum pump is used. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. It is preferable to use a displacement pump as the exhaust means. A cryopump may be used to evacuate the deposition chamber. For example, hydrogen atoms, water (HO) and other compounds containing hydrogen atoms (more preferably carbon atoms Since the exhaust gas contains the compound containing the compound, the oxide semiconductor film formed in the deposition chamber is The concentration of impurities can be reduced.

[0188] As an example of the deposition conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa. The conditions were: DC power supply 0.5kW, oxygen (oxygen flow rate 100%) atmosphere. In addition, if a pulsed direct current (DC) power supply is used, dust generated during film formation can be reduced, and the film can be This is preferable since the thickness distribution is also uniform.

[0189] In order to prevent hydrogen, a hydroxyl group, and moisture from being contained in the oxide semiconductor film as much as possible, As a pre-treatment for film formation, the gate insulating film 704 is formed in the pre-heating chamber of the sputtering device. The substrate 700 is preheated to remove impurities such as moisture or hydrogen adsorbed on the substrate 700. The preheating temperature is preferably 100°C or higher and 400°C or lower. The temperature is preferably 150°C or higher and 300°C or lower. A pump is preferable. However, this preheating process may be omitted.

[0190] In addition, the leak rate of the sputtering equipment processing chamber was set to 1×10 -10 Pa·m 3 / second or less By doing so, it is possible to prevent alkali from being added to the oxide semiconductor film during the film formation by the sputtering method. It is possible to reduce the inclusion of impurities such as metals and hydrides. By using an adsorption type vacuum pump, alkali metals, hydrogen atoms, hydrogen molecules, The backflow of impurities such as water, hydroxyl radicals, or hydrides can be reduced.

[0191] In addition, by setting the purity of the target to 99.99% or more, the amount of the target that is mixed into the oxide semiconductor film can be reduced. It is possible to reduce alkali metals, hydrogen atoms, hydrogen molecules, water, hydroxyl groups, hydrides, etc. In addition, by using the target, lithium, sodium, and the like can be easily formed in the oxide semiconductor film. The concentration of alkali metals such as sodium and potassium can be reduced.

[0192] Note that etching for forming the oxide semiconductor films 705 and 706 was performed using a doped Dry etching or wet etching may be used, or both may be used. The etching gas used in this process is a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2 ), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride (CCl4), etc. ) is preferable. In addition, a gas containing fluorine (a fluorine-based gas, for example, carbon tetrafluoride (CF4), Sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.) , hydrogen bromide (HBr), oxygen (O2), and these gases are mixed with helium (He) and argon (A r), or a gas containing an added rare gas such as argon.

[0193] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing method and ICP (Inductively Coupled Plasma) A method of etching a silicon wafer using a plasma-coupled plasma (PPS) can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are adjusted appropriately.

[0194] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. In the present embodiment, an organic acid such as phosphoric acid or oxalic acid can be used. (Kanto Chemical Co., Ltd.) is used.

[0195] Resist masks for forming the oxide semiconductor films 705 and 706 are formed by ink jet printing. If the resist mask is formed by the inkjet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0196] Note that reverse sputtering is performed before forming a conductive film in the next step. Resist residues adhering to the surfaces of the semiconductor film 706 and the gate insulating film 704 are removed. It is preferable that

[0197] Note that moisture or hydrogen (water) may be contained as an impurity in the oxide semiconductor film formed by sputtering or the like. Water or hydrogen tends to form donor levels. Therefore, in one embodiment of the present invention, In order to reduce impurities such as moisture or hydrogen in the conductor film (dehydration or dehydrogenation), Atmosphere, inert gas atmosphere such as nitrogen or rare gas, oxygen gas atmosphere, or ultra-dry air (When measured using a CRDS (Cavity Ring Down Laser Spectroscopy) type dew point meter The moisture content in the case of the above is 20 ppm or less (-55°C in terms of dew point), preferably 1 ppm or less, more preferably The oxide semiconductor film 705 and the oxide semiconductor film 706 are The mixture is subjected to heat treatment.

[0198] The oxide semiconductor films 705 and 706 are subjected to heat treatment. Moisture or hydrogen in the oxide semiconductor film 705 and the oxide semiconductor film 706 can be eliminated. Heat treatment is performed at a temperature of 250° C. or higher and 750° C. or lower, preferably at a temperature of 400° C. or higher and lower than the distortion point of the substrate. For example, the heat treatment can be performed at 500°C for 3 to 6 minutes. If the RTA method is used, dehydration or dehydrogenation can be performed in a short time, so the strain point of the glass substrate can be reduced. It can also be processed at temperatures above this.

[0199] In this embodiment mode, an electric furnace, which is one of the heat treatment devices, is used.

[0200] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat radiation from a heating element such as a resistance heating element. The apparatus may be equipped with a device for heating the object to be treated by irradiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, high pressure water A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the workpiece during heat treatment, such as a rare gas such as argon or nitrogen. The body is used.

[0201] In the heat treatment, nitrogen or rare gas such as helium, neon, or argon is mixed with water or water. It is preferable that the nitrogen or helium introduced into the heat treatment device is not included. The purity of rare gases such as neon and argon is 6N (99.9999%) or more, preferably 7N (99.9999%) or more. N (99.99999%) or more (i.e., impurity concentration is 1 ppm or less, preferably 0.1 ppm pm or less).

[0202] In addition, oxide semiconductors are insensitive to impurities, and the film contains a considerable amount of metal impurities. There is no problem with using sodalite, which is inexpensive and contains a large amount of alkali metals such as sodium. It has been pointed out that ash glass can also be used (Kamiya, Nomura, Hosono, "Amorphous Oxide Semiconductors" "Current status of physical properties and device development," Solid State Physics, September 2009, Vol. 44, pp. 62 1-633.) However, this is not an appropriate indication. Alkali metals form oxide semiconductors. Alkaline earth metals are not constituent elements of oxide semiconductors and are therefore considered impurities. In particular, Na, an alkali metal, is an impurity when it is not an element that is included in the alloy. When the insulating film in contact with the semiconductor film is an oxide, Na diffuses into the insulating film. + It becomes. In addition, Na separates the bonds between the metal and oxygen that constitute the oxide semiconductor in the oxide semiconductor film. As a result, for example, the threshold voltage may shift in the negative direction. The shift leads to degradation of transistor characteristics such as normally on and reduced mobility. In addition, the transistor characteristics may vary. The deterioration and variation in characteristics occur when the hydrogen concentration in the oxide semiconductor film is sufficiently low. Therefore, the hydrogen concentration in the oxide semiconductor film is more pronounced when the hydrogen concentration is 1×10 18 / cm 3 below, More preferably, 1×10 17 / cm 3 If it is less than 100%, reduce the concentration of the impurity. Specifically, the measured value of the Na concentration by secondary ion mass spectrometry is 5×10 16 / cm 3 Less than or equal to 1×10 16 / cm 3 More preferably, 1×10 15 / cm 3 Similarly, the measured value of Li concentration should be 5×10 15 / cm 3 below, Preferably 1 x 10 15 / cm 3 Similarly, the measured value of the K concentration should be 5 x 1 0 15 / cm 3 Less than or equal to 1×10 15 / cm 3 The following should be used.

[0203] Through the above steps, the hydrogen concentrations in the oxide semiconductor films 705 and 706 are reduced. Therefore, the oxide semiconductor film can be highly purified, and the oxide semiconductor film can be stabilized. In addition, the carrier density caused by hydrogen defects is extremely low when the material is heated below the glass transition temperature. Therefore, it is possible to form an oxide semiconductor film having a wide band gap. The plate can be used to manufacture transistors, which can improve mass productivity. The treatment can be performed at any time after the formation of the oxide semiconductor film.

[0204] Note that the oxide semiconductor films 705 and 706 may be amorphous or crystalline. The crystalline oxide semiconductor film may have a crystallinity having a c-axis orientation. Oxide semiconductor (also called C Axis Aligned Crystal: CAAC) Even if the oxide semiconductor film contains This is preferable because it is possible.

[0205] The oxide semiconductor film composed of CAAC can also be fabricated by a sputtering method. In order to obtain CAAC by sputtering, the oxide semiconductor film must be deposited at the initial stage. The method comprises the steps of: forming a hexagonal crystal by using the hexagonal crystal as a seed; and growing a crystal by using the hexagonal crystal as a seed. To achieve this, it is important to keep the target and substrate apart (for example, For example, about 150 mm to 200 mm), and the substrate heating temperature is set to 100°C to 500°C, preferably 20 The temperature is preferably 0°C to 400°C, and more preferably 250°C to 300°C. In addition, the deposited oxide semiconductor film is heat-treated at a temperature higher than the substrate heating temperature during film formation. This makes it possible to repair microscopic defects in the film and defects at the interface of the stacked layers.

[0206] Specifically, CAAC is a hexagonal lattice bond in the ab plane parallel to the insulating film surface. and a zinc-containing crystal having a hexagonal crystal structure and a c-axis orientation approximately perpendicular to the ab plane. It's Akira.

[0207] Compared to amorphous oxide semiconductors, CAAC has an ordered structure of metal-oxygen bonds. In other words, when the oxide semiconductor is amorphous, the coordination number may differ depending on the individual metal atoms. It is possible, but in CAAC, the coordination number of the metal atom is almost constant. Therefore, the microscopic oxygen The deficiency of hydrogen atoms (including hydrogen ions) and alkali metal atoms is reduced, and the release and bonding of hydrogen atoms and alkali metal atoms It has the effect of reducing charge transfer and instability.

[0208] Therefore, by manufacturing a transistor using an oxide semiconductor film formed of CAAC, Occurs after a transistor is exposed to light or subjected to bias-thermal stress (BT) Therefore, the amount of change in the threshold voltage of the transistor can be reduced. It is possible to fabricate transistors with dielectric properties.

[0209] Next, as shown in FIG. 12C, a source electrode or a drain electrode is formed over the oxide semiconductor film 705. The conductive films 707 and 708 functioning as gate electrodes are formed over the oxide semiconductor film 706. A conductive film 709 and a conductive film 710 which function as a source electrode and a drain electrode are formed.

[0210] Specifically, the conductive films 707 to 710 are formed by the oxide semiconductor film 705 and the oxide semiconductor film After forming a conductive film on the substrate 706 by sputtering or vacuum deposition, the conductive film is molded into a desired shape. The film can be formed by patterning.

[0211] The conductive films 707 to 710 can be formed using a material selected from the group consisting of aluminum, chromium, copper, tantalum, and the like. An element selected from titanium, molybdenum, and tungsten, or a composite material containing the above elements. The metal layer may be a gold layer or an alloy layer made of a combination of the above elements. In addition, the metal layer may be a aluminum layer, a copper layer, etc. Chromium, tantalum, titanium, molybdenum, tungsten, etc. on the underside or on the top of the metal film The metal film may be a laminate of any high melting point metal film. To avoid problems with corrosion, it is recommended to use it in combination with high melting point metal materials. Metal materials include molybdenum, titanium, chromium, tantalum, tungsten, neodymium, Scandium, yttrium, etc. can be used.

[0212] The conductive films 707 to 710 may each be formed of a single conductive film. For example, the conductive film may be formed by laminating a plurality of conductive films. A single-layer structure of aluminum film, a two-layer structure of titanium film laminated on aluminum film, a titanium film, An aluminum film is layered on top of the titanium film, and a titanium film is then formed on top of that, resulting in a three-layer structure. Structure, etc.

[0213] The conductive films 707 to 710 are formed using a conductive metal oxide. The conductive metal oxide may be indium oxide, tin oxide, zinc oxide, indium oxide, or zinc oxide. Indium tin oxide mixture, indium oxide zinc oxide mixture or the above metal oxide materials with silicon It is possible to use a material containing silicon or silicon oxide.

[0214] In the case where heat treatment is performed after the conductive films 707 to 710 are formed, the conductive films 707 to 710 must be made of a material that can withstand the heat treatment. It is preferable that the conductive films 707 to 710 have high heat resistance.

[0215] Note that the oxide semiconductor films 705 and 706 are formed during etching of the conductive film. The materials and etching conditions are appropriately adjusted so that the etching is performed without removing the remaining material. Depending on the conditions, exposed portions of the oxide semiconductor film 705 and the oxide semiconductor film 706 may be partially etched. By etching, a groove (recess) may be formed.

[0216] In this embodiment, a titanium film is used as the conductive films 707 to 710. Therefore, a solution containing ammonia and hydrogen peroxide (ammonia hydrogen peroxide solution) is used to selectively induce The oxide semiconductor film 705 and the oxide semiconductor film 706 can be etched by wet etching. 706 may also be partially etched. Specifically, the solution containing ammonia hydrogen peroxide is 31% hydrogen peroxide, 28% ammonia and water in a volume ratio of 5:2:2 Use a mixed aqueous solution. Or use a solution containing chlorine (Cl2), boron trichloride (BCl3), etc. The conductive film may be dry-etched using a gas.

[0217] In order to reduce the number of photomasks and steps used in the photolithography process, A resist mask formed by a multi-tone mask that gives multiple levels of intensity to the light is used. The resist mask formed using the multi-tone mask may be a multi-layer mask. The shape can be further modified by etching. Therefore, it can be used in multiple etching processes to process different patterns. A resist that corresponds to at least two different patterns using a single multi-tone mask Therefore, the number of exposure masks can be reduced, and the corresponding Since the photolithography process can also be eliminated, the process can be simplified.

[0218] In addition, the oxide semiconductor film 705 and the conductive film 707 functioning as a source electrode or a drain electrode and between the conductive film 708 or between the oxide semiconductor film 706 and the source or drain electrode Between the conductive film 709 and the conductive film 710 serving as the source region and the drain region, As a material for the oxide conductive film, an oxide conductive film may be provided. It is preferable that the material contains zinc as a component, and it is preferable that the material does not contain indium oxide. Such oxide conductive films include zinc oxide, zinc aluminum oxide, and zinc aluminum oxynitride. Aluminum, etc. can be applied.

[0219] For example, in the case of forming an oxide conductive film, a patterning process for forming the oxide conductive film is performed. The conductive films 707 to 710 are patterned together. is also good.

[0220] By providing an oxide conductive film functioning as a source region and a drain region, Resistance between the oxide semiconductor film 705 and the conductive film 707 and between the oxide semiconductor film 706 and the conductive film 708 Since the resistance between the conductive film 709 and the conductive film 710 can be reduced, the high-speed operation of the transistor can be improved. In addition, the oxide layer that functions as the source and drain regions can be formed. By providing the conductive film, the withstand voltage of the transistor can be increased.

[0221] Next, a plasma treatment may be performed using a gas such as N2O, N2, or Ar. The plasma treatment removes water and the like attached to the exposed surface of the oxide semiconductor film. Alternatively, a plasma treatment may be performed using a mixed gas of oxygen and argon.

[0222] After the plasma treatment, the conductive films 707 to 7 An insulating film 711 is formed to cover the oxide semiconductor film 705 and the oxide semiconductor film 706. Form.

[0223] The insulating film 711 is formed using the same material and the same layered structure as the gate insulating film 704. The insulating film 711, like the gate insulating film 704, is resistant to moisture and hydrogen. It is preferable that the insulating film 711 does not contain impurities such as hydrogen. The hydrogen penetrates into the oxide semiconductor film 705 and the oxide semiconductor film 706. Oxygen is extracted from the oxide semiconductor film 706, and the oxide semiconductor film 705 and the oxide semiconductor film 70 6 becomes low resistance (n-type), which may cause a parasitic channel to form. In order to form the insulating film 711 as a film containing as little hydrogen as possible, a method for forming the insulating film is used that does not use hydrogen. It is important that the insulating film 711 is made of a material having a high barrier property. For example, insulating films with high barrier properties include silicon nitride films, silicon oxynitride films, and aluminum nitride films. A laminate of insulating films, such as an aluminum nitride oxide film, an aluminum oxide film, or the like, can be used. When using an insulating film such as a silicon oxide film or a silicon oxynitride film having a low nitrogen content, The insulating film having a high barrier property is closer to the oxide semiconductor film 705 and the oxide semiconductor film 706. Then, the conductive films 707 to 709 are formed with an insulating film having a low nitrogen content therebetween. The oxide semiconductor film 710 and the oxide semiconductor film 705 and the oxide semiconductor film 706 are overlapped with each other. By using an insulating film with high barrier properties, the oxide semiconductor film 705 and the oxide In the oxide semiconductor film 706, in the insulating film 711, or in the oxide semiconductor film 705, the oxide semiconductor The film 706 is formed by absorbing impurities such as water and hydrogen into the interface between the film 706 and other insulating films and the vicinity thereof. In addition, a nitride semiconductor film is formed in contact with the oxide semiconductor film 705 and the oxide semiconductor film 706. By forming an insulating film such as a silicon oxide film or a silicon oxynitride film with a low ratio of silicon, the barrier property is improved. The insulating film using a high-temperature material is in direct contact with the oxide semiconductor film 705 and the oxide semiconductor film 706. This can be prevented.

[0224] In this embodiment, a silicon oxide film having a thickness of 200 nm is formed by sputtering. The insulating film 711 has a structure in which a silicon nitride film having a thickness of 100 nm formed by a method is laminated. The substrate temperature during film formation may be set to a temperature between room temperature and 300° C. in this embodiment. The temperature is 100°C.

[0225] Note that heat treatment may be performed after the insulating film 711 is formed. In an atmosphere of dry air or rare gas (argon, helium, etc.), preferably at 200 The temperature is from 250°C to 350°C, for example. is 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less. In this embodiment, for example, heat treatment is performed in a nitrogen atmosphere at 250° C. for 1 hour. Alternatively, before the conductive films 707 to 710 are formed, moisture or hydrogen is reduced. In the same manner as the heat treatment performed on the oxide semiconductor film for the purpose of After the insulating film 711 containing oxygen is provided, heat treatment is performed. Therefore, the oxide semiconductor films 705 and 706 were subjected to the heat treatment. Even if oxygen vacancies occur in the oxide semiconductor films 705 and 706, Oxygen is supplied from the insulating film 711 to the oxide semiconductor film 705 and the oxide semiconductor film 706. In addition, oxygen is supplied to the oxide semiconductor films 705 and 706, so that the oxide semiconductor films In the semiconductor film 705 and the oxide semiconductor film 706, oxygen vacancies serving as donors are reduced, and The oxide semiconductor film 705 and the oxide semiconductor film 706 can have a stoichiometric composition. It is preferred that the oxygen content of the oxygen-containing oxide exceeds the stoichiometric ratio. The nitride semiconductor film 705 and the oxide semiconductor film 706 can be made closer to i-type. This reduces the variation in the electrical characteristics of the transistors that are used, thereby improving their electrical characteristics. Cut.

[0226] In addition, the oxide semiconductor films 705 and 706 are subjected to heat treatment in an oxygen atmosphere. In this manner, oxygen is added to the oxide semiconductor, and the oxide semiconductor film 705 and the oxide semiconductor film 706 are formed. The temperature of the heat treatment may be, for example, 100° C. or higher. The heating temperature is set to 350° C. or lower, preferably 150° C. or higher and lower than 250° C. in an oxygen atmosphere. It is preferable that the oxygen gas used in the treatment does not contain water, hydrogen, etc. The purity of the oxygen gas introduced into the treatment device is set to 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e., impurity concentration in oxygen is 1 ppm or less, preferably 0 It is preferable to keep the concentration at 0.1 ppm or less.

[0227] Alternatively, the oxide semiconductor film 705 and the acid By adding oxygen to the compound semiconductor film 706, oxygen vacancies acting as donors may be reduced. For example, oxygen plasma generated by microwaves of 2.45 GHz is used for the oxide semiconductor film 705. The oxide semiconductor film 706 may be doped with this compound.

[0228] Through the above steps, a transistor 712 and a transistor 713 are formed. The gate electrode 712 is made of a conductive film 702 that functions as a gate electrode, a gate insulating film 704, and an oxide film. A semiconductor film 705, a conductive film 707 functioning as a source electrode or a drain electrode, and a conductive The transistor 712 includes an insulating film 711 as a component thereof. The transistor 713 includes a conductive film 702 functioning as a gate electrode and a gate insulating film 704. The insulating film 704, the oxide semiconductor film 706, and a semiconductor layer functioning as a source electrode or a drain electrode The transistor 713 includes a conductive film 709 and a conductive film 710. It may be included in the components.

[0229] The conductive film 703 and the conductive film 708 overlap with each other with the gate insulating film 704 interposed therebetween. This corresponds to a capacitor element 714. In addition, the conductive film 703 and the conductive film 704 are sandwiched between them. The portion where the conductive film 710 overlaps corresponds to a capacitance element 715 .

[0230] Note that many oxide semiconductors contain Group 13 elements, and insulating materials containing Group 13 elements are The oxide semiconductor has good compatibility with the insulating film (in this embodiment, The gate insulating film 704 and the insulating film 711 correspond to the above-mentioned insulating films. Therefore, the interface characteristics between the body film and the insulating film can be maintained excellent.

[0231] An insulating material containing a Group 13 element means that the insulating material contains one or more Group 13 elements. Examples of insulating materials containing Group 13 elements include gallium oxide and aluminum oxide. gallium oxide, aluminum gallium oxide, and gallium aluminum oxide. Aluminum gallium is a metal whose aluminum content (atomic percent) is higher than its gallium content (atomic percent). %), and gallium aluminum oxide is a material with a high gallium content (atomic %). This indicates an aluminum content (atomic percent) or higher.

[0232] For example, when an insulating film is formed in contact with an oxide semiconductor film containing gallium, By using a material containing gallium oxide, the interface characteristics between the oxide semiconductor film and the insulating film can be kept good. For example, an oxide semiconductor film and an insulating film containing gallium oxide can be provided in contact with each other. As a result, the pile-up of hydrogen at the interface between the oxide semiconductor film and the insulating film can be reduced. In addition, when an element of the same group as the component element of the oxide semiconductor is used for the insulating film, the same can be said. For example, it is possible to form an insulating film using a material containing aluminum oxide. It is also effective to form a thin film of aluminum oxide, which has the characteristic of being difficult for water to pass through. Therefore, the use of this material is advantageous in terms of preventing water from entering the oxide semiconductor film. It is also preferred in

[0233] The insulating films in contact with the oxide semiconductor films 705 and 706 are heated under an oxygen atmosphere. By heat treatment using oxygen or oxygen doping, insulating materials are made into a state with more oxygen than the stoichiometric composition ratio. The oxygen doping means adding oxygen to the bulk. The term "bulk" is used to clarify that oxygen is added not only to the surface of the thin film but also to the inside of the thin film. For oxygen doping, oxygen plasma is added to the bulk. Oxygen doping is performed by using ion implantation or ion doping. It is acceptable to do so.

[0234] For example, a gallium oxide insulating film may be used as an insulating film in contact with the oxide semiconductor film 705 and the oxide semiconductor film 706. When using gallium oxide, the gallium oxide can be removed by heat treatment in an oxygen atmosphere or by oxygen doping. The composition of the aluminum is GaO X (X=3+α, 0<α<1).

[0235] In addition, an insulating film in contact with the oxide semiconductor film 705 and the oxide semiconductor film 706 is made of aluminum oxide. When aluminum is used, it is possible to obtain aluminum oxide by performing heat treatment in an oxygen atmosphere or oxygen doping. The composition of aluminum is AlO X (X=3+α, 0<α<1).

[0236] In addition, gallium oxide was used as an insulating film in contact with the oxide semiconductor film 705 and the oxide semiconductor film 706. When aluminum (aluminum gallium oxide) is used, heat treatment in an oxygen atmosphere or By doping with oxygen, gallium aluminum oxide (aluminum gallium oxide) ) composition of Ga X Al 2-X O 3+α (0 <X<2、0<α<1)とすることができる。

[0237] By performing oxygen doping treatment, an insulating film having a region in which oxygen is more abundant than the stoichiometric composition ratio is formed When the insulating film having such a region is in contact with the oxide semiconductor film, As a result, excess oxygen in the insulating film is supplied to the oxide semiconductor film, and the oxide semiconductor film or the oxygen The oxide semiconductor film is made i-type or i-type by reducing oxygen defects at the interface between the oxide semiconductor film and the insulating film. It is possible to make it as close as possible to the mold.

[0238] Note that the insulating film having a region containing more oxygen than the stoichiometric composition is the oxide semiconductor film 705. Among the insulating films in contact with the oxide semiconductor film 706, an insulating film located above or a It may be used for only one of the insulating films, but it is preferable to use it for both insulating films. The insulating film having a region containing more oxygen than the stoichiometric composition is an oxide semiconductor film 705. The insulating film is used for the insulating film located above and below the oxide semiconductor film 706. The above effect can be further enhanced by sandwiching the oxide semiconductor film 705 and the oxide semiconductor film 706. can be done.

[0239] The insulating films used above or below the oxide semiconductor film 705 and the oxide semiconductor film 706 are The upper and lower insulating films may have the same constituent elements, or may have different constituent elements. For example, the composition of the upper and lower layers may be GaO X (X=3+α, 0<α<1 ) gallium oxide, or one of the upper and lower parts may be made of GaO X (X=3+α, 0<α<1) and the other is AlO X (X=3+α, 0<α<1) Aluminum oxide may also be used.

[0240] In addition, the insulating films in contact with the oxide semiconductor film 705 and the oxide semiconductor film 706 have a stoichiometric composition. For example, the oxide semiconductor film 70 may be a stack of insulating films each having a region with a relatively large amount of oxygen. 5. Above the oxide semiconductor film 706, a layer having a composition of GaO X Oxidation of (X=3+α, 0<α<1) Gallium is formed on it, and the composition is Ga X Al 2-X O 3+α (0 <X<2、0<α<1 ) may be formed as gallium aluminum oxide (aluminum gallium oxide). The oxide semiconductor film 705 and the oxide semiconductor film 706 are formed under the oxide semiconductor film 705 and the oxide semiconductor film 706. Alternatively, the oxide semiconductor film 705 and the oxide semiconductor film 706 may be stacked. The upper and lower portions of the insulating film 06 are each formed of an insulating film having an area with more oxygen than the stoichiometric composition ratio. It may also be layered.

[0241] This embodiment mode can be implemented in combination with the above embodiment modes.

[0242] (Embodiment 4) An example of a specific configuration of a driver circuit in a memory device according to one embodiment of the present invention will be described.

[0243] FIG. 13 is a block diagram illustrating an example of a specific configuration of a memory device according to one embodiment of the present invention. In the block diagram shown in Figure 13, the circuits in the memory device are classified by function and are mutually Although they are shown as independent blocks, the actual circuit can be completely separated by function. It is difficult, and one circuit may be involved in multiple functions.

[0244] The memory device 300 shown in FIG. The drive circuit 302 is a read circuit that generates a signal including data read from the cell array 301. A read circuit 303, a word line drive circuit 304 for controlling the potential of the word line, and a cell array 3 A bit line driver circuit controls writing of data to the memory cell selected in step 01. The driving circuit 302 further includes a read circuit 303, a word line driving circuit 304, and a write circuit 305. The control circuit 306 controls the operation of the bit line driver circuit 305 .

[0245] As shown in FIG. 9, when the cell array 301 is composed of multiple blocks, A word line driver circuit and a bit line driver circuit corresponding to each block may be provided.

[0246] In the memory device 300 shown in FIG. 13, the word line driver circuit 304 is connected to a decoder 307. , a level shifter 308, and a buffer 309. The bit line driver circuit 305 It includes a decoder 310 and a selector 312 .

[0247] The memory device 300 according to one embodiment of the present invention includes at least the cell array 301 as its configuration. Furthermore, the memory device 300 according to one embodiment of the present invention may include a cell array 301. The memory module in which a part or all of the driving circuit 302 is connected to the The memory module is provided with connection terminals that can be mounted on a printed wiring board, etc. The semiconductor device may be in a so-called packaged state, that is, protected by a resin or the like.

[0248] Also, a cell array 301, a read circuit 303, a word line driving circuit 304, a bit line driving circuit 305, The circuit 305 and the control circuit 306 may be formed using a single substrate. One or all of the electrodes may be formed using a different substrate.

[0249] If different substrates are used, FPC (Flexible Printed Circuit) In this case, the electrical connection of the driving circuit 302 can be ensured through a A part of it may be connected to the FPC using a COF (Chip On Film) method. Alternatively, the COG (Chip On Glass) method can be used to ensure electrical connection. This can be done.

[0250] A signal A, which includes the address (Ax, Ay) of the cell array 301 as information, is input to the memory device 300. When D is input, the control circuit 306 transmits the address Ax in the column direction to the bit line driving circuit 305. and sends row address Ay to the word line driver circuit 304. The signal DATA including the data input to the memory device 300 is transmitted to the bit line driving circuit 305. Send to.

[0251] The selection of data write and read operations in the cell array 301 is performed by the control circuit 30 The RE (Read enable) and WE (Write enable) signals are supplied to 9, the cell array 301 may be a plurality of blocks. When the block is configured as a block, the control circuit 306 receives a signal C for selecting the block. E (Chip enable) may be input. In this case, the signal RE and the signal WE The operation selected by signal CE is executed in the block selected by signal CE.

[0252] In the cell array 301, when a write operation is selected by the signal WE, the control circuit 306 In response to the instruction from the word line driver circuit 304, the decoder 307 in the word line driver circuit 304 reads the address A signal is generated to select a memory cell corresponding to the Ay level shift register. After the amplitude of the potential is adjusted by the lid 308, the waveform is processed in the buffer 309. The signal is input to the cell array 301. On the other hand, in the bit line driving circuit 305, the control circuit 3 In accordance with the instruction from 06, the address of the memory cell selected by the decoder 310 is A signal is generated to select a memory cell corresponding to the selector Ax. The signal DATA is input to the selector 312. The selector 312 samples the signal DATA according to the input signal. The sampled signal is input to the memory cell corresponding to the address (Ax, Ay). To exert effort.

[0253] In addition, in the cell array 301, when a read operation is selected by a signal RE, the control circuit In response to an instruction from 306, a decoder 307 in the word line driving circuit 304 A signal is generated to select a memory cell corresponding to the address Ay. After the amplitude is adjusted by the bell shifter 308, the waveform is processed in the buffer 309. , is input to the cell array 301. Meanwhile, in the read circuit 303, In accordance with this instruction, among the memory cells selected by the decoder 307, the memory cell corresponding to the address Ax is Then, the memory cell corresponding to the address (Ax, Ay) is selected. The stored data is read and a signal containing the data is generated.

[0254] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0255] (Embodiment 5) In this embodiment, an example of a specific configuration of the readout circuit will be described.

[0256] The potential read from the cell array is determined according to the data written in the memory cell. Therefore, ideally, multiple memory cells would store the same digital value. If the voltages are stored in the memory cells, the voltages read from the memory cells are all at the same level. However, in reality, the transistors that function as memory elements or the transistors that function as read elements are The characteristics of the transistor that functions as a switching element in the In this case, the data to be read out may all have the same digital value. However, the potential actually read out varies, and the potential distribution has a certain range. Therefore, even if there is some variation in the potential read from the cell array, accurate data can be obtained. The readout contains the data and produces a signal whose amplitude and waveform are processed to meet the desired specifications. It is preferable that the output circuit is provided in the drive circuit.

[0257] FIG. 14 is a circuit diagram showing an example of a readout circuit. The readout circuit shown in FIG. A switch for controlling the input of the potential Vdata read from the A transistor 260 functions as a switching element, and a transistor 261 functions as a resistor. 14 includes an operational amplifier 262.

[0258] Specifically, the transistors 261 each have a gate electrode and a drain terminal connected to each other. Moreover, a high-level power supply potential Vdd is applied to the gate electrode and the drain terminal. The source terminal of the transistor 261 is connected to the non-inverting input of the operational amplifier 262. The transistor 261 is connected to the terminal (+). A resistor connected between the node where the resistor is connected and the non-inverting input terminal (+) of the operational amplifier 262. In FIG. 14, the gate electrode and the drain terminal are connected. However, the present invention is not limited to this, and any element that functions as a resistor may be used. Substitutions are possible.

[0259] In addition, the transistor 260 that functions as a switching element has a gate electrode connected to a bit line. The transistor 260 has a potential that is connected to the bit line. The supply of the potential Vdata to the source electrode is controlled.

[0260] When the transistor 260 connected to the bit line is turned on, the potential Vdata and the power supply potential V dd is obtained by resistively dividing the voltage Vdd by transistors 260 and 261. The potential is applied to the non-inverting input terminal (+) of the operational amplifier 262. Since the level of d is fixed, the level of the potential obtained by resistive division is the potential Vd This reflects the ATA level, i.e., the digital value of the data read.

[0261] On the other hand, the inverting input terminal (-) of the operational amplifier 262 is supplied with a reference potential Vref. And the potential applied to the non-inverting input terminal (+) is higher than the reference potential Vref. Depending on whether the output terminal potential Vout is low or high, the level of the output terminal potential Vout can be made different. It is possible to indirectly obtain a signal containing data.

[0262] Note that even if the same data value is stored in memory cells, there may be variations in the characteristics between the memory cells. Due to the variation, the level of the read potential Vdata also varies, and the distribution becomes wider. Therefore, the level of the reference potential Vref is important for reading the data value accurately. In order to achieve this, the variation in the node potential Vdata is taken into consideration.

[0263] Also, since FIG. 14 shows an example of a read circuit that handles binary digital values, The operational amplifiers used to read the data are connected to the nodes to which the potential Vdata is applied. However, the number of operational amplifiers is not limited to this. When dealing with data, the number of operational amplifiers for the node to which the potential Vdata is applied is n- Let's say it's 1.

[0264] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0265] (Embodiment 6) The mobility of insulated gate transistors that are actually measured, not limited to oxide semiconductors, varies The mobility is lower than it should be for various reasons. There are internal defects and defects at the interface between the semiconductor and the insulating film, but the Levinson model is used. If we assume that there are no defects inside the semiconductor, we can theoretically derive the mobility. In the embodiment, the mobility of an ideal oxide semiconductor without defects inside the semiconductor is theoretically derived. The researchers also demonstrated the characteristics of miniaturized transistors fabricated using such oxide semiconductors. The results of the calculations are shown below.

[0266] The inherent mobility of the semiconductor is μ0, the measured mobility is μ, and if there is some potential in the semiconductor, Assuming the existence of barriers (such as grain boundaries), the mobility μ can be expressed by the following Equation 2.

[0267]

number

[0268] Here, E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. Also, if we assume that the potential barrier originates from defects, in the Levinson model, The following equation 3 holds true.

[0269]

number

[0270] Here, e is the elementary charge, N is the average defect density per unit area in the channel formation region, and ε is the half The dielectric constant of the conductor, n is the number of carriers contained in the channel formation region per unit area, C ox teeth Capacitance per unit area, V g is the gate voltage, and t is the thickness of the channel formation region. If the semiconductor film is 30 nm or less thick, the thickness of the channel formation region is the same as the thickness of the semiconductor film. The drain current in the linear region I d can be expressed by the following Equation 4.

[0271]

number

[0272] L is the channel length, W is the channel width, and here, L=W=10 μm. d is the drain voltage. g Dividing by and taking the logarithm of both sides gives us the following equation: 5 is obtained.

[0273]

number

[0274] The right hand side of Equation 5 is V g As can be seen from Equation 5, the vertical axis is a function of ln(I d / V g ) , the horizontal axis is 1 / V g The defect density is calculated from the slope of the line obtained by plotting the measured values ​​as N is calculated. That is, the I d -V g From the characteristics, the defect density can be evaluated. The ratio of indium (In), tin (Sn), and zinc (Zn) in oxide semiconductors is: In the case of In:Sn:Zn=1:1:1, the defect density N is 1×10 12 / cm 2 About .

[0275] Based on the defect density thus obtained, equations 2 and 3 are used to calculate μ0 = 120 cm 2 / Vs The mobility measured in the defective In-Sn-Zn oxide system is 35 cm 2 / However, the oxide film without defects in the semiconductor and at the interface between the semiconductor and the insulating film The semiconductor mobility μ0 is 120 cm 2 It can be expected that / Vs.

[0276] However, even if there are no defects inside the semiconductor, there is a possibility that the diffusion of the semiconductor at the interface between the channel formation region and the gate insulating film may occur. The transport properties of the transistor are affected by the disturbances in the x direction from the gate insulating film interface. The mobility μ1 at a distance of 100 nm can be expressed by the following equation 6.

[0277]

number

[0278] D is the electric field in the gate direction, and B and G are constants. B and G are determined from actual measurement results. From the above measurement results, B = 4.75 × 10 7 cm / s, G=10nm (field As D increases (i.e., gate voltage V g becomes higher), and the formula It can be seen that the mobility μ1 decreases because the second term of Eq. 6 increases.

[0279] A transistor that uses an ideal oxide semiconductor with no internal defects in the channel formation region The results of the calculation of the mobility μ2 of the MOSFET are shown in Figure 18. The calculation was performed using a Synopsys device simulator. Using the simulation software Sentaurus Device, The band gap, electron affinity, dielectric constant, and thickness are 2.8 eV and 4.7 eV, respectively. These values ​​are for thin films formed by sputtering. This was obtained by measuring the

[0280] In addition, the work functions of the gate electrode, source electrode, and drain electrode are set to 5.5 eV. The gate insulating film thickness was 100 nm. The channel length L and width W were both 10 μm, and the drain Input voltage V d is 0.1V.

[0281] As shown in Figure 18, the gate voltage V g is just over 1V and the mobility μ2 is 100cm 2 / Vs or later The peak is set at the gate voltage V g If the temperature is further increased, the interface scattering becomes large and the In order to reduce the interface scattering, the surface of the semiconductor film is treated at the atomic level. Atomic Layer Flatness is desirable.

[0282] When a miniature transistor is manufactured using an oxide semiconductor having such mobility, The results of calculating the electrical characteristics are shown in FIG. 19 to FIG. 21. The cross-sectional structure of the transistor shown in FIG. + The conductivity type of The semiconductor region 8103a and the semiconductor region 8103c are formed of a semiconductor material. a and the resistivity of semiconductor region 8103c is 2×10 -3 Let it be Ωcm.

[0283] The transistor shown in FIG. 22A includes a base insulating film 8101 and a A buried insulating material 8102 made of aluminum oxide is formed on the buried insulating material 8102. The transistor is made up of a semiconductor region 8103a, a semiconductor region 8103c, and a semiconductor region 8103c sandwiched between them. The semiconductor device has an intrinsic semiconductor region 8103b which becomes a channel forming region and a gate electrode 8105. do.

[0284] Between the gate electrode 8105 and the semiconductor region 8103b, a gate insulating film 8104 is provided. In addition, the gate electrode 8105 is provided on both sides with a sidewall insulator 8106a and a sidewall insulator 8106b. In order to prevent a short circuit between the gate electrode 8105 and other wiring, The width of the sidewall insulator is set to 5 nm. A source electrode 8108a and a drain electrode 8103b are disposed in contact with the semiconductor region 8103a and the semiconductor region 8103c. The channel width of this transistor is 40 nm.

[0285] The transistor shown in FIG. 22B is made of a base insulating film 8101 and aluminum oxide. A semiconductor region 8103a and a semiconductor region 8103c are formed on the buried insulator 8102. and an intrinsic semiconductor region 8103b sandwiched therebetween, and a gate electrode 8105 having a width of 33 nm. and the gate insulating film 8104, the sidewall insulator 8106a, the sidewall insulator 8106b, and the insulator 8 107 and the source electrode 8108a and the drain electrode 8108b. This is the same as the transistor shown in

[0286] The transistor shown in FIG. 22(A) and the transistor shown in FIG. 22(B) differ in that the sidewall insulation The conductivity type of the semiconductor region under the edge 8106a and the sidewall insulator 8106b. In the transistor shown in A), the sidewall insulators 8106a and 8106b are The semiconductor region is n + The semiconductor regions 8103a and 8103c have the same conductivity type. However, in the transistor shown in FIG. 22B, the intrinsic semiconductor region is 8103b. That is, in the oxide semiconductor film illustrated in FIG. There is an area where the region 8103c) and the gate electrode 8105 do not overlap by a width Loff. This area is called the offset area, and its width Loff is called the offset length. As is clear from the above, the offset length Loff is The width is the same as that of 6b).

[0287] The other parameters used in the calculation are as described above. We used the Sentaurus Device simulation software. Figure 19 shows the The drain current (I d , solid line) and mobility (μ, dotted line) gate voltage (V g The drain voltage dependence is shown. Flow I d The drain voltage (potential difference between the drain and source) is +1V, and the mobility μ is The calculations were made assuming a voltage of +0.1V.

[0288] In FIG. 19(A), the thickness t of the gate insulating film is set to 15 nm, and in FIG. 19(B), In FIG. 19(C), t is set to 10 nm, and in FIG. 19(C), t is set to 5 nm. As the thickness t of the d (Off current) is significantly reduced On the other hand, the peak value of the mobility μ and the drain current I d (ON current) is not noticeable At a gate voltage of around 1V, the drain current is 1V, which is the current required for memory cells, etc. It was shown to exceed 0 μA.

[0289] FIG. 20 shows a transistor having the structure shown in FIG. 22(B), with the offset length Loff set to 5n m, the drain current I d (solid line) and mobility μ (dotted line) vs. gate voltage V g dependence The drain current I d The drain voltage is +1V, and the mobility μ is The calculation was done with +0.1V. Figure 20(A) shows the gate insulating film thickness t of 15 nm. In FIG. 20(B), t is set to 10 nm, and in FIG. 20(C), t is set to The thickness was set at 5 nm.

[0290] FIG. 21 shows the offset length Loff The drain current I d (solid line) and mobility μ (dotted line) The drain current I d The drain voltage is +1V, and the mobility μ is the drain voltage The calculation was performed with a voltage of +0.1 V. nm, FIG. 21(B) shows t=10 nm, and FIG. 21(C) shows t is set to 5 nm.

[0291] In both cases, the thinner the gate insulating film, the more significantly the off-state current decreases, while the peak of the mobility μ There is no noticeable change in the on-state current or the on-state voltage.

[0292] In addition, the peak of the mobility μ is 80 cm in FIG. 2 / Vs, but in Figure 20, cm 2 / Vs, 40 cm in Figure 21 2 / Vs, the offset length Loff increases. The off-current also has a similar tendency. On the other hand, the on-current also decreases with increasing offset length L It decreases with increasing off, but it is much slower than the decrease in off current. In addition, the gate voltage is about 1V, and the drain current is 1 It was shown to exceed 0 μA.

[0293] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes.

[0294] (Embodiment 7) A transistor that uses an oxide semiconductor containing In, Sn, and Zn as its main components for the channel formation region is The oxide semiconductor film is formed by heating the substrate or by forming the oxide semiconductor film. By performing heat treatment after formation, good characteristics can be obtained. In the present embodiment, the oxide semiconductor In the case where the mobility of a transistor is improved by intentionally heating the substrate after deposition of the semiconductor film This will be described with reference to FIGS.

[0295] Intentionally heating the substrate after forming an oxide semiconductor film mainly composed of In, Sn, and Zn In addition, the mobility of the transistor can be improved. This makes it possible to positively shift the value voltage and make it normally off.

[0296] For example, FIG. 23(A) to FIG. 23(C) show a semiconductor device having a channel length L The oxide semiconductor film has a channel width W of 10 μm and a gate insulating film with a thickness of 100 nm. These are the characteristics of a transistor using an insulating film. d was set to 10V.

[0297] Figure 23(A) shows a sputtering method in which the main components In, Sn, and Zn were deposited on the substrate without intentionally heating it. The mobility is 18 .8cm 2 On the other hand, the substrate was intentionally heated to obtain In, Sn, and Zn. By forming an oxide semiconductor film containing the ZnO component, it is possible to improve the mobility. B) The substrate is heated to 200°C to form an oxide semiconductor film mainly composed of In, Sn, and Zn. The transistor characteristics are shown below. The mobility is 32.2 cm. 2 / Vs is obtained.

[0298] The mobility was improved by forming an oxide semiconductor film mainly composed of In, Sn, and Zn and then performing heat treatment. FIG. 23(C) shows a graph of the structure of a quartz crystal with In, Sn, and Zn as the main components. The oxide semiconductor film was formed by a sputtering method at 200° C. and then subjected to heat treatment at 650° C. The transistor characteristics are shown below. At this time, the mobility is 34.5 cm 2 / Vs is obtained. is.

[0299] By intentionally heating the substrate, moisture is absorbed into the oxide semiconductor film during film formation by a sputtering method. In addition, by performing a heat treatment after the film formation, Even if the oxide semiconductor film is heated, hydrogen, a hydroxyl group, or moisture can be released and removed from the oxide semiconductor film. As described above, the mobility can be improved. It is presumed that this is due not only to the removal of impurities by oxidation, but also to the shortening of interatomic distances due to densification. In addition, impurities are removed from the oxide semiconductor to achieve high purification, thereby crystallizing the oxide semiconductor. Such a highly purified non-single crystal oxide semiconductor can ideally have a capacitance of 100 cm 2 It is estimated that it will be possible to realize a mobility exceeding 1 / Vs.

[0300] Oxygen ions are implanted into an oxide semiconductor whose main components are In, Sn, and Zn, and the oxide is then converted into The hydrogen, hydroxyl groups, or moisture contained in the oxide semiconductor is released, and the heat treatment is performed simultaneously or in conjunction with the heat treatment. The oxide semiconductor may be crystallized by subsequent heat treatment. By the crystallization treatment, a non-single-crystal oxide semiconductor with good crystallinity can be obtained.

[0301] The effect of intentionally heating the substrate during deposition and / or performing a heat treatment after deposition is to reduce migration This not only improves the efficiency but also contributes to making the transistor normally off. The oxide semiconductor film, mainly composed of In, Sn, and Zn, was formed without intentionally heating the plate. The threshold voltage of a transistor with a channel formation region tends to shift negatively. However, when an oxide semiconductor film is used that is formed by intentionally heating a substrate, The negative shift of the threshold voltage is eliminated. In other words, the threshold voltage is The trend is toward normally off. This trend is seen in the comparison of Figures 23(A) and 23(B). It can also be confirmed from.

[0302] The threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. It is possible to obtain a transistor with a composition ratio of In:Sn:Zn=2:1:3. In addition, the atomic ratio of In:Sn:Zn=1:1: In-Sn-Zn based acids with ratios of 1, 2:1:3, 1:2:2, or 20:45:35 By forming an oxide semiconductor film using an oxide target, a polycrystalline or CAAC film can be formed. It becomes easier to achieve.

[0303] The intentional substrate heating temperature or heat treatment temperature is 150° C. or higher, preferably 200° C. or higher. More preferably, the temperature is 400° C. or higher. By forming the film or performing heat treatment at a higher temperature, the transistor can be formed. This makes it possible to achieve a normally-off start.

[0304] In addition, the gate bianode can be formed by intentionally heating the substrate and / or by carrying out heat treatment after the film formation. It can improve the stability against ass-stress. For example, 2MV / cm, 150℃ , and 1 hour application, the drift is less than ±1.5V, preferably 1.0V You can get less than that.

[0305] In fact, Sample 1 was not subjected to heat treatment after the oxide semiconductor film was formed, and Sample 2 was subjected to heat treatment at 650° C. The BT test was performed on the transistor of sample 2 that had been subjected to the above.

[0306] First, the substrate temperature is set to 25°C, and V d is set to 10V, and the V of the transistor g -I d Measurement of characteristics In addition, V d indicates the drain voltage (potential difference between the drain and source). Next, the substrate temperature The temperature is set to 150℃, and V d Next, the electric field applied to the gate insulating film 608 was set to 0.1 V. V so that the strength is 2MV / cm g A voltage of 20 V was applied to the sample and the sample was held there for 1 hour. , V g Next, the substrate temperature was set to 25°C, and V d is set to 10V, and the V of the transistor g -I d This measurement was called the Plus BT test.

[0307] Similarly, first set the substrate temperature to 25°C and V d is set to 10V, and the V of the transistor g -I d characteristics Next, the substrate temperature was set to 150°C, and V d was set to 0.1V. Next, the gate V is set so that the electric field strength applied to the insulating film 608 is −2 MV / cm. g Apply -20V to Then, the V g Next, the substrate temperature was set to 25°C, and V d is set to 10V, and the V of the transistor g -I d This is called the negative BT test. Oink.

[0308] The results of the positive BT test of sample 1 are shown in FIG. 24(A), and the results of the negative BT test are shown in FIG. 24(B). The results of the positive BT test of sample 2 are shown in FIG. 25(A), and the results of the negative BT test are shown in FIG. The results are shown in Figure 25(B).

[0309] The threshold voltage shifts of sample 1 due to the positive BT test and the negative BT test are 1.80V and -0.42V. In addition, the positive BT test and negative BT test of sample 2 The threshold voltage variations due to the BT test were 0.79 V and 0.76 V, respectively. In both samples 1 and 2, the change in threshold voltage before and after the BT test was small, and the signal It is known to be highly reliable.

[0310] The heat treatment can be carried out in an oxygen atmosphere, but it is first necessary to prepare a nitrogen or inert gas or a reducing gas atmosphere. Alternatively, heat treatment may be performed under pressure and then in an oxygen-containing atmosphere. By adding oxygen to the oxide semiconductor after dehydrogenation, the effect of the heat treatment can be further improved. To add oxygen later, oxygen ions can be accelerated by an electric field to form a A method of injecting the film may also be applied.

[0311] Defects due to oxygen vacancies are generated in the oxide semiconductor and at the interface between the oxide semiconductor and the film. However, when excess oxygen is contained in the oxide semiconductor by such heat treatment, It is possible to compensate for the oxygen deficiency that is constantly generated by excess oxygen. is mainly interstitial oxygen, and its oxygen concentration is 1×10 16 / cm 3 More than 2×10 20 / cm 3If the following conditions are met, the material can be included in the oxide semiconductor without causing distortion or the like to the crystal. It is possible.

[0312] In addition, by making the oxide semiconductor contain crystals at least in part through heat treatment, For example, when the composition ratio of In:Sn:Zn=1, a more stable oxide semiconductor film can be obtained. The film was formed by sputtering using a 1:1 target without intentionally heating the substrate. The oxide semiconductor film was found to have a halo by X-ray diffraction (XRD). The oxide semiconductor film thus formed is then heat-treated to crystallize it. The heat treatment temperature can be selected as desired, but for example, by performing heat treatment at 650°C, Clear diffraction peaks can be observed by X-ray diffraction.

[0313] In fact, an XRD analysis of the In-Sn-Zn oxide semiconductor film was carried out. Out-of-Pl The measurements were performed using the ane method.

[0314] Samples A and B were prepared for XRD analysis. The method for preparing material B will be explained.

[0315] A 100 nm thick In-Sn-Zn oxide semiconductor film was formed on a dehydrogenated quartz substrate. The film was formed.

[0316] The In-Sn-Zn oxide semiconductor film was formed by sputtering in an oxygen atmosphere. The film was deposited at 100 W (DC). The target was In:Sn:Zn=1:1:1 [atomic ratio] The In-Sn-Zn oxide target with a thickness of 100 nm was used. The temperature was 200° C. The sample thus prepared was designated as sample A.

[0317] Next, a sample prepared in the same manner as sample A was subjected to a heat treatment at a temperature of 650°C. The heat treatment is first performed in a nitrogen atmosphere for one hour, and then in an oxygen atmosphere without lowering the temperature. The sample was then subjected to an additional heat treatment for 1 hour.

[0318] Figure 28 shows the XRD spectra of sample A and sample B. In sample A, the peaks derived from crystals However, in sample B, 2θ was observed around 35 deg and 37 deg to 38 deg. A peak derived from crystals was observed in g.

[0319] In this way, oxide semiconductors mainly composed of In, Sn, and Zn are intentionally heated during film formation. and / or by subjecting the film to heat treatment after deposition, the characteristics of the transistor can be improved. Cut.

[0320] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. In other words, it has the effect of preventing the oxide semiconductor from being included in the film or removing it from the film. High purification can be achieved by removing hydrogen, an impurity that generates donors in the conductor. This allows the transistor to be normally off, and the oxide semiconductor is highly By purifying the material, the off-state current can be reduced to 1 aA / μm or less. The unit of the off-state current value is the current value per 1 μm of channel width.

[0321] Figure 29 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. In Figure 29, the reciprocal of the substrate temperature during measurement multiplied by 1000 (1000 / T) is plotted horizontally. It is the axis.

[0322] As shown in FIG. 29, when the substrate temperature is 125°C, the off-current is 1 aA / μm (1×10 -18 At 85°C, the off-state current is 100zA / μm (1×10 -19 At room temperature (27°C), the off-state current is 1zA / μm (1×10 -21 A Preferably, the off-state current at 125° C. can be reduced to 0.1 aA or less. / μm(1×10 -19 A / μm) or less, and the off-state current at 85°C is reduced to 10zA / μm ( 1×10 -20 A / μm) or less at room temperature, and the off-state current is reduced to 0.1zA / μm (1×10 -22 These off-state current values ​​can be achieved with Si as a semiconductor film. It is clear that this is extremely low compared to the transistors used in the previous study.

[0323] Note that in order to prevent hydrogen or moisture from entering the oxide semiconductor film during the formation of the film, The leakage of gas and outgassing from the inner walls of the deposition chamber are sufficiently suppressed, and the sputtering gas is highly purified. For example, the sputtering gas should have a dew point of -70°C or less so that moisture is not included in the film. It is preferable to use a gas that does not contain impurities such as hydrogen or moisture. It is preferable to use a target that has been highly purified so as to be free of In. Oxide semiconductors that are mainly composed of Sn and Zn can remove moisture from the film by heat treatment. However, the temperature at which moisture is released is higher than that of oxide semiconductors whose main components are In, Ga, and Zn. Therefore, it is preferable to form a film that does not contain moisture from the beginning.

[0324] In addition, the transistor using Sample B, which was subjected to heat treatment at 650° C. after the formation of the oxide semiconductor film The relationship between the substrate temperature and the electrical characteristics was evaluated.

[0325] The transistor used for the measurement had a channel length L of 3 μm, a channel width W of 10 μm, and Lov is 0 μm and dW is 0 μm. d The voltage was set to 10 V. The substrate temperature was -40°C. The tests were carried out at temperatures of -25°C, 25°C, 75°C, 125°C and 150°C. In the case of a transistor, the width of overlap between the gate electrode and the source and drain electrodes is called Lov, The protrusion of the source electrode and the drain electrode from the oxide semiconductor film is referred to as dW.

[0326] In Figure 26, I d (solid line) and mobility (dotted line) g The dependency is shown in FIG. FIG. 27(B) shows the relationship between the substrate temperature and the threshold voltage, and FIG. 27(C) shows the relationship between the substrate temperature and the mobility.

[0327] From FIG. 27(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The range was 1.09V to -0.23V from -40℃ to 150℃.

[0328] Also, from FIG. 27(B), it can be seen that the higher the substrate temperature, the lower the mobility. The range is -40℃~150℃ and 36cm 2 / Vs~32cm 2 / Vs. Therefore, It can be seen that the fluctuation in electrical characteristics is small within the above-mentioned temperature range.

[0329] The above-mentioned oxide semiconductor mainly composed of In, Sn, and Zn is used as a channel forming region. According to Transistor, the mobility can be increased to 30 cm while keeping the off-current below 1 aA / μm. 2 / V s or more, preferably 40cm 2 / Vs or more, preferably 60cm 2 / Vs or more, It is possible to satisfy the on-current value required for LSI. For example, L / W=33nm / 4 With a gate voltage of 2.7 V and a drain voltage of 1.0 V, the on-state current is 12 μA or more for a 0 nm FET. In addition, the transistor can operate in the temperature range required for It is possible to ensure sufficient electrical characteristics. If such characteristics are available, it is possible to use a silicon semiconductor. Even if transistors made of oxide semiconductors are embedded in an integrated circuit that uses It is possible to realize integrated circuits having new functions without sacrificing performance.

[0330] This embodiment mode can be implemented in appropriate combination with any of the above embodiment modes. EXAMPLES

[0331] In this example, an example of a transistor in which an In-Sn-Zn-based oxide is used for an oxide semiconductor film will be described. This will be explained using FIG. 30 etc.

[0332] Figure 30 shows the top of a coplanar top-gate top-contact transistor. FIG. 30(A) shows a top view of a transistor. FIG. 30B) shows a cross section AB corresponding to the dashed line AB in FIG.

[0333] The transistor shown in FIG. 30B includes a substrate 1100 and a base film provided over the substrate 1100. An insulating film 1102, a protective insulating film 1104 provided around the base insulating film 1102, and a base insulating film A high resistance region 1106a and a low resistance region 1106b are provided on the insulating film 1102 and the protective insulating film 1104. The oxide semiconductor film 1106 has a resistor region 1106b. The oxide semiconductor film 110 is formed by interposing the gate insulating film 1108 therebetween. A gate electrode 1110 is provided so as to overlap with the gate electrode 6, and a gate electrode 1110 is provided so as to contact with the side surface of the gate electrode 1110. A pair of sidewall insulating films 1112 provided in contact with at least the low resistance region 1106b. The electrode 1114, at least the oxide semiconductor film 1106, the gate electrode 1110, and a pair of An interlayer insulating film 1116 is provided to cover the electrode 1114, and a A wiring 1111 is provided so as to be connected to at least one of a pair of electrodes 1114 through the opening. 18 and,

[0334] Although not shown, a protective film is provided to cover the interlayer insulating film 1116 and the wiring 1118. By providing the protective film, the surface conduction of the interlayer insulating film 1116 can be prevented. This can reduce the minute leakage current caused by the above problem, thereby reducing the off-state current of the transistor. It is possible.

[0335] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. EXAMPLES

[0336] In this embodiment, an In-Sn-Zn-based oxide semiconductor different from the above is used for the oxide semiconductor film. Another example of the transistor will be described.

[0337] FIG. 31 is a top view and a cross-sectional view showing the structure of the transistor fabricated in this example. 31(A) is a top view of a transistor. Also, FIG. 31(B) is a dot-chain diagram of FIG. 31(A). FIG. 2 is a cross-sectional view corresponding to line AB.

[0338] The transistor shown in FIG. 31B includes a substrate 600 and a base insulating film provided over the substrate 600. a base insulating film 602, an oxide semiconductor film 606 provided over the base insulating film 602, and an oxide semiconductor film A pair of electrodes 614 in contact with the oxide semiconductor film 606 and a pair of electrodes 614 A gate insulating film 608 is provided, and an oxide semiconductor film 606 is provided with the gate insulating film 608 interposed therebetween. The gate electrode 610 is provided so as to overlap with the gate insulating film 608 and the gate electrode 610. The insulating interlayer 616 is provided to cover the semiconductor substrate 101 and is connected to the semiconductor substrate 101 through an opening provided in the insulating interlayer 616. A wiring 618 connected to the pair of electrodes 614 and a layer insulating film 616 and a layer insulating film 618 are provided to cover the wiring 618. and a protective film 620 .

[0339] The substrate 600 is a glass substrate, the insulating base film 602 is a silicon oxide film, and the oxide The semiconductor film 606 is made of an In-Sn-Zn oxide semiconductor, and the pair of electrodes 614 is made of A tungsten film is used as the gate insulating film 608, a silicon oxide film is used as the gate electrode 610, The interlayer insulating film 616 is a laminated structure of a tantalum nitride film and a tungsten film. The laminated structure of the silicon nitride film and the polyimide film is a titanium film and an aluminum film as the wiring 618. The laminated structure is made up of a tungsten film, a titanium film, and a polyimide film as the protective film 620. were used, respectively.

[0340] In the transistor having the structure shown in FIG. 31A, the gate electrode 610 and the pair of electrodes The width of the overlap with the oxide semiconductor film 606 is referred to as Lov. The protrusion of pole 614 is called dW.

[0341] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. EXAMPLES

[0342] The storage device according to one aspect of the present invention is capable of increasing the recording capacity per unit area without complicating the process. Therefore, the present invention provides a storage device according to an embodiment of the present invention. By using the above, it is possible to manufacture small electronic devices with low production costs or electronic devices with high functionality. can be provided.

[0343] The storage device according to one aspect of the present invention is used in a display device, a notebook personal computer, a recording medium, Image playback devices equipped with a DVD player (typically DVD: Digital Versatile Digital Used for devices that play recording media such as ISC and have a display that can display the images. In addition, an electronic device in which the memory device according to one embodiment of the present invention can be used As containers, mobile phones, portable game consoles, personal digital assistants, electronic books, video cameras, digital still camera, goggle-type display (head-mounted display), navigation Audio playback devices (car audio, digital audio players, etc.), Copiers, fax machines, printers, multifunction printers, automated teller machines (ATMs) ), vending machines, etc. Specific examples of these electronic devices are shown in Figure 32.

[0344] FIG. 32A shows a portable game machine. The portable game machine includes a housing 7031, a housing 7032, a display portion 7033, A display unit 7034, a microphone 7035, a speaker 7036, an operation key 7037, a star The storage device according to one embodiment of the present invention is a portable game machine. The present invention can be used in an integrated circuit for controlling a portable game machine. By using a memory device according to one embodiment of the present invention for an integrated circuit, a small-sized integrated circuit with low cost can be realized. It is possible to provide a portable game machine or a portable game machine having high functionality. The portable game machine shown in FIG. 32A has two display units 7033 and 7034. However, the number of display units that the portable game machine has is not limited to this.

[0345] FIG. 32B shows a mobile phone. The mobile phone includes a housing 7041, a display unit 7042, an audio input unit 7043, The device has a voice output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received in the sensor into an electrical signal, an external image can be captured. The memory device according to one aspect of the present invention can be used in an integrated circuit for controlling the operation of a mobile phone. The memory device according to one embodiment of the present invention can be incorporated in an integrated circuit for controlling the operation of a mobile phone. By using this technology, it is possible to produce small mobile phones with low production costs, or mobile phones with high functionality. can be provided.

[0346] FIG. 32C shows a portable information terminal, which includes a housing 7051, a display unit 7052, and operation keys 7053. The portable information terminal shown in FIG. 32C has a modem built in a housing 7051. The memory device according to one embodiment of the present invention may be an integrated circuit for controlling the operation of a portable information terminal. The present invention can be applied to an integrated circuit for controlling the operation of a portable information terminal. By using the storage device according to the embodiment, a small portable information terminal with low cost can be manufactured. Thus, a highly functional portable information terminal can be provided.

[0347] This embodiment can be implemented in appropriate combination with any of the above embodiment modes. [Explanation of symbols]

[0348] 100 Cell Array 101 Memory Cell 102 Transistor 103 Capacitive element 104 Substrate 105 Semiconductor Film 106 Conductive Film 107 Conductive Film 108 Insulating film 109 Conductive Film 110 Insulating film 111 Conductive film 115 Semiconductor Film 116 Conductive Film 117 Conductive Film 118 Insulating film 119 Conductive Film 120 Insulating film 121 Conductive Film 125 Semiconductor Film 126 Conductive Film 127 Conductive Film 128 Insulating film 129 Conductive Film 130 Insulating film 131 Conductive Film 135 Semiconductor Film 136 Conductive Film 137 Conductive Film 138 Insulating Film 139 Conductive Film 140 Insulating film 141 Conductive Film 200 Cell Array 201 Memory Cell 202 Transistor 202a Transistor 202b Transistor 202c Transistor 202d Transistor 203 Capacitive element 203a Capacitive element 203b Capacitive element 203c Capacitive element 203d Capacitive element 204 Substrate 205a Semiconductor film 205b Semiconductor film 205c Semiconductor film 205d Semiconductor film 206a Conductive film 206b Conductive film 206c conductive film 206d Conductive film 207a Conductive film 207b Conductive film 207c conductive film 207d Conductive film 208 Insulating film 209 Conductive Film 215a Semiconductor film 215b Semiconductor film 215c Semiconductor film 215d Semiconductor film 216a Conductive film 216b Conductive film 216c conductive film 216d Conductive film 217a Conductive film 217b Conductive film 217c Conductive film 217d Conductive film 218 Insulating film 219 Conductive Film 230 Insulating film 231 Conductive Film 232 Insulating film 234 Insulating film 235 Insulating Film 236 Conductive Film 240 Insulating Film 241 Insulating Film 242 Conductive Film 243 Insulating Film 244 Insulating Film 245 Insulating Film 246 Conductive Film 247 Insulating Film 260 Transistors 261 Transistor 262 Operational Amplifier 290 blocks 291 Blocks 300 storage device 301 Cell Array 302 Drive circuit 303 Circuit 304 Word line driver circuit 305 Bit line driver circuit 306 Control Circuit 307 Decoder 308 Level Shifter 309 Buffer 310 Decoder 312 Selector 600 Substrates 602 Undercoat insulating film 604 Pair of electrodes 606 Oxide Semiconductor Film 608 Gate insulating film 610 Gate electrode 614 Pair of Electrodes 616 Interlayer insulating film 618 Wiring 620 Protective film 700 Substrates 701 Insulating film 702 Conductive film 703 Conductive film 704 Gate insulating film 705 Oxide Semiconductor Film 706 Oxide Semiconductor Film 707 Conductive Film 708 Conductive Film 709 Conductive Film 710 Conductive Film 711 Insulating film 712 Transistor 713 Transistor 714 Capacitive element 715 Capacitive element 1100 Substrate 1102 Undercoat insulating film 1104 Protective insulating film 1106a High resistance region 1106b Low resistance region 1106 Oxide semiconductor film 1108 Gate insulating film 1110 Gate electrode 1112 Sidewall insulating film 1114 Pair of electrodes 1116 Interlayer insulating film 1118 Wiring 7031 Case 7032 Case 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Key 7038 Stylus 7041 Case 7042 Display section 7043 Audio input section 7044 Audio output section 7045 Operation key 7046 Light receiving section 7051 Case 7052 Display section 7053 Operation key 8101 Undercoat insulating film 8102 Embedded insulation 8103a Semiconductor area 8103b Semiconductor area 8103c Semiconductor field 8104 Gate insulating film 8105 Gate electrode 8106a Sidewall insulation 8106b Sidewall insulation 8107 Insulation 8108a Source electrode 8108b Drain electrode

Claims

1. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first oxide semiconductor film having a channel formation region of the first transistor; a first conductive film having a region located above the first oxide semiconductor film and functioning as a gate of the first transistor; a second conductive film electrically connected to the first oxide semiconductor film and having a region located above the first oxide semiconductor film; a third conductive film electrically connected to the first oxide semiconductor film and having a region located above the first oxide semiconductor film; a second oxide semiconductor film having a channel formation region of the second transistor; a fourth conductive film having a region located above the second oxide semiconductor film and functioning as a gate of the second transistor; a fifth conductive film having a region located below the first oxide semiconductor film with an insulating film interposed therebetween and electrically connected to the second oxide semiconductor film; a sixth conductive film electrically connected to the second oxide semiconductor film; having a first region of the first conductive film overlapping with the first oxide semiconductor film overlaps with the fifth conductive film with the insulating film interposed therebetween; the first conductive film does not overlap with the fourth conductive film; the first conductive film functions as a first electrode of the capacitor element; the fifth conductive film functions as a second electrode of the capacitor element; Semiconductor device.

2. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first oxide semiconductor film having a channel formation region of the first transistor; a first conductive film having a region located above the first oxide semiconductor film and functioning as a gate of the first transistor; a second conductive film electrically connected to the first oxide semiconductor film and having a region located above the first oxide semiconductor film; a third conductive film electrically connected to the first oxide semiconductor film and having a region located above the first oxide semiconductor film; a second oxide semiconductor film having a channel formation region of the second transistor; a fourth conductive film having a region located above the second oxide semiconductor film and functioning as a gate of the second transistor; a fifth conductive film having a region located below the first oxide semiconductor film with an insulating film interposed therebetween and electrically connected to the second oxide semiconductor film; a sixth conductive film electrically connected to the second oxide semiconductor film; having the fifth conductive film has a region in contact with the insulating film, the sixth conductive film has a region in contact with the insulating film, a first region of the first conductive film overlapping with the first oxide semiconductor film overlaps with the fifth conductive film with the insulating film interposed therebetween; the first conductive film does not overlap with the fourth conductive film; the first conductive film functions as a first electrode of the capacitor element; the fifth conductive film functions as a second electrode of the capacitor element; Semiconductor device.

3. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first oxide semiconductor film having a channel formation region of the first transistor; a first conductive film having a region located above the first oxide semiconductor film and functioning as a gate of the first transistor; a second conductive film electrically connected to the first oxide semiconductor film and having a region located above the first oxide semiconductor film; a third conductive film electrically connected to the first oxide semiconductor film and having a region located above the first oxide semiconductor film; a second oxide semiconductor film having a channel formation region of the second transistor; a fourth conductive film having a region located above the second oxide semiconductor film and functioning as a gate of the second transistor; a fifth conductive film having a region located below the first oxide semiconductor film with an insulating film interposed therebetween and electrically connected to the second oxide semiconductor film; a sixth conductive film electrically connected to the second oxide semiconductor film; having the second conductive film has a region in contact with the first oxide semiconductor film, the third conductive film has a region in contact with the first oxide semiconductor film, a first region of the first conductive film overlapping with the first oxide semiconductor film overlaps with the fifth conductive film with the insulating film interposed therebetween; the first conductive film does not overlap with the fourth conductive film; the first conductive film functions as a first electrode of the capacitor element; the fifth conductive film functions as a second electrode of the capacitor element; Semiconductor device.

4. A semiconductor device including a first transistor, a second transistor, and a capacitor, a first oxide semiconductor film having a channel formation region of the first transistor; a first conductive film having a region located above the first oxide semiconductor film and functioning as a gate of the first transistor; a second conductive film electrically connected to the first oxide semiconductor film and having a region located above the first oxide semiconductor film; a third conductive film electrically connected to the first oxide semiconductor film and having a region located above the first oxide semiconductor film; a second oxide semiconductor film having a channel formation region of the second transistor; a fourth conductive film having a region located above the second oxide semiconductor film and functioning as a gate of the second transistor; a fifth conductive film having a region located below the first oxide semiconductor film with an insulating film interposed therebetween and electrically connected to the second oxide semiconductor film; a sixth conductive film electrically connected to the second oxide semiconductor film; having the second conductive film has a region in contact with the first oxide semiconductor film, the third conductive film has a region in contact with the first oxide semiconductor film, the fifth conductive film has a region in contact with the insulating film, the sixth conductive film has a region in contact with the insulating film, a first region of the first conductive film overlapping with the first oxide semiconductor film overlaps with the fifth conductive film with the insulating film interposed therebetween; the first conductive film does not overlap with the fourth conductive film; the first conductive film functions as a first electrode of the capacitor element; the fifth conductive film functions as a second electrode of the capacitor element; Semiconductor device.

5. In any one of claims 1 to 4, each of the first conductive film to the sixth conductive film contains at least one element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; Semiconductor device.

6. In any one of claims 1 to 5, the second conductive film and the third conductive film are disposed in a layer different from the fifth conductive film and the sixth conductive film; Semiconductor device.

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