Semiconductor device

Abstract

To provide a technique of manufacturing a semiconductor device including a transistor with high performance and high reliability.SOLUTION: A protective conductive film for protecting an oxide semiconductor layer when a wiring layer is formed of a conductive layer is formed between the oxide semiconductor layer and the conductive layer and two-step etching is performed. A first etching step employs an etching method in which the protective conductive film is etched less easily than the conductive layer and the etching selection ratio between the conductive layer and the protective conductive layer is high. A second etching step employs an etching method in which the protective conductive film is etched more easily than the oxide semiconductor layer and the etching selection ratio between the protective conductive film and the oxide semiconductor layer is high.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] In recent years, oxide semiconductors that exhibit semiconducting properties have been attracting attention. The body may be applied to a transistor.

[0003] There are many etching methods for oxide semiconductors that are highly reproducible and can obtain the desired shapes. Among them, the one that contains an oxide semiconductor containing In, Ga, and Zn is In the method for processing a film formed on a semiconductor substrate, an oxide semiconductor layer of a transistor is etched with a halogen-based gas. A technology for matching has been reported (see Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2008-42067 A Summary of the Invention [Problem to be solved by the invention]

[0005] Incidentally, some transistors have a structure in which a wiring layer is provided on a semiconductor layer. However, in the manufacturing process of such a transistor, the conductive layer is etched. The wiring layer is formed. When etching the conductive layer on such a semiconductor layer, halogen is also used. The gas used is

[0006] Therefore, when an oxide semiconductor is used as the semiconductor layer in the above structure, the conductive layer is etched. During etching, the oxide semiconductor layer may be etched at the same time.

[0007] When the oxide semiconductor layer is etched in this manner, the thickness of the oxide semiconductor layer becomes uneven. This causes variations in transistor characteristics and reduces reliability. .

[0008] In a method for manufacturing a semiconductor device including a transistor using an oxide semiconductor, In the etching process, the oxide semiconductor layer located below the conductive layer may be etched. One of the objects of the present invention is to provide a technology for reducing the above-mentioned problems.

[0009] In a method for manufacturing a semiconductor device including a transistor using an oxide semiconductor, Technology to reduce the effect on transistor characteristics caused by thinning of conductor layers One of the objectives is to provide.

[0010] Also, a technique for manufacturing a semiconductor device having a high-performance and highly reliable transistor is provided. One of the objectives of the organization is to [Means for solving the problem]

[0011] In a method for manufacturing a semiconductor device including a structure in which a wiring layer is stacked over an oxide semiconductor layer, The conductive layer is etched to form the wiring layer. When etching the conductive layer, the oxide semiconductor A protective conductive film for protecting the oxide semiconductor layer is formed between the oxide semiconductor layer and the conductive layer.

[0012] The protective conductive film and conductive layer formed on the oxide semiconductor layer are etched in two steps. The two-step etching process is performed in two stages. The first etching is to etch the conductive layer. and a third step of etching the protective conductive film until the underlying oxide semiconductor layer is exposed. The second step is the etching process.

[0013] In the first etching step, the protective conductive film is formed by etching the oxide semiconductor layer and the conductive layer at the same time. To prevent the conductive layer from being etched, the conductive layer is placed on the substrate to function as an etching stopper. On the other hand, in the second etching step, the oxide semiconductor layer The oxide semiconductor layer is etched so that the protective conductive film is removed without any residue in the exposed region. The membrane must be easily broken down.

[0014] Therefore, the first etching step is performed under conditions where the etching selectivity between the conductive layer and the protective conductive film is high. The second etching step is performed under the condition that the etching selectivity between the protective conductive film and the oxide semiconductor layer is The test is carried out under high conditions.

[0015] In this specification, the etching rate of A divided by the etching rate of B is called "A For example, the etching selectivity between the conductive layer and the protective conductive film is defined as the etching selectivity between A and B. The "selectivity ratio" means the value obtained by dividing the etching rate of the conductive layer by the etching rate of the protective conductive film. In this specification, "high etching selectivity" means an etching selectivity of 1 or more. It means that the

[0016] Since the conductive layer has a high etching selectivity with respect to the protective conductive film, even if the protective conductive film is thin, It can function as an etching stopper.

[0017] By making the protective conductive film thinner, the time required to etch the protective conductive film can be shortened. can.

[0018] The first etching is performed using a chlorine-based gas, and the second etching is performed using a chlorine-based gas and a fluorine-based gas. It is preferable to use a mixture of nitrogen-based gases.

[0019] Specifically, the chlorine-based gas may be a mixture of BCl3 and Cl2. An example of a mixed gas of a nitrogen-based gas and a fluorine-based gas is a mixed gas of SF6 and Cl2.

[0020] As a preferred embodiment of the method for manufacturing a semiconductor device disclosed in the present specification, specifically, The configuration will be described below.

[0021] One embodiment of a method for manufacturing a semiconductor device disclosed in this specification is to form a gate electrode layer, A gate insulating film is formed on the gate electrode layer, an oxide semiconductor layer is formed on the gate insulating film, and an oxide semiconductor layer is formed on the gate insulating film. A protective conductive film is formed on the semiconductor layer, a conductive layer is formed on the protective conductive film, and a resist is formed on the conductive layer. A first etching process is performed using a resist mask and a chlorine-based gas. The conductive layer is selectively etched to expose the protective conductive film, and the conductive layer is then Then, a second etching process using a mixture of chlorine-based gas and fluorine-based gas is performed to selectively The protective conductive film is then etched to expose the oxide semiconductor layer and a wiring layer is formed. forming an insulating film on the semiconductor layer, the protective conductive film, and the wiring layer; and The protective conductive film is less easily etched than the conductive layer, and etching selectivity between the conductive layer and the protective conductive film is low. In the second etching step, the protective conductive film is formed thicker than the oxide semiconductor layer. The etching selectivity between the protective conductive film and the oxide semiconductor layer is high. conduct.

[0022] One embodiment of a method for manufacturing a semiconductor device disclosed in this specification includes forming an oxide semiconductor layer, A protective conductive film is formed over the oxide semiconductor layer, a conductive layer is formed over the protective conductive film, and a laser is formed over the conductive layer. A resist mask is formed, and the first etching is performed using a chlorine-based gas through the resist mask. In the process, the conductive layer is selectively etched to expose the protective conductive film, and the resist mask is removed. A second etching step using a mixture of a chlorine-based gas and a fluorine-based gas is performed to remove the selected selectively etching the protective conductive film to expose the oxide semiconductor layer and form a wiring layer; A gate insulating film is formed on the wiring layer, and a gate insulating film is formed in a region overlapping with the oxide semiconductor layer on the gate insulating film. A protective conductive film is etched from the conductive layer in the first etching step. The second etching is performed under conditions in which the etching selectivity between the conductive layer and the protective conductive film is high. In the etching process, the protective conductive film is more easily etched than the oxide semiconductor layer. The etching is performed under conditions where the etching selectivity between the film and the oxide semiconductor layer is high.

[0023] In one embodiment of the method for producing a semiconductor device disclosed in the present specification, for example, The thickness of the insulating layer is preferably equal to or smaller than the thickness of the oxide semiconductor layer.

[0024] In one embodiment of the method for manufacturing a semiconductor device disclosed in the present specification, for example, In the etching step, the etching selectivity between the conductive layer and the protective conductive film is 4 or more, preferably 6 or more. The second etching step is performed such that the etching selectivity between the protective conductive film and the oxide semiconductor layer is 3. It is sufficient that the value is 0 or more, and preferably 45 or more.

[0025] In one embodiment of the method for manufacturing a semiconductor device disclosed in the present specification, for example, the wiring layer is made of a material It is preferable to form a laminate structure having a film containing aluminum as the material.

[0026] In one embodiment of the method for manufacturing a semiconductor device disclosed in the present specification, for example, the wiring layer is It is preferable to form a laminate structure having a titanium film under the film containing aluminum.

[0027] In one embodiment of the method for producing a semiconductor device disclosed in the present specification, for example, It is preferable to form the insulating film using a tungsten film.

[0028] In one embodiment of the method for manufacturing a semiconductor device disclosed in the present specification, for example, The body layer is preferably formed using a film containing indium, gallium, and zinc. Effect of the Invention

[0029] The conductive layer is etched with a high etching selectivity, so that the oxide semiconductor layer is etched. can be reduced.

[0030] The etching process can be precisely controlled, resulting in a thin, normally-on resistant A transistor having an oxide semiconductor layer can be manufactured.

[0031] In addition, the occurrence of variations in the thickness of the oxide semiconductor layer can be reduced, and the transistor lead It is possible to manufacture a semiconductor device having a transistor with high performance and high reliability by suppressing a current flowing through the transistor. It is possible. [Brief description of the drawings]

[0032] [Figure 1] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Diagram 2] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device. [Diagram 3] 1A and 1B are a plan view and a cross-sectional view of a semiconductor device. [Figure 4] FIG. [Diagram 5] 1A to 1C are a cross-sectional view, a top view, and a circuit diagram of a semiconductor device. [Figure 6] FIG. [Figure 7] STEM images described in Example 1. [Figure 8] 4 is a STEM image of a comparative example described in Example 1. [Figure 9] STEM images as described in Example 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and may be modified in any form without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments. In describing the configuration of the invention using the drawings, the same reference numerals are used in different drawings. In addition, when referring to similar items, the same hatch pattern is used and special symbols are added. Also, for convenience, insulating layers may not be shown in the top view.

[0034] In the following explanation, ordinal numbers such as 1st, 2nd, etc. are added for convenience of explanation. This does not limit the number.

[0035] (Embodiment 1) This embodiment describes a method for manufacturing a semiconductor device including a transistor according to one embodiment of the present invention. We will explain about this.

[0036] First, a gate electrode layer 102 is selectively formed over a substrate 100 (see FIG. 1A).

[0037] The substrate 100 may have an insulating surface. For example, a glass substrate or a quartz substrate may be used. plate, semiconductor substrate with an insulating layer on its surface, or stainless steel with an insulating layer on its surface A substrate or the like may be used.

[0038] The gate electrode layer 102 may be formed using a conductive material. A conductive material film may be formed and then processed by photolithography.

[0039] A gate insulating film 104 is formed to cover the gate electrode layer 102, and an oxide film is formed on the gate insulating film 104. Then, a compound semiconductor layer 106 is selectively formed (see FIG. 1(B)).

[0040] The gate insulating film 104 is made of silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide. The insulating film may be formed of silicon carbide or the like, and is preferably formed by a sputtering method. Moisture and hydrogen are removed as much as possible from the gate insulating film 104 in contact with the oxide semiconductor layer 106. It is preferable to remove the insulating film 104. Alternatively, a plurality of layers may be laminated.

[0041] Note that "silicon oxynitride" is a material whose composition contains more oxygen than nitrogen. Preferably, the Rutherford Backscattering Spectroscopy (RBS) is used. ackscattering spectrometry) and hydrogen forward scattering spectrometry (HF When measured using Hydrogen Forward Scattering (S) The composition range is 50 atomic % to 70 atomic % of oxygen, 0.5 atomic % to 15 atomic % of nitrogen, This refers to a material containing silicon in the range of 25 atomic % to 35 atomic %.

[0042] Note that "silicon nitride oxide" refers to a material whose composition contains more nitrogen than oxygen. Preferably, the composition range is as follows, as measured by RBS and HFS: Oxygen is 5 to 30 atomic percent, nitrogen is 20 atomic percent to 55 atomic percent, silicon is 25 atomic percent to 35 atomic percent However, silicon oxynitride or silicon nitride oxide is not included. When the total of the constituent atoms is 100 atomic %, the content ratio of nitrogen, oxygen, and silicon is as above. shall be included within the scope of the

[0043] The gate insulating film 104 is made of aluminum oxide, tantalum oxide, hafnium oxide, or oxide. Yttrium silicate, hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen Doped hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen is added Hafnium aluminate (HfAl x O y (x>0, y>0)), etc. The thickness of the insulating film is preferably not particularly limited, but it is preferable to form the insulating film in such a manner that the thickness of the insulating film is smaller than that of the insulating film. In order to ensure the operation of the transistor, it is desirable to make the thickness thin. For example, When silicon is used, the thickness is 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less. m or less.

[0044] As mentioned above, when the gate insulating film is made thin, the gate leakage caused by the tunnel effect etc. In order to solve the gate leakage problem, the gate insulating film 104 is provided with hafnium oxide. tantalum oxide, yttrium oxide, hafnium silicate (HfSi x O y (x> 0, y>0), nitrogen-doped hafnium silicate (HfSi x O y (x>0, y >0)), nitrogen-doped hafnium aluminate (HfAl x O y (x>0, y>0 It is recommended to use high-k materials such as GaN, GaN, and GaN. By using it for the insulating film 104, it is possible to suppress gate leakage while maintaining electrical characteristics. It is possible to increase the thickness of the film. , silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, etc. Alternatively, the film may have a laminated structure with a film containing the above-mentioned.

[0045] The oxide semiconductor layer 106 is formed of an oxide semiconductor from which impurities such as water and hydrogen are removed. The oxide semiconductor is made so that impurities that act as carrier donors other than the main component of the oxide semiconductor are not included as much as possible. By purifying it to a high level and supplying sufficient oxygen, it becomes intrinsic (i-type) or substantially intrinsic (i-type) The present invention uses a gate insulating film (gate insulating film)-type oxide semiconductor.

[0046] As described above, the oxide semiconductor layer 106 used in the transistor contains impurities such as hydrogen. It is highly purified by sufficiently removing the pollutants and supplying sufficient oxygen. Specifically, the hydrogen concentration in the oxide semiconductor layer 106 is preferably 5×10 19 ato ms / cm 3 Less than 5×10 18 atoms / cm 3 Less than or equal to 5, preferably ×10 17 atoms / cm3 Note that the hydrogen in the oxide semiconductor layer 106 is The concentration is determined by secondary ion mass spectrometry (SIMS). This is measured by spectroscopic analysis. The energy gap caused by oxygen deficiency is eliminated by supplying sufficient oxygen. In the oxide semiconductor layer 106 in which the defect levels are reduced, the carrier concentration is 1×10 12 / cm 3 Less than 1×10 11 / cm 3 Less than 1.45×10 10 / cm 3 For example, the off-current at room temperature (25° C.) (here, unit channel width ( The value per 1 μm is 100 zA (1 zA (zeptoampere) is 1 × 10 -21 A) Below In this way, the i-type (intrinsic) or substantially i-type By using the oxide semiconductor layer 106, a transistor with excellent off-state current characteristics can be obtained. You can get the data.

[0047] The sodium concentration in the oxide semiconductor layer 106 is 5×10 16 atoms / cm 3 below , preferably 1 x 10 16 atoms / cm 3 Less than 1×10, more preferably 15 at oms / cm 3 The lithium concentration in the oxide semiconductor layer 106 is 5×10 15 atoms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 The following applies. The potassium concentration in the oxide semiconductor layer 106 is 5×10 15 atoms / cm 3 The following is preferred: 1×10 15 atoms / cm 3 Note that in the oxide semiconductor layer 106 The sodium, lithium and potassium concentrations of the Alkali metals and alkaline earth metals are harmful to oxide semiconductors. In particular, sodium is an impurity that is highly detrimental to oxide semiconductors. If the insulating film in contact with the electrode is an oxide, Na diffuses into it and + In addition, the oxide semiconductor In the conductor, it breaks the bonds between metal and oxygen or breaks into the bonds. Degradation of transistor characteristics (e.g., normally-on (negative shift of threshold voltage), mobility In addition, it can cause variations in characteristics. This is particularly noticeable when the concentration of hydrogen in the oxide semiconductor is sufficiently low. The hydrogen concentration in the semiconductor is 5×10 19 cm -3 Below, especially 5×10 18 cm -3 Below In some cases, it is highly desirable to have the above-mentioned concentrations of alkali metals.

[0048] Such highly purified oxide semiconductors are extremely sensitive to interface states and interface charges. Therefore, the state of the interface between the gate insulating film 104 and the oxide semiconductor layer 106 (interface state, interface It is important to adjust the charge, etc., so that the The gate insulating film 104 in contact with the oxide semiconductor is preferably of high quality. The term "gate insulating film 104 is of high quality" means that the gate insulating film 104 has a high It contains few defects, has few defect states and interface states that trap electric charges, and does not generate fixed charges. Examples of this include the fact that it is difficult to grow.

[0049] The gate insulating film 104 is formed by, for example, using microwaves (for example, a frequency of 2.45 GHz). Forming the film using high density plasma CVD is preferred because it is dense and can increase the dielectric strength. A highly purified oxide semiconductor layer and a high-quality gate insulating film are formed in close contact with each other. This is because, by using such a material, the interface state density can be reduced and the interface characteristics can be improved.

[0050] Of course, any material that can form a high-quality insulating layer as the gate insulating film 104 can be used. Other film forming methods such as a tar deposition method or a plasma CVD method may also be used.

[0051] The gate insulating film 104 in contact with the oxide semiconductor layer 106 contains Group 13 elements and oxygen. The insulating material may contain an element of Group 13. Insulating materials containing group 13 elements are compatible with oxide semiconductors, and when they are in contact with the oxide semiconductor layer, By using the insulating layer, the state of the interface with the oxide semiconductor layer can be kept good. The insulating film 116 which functions as a protective film for the oxide semiconductor film, which will be described later, is also formed in the same manner. The insulating material may contain a Group 13 element and oxygen.

[0052] Here, the insulating material containing a Group 13 element refers to an insulating material containing one or more Group 13 elements. The insulating material containing a Group 13 element is, for example, gallium oxide, oxide These include aluminum oxide, aluminum gallium oxide, and aluminum gallium oxide. Here, aluminum gallium oxide is a material that has a higher gallium content (atomic percent) than aluminum. Gallium aluminum oxide refers to the material with a high content (atomic percent) of aluminum. This indicates that the gallium content (atomic %) is higher than the amount (atomic %) of gallium.

[0053] For example, when a gate insulating film is formed in contact with an oxide semiconductor layer containing gallium, By using a material containing gallium oxide for the gate insulating film, In addition, the oxide semiconductor layer and the insulating layer containing gallium oxide can be formed in a thin film. By providing the insulating layer in contact with the oxide semiconductor layer, hydrogen pile-up at the interface between the oxide semiconductor layer and the insulating layer can be prevented. In addition, when an element of the same group as the component element of the oxide semiconductor is used for the insulating layer, For example, if a material containing aluminum oxide is used, the same effect can be obtained. It is also effective to form an insulating layer using aluminum oxide. Therefore, the use of this material is advantageous in preventing water from entering the oxide semiconductor layer. This is also preferable in terms of preventing the intrusion of bacteria.

[0054] In addition, the insulating layer in contact with the oxide semiconductor layer 106, for example, the gate insulating film 104, is By heat treatment under atmospheric pressure or oxygen doping, the insulating material is made to have more oxygen than the stoichiometric composition ratio. It is preferable to make the state of oxygen doping a material that does not have oxygen. The term "bulk" clearly means that oxygen is added not only to the surface of the thin film but also to the inside of the thin film. In addition, oxygen doping is done by adding oxygen plasma to the bulk. The oxygen doping includes oxygen plasma doping, which is a method for doping a semiconductor substrate by ion implantation or ion doping. This may be done using the ping method.

[0055] For example, when gallium oxide is used as an insulating layer in contact with the oxide semiconductor layer 106, oxygen By performing heat treatment in an atmosphere or oxygen doping, the composition of gallium oxide is changed to GaO x (x=3+α, 0<α<1). When aluminum oxide is used as the insulating layer, the heat treatment in an oxygen atmosphere or the oxygen doping By performing the step, the composition of aluminum oxide is changed to AlO x (x=3+α, 0<α<1) Alternatively, a gallium oxide insulating layer can be used as an insulating layer in contact with the oxide semiconductor layer 106. When aluminum (aluminum gallium oxide) is used, heat treatment in an oxygen atmosphere or By doping with oxygen, gallium aluminum oxide (aluminum gallium oxide) ) composition of Ga x Al 2-x O 3+α (0 <x<2、0<α<1)とすることができる。

[0056] By performing oxygen doping treatment, etc., an insulating film having a region with more oxygen than the stoichiometric composition ratio can be obtained. The insulating layer having such a region and the oxide semiconductor layer are in contact with each other. As a result, excess oxygen in the insulating layer is supplied to the oxide semiconductor layer, and the oxide semiconductor layer or reducing oxygen deficiency defects at the interface between the oxide semiconductor layer and the insulating layer, and The hydrogenated oxide semiconductor layer is made into an i-type or nearly i-type oxide semiconductor. It is possible.

[0057] The insulating layer having a region with more oxygen than the stoichiometric composition ratio is the gate insulating film 104. Instead, an insulating film (for example, an insulating film described later) formed as a protective film for the oxide semiconductor layer 106 116, etc.), and the insulating film formed as the gate insulating film 104 and the protective film It may be applied to both.

[0058] The oxide semiconductor used is one that contains at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains In and Zn. As a stabilizer to reduce the variation in the electrical characteristics of transistors In addition, it is preferable to have gallium (Ga). Also, tin (S n) as a stabilizer. It is preferable that the stabilizer is aluminum (Al). It is.

[0059] Other stabilizers include the lanthanides lanthanum (La) and cerium. (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium Eu, Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Luminium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), It may contain one or more of lutetium (Lu).

[0060] The oxide semiconductor layer 106 is made of an oxide semiconductor such as In, which is a quaternary metal oxide. -Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Z n-based oxides, In-Sn-Al-Zn-based oxides, In-Sn-Hf-Zn-based oxides, In -Hf-Al-Zn oxides and ternary metal oxides such as In-Ga-Zn oxides (I Also written as GZO), In-Al-Zn oxide, In-Sn-Zn oxide, Sn- Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-H f-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr -Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu- Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Z n-type oxides, In-Ho-Zn-type oxides, In-Er-Zn-type oxides, In-Tm-Zn In-Yb-Zn oxide, In-Lu-Zn ​​oxide, and binary metal oxide In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, and single-element metal oxides Indium oxide, tin oxide, zinc oxide, etc., which are oxides of In-Ga, can be used. -Zn-based oxide means an oxide having In, Ga, and Zn as the main components. The ratio of In, Ga, and Zn is not important. In addition, metal elements other than In, Ga, and Zn may be included. This is also fine.

[0061] The oxide semiconductor layer 106 is formed of a material having the chemical formula InMO3(ZnO). m (m>0) Here, M is selected from Zn, Ga, Al, Mn and Co. For example, M may be Ga, Ga and Al, Ga and and Mn, or Ga and Co.

[0062] In addition, a thin film of an oxide semiconductor that forms the oxide semiconductor layer 106 is formed by a sputtering method. For example, the composition ratio of the target for this purpose is In2O3:Ga2O3:Zn. Using an oxide semiconductor film deposition target with a molar ratio of In-Ga-Z The material and composition of the target are not limited to those mentioned above, and examples thereof include: , a substrate for oxide semiconductor film formation with In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] In this case, for example, the In-Ga-Zn oxide film is an In It means an oxide film containing indium (In), gallium (Ga), and zinc (Zn). The composition ratio is not particularly important.

[0063] In addition, when using an In-Zn oxide as the oxide semiconductor, the composition of the target to be used The composition ratio, in terms of atomic ratio, is In:Zn=50:1 to 1:2 (converted to a molar ratio of In2O3: ZnO=25:1 to 1:4), preferably In:Zn=20:1 to 1:1 (in terms of molar ratio) In this case, the ratio of In2O3:ZnO is preferably 10:1 to 1:2, and more preferably In:Zn is preferably 15: The ratio is 1 to 1.5:1 (converted into a molar ratio of In2O3:ZnO=15:2 to 3:4). For example, a target used for forming an In-Zn-O based oxide semiconductor has an atomic ratio of In: When Zn:O=X:Y:Z, Z>1.5X+Y.

[0064] In addition, In-Sn-Zn oxide can be called ITZO, and the target used is The composition ratio of In:Sn:Zn is 1:2:2, In:Sn:Zn is 2:1, 3. In:Sn:Zn=1:1:1, or In:Sn:Zn=20:45:35, etc. An oxide target having the following structure is used.

[0065] The thickness of the semiconductor film to be the oxide semiconductor layer 106 is set to 3 nm or more and 30 nm or less. If the semiconductor film to be the oxide semiconductor layer 106 is made too thick (for example, This is because there is a risk that the transistor will become normally on in the case of a device with a gate size of 50 nm or more.

[0066] Here, the semiconductor film that becomes the oxide semiconductor layer 106 is an In-Ga-Zn-O-based oxide. The film is formed in a reduced pressure atmosphere by sputtering using a semiconductor film-forming target.

[0067] The filling rate of the oxide semiconductor film forming target is 90% or more and 100% or less, preferably In this way, the filling rate of the oxide semiconductor film deposition target is 95% or more and 99.9% or less. By using the above-mentioned hot plate, the oxide semiconductor film can be formed into a dense film.

[0068] For example, the oxide semiconductor layer can be formed as follows.

[0069] First, the substrate is held in a film-forming chamber maintained under reduced pressure, and the substrate temperature is kept at 200° C. 500°C or less, preferably more than 300°C or less and 500°C or less, more preferably 350°C or more Heat to below 450°C.

[0070] Next, while removing the remaining moisture in the film formation chamber, impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed. A high-purity gas that has been sufficiently removed is introduced, and an oxide semiconductor layer is formed on a substrate using the target. In order to remove the residual moisture in the deposition chamber, a cryopump is used as an exhaust means. Use an adsorption type vacuum pump such as an ion pump or titanium sublimation pump. It is preferable that the exhaust means is a turbo pump with a cold trap added. The deposition chamber evacuated using a cryopump may be contaminated with, for example, hydrogen, water, hydroxyl radicals, or water. Since impurities such as chlorine and fluorine (and more preferably compounds containing carbon atoms) are removed, Therefore, hydrogen, water, a hydroxyl group, hydride, or the like contained in the oxide semiconductor layer formed in the deposition chamber The concentration of any impurities can be reduced.

[0071] When the substrate temperature during film formation is low (for example, 100°C or lower), hydrogen atoms are added to the oxide semiconductor. It is preferable to heat the substrate at the above-mentioned temperatures, since there is a risk of contamination with substances containing the substrate. The substrate is heated to the above-mentioned temperature to form the oxide semiconductor layer, and the substrate temperature is high. Therefore, the hydrogen bonds are broken by heat, and substances containing hydrogen atoms are incorporated into the oxide semiconductor layer. Therefore, when the oxide semiconductor layer is formed in a state where the substrate is heated to the above-mentioned temperature, By performing the above, impurities such as hydrogen, water, a hydroxyl group, or hydride contained in the oxide semiconductor layer can be removed. The concentration of impurities can be sufficiently reduced. The damage can be reduced.

[0072] As an example of the deposition conditions, the distance between the substrate and the target is 60 mm, and the pressure is 0.4 Pa. The direct current (DC) power supply was 0.5 kW, the substrate temperature was 400°C, and the deposition atmosphere was oxygen (oxygen flow rate ratio The atmosphere should be 100%. Note that if a pulsed DC power source is used, the powder particles that are generated during film formation will be This is preferable because it reduces the amount of contamination (also called particles or dust) and reduces the film thickness distribution.

[0073] Before the oxide semiconductor layer was formed by a sputtering method, argon gas was introduced. The oxide semiconductor layer is then deposited on the surface on which the oxide semiconductor layer is to be formed. It is preferable to remove powdery substances (also called particles or dust). This is a method in which a voltage is applied to a substrate, plasma is generated near the substrate, and the surface on the substrate side is modified. Instead of argon, gas such as nitrogen, helium, or oxygen may be used.

[0074] Note that preheating can be performed before the oxide semiconductor layer 106 is formed, so that the oxide semiconductor layer 106 can be dehydrated or It may be dehydrogenated.

[0075] Note that before a semiconductor film to be the oxide semiconductor layer 106 is formed, moisture remaining in a film formation chamber and It is preferable to remove hydrogen sufficiently. Before formation, use an adsorption-type vacuum pump (e.g., cryopump, ion pump, titanium sublimation pump, etc.). It is preferable to use a displacement pump for evacuation.

[0076] The oxide semiconductor layer includes a first crystalline oxide semiconductor layer on the first crystalline oxide semiconductor layer. A stacked structure including a second crystalline oxide semiconductor layer that is thicker than the first crystalline oxide semiconductor layer may be used. The oxide semiconductor layer having a layer structure can be formed by the following method.

[0077] First, a first crystalline oxide semiconductor layer having a thickness of 1 nm to 10 nm is formed on the gate insulating film 104. The first crystalline oxide semiconductor layer is formed by sputtering. The substrate temperature during film formation by sputtering is set to 200°C or higher and 400°C or lower. Then, the chamber atmosphere in which the substrate is placed is set to nitrogen or dry air, and the first heat treatment is performed. The temperature of the heat treatment is 400°C or higher and 750°C or lower.

[0078] Although it depends on the substrate temperature during film formation and the temperature of the first heat treatment, such a heat treatment As a result, crystallization occurs from the film surface, and crystals grow from the surface to the inside of the film, and the c-axis is oriented. The heat treatment causes zinc and oxygen to gather on the surface of the film, resulting in a hexagonal top surface. One or more layers of graphene-type two-dimensional crystals made of zinc and oxygen form on the outermost surface. These grow in the film thickness direction and become stacked. When the temperature of the heat treatment is increased, Crystal growth progresses from the inside to the bottom and then from the inside to the bottom.

[0079] Next, a second oxide semiconductor layer having a thickness of more than 10 nm is formed on the first crystalline oxide semiconductor layer. The second oxide semiconductor layer is formed by a sputtering method. The substrate temperature during film formation is set to 200° C. or higher and 400° C. or lower. By setting the temperature at 400° C. or lower, the first crystalline oxide semiconductor layer is formed on and in contact with the surface of the first crystalline oxide semiconductor layer. Precursors are aligned in the oxide semiconductor layer, and so-called orderliness can be imparted to the oxide semiconductor layer.

[0080] Next, the atmosphere in the chamber in which the substrate is placed is changed to nitrogen or dry air, and a second heating process is performed. The temperature of the heat treatment is 400°C or higher and 750°C or lower. The heat treatment is performed in a nitrogen atmosphere or an oxygen atmosphere to form a second crystalline oxide semiconductor layer. The second crystalline oxide semiconductor layer is formed by performing the deposition under an atmosphere of nitrogen or a mixed atmosphere of nitrogen and oxygen. The second heat treatment increases the density of the first crystalline oxide semiconductor and reduces the number of defects. The conductor layer acts as a nucleus and crystal growth proceeds in the film thickness direction, i.e., from the bottom to the inside, to form a second crystalline oxide. A semiconductor layer is formed.

[0081] In addition, the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer obtained by the above manufacturing method One of the features of the oxide semiconductor layer is that it has a c-axis orientation. The crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer are crystals having a c-axis orientation (C Axis Aligned Crystal (CAAC) containing oxides Note that the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer are partially fused. It has grain boundaries.

[0082] In a broad sense, oxides containing CAAC are non-single crystals that are perpendicular to the ab plane. When viewed from the outside, the atomic arrangement is a triangle, a hexagon, an equilateral triangle, or an equilateral hexagon, and the c-axis direction is perpendicular to the When viewed from any direction, it contains a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. This refers to oxides.

[0083] CAAC is not a single crystal, but it is not composed of only amorphous matter. AAC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is Sometimes it is not possible to clearly distinguish

[0084] When oxygen is contained in CAAC, a part of the oxygen may be replaced by nitrogen. The c-axes of the individual crystals that make up C are aligned in a certain direction (e.g., the substrate surface supporting the CAAC, The CAAC may be aligned in a direction perpendicular to the surface of the CAAC. The normal of the ab plane of each crystal part is in a certain direction (e.g., the substrate plane supporting the CAAC, C) may be oriented in a direction perpendicular to the surface.

[0085] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Also, depending on the composition, it may be transparent or opaque to visible light. Or something like that.

[0086] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from a certain direction, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, Then, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Examples of such crystals include

[0087] The stack of the first crystalline oxide semiconductor layer and the second crystalline oxide semiconductor layer is By using this material in transistors, it is possible to produce transistors with stable electrical characteristics and high reliability. It can be achieved.

[0088] The oxide semiconductor layer is processed by forming a mask of a desired shape on the oxide semiconductor layer. The above-mentioned mask can be used for etching the oxide semiconductor layer. The insulating layer 11 can be formed by using a method such as lithography. Alternatively, the insulating layer 11 can be formed by using an inkjet method. The mask may be formed by any method. Of course, a combination of these may be used. Good too.

[0089] Next, the oxide semiconductor layer 106 is subjected to heat treatment (third heat treatment). The oxide semiconductor layer can be dehydrated or dehydrogenated by heating in an inert atmosphere. The temperature of the heat treatment is 250° C. or higher and 700° C. or lower, preferably 450° C. or higher and 60° C. or lower. The temperature is set to 0° C. or lower. It is preferable that the temperature is set to be lower than the distortion point of the substrate. The heat treatment is performed at 450°C for 1 hour in a nitrogen atmosphere. The timing is not limited to this as long as it is after the oxide semiconductor layer 106 is formed. The atmosphere in which the heat treatment is performed is not limited to a nitrogen atmosphere, but may be a mixed gas of oxygen gas and nitrogen gas. The atmosphere may be oxygen atmosphere, or air from which moisture has been sufficiently removed (Dry Air After the heat treatment, the oxide semiconductor layer 106 is prevented from being exposed to air, for example. It is preferable to prevent re-incorporation of hydrogen.

[0090] Further, the oxide semiconductor layer that has been subjected to the third heat treatment may be subjected to a fourth heat treatment. The heat treatment in step 4 is performed in an oxidizing atmosphere to supply oxygen to the oxide semiconductor layer. The third heat treatment is performed to fill oxygen vacancies in the oxide semiconductor layer. For this reason, the fourth heat treatment can also be called an oxygen-adding treatment. For example, the temperature may be 200° C. or higher and lower than the distortion point of the substrate. The treatment time is 3 minutes to 24 hours. The longer the treatment time, the more the amorphous region is damaged. However, when the oxide semiconductor layer is heated for more than 24 hours, Such processing is undesirable because it reduces productivity.

[0091] By performing such heat treatment, an oxide semiconductor layer in which impurities are reduced is formed. Thus, a transistor with extremely excellent characteristics can be realized.

[0092] Next, a protective conductive film 107 is formed to cover the gate insulating film 104 and the oxide semiconductor layer 106. Then, a conductive layer 108 that will later become a wiring layer 112 is formed on the protective conductive film 107 (FIG. 1C). )reference).

[0093] The protective conductive film 107 is formed later when the wiring layer 112 is formed by etching the conductive layer 108. The protective conductive film 10 protects the oxide semiconductor layer 106 present below the conductive layer 108. The conductive material for forming the conductive layer 7 is, for example, W or Mo. Examples of the conductive material include Ti, Al, Ta, and nitrides thereof. Note that the conductive layer 108 may be a single layer or a stack of multiple layers. In this embodiment, the conductive layer 108 has a stacked structure of Ti\Al\Ti.

[0094] In addition, when a metal having high oxygen affinity is used for a metal film in contact with the oxide semiconductor layer 106, Therefore, oxygen is easily extracted from the oxide semiconductor layer 106, and the oxide semiconductor layer 106 is changed in quality. There is a risk of this happening.

[0095] Therefore, a metal having low oxygen affinity is used for the metal film in contact with the oxide semiconductor layer 106. In this embodiment, the metal film in contact with the oxide semiconductor layer 106 is preferably a protective conductive film. A W film with a thickness of 107 is used.

[0096] The protective conductive film 107 using W has a higher oxygen affinity than the Ti used as the conductive layer 108. By providing the protective conductive film 107 using W, the oxide semiconductor layer 106 and the Ti film Since the oxide semiconductor layer 106 is not easily extracted with the oxide semiconductor layer 106, the oxide semiconductor layer 106 is not easily extracted with the oxide semiconductor layer 106. Therefore, the contact interface between the W film and the oxide semiconductor layer 106 is unlikely to deteriorate. The substantial thickness reduction of the oxide semiconductor layer 106 caused by the deterioration of a part of the oxide semiconductor layer 106 is reduced. It is possible.

[0097] Next, a resist mask 110 is selectively formed over the conductive layer 108 (see FIG. 1(D)). The resist mask 110 may be formed by photolithography.

[0098] Next, the conductive layer 108 and the protective conductive film 107 are etched using the resist mask 110. Etching is performed to form the wiring layer 112 and the conductive layer 114. The etching process for forming the conductive layer 114 is performed by over-etching the oxide semiconductor. In order to minimize the thickness loss of the layer 106, etching is performed in two stages.

[0099] First, the conductive layer 108 is formed using a resist mask 110 until the protective conductive film 107 is exposed. The conductive layer 108 is selectively etched (first etching step). The wiring layer 112 is formed by arranging at least the source electrode of the transistor. and the drain electrode (see FIG. 1(E)).

[0100] In the first etching step, the protective conductive film 107 is etched away from the conductive layer 108. The etching is performed under conditions where the etching selectivity between the conductive layer 108 and the protective conductive film 107 is high. For example, a chlorine-based gas can be used as the etching gas. Examples of the fluorine-containing compound include CCl4, SiCl4, BCl3, and Cl2. Particularly preferred is BC A mixture of I3 and Cl2 gas is used.

[0101] Next, the protective conductive film 107 is selectively etched until the oxide semiconductor layer 106 is exposed. (second etching step). Here, the protective conductive film 107 is etched to leave the conductive layer 1 In the second etching step, the oxide semiconductor layer 10 is removed. In the exposed region of the oxide semiconductor layer 106, the protective conductive film 107 is removed without leaving any residue. It is preferred that 6 is not etched.

[0102] Note that in the second etching step, the protective conductive film 107 is etched more thoroughly than the oxide semiconductor layer 106. The etching selectivity between the protective conductive film 107 and the oxide semiconductor layer 106 is high. For example, a mixture of chlorine and fluorine gases is used as the etching gas. Here, the mixed gas of a chlorine-based gas and a fluorine-based gas is particularly preferably uses a mixture of SF6 and Cl2 gas.

[0103] As described above, due to the effect of the protective conductive film 107, the portion that becomes the channel formation region While maintaining the thickness of the oxide semiconductor layer 106, the wiring layer 112 in the portion that will become the channel formation region is The wiring layer 112 is formed by using such an etching method. As a result, even if the substrate 100 is a large-area substrate, the channel formation region within the substrate surface can be formed. This can reduce variation in the thickness of the oxide semiconductor layer 106 in some areas.

[0104] Then, the resist mask 110 is removed. It is preferable to form an insulating film 116 on the layer. The insulating film 116 is made of silicon oxide, silicon nitride, etc. The insulating film may be formed of silicon oxide, silicon nitride, or the like by a sputtering method. In addition, the insulating film 116 may be made of the same material as the gate insulating film 104. do.

[0105] After the insulating film 116 is formed, a fourth heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or more and 450°C or less, preferably 250°C. For example, heat treatment at 250°C for 1 hour in a nitrogen atmosphere is sufficient. The fourth heat treatment reduces the variation in electrical characteristics of the transistors. In addition, when the insulating film 116 contains oxygen, it is possible to form a dehydrated or dehydrogenated oxide. Oxygen is supplied to the oxide semiconductor layer 106 to compensate for oxygen vacancies in the oxide semiconductor layer 106, thereby forming an i-type An (intrinsic) semiconductor layer or an oxide semiconductor layer that is extremely close to i-type can also be formed.

[0106] In this embodiment, the fourth heat treatment is performed after the insulating film 116 is formed. The timing of the heat treatment is not limited to this. For example, the fourth heat treatment may be performed after the third heat treatment. Alternatively, the third heat treatment may be combined with the fourth heat treatment, or the fourth heat treatment may be combined with the third heat treatment. This may also serve as the third heat treatment.

[0107] The oxide semiconductor layer 106 is highly purified by forming it using the above-described method. The transistor with this structure has a current value in the off state (off-state current value) of at 85°C to less than 10zA / μm, and at 85°C to less than 100zA / μm. In other words, the off-state current can be reduced to near the measurement limit or below. do.

[0108] In one embodiment of the semiconductor device disclosed in the present specification, a high-performance and highly reliable transistor is provided. It is possible to create a data.

[0109] This embodiment mode can be freely combined with other embodiment modes.

[0110] (Embodiment 2) The present invention is not limited to the embodiment shown in the first embodiment. For example, The semiconductor device may have a top gate structure in which a gate electrode layer is disposed on a wiring layer.

[0111] First, a base insulating layer 201 is preferably formed on a substrate 200, and an oxide is deposited on the base insulating layer 201. Then, a nitride semiconductor layer 206 is selectively formed (see FIG. 2(A)).

[0112] The substrate 200 may be the same as the substrate 100 of the first embodiment.

[0113] The base insulating layer 201 is made of the same material and formed as the gate insulating film 104 of the first embodiment. It can be formed by the method.

[0114] The oxide semiconductor layer 206 has the same material and shape as the oxide semiconductor layer 106 of the first embodiment. It can be formed by a forming method.

[0115] Next, a protective conductive film 207 is formed to cover the base insulating layer 201 and the oxide semiconductor layer 206. Then, a conductive layer 208 that will later become a wiring layer 212 is formed on the protective conductive film 207 (FIG. 2(B)). reference).

[0116] The protective conductive film 207 is made of the same material and is formed by the same method as the protective conductive film 107 of the first embodiment. The conductive layer 208 can be formed by the same method as the conductive layer 108 in the first embodiment. In this embodiment, the conductive layer 208 can be formed by the following materials and forming methods. A Ti\Al\Ti layered structure is used.

[0117] In addition, when a metal having a high oxygen affinity is used for a metal film in contact with the oxide semiconductor layer, the oxide semiconductor layer can be easily oxidized. This tends to extract oxygen from the oxide semiconductor layer, which may result in alteration of the oxide semiconductor layer.

[0118] Therefore, it is preferable to use a metal having low oxygen affinity for the metal film in contact with the oxide semiconductor layer. In this embodiment, the metal film in contact with the oxide semiconductor layer is a W film that is a protective conductive film. It is used.

[0119] The protective conductive film using W has a lower oxygen affinity than Ti used as the conductive layer 208. By providing a protective conductive film using W, the oxide semiconductor layer and the Ti film are formed in contact with each other. Therefore, the action of extracting oxygen from the oxide semiconductor layer is weakened, and the W film and the oxide semiconductor layer Therefore, the contact interface between the oxide semiconductor layer and the oxide semiconductor layer is not easily deteriorated. Therefore, the substantial decrease in the thickness of the semiconductor layer can be reduced.

[0120] Next, a resist mask 210 is selectively formed over the conductive layer 208 (see FIG. 2C). The resist mask 210 is formed by photolithography in the same manner as the resist mask 110 of the first embodiment. It can be formed by the Raffin process.

[0121] Next, the conductive layer 208 and the protective conductive film 207 are etched using a resist mask 210. Etching is performed to form the wiring layer 212 and the conductive layer 214. The wiring layer 212 is The wiring layer 212 and the conductive layer 213 form at least the source electrode and the drain electrode of the transistor. The etching process for forming the conductive layer 214 is performed by over-etching the oxide semiconductor. In order to minimize the thickness loss of the layer 206, the etching is performed in two stages.

[0122] First, the conductive layer 208 is formed using a resist mask 210 until the protective conductive film 207 is exposed. is selectively etched (first etching step). This is then bonded to the wiring layer 212 (see FIG. 2(D)).

[0123] In the first etching process, the protective conductive film 207 is etched away from the conductive layer 208. The etching is performed under conditions where the etching selectivity between the conductive layer 208 and the protective conductive film 207 is high. For example, a chlorine-based gas can be used as the etching gas. Examples of the fluorine-containing fluorine-containing compounds include CCl4, SiCl4, BCl3 and Cl2. Particularly preferred are BCl A mixture of 3 and Cl2 is used.

[0124] Next, the protective conductive film 207 is selectively etched until the oxide semiconductor layer 206 is exposed. (second etching step). Here, the protective conductive film 207 is etched to leave the conductive layer 2 In the second etching step, the oxide semiconductor layer 20 In the exposed region of the oxide semiconductor layer 206, the protective conductive film 207 is removed without leaving any residue. It is preferred that 6 is not etched.

[0125] Note that in the second etching step, the protective conductive film 207 is etched more thoroughly than the oxide semiconductor layer 206. The etching selectivity between the protective conductive film 207 and the oxide semiconductor layer 206 is high. For example, a mixture of chlorine and fluorine gases is used as the etching gas. Here, the mixed gas of a chlorine-based gas and a fluorine-based gas is particularly preferably uses a mixture of SF6 and Cl2 gas.

[0126] As described above, due to the effect of the protective conductive film 207, the portion that will become the channel formation region While maintaining the thickness of the oxide semiconductor layer 206, the wiring layer 212 in the portion that will become the channel formation region is The wiring layer 212 is formed by using such an etching method. As a result, even if the substrate 200 is a large-area substrate, the channel formation region within the substrate surface can be formed. This can reduce variations in the thickness of the oxide semiconductor layer 206 in some areas.

[0127] Then, the resist mask 210 is removed. A gate insulating film 204 is formed on the oxide semiconductor layer 206, and a gate electrode layer 20 is formed on the oxide semiconductor layer 206. 2 is selectively formed. Through the above steps, the transistor 220 of this embodiment is completed ( The gate insulating film 204 is the same as the gate insulating film 104 in the first embodiment. The gate electrode layer 202 can be formed by the material and the formation method of the gate electrode layer 202 according to the first embodiment. The insulating layer 104 can be formed using a material and a method similar to those of the gate electrode layer 102 and the like.

[0128] Note that also in this embodiment, the oxide semiconductor layer is highly purified. In the transistor including the oxide semiconductor layer 206, The current value (off-state current value) at 85°C is less than 10zA / μm per 1μm of channel width. It is possible to reduce the measurement to a level of less than 100zA / μm. can reduce the off-state current to near the measurement limit or below.

[0129] In one embodiment of the semiconductor device disclosed in the present specification, a high-performance and highly reliable transistor is provided. It is possible to create a data.

[0130] This embodiment mode can be freely combined with other embodiment modes.

[0131] The present invention is not limited to the embodiments shown in the first and second embodiments, and the gist of the present invention is The embodiment may have a different form without departing from the scope of the present invention.

[0132] (Embodiment 3) In this embodiment, the appearance and cross section of a liquid crystal display panel, which is one embodiment of a semiconductor device, will be described. The liquid crystal display panel shown in FIG. 3 is the same as that shown in the first embodiment. However, the present invention is not limited to this and may be applied to the first or second embodiment. 3A and 3C show a transistor 401. 0, a transistor 4011, and a liquid crystal element 4013 are disposed between a first substrate 4001 and a second substrate 4006 with a sealing material 4005. FIG. 3B) corresponds to a cross-sectional view taken along line MN in FIG. 3A or FIG. 3C.

[0133] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. A sealant 4005 is provided so as to cover the pixel portion 4002. A second substrate 4006 is provided on the driving circuit 4004. The scanning line driver circuit 4004 is a circuit board including a first substrate 4001, a sealant 4005, and a second substrate 4006. 4006, the liquid crystal layer 4008 is sealed. A region other than the region surrounded by the sealant 4005 is provided on a substrate separately prepared. A signal line driver circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on the is.

[0134] The method of connecting the separately formed drive circuit is not particularly limited, and may be a COG method. For example, a wire bonding method or a TAB method can be used. 3C is an example of mounting a signal line driver circuit 4003 by the COG method. This is an example of mounting a signal line driver circuit 4003 by this method.

[0135] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. 3B, the transistor included in the pixel portion 4002 is 4004 and a transistor 4011 included in the scanning line driver circuit 4004. In FIG. 3B, an insulating layer is provided on the transistor 4011 and the transistor 4010. A layer 4041, an insulating layer 4042, and an insulating layer 4021 are provided.

[0136] The transistor 4010 and the transistor 4011 are the same as those in the first embodiment or the second embodiment. In this embodiment, the transistor 40 10. The transistor 4011 is an n-channel transistor.

[0137] In addition, a pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 40. 06. A pixel electrode layer 4030, a counter electrode layer 4031, and a liquid crystal layer 4008 are formed on the liquid crystal layer 4006. The overlapping portion corresponds to a liquid crystal element 4013. The electrode layer 4031 is provided with an insulating layer 4032 and an insulating layer 4033 which function as an alignment film. The liquid crystal layer 4008 is sandwiched between the insulating layers 4032 and 4033 .

[0138] It is to be noted that the first substrate 4001 and the second substrate 4006 may each be a light-transmitting substrate. It can be used with plastics such as polyester film or acrylic resin film, or glass. For example, a material such as a quartz glass or a ceramic material can be used.

[0139] The columnar spacers 4035 are obtained by selectively etching the insulating layer. A cell gap is set to control the distance between the electrode layer 4030 and the counter electrode layer 4031. A spherical spacer may be used. The counter electrode layer 4031 is The transistor 4010 is electrically connected to a common potential line provided on the same substrate. Using the connection portion, the counter electrode layer 4031 is connected to the conductive particles disposed between the pair of substrates. The conductive particles are contained in the sealing material 4005. To have.

[0140] In addition, a liquid crystal that exhibits a blue phase without using an alignment film may be used. In this case, a lateral electric field type liquid crystal is used. For this reason, the electrode arrangement is different from that shown in FIG. 3. For example, the pixel electrodes are arranged on the same insulating layer. The liquid crystal layer is connected to a common electrode layer, and a horizontal electric field is applied to the liquid crystal layer. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the cholesteric phase transitions to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to improve the liquid crystal layer 4008, a liquid crystal composition containing a chiral agent of several weight percent or more is used. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent has a response speed of 1 msec. c or less, it is optically isotropic so no alignment treatment is required, and it has low viewing angle dependency.

[0141] In addition to the transmission type liquid crystal display device, the present invention can also be applied to a semi-transmission type liquid crystal display device.

[0142] In addition, in liquid crystal display devices, a polarizing plate is provided on the outer side (the viewing side) of the substrate, and a colored layer (color In this example, the polarizing plate is placed on the substrate. The laminated structure of the polarizing plate and the colored layer is not limited to the embodiment, and may be any other structure. The thickness may be appropriately set depending on the materials of the light plate and the colored layer and the manufacturing process conditions. A light-shielding film that functions as a black matrix may be provided.

[0143] An insulating layer is provided in contact with an oxide semiconductor layer over the transistor 4011 and the transistor 4010. A protective insulating layer 4042 is formed on and in contact with the insulating layer 4041. In order to reduce the surface unevenness of the transistor, the protective insulating layer 4042 is formed as a planar insulating layer. The insulating layer 4021 may be used to cover the insulating film.

[0144] In addition, an insulating layer 4021 is formed as a planarizing insulating film. Heat-resistant polymers such as imide, acrylic, benzocyclobutene, polyamide, and epoxy. In addition to the above organic materials, low-k materials can be used. ), siloxane resin, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. In addition, by stacking multiple insulating films made of these materials, it is possible to obtain an insulating A layer 4021 may be formed.

[0145] The method for forming the insulating layer 4021 is not particularly limited, and may be a sputtering method, a SOG method, or the like, depending on the material. method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, An IFCOATER or the like can be used. Firing process of the insulating layer 4021 and annealing of the semiconductor layer By combining these functions, a semiconductor device can be manufactured efficiently.

[0146] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. Indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide , Indium Tin Oxide with Titanium Dioxide, Indium Tin Oxide (also called ITO), In Conductive materials with optical transparency such as indium zinc oxide, indium tin oxide doped with silicon oxide, etc. A conductive material can be used. A material consisting of 1 to 10 graphene sheets can also be used. may also be used.

[0147] In addition, a signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel driver circuit 4006 are separately formed. Various signals and potentials are provided to the unit 4002 through an FPC 4018 .

[0148] The connection terminal electrode 4015 is made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013. The terminal electrode 4016 is formed of the transistors 4010 and 4011. It is formed from the same conductive film as the source electrode and the drain electrode.

[0149] The connection terminal electrode 4015 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. The electrodes are electrically connected to each other.

[0150] In FIG. 3, a signal line driver circuit 4003 is formed separately and is mounted on a first substrate 4001. The example shown is implemented as an example, but is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed separately. It may be implemented as follows.

[0151] The liquid crystal display panel described in this embodiment mode is the same as the liquid crystal display panel described in Embodiment Mode 1 or 2. It is made of highly reliable transistors with good thermal characteristics, so it has good quality. It is possible to provide a liquid crystal display panel having the above-mentioned structure.

[0152] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0153] (Embodiment 4) In this embodiment, an example of electronic paper will be described as one mode of a semiconductor device.

[0154] The transistor described in Embodiment 1 or 2 is electrically connected to a switching element. The connected elements may be used to drive electronic ink in electronic paper. The paper is also called an electrophoretic display (electrophoretic display) and has the same readability as paper. In addition, it has the advantage of being able to consume less power and be made thinner and lighter than other display devices. is.

[0155] Electrophoretic displays can take a variety of forms, but generally have a first electrode having a positive charge. The microcapsules containing the negatively charged particles and the second particles are then mixed with a solvent or solute. By applying an electric field to the microcapsules, The particles in the capsule are moved in opposite directions to display only the color of the particles that have gathered on one side. The first particles or the second particles contain a dye, and in the absence of an electric field, The first particles and the second particles are different in color (colorless). (including

[0156] Thus, electrophoretic displays are devices in which materials with high dielectric constants migrate to areas of high electric field. This is a display that utilizes the so-called dielectrophoretic effect.

[0157] The microcapsules dispersed in a solvent are called electronic ink. This electronic ink can be printed on surfaces such as glass, plastic, fabric, and paper. In addition, a color display is possible by using a color filter or particles having a pigment.

[0158] In addition, the above-mentioned microstrip line is appropriately arranged on the active matrix substrate so as to be sandwiched between two electrodes. By arranging multiple black capsules, an active matrix display device is completed, and a microcapsule is By applying an electric field to the capsule, display can be performed. An active matrix substrate obtained by using the transistor of the second aspect can be used. .

[0159] The first particles and the second particles in the microcapsules are made of a conductive material and an insulating material. , semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials, A material selected from the group consisting of magnetochromic materials and magnetophoretic materials, or a composite material of these materials. can be used.

[0160] FIG. 4 shows an active matrix type electronic paper as an example of a semiconductor device. The transistor 581 used in the device may be the transistor shown in embodiment 1 or embodiment 2. It can be manufactured in the same way as a transistor, has good electrical characteristics, and is a highly reliable transistor. .

[0161] The electronic paper in Figure 4 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. and placing the first electrode layer and the second electrode layer between the first electrode layer and the second electrode layer. This is a method of displaying information by creating a potential difference to control the orientation of spherical particles.

[0162] In FIG. 4, transistor 581 is a bottom-gate transistor. The transistor described in Embodiment 1 or 2 can be used.

[0163] The source electrode or drain electrode of the transistor 581 is formed by insulating layers 583 and 585. In the opening formed in the first electrode layer 587, the first electrode layer 587 is in contact with the first electrode layer 587 and is electrically connected to the first electrode layer 587. Between the first electrode layer 587 and the second electrode layer 588, a black region 590a and a white region 59 0b, and a spherical particle 589 filled with liquid is disposed on a pair of substrates 580 and 59. 6, and the periphery of the spherical particle 589 is filled with a filler 595 such as resin. do.

[0164] The first electrode layer 587 corresponds to a pixel electrode, and the second electrode layer 588 corresponds to a common electrode. The second electrode layer 588 is a common potential line provided over the same substrate as the transistor 581. The common connection portion is disposed between the pair of substrates 580 and 596. The second electrode layer 588 and the common potential line can be electrically connected via the conductive particles. Cut.

[0165] Also, instead of the twist ball, an electrophoretic element can be used. The body is a 10μm to 2 cm diameter encapsulating positively charged white particles and negatively charged black particles. Microcapsules with a diameter of about 0.1 μm are used. When an electric field is applied to the microcapsules by the first and second electrode layers, White particles and black particles move in opposite directions, allowing the display to be white or black. The display element that applies this principle is the electrophoretic display element, which is generally called electronic paper. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. It also consumes little power and the display can be seen even in dimly lit places. In addition, even if power is not supplied to the display, the image once displayed can be retained. Therefore, it is necessary to separate a semiconductor device with a display function (simply a display device, or a display device) from the radio wave source. The displayed image is preserved even if the semiconductor device (also called a semiconductor device) is moved away. It becomes possible.

[0166] Through the above steps, an electronic device having the transistor described in Embodiment 1 or 2 can be manufactured. The electronic paper shown in this embodiment can be manufactured using the same method as in Embodiment 1. or a transistor having favorable electrical characteristics and high reliability, which is described in Embodiment 2. Therefore, it is possible to obtain electronic paper with good quality.

[0167] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is Noh.

[0168] (Embodiment 5) In this embodiment, a storage medium (memory element) is shown as an example of a semiconductor device. In this embodiment, a transistor including an oxide semiconductor described in Embodiment 1 and a transistor including an oxide semiconductor or Transistors using other materials are formed on the same substrate.

[0169] FIG. 5 shows an example of the configuration of a semiconductor device. FIG. 5(A) shows a cross section of the semiconductor device. FIG. 5(A) shows the semiconductor device in a plan view. FIG. 5(B) shows the semiconductor device in a plan view. FIG. 5(C) corresponds to a cross section taken along the lines A1-A2 and B1-B2. An example of a circuit diagram when the device is used as a memory element is shown in FIG. 5(A) and FIG. 5(B). The semiconductor device shown in FIG. 1 has a transistor 360 using a first semiconductor material in the lower part. A transistor 362 using a second semiconductor material is provided in the upper portion. The first semiconductor material is a semiconductor material other than an oxide semiconductor, and the second semiconductor material is an oxide semiconductor. Examples of semiconductor materials other than oxide semiconductors include silicon, germanium, silicon, and Silicon germanium, silicon carbide, or gallium arsenide can be used, and single crystal It is preferable to use a semiconductor. Transistors using such semiconductor materials have high speed operation. On the other hand, transistors using oxide semiconductors can be used for a long time due to their characteristics. Allows charge retention.

[0170] The transistor 360 in FIG. 5 is a substrate that includes a semiconductor material (such as silicon). A channel forming region 316 is provided in the channel forming region 300, and The impurity region 320 is formed by arranging the impurity region 320, and the metal compound region 324 is in contact with the impurity region 320. A gate insulating film 308 is provided on the panel forming region 316, and a gate insulating film 308 is provided on the gate insulating film 308. and a gate electrode 310 .

[0171] The substrate 300 containing a semiconductor material may be a single crystal semiconductor substrate such as silicon or silicon carbide, a multi-crystalline semiconductor substrate, or a Applies to crystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI substrates Generally, an "SOI substrate" is a substrate in which a silicon semiconductor layer is provided on an insulating surface. In this specification, however, it refers to a substrate having a material other than silicon on an insulating surface. In other words, the semiconductor layer of the "SOI substrate" is The substrate layer is not limited to a silicon semiconductor layer. In addition, the SOI substrate may be formed using an insulating layer such as a glass substrate. The present invention also includes a structure in which a semiconductor layer is provided on a peripheral substrate via an insulating layer.

[0172] An electrode 326 is connected to a portion of the metal compound region 324 of the transistor 360. Here, the electrode 326 functions as a source electrode or a drain electrode of the transistor 360. In addition, an element isolation insulating layer 306 is provided to surround the transistor 360. An insulating layer 328 is provided to cover the transistor 360. In order to achieve this, the transistor 360 has a structure without a sidewall insulating layer as shown in FIG. On the other hand, if the characteristics of the transistor 360 are important, A sidewall insulating layer is provided on the side of the electrode 310, and an impurity region including a region with a different impurity concentration is formed. An object area 320 may also be provided.

[0173] The transistor 360 can be fabricated using known techniques. For example, silicon, germanium, silicon germanium, silicon carbide, or gallium. The transistor 360 using arsenic or the like has the advantage of being capable of high speed operation. Therefore, by using the transistor as a read transistor, it is possible to read information. The output can be made at high speed.

[0174] After forming the transistor 360, but before forming the transistor 362 and the capacitor element 364 As the first process, the insulating layer 328 is subjected to a CMP process to expose the upper surface of the gate electrode 310. The process for exposing the upper surface of the gate electrode 310 includes etching process in addition to CMP process. However, in order to improve the characteristics of the transistor 362, It is desirable to keep the surface of the insulating layer 328 as flat as possible.

[0175] Next, a conductive layer is formed on the gate electrode 310, the insulating layer 328, etc., and the conductive layer is selectively 5. The semiconductor device shown in FIG. The semiconductor device transistor 362 has a gate electrode 348a and a gate insulating film covering the gate electrode 348a. A gate insulating film 346 and a gate electrode 348a are provided on the gate insulating film 346 so as to overlap the gate electrode 348a. a conductive film electrically connected to the oxide semiconductor layer 344; 341a, a source electrode 342a and a conductive film 341b, and a drain electrode 342b. For details, refer to the description of the transistor in Embodiment 1 or 2. In FIG. 5, the gate insulating film 346 is However, the present invention is not limited to this. At least the gate voltage The electrode 326 is electrically connected to the conductive film 341a and the source electrode 342a. 3, and the gate electrode 310 is electrically connected to the conductive film 341b and the drain electrode 342b. It is sufficient to provide the circuit so that the signal is connected to the

[0176] In the semiconductor device shown in FIG. 5, an insulating layer 357 is provided over the transistor 362. A conductive layer is formed on the insulating layer 357 so as to at least partially overlap the drain electrode 342b. That is, the conductive layer 358 functions as one electrode of the capacitor 364. Here, the insulating layer 357 can be formed of the same material as the gate insulating film 346. The conductive layer 358 can be formed of the same material as the gate electrode 348a.

[0177] In addition, an insulating layer 350 is provided on the insulating layer 357 and the conductive layer 358. A wiring 354 is provided on the insulating layer 350. The wiring 354 is connected to a gate insulating film 346, The source electrode 342a is connected to the insulating layer 350 through an opening formed therein. The wiring 354 overlaps with at least part of the oxide semiconductor layer 344 of the transistor 362. It is provided so that

[0178] In the semiconductor device shown in FIG. In particular, the source of the transistor 360 is The source region or the drain region is provided so as to partly overlap with the oxide semiconductor layer 344. The wiring 354 is provided so as to overlap at least part of the oxide semiconductor layer 344. In addition, the transistor 362 and the capacitor 364 overlap with the transistor 360. For example, the conductive layer 358 of the capacitor 364 is 60 and the gate electrode 310 at least partially overlapping each other. By adopting this layout, it is possible to achieve high integration of the semiconductor device. For example, When a memory cell is constructed using the semiconductor device, the minimum processing dimension is F, and the memory cell The area occupied by the room is 15F 2 ~25F 2 It is possible to make the following:

[0179] FIG. 5C shows an example of a circuit diagram in which the semiconductor device is used as a memory element. In FIG. 5C, one of a source electrode and a drain electrode of a transistor 362, One electrode of the capacitor 364 and the gate electrode of the transistor 360 are electrically connected. In addition, the first line (also called the source line) and the transistor 3 The source electrode of 60 is electrically connected to the second wiring (2nd Line: bit line). The drain electrode of the transistor 360 is electrically connected to the drain electrode of the transistor 360. The third line (also called the first signal line) and the source voltage of the transistor 362 The other of the first and second electrodes is electrically connected to the first and second wirings (4th Line: The second signal line (also referred to as a second signal line) and the gate electrode of the transistor 362 are electrically connected to each other. A fifth line (also called a word line) and a capacitance element 364 The other electrode is electrically connected.

[0180] The transistor 362 including an oxide semiconductor has an extremely low off-state current. Therefore, by turning off the transistor 362, the source of the transistor 362 One of the source electrode or drain electrode of the capacitor 364 and one of the electrodes of the transistor 36 The potential of the node (hereinafter, node FG) electrically connected to the gate electrode of By including the capacitance element 364, This makes it easier to hold the charge given to node FG, and also makes it easier to read out the held information. It becomes easier.

[0181] When storing (writing) information in the semiconductor device, first, the potential of the fourth wiring is set to The transistor 362 is turned on by applying a potential to the transistor 362. As a result, the potential of the third wiring is supplied to the node FG, and a predetermined amount of charge is stored in the node FG. Here, the charges that give two different potential levels (hereafter, low level) are Either a low level charge or a high level charge is given. After that, the potential of the fourth wiring is set to a potential at which the transistor 362 is turned off. By turning off the capacitor 362, the node FG is in a floating state, so that As described above, a certain amount of charge is stored in the node FG. By storing and holding the charge, information can be stored in the memory cell.

[0182] Since the off-state current of the transistor 362 is extremely small, the charge supplied to the node FG is Therefore, no refresh operation is required or the This makes it possible to reduce the frequency of refresh operations significantly, thereby significantly reducing power consumption. In addition, even if there is no power supply, the memory contents can be maintained for a long period of time. It is possible.

[0183] When reading out the stored information, a predetermined potential (constant potential) is applied to the first wiring. In this state, when an appropriate potential (read potential) is applied to the fifth wiring, the potential is held at the node FG. Depending on the amount of charge applied, transistor 360 assumes different states. If 360 is an n-channel type, when a high-level charge is held at node FG, The apparent threshold voltage V of the transistor 360 th_H A low-level charge is applied to node FG. The apparent threshold voltage V of transistor 360 when th_L Lower Here, the apparent threshold is the threshold voltage at which the transistor 360 is turned on. This refers to the potential of the fifth wiring required for this purpose. Therefore, the potential of the fifth wiring is V t h_H and V th_L By setting the potential V0 between the two, the charge held in node FG is For example, if a high level charge is applied during writing, , the potential of the fifth wire is V0 (> V th_H ), transistor 360 is in the "on state" When a low-level charge is applied, the potential of the fifth wire becomes V0( <V th_L ), transistor 360 remains in the “off state.” The potential of the wiring 5 is controlled to read out the on / off state of the transistor 360 ( The stored data can be read out by reading out the potential of the second wiring.

[0184] In addition, when the stored information is rewritten, a predetermined amount of By supplying a new potential to the node FG that holds the charge, new information is added to the node FG. Specifically, the potential of the fourth wiring is held when the transistor 362 is turned on. The transistor 362 is turned on by applying a potential to the third wiring A potential (a potential related to new information) is supplied to node FG, and a predetermined amount of charge is applied to node FG. After that, the potential of the fourth wiring is set to a potential at which the transistor 362 is turned off. By turning off the transistor 362, the node FG is That is, a predetermined amount of charge is stored in the node FG by the first write. While the charge is held, the same operation as the first write (second write) is performed. It is possible to overwrite the stored information.

[0185] The transistor 362 described in this embodiment is a highly purified and intrinsic oxide semiconductor. By using the layer 344, the off-state current of the transistor 362 can be sufficiently reduced. By using such transistors, memory contents can be retained for an extremely long period of time. Thus, a semiconductor device capable of performing the above-mentioned operations can be obtained.

[0186] In the semiconductor device described in this embodiment, the transistor 360 and the transistor By overlapping the gates 362, a semiconductor device with a sufficiently high integration density is realized.

[0187] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0188] (Embodiment 6) The semiconductor device disclosed in this specification can be applied to various electronic devices (including game machines). The electronic device can be, for example, a television device (television or television (also called digital receivers), computer monitors, digital cameras, digital video cameras, etc. digital photo frames, mobile phones (also called mobile phones or mobile phone devices), These include large game machines such as small game machines, portable information terminals, audio playback devices, and pachinko machines. can be.

[0189] In this embodiment, the electrical characteristics obtained in any one of the above embodiments are excellent and reliable. An example of an electronic device incorporating a highly efficient transistor will be described with reference to FIG.

[0190] FIG. 6A shows a notebook personal computer, which includes a main body 3001 and a housing 300 2, a display unit 3003, a keyboard 3004, etc. The personal computer includes the transistor described in the above embodiment. This makes it possible to realize a notebook type personal computer having good quality and high reliability.

[0191] FIG. 6B shows a portable digital assistant (PDA), which includes a display unit 3023 and a display unit 3024 on a main body 3021. An external interface 3025 and operation buttons 3024 are provided. The Stylus 3022 is an accessory for the . Therefore, the semiconductor device has good quality and high reliability. A personal digital assistant (PDA) will be realized.

[0192] FIG. 6C shows an electronic device manufactured by mounting the electronic paper shown in the above embodiment as one component. FIG. 6C shows an example of an electronic book. For example, electronic book 2700 The device is composed of two housings, a housing 2701 and a housing 2703. The housing 2703 is integrated with a shaft portion 2711 and opens around the shaft portion 2711. This configuration allows the book to be operated like a paper book. This structure also makes it possible to withstand stronger external shocks. In addition, the shaft portion 2711 can be removed to separate the housing 2701 and the housing 2703. It is also possible.

[0193] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 2705 in FIG. 6C) and An image can be displayed on the display portion (the display portion 2707 in FIG. 6C).

[0194] FIG. 6C shows an example in which an operating unit and the like are provided in the housing 2701. For example, The housing 2701 includes a power supply 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. The display may be configured with a keyboard or a pointing device on the front side. On the back or side, there are external connection terminals (earphone terminal, USB terminal, AC adapter and It is equipped with a terminal that can be connected to various cables such as USB cables, a recording medium insertion section, etc. Furthermore, the electronic book 2700 may be configured to function as an electronic dictionary. It may also be composed of.

[0195] The electronic book 2700 may be configured to transmit and receive information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. It is also possible.

[0196] FIG. 6D shows a mobile phone, which is composed of two housings, a housing 2800 and a housing 2801. The housing 2801 includes a display panel 2802, a speaker 2803, a microphone, and the like. 2804, a pointing device 2806, a camera lens 2807, an external connection terminal The housing 2801 also includes a power supply 2808 for charging the portable information terminal. The device is equipped with a solar cell 2810, an external memory slot 2811, etc. Also, the antenna The mobile phone is built in a housing 2801. The stencil includes at least one component.

[0197] The display panel 2802 is equipped with a touch panel, and the image displayed on the display panel 2802 is shown in FIG. The multiple operation keys 2805 are indicated by dotted lines. It also implements a boost circuit to boost the input voltage to the voltage required for each circuit.

[0198] The display direction of the display panel 2802 changes appropriately depending on the usage mode. The camera lens 2807 is located on the same surface as the camera 2802, so video calls are possible. The speaker 2803 and the microphone 2804 are not limited to voice calls, The housing 2800 and the housing 2801 can be slid apart. As shown in Figure 6(D), the device can be folded from the unfolded state to the overlapped state, making it easy to carry. Suitable miniaturization is possible.

[0199] The external connection terminal 2808 can be used to connect to various cables such as an AC adapter and a USB cable. It is possible to charge the battery and to communicate with a personal computer, etc. A recording medium can be inserted into the external memory slot 2811 for storing and transferring a larger amount of data. The semiconductor device described in the embodiment 5 can be used as the recording medium. According to the fifth embodiment, a transistor capable of sufficiently reducing an off-state current is used. Thus, a semiconductor device capable of retaining stored contents for an extremely long period of time can be obtained.

[0200] In addition to the above functions, it also has infrared communication function, TV reception function, etc. Good too.

[0201] FIG. 6E shows a digital camera, which includes a main body 3051, a display unit (A) 3057, and an eyepiece. 3053, an operation switch 3054, a display unit (B) 3055, a battery 3056, etc. Note that the digital camera includes the transistor described in the above embodiment. This results in a high quality and highly reliable digital camera.

[0202] As described above, the electronic device described in this embodiment mode includes the semiconductor device according to the above embodiment. This allows for the realization of electronic devices with good quality. EXAMPLES

[0203] In this example, an example of the transistor in Embodiment 1 is manufactured, and ng Transmission Electron Microscope) In addition, a STEM image of the cross-sectional shape of the transistor was observed.

[0204] In this embodiment, a glass substrate was used as the substrate 100. The gate electrode layer 102 was formed by sputtering. The gate insulating film was formed using a tungsten target in a quartz crystal device, and the thickness was set to 100 nm. The insulating film 104 is formed by using a silicon oxynitride target in a sputtering device, and has a thickness of 1. The oxide semiconductor layer 106 was grown at a pressure of 0.6 Pa and a direct current (DC) power supply of 5 kW. The substrate temperature was 200°C, and the deposition atmosphere was a mixture of argon and oxygen (oxygen:argon = 5 0:50) using a sputtering device with an In-Ga-Zn oxide semiconductor target. The thickness was 100 mm. The protective conductive film 107 was formed by sputtering using a tungsten target. The thickness of the film was 50 nm.

[0205] The conductive layer 108 is made up of a first conductive film 108A, a second conductive film 108B, and a A three-layer laminate structure was formed to form the first conductive film 108B and the third conductive film 108C. The first conductive film 108A is formed of Ti and has a thickness of 100 nm, and the second conductive film 108B is formed of A The third conductive film 108C is formed of Ti and has a thickness of 100 nm. The thickness was set to 100 nm.

[0206] In this embodiment, an ICP (Inductively Coupled Plasma) In this example, a two-stage etching process was carried out using an inductively coupled plasma (ICP) device. The etching for processing the conductive layer to form the conductive layer 108 is performed using a mixed gas of BCl3 and Cl2 ( After the first etching step, the gas type was changed to SF The second etching step was performed using a mixture of 6 and Cl2.

[0207] The conditions for the first etching step were: ICP power 0 W, bias power 1500 W, Pressure: 2.0 Pa, BCl3 and Cl2 gas flow ratio: 750 sccm:150 sccm The etching time was extended by 20 seconds to perform overetching.

[0208] In the first etching step conditions in this embodiment, the etching rate of Ti is 86.10 nm / min, the etching rate of Al is 98.40nm / min, and the etching rate of W is 12 .20nm / min.

[0209] The first conductive layer 108 is a Ti film that is in contact with the protective conductive film 107 of the conductive layer 108 having a laminated structure. The etching selectivity of the film 108A to the protective conductive film 107, which is a W film, is the etching rate of Ti. 86.10nm / min divided by the etching rate of W, 12.20nm / min. So the result is 7.06.

[0210] In the second etching process in this embodiment, the ICP power was 2000 W, the bias power was 0.01 W, and the Power 300W, pressure 1.5Pa, gas flow ratio of SF6 and Cl2 540sccm: The etching time was extended by 15 seconds to perform overetching. In this manner, the transistor of the embodiment was fabricated.

[0211] Under the conditions of this embodiment, the etching rate of W is 98.40 nm / min, and In-Ga-Zn The etching rate of the oxide semiconductor was 2.15 nm / min.

[0212] A protective conductive film 107 made of a W film and an oxide semiconductor made of an In-Ga-Zn oxide semiconductor The etching selectivity of the In-G layer 106 is 98.40 nm / min for W. This is divided by the etching rate of a-Zn-based oxide semiconductor, 2.15 nm / min. The result was 45.77.

[0213] The conductive layer 108 having a laminated structure is processed without providing a protective conductive film 107 below the conductive layer 108. The etching process is performed with a mixture of BCl3 and Cl2 gas (first etching step). The transistors of the embodiment and the comparative example were fabricated. We then observed STEM images of the cross-sectional shapes of each.

[0214] FIG. 7 shows a connection portion between the oxide semiconductor layer 106 and the conductive layer 108 of the transistor of this embodiment. 8 shows a cross-sectional STEM image of the oxide semiconductor layer 106 and the conductive layer 107 of the transistor of the comparative example. A cross-sectional STEM image of the connection point 108 is shown.

[0215] In the transistor of this embodiment, the oxide semiconductor layer 1 in the portion not overlapping with the conductive layer 108 The thickness of the oxide semiconductor layer 106 (hereinafter referred to as the first thickness) and the portion overlapping with the conductive layer 108 The difference between the thickness of the conductive layer 106 (hereinafter referred to as the second thickness) is almost 1 nm. I did. On the other hand, in the comparative transistor, the oxide semiconductor is simultaneously etched when the conductive layer 108 is etched. Since the oxide semiconductor layer 106 was also etched, the first and second thicknesses of the oxide semiconductor layer 106 were The difference in film thickness was about 20 nm.

[0216] From the above results, it is clear that the oxide semiconductor layer 106 provided under the conductive layer 108 is In the present embodiment, the protective conductive film 107 was overetched by about 20 nm. Due to this effect, the oxide semiconductor layer 106 provided under the conductive layer 108 is almost completely etched. As described above, the oxide semiconductor To reduce excessive etching of the conductor layer and unevenness in the thickness of the oxide semiconductor layer. This makes it possible to improve productivity and manufacture transistors with high yield. It can be seen that... EXAMPLES

[0217] In this embodiment, another example that can be used as the condition for the second etching step will be described. The configuration and manufacturing process of the transistor of this embodiment are the same as those of the second etching process. The second etching process conditions in this embodiment are the same as those in Example 1. The ICP power is 2 000W, bias power 300W, pressure 1.5Pa, gas flow rate of SF6 and Cl2 The ratio was 450sccm:630sccm, and the etching time was extended by 15 seconds to overshoot. As a result, the transistor of the embodiment was fabricated and STEM measurements were performed. The transistor of this example was subjected to STEM observation of its cross-sectional shape.

[0218] FIG. 9 shows a connection portion between the oxide semiconductor layer 106 and the conductive layer 108 of the transistor of this embodiment. A cross-sectional STEM image is shown.

[0219] In the transistor manufactured under the conditions of the second etching step of this embodiment, the oxide semiconductor The difference between the first and second film thicknesses of the conductor layer 106 was almost the same, about 1 nm. In the example, the protective conductive film 107 prevents the oxide layer 108 from being exposed to the The semiconductor layer 106 was hardly etched.

[0220] As shown in FIG. 9, the first conductive film 108A, the second conductive film 108B and the third conductive film It can be seen that the ends of the conductive film 108C are almost aligned and have a continuous shape. The first conductive film 108A, the second conductive film 108B, and the third conductive film 108C The first conductive film 108A and the second conductive film 108B have a continuous shape with reduced steps at their ends. Coverage of the films formed on the second conductive film 108B and the third conductive film 108C can be improved.

[0221] As described above, by the method for manufacturing a transistor of this embodiment, an excess edge of an oxide semiconductor layer can be removed. This can reduce variations in the thickness of the oxide semiconductor layer and the semiconductor film. It is clear that this improves the manufacturing efficiency and enables the fabrication of transistors with high yield. In addition, by controlling the etching process, it is possible to process the material into a good shape, so that the This makes it possible to suppress the leakage current of transistors and create high-performance, highly reliable transistors. I realize something. [Explanation of symbols]

[0222] 100 Substrates 102 Gate electrode layer 104 Gate insulating film 106 Oxide semiconductor layer 107 Protective Conductive Film 108 Conductive Layer 108A conductive film 108B Conductive film 108C conductive film 110 Resist mask 112 Wiring layer 114 Conductive layer 116 Insulating film 120 Transistor 200 boards 201 Undercoat insulation layer 202 Gate electrode layer 204 Gate insulating film 206 Oxide semiconductor layer 207 Protective Conductive Film 208 Conductive Layer 210 Resist mask 212 Wiring layer 214 Conductive layer 220 Transistor 300 Substrates 306 Element isolation insulating layer 308 Gate insulating film 310 Gate electrode 316 Channel formation region 320 Impurity region 324 Metal compound area 326 Electrode 328 Insulating Layer 341a Conductive film 341b Conductive film 342a Source electrode 342b Drain electrode 344 Oxide Semiconductor Layer 346 Gate insulating film 348a Gate electrode 350 Insulation layer 354 Wiring 357 Insulating Layer 358 Conductive Layer 360 Transistor 362 Transistor 364 Capacitive element 580 Substrate 581 Transistor 583 Insulating Layer 585 Insulation Layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 595 Filling material 596 Board 2700 e-books 2701 Case 2703 Case 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation key 2725 Speaker 2800 Chassis 2801 Case 2802 Display Panel 2803 Speaker 2804 Microphone 2805 Operation key 2806 Pointing Device 2807 Camera lenses 2808 External connection terminal 2810 Solar Cell 2811 External memory slot 3001 Main unit 3002 Case 3003 Display section 3004 Keyboard 3021 Main unit 3022 Stylus 3023 Display section 3024 Operation button 3025 External Interface 3051 Main unit 3053 Eyepiece 3054 Operation switch 3055 Display section (B) 3056 Battery 3057 Display section (A) 4001 Substrate 4002 Pixel section 4003 Signal line driver circuit 4004 Scanning line driver circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4021 Insulation layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4041 Insulation layer 4042 Insulation layer

Claims

1. A first transistor; A second transistor; and A capacitive element; having one of the source and the drain of the second transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the second transistor is always electrically connected to one of the source and the drain of the first transistor; a semiconductor device in which one electrode of the capacitance element is always electrically connected to a gate of the first transistor, a silicon semiconductor layer having a channel formation region of the first transistor; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate of the first transistor; a first insulating layer having a region disposed above the silicon semiconductor layer; a second conductive layer having a region disposed above the first insulating layer and functioning as a gate of the second transistor; an oxide semiconductor layer having a region located above the second conductive layer and including a channel formation region of the second transistor; a third conductive layer having a region located above the oxide semiconductor layer, functioning as one of a source and a drain of the second transistor and functioning as one electrode of the capacitor; a fourth conductive layer having a region located above the oxide semiconductor layer and functioning as the other of the source and the drain of the second transistor; a fifth conductive layer having a region disposed above the third conductive layer and functioning as the other electrode of the capacitor; having the oxide semiconductor layer does not overlap with the first conductive layer, a channel formation region of the second transistor does not overlap with a channel formation region of the first transistor in a plan view; Semiconductor device.

2. A first transistor; A second transistor; and A capacitive element; having one of the source and the drain of the second transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the second transistor is always electrically connected to one of the source and the drain of the first transistor; a semiconductor device in which one electrode of the capacitance element is always electrically connected to a gate of the first transistor, a silicon semiconductor layer having a channel formation region of the first transistor; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate of the first transistor; a first insulating layer having a region disposed above the silicon semiconductor layer; a second conductive layer having a region disposed above the first insulating layer and functioning as a gate of the second transistor; an oxide semiconductor layer having a region located above the second conductive layer and including a channel formation region of the second transistor; a third conductive layer having a region located above the oxide semiconductor layer, functioning as one of a source and a drain of the second transistor and functioning as one electrode of the capacitor; a fourth conductive layer having a region located above the oxide semiconductor layer and functioning as the other of the source and the drain of the second transistor; a fifth conductive layer having a region disposed above the third conductive layer and functioning as the other electrode of the capacitor; having the fifth conductive layer has an overlap with the first conductive layer; the oxide semiconductor layer does not overlap with the first conductive layer, a channel formation region of the second transistor does not overlap with a channel formation region of the first transistor in a plan view; Semiconductor device.

3. A first transistor; A second transistor; and A capacitive element; having one of the source and the drain of the second transistor is always electrically connected to the gate of the first transistor; the other of the source and the drain of the second transistor is always electrically connected to one of the source and the drain of the first transistor; a semiconductor device in which one electrode of the capacitance element is always electrically connected to a gate of the first transistor, a silicon semiconductor layer having a channel formation region of the first transistor; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate of the first transistor; a first insulating layer having a region disposed above the silicon semiconductor layer; a second conductive layer having a region disposed above the first insulating layer and functioning as a gate of the second transistor; an oxide semiconductor layer having a region located above the second conductive layer and including a channel formation region of the second transistor; a third conductive layer having a region located above the oxide semiconductor layer, functioning as one of a source and a drain of the second transistor and functioning as one electrode of the capacitor; a fourth conductive layer having a region located above the oxide semiconductor layer and functioning as the other of the source and the drain of the second transistor; a fifth conductive layer having a region disposed above the third conductive layer and functioning as the other electrode of the capacitor; having the fifth conductive layer overlaps with a channel formation region of the first transistor; the oxide semiconductor layer does not overlap with the first conductive layer, a channel formation region of the second transistor does not overlap with a channel formation region of the first transistor in a plan view; Semiconductor device.

4. In any one of claims 1 to 3, each of the third conductive layer and the fourth conductive layer includes a first film including titanium and a second film including aluminum disposed above the first film; Semiconductor device.

5. In any one of claims 1 to 4, the oxide semiconductor layer contains In, Ga, and Zn; Semiconductor device.

Images