Data processing apparatus, memory failure determination method, and memory failure determination program

Abstract

To accurately determine the presence or absence of a memory failure.SOLUTION: In a data processing apparatus 11, respective buffer memories BM of a first buffer memory RM1, a second buffer memory MM1, a third buffer memory RM2, and a fourth buffer memory MM2 store therein data formed of a plurality of bits. A CPU 11A reads data from a buffer memory BM, inverts a plurality of bits to generate bit-inverted data resulting from inverting respective values of the plurality of bits, writes the bit-inverted data to the buffer memory BM at a first time, reads the bit-inverted data from the buffer memory BM at a second time later than the first time, and determines the presence or absence of a failure of the buffer memory BM by comparing first data being the bit-inverted data written in the buffer memory BM at the first time with second data being the bit-inverted data read from the buffer memory BM at the second time.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a data processing device, a memory failure determination method, and a memory failure determination program. [Background technology]

[0002] Data (hereinafter sometimes referred to as "detected data") indicating the value detected by the detector (hereinafter sometimes referred to as the "detected value") may be temporarily stored in memory within an FPGA (Field-Programmable Gate Array) possessed by a data processing device connected to the detector. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-191770 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the memory in the FPGA is prone to failure, and when a failure occurs in the memory, accurate detection values ​​may not be presented to the detector operator.

[0005] Therefore, the present disclosure proposes a technique that can accurately determine whether or not a memory has a failure. [Means for solving the problem]

[0006] The data processing device of the present disclosure includes a memory and a processor. The memory stores data formed of a plurality of bits. The processor reads the data from the memory, performs bit inversion on the plurality of bits to generate bit-inverted data after the value of each bit of the plurality of bits is inverted, writes the bit-inverted data to the memory at a first time, and reads the bit-inverted data from the memory at a second time that is later than the first time. The processor then compares first data, which is the bit-inverted data written to the memory at the first time, with second data, which is the bit-inverted data read from the memory at the second time, to determine whether or not the memory is faulty. Effect of the Invention

[0007] According to the present disclosure, the presence or absence of a memory failure can be accurately determined. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating a configuration example of a substance detection system according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram illustrating an example of a configuration of a buffer memory according to an embodiment of the present disclosure. [Diagram 3] FIG. 13 illustrates an example of bit inversion according to an embodiment of the present disclosure. [Figure 4] FIG. 13 illustrates an example of bit inversion according to an embodiment of the present disclosure. [Diagram 5] FIG. 11 is a diagram showing an example of a processing procedure in a substance detection system according to an embodiment of the present disclosure. [Figure 6] FIG. 13 is a diagram illustrating an example of fixed data according to a comparative example of the present disclosure. [Figure 7] FIG. 13 is a diagram illustrating an example of fixed data according to a comparative example of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, the same components or processes are denoted by the same reference numerals, and redundant description may be omitted.

[0010] [Example] <Material detection system configuration> FIG. 1 is a diagram showing a configuration example of a substance detection system according to an embodiment of the present disclosure. In FIG. 1, the substance detection system 1 includes a detection value display device 10 and a detector 20. The detection value display device 10 includes a data processing device 11 and an LCD (Liquid Crystal Display) 12, and the data processing device 11 is connected to the detector 20. The data processing device 11 includes a CPU (Central Processing Unit) 11A and an FPGA 11B. The CPU 11A includes a CPU memory CM. The FPGA 11B includes an A / D conversion unit 11C, a first buffer memory RM1, a second buffer memory MM1, a third buffer memory RM2, and a fourth buffer memory MM2. Hereinafter, the first buffer memory RM1, the second buffer memory MM1, the third buffer memory RM2, and the fourth buffer memory MM2 may be collectively referred to as a "buffer memory BM."

[0011] An example of a substance to be detected by the substance detection system 1 is gas, and an example of the detector 20 is a probe-type gas analyzer. The CPU 11A is an example of a processor. An example of the buffer memory BM is a FIFO (First In First Out) type RAM (Random Access Memory). The LCD 12 is an example of a display.

[0012] The detector 20 detects the absorption spectrum of a reference gas for the first gas (hereinafter sometimes referred to as the "first reference gas") and outputs detection data indicating the value of the absorption spectrum of the first reference gas (hereinafter sometimes referred to as the "first gas reference data") to the A / D conversion unit 11C. The A / D conversion unit 11C converts the analog first gas reference data into digital first gas reference data and writes the digitally converted first gas reference data to the first buffer memory RM1. The digital first gas reference data is formed of multiple bits (e.g., 8 bits).

[0013] Furthermore, detector 20 detects the absorption spectrum of the first gas, and outputs detection data indicating the value of the absorption spectrum of the first gas (hereinafter, sometimes referred to as "first gas detection data") to A / D conversion unit 11C. A / D conversion unit 11C converts the analog first gas detection data into digital first gas detection data, and writes the digitally converted first gas detection data to second buffer memory MM1. The digital first gas detection data is formed of a plurality of bits (e.g., 8 bits).

[0014] Furthermore, the detector 20 detects the absorption spectrum of a reference gas for the second gas (hereinafter sometimes referred to as the "second reference gas") and outputs detection data indicating the value of the absorption spectrum of the second reference gas (hereinafter sometimes referred to as the "second gas reference data") to the A / D conversion unit 11C. The A / D conversion unit 11C converts the analog second gas reference data into digital second gas reference data, and writes the digitally converted second gas reference data to the third buffer memory RM2. The digital second gas reference data is formed of multiple bits (e.g., 8 bits).

[0015] Furthermore, detector 20 detects the absorption spectrum of the second gas, and outputs detection data indicating the value of the absorption spectrum of the second gas (hereinafter sometimes referred to as "second gas detection data") to A / D conversion unit 11C. A / D conversion unit 11C converts the analog second gas detection data into digital second gas detection data, and writes the digitally converted second gas detection data to fourth buffer memory MM2. The digital second gas detection data is formed of a plurality of bits (e.g., 8 bits).

[0016] The CPU 11A reads the first gas reference data from the first buffer memory RM1, and displays the value indicated by the read first gas reference data on the LCD 12. The CPU 11A also performs bit inversion on a plurality of bits forming the first gas reference data read from the first buffer memory RM1, thereby generating data after the values ​​of each of the plurality of bits included in the first gas reference data are inverted (hereinafter, may be referred to as "first reference gas inversion data"). The CPU 11A also writes and stores the first reference gas inversion data in the CPU memory CM at time t11, and writes the first reference gas inversion data to the first buffer memory RM1. Next, at time t12 after time t11, the CPU 11A reads the first reference gas inversion data from the first buffer memory RM1, and reads the first reference gas inversion data from the CPU memory CM. Then, the CPU 11A compares the first reference gas inversion data read from the CPU memory CM at time t12 (i.e., the first reference gas inversion data written to the first buffer memory RM1 at time t11) with the first reference gas inversion data read from the first buffer memory RM1 at time t12 to determine whether or not the first buffer memory RM1 has a failure. The CPU 11A determines that the first buffer memory RM1 has a failure when the value of the first reference gas inversion data written to the first buffer memory RM1 at time t11 is different from the value of the first reference gas inversion data read from the first buffer memory RM1 at time t12, whereas it determines that the first buffer memory RM1 has no failure when the two values ​​are the same. Furthermore, when the CPU 11A determines that the first buffer memory RM1 has a failure, it causes the LCD 12 to display a warning indicating that the first buffer memory RM1 has a failure.

[0017] Furthermore, the CPU 11A reads the first gas detection data from the second buffer memory MM1, and displays a value indicated by the read first gas detection data on the LCD 12. The CPU 11A also performs bit inversion on a plurality of bits forming the first gas detection data read from the second buffer memory MM1, thereby generating data after the values ​​of each of the plurality of bits included in the first gas detection data are inverted (hereinafter, may be referred to as "first gas inversion data"). Furthermore, at time t21, the CPU 11A writes and stores the first gas inversion data in the CPU memory CM, and also writes the first gas inversion data to the second buffer memory MM1. Next, at time t22, which is later than time t21, the CPU 11A reads the first gas inversion data from the second buffer memory MM1, and also reads the first gas inversion data from the CPU memory CM. Then, the CPU 11A compares the first gas inversion data read from the CPU memory CM at time t22 (i.e., the first gas inversion data written to the second buffer memory MM1 at time t21) with the first gas inversion data read from the second buffer memory MM1 at time t22 to determine whether or not the second buffer memory MM1 is faulty. The CPU 11A determines that the second buffer memory MM1 is faulty when the value of the first gas inversion data written to the second buffer memory MM1 at time t21 is different from the value of the first gas inversion data read from the second buffer memory MM1 at time t22, whereas it determines that the second buffer memory MM1 is not faulty when the two values ​​are the same. Furthermore, when the CPU 11A determines that the second buffer memory MM1 is faulty, it causes the LCD 12 to display a warning indicating that the second buffer memory MM1 is faulty.

[0018] Moreover, the CPU 11A reads the second gas reference data from the third buffer memory RM2, and displays the value indicated by the read second gas reference data on the LCD 12. The CPU 11A also performs bit inversion on a plurality of bits forming the second gas reference data read from the third buffer memory RM2, thereby generating data after the values ​​of each of the plurality of bits included in the second gas reference data are inverted (hereinafter, may be referred to as "second reference gas inversion data"). Furthermore, at time t31, the CPU 11A writes and stores the second reference gas inversion data in the CPU memory CM, and also writes the second reference gas inversion data to the third buffer memory RM2. Next, at time t32, which is later than time t31, the CPU 11A reads the second reference gas inversion data from the third buffer memory RM2, and also reads the second reference gas inversion data from the CPU memory CM. Then, the CPU 11A compares the second reference gas inversion data read from the CPU memory CM at time t32 (i.e., the second reference gas inversion data written to the third buffer memory RM2 at time t31) with the second reference gas inversion data read from the third buffer memory RM2 at time t32 to determine whether or not the third buffer memory RM2 has a failure. The CPU 11A determines that the third buffer memory RM2 has a failure when the value of the second reference gas inversion data written to the third buffer memory RM2 at time t31 is different from the value of the second reference gas inversion data read from the third buffer memory RM2 at time t32, whereas it determines that the third buffer memory RM2 has no failure when the two values ​​are the same. Furthermore, when the CPU 11A determines that the third buffer memory RM2 has a failure, it causes the LCD 12 to display a warning indicating that the third buffer memory RM2 has a failure.

[0019] Furthermore, the CPU 11A reads the second gas detection data from the fourth buffer memory MM2, and displays a value indicated by the read second gas detection data on the LCD 12. The CPU 11A also performs bit inversion on a plurality of bits forming the second gas detection data read from the fourth buffer memory MM2, thereby generating data after the values ​​of each of the plurality of bits included in the second gas detection data are inverted (hereinafter, may be referred to as "second gas inversion data"). Furthermore, at time t41, the CPU 11A writes and stores the second gas inversion data in the CPU memory CM, and also writes it to the fourth buffer memory MM2. Next, at time t42, which is later than time t41, the CPU 11A reads the second gas inversion data from the fourth buffer memory MM2, and also reads the second gas inversion data from the CPU memory CM. Then, the CPU 11A compares the second gas inversion data read from the CPU memory CM at time t42 (i.e., the second gas inversion data written to the fourth buffer memory MM2 at time t41) with the second gas inversion data read from the fourth buffer memory MM2 at time t42 to determine whether or not the fourth buffer memory MM2 has a failure. The CPU 11A determines that the fourth buffer memory MM2 has a failure when the value of the second gas inversion data written to the fourth buffer memory MM2 at time t41 is different from the value of the second gas inversion data read from the fourth buffer memory MM2 at time t42, and determines that the fourth buffer memory MM2 has no failure when the two values ​​are the same. Furthermore, when the CPU 11A determines that the fourth buffer memory MM2 has a failure, it causes the LCD 12 to display a warning indicating that the fourth buffer memory MM2 has a failure.

[0020] <Buffer memory configuration> 2 is a diagram illustrating an example of a configuration of a buffer memory according to an embodiment of the present disclosure. As an example, FIG. 2 illustrates a FIFO type buffer memory BM formed of five areas: a first area #1, a second area #2, a third area #3, a fourth area #4, and a fifth area #5.

[0021] In a buffer memory BM as shown in FIG. 2, when the detected data to be displayed on the LCD 12 (hereinafter sometimes referred to as "data to be displayed") is the nth detected data written in the first area #1, the CPU 11A reads the nth detected data written in the first area #1 from the buffer memory BM as the data to be displayed and the detected data to be subjected to bit inversion (hereinafter sometimes referred to as "data to be bit inversion").

[0022] Next, the CPU 11A writes the n-th detection data read from the buffer memory BM to an area #A in the CPU memory CM as data to be displayed.

[0023] In addition, the CPU 11A performs bit inversion on the multiple bits that form the nth detection data read from the buffer memory BM, and writes the bit-inverted data (hereinafter sometimes referred to as the "nth inverted data") to area #B in the CPU memory CM and also to the first area #1 of the buffer memory BM.

[0024] Next, the CPU 11A reads the n-th inverted data from the first area #1 of the buffer memory BM.

[0025] Then, the CPU 11A determines whether or not there is a memory error in the first area #1 of the buffer memory BM by determining whether or not the nth inverted data written to area #B in the CPU memory CM differs from the nth inverted data read from the first area #1 of the buffer memory BM.

[0026] Thereafter, the CPU 11A determines whether or not a memory error occurs for each of the second area #2, the third area #3, the fourth area #4, and the fifth area #5 of the buffer memory BM in the same manner as for the first area #1.

[0027] <Bit inversion> 3 and 4 are diagrams showing an example of bit inversion according to an embodiment of the present disclosure. As shown in Fig. 3, for example, when the (n-1)th detection data is 8-bit data of "00001111", the CPU 11A generates 8-bit (n-1)th inverted data of "11110000" as shown in Fig. 4 by inverting the value of each bit of the multiple bits forming the (n-1)th detection data.

[0028] <Processing Procedure> FIG. 5 is a diagram illustrating an example of a processing procedure in the substance detection system according to the embodiment of the present disclosure.

[0029] In FIG. 5, in step ST1, the detector 20 writes the first gas reference data to the first buffer memory RM1.

[0030] Next, in step ST2, the detector 20 detects the absorption spectrum of the first gas, and writes the first gas detection data to the second buffer memory MM1.

[0031] Next, in step ST3, the detector 20 detects the absorption spectrum of the second gas, and writes the second gas detection data to the fourth buffer memory MM2.

[0032] Next, in step ST4, the CPU 11A determines whether or not there is a failure in the first buffer memory RM1 and the second buffer memory MM1 in the manner described above.

[0033] Next, in step ST5, the detector 20 writes the second gas reference data to the third buffer memory RM2.

[0034] Next, in step ST6, the detector 20 detects the absorption spectrum of the first gas, and writes the first gas detection data to the second buffer memory MM1.

[0035] Next, in step ST7, the detector 20 detects the absorption spectrum of the second gas, and writes the second gas detection data to the fourth buffer memory MM2.

[0036] Next, in step ST8, the CPU 11A determines whether or not there is a failure in the third buffer memory RM2 and the fourth buffer memory MM2 in the manner described above.

[0037] As described above, the CPU 11A determines whether or not the first buffer memory RM1 and the second buffer memory MM1 have a failure in step ST4 immediately after the detector 20 writes the first gas detection data to the second buffer memory MM1 in step ST2 and writes the second gas detection data to the fourth buffer memory MM2 in step ST3. Also, the CPU 11A determines whether or not the third buffer memory RM2 and the fourth buffer memory MM2 have a failure in step ST8 immediately after the detector 20 writes the first gas detection data to the second buffer memory MM1 in step ST6 and writes the second gas detection data to the fourth buffer memory MM2 in step ST7.

[0038] After the process of step ST8, the processes of steps ST1 to ST8 are repeated, with the processes of steps ST1 to ST8 constituting one cycle.

[0039] <Comparative Example> In the above-described embodiment of the present disclosure, in order to determine whether or not there is a fault in the buffer memory BM, data formed from multiple bits was used after the values ​​of each bit were inverted (hereinafter sometimes referred to as "bit-inverted data").

[0040] Here, the types of failures that can occur in the buffer memory BM include a failure in which the bit value becomes stuck at “0” (hereinafter sometimes referred to as a “stuck at 0 failure”), and a failure in which the bit value becomes stuck at “1” (hereinafter sometimes referred to as a “stuck at 1 failure”).

[0041] As in the above embodiment, by writing one bit-inverted data once to one area in the buffer memory BM and reading it once, it is possible to detect both a stuck-at-0 fault and a stuck-at-1 fault in the one area.

[0042] In contrast to this, a comparative example can be considered in which the presence or absence of a fault in the buffer memory BM is determined using data whose bit values ​​are fixed in advance (hereinafter, sometimes referred to as "fixed data") without using bit-inverted data. FIGS. 6 and 7 are diagrams showing an example of fixed data according to the comparative example of the present disclosure. In this comparative example, when first fixed data having an 8-bit value of "10101010" as shown in FIG. 6 is used, second fixed data having an 8-bit value of "01010101" as shown in FIG. 7 in which the values ​​of each bit of the first fixed data are inverted is also required. That is, in order to detect both a stuck-at-0 fault and a stuck-at-1 fault in one area to be determined for faults in the buffer memory BM in the comparative example, it is necessary to write and read the first fixed data once and to write and read the second fixed data once for the one area.

[0043] As described above, by using bit-inverted data to determine whether or not there is a failure in the buffer memory BM, the number of writes and reads to the buffer memory BM can be halved compared to when fixed data is used, and therefore it is possible to efficiently determine whether or not there is a failure in the buffer memory BM.

[0044] The examples and comparative examples of the present disclosure have been described above.

[0045] In the above embodiment, a case has been described as an example in which the substance to be detected by the substance detection system 1 is a gas. However, the technology of the present disclosure can also be applied to cases in which the substance to be detected by the substance detection system 1 is a substance other than a gas.

[0046] In the above embodiment, a case where one detector 20 is connected to one data processing device 11 has been described as an example. However, the technology of the present disclosure can also be applied to a case where multiple detectors 20 are connected to one data processing device 11.

[0047] Also, all or part of each process in the data processing device 11 described above may be realized by having the CPU 11A execute a program corresponding to each process. For example, a program corresponding to each process in the above description may be stored in a memory or storage of the data processing device 11, and the program may be read from the memory or storage by the CPU 11A and executed. Also, the program may be stored in a program server connected to the data processing device 11 via any network, downloaded from the program server to the data processing device 11 and executed, or stored in a recording medium readable by the data processing device 11, read from the recording medium and executed. Examples of recording media readable by the data processing device 11 include portable storage media such as memory cards, USB memories, SD cards, flexible disks, magneto-optical disks, CD-ROMs, and DVDs.

[0048] As described above, the data processing device (data processing device 11 of the embodiment) of the present disclosure includes a memory (buffer memory BM of the embodiment) and a processor (CPU 11A of the embodiment). The memory stores data formed of a plurality of bits. The processor reads the data from the memory and performs bit inversion on the plurality of bits to generate bit-inverted data after the value of each bit of the plurality of bits is inverted. The processor also writes the bit-inverted data to the memory at a first time, and reads the bit-inverted data from the memory at a second time that is later than the first time. The processor then compares the first data, which is the bit-inverted data written to the memory at the first time, with the second data, which is the bit-inverted data read from the memory at the second time, to determine whether or not the memory is faulty.

[0049] For example, the processor determines that there is no fault in the memory when the value of the first data and the value of the second data are identical, and determines that there is a fault in the memory when the value of the first data and the value of the second data are different.

[0050] Furthermore, for example, the data processing device according to the present disclosure includes an FPGA (FPGA 11B in the embodiment) having a memory.

[0051] Also, for example, the data stored in the memory is detection data indicating values ​​detected by a detector connected to the data processing device.

[0052] By doing so, the presence or absence of a memory failure can be accurately determined.

[0053] In addition, some examples of combinations in the techniques of the present disclosure are described below.

[0054] (1) A data processing device comprising: a memory that stores data formed from a plurality of bits; and a processor that reads the data from the memory, performs bit inversion on the plurality of bits to generate bit-inverted data after the values ​​of each bit of the plurality of bits are inverted, writes the bit-inverted data to the memory at a first time, reads the bit-inverted data from the memory at a second time that is later than the first time, and determines whether or not the memory is faulty by comparing first data, which is the bit-inverted data written to the memory at the first time, with second data, which is the bit-inverted data read from the memory at the second time.

[0055] (2) The data processing device described in (1), wherein the processor determines that there is no fault in the memory when the value of the first data and the value of the second data are identical, and determines that there is a fault in the memory when the value of the first data and the value of the second data are different.

[0056] (3) The data processing device according to (1) or (2), comprising an FPGA having the memory.

[0057] (4) A data processing device according to any one of (1) to (3), wherein the data is detection data indicating a value detected by a detector connected to the data processing device.

[0058] (5) A method for determining whether or not the memory has a failure, in which a processor reads data consisting of a plurality of bits from a memory, performs bit inversion on the plurality of bits to generate bit-inverted data after the values ​​of each bit of the plurality of bits are inverted, writes the bit-inverted data to the memory at a first time, reads the bit-inverted data from the memory at a second time that is later than the first time, and compares first data, which is the bit-inverted data written to the memory at the first time, with second data, which is the bit-inverted data read from the memory at the second time, to determine whether or not the memory has a failure.

[0059] (6) A memory fault determination program for causing a processor to execute a process of reading data consisting of a plurality of bits from a memory, performing bit inversion on the plurality of bits to generate bit-inverted data after the values ​​of each bit of the plurality of bits are inverted, writing the bit-inverted data to the memory at a first time, reading the bit-inverted data from the memory at a second time that is later than the first time, and comparing first data, which is the bit-inverted data written to the memory at the first time, with second data, which is the bit-inverted data read from the memory at the second time, to determine whether or not the memory has a fault. [Explanation of symbols]

[0060] 1. Material Detection System 10. Detection value display device 20 Detector 11 Data processing device 11A CPU CM CPU memory 11B FPGA RM1 First buffer memory MM1 Second buffer memory RM2 Third buffer memory MM2 4th buffer memory

Claims

1. A memory for storing data formed from a plurality of bits; reading the data from the memory; performing bit inversion on the plurality of bits to generate bit-inverted data after a value of each bit of the plurality of bits is inverted; writing the bit-inverted data to the memory at a first time; reading the bit-inverted data from the memory at a second time that is later than the first time; a processor that determines whether or not the memory is faulty by comparing first data, which is the bit-inverted data written to the memory at the first time, with second data, which is the bit-inverted data read from the memory at the second time; A data processing device comprising:

2. the processor determines that the memory is not faulty when a value of the first data and a value of the second data are identical, and determines that the memory is faulty when a value of the first data and a value of the second data are different; 2. A data processing apparatus according to claim 1.

3. An FPGA having the memory.

2. A data processing apparatus according to claim 1.

4. The data is detection data indicating a value detected by a detector connected to the data processing device.

2. A data processing apparatus according to claim 1.

5. The processor: reading data consisting of a plurality of bits from the memory; performing bit inversion on the plurality of bits to generate bit-inverted data after a value of each bit of the plurality of bits is inverted; writing the bit-inverted data to the memory at a first time; reading the bit-inverted data from the memory at a second time that is later than the first time; determining whether or not the memory has a failure by comparing first data, which is the bit-inverted data written to the memory at the first time, with second data, which is the bit-inverted data read from the memory at the second time; A method for determining memory failure.

6. reading data consisting of a plurality of bits from the memory; performing bit inversion on the plurality of bits to generate bit-inverted data after a value of each bit of the plurality of bits is inverted; writing the bit-inverted data to the memory at a first time; reading the bit-inverted data from the memory at a second time that is later than the first time; determining whether or not the memory has a failure by comparing first data, which is the bit-inverted data written to the memory at the first time, with second data, which is the bit-inverted data read from the memory at the second time; A memory failure determination program for causing a processor to execute a process.

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