Gate driving device and gate driving method

Abstract

To generate a feedback signal by performing collation of all gate instructions for a multigate semiconductor element against corresponding actual gate voltages, and determine which gate terminal does not match when the result of the collation does not match.SOLUTION: A gate driving device for driving a multigate semiconductor element having a plurality of gate terminals generates a feedback signal to a control logic unit on the basis of a result of collation between a driving signal of each of a plurality of gate terminals that was generated based on a command signal input from the control logic unit in order to turn on / off the multigate semiconductor element and each terminal voltage at the gate terminal corresponding to the driving signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a gate drive device and a gate drive method for a power semiconductor element, and is particularly suitable for driving the gates of a power semiconductor element having a plurality of gate control terminals employed in a power conversion device. [Background technology]

[0002] In order to improve the efficiency of power conversion devices, the development of multi-gate power devices with multiple gates is underway. Furthermore, since power conversion devices are used for controlling motors in railroad cars and the like to control high voltages and large currents, if the power semiconductor elements that make up the power conversion device are erroneously controlled and a power short circuit occurs, the device itself may be severely damaged. Therefore, in order to prevent such abnormal operation of the power semiconductor elements, a technique for detecting failures as early as possible is required. One such technique is disclosed in Patent Document 1, for example.

[0003] Patent Document 1 discloses a technology for a power conversion device using a multi-gate semiconductor element, which prevents the device from becoming larger due to an increase in the number of wiring and quickly stops the switching of the multi-gate semiconductor element when an abnormality occurs in the device, by generating a feedback signal indicating the on / off state of the multi-gate semiconductor element, and a control logic unit comparing a PWM command with the feedback signal and generating a command different from the PWM command based on the result of the comparison and superimposing it on the PWM command. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2023 / 286627 Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, only the gate voltage of the Gs terminal of the multi-gate semiconductor element, i.e., only the state of a single gate voltage, is fed back, and it is not assumed that the remaining gate voltage states (the gate voltage states of the Gc terminal and the Gd terminal) will be determined from the control logic unit. Therefore, the effect is limited to detecting gate abnormalities from the feedback of the gate voltage state only for the Gs terminal for switching commands.

[0006] Therefore, the present invention aims to provide a technology that generates a feedback signal by comparing all gate commands of a multi-gate semiconductor element with the corresponding actual gate voltages, and, when the comparison results in a mismatch, superimposes information on the feedback signal that identifies which gate terminal is in a mismatch. [Means for solving the problem]

[0007] In order to solve the above problems, one representative gate driver of the present invention is a gate driver for driving a multi-gate semiconductor element having multiple gate terminals, and generates a feedback signal to the control logic unit based on the result of comparing the drive signals for each of the multiple gate terminals generated based on a command signal input from a control logic unit to turn the multi-gate semiconductor element on / off with the terminal voltages of the gate terminals corresponding to the drive signals. Effect of the Invention

[0008] According to the present invention, it is possible to detect gate abnormalities for all gate terminals of a multi-gate semiconductor device, and to identify and determine which gate terminal is abnormal. Problems, configurations and effects other than those described above will become apparent from the description of the following embodiments. [Brief description of the drawings]

[0009] [Figure 1] 1 is a diagram showing a configuration of a gate driver for driving a multi-gate semiconductor element according to a first embodiment of the present invention. [Diagram 2] FIG. 4 is a diagram illustrating an example of a sequence when an abnormality occurs in the gate drive device according to the first embodiment. [Diagram 3] FIG. 11 is a diagram showing a configuration of a gate driver for driving a multi-gate semiconductor element according to a second embodiment of the present invention. [Figure 4] FIG. 11 is a diagram illustrating an example of a sequence when an abnormality occurs in the gate drive device according to the second embodiment. [Diagram 5] FIG. 11 is a diagram showing a configuration of a gate driver for driving a multi-gate semiconductor element according to a third embodiment of the present invention. [Figure 6] 2 is a diagram showing pulse patterns generated by a pulse generating unit 1 and a pulse generating unit 2. FIG. [Figure 7] 2 is a diagram showing pulse patterns generated by a pulse generating section 3 and a pulse generating section 4. FIG. [Figure 8] FIG. 13 is a diagram showing a sequence for discriminating between Gs abnormality, Gc abnormality, and Gd abnormality based on differences in pulse width and feeding back the results. [Figure 9] FIG. 13 is a diagram showing a sequence for discriminating between Gs abnormality, Gc abnormality, and Gd abnormality based on differences in the number of pulses and feeding back the results. [Figure 10] FIG. 13 shows the results of simulating Gc anomalies. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, with reference to the drawings, a description will be given of examples 1 to 3 as modes for carrying out the present invention. Note that the present invention is not limited to these examples. In addition, in the description of the drawings, the same parts are denoted by the same reference numerals.

[0011] Furthermore, the multi-gate semiconductor device (multi-gate semiconductor device 1 shown in Figs. 1, 3 and 5) driven by the gate drive device according to the first to third embodiments is shown as an element provided in the upper and lower arms of one phase of a power conversion device (not shown) represented by a three-phase inverter, for example. Also, the power conversion device is typically used for driving vehicles mounted on railway cars, for example, but the use is not limited thereto. EXAMPLES

[0012] FIG. 1 is a diagram showing a configuration of a gate driver for driving a multi-gate semiconductor device according to a first embodiment of the present invention. Here, the multi-gate semiconductor element used in the present invention is a power semiconductor element (power semiconductor element) that controls electric power and has multiple gate control terminals. For example, it is an element in which a dual-gate IGBT that can control the carrier state in the semiconductor element and reduce loss by switching on / off signals of multiple gate control terminals, and a MOS control diode, which is a diode having a gate, are connected in inverse parallel to the IGBT, are mounted on the same power module.

[0013] The multi-gate semiconductor element 1 shown in FIG. 1 is a semiconductor element composed of a dual-gate IGBT 11 and a MOS controlled diode 12 connected in inverse parallel to this dual-gate IGBT 11, and has three terminals as gate control terminals for switching the on (conducting) state and off (non-conducting) state of this semiconductor element: a Gs terminal 13 for switching commands, a Gc terminal 14 for carrier control, and a Gd terminal 15 for the MOS controlled diode.

[0014] Next, the gate driver 2 is composed of the following components: ·Command generation unit 3: Based on a PWM signal (a signal that commands the on / off switching of a semiconductor element) transmitted from a higher-level control logic unit (not shown), each of the gate commands Gs command, Gc command, and Gd command is generated.

[0015] Gate driver 4: Each gate command (Gs command, Gc command, and Gd command) output by the command generating unit 3 is converted into a gate terminal drive signal (Gs signal, Gc signal, and Gd signal) to drive each gate terminal (Gs terminal 13, Gc terminal 14, and Gd terminal 15) of the multi-gate semiconductor element 1.

[0016] Matching circuits 51 to 53, OR circuit 61 These circuits compare the state (high or low terminal voltage) of each gate terminal (Gs terminal 13, Gc terminal 14, and Gd terminal 15) with the gate command, and generate a feedback (FB) signal to be transmitted to a control logic unit (not shown). Here, the comparison circuits 51 to 53 are composed of exclusive OR (XOR) circuits that output level L if two input signals match, and output level H if they do not match.

[0017] The comparison circuit 51 compares the voltage level of the Gc terminal 14 with the Gc command, and the comparison circuit 52 compares the voltage level of the Gd terminal 15 with the Gd command, and the comparison results are passed through an OR circuit 61 to a comparison circuit 53 which compares the voltage level of the Gs terminal 13. The comparison result of the comparison circuit 52 becomes a feedback (FB) signal.

[0018] Specifically, for the Gc terminal 14 and the Gd terminal 15, if the comparison results are both level L, i.e., if the drive of the Gc terminal 14 and the drive of the Gd terminal 15 are both normal, the feedback (FB) signal will be a signal based on the state of the Gs signal, which is the gate terminal drive signal of the Gs terminal 13 (level H when the Gs signal is high, level L when the Gs signal is low). The control logic unit (not shown) that receives this feedback (FB) signal compares it with a judgment pattern generated inside the control logic unit to judge whether there is a gate abnormality.

[0019] On the other hand, if at least either of the comparison results for the Gc terminal 14 and the Gd terminal 15 is level H, i.e., if at least either the drive of the Gc terminal 14 or the drive of the Gd terminal 15 is abnormal, the feedback (FB) signal will invert the signal based on the state of the Gs signal, which is the gate terminal drive signal for the Gs terminal 13 (level L when the Gs signal is high, level H when the Gs signal is low). When the control logic unit (not shown) receives this feedback (FB) signal and compares it with an internal judgment pattern, it can determine that a gate abnormality exists because the feedback (FB) signal is inverted.

[0020] FIG. 2 is a diagram showing an example of a sequence when an abnormality occurs in the gate drive device according to the first embodiment. The diagram shows a sequence when the voltage of the Gc terminal 14 becomes abnormal. delay is the time difference between the PWM signal and the Gs command, and t A is the time when the abnormality occurred.

[0021] When the PWM signal transitions to ON, T delay After a certain time, the Gs command and the Gc command are turned ON. A Then, when the Gc command is ON but the actual Gc terminal 14 is OFF, the feedback (FB) signal is inverted from ON to OFF ("B" in FIG. 2) based on the result of the comparison by the comparison circuit 51 of a mismatch ("A" in FIG. 2).

[0022] In response to the inversion of this feedback (FB) signal, the control logic unit (not shown) determines the judgment pattern (the PWM signal with a delay (T delay By comparing the signal multiplied by the time ("C" in Figure 2), it is possible to determine whether there is a gate abnormality. Although the sequence when an abnormality occurs in Gc has been described above, the sequence when an abnormality occurs in Gs and Gd is similar.

[0023] When an abnormality occurs in Gs, the change in state of the Gs signal, which is the gate terminal drive signal of the Gs terminal 13, becomes a feedback (FB) signal as it is, so that a gate abnormality can be determined by comparing it with the judgment pattern of the control logic unit (not shown) (the judgment pattern shown at the bottom of Figure 2).

[0024] When an abnormality occurs in Gd, the feedback (FB) signal is inverted at the time of the abnormality occurrence, and therefore, a gate abnormality can be determined by comparing it with the judgment pattern (the judgment pattern shown at the bottom of Figure 2) of the control logic unit (not shown). EXAMPLES

[0025] Second Embodiment FIG. 3 is a diagram showing a configuration of a gate driver for driving a multi-gate semiconductor device according to a second embodiment of the present invention. In the second embodiment, a comparison circuit 54 is added to the first embodiment for comparing the voltage level of the Gs terminal 13 with the Gs command. In addition, a feedback (FB) signal is generated by passing the comparison results of the comparison circuits 51, 52, and 54 through an OR circuit 62.

[0026] This makes it possible to eliminate the determination pattern inside the control logic unit (not shown) in addition to the advantageous effects achieved in the first embodiment.

[0027] 4 is a diagram showing an example of a sequence when an abnormality occurs in the gate drive device according to the second embodiment. In the diagram, as in the case of the first embodiment, a sequence when the voltage of the Gc terminal 14 becomes abnormal is shown. delay is the time difference between the PWM signal and the Gs command, and t D is the time when the abnormality occurred.

[0028] When the PWM signal transitions to ON, T delay After a certain time, the Gs command and the Gc command are turned ON. DThen, when the actual Gc terminal 14 is OFF even though the Gc command is ON, the feedback (FB) signal is turned ON ("E" in FIG. 4) based on the result of the comparison by the comparison circuit 51 of a mismatch ("D" in FIG. 4).

[0029] When this feedback (FB) signal is turned ON, a control logic unit (not shown) can determine whether there is a gate abnormality by comparing it with the PWM signal. Although the sequence when an abnormality occurs in Gc has been described above, the sequence when an abnormality occurs in Gs and Gd is similar.

[0030] When an abnormality occurs in Gs, the feedback signal turns ON at the point in time when a mismatch occurs between the voltage level of the Gs terminal 13 and the Gs command, making it possible to determine whether or not a gate abnormality has occurred.

[0031] When an abnormality occurs in Gd, the feedback signal turns ON at the point in time when a mismatch occurs between the voltage level of the Gd terminal 15 and the Gd command, making it possible to determine whether or not a gate abnormality has occurred. EXAMPLES

[0032] Third Embodiment FIG. 5 is a diagram showing a configuration of a gate driver for driving a multi-gate semiconductor device according to a third embodiment of the present invention. In comparison with the previous first and second embodiments, the third embodiment adds a function for determining which of the three gate terminals, Gs terminal 13, Gc terminal 14, and Gd terminal 15, is inconsistent.

[0033] The matching circuits 51 to 54, OR circuits 61 to 63, AND circuits 71 to 73, and pulse generating units 1 (81) to 4 (84) shown in FIG. 5 are components for generating a feedback (FB) signal, and those common to the above-mentioned first and second embodiments are given the same numbers.

[0034] Here, the operation of the pulse generating units 1 (81) to 4 (84) newly added in the third embodiment will be described with reference to FIG. 6 and FIG.

[0035] FIG. 6 is a diagram showing pulse patterns generated by pulse generating unit 1 (81) and pulse generating unit 2 (82). As shown in the upper part of FIG. 6, when the pulse generating unit 1 (81) receives a level H input, it outputs a one-shot pulse with a time width of T1 (e.g., 1 μs), and then generates a pulse in which no output is generated for a time period T2 (e.g., 2 ms, where T2>>T1) regardless of the presence or absence of an input signal.

[0036] As shown in the lower part of FIG. 6, when the pulse generating unit 2 (82) receives a level H input, it generates a pulse to output a pulse having a time width T4 (e.g., 3 μs) after a pulse delay time T3 (e.g., 10 μs) has elapsed.

[0037] FIG. 7 is a diagram showing pulse patterns generated by pulse generating unit 3 (83) and pulse generating unit 4 (84). As shown in the upper part of FIG. 7, when the pulse generating unit 3 (83) receives a level H input, it generates a pulse to output a pulse having a time width T6 (e.g., 6 μs) after a pulse delay time T5 (e.g., 16 μs) has elapsed.

[0038] As shown in the lower part of FIG. 7, when the pulse generating unit 4 (84) receives a level H input, it generates a pulse to output a pulse with a time width T8 (e.g., 9 μs) after a pulse delay time T7 (e.g., 35 μs) has elapsed.

[0039] As described above, pulse generating unit 1 (81) generates and outputs a one-shot pulse in response to the first input of level H received at each predetermined time period. Furthermore, pulse generating unit 2 (82), pulse generating unit 3 (83), and pulse generating unit 4 (84) each generate and output pulses of different output widths after receiving a level H input and after the lapse of different delay times.

[0040] Next, the input state of each pulse generating unit will be described. The pulse generating unit 1 (81) receives the output of an OR circuit 62 that takes the logical sum (OR) of the outputs of the comparison circuits 51, 52, and 54. In other words, the output (feedback (FB) signal) of the gate driving device 2 described in the previous second embodiment is received as an input, and a determination signal for gate abnormalities in Gs, Gc, and Gd is input.

[0041] Pulse generating unit 2 (82) receives as its input the output of AND circuit 71, which takes the logical product of the output of pulse generating unit 1 (81) and the output of comparison circuit 54, which compares the voltage level of Gs terminal 13 with the Gs command. In other words, pulse generating unit 2 (82) reliably receives the gate abnormality determination signal for Gs from the logical product (AND) of the gate abnormality determination signals for Gs, Gc, and Gd from pulse generating unit 1 (81) and the gate abnormality determination signal for Gs from comparison circuit 54.

[0042] Similarly, pulse generating unit 3 (83) receives as input the output of AND circuit 72, which takes the logical product of the output of pulse generating unit 1 (81) and the output of comparison circuit 51, which compares the voltage level of Gc terminal 14 with the Gc command, to reliably receive a determination signal of a gate abnormality in Gc.

[0043] Similarly, pulse generating unit 4 (84) reliably receives a determination signal of a gate abnormality in Gd by using as input the output of AND circuit 73, which takes the logical product of the output of pulse generating unit 1 (81) and the output of comparison circuit 52, which compares the voltage level of Gd terminal 15 with the Gd command.

[0044] The OR circuit 63 outputs, as a feedback (FB) signal, the logical sum (OR) of the output of the comparison circuit 53, which performs comparison similar to that in the previous embodiment 1, and each output of the pulse generating units 2 (82), 3 (83), and 4 (84). That is, in response to the output of the comparison circuit 53, a feedback (FB) signal related to gate abnormalities in Gs, Gc, and Gd similar to that in the first embodiment is output, and in response to the outputs of the pulse generating units 2 (82), 3 (83), and 4 (84), a feedback (FB) signal related to each individual gate abnormality in Gs, Gc, and Gd is output.

[0045] Next, the sequence of the feedback (FB) signal output from the OR circuit 63 will be described with reference to FIGS. 8 and 9, the first row shows a PWM signal. The PWM signal includes an emergency stop short OFF pulse (3 μs pulse missing as shown in FIG. 8 and FIG. 9) used to stop subsequent operations when an abnormality occurs. The second row shows a feedback (FB) signal generated by the first embodiment (the output signal of the collation circuit 53 in the third embodiment) as a conventional feedback (FB) signal.

[0046] FIG. 8 is a diagram showing a sequence for discriminating between the Gs abnormality, the Gc abnormality, and the Gd abnormality based on differences in the pulse width of the output pulse and providing feedback. In the event of a Gs abnormality, when the logical product (AND) of the output of pulse generation unit 1 (81) and the comparison result of comparison circuit 54 becomes level H (ON) by pulse generation unit 2 (82), a pulse of a predetermined time width T4 (3 μs in FIG. 8) is output as a feedback (FB) signal after a predetermined pulse delay time has elapsed, following the pulse pattern in the lower diagram of FIG. 6.

[0047] Here, we will provide further information on the logical product (AND) output of the output of pulse generation unit 1 (81) and the comparison result of comparison circuit 54. When a Gs abnormality occurs, level H is input to pulse generation unit 1 by comparison circuits 51, 52, 54 and OR circuit 62, which have the same configuration as in the previous embodiment 2, and as a result, a one-shot pulse of level H" is output from pulse generation unit 1, as shown in the upper diagram of FIG. 6. Meanwhile, level H is also output from comparison circuit 54 by exclusive OR (XOR) at the time of the Gs abnormality. A level H pulse, which is the logical product (AND) of the two, is input from AND circuit 71 to pulse generation unit 2 (82).

[0048] For the remaining Gc anomaly and Gd anomaly, feedback (FB) signals with different pulse delay times and pulse widths are outputted in the same operational manner (sequence) as for the Gs anomaly described above, as shown in FIG.

[0049] That is, in the case of a Gc abnormality, when the logical product (AND) of the output of pulse generation unit 1 (81) and the comparison result of comparison circuit 51 becomes level H (ON) by pulse generation unit 3 (83), a pulse of a predetermined time width T6 (6 μs in FIG. 8) is output as a feedback (FB) signal after a predetermined pulse delay time has elapsed, following the pulse pattern in the upper diagram of FIG. 7.

[0050] In addition, in the case of a Gd abnormality, when the logical product (AND) of the output of pulse generation unit 1 (81) and the comparison result of comparison circuit 52 becomes level H (ON) by pulse generation unit 4 (84), a pulse of a predetermined time width T8 (9 μs in FIG. 8) is output as a feedback (FB) signal after a predetermined pulse delay time has elapsed, following the pulse pattern in the lower diagram of FIG. 7.

[0051] FIG. 9 is a diagram showing a sequence for discriminating between Gs abnormality, Gc abnormality, and Gd abnormality based on the difference in the number of output pulses and providing feedback. In the sequence shown in FIG. 8, Gs abnormalities, Gc abnormalities, and Gd abnormalities are distinguished from one another by differences in the pulse width of the output pulse, whereas the sequence shown in FIG. 9 differs in that Gs abnormalities, Gc abnormalities, and Gd abnormalities are distinguished from one another by differences in the number of pulses in the output pulse.

[0052] That is, a Gs abnormality is represented by a single pulse of a predetermined time width (3 μs in FIG. 9) after a predetermined pulse delay time has elapsed, a Gc abnormality is represented by two consecutive pulses of a predetermined time width (3 μs in FIG. 9) after a predetermined pulse delay time has elapsed (longer than the Gs abnormality and shorter than the Gd abnormality), and a Gd abnormality is represented by three consecutive pulses of a predetermined time width (3 μs in FIG. 9) after a predetermined pulse delay time has elapsed (longer than the Gs abnormality and Gc abnormality). However, the pulse time width and number are not limited to these.

[0053] Moreover, the numbers of pulses corresponding to the Gs abnormality, Gc abnormality, and Gd abnormality, respectively, are generated by pulse generating unit 2 (82), pulse generating unit 3 (83), and pulse generating unit 4 (84) using a method different from the change in pulse width shown in Fig. 8. For example, instead of changing the time width of the output pulse as shown in the lower diagram of Fig. 6, the upper diagram of Fig. 7, and the lower diagram of Fig. 7, the number of pulses is changed by changing the continuity of pulse generation of the same time width.

[0054] As described above, according to the third embodiment, by superimposing signals with different pulse widths or pulse numbers corresponding to the Gs abnormality, the Gc abnormality, and the Gd abnormality, on the feedback (FB) signal, it becomes possible to determine which of the Gs, Gc, and Gd terminals has an abnormality. In addition, the signal can be recorded in a control logic unit (not shown) or, if it is a multi-gate semiconductor device constituting a power conversion device mounted on a railway vehicle, in a train information control device.

[0055] FIG. 10 shows the results of simulating Gc abnormalities. It can be seen that when the Gc terminal voltage is applied based on the Gc command, the occurrence of a Gc abnormality causes the Gc terminal voltage to change to level L at that point, resulting in a Gc mismatch determination and an inversion of the feedback (FB) signal. After the inversion, an additional pulse is output to the feedback (FB) signal by the pulse generation described above.

[0056] Here, as described above, if this additional pulse is recorded, it is possible to determine the gate states of Gs, Gc, and Gd, i.e., whether it is a Gs abnormality, a Gc abnormality, or a Gd abnormality, by checking the width of this additional pulse from the log using, for example, a fault monitor.

[0057] According to the above-mentioned first to third embodiments, the present invention includes at least the following aspects. <Aspect 1> A gate drive device for driving a multi-gate semiconductor element having a plurality of gate terminals, characterized in that the device generates a feedback signal to the control logic unit based on a comparison result between drive signals for each of the plurality of gate terminals, which are generated based on a command signal input from a control logic unit to turn the multi-gate semiconductor element on / off, and the terminal voltages of each of the gate terminals corresponding to the drive signals.

[0058] <Aspect 2> In the gate driving device according to the first aspect, the feedback signal is a signal indicating that the comparison result at at least one of the plurality of gate terminals is a mismatch.

[0059] <Aspect 3> The gate driver according to the second aspect above is characterized in that an identification signal for identifying a gate terminal for which the comparison result is a mismatch is added to the feedback signal.

[0060] <Aspect 4> In the gate driving device according to the third aspect, the identification signal is a pulse signal having a different signal width for each gate terminal.

[0061] <Aspect 5> In the gate driving device according to the third aspect, the identification signal is one or more pulse signals having a different number of pulses for each gate terminal.

[0062] <Aspect 6> A power conversion device including a plurality of multi-gate semiconductor devices driven by the gate drive device according to any one of the first to fifth aspects.

[0063] <Aspect 7> The power conversion device according to the sixth aspect, wherein the command signal is a PWM signal.

[0064] <Aspect 8> A power conversion device according to the sixth or seventh aspect, characterized in that the multi-gate semiconductor element is composed of a dual-gate IGBT and a MOS control diode with a gate terminal connected in inverse parallel to the dual-gate IGBT.

[0065] <Aspect 9> A railway vehicle equipped with the power conversion device according to any one of the sixth to eighth aspects.

[0066] <Aspect 10> A gate driving method for driving a multi-gate semiconductor element having a plurality of gate terminals, comprising the steps of: inputting a command signal for turning on / off the multi-gate semiconductor element from a control logic unit; generating drive signals for each of the plurality of gate terminals based on the command signal; comparing the drive signals with terminal voltages of the gate terminals corresponding to the drive signals; and generating a feedback signal to the control logic unit based on the comparison result.

[0067] <Aspect 11> The gate driving method according to the tenth aspect is characterized in that the feedback signal is generated as a signal indicating that the comparison result is a mismatch at least for any of the multiple gate terminals.

[0068] <Aspect 12> The gate driving method according to the eleventh aspect above is characterized in that an identification signal for identifying a gate terminal for which the comparison result is a mismatch is added to the feedback signal.

[0069] <Aspect 13> The gate driving method according to the twelfth aspect, wherein the identification signal is a pulse signal having a different signal width for each gate terminal.

[0070] <Aspect 14> The gate driving method according to the twelfth aspect, wherein the identification signal is one or more pulse signals having a different number of pulses for each gate terminal.

[0071] <Aspect 15> The gate driving method according to any one of the above aspects 10 to 14, wherein the command signal is a PWM signal.

[0072] As described above, the first to third embodiments have been described as forms for carrying out the present invention. However, the present invention is not limited to the above-described embodiments, and various modifications are possible without departing from the gist of the present invention. [Explanation of symbols]

[0073] 1... multi-gate semiconductor element, 2... gate driving device, 3... command generating unit, 4...gate driver, 11...dual gate IGBT, 12...MOS control diode, 13...Gs terminal, 14...Gc terminal, 15...Gd terminal, 51, 52, 53, 54 ... matching circuits, 61, 62, 63 ... OR circuits, 71, 72, 73...AND circuit, 81...pulse generating unit 1, 82...pulse generating unit 2, 83...pulse generating unit 3, 84...pulse generating unit 4

Claims

1. A gate driver for driving a multi-gate semiconductor element having a plurality of gate terminals, comprising: A feedback signal is generated for the control logic unit based on a comparison result between a drive signal for each of the plurality of gate terminals, which is generated based on a command signal input from a control logic unit to turn on / off the multi-gate semiconductor device, and a terminal voltage for each of the gate terminals corresponding to the drive signal. A gate drive device comprising:

2. 2. The gate driver of claim 1, The feedback signal is a signal indicating that the comparison result at at least one of the plurality of gate terminals is a mismatch. A gate drive device comprising:

3. 3. The gate driver according to claim 2, An identification signal for identifying the gate terminal where the comparison result is inconsistent is added to the feedback signal. A gate drive device comprising:

4. 4. The gate driver according to claim 3, The identification signal is a pulse signal having a different signal width for each of the gate terminals. A gate drive device comprising:

5. 4. The gate driver according to claim 3, The identification signal is one or more pulse signals having a different number of pulses for each of the gate terminals. A gate drive device comprising:

6. A power conversion device comprising a plurality of multi-gate semiconductor devices driven by the gate drive device according to any one of claims 1 to 5.

7. The power conversion device according to claim 6, The command signal is a PWM signal. A power conversion device comprising:

8. The power conversion device according to claim 6, The multi-gate semiconductor element is composed of a dual-gate IGBT and a MOS control diode with a gate terminal connected in inverse parallel to the dual-gate IGBT. A power conversion device comprising:

9. A railway vehicle equipped with the power conversion device according to claim 6.

10. A gate driving method for driving a multi-gate semiconductor device having a plurality of gate terminals, comprising the steps of: A command signal for turning on / off the multi-gate semiconductor device is input from a control logic unit; generating drive signals for the plurality of gate terminals based on the command signal; comparing the drive signal with the terminal voltage of each of the gate terminals corresponding to the drive signal; generating a feedback signal to the control logic based on the results of the comparison; A gate driving method comprising:

11. The gate driving method according to claim 10, The feedback signal is generated as a signal indicating that the comparison result is a mismatch at least in any of the plurality of gate terminals. A gate driving method comprising:

12. The gate driving method according to claim 11, An identification signal for identifying the gate terminal where the comparison result is inconsistent is added to the feedback signal. A gate driving method comprising:

13. 13. The gate driving method according to claim 12, The identification signal is a pulse signal having a different signal width for each of the gate terminals. A gate driving method comprising:

14. 13. The gate driving method according to claim 12, The identification signal is one or more pulse signals having a different number of pulses for each of the gate terminals. A gate driving method comprising:

15. 15. A gate driving method according to claim 10, further comprising the steps of: The command signal is a PWM signal. A gate driving method comprising:

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