Semiconductor package and method for manufacturing the same

Abstract

To provide a new semiconductor package and a method for manufacturing the same that can solve the problems of 3.5D packaging technology.SOLUTION: A semiconductor package includes a rewiring structure, a first semiconductor stack structure on an upper surface of the rewiring structure, the first semiconductor stack structure including a first chiplet and a second chiplet disposed on the first chiplet, a second semiconductor stack structure disposed on the upper surface of the rewiring structure in parallel with the first semiconductor stack structure, a bridge die that is disposed on the first semiconductor stack structure and the second semiconductor stack structure, and electrically connects the first semiconductor stack structure and the second semiconductor stack structure to each other, and a surface mounted device (SMD) on the upper surface of at least one of the first semiconductor stack structure and the second semiconductor stack structure.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor package and a manufacturing method thereof, and more particularly to a new semiconductor package and a manufacturing method thereof that can solve the problems of 3.5D packaging technology. [Background technology]

[0002] The semiconductor industry strives for increased integration density so that more passive or active devices can be integrated into a given area. Technological development for miniaturizing circuit line widths in semiconductor front-end processes is gradually reaching its limits. Accordingly, the semiconductor industry has developed semiconductor packaging technologies that enable high integration density to make up for the limitations of semiconductor front-end processes.

[0003] Following this trend, 3.5D packaging technology was developed in which a bridge die is used to connect the bottom surface of a High Bandwidth Memory (HBM) to the bottom surface of a chiplet stack structure, a substrate is placed under the bridge die, and a surface mount device (SMD) is placed on the bottom surface of the substrate.

[0004] In 3.5D packaging technology, a bridge die and substrate are placed between the high-bandwidth memory (HBM) and chiplet stack on top and the surface-mounted device (SMD) on the bottom. Therefore, the 3.5D packaging technology has long electrical paths between the high bandwidth memory (HBM) and chiplet stack on top and the surface mount device (SMD) on the bottom, which makes it difficult to achieve high performance semiconductor packages and increases the vertical thickness of the 3.5D packages. In addition, by placing surface mount devices (SMDs) under the substrate, the number of connection members placed under the substrate is reduced, which increases the horizontal size of the 3.5D package.

[0005] Therefore, there is a need to develop a new semiconductor packaging technology that can solve the problems of the conventional semiconductor packaging technology. Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made in consideration of the above-mentioned problems in the conventional semiconductor package technology, and an object of the present invention is to provide a semiconductor package and a semiconductor package manufacturing method in a 3.5D package, in which an upper surface of a high bandwidth memory (HBM) and an upper surface of a chiplet stacked structure are connected by a bridge die, a surface mount device (SMD) is disposed on at least one of the upper surface of the high bandwidth memory (HBM) and the upper surface of the chiplet stacked structure, and a redistribution structure is disposed on a lower surface of the high bandwidth memory (HBM) and the lower surface of the chiplet stacked structure. [Means for solving the problem]

[0007] In order to achieve the above-mentioned object, the semiconductor package according to the present invention comprises a redistribution structure, a first semiconductor stack structure on an upper surface of the redistribution structure, the first semiconductor stack structure including a first chiplet and a second chiplet arranged on the first chiplet, a second semiconductor stack structure arranged side by side with the first semiconductor stack structure on the upper surface of the redistribution structure, a bridge die arranged on the first semiconductor stack structure and the second semiconductor stack structure, electrically connecting the first semiconductor stack structure and the second semiconductor stack structure, and a surface mounted device (SMD) on the upper surface of at least one of the first semiconductor stack structure and the second semiconductor stack structure.

[0008] In order to achieve the above object, a semiconductor package according to the present invention includes a rewiring structure, a first semiconductor stack structure on the rewiring structure, the first semiconductor stack structure including a first chiplet and a first molding material molding a side surface of the first chiplet, a second chiplet on the first chiplet and on the first molding material, the first chiplet being disposed between the rewiring structure and the second chiplet and including a first interconnect structure between the first chiplet and the second chiplet, a second semiconductor stack structure disposed side by side with the first semiconductor stack structure on the rewiring structure, a bridge die disposed on the first semiconductor stack structure and the second semiconductor stack structure and electrically connecting the first semiconductor stack structure and the second semiconductor stack structure, a surface mounted device (SMD) disposed on at least one of the first semiconductor stack structure and the second semiconductor stack structure, and a second molding material on the rewiring structure covering the first semiconductor stack structure, the second semiconductor stack structure, the bridge die, and the surface mounted device.

[0009] In order to achieve the above-mentioned object, a semiconductor package manufacturing method according to the present invention includes a step of mounting a first semiconductor stack structure on a redistribution structure, wherein the first semiconductor stack structure includes a first chiplet and a second chiplet on the first chiplet, and a step of mounting a second semiconductor stack structure on the redistribution structure side by side with the first semiconductor stack structure; a step of mounting a bridge die on the first semiconductor stack structure and the second semiconductor stack structure, wherein the bridge die is located on the first semiconductor stack structure and the second semiconductor stack structure, and the bridge die electrically connects the first semiconductor stack structure and the second semiconductor stack structure, and a step of mounting a surface mounted device (SMD) on at least one of the first semiconductor stack structure and the second semiconductor stack structure. Effect of the Invention

[0010] According to the semiconductor package and manufacturing method thereof of the present invention, a surface mounted device (SMD) that was previously placed under a substrate can be placed on the top surface of a high bandwidth memory (HBM) and the top surface of a chiplet stack structure. Therefore, the electrical path length between high bandwidth memory (HBM) and chiplet stacks and surface mounted devices (SMD) can be reduced. In addition, a bridge die, which was previously placed on the top surface of the substrate and between the chiplet stack and the bottom surface of the high bandwidth memory (HBM) and embedded in a silicon interposer, can be placed on the top surface of the high bandwidth memory (HBM) and on the top surface of the chiplet stack. Therefore, the length of the electrical paths between the external connection members of the semiconductor package and the high bandwidth memory (HBM), and between the external connection members of the semiconductor package and the chiplet stack structure, can be reduced without using a silicon interposer.

[0011] Additionally, the redistribution structures can be used without the use of a substrate to connect the redistribution structures to high bandwidth memory (HBM) and finely spaced I / Os in chiplet stacks. Additionally, surface mounted devices (SMDs), traditionally placed alongside external connections from underneath the substrate, can be placed on the top surface of the high bandwidth memory (HBM) and on the top surface of the chiplet stack. This allows the size of the 3.5D package to be reduced without reducing the number of external connection components, which had to be reduced to ensure the area in which surface-mounted devices (SMDs) could be placed. [Brief description of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view showing a schematic configuration of a semiconductor package according to an embodiment of the present invention. [Diagram 2] 2 is a plan view illustrating an example of an upper surface of a semiconductor package according to an embodiment of the present invention; [Diagram 3]11 is a plan view illustrating another example of an upper surface of a semiconductor package according to an embodiment of the present invention; [Figure 4] 11 is a cross-sectional view showing a semiconductor package according to another embodiment of the present invention; [Diagram 5] 2A to 2C are cross-sectional views illustrating a method for manufacturing a first semiconductor stacked structure according to an embodiment of the present invention. [Figure 6] 2A to 2C are cross-sectional views illustrating a method for manufacturing a first semiconductor stacked structure according to an embodiment of the present invention. [Figure 7] 2A to 2C are cross-sectional views illustrating a method for manufacturing a first semiconductor stacked structure according to an embodiment of the present invention. [Figure 8] 2A to 2C are cross-sectional views illustrating a method for manufacturing a first semiconductor stacked structure according to an embodiment of the present invention. [Figure 9] 2A to 2C are cross-sectional views illustrating a method for manufacturing a first semiconductor stacked structure according to an embodiment of the present invention. [Figure 10] 2A to 2C are cross-sectional views illustrating a method for manufacturing a first semiconductor stacked structure according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Next, a specific example of an embodiment for carrying out a semiconductor package and a manufacturing method thereof according to the present invention will be described with reference to the drawings.

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail so that those skilled in the art to which the present invention pertains can easily carry out the present invention. This invention may be embodied in several different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention in the drawings, parts that are not relevant to the description are omitted, and the same reference numerals are used throughout the specification to refer to the same or similar components. Furthermore, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings.

[0015] Throughout the specification, when a part is "coupled" to another part, this includes not only a "directly coupled" connection, but also an "indirectly coupled" connection via another member. Furthermore, when a part is said to "comprise" certain elements, this means that it can further include other elements, rather than excluding other elements, unless specifically stated to the contrary. In addition, when a part such as a layer, film, region, or plate is said to be "on" or "above" another part, this includes not only the case where it is "directly on" the other part, but also the case where there is another part in between. Conversely, when we say that one part is "directly on" another part, it means that there is no other part in between. In addition, being "on" or "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "above" the direction against gravity. Additionally, throughout the specification, "on a plane" means when the target part is viewed from above, and "on a cross section" means when the target part is cut vertically and viewed from the side.

[0016] A semiconductor package 100 and a method for manufacturing the semiconductor package 100 according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor package 100 according to an embodiment of the present invention. Referring to FIG. 1, a bridge die 190 and a surface mounted device (SMD) 195 are disposed on the top surface of a first semiconductor stack structure 160 and the top surface of a second semiconductor stack structure 170, and are electrically connected to the first semiconductor stack structure 160 and the second semiconductor stack structure 170 by hybrid bonding.

[0017] The semiconductor package 100 includes an external connection structure 110, a redistribution structure 120, a first semiconductor stack structure 160, a second semiconductor stack structure 170, a bridge die 190, a surface mounted device (SMD) 195, and a second molding material 162. In one embodiment, the semiconductor package 100 comprises a 3.5D semiconductor package. In one embodiment, the semiconductor package 100 includes a Fan Out Wafer Level Package (FOWLP) or a Fan Out Panel Level Package (FOPLP).

[0018] The external connection structure 110 is disposed on the bottom surface of the redistribution structure 120 . The external connection structure 110 includes a conductive pad 111 , an insulating layer 112 , and an external connection member 113 . The conductive pad 111 electrically connects a first redistribution via 122 of the redistribution structure 120 to an external connection member 113 . The insulating layer 112 includes a number of openings for soldering. The insulating layer 112 can prevent the external connection members 113 from being short-circuited to each other. The external connection members 113 electrically connect the semiconductor package 100 to an external device.

[0019] The redistribution structure 120 includes a dielectric layer 121 and a first redistribution via 122, a first redistribution line 123, and a second redistribution via 124 within the dielectric layer 121. In other embodiments, redistribution structures 120 including fewer or greater numbers of redistribution lines and redistribution vias are within the scope of the present invention. The first redistribution via 122 is disposed between the first redistribution line 123 and the conductive pad 111 . The first redistribution vias 122 electrically connect the first redistribution lines 123 to the external connection members 113 connected to the conductive pads 111 in the vertical direction. The first redistribution line 123 is disposed between the first redistribution via 122 and the second redistribution via 124 . The first redistribution line 123 electrically connects the first redistribution via 122 and the second redistribution via 124 in the horizontal direction. The second redistribution via 124 is disposed between the bonding pad 125 and the first redistribution line 123 . The second redistribution via 124 electrically connects the bonding pad 125 to the first redistribution line 123 in the vertical direction.

[0020] The bonding pads 125 are disposed between the second redistribution vias 124 and the connection members 135 of the first semiconductor stacked structure 160 and between the second redistribution vias 124 and the connection members 172 of the second semiconductor stacked structure 170 . The bonding pads 125 vertically electrically connect the connection members 135 of the first semiconductor stack structure 160 to the second redistribution vias 124 and the connection members 172 of the second semiconductor stack structure 170 to the second redistribution vias 124 . In accordance with the present invention, the redistribution structure 120 can be used in place of a substrate as conventionally used to connect the redistribution structure to finely spaced I / Os of a first semiconductor stack 160 (e.g., a chiplet stack) and a second semiconductor stack 170 (e.g., a high bandwidth memory (HBM)).

[0021] The first semiconductor stack 160 is disposed over the redistribution structure 120 . The first semiconductor stack 160 is a chiplet stack structure formed by stacking chiplets. The first semiconductor stack 160 includes a first chiplet 130 , a second chiplet 140 on the first chiplet 130 , a first interconnect structure 150 between the first chiplet 130 and the second chiplet 140 , and a first molding material 161 . Chiplets are building blocks of high-performance processors that are differentiated according to their functions. Chiplets that do not require the use of the latest process can be manufactured using an inexpensive older process, and chiplets that must use the latest process can be manufactured using the latest process. In this way, chiplets can be manufactured separately according to their functions, and the manufactured chiplets can be connected to manufacture a single high-performance processor. Each chiplet cannot operate as a unit chip, and a high-performance processor manufactured by connecting such chiplets can overcome the performance limitations of a conventional processor manufactured on a single chip.

[0022] The first chiplet 130 includes a first active area 131 , a first chiplet base 132 , a bottom connection pad 133 , a first through silicon via (TSV) 134 , and a connection member 135 . In one embodiment, first chiplet 130 includes a central processing unit (CPU) or a graphic processing unit (GPU). The first chiplet 130 is electrically connected to an upper second chiplet 140 by a first interconnect structure 150 . The lower connection pad 133 is electrically connected to the bonding pad 125 via a connection member 135 . A redistribution structure 120 is disposed below the first chiplet 130 . The sides of first chiplet 130 are surrounded by first molding material 161 .

[0023] The first active region 131 is located on the front side of the first chiplet 130 . The first active area 131 is located at the top level of the first chiplet 130 . First active area 131 is located on the surface facing second chiplet 140 . The first active area 131 is disposed between the lower bonding pad 151 of the first interconnect structure 150 and the first through silicon via 134 . The first active area 131 electrically connects the bottom bond pad 151 of the first interconnect structure 150 to the first through silicon via 134 . In one embodiment, the first active area 131 includes logic circuitry.

[0024] The first chiplet base 132 is located on a back side of the first chiplet away from the first active area 131 . A bottom connection pad 133 and a first through silicon via 134 are disposed within first chiplet base 132 . The first chiplet base 132 includes a silicon material. The lower connection pad 133 is disposed between the first through silicon via 134 and the connection member 135 . The lower connection pad 133 electrically connects the first through silicon via 134 to the connection member 135 .

[0025] The first through silicon via 134 is disposed between the first active area 131 and the lower connection pad 133 . A first through silicon via 134 electrically connects the first active area 131 to the bottom contact pad 133 . One end of the first through silicon via 134 contacts the first active region 131 , and the other end of the first through silicon via 134 contacts the lower connection pad 133 . The first through silicon via 134 extends downward from the first active area 131 of the first chiplet 130 to the rear surface of the first chiplet 130 . In this manner, because the first through silicon via 134 is disposed within the first chiplet 130 and the first chiplet 130 and the second chiplet 140 are arranged with their active surfaces facing each other and interconnected via the first interconnect structure 150, the speed at which signals and power can be transmitted and responded to between the first chiplet 130 and the second chiplet 140 is increased due to the relatively short electrical path through the first interconnect structure 150.

[0026] The connection member 135 is disposed between the lower connection pad 133 and the second redistribution via 124 of the redistribution structure 120 . The connection member 135 electrically connects the bottom connection pad 133 to the second redistribution via 124 of the redistribution structure 120 . In one embodiment, the connection members 135 include microbumps or solder balls. In one embodiment, the bottom contact pad 133 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof. In one embodiment, the first through silicon via 134 may include at least one of tungsten, aluminum, copper, and alloys thereof. In one embodiment, the connecting member 135 may include at least one of tin, silver, lead, nickel, copper, or alloys thereof.

[0027] Second chiplet 140 includes a second active area 141 , a second chiplet base 142 , a second through silicon via 143 , and a top connection pad 144 . In one embodiment, second chiplet 140 includes a static random access memory (SRAM). The second chiplet 140 is electrically connected to the underlying first chiplet 130 by a first interconnect structure 150 . A second interconnect structure 180A is disposed on top of the second chiplet 140. Second chiplet 140 is electrically connected to at least one of bridge die 190 and surface mounted device (SMD) 195 by second interconnect structure 180A. The sides of second chiplet 140 are surrounded by a second molding material 162 . The footprint of the first chiplet 130 is contained within the footprint of the second chiplet 140 .

[0028] The second active region 141 is located on the front side of the second chiplet 140 . A second active area 141 is located at the bottom level of the second chiplet 140 . The second active area 141 is disposed between the top bond pad 152 of the first interconnect structure 150 and the second through silicon via 143 . The second active area 141 electrically connects the second through silicon via 143 to the top bond pad 152 of the first interconnect structure 150 . In one embodiment, the second active area 141 includes logic circuitry.

[0029] The second chiplet base 142 is located on the back side of the second chiplet 140 opposite the second active region 141 . A top connection pad 144 and a second through silicon via 143 are disposed within second chiplet base 142 . The second chiplet base 142 includes a silicon material. The top connection pad 144 is disposed between the second through silicon via 143 and the bottom bonding pad 181 of the second interconnect structure 180A. The top connection pad 144 electrically connects the bottom bond pad 181 of the second interconnect structure 180A to the second through silicon via 143 .

[0030] A second through silicon via 143 is disposed between the second active area 141 and the upper connection pad 144 . The second through silicon via 143 extends upward from the second active region 141 to the rear surface of the second chiplet 140 . A second through silicon via 143 electrically connects the top connection pad 144 to the second active area 141 . One end of the second through silicon via 143 contacts the second active region 141 , and the other end of the second through silicon via 143 contacts the upper connection pad 144 . In this manner, because the second through silicon via 143 is disposed within the second chiplet 140 and is connected to the first chiplet 130 through the first interconnect structure 150 and to the bridge die 190 or surface mounted device (SMD) through the second interconnect structure 180A, the speed at which signals and power can be transmitted and responded between the first chiplet 130 and the second chiplet 140, and between the second chiplet 140 and the second semiconductor stack structure 170, is increased due to the relatively shorter electrical paths.

[0031] In one embodiment, the second through silicon via 143 may include at least one of tungsten, aluminum, copper, and alloys thereof. In one embodiment, the upper connection pad 144 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof.

[0032] First interconnect structure 150 is disposed between first chiplet 130 and second chiplet 140 and between first molding material 161 and second chiplet 140 . The first interconnect structure 150 includes a lower bond pad 151 , an upper bond pad 152 , a lower silicon insulating layer 153 , and an upper silicon insulating layer 154 . Bottom bond pad 151 and top bond pad 152 electrically connect second chiplet 140 to first chiplet 130 .

[0033] In the semiconductor package 100 according to the present invention, a first chiplet 130 and a second chiplet 140 are bonded together by hybrid bonding using a first interconnect structure 150 . Hybrid bonding is the bonding of two devices in a manner that utilizes the bonding properties of the same material to fuse the same materials of the two devices together. In this context, hybrid means that two different types of bonding are performed, e.g., two devices are bonded together by a first type of metal-metal bonding and a second type of non-metal-non-metal bonding. Hybrid bonding allows for the formation of I / Os with fine pitch.

[0034] A lower bonding pad 151 formed on the first chiplet 130 is directly bonded to an upper bonding pad 152 formed under the second chiplet 140 by metal-metal hybrid bonding, and a lower silicon insulating layer 153 formed on the first chiplet 130 is directly bonded to an upper silicon insulating layer 154 formed under the second chiplet 140 by non-metal-non-metal hybrid bonding.

[0035] A second semiconductor stack 170 is disposed over the redistribution structure 120 . The second semiconductor stack 170 is a high bandwidth memory (HBM). High Bandwidth Memory (HBM) is a high-performance three-dimensional (3D) stacked dynamic random access memory (DRAM). High Bandwidth Memory (HBM) is manufactured by stacking memory dies vertically using hybrid bonding or microbumps to form a memory stack. High-bandwidth memory (HBM) has various memory channels through a memory stack in which memory dies are stacked vertically, and can simultaneously achieve shorter latency and higher bandwidth compared to conventional DRAM products. It also reduces the total area that individual DRAMs occupy on a board, which is advantageous for high bandwidth per area and reduces power consumption.

[0036] The second semiconductor stack 170 includes a buffer die (not shown) and multiple memory dies (not shown) stacked on the buffer die. The second semiconductor stack 170 includes an upper connection pad 171 and a connection member 172 . The upper connection pad 171 is disposed below the lower bonding pad 181 of the second interconnect structure 180A. The connection members 172 are disposed on the bond pads 125 of the redistribution structure 120 . In one embodiment, the upper connection pad 171 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof. The connection members 172 electrically connect the second semiconductor stack 170 to the bonding pads 125 of the redistribution structure 120 . In one embodiment, the connection members 172 include microbumps or solder balls.

[0037] The bridge die 190 is disposed on the first semiconductor stack structure 160 and the second semiconductor stack structure 170 . The bridge die 190 is disposed on a portion of the top surface of the first semiconductor stack structure 160 and on a portion of the top surface of the second semiconductor stack structure 170 . The bridge die 190 is electrically connected to the first semiconductor stack structure 160 and the second semiconductor stack structure 170 by a second interconnect structure 180A. The first semiconductor stack 160 and the second semiconductor stack 170 exchange signals and power through a bridge die 190 . Bridge die 190 includes bottom connection pads 191 , connection lines 192 , and a bridge die base 193 . In one embodiment, bridge die 190 includes a silicon bridge.

[0038] The lower connection pad 191 is disposed between the upper bonding pad 182 and the connection line 192 . The lower connection pad 191 electrically connects the connection line 192 to the upper bonding pad 182 . The connection lines 192 are disposed between the lower connection pads 191 and electrically connect the lower connection pads 191 . The bottom contact pad 191 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof. The connection lines 192 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, tungsten, and alloys thereof.

[0039] According to the present invention, a bridge die, which was previously disposed on the top surface of a substrate and between the bottom surface of a chiplet stack and a high bandwidth memory (HBM) and embedded in a silicon interposer, can be disposed on the top surface of a first semiconductor stack 160 (e.g., a chiplet stack) and on the top surface of a second semiconductor stack 170 (e.g., a high bandwidth memory (HBM)). Therefore, without using a silicon interposer, the length of the electrical path between the external connection member 113 of the semiconductor package 100 and the first semiconductor stacked structure 160, and between the external connection member 113 of the semiconductor package 100 and the second semiconductor stacked structure 170 can be reduced.

[0040] A surface mounted device (SMD) 195 is disposed on at least one of the first semiconductor stack structure 160 and the second semiconductor stack structure 170 . A surface mounted device (SMD) 195 is electrically connected to the first semiconductor stack structure 160 or the second semiconductor stack structure 170 by a second interconnect structure 180A. A surface mount device (SMD) 195 provides additional functionality or programming to the overall semiconductor package 100 . The surface mount devices (SMD) 195 may include at least one of a resistor, an inductor, a capacitor, and a jumper. A surface mounted device (SMD) 195 is electrically connected to the first semiconductor stack structure 160 or the second semiconductor stack structure 170 by a second interconnect structure 180A.

[0041] In accordance with the present invention, surface mounted devices (SMDs) that were previously disposed under a substrate may be disposed on an upper surface of a first semiconductor stack structure 160 (e.g., a chiplet stack structure) and an upper surface of a second semiconductor stack structure 170 (e.g., a high bandwidth memory (HBM)). This allows the length of the electrical path between the first semiconductor stacked structure 160 and the second semiconductor stacked structure 170 to be reduced. Additionally, surface mounted devices (SMDs), conventionally arranged alongside external connection members under a substrate, may be disposed on the top surface of the first semiconductor stack structure 160 (e.g., a chiplet stack structure) and the top surface of the second semiconductor stack structure 170 (e.g., a high bandwidth memory (HBM)). Therefore, the size of the 3.5D semiconductor package can be reduced without reducing the number of external connection members, which had to be reduced in order to secure an area for arranging surface mounted devices (SMDs).

[0042] The second interconnect structure 180A is disposed between the first semiconductor stack structure 160 and the bridge die 190, between the first semiconductor stack structure 160 and the surface mounted device (SMD) 195, between the second semiconductor stack structure 170 and the bridge die 190, and between the second semiconductor stack structure 170 and the surface mounted device (SMD) 195. The second interconnect structure 180A includes a lower bond pad 181, an upper bond pad 182, a lower silicon insulating layer 183, and an upper silicon insulating layer 184. The bottom bond pad 181 and the top bond pad 182 electrically connect the bridge die 190 or surface mounted device (SMD) 195 to the first semiconductor stack structure 160 or the second semiconductor stack structure 170 .

[0043] In the semiconductor package 100 according to the present invention, a bridge die 190 or a surface mounted device (SMD) 195 is bonded to the first semiconductor stack structure 160 or the second semiconductor stack structure 170 using a first interconnect structure 180A by hybrid bonding. A lower bonding pad 181 formed on the first semiconductor stack 160 or the second semiconductor stack 170 is directly bonded to an upper bonding pad 182 formed under a bridge die 190 or a surface mounted device (SMD) 195 by metal-metal hybrid bonding. A lower silicon insulating layer 183 formed on the first semiconductor stack 160 or the second semiconductor stack 170 is directly bonded to an upper silicon insulating layer 184 formed under a bridge die 190 or a surface mounted device (SMD) 195 by non-metallic-non-metallic hybrid bonding. A second molding material 162 is disposed over the redistribution structure 120 and molds the first semiconductor stack structure 160, the second semiconductor stack structure 170, the bridge die 190, and the surface mounted device (SMD) 195.

[0044] FIG. 2 is a plan view showing an example of an upper surface of a semiconductor package 100 according to an embodiment of the present invention. Referring to FIG. 2, when viewing the semiconductor package 100 in a plan view excluding the second molding material 162, the first semiconductor stacked structure 160 is disposed in the center, and the second semiconductor stacked structure 170 is disposed around the first semiconductor stacked structure 160. Each bridge die in bridge die 190 electrically connects a first semiconductor stack structure 160 and a second semiconductor stack structure in second semiconductor stack structures 170 . A surface mounted device (SMD) 195 is disposed on the first semiconductor stack structure 160 and on each of the second semiconductor stack structures 170 .

[0045] FIG. 3 is a plan view showing another example of the upper surface of the semiconductor package 100 according to an embodiment of the present invention. Referring to FIG. 3, when viewing the semiconductor package 100 in a plan view excluding the second molding material 162, the first semiconductor stacked structure 160 is disposed in the center, and the second semiconductor stacked structure 170 is disposed around the first semiconductor stacked structure 160. Each bridge die in bridge die 190 electrically connects the first semiconductor stack structure 160 and multiple second semiconductor stack structures in second semiconductor stack structures 170 . A surface mounted device (SMD) 195 is disposed on the first semiconductor stack structure 160 and on each of the second semiconductor stack structures 170 .

[0046] FIG. 4 is a cross-sectional view showing a schematic configuration of a semiconductor package 100 according to another embodiment of the present invention. In FIG. 1, the first semiconductor stack structure 160 and the bridge die 190, the first semiconductor stack structure 160 and the surface mount device (SMD) 195, the second semiconductor stack structure 170 and the bridge die 190, and the second semiconductor stack structure 170 and the surface mount device (SMD) 195 are connected by hybrid bonding, whereas in FIG. 4, the first semiconductor stack structure 160 and the bridge die 190, the first semiconductor stack structure 160 and the surface mount device (SMD) 195, the second semiconductor stack structure 170 and the bridge die 190, and the second semiconductor stack structure 170 and the surface mount device (SMD) 195 are connected by flip chip bonding.

[0047] Referring to FIG. 4, the second interconnect structure 180B is disposed between the first semiconductor stack structure 160 and the bridge die 190, between the first semiconductor stack structure 160 and the surface mounted device (SMD) 195, between the second semiconductor stack structure 170 and the bridge die 190, and between the second semiconductor stack structure 170 and the surface mounted device (SMD) 195. A connecting member 188 and a bonding pad 189 are disposed on the bottom surface of the bridge die 190 as the second interconnect structure 180B. Connection members 188 are disposed between top connection pads 144 and bonding pads 189 of second chiplet 140 , and between top connection pads 171 and bonding pads 187 of second semiconductor stack 170 . Connection members 188 electrically connect bond pads 189 to top connection pads 144 of second chiplet 140 and to top connection pads 171 of second semiconductor stack 170 . Bonding pad 189 is disposed between connecting member 188 and a bottom connection pad 191 of bridge die 190 . Bond pad 189 electrically connects bottom connection pad 191 of bridge die 190 to connection member 188 .

[0048] In one embodiment, the connection members 188 may include microbumps or solder balls. In one embodiment, the connecting member 188 may include at least one of tin, silver, lead, nickel, copper, or an alloy thereof. In one embodiment, the bond pad 189 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof.

[0049] A second interconnect structure 180B, which includes a connection member 186 and a bonding pad 187, is disposed on the bottom surface of the surface mount device (SMD) 195. The connection members 186 are disposed between the top connection pads 144 and the bonding pads 187 of the second chiplet 140 or between the top connection pads 171 and the bonding pads 187 of the second semiconductor stack 170 . Connection member 186 electrically connects bonding pad 187 to top connection pad 144 of second chiplet 140 or bonding pad 187 to top connection pad 171 of second semiconductor stack 170 . Bonding pads 187 are disposed on connecting members 186 . The bonding pad 187 is electrically connected to the connection member 186 .

[0050] In one embodiment, the connection members 186 may include microbumps or solder balls. In one embodiment, the connecting member 186 may include at least one of tin, silver, lead, nickel, copper, or an alloy thereof. In one embodiment, bond pad 187 may include at least one of copper, aluminum, silver, tin, gold, nickel, lead, titanium, and alloys thereof. In FIG. 4, the configuration of the second interconnect structure 180B, other than the connection member 186 and the bonding pad 187, is the same as the configuration shown in FIG. 4, the configuration other than the connection member 186 and bonding pad 187 of the second interconnect structure 180B is the same as that described in FIG.

[0051] 5 to 10 are cross-sectional views illustrating a method for manufacturing a first semiconductor stacked structure 160 according to an embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating a step of mounting second chiplet 140 on first carrier 200. As shown in FIG.

[0052] Referring to FIG. 5, a second chiplet 140 is mounted on a first carrier 200 . First, a first carrier 200 is provided. In one embodiment, the first carrier 200 may comprise a silicon-based material such as glass or silicon oxide, an organic material, or other material such as aluminum oxide, any combination of these materials, or the like. Thereafter, the second chiplet 140 is mounted on the first carrier 200 . In one embodiment, the second chiplet 140 is mounted on the first carrier 200 by a laser. The second chiplet 140 has an upper bonding pad 152 and an upper silicon insulating layer 154 formed on the second active region 141 for hybrid bonding.

[0053] FIG. 6 is a cross-sectional view illustrating a step of bonding first chiplet 130 to second chiplet 140. As shown in FIG. Referring to FIG. 6, the first chiplet 130 is bonded to the second chiplet 140 by hybrid bonding. In the first chiplet 130, a lower bonding pad 151 and a lower silicon insulating layer 153 for performing hybrid bonding are formed on the first active region 131. Bottom bond pad 151 on first chiplet 130 and top bond pad 152 on second chiplet 140 are directly bonded by metal-metal hybrid bonding. A metal-metal hybrid bond provides a metallurgical bond at the interface between lower bond pad 151 and upper bond pad 152 .

[0054] In one embodiment, bottom bond pad 151 and top bond pad 152 comprise copper. In another embodiment, the lower bond pad 151 and the upper bond pad 152 may be metallic materials that allow hybrid bonding. The lower bonding pad 151 and the upper bonding pad 152 are made of the same material, and there is no interface between the lower bonding pad 151 and the upper bonding pad 152 after hybrid bonding. First chiplet 130 is electrically connected to second chiplet 140 via bottom bonding pad 151 and top bonding pad 152 . The lower silicon insulating layer 153 and the upper silicon insulating layer 154 are directly bonded by non-metallic-non-metallic hybrid bonding. A covalent bond is formed at the interface between the lower silicon insulating layer 153 and the upper silicon insulating layer 154 by non-metallic-non-metallic hybrid bonding.

[0055] In one embodiment, the lower silicon insulating layer 153 and the upper silicon insulating layer 154 comprise silicon oxide or a TEOS forming oxide. In one embodiment, the lower silicon insulating layer 153 and the upper silicon insulating layer 154 are made of SiO 2 Includes. In one embodiment, the lower silicon insulating layer 153 and the upper silicon insulating layer 154 may be silicon nitrate, silicon acid nitrate, or other suitable dielectric material. In one embodiment, the lower silicon insulating layer 153 and the upper silicon insulating layer 154 include SiN or SiCN. The lower silicon insulating layer 153 and the upper silicon insulating layer 154 are made of the same material, and there is no interface between the lower silicon insulating layer 153 and the upper silicon insulating layer 154 after hybrid bonding.

[0056] FIG. 7 is a cross-sectional view illustrating the step of molding first chiplet 130 in first molding material 161 over second chiplet 140. As shown in FIG. Referring to FIG. 7, the first chiplet 130 is molded in a first molding material 161 over the second chiplet 140 . In one embodiment, the process of molding with the first molding material 161 includes a compression molding process or a transfer molding process. In one embodiment, the first molding material 161 includes an epoxy molding compound (EMC).

[0057] FIG. 8 is a cross-sectional view showing a step of planarizing the first molding material 161. As shown in FIG. Referring to FIG. 8, in order to level the top surface of the first molding material 161, chemical mechanical polishing (CMP) is performed. The top surface of the first molding material 161 is planarized by applying a CMP process. After performing the CMP process, the bottom surface of the first chiplet 130 and the bottom connection pads 133 are exposed from the first molding material 161 .

[0058] FIG. 9 is a cross-sectional view illustrating a step of forming connection members 135 on lower connection pads 133 of first chiplet 130. As shown in FIG. Referring to FIG. 9, a connection member 135 is formed on a lower connection pad 133 of a first chiplet 130 . In one embodiment, the connecting member 135 may include at least one of tin, silver, lead, nickel, copper, or an alloy thereof.

[0059] FIG. 10 is a cross-sectional view showing a step of de-bonding the first carrier 200 from the second chiplet 140. As shown in FIG. Referring to FIG. 10, the first carrier 200 is removed from the second chiplet 140 .

[0060] 11 to 17 are cross-sectional views illustrating a method for manufacturing a semiconductor package 100 according to an embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a step of forming a redistribution structure 120 on a second carrier 210. As shown in FIG. Referring to FIG. 11, a redistribution structure 120 is formed on a second carrier 210 .

[0061] First, a second carrier 210 is provided. In one embodiment, the second carrier 210 may comprise a silicon-based material such as glass or silicon oxide, an organic material, or other material such as aluminum oxide, any combination of these materials, or the like. Thereafter, the dielectric layer 121 is formed on the second carrier 210 . In one embodiment, the dielectric layer 121 comprises a photoimageable dielectric (PID) used in the redistribution process. A photoimageable insulator is a material that can be formed into fine patterns by applying a photolithography process. In one embodiment, the photoimageable dielectric (PID) may include a polyimide-based photopolymer, a novolac-based photopolymer, a polybenzoxazole, a silicon-based polymer, an acrylate-based polymer, or an epoxy-based polymer. In other embodiments, the dielectric layer 121 is formed of an inorganic dielectric material, such as silicon nitrate, silicon oxide, or the like. In one embodiment, the dielectric layer 121 may be formed by a CVD, ALD, or PECVD process.

[0062] After forming the dielectric layer 121, the dielectric layer 121 is selectively etched to form a via hole, and the via hole is filled with a conductive material to form a first redistribution via 122. Next, a dielectric layer 121 is additionally deposited on the first redistribution via 122 and the dielectric layer 121, the additionally deposited dielectric layer 121 is selectively etched to form an opening, and the opening is filled with a conductive material to form a first redistribution line 123. Next, a dielectric layer 121 is additionally deposited on the first redistribution line 123 and the dielectric layer 121, the additionally deposited dielectric layer 121 is selectively etched to form a via hole, and the via hole is filled with a conductive material to form a second redistribution via 124. Next, photoresist (not shown) is additionally deposited on the second redistribution via 124 and the dielectric layer 121, and the photoresist is selectively exposed and developed to form a photoresist pattern including a via hole, and the via hole is filled with a conductive material to form a bonding pad 125.

[0063] In one embodiment, the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, and the bonding pad 125 may include at least one of copper, aluminum, tungsten, nickel, gold, tin, titanium, and alloys thereof. In one embodiment, the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, and the bonding pad 125 are formed by performing a sputtering process. In another embodiment, the first redistribution via 122, the first redistribution line 123, the second redistribution via 124, and the bonding pad 125 are formed by performing an electrolytic plating process after forming a seed metal layer.

[0064] FIG. 12 is a cross-sectional view showing a step of mounting a first semiconductor stacked structure 160 on the redistribution structure 120. As shown in FIG. Referring to FIG. 12, a first semiconductor stacked structure 160 is mounted on the redistribution structure 120 by flip-chip bonding. The connection member 135 of the first semiconductor stacked structure 160 is bonded to the bonding pad 125 of the rewiring structure 120 to electrically connect the first semiconductor stacked structure 160 and the rewiring structure 120 .

[0065] FIG. 13 is a cross-sectional view showing a step of mounting a second semiconductor stacked structure 170 on the redistribution structure 120. As shown in FIG. Referring to FIG. 13, a second semiconductor stacked structure 170 is mounted on the redistribution structure 120 by flip-chip bonding. The first semiconductor stacked structure 160 and the second semiconductor stacked structure 170 are arranged side by side and horizontally at the same level. The connection member 172 of the second semiconductor stacked structure 170 is bonded to the bonding pad 125 of the rewiring structure 120 to electrically connect the first semiconductor stacked structure 160 and the rewiring structure 120 .

[0066] FIG. 14 is a cross-sectional view showing a step of hybrid bonding a bridge die 190 onto the upper surface of the first semiconductor stack structure 160 and the upper surface of the second semiconductor stack structure 170, and hybrid bonding a surface mounted device (SMD) 195 onto at least one of the upper surface of the first semiconductor stack structure 160 and the upper surface of the second semiconductor stack structure 170. Referring to FIG. 14, a bridge die 190 is hybrid bonded onto a portion of the top surface of the first semiconductor stack structure 160 and a portion of the top surface of the second semiconductor stack structure 170, and a surface mounted device (SMD) 195 is hybrid bonded onto at least one of the top surface of the first semiconductor stack structure 160 and the top surface of the second semiconductor stack structure 170.

[0067] A lower bonding pad 181 and a lower silicon insulating layer 183 for hybrid bonding are formed on the upper surface of the first semiconductor stacked structure 160 and the upper surface of the second semiconductor stacked structure 170, and an upper bonding pad 182 and an upper silicon insulating layer 184 for hybrid bonding are formed on the lower surface of the bridge die 190 and the lower surface of the surface mounted device (SMD) 195. The lower bonding pad 181 and the upper bonding pad 182 are directly bonded by metal-metal hybrid bonding. A metal-metal hybrid bond provides a metallurgical bond at the interface between lower bond pad 181 and upper bond pad 182 . In one embodiment, lower bond pad 181 and upper bond pad 182 comprise copper. In another embodiment, the lower bond pad 181 and the upper bond pad 182 may be a metallic material that allows hybrid bonding. The lower bonding pad 181 and the upper bonding pad 182 are made of the same material, and there is no interface between the lower bonding pad 181 and the upper bonding pad 182 after hybrid bonding. Via the lower bonding pad 181 and the upper bonding pad 182 , the first semiconductor stack structure 160 or the second semiconductor stack structure 170 is electrically connected to a bridge die 190 or a surface mounted device (SMD) 195 .

[0068] The lower silicon insulating layer 183 and the upper silicon insulating layer 184 are directly bonded by non-metallic-non-metallic hybrid bonding. A covalent bond is formed at the interface between the lower silicon insulating layer 183 and the upper silicon insulating layer 184 by non-metallic-non-metallic hybrid bonding. In one embodiment, the lower silicon insulating layer 183 and the upper silicon insulating layer 184 comprise silicon oxide or a TEOS forming oxide. In one embodiment, the lower silicon insulating layer 183 and the upper silicon insulating layer 184 are SiO 2 Includes. In one embodiment, the lower silicon insulating layer 183 and the upper silicon insulating layer 184 may be silicon nitrate, silicon acid nitrate, or other suitable dielectric material. In one embodiment, the lower silicon insulating layer 183 and the upper silicon insulating layer 184 may include SiN or SiCN. The lower silicon insulating layer 183 and the upper silicon insulating layer 184 are made of the same material, and there is no interface between the lower silicon insulating layer 183 and the upper silicon insulating layer 184 after hybrid bonding.

[0069] Figure 15 is a cross-sectional view showing a step of flip-chip bonding a bridge die 190 onto the upper surface of the first semiconductor stacked structure 160 and the upper surface of the second semiconductor stacked structure 170, following Figure 13, and flip-chip bonding a surface-mounted device (SMD) 195 onto at least one of the upper surface of the first semiconductor stacked structure 160 and the upper surface of the second semiconductor stacked structure 170. FIG. 15 is a cross-sectional view showing a method for manufacturing the semiconductor package 100 according to the alternative embodiment of FIG. The method of manufacturing the semiconductor package 100 according to the embodiment of the present invention shown in FIG. 16 and FIG. 17 can be applied to the method of manufacturing the semiconductor package 100 according to the other embodiment of FIG.

[0070] In FIG. 14 , the first semiconductor stack structure 160 and the bridge die 190, the first semiconductor stack structure 160 and the surface mount device (SMD) 195, the second semiconductor stack structure 170 and the bridge die 190, and the second semiconductor stack structure 170 and the surface mount device (SMD) 195 are connected by hybrid bonding, whereas in FIG. 15 , the first semiconductor stack structure 160 and the bridge die 190, the first semiconductor stack structure 160 and the surface mount device (SMD) 195, the second semiconductor stack structure 170 and the bridge die 190, and the second semiconductor stack structure 170 and the surface mount device (SMD) 195 are connected by flip chip bonding. Flip chip bonding is performed by performing a reflow process.

[0071] FIG. 16 is a cross-sectional view showing a step of molding the first semiconductor stack structure 160, the second semiconductor stack structure 170, the bridge die 190, and a surface mount device (SMD) 195 with a second molding material 162 on the rewiring structure 120. Referring to FIG. 16, the first semiconductor stack structure 160, the second semiconductor stack structure 170, the bridge die 190, and a surface mount device (SMD) 195 are molded in a second molding material 162 on the redistribution structure 120. In one embodiment, the process of molding with the second molding material 162 includes a compression molding or transfer molding process. In one embodiment, the second molding material 162 includes an epoxy molding compound (EMC).

[0072] FIG. 17 is a cross-sectional view showing a step of de-bonding the second carrier 210 from the redistribution structure 120. As shown in FIG. Referring to FIG. 17, the second carrier 210 is removed from the rewiring structure 120. Then, as shown in FIG. 1, an external connection structure 110 is formed on the bottom surface of the redistribution structure 120. As shown in FIG. An insulating layer 112 is formed on the bottom surface of the dielectric layer 121 of the redistribution structure 120 , and a conductive pad 111 is formed under the first redistribution via 122 .

[0073] In one embodiment, the conductive pads 111 may include at least one of copper, nickel, zinc, gold, silver, platinum, palladium, chromium, titanium, and alloys thereof. In one embodiment, the insulating layer 112 comprises a solder resist. In one embodiment, the external connection members 113 may include at least one of tin, silver, lead, nickel, copper, or alloys thereof. In one embodiment, the conductive pad 111 is formed by a sputtering process or by forming a seed metal layer and then performing an electrolytic plating process. In one embodiment, the insulating layer 112 may be formed by a CVD, ALD, or PECVD process.

[0074] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0075] 100 Semiconductor Packages 110 External connection structure 111 Conductive Pad 112 Insulating layer 113 External connection parts 120 Rewiring Structure 121 First dielectric layer 122 1st Redistribution Via 123 First Rewiring Line 124 2nd Redistribution Via 125 Bonding Pad 130 First Chiplet 131 1st active region 132 First Chiplet Base 133 Bottom Connection Pad 134 1st Through Silicon Via 135 Connection parts 140 Second Chiplet 141 2nd active region 142 Second Chiplet Base 143 2nd Through Silicon Via 144 Top Connection Pad 150 First interconnect structure 151 Bottom Bonding Pad 152 Top Bonding Pad 153 Lower silicon insulating layer 154 Upper silicon insulating layer 160 First semiconductor laminated structure 161 First molding material 162 Second molding material 170 Second semiconductor laminated structure 171 Top Connection Pad 172 Connection parts 180A, 180B Second interconnect structure 181 Bottom Bonding Pad 182 Top Bonding Pad 183 Lower Silicon Insulation Layer 184 Upper silicon insulating layer 185 Bottom Connection Pad 186 Connection parts 187 Bottom Connection Pad 190 Bridge Die 191 Bottom Connection Pad 192 Connection Line 193 Bridge Die Base 195 Surface Mount Devices (SMD) 200 1st Career 210 Second Career

Claims

1. a rewiring structure; a first semiconductor stack on an upper surface of the redistribution structure; wherein the first semiconductor stacked structure includes a first chiplet and a second chiplet disposed on the first chiplet, a second semiconductor stack structure disposed side by side with the first semiconductor stack structure on an upper surface of the redistribution structure; a bridge die disposed on the first semiconductor stacked structure and the second semiconductor stacked structure, electrically connecting the first semiconductor stacked structure and the second semiconductor stacked structure; a surface mounted device (SMD) on a top surface of at least one of the first semiconductor stack and the second semiconductor stack.

2. The semiconductor package of claim 1 , wherein the first semiconductor stacked structure and the second semiconductor stacked structure exchange signals through the bridge die.

3. The semiconductor package of claim 1 , wherein the first chiplet includes a first active area located on a surface facing the second chiplet.

4. The semiconductor package of claim 3 , wherein the first chiplet comprises a plurality of first through silicon vias extending downward from the first active area to a rear surface of the first chiplet.

5. The semiconductor package of claim 1 , wherein the second chiplet includes a second active area located on a surface facing the first chiplet.

6. The semiconductor package of claim 5 , wherein the second chiplet comprises a plurality of second through silicon vias extending upward from the second active region to a rear surface of the second chiplet.

7. The semiconductor package of claim 6 , wherein each of the plurality of second through silicon vias is electrically connected to the bridge die or the surface mount device.

8. the first chiplet has a first footprint; the second chiplet has a second footprint; 2. The semiconductor package of claim 1, wherein the first footprint is within the second footprint.

9. a rewiring structure; a first semiconductor stack on the rewiring structure; Here, the first semiconductor stacked structure is a first chiplet; and a first molding material that molds a side surface of the first chiplet; a second chiplet on the first chiplet and on the first molding material; wherein the first chiplet is disposed between the redistribution structure and the second chiplet; a first interconnect structure between the first chiplet and the second chiplet; a second semiconductor stack structure disposed side by side with the first semiconductor stack structure on the redistribution structure; a bridge die disposed on the first semiconductor stacked structure and the second semiconductor stacked structure, the bridge die electrically connecting the first semiconductor stacked structure and the second semiconductor stacked structure; a surface mounted device (SMD) disposed on at least one of the first semiconductor stack and the second semiconductor stack; A semiconductor package comprising: a second molding material covering the first semiconductor laminated structure, the second semiconductor laminated structure, the bridge die, and the surface-mounted device on the rewiring structure.

10. The semiconductor package of claim 9 , wherein the first chiplet includes a central processing unit (CPU) or a graphic processing unit (GPU).

11. The semiconductor package of claim 9 , wherein the second chiplet comprises an SRAM.

12. 10. The semiconductor package of claim 9, wherein the second semiconductor stack structure comprises a high bandwidth memory (HBM).

13. The semiconductor package of claim 9 , wherein the surface mount device comprises a capacitor structure.

14. 10. The semiconductor package of claim 9, further comprising a second interconnect structure between the first semiconductor stack structure, the second semiconductor stack structure, and the bridge die.

15. The semiconductor package of claim 14 , wherein the second interconnect structure comprises a microbump.

16. The second interconnect structure comprises: a first silicon insulating layer and a first plurality of bonding pads on a top surface of the second chiplet and on a top surface of the second semiconductor stack; 15. The semiconductor package of claim 14, further comprising a second plurality of bonding pads and a second silicon insulating layer on a bottom surface of the bridge die.

17. 17. The semiconductor package of claim 16, wherein each of the first bonding pads of the plurality of first bonding pads is directly bonded to each of the second bonding pads of the plurality of second bonding pads.

18. 17. The semiconductor package of claim 16, wherein the first silicon insulating layer is directly bonded to the second silicon insulating layer.

19. Mounting a first semiconductor stack on the redistribution structure; wherein the first semiconductor stack includes a first chiplet and a second chiplet on the first chiplet; mounting a second semiconductor stack over the redistribution structure, side by side with the first semiconductor stack; mounting a bridge die on the first semiconductor stack and on the second semiconductor stack; Here, the bridge die is located on the first semiconductor stacked structure and the second semiconductor stacked structure, and the bridge die electrically connects the first semiconductor stacked structure and the second semiconductor stacked structure; and mounting a surface mount device (SMD) on at least one of the first semiconductor stack and the second semiconductor stack.

20. 20. The method of claim 19, wherein the bridge die is mounted on the first semiconductor stack and the second semiconductor stack by hybrid bonding.

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