Superjunction mosfet

Abstract

To provide a method for filling a trench formed in a silicon substrate, which has a small opening width and a large aspect ratio, by high-speed epitaxial growth while preventing the opening from being blocked.SOLUTION: A silicon substrate having a high aspect ratio trench formed therein is subjected to selective epitaxial growth at a growth temperature set in the range of 950°C to 1050°C such that the opening of the trench is not blocked. Hydrogen chloride gas is added to a reaction gas having a high concentration of silane chloride as a silicon source in an amount corresponding to the aspect ratio of the trench, and the trench is filled by epitaxial growth at a high growth rate within the range in which blocking does not occur.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device having a superjunction structure. [Background technology]

[0002] In recent years, power semiconductors using SiC and GaN have been put to practical use. However, Si power semiconductors are now being manufactured using 300mmφ substrates, and cost performance has not caught up with Si-based semiconductors. For Super Junction MOSFETs (SJMOS), the cost of the epitaxial growth process has been reduced by about half by using 300mmφ substrates, and the epitaxial layers of the multi-epi method have been multi-layered to about 12 layers, realizing finer design, reducing on-resistance and costs. For Insulated Gate Bipolar Transistors (IGBTs), the cost of IGBT modules is being reduced by using RC-IGBT technology, which incorporates diodes to create a single chip.

[0003] However, while larger diameters of 300 mm have been gradually achieved, development activities aimed at further improving the performance of Si power semiconductor elements through further miniaturization have stagnated. As an example, only a very small number of companies are developing trench-fill type SJMOS. In the four or five years after 2008, four or five companies sold new generation SJMOS products with trench-fill type elements. However, for the next high-performance generation of SJMOS, many companies have reverted back to multi-epi type products. After that, after Infineon sold a multi-epi type SJMOS (C7) with extremely low on-resistance, no SJMOS products with higher performance than that were released for nearly ten years.

[0004] The manufacturing technology of trench-fill type silicon SJMOS commercialized by major power semiconductor manufacturers around 2008 was based on the manufacturing method of DRAM trench capacitors in which the blocking of the trench opening is etched back with HCL in accordance with Non-Patent Document 1, or the manufacturing method based on the technology using the LPCVD trench filling method. From 200 mmφ, it has been adopted for product manufacturing by compensating for the decrease in productivity of radiant heating type single wafer epitaxial equipment with a load lock mechanism and high-speed growth as a slip countermeasure. The idea that reaction-limited growth is desirable to prevent the growth rate from increasing locally at the trench opening was explained in early trench fill patents, and Aurhenius plots and the like were also mentioned (Patent Document 1), but there was no concrete response to the decrease in growth rate until Patent Document 2. Trench-fill epitaxial growth technology was developed by device manufacturer engineers, not by AMAT process engineers of the equipment manufacturer. Perhaps for this reason, silicon epitaxial growth was attempted under low pressure conditions. In single-wafer equipment, problems of uniform gas-phase reaction and wall deposition occurred under low pressure conditions of less than one-tenth of atmospheric pressure, and the mean free path could not be increased as in LPCVD. Productivity could not be increased due to problems such as clogging at the opening and low growth rate. Quantitative studies on the transport of the source to the growth surface had been mainly performed by equipment manufacturers until then, but detailed studies on uniform epitaxial growth on a step-shaped growth surface had not been performed by equipment manufacturer engineers. This is thought to be the background behind the established recognition that the practical application of trench-fill epitaxial technology is not realistic.

[0005] For silicon-based power semiconductors, the use of 300mmφ wafers, which are effective in reducing costs, has expanded, and the manufacturing costs of IGBTs and MOSFETs have been reduced. For IGBTs, energy saving at the module stage using RC-IGBT technology is also being promoted. To reduce on-resistance, the manufacturing of superjunction MOSFETs used as 600V-class switching elements has been scaled down to 300mmφ, halving the cost of the epitaxial process, and multi-epi has been scaled up to about 12 layers, achieving finer design and lower costs. Elements using GaN on Si substrates are gradually coming into use. Although some efforts are being made to scale down to 200mmφ, it is difficult to handle elements with large currents, so silicon superjunctions are being scaled down to 300mmφ and production volume is increasing. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2001-127289 A [Patent Document 2] Patent No. 7303971 [Non-patent literature]

[0007] [Non-Patent Document 1] S.Yamauchi,et.al,Proc.ISPSD 2001,p363 Summary of the Invention [Problem to be solved by the invention]

[0008] Around 2008, when development of manufacturing methods for superjunction MOSFET was actively progressing, the deep trench method was thought to have the following advantages over the multi-epi method: 1) it was easier to miniaturize, 2) it required fewer steps, and 3) it could be manufactured at low cost. However, in the subsequent development of the deep trench method, it was recognized that in order to fill the trench by epitaxial growth without generating voids, the epitaxial growth rate had to be extremely slow. As a result, with regard to miniaturization, the opening of the trench is prone to blockage, and miniaturization beyond that achieved by the multi-epitaxial method has not been achieved. The reason why the deep trench method could not be miniaturized and productivity could not be improved is thought to be that the process engineers of the equipment manufacturers, who had been developing and guiding the process technology of silicon epitaxial growth, are no longer active, and the epitaxial engineers of the device manufacturers are now developing the technology. Most device manufacturers have used dichlorosilane as the silicon source, which is easy to install and manage the supply equipment. This makes it difficult to use a high-concentration silicon source, making it difficult to carry out reaction-rate-limited epitaxial growth. As a result, it is difficult to suppress the generation of voids and fill a narrow trench opening. Since Patent Document 1 has made it possible to put into practical use a fine and high aspect ratio trench fill method, it is necessary to further reduce the on-resistance.

[0009] Until then, epitaxial growth was performed under diffusion-limited conditions, and the amount of silicon source supplied to the entire flat epitaxial substrate surface was constant by controlling the flow of reaction gas, achieving thickness variation of less than 2% even at high growth rates. The effective surface area of ​​the fine trench substrate was misunderstood, and the fundamental idea of ​​what epitaxial growth conditions should be used to fill the trench by epitaxial growth was not clearly defined, which is thought to be the reason why the trench-filling epitaxial growth method did not produce the desired results. In order to achieve uniform epitaxial growth on the surface of a trench-shaped substrate, epitaxial growth under reaction-limited conditions is necessary. In reaction-limited epitaxial growth, it is necessary to consider the supply of the silicon source while taking into account the crystal orientation of the substrate and the behavior of the adsorption source on the surface, but it must be said that the epitaxial engineers of device manufacturers did not have sufficient knowledge of the orientation of silicon single crystals. The results in Patent Document 1 show that by considering these factors comprehensively, it is possible to avoid the occurrence of voids even at relatively high growth rates. Although the practical application of GaN on Si switching elements is progressing, we should not hastily conclude that there is no possibility of further reducing the on-resistance and achieving cost reductions in silicon-based superjunction MOSFETs.

[0010] Cost reduction has been an important issue for superjunction MOS SFET, but the proportion of the epitaxial growth process in the cost structure is high, and it is not easy to reduce the cost by using single-wafer epitaxial equipment. Reducing the on-resistance by miniaturization, i.e., reducing the cell pitch, is an effective cost reduction measure. The above-mentioned Patent Document 1 shows a technology for filling trenches at a relatively high speed while suppressing the occurrence of voids even if the cell pitch is reduced. Based on this technology, it is desired to further realize an on-resistance close to GaN on Si at low cost for Si devices by reducing the pitch (cell pitch) of p-type and n-type columns of SJMOS. [Means for solving the problem]

[0011] The invention described in claim 1 is a superjunction MOSFET (SJMOSFET) characterized in that the sidewalls in the vertical direction of the p-type pillars are flat and have a substantially constant width from the top to the bottom. This SJMOSFET is manufactured using a trench-fill type manufacturing method. However, instead of forming a stripe-shaped trench in an n-type epitaxial layer of an n / n+ type substrate and forming a p-type pillar by p-type epitaxial growth as has been conventionally done, an epitaxial substrate having a p / n / n+ structure is used, and a trench is formed by RIE or the like so that the bottom of the trench is located in the n-type epitaxial layer and the trench is filled by epitaxial growth of an n-type dopant concentration that does not cause voids or crystal defects and does not cause charge imbalance with the p-type pillars, thereby forming a superjunction (SJ) structure in which p-type and n-type pillars having a shape close to a rectangular parallelepiped are alternately arranged.

[0012] Since this method does not use the multi-epitaxial method, there is no big problem in forming the side of the pillar flat even if the pillar is miniaturized. In addition, when forming a trench to form p-type and n-type pillars, a p / n / n+ substrate is used to make the p-type layer of the epitaxial substrate into a p-type pillar, so by digging the trench to the n-type layer below the p-type epitaxial layer, the width of the p-type pillar can be made constant to the bottom. The width of the trench filled by the n-type epitaxial growth is set to a range that can suppress the generation of voids and does not reduce productivity. Conventionally, if voids or crystal defects exist in the n-type pillar through which the drift current flows, leakage current and hot spots occur, reducing the characteristics and life of the element, so in n-channel MOS, the n-type epitaxial layer of the n / n+ substrate has been used in the n-type pillar part through which the drift current flows, because it has no crystal defects and the impurity concentration and its in-plane distribution can be strictly controlled. In this method, for example, by performing trench-filling epitaxial growth using the method of Patent Document 1, no voids are generated even when the n-type pillar portion is formed by epitaxial growth, and the crystal defects are at the same level as the n layer of the n / n+ substrate. Figure 7 is an example of an SEM photo after defect etching of the (110) cleavage plane of the SJ structure after trench filling using the method of Patent Document 1. No difference is observed in the crystallinity of the pn pillar. The resistivity of the n-type filling region cannot be accurately evaluated, but since it is filled by reaction-limited epitaxial growth, it is approximately constant at the SIMS level. It can be understood that the method described above can form p-type and n-type pillars in a fine shape close to a rectangular parallelepiped.

[0013] There are rare proposals for a manufacturing method in which an n-type trench is formed in a p / n+ substrate and pillars are formed by buried epitaxial growth. In this case, no specific measures are shown for the problem of how to align the bottom of the n-type trench with the surface of the n+ type substrate. In this method, the position of the bottom of the p-type pillar can be set to the bottom of the p-type epitaxial layer, so the length of the p-type pillar can be controlled with high precision. The shape of the p-type pillar manufactured by the deep trench method is shown in Figure 9 as an image of the analysis results of some commercially available products, but compared to the multi-epi method, the tip is thin and the shape of the bottom tends to be round. In this manufacturing method, the width of the narrow p-type pillar can be made into a constant rectangular parallelepiped shape from the surface to the bottom, and the imbalance (charge imbalance) of the doping amount between the n-type and p-type pillars can be reduced. As a result, it becomes possible to realize withstand voltage and on-resistance characteristics close to the design values.

[0014] The invention of claim 2 is a manufacturing method of an SJ structure characterized in that, in forming an SJ structure by the manufacturing method of claim 1, in the step of forming a striped trench in a p-type epitaxial layer, since there is no need to worry about voids or crystal defects being generated in the p-type silicon layer sandwiched between the trenches, the width of the trench can be narrowed within a range that does not affect the accuracy and quality of the trench processing relative to the width of the trench, and the width of the p-type column is narrowed within that range to reduce the cell pitch of the pn column of the SJ structure, and the superjunction MOSFET characterized in that the leakage current of the element is suppressed and a desired breakdown voltage is ensured by doping the impurity concentrations of the p layer, n layer, and trench-filled n-type epitaxial layer of the p / n / n+ substrate to the impurity concentrations of the n-type pillar and p-type pillar that do not cause charge imbalance, which is calculated for the dimensions of the n-type and p-type pillars.

[0015] When forming a stripe-shaped trench in a p-type epitaxial layer, even if the width of the trench and the p-type silicon layer sandwiched between the trenches are made smaller than the width of the trench, the difficulty of suppressing the occurrence of voids in the epitaxial growth that fills the trench does not change significantly, so if the cell pitch of the pn column of the SJ structure is 6 μm (3 μm + 3 μm), the cell pitch can be made 4.0 μm by making the p-type column 1.0 μm. This reduces the on-resistance by up to 33%. Since the width of the buried trench is 3 μm, the conditions for the buried epitaxial growth that do not generate voids do not change, so it is expected that costs can be reduced by the reduction in on-resistance and the reduction in chip size. Effect of the Invention

[0016] In the study of manufacturing technology for SJMOS using the trench-fill method, it was believed that elements with low on-resistance could be manufactured at low cost because miniaturization is easily achieved and there are few processes, but the problem of voids occurring when filling fine, high aspect ratio trenches by epitaxial growth has meant that it has not been as good as the multi-epi method. One manufacturing technology that is effective in solving this problem is proposed in Patent Document 1, and by using this method, it is possible to manufacture even finer SJ structures with higher aspect ratios, making it possible to manufacture SJMOS elements with characteristics close to those of switching elements using GaN on Si at low cost. [Brief description of the drawings]

[0017] [Figure 1] 1A to 1C are schematic cross-sectional views of two examples of typical semiconductor devices according to the present invention. [Diagram 2] 1A to 1C are schematic diagrams illustrating the steps of manufacturing a substrate for a superjunction MOSFET according to the present invention. [Diagram 3] Schematic diagrams of the process from trench processing to epitaxial growth to fill the trench for a superjunction MOSFET using this method. (d) to (f) [Figure 4]Schematic diagrams of the removal process by polishing of the trench-filled epitaxial overgrowth layer of a superjunction MOSFET according to the present method. (g) to (h) [Diagram 5] This is a schematic diagram of the process for forming the source and gate of a planar type superjunction MOSFET. (p1)~(p2) [Figure 6] Schematic diagrams of the source and gate formation process of a trench-gate type superjunction MOSFET. (t1) to (t3) [Figure 7] 1 is an SEM photograph of the (110) cleavage plane of the SJ structure region after defect etching using the method described in Patent Document 1. [Figure 8] Theoretical formulas for pn column pitch size and on-resistance of SJ structure, approximate actual values ​​for various methods, and rough predicted values ​​from simulation of this method [Figure 9] Examples and cross-sectional images of some deep trench type commercially available products DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The semiconductor device according to this embodiment includes planar type and trench gate type SJMOSFETs. Since the initial manufacturing process is the same, the manufacturing method of the planar type SJMOSFET will be explained first until the end, and then the manufacturing method of the trench gate type SJMOSFET will be explained focusing on the differences from the manufacturing method of the planar type.

[0019] FIG. 1 shows a schematic diagram of the cross-sectional shape of a planar type and a trench gate type SJMOSFET product. FIG. 2 and subsequent figures show a schematic flow of the manufacturing process. In this embodiment, a p / n / n+ type epitaxial substrate is first prepared. The semiconductor device is a vertical MOSFET with a superjunction structure. The semiconductor substrate is an n+ type single crystal silicon mirror substrate 11, which may be arsenic doped, phosphorus or antimony doped, on which an n type silicon epitaxial layer 12 is provided. Furthermore, a first layer of a p type epitaxial layer 13 is formed on the n type epitaxial layer 12.

[0020] The thickness of the p-type epitaxial layer is set to be slightly thicker than the length of the p-type pillar, which determines the breakdown voltage of the SJMOSFET. Next, the width of the trench and the distance between the trenches are appropriately set on the p-type epitaxial layer, a mask film 14 is formed from an oxide film or a resist film, and etching is performed to the bottom of the second n-type epitaxial layer by the RIE method, preferably the Bosch method used for deep etching, to form a trench 15. At this time, the bottom surface of the p-type pillar becomes the bottom surface of the first p-type epitaxial layer, and if the impurity concentrations of the trench epitaxial layer and the second epitaxial layer are equal, the cross-sectional shape of the bottom of the trench will be rectangular.

[0021] The Bosch process, a type of RIE widely used for deep etching to create through-silicon vias (TSVs) used in 3D packaging, can perform vertical, high-speed deep etching with an aspect ratio of 50 or more by suppressing sidewall etching through alternating passivation and etching modes. However, at an etching speed of about 10 μm / min, scallops with unevenness of 30 to 80 nm are generated on the sidewalls. The unevenness of the scallops can be flattened to a certain extent by appropriately setting the conditions for pre-annealing in a hydrogen atmosphere at around 1050°C before the start of trench-filling epitaxial growth.

[0022] After the trench etching is completed, if a resist is used as a mask, it is removed. If an oxide film is used as a mask, it may be removed or left. Below, the case where the oxide film is left and the embedding epitaxial process is performed will be described. The conditions for trench embedding epitaxial growth are described in detail in Patent Document 1. The gist of the method is to adjust the flow rate, composition, reaction temperature, and amount of HCL added as the reaction product of the supply gas so that the amount of silicon source consumed per unit time by the epitaxial reaction on the entire growth surface of the substrate on which the trench is formed exceeds the amount of silicon source supplied thereto, so that the epitaxial growth is reaction-limited, and to embed the trench at a high growth rate within a range where the generation of voids can be suppressed. A trench with a trench width of 3 μm and an aspect ratio of 20 or more can be embedded in a relatively short time without the generation of voids.

[0023] The silicon is grown slightly oversized so that the trench is completely filled, and that area is removed by polishing. The oxide film 17 used as a mask in the trench etching is used as a polishing stopper and to recreate the alignment mark, and then the SJ structure with repeated pn pillars is exposed on the surface (Fig. 4(h)). Figure 5 shows an overview of the method for creating an element with a planar SJMOSFET structure. By devising an alignment method, a p-well 21, gate oxide film 22, gate electrode 23, n+ source 20, interlayer insulating film, etc. are formed in appropriate positions, and an electrode is formed on the drain 25 back-wrapped with the epitaxial n+ substrate to create an element with a planar SJMOSFET structure, but the diagram has been simplified by omitting some of the interlayer insulating film and electrodes to the extent that the basic structure can be understood.

[0024] Recently, MOSFETs with a trench gate structure, which have excellent performance, have come to be used more often. An overview of the manufacturing process for creating a MOSFET with this structure is shown in Figure 6 (T1) to (T3). The substrate process (T1), in which a p-type base layer 30 is deposited by epitaxial growth, is unique. Most of the electrodes and interlayer insulating films are omitted. An n-type low-resistance source region 31, a gate oxide film 32, and a gate electrode 33, which is mainly made of polysilicon, are formed. In this case, electrons flow vertically in the FET region toward the bottom surface of the substrate, and the initial n+ substrate is thinned by backlapping to become the drain 34.

[0025] In this method, trench-filled epitaxial growth can be used for both n-type and p-type pillar formation, but the feature is that the trench-filled epitaxial growth method is not used for p-type pillar formation, and instead, the pillar is miniaturized using a p-type substrate to increase its aspect ratio. Since the p-type pillar is not formed by trench-filled epitaxial growth, the problem of voids does not occur. The n-type pillar is formed by trench-filled epitaxial growth with a width in a range where voids do not occur. The cell pitch of the pn pillar can be reduced accordingly, so the on-resistance can be reduced. When the width of the p-type pillar is miniaturized, the charge balance between the p-type and n-type will be poor unless the shape is processed with high precision. However, since the Bosch method can form trenches wider than 1 μm in width with a high aspect ratio, it is possible to perform high-precision processing to leave a 1.5 μm-wide p-type pillar without any problems, so it is quite possible to reduce the charge imbalance caused by the pillar width to 5% or less.

[0026] In many cases, an SJ structure is used in which the width of the n-type pillar through which the charge flows is somewhat wider. By slightly lowering the impurity concentration so that the decrease in the p-type and n-type charge balance does not cause a significant decrease in the breakdown voltage or a large increase in the on-resistance, the effect of miniaturization is hardly reduced. In this method, the length of the p-type pillar, which determines the breakdown voltage of the SJMOSFET, is set to be slightly longer than the set breakdown voltage. Next, the width of the trench and the distance between the trenches are appropriately set on the p-type epitaxial layer, a mask film is formed using an oxide film or a resist film, and a trench is formed by etching to the bottom of the second layer of n-type epitaxial layer using the RIE method, preferably the Bosch method used for deep etching. At this time, the bottom surface of the p-type pillar becomes the bottom surface of the first epitaxial layer (p-type), and if the n-type impurity concentration of the trench epitaxial layer and the second epitaxial layer are equal, the cross-sectional shape of the bottom of the trench is a rectangular parallelepiped.

[0027] In single-wafer epitaxial equipment, the impurity concentration can be controlled within the range of ±2.0%, so there is no decrease in breakdown voltage or significant increase in on-resistance due to charge imbalance. In this manufacturing method, the width of the p-type pillar is 1.0 μm, and the on-resistance of a 600V-class SJMOS in which a 3.0 μm-wide trench is filled by n-type epitaxial growth is theoretically 6.5 mΩcm-cm2, but the question is what level of on-resistance can be obtained in an actual device. In order to estimate this actual on-resistance, the on-resistance calculated from the cell pitch values ​​of two companies reported in a SEMI seminar on one commercially available multi-epi method company and one trench-fill method company, and the on-resistance values ​​published by each company according to their own standards are plotted as a relationship between cell pitch and on-resistance in Figure 8. Assuming that charge imbalance etc. will be at the same level, the actual on-resistance of the theoretical value of 6.5 mΩcm-cm2 when the cell pitch is 4.0 μm using this manufacturing method is estimated to be at most 7.2 mΩcm-cm2. It is expected that an element with an on-resistance nearly 30% smaller will be obtained, even compared to SJMOS, which has been said to have the best on-resistance characteristics commercially available with a cell pitch of around 5.5 μm using the multi-epi method. Of course, the on-resistance will be smaller than the results of the simulation of the SJMOS characteristics with a 3 μm + 3 μm pitch in Patent Document 1. Figure 9 shows an image based on an element analysis report of an estimated element cross-sectional structure with a cell pitch of 4.0 μm using this method and a cell pitch of 7.9 μm using the commercially available deep trench method. It can also be seen that with this manufacturing method, the shape of the p-type pillars becomes rectangular, making it easier to reduce charge imbalance.

[0028] A simple comparison of costs is difficult because it depends on the manufacturing equipment, but for the manufacture of 600V-class SJMOS, miniaturization is required with 12 to 13 layers of epitaxial growth to achieve a low on-resistance of about 10mΩ-cm2. Under these conditions, the deep trench method is expected to have lower epitaxial process costs using single-wafer equipment. Both methods can be scaled down to 300mmφ, so it is estimated that this manufacturing method has ample potential for cost reduction. This method makes miniaturization easy, and it may be possible to achieve characteristics that are quite close to the on-resistance of GaN on Si, and considering the ease of scaling up, it is believed that the cost advantage will remain unchanged from the current situation. [Explanation of symbols]

[0029] 11 n+ type low resistance silicon mirror substrate, 12 n type epitaxial layer (second layer), 13 p-type epitaxial layer (second layer), 14 RIE mask film, 15 deep trench, 16 buried epitaxial layer (n-type), 17 mask oxide film, 20 p well, 21 n+ source, 22 gate oxide film, 23 gate electrode, 24 source electrode, 25 n+ drain, 29 gate trench, 30 p-type base layer, 31 n+ source, 32 gate oxide film, 33 gate electrode, 41 Buried epitaxial layer (p-type), 42 Overgrowth layer (p-type) 43 n-type pillar, 44 n-type epitaxial layer (n / n+)

Claims

1. A superjunction MOSFET (SJMOSFET) characterized in that the sidewalls of the p-type pillars in the vertical direction are flat and have a constant width from the top to the bottom. This SJMOSFET is manufactured using a trench-fill type manufacturing method, but instead of forming a stripe-shaped trench in an n-type epitaxial layer of an n / n+ type substrate and forming a p-type pillar by p-type epitaxial growth as has been conventionally done, an epitaxial substrate with a p / n / n+ structure is used, and a trench is formed by RIE or the like so that it penetrates the p-type epitaxial layer and the bottom of the trench is located at the center-lower part of the n-type epitaxial layer, and the trench is filled by epitaxial growth of an n-type dopant concentration that does not cause voids or crystal defects and does not cause charge imbalance with the p-type pillars, thereby forming a superjunction (SJ) structure in which p-type and n-type pillars shaped like rectangular parallelepipeds are alternately arranged.

2. In forming an SJ structure by the manufacturing method of claim 1, in the step of forming a stripe-shaped trench in a p-type epitaxial layer, since there is no need to worry about voids or crystal defects occurring in the p-type silicon layer sandwiched between the trenches, the width of the trench can be narrowed to a range that does not affect the accuracy and quality of the trench processing relative to the width of the trench, and therefore the width of the p-type column is narrowed within that range to reduce the cell pitch of the pn column of the SJ structure. A superjunction MOSFET having an SJ structure according to claim 1, characterized in that the p layer and n layer of the p / n / n+ substrate and the n-type trench buried layer are doped to have impurity concentrations in the n-type pillar and p-type pillar that do not cause charge imbalance calculated for the dimensions of the n-type and p-type pillars, thereby suppressing the leakage current of the element and ensuring the desired breakdown voltage.

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