Contact structure for three-dimensional memory

Abstract

To provide a contact structure for 3D memory capable of providing electric connections between word lines of perpendicularly stacked memory cells and a control gate without using a staircase structure.SOLUTION: There are disclosed a 3D memory structure and an embodiment of a method for forming the 3D memory structure. A fabrication method includes a step of arranging alternate dielectric stacks on a substrate, and the alternate dielectric stacks have a first and a second dielectric layer stacked alternately thereupon. Then a plurality of contact openings may be formed in the alternate dielectric stacks so that pairs of dielectric layers may be exposed inside at least one of the plurality of contact openings. The method further includes the steps of: substituting conductive layers for second dielectric layers to form film stacks of alternate conductive layer and dielectric layers; and forming a contact structure so as to come into contact with conductive layers in the film stacks of the alternate conductive layers and dielectric layers.SELECTED DRAWING: Figure 20

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates generally to the field of semiconductor technology, and more particularly to methods for forming three-dimensional (3D) memories. [Background technology]

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells.

[0003] In 3D NAND memory, a staircase structure is typically used to provide electrical contact between the word lines and control gates of vertically stacked memory cells. However, as memory capacity continues to increase in 3D NAND memory, the number of vertically stacked memory cells is greatly increased. Thus, the lateral dimensions of the staircase structure are also increased, which reduces the effective memory capacity per unit area. Furthermore, a larger staircase structure leads to greater mechanical stress between the memory array region and the staircase region, which may cause reliability issues in 3D NAND memory. Summary of the Invention [Problem to be solved by the invention]

[0004] Therefore, there is a need for a 3D memory contact structure that can provide electrical coupling between the word lines and control gates of vertically stacked memory cells without using staircase structures. [Means for solving the problem]

[0005] DETAILED DESCRIPTION OF THE DRAWINGS Embodiments of three-dimensional (3D) memory devices and methods for forming three-dimensional (3D) memory devices are described in this disclosure.

[0006] A first aspect of the present disclosure provides a method for forming a three-dimensional (3D) memory device, comprising disposing an alternating dielectric stack on a substrate, the alternating dielectric stack comprising first and second dielectric layers alternately stacked on top of each other. The method also comprises forming a plurality of contact openings in the alternating dielectric stack such that the dielectric layer pair is exposed inside at least one of the plurality of contact openings, the dielectric layer pair comprising a pair of the first and second dielectric layers. The method further comprises replacing the second dielectric layer with a conductive layer to form a film stack of alternating conductive and dielectric layers, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

[0007] Forming the plurality of contact openings includes forming a plurality of openings in the alternating dielectric stack by etching N dielectric layer pairs, where N is an integer. A mask is then formed to protect a first group of the plurality of openings and expose a second group of the plurality of openings, where the first group of the plurality of openings is a first subset of openings that extends through the N dielectric layer pairs. Forming the plurality of contact openings further includes forming a second subset of openings in the second group of the plurality of openings by etching M dielectric layer pairs, where M is an integer. The second subset of openings extends through (N+M) dielectric layer pairs. By repeating the steps of forming the mask and etching for each of the subset of openings, a plurality of contact openings can be formed in the alternating dielectric stack.

[0008] In some embodiments, the first and second subsets of apertures comprise the same number of apertures.

[0009] In some embodiments, M dielectric layer pairs is twice as many as N dielectric layer pairs.

[0010] In some embodiments, forming the film stack of alternating conductive and dielectric layers includes forming a slit opening in the alternating dielectric stack, hi some embodiments, forming the film stack also includes forming a common source contact in the slit opening that is electrically coupled to the substrate.

[0011] In some embodiments, the method for forming a 3D memory structure further includes disposing a fill material inside the plurality of contact openings.

[0012] In some embodiments, the method for forming a 3D memory structure also includes forming a plurality of memory strings in the alternating dielectric stacks prior to forming the plurality of contact openings.

[0013] In some embodiments, the method for forming a 3D memory structure further includes forming a plurality of memory strings in the alternating dielectric stacks after forming the plurality of contact openings.

[0014] In some embodiments, forming the multiple memory strings includes forming a channel hole vertically through the alternating dielectric stack and disposing a memory film, a channel layer, and a core fill film on sidewalls of the channel hole.

[0015] In some embodiments, forming the contact structures includes forming a liner on sidewalls of the plurality of contact openings, forming a contact hole inside each of the plurality of contact openings to expose a conductive layer in a film stack of alternating conductive and dielectric layers, and disposing a conductive material inside the contact hole to form an electrical contact with the conductive layer. In some embodiments, forming the contact structures also includes forming a coplanar surface by chemical mechanical polishing.

[0016] A second aspect of the present disclosure provides a three-dimensional (3D) memory structure comprising a film stack disposed on a substrate, the film stack having conductive and dielectric layers alternately stacked on top of each other. The 3D memory structure also comprises a plurality of memory strings vertically penetrating the film stack, each memory string comprising a memory film, a channel layer, and a core fill film. The 3D memory structure also comprises a plurality of contact structures disposed inside the film stack, the plurality of contact structures vertically penetrating one or more conductive and dielectric layers such that each conductive layer of the film stack is electrically coupled to at least one of the plurality of contact structures. The plurality of contact structures are surrounded by the plurality of memory strings.

[0017] In some embodiments, each of the plurality of contact structures comprises a liner surrounding the conductive material, hi some embodiments, the liner comprises an insulator configured to electrically isolate the plurality of contact structures from one or more conductive layers of the film stack.

[0018] In some embodiments, the 3D memory structure of claim 13 also comprises a common source contact that extends vertically through the film stack and is electrically coupled to the substrate. In some embodiments, the common source contact comprises an isolation liner configured to electrically isolate the common source contact from the conductive layers of the film stack.

[0019] In some embodiments, the 3D memory structure further comprises a plurality of dummy memory strings extending vertically through the film stack adjacent to the plurality of contact structures, each dummy memory string comprising a core fill film.

[0020] In some embodiments, the contact structures are flush with the film stack.

[0021] In some embodiments, the multiple contact structures are randomly distributed in the memory array.

[0022] A third aspect of the present disclosure is a step of disposing an alternating dielectric stack on a substrate, the alternating dielectric stack comprising two n Another method for forming a three-dimensional (3D) memory structure is provided, the method including forming a plurality of contact openings using a repeated patterning process (n+1) times. The i-th patterning process is a repeat of the above two patterning processes. i The dielectric layer pairs are exposed inside the contact openings. (i-1) the first dielectric layer pairs, where i is an integer from 1 to n. The method of forming a 3D memory structure further includes replacing the second dielectric layer with a conductive layer to form a film stack of alternating conductive and dielectric layers, and forming a contact structure electrically coupled to the conductive layer in the film stack of alternating conductive and dielectric layers.

[0023] In some embodiments, the i-th patterning process further includes forming a mask to expose a subset of the plurality of contact openings prior to etching, (i-1) The dielectric layer pair is exposed inside a subset of the plurality of contact openings.

[0024] In some embodiments, the method for forming a 3D memory structure further includes, prior to forming the plurality of contact openings, disposing a hard mask on the alternating dielectric stack and forming a plurality of openings in the hard mask.

[0025] Other aspects of the present disclosure may be understood by those skilled in the art in view of the description, claims, and drawings of the present disclosure.

[0026] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the art to make and use the disclosure. [Brief description of the drawings]

[0027] [Figure 1] 1 is a schematic top-down view of an example three-dimensional (3D) memory die in accordance with some embodiments of the present disclosure. [Diagram 2] 2 is a schematic top-down view of a region of a 3D memory die in accordance with some embodiments of the present disclosure. [Diagram 3] 1 is a perspective view of a portion of an example 3D memory array structure according to some embodiments of the present disclosure. [Figure 4] 1 is a flow diagram of an example method for forming a 3D memory device according to some embodiments of the present disclosure. [Diagram 5] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 6] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 7] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 8] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 9] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 10] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 11] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 12]5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 13] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 14A] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 14B] 2A-2C illustrate the relationship between contact openings at various process steps according to some embodiments of the present disclosure. [Figure 15] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 16] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 17] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 18] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 19] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 20] 5A-5C are cross-sectional views of an exemplary 3D memory device at various process steps following the flow diagram of FIG. 4 according to some embodiments of the present disclosure. [Figure 21A] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 21B] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 21C] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 21D] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 21E] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 21F] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 21G] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Fig. 21H] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 21I] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 21J] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 21K] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 21L] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 21M] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 21N] 1A-1D are perspective views of an example 3D memory device at various process steps according to some embodiments of the present disclosure. [Figure 22]1 is a flow diagram of another example method for forming a 3D memory device according to some embodiments of the present disclosure. [Figure 23] 23A-23C are cross-sectional views of an example 3D memory device at various process steps following the flow diagram of FIG. 22 according to some embodiments of the present disclosure. [Figure 24] 23A-23C are cross-sectional views of an example 3D memory device at various process steps following the flow diagram of FIG. 22 according to some embodiments of the present disclosure. [Diagram 25] 23A-23C are cross-sectional views of an example 3D memory device at various process steps following the flow diagram of FIG. 22 according to some embodiments of the present disclosure. [Figure 26] 23A-23C are cross-sectional views of an example 3D memory device at various process steps following the flow diagram of FIG. 22 according to some embodiments of the present disclosure. [Figure 27] 23A-23C are cross-sectional views of an example 3D memory device at various process steps following the flow diagram of FIG. 22 according to some embodiments of the present disclosure. [Figure 28] 23A-23C are cross-sectional views of an example 3D memory device at various process steps following the flow diagram of FIG. 22 according to some embodiments of the present disclosure. [Figure 29] 23A-23C are cross-sectional views of an example 3D memory device at various process steps following the flow diagram of FIG. 22 according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The features and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like numerals identify corresponding elements throughout. In the drawings, like numerals generally indicate similar, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the left-most digit in the corresponding number.

[0029] Embodiments of the present disclosure will now be described with reference to the accompanying drawings.

[0030] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure can be employed in a variety of other applications.

[0031] It is noted that references herein to "one embodiment," "embodiment," "example embodiment," "some embodiments," and the like, mean that the described embodiment may include a particular feature, structure, or characteristic, but not necessarily all embodiments may include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in the context of an embodiment, it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in the context of other embodiments, whether or not expressly described.

[0032] Generally, terminology may be understood, at least in part, from use in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular sense, or may be used to describe a combination of features, structures, or characteristics in the plural sense, depending at least in part on the context. Similarly, terms such as "a" or "the" may be understood to convey singular use or to convey plural use, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive collection of factors, but may instead permit the presence of additional factors not necessarily explicitly recited, again depending at least in part on the context.

[0033] It should be readily understood that the meanings of "on", "above" and "across" in this disclosure should be interpreted in the broadest manner, such that "on" does not only mean "directly" something, but also includes the meaning of being "on" something with an intermediate feature or layer between them. Furthermore, "above" or "across" can also include the meaning of being "above" or "across" something (i.e., directly on something) without an intermediate feature or layer between them, rather than only meaning "above" or "across" something.

[0034] Additionally, spatially relative terms such as "below," "below," "lower," "above," "above" and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or to other orientations) and the spatially relative descriptions used herein may be similarly interpreted accordingly.

[0035] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. Substrates include an "upper" surface and a "lower" surface. The upper surface of a substrate is typically where semiconductor devices are formed, so that semiconductor devices are formed on the upper side of the substrate unless otherwise stated. The lower surface is the opposite of the upper surface, so that the lower side of the substrate is the opposite of the upper side of the substrate. The substrate itself may be patterned. Materials added onto the substrate may be patterned or left unpatterned. Additionally, substrates may include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, substrates may be formed from non-conductive materials, such as glass, plastic, or sapphire wafers.

[0036] As used herein, the term "layer" refers to a portion of material that includes a region of thickness. A layer has an upper side and a lower side, the lower side of the layer being relatively closer to the substrate and the upper side being relatively farther from the substrate. A layer can extend throughout an underlying or overlying structure, or can have an extent less than the extent of the underlying or overlying structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between the upper and lower surfaces of a continuous structure, or between any set of horizontal surfaces at the upper and lower surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers, and / or can have one or more layers on, above, and / or below. A layer may include multiple layers. For example, the interconnect layer may include one or more conductive layers and contact layers (in which the contacts, interconnect lines, and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0037] In this disclosure, for ease of description, a "level" is used to refer to elements of substantially the same height along a vertical direction. For example, a wordline and an underlying gate dielectric layer may be referred to as a "level," a wordline and an underlying insulating layer may both be referred to as a "level," wordlines of substantially the same height may be referred to as a "level of wordlines" or the like.

[0038] As used herein, "nominal" refers to a desired or target value of a characteristic or parameter for a component or process step that is set during the design phase or process of a product, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations or tolerances in the manufacturing process. As used herein, the term "about" refers to a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" can refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0039] In this disclosure, the term "horizontal / horizontally / lateral / laterally" means nominally parallel to a lateral surface of the substrate, and the term "vertical" or "vertically" means nominally perpendicular to a lateral surface of the substrate.

[0040] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device with vertically oriented strings of memory cell transistors (referred to herein as "memory strings", such as NAND strings) in a laterally oriented substrate such that the memory strings extend vertically relative to the substrate.

[0041] FIG. 1 is a top-down view of an exemplary three-dimensional (3D) memory device 100 according to some embodiments of the present disclosure. The 3D memory device 100 may be a memory chip (package), a memory die, or any portion of a memory die, and may include one or more memory planes 101, each of which may include multiple memory blocks 103. Identical or simultaneous operations may be performed on each memory plane 101. A memory block 103, which may be megabytes (MB) in size, is the minimum size for performing an erase operation. As shown in FIG. 1, the exemplary 3D memory device 100 includes four memory planes 101, each of which includes six memory blocks 103. Each memory block 103 may include multiple memory cells, and each memory cell may be addressed through interconnects such as bit lines and word lines. The bit lines and word lines may be arranged vertically (e.g., rows and columns, respectively) to form an array of metal lines. The bit line direction and word line direction are marked as "BL" and "WL" in FIG. 1. In this disclosure, memory block 103 is also referred to as a “memory array” or “array.” A memory array is the core area in a memory device that performs the storage function.

[0042] The 3D memory device 100 also includes a peripheral region 105, which is the area surrounding the memory plane 101. The peripheral region 105 includes many digital, analog, and / or mixed-signal circuits to support the functionality of the memory array, such as page buffers, row decoders, column decoders, and sense amplifiers. The peripheral circuits use active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0043] It is noted that the arrangement of memory planes 101 in the 3D memory device 100 and the arrangement of memory blocks 103 in each memory plane 101 shown in FIG. 1 are used only as examples without limiting the scope of the present disclosure.

[0044] Referring to FIG. 2, a close-up top-down view of the region 108 in FIG. 1 is shown according to some embodiments of the present disclosure. The region 108 of the 3D memory device 100 can include a staircase region 210 and a channel structure region 211. The channel structure region 211 can include an array of memory strings 212, each including a plurality of stacked memory cells. The staircase region 210 can include a staircase structure and an array of contact structures 214 formed in the staircase structure. In some embodiments, a plurality of slit structures 216 extending in a word line direction (WL) across the channel structure region 211 and the staircase region 210 can divide the memory block into a plurality of memory fingers 218, with the WL direction (i.e., WL direction) being similar to that shown in FIG. 1. At least some of the slit structures 216 can function as a common source contact for the array of memory strings 212 in the channel structure region 211. A top select gate disconnect 220 can be placed in the middle of each memory finger 218, for example, to split the top select gate (TSG) of the memory finger 218 into two parts, thereby dividing the memory finger into two memory slices 224, where memory cells in the memory slices 224 that share the same word line form a programmable (read / write) memory page. While the erase process of the 3D NAND memory can be performed at the level of memory blocks, read and write operations can be performed at the level of memory pages. The memory pages can be kilobytes (KB) in size. In some embodiments, the region 108 also includes dummy memory strings 222 for process variation control during fabrication and / or for additional mechanical support.

[0045] 3 illustrates a perspective view of a portion of an example three-dimensional (3D) memory array structure 300 according to some embodiments of the present disclosure. The memory array structure 300 comprises a substrate 330, an insulating film 331 over the substrate 330, a level of Lower Select Gates (LSG) 332 over the insulating film 331, and multiple levels of control gates 333, also referred to as "word lines (WL)", stacked on the LSG 332 to form a film stack 335 of alternating conductive and dielectric layers. Dielectric layers adjacent to the level of control gates are not shown in FIG. 3 for clarity.

[0046] The control gates of each level are separated by slit structures 216-1 and 216-2 through a film stack 335. The memory array structure 300 also includes a level of top select gates (TSGs) 334 over the stack of control gates 333. The stack of TSGs 334, control gates 333, and LSGs 332 is also referred to as a "gate electrode." The memory array structure 300 further includes memory strings 212 and doped source line regions 344 in the portion of the substrate 330 between adjacent LSGs 332. Each memory string 212 includes a channel hole 336 that extends through the insulating film 331 and the film stack 335 of alternating conductive and dielectric layers. The memory string 212 also includes a memory film 337 on the sidewalls of the channel hole 336, a channel layer 338 over the memory film 337, and a core fill film 339 surrounded by the channel layer 338. A memory cell 340 can be formed at the intersection of the control gate 333 and the memory string 212. The memory array structure 300 further comprises a number of bit lines (BL) 341 coupled to the memory strings 212 across the TSG 334. The memory array structure 300 also comprises a number of metal interconnect lines 343 coupled to the gate electrodes through a number of contact structures 214. The edges of the film stack 335 are configured in a stepped manner to allow electrical connection to each level of the gate electrodes.

[0047] In FIG. 3, for illustration purposes, three levels of control gates 333-1, 333-2, and 333-3 are shown along with one level of TSG 334 and one level of LSG 332. In this example, each memory string 212 may include three memory cells 340-1, 340-2, and 340-3 corresponding to control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells may be greater than three to increase storage capacity. The memory array structure 300 may include other structures, such as TSG disconnects, common source contacts, and dummy memory strings. These structures are not shown in FIG. 3 for simplicity.

[0048] In pursuit of larger storage capacity in 3D memory, the number of vertically stacked memory cells is greatly increased. As a result, the number of control gates or word lines 333 is greatly increased. To form electrical contacts (e.g., contact structures 214) for each word line 333, the staircase region 210 is extended laterally from both sides of the channel structure region 211. The increased dimensions of the staircase region 210 reduce the effective storage capacity per unit area, and thus increase the cost per bit of the 3D memory. Furthermore, the large staircase region 210 may cause mechanical stress on the channel structure region 211, which may cause reliability issues in the memory cells. Therefore, there is a demand to form a contact structure for 3D memory without relying on the staircase structure.

[0049] FIG. 4 illustrates an example fabrication process 400 for forming a 3D memory device according to some embodiments of the present disclosure. FIGS. 5-13, 14A-14B, and 15-20 illustrate cross-sectional views of a 3D memory device at various process steps according to the fabrication process 400. It should be understood that the process steps illustrated in the fabrication process 400 are not exhaustive and other process steps may be performed before, after, or between any of the illustrated process steps. In some embodiments, some process steps of the example fabrication process 400 may be omitted and other process steps may be included that are not described herein for brevity. In some embodiments, the process steps of the fabrication process 400 may be performed in a different order and / or may be altered.

[0050] 4, the fabrication process 400 begins in process step S410, where an alternating dielectric stack may be disposed on a substrate. An example of a 3D memory device in process step S410 is shown in FIG. 5 as 3D memory structure 500.

[0051] In some embodiments, the substrate of the 3D memory structure 500 may be similar to the substrate 330 in FIG. 3. The substrate 330 may provide a platform for forming subsequent structures. In some embodiments, the substrate 330 may be any suitable semiconductor substrate having any suitable semiconductor material, such as monocrystalline, polycrystalline, or single crystal semiconductors. For example, the substrate 330 may include silicon, silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some embodiments, the substrate 330 may include a layer of semiconductor material formed on a handle wafer, such as a glass, plastic, or other semiconductor substrate.

[0052] The front surface 330f of the substrate 330 is also referred to herein as the "main surface" or "top surface" of the substrate. A layer of material may be disposed on the front surface 330f of the substrate 330. The "top" or "upper" layer is the layer furthest or further away from the front surface 330f of the substrate. The "bottom" or "lower" layer is the layer closest or closer to the front surface 330f of the substrate.

[0053] In some embodiments, the alternating dielectric stack 554 comprises a plurality of dielectric layer pairs 556 alternately stacked on top of one another, with each dielectric layer pair 556 comprising a first dielectric layer 558 and a second dielectric layer 560 (also referred to as a “sacrificial layer”) that is different from the first dielectric layer 558. The alternating dielectric stack 554 extends in a lateral direction that is parallel to the front surface 330f of the substrate 330.

[0054] In the alternating dielectric stack 554, the first dielectric layers 558 and the second dielectric layers 560 alternate in a vertical direction perpendicular to the substrate 330. Stated differently, each second dielectric layer 560 is sandwiched between two first dielectric layers 558, and each first dielectric layer 558 can be sandwiched between two second dielectric layers 560 (except for the bottom and top layers).

[0055] Forming the alternating dielectric stack 554 may include disposing the first dielectric layers 558 to each have the same thickness or to each have different thicknesses. Exemplary thicknesses of the first dielectric layers 558 may range from 10 nm to 500 nm, and preferably about 25 nm. Similarly, the second dielectric layers 560 may each have the same thickness or each have different thicknesses. Exemplary thicknesses of the second dielectric layers 560 may range from 10 nm to 500 nm, and preferably about 35 nm. It should be understood that the number of dielectric layer pairs 556 in FIG. 5 is for illustrative purposes only, and that any suitable number of layers may be included in the alternating dielectric stack 554.

[0056] In some embodiments, the first dielectric layer 558 comprises any suitable insulating material, such as, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide with F-, C-, N-, and / or H- incorporation. The first dielectric layer 558 may also comprise a high-k dielectric material, such as, for example, a hafnium oxide film, a zirconium oxide film, an aluminum oxide film, a tantalum oxide film, or a lanthanum oxide film. In some embodiments, the first dielectric layer 558 may be any combination of the above materials.

[0057] Formation of the first dielectric layer 558 on the substrate 330 may include any suitable deposition method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), rapid thermal chemical vapor deposition (RTCVD), low pressure chemical vapor deposition (LPCVD), sputtering, metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high density plasma CVD (HDP-CVD), thermal oxidation, nitridation, any other suitable deposition method, and / or combinations thereof.

[0058] In some embodiments, the second dielectric layer 560 comprises any suitable material different from the first dielectric layer 558 and can be selectively removed relative to the first dielectric layer 558. For example, the second dielectric layer 560 can comprise silicon oxide, silicon oxynitride, silicon nitride, TEOS, polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, and any combination thereof. In some embodiments, the second dielectric layer 560 also comprises an amorphous semiconductor material, such as amorphous silicon or amorphous germanium. The second dielectric layer 560 can be disposed using a technique similar to the first dielectric layer 558, such as CVD, PVD, ALD, thermal oxidation, thermal nitridation, or any combination thereof.

[0059] In some embodiments, the first dielectric layer 558 can be silicon oxide and the second dielectric layer 560 can be silicon nitride.

[0060] In some embodiments, the alternating dielectric stack 554 can include layers in addition to the first dielectric layer 558 and the second dielectric layer 560 and can be made from different materials and / or with different thicknesses.

[0061] In addition to the alternating dielectric stacks 554, in some embodiments, peripheral devices (not shown) may be formed on the front surface 330f of the substrate 330 in the peripheral region 105 (see FIG. 1). In some embodiments, active device regions (not shown) may also be formed on the front surface 330f of the substrate 330 in the memory blocks 103 (see FIG. 1). In some embodiments, the substrate 330 may further include an insulating film 331 on the front surface 330f (not shown in FIG. 5). The insulating film 331 may be made of the same or different material as the alternating dielectric stacks 554.

[0062] The peripherals may include any suitable semiconductor devices, such as, for example, metal oxide semiconductor field effect transistors (MOSFETs), diodes, resistors, capacitors, etc. The peripherals may be used in the design of digital, analog, and / or mixed-signal circuits that support the storage functions of the memory core, such as, for example, row decoders, column decoders, drivers, page buffers, sense amplifiers, timing, and control.

[0063] The active device regions in the memory blocks are surrounded by isolation structures, such as shallow trench isolation. Doped regions, such as p-type and / or n-type doped wells, may be formed in the active device regions depending on the functionality of the array devices in the memory blocks.

[0064] Referring to FIG. 4, according to some embodiments of the present disclosure, in process step S415, a hard mask may be disposed on the alternating dielectric stack. An example of a 3D memory device in process step S415 is shown as 3D memory structure 600 in FIG. 6. The 3D memory structure 600 includes a hard mask 662 disposed on the alternating dielectric stack 554. The hard mask 662 is used to provide protection to the underlying structures and materials during the subsequent etching process. In some embodiments, the hard mask 662 includes any suitable material that can withstand the etching process, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, amorphous silicon, polycrystalline silicon, high-k dielectric materials, or any combination thereof. In some embodiments, the hard mask 662 may include amorphous carbon. In some embodiments, the amorphous carbon may be doped with other etch-resistant elements, such as boron, to improve the etch resistance of the amorphous carbon. In some embodiments, a thin metal or metal oxide layer, such as zirconium oxide (ZrO2), yttrium oxide (Y2O3), and aluminum oxide (Al2O3), may be disposed over the amorphous carbon layer. The hard mask 662 may be disposed by LPCVD, RTCVD, PECVD, ALD, PVD, evaporation, sputtering, or any combination thereof.

[0065] FIG. 7 illustrates a 3D memory structure 700 according to some embodiments of the present disclosure. The 3D memory structure 700 includes a contact definition mask 764 disposed on the hard mask 662 over the alternating dielectric stacks 554. In some embodiments, the contact definition mask 764 may include a photoresist material or a carbon-based polymer material and may be formed using a patterning process such as lithography. The contact definition mask 764 defines the location of contact structures for the control gate and the select gate of the 3D memory device formed in the subsequent process. In some embodiments, the contact structures may be similar to the contact structures 214 for the control gate 333, the top select gate (TSG) 334, and the lower select gate (LSG) 332 shown in FIG. 3. The contact structures 214 may be disposed in a region adjacent to the channel structure region 211 in FIG. 3 (e.g., the staircase region 210). In some embodiments, the contact structures 214 may be disposed inside the channel structure region 211, which will be discussed in more detail later.

[0066] 4, according to some embodiments of the present disclosure, in process step S420, a plurality of hard mask openings can be formed by patterning a hard mask. An example 3D memory device in process step S420 is shown as 3D memory structure 800 in FIG. 8. The 3D memory structure 800 includes a plurality of hard mask openings 866 formed by patterning the hard mask 662 with the contact definition mask 764 in FIG. 7. The hard mask openings expose a top surface 866-t of the first dielectric layer pair (i.e., the topmost dielectric layer pair in the alternating dielectric stack 554).

[0067] In some embodiments, the hard mask openings 866 may be patterned using a suitable etching process, such as a wet etch, a dry etch, and / or a combination thereof. In some embodiments, the hard mask 662 may be etched using an anisotropic etch, such as a reactive ion etch (RIE) or other dry etch process. In some embodiments, the hard mask 662 is silicon oxide. In this example, the silicon oxide etch may include RIE using a fluorine-based gas, such as fluorocarbon (CF4), hexafluoroethane (C2F6), CHF3, C3F6, and / or any other suitable gas. In some embodiments, the silicon oxide layer may be etched by a wet chemistry, such as hydrofluoric acid, or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etch approach may be used. In some embodiments, the hard mask 662 is silicon nitride. In this example, the silicon nitride etch may include RIE using O2, N2, CF4, NF3, Cl2, HBr, BCl3, and / or a combination thereof. The method and etchant for patterning the hard mask 662 should not be limited by the embodiments of the present disclosure.

[0068] In some embodiments, after forming the hard mask openings 866, the contact definition mask 764 in FIG. 7 can be removed using techniques such as dry etching with an O2 or CF4 plasma or wet etching with a resist / polymer stripper, e.g., a solvent-based chemistry.

[0069] 4, according to some embodiments of the present disclosure, in process step S425, a first contact mask may be formed over the alternating dielectric stacks. An example 3D memory device in process step S425 is shown as 3D memory structure 900 in FIG.

[0070] In some embodiments, the 3D memory structure 900 comprises a first contact mask 968 disposed in the 3D memory structure 800 over at least a portion of the alternating dielectric stacks. In some embodiments, the first contact mask 968 covers half of the hard mask opening 866 and exposes the other half of the hard mask opening 866. In some embodiments, the first contact mask 968 may include a photoresist material or a carbon-based polymer material and may be formed using a patterning process such as lithography.

[0071] 4, according to some embodiments of the present disclosure, in process step S430, a first subset of contact openings may be formed in the alternating dielectric stack. An example 3D memory device in process step S430 is shown in FIG. 10 as 3D memory structure 1000. 3D memory structure 1000 comprises a first subset of contact openings 1070.

[0072] In some embodiments, the first subset of contact openings 1070 can be formed by etching one dielectric layer pair 556 using the first contact mask 968 shown in FIG. 9. The first subset of contact openings 1070 exposes a top surface 1070-t of a second dielectric layer pair, which is located below a first or top dielectric layer pair in the alternating dielectric stack 554. In this disclosure, the dielectric layer pairs are numbered sequentially from top to bottom in the alternating dielectric stack 554. In some embodiments, one or more dielectric layer pairs 556 can be etched with the first contact mask 968. The etching process for the first dielectric layer 558 can have a high selectivity to the second dielectric layer 560 and / or the etching process for the second dielectric layer 560 can have a high selectivity to the first dielectric layer 558. Thus, the underlying dielectric layer pair 556 can function as an etch stop layer. As a result, multiple dielectric layer pairs 556 can be controllably etched.

[0073] In some embodiments, the dielectric layer pair 556 may be etched using an anisotropic etch such as reactive ion etching (RIE) or other dry etching process. In some embodiments, the first dielectric layer 558 is silicon oxide. In this example, the silicon oxide etch may include RIE using a fluorine-based gas such as fluorocarbon (CF4), hexafluoroethane (C2F6), CHF3, C3F6, and / or any other suitable gas. In some embodiments, the silicon oxide layer may be etched by wet chemistry such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etch approach may be used. In some embodiments, the second dielectric layer 560 is silicon nitride. In this example, the silicon nitride etch may include RIE using O2, N2, CF4, NF3, Cl2, HBr, BCl3, and / or combinations thereof. The method and etchant used to etch the dielectric layer pair 556 should not be limited by the embodiments of the present disclosure.

[0074] In some embodiments, after forming the first subset of contact openings 1070, the first contact mask 968 can be removed using techniques such as dry etching with an O2 or CF4 plasma or wet etching with a resist / polymer stripper, e.g., a solvent-based chemistry.

[0075] In some embodiments, after process step S430, half of the hard mask openings 866 can be converted into the first subset of contact openings 1070, and the other half remains as the hard mask openings 866. Thus, a top surface 866-t of the first dielectric layer pair and a top surface 1070-t of the second dielectric layer pair can be exposed inside the hard mask openings 866 and the first subset of contact openings 1070, respectively.

[0076] In some embodiments, the alternating dielectric stack 554 comprises L dielectric layer pairs 556. In some embodiments, the 3D memory structure 800 ( FIG. 8 ) comprises N hard mask openings 866, where the number N is equal to or greater than the number L, i.e., N≧L. In this example, half of the hard mask openings 866 may be converted into the first subset of contact openings 1070. In other words, after process step S430, the number of the first subset of contact openings 1070 may be N / 2, and the number of the remaining hard mask openings 866 may also be N / 2. However, the first subset of contact openings 1070 is not limited to as previously described and may include any suitable number of hard mask openings 866.

[0077] 4, according to some embodiments of the present disclosure, in process step S435, a second contact mask may be formed over the alternating dielectric stacks. An example 3D memory device in process step S435 is shown in FIG. 11 as 3D memory structure 1100.

[0078] In some embodiments, the 3D memory structure 1100 comprises a second contact mask 1172 disposed in the 3D memory structure 1000 over at least a portion of the alternating dielectric stacks 554. In some embodiments, the second contact mask 1172 covers half of the remaining hard mask openings 866 and exposes the other half of the remaining hard mask openings 866. In some embodiments, the second contact mask 1172 also covers half of the first subset of contact openings 1070 and exposes the other half of the first subset of contact openings 1070. In some embodiments, the second contact mask 1172 may include a photoresist material or a carbon-based polymer material and may be formed using a patterning process, such as lithography.

[0079] 4, according to some embodiments of the present disclosure, in process step S440, a second subset of contact openings and a third subset of contact openings may be formed in the alternating dielectric stack. An example 3D memory device in process step S440 is shown in FIG. 12 as 3D memory structure 1200. 3D memory structure 1200 comprises second subset of contact openings 1274 and third subset of contact openings 1275.

[0080] In some embodiments, the second subset of contact openings 1274 and the third subset of contact openings 1275 can be formed by etching two dielectric layer pairs 556 using the second contact mask 1172 shown in Figure 11. In some embodiments, one or more of the dielectric layer pairs 556 can be etched with the second contact mask 1172. The etch process for the first dielectric layer 558 and the second dielectric layer 560 can be similar to the etch process used for the first subset of contact openings 1070, and each dielectric layer pair 556 can be controllably etched with an etch stop at the underlying dielectric layer pair 556.

[0081] In some embodiments, the first contact mask 968 and the second contact mask 1172 can be designed such that the second subset of contact openings 1274 includes half of the first subset of contact openings 1070, and the third subset of contact openings 1275 includes half of the remaining hard mask openings 866 that were not converted to the first subset of contact openings 1070 in process step S430. In an example where the hard mask openings 866 are formed by etching through the hard mask 662 and the first subset of contact openings 1070 are formed by etching one dielectric layer pair 556, the second subset of contact openings 1274 can extend through three dielectric layer pairs and expose a top surface 1274-t of a fourth dielectric layer pair by etching two dielectric layer pairs 556 in process step S440. Meanwhile, the third subset of contact openings 1275 can extend through two dielectric layer pairs and expose a top surface 1275-t of a third dielectric layer pair. Thus, after process step S440, half of the first subset of contact openings 1070 are converted into a second subset of contact openings 1274, and half of the remaining hard mask openings 866 are converted into a third subset of contact openings 1275.

[0082] As shown in FIG. 12, the 3D memory structure 1200 may also include a portion of the first subset of contact openings 1070 that extend through one dielectric layer pair 556 and expose a top surface 1070-t of a second dielectric layer pair. The 3D memory structure 1200 may also include a portion of the hard mask openings 866 that extend through the hard mask 662 and expose a top surface 866-t of the first dielectric layer pair. As shown in FIG. 11, these openings are covered by the second contact mask 1172 in process step S435 and are protected during the etching process of the dielectric layer pair 556 in process step S440. Therefore, the depth of the aforementioned openings is not changed in process step S440.

[0083] After process step S440, the top surfaces of the first, second, third, and fourth dielectric layer pairs may be exposed inside the hard mask opening 866, the first subset of contact openings 1070, the third subset of contact openings 1275, and the second subset of contact openings 1274, respectively.

[0084] In an example where the 3D memory structure 1000 comprises the first subset of N / 2 contact openings 1070 and N / 2 hard mask openings 866, after process step S430, the 3D memory structure 1200 may comprise the second subset of N / 4 contact openings 1274 and the third subset of N / 4 contact openings 1275. Meanwhile, there may be the first subset of N / 4 contact openings 1070 and N / 4 hard mask openings 866 remaining in the 3D memory structure 1200.

[0085] It is noted that the first subset of contact openings 1070, the second subset of contact openings 1274, the third subset of contact openings 1275, and the hard mask openings 866 in Figure 12 are for illustration purposes only. The 3D memory structure 1200 may comprise different arrangements and depths in the first subset of contact openings 1070, the second subset of contact openings 1274, the third subset of contact openings 1275, and the hard mask openings 866.

[0086] 4, in accordance with some embodiments of the present disclosure, in process step S445, a third contact mask is formed over the alternating dielectric stacks. An example 3D memory device in process step S445 is shown in FIG. 13 as 3D memory structure 1300.

[0087] The 3D memory structure 1300 comprises a third contact mask 1376 disposed in the 3D memory structure 1200 over at least a portion of the alternating dielectric stacks 554. In some embodiments, the third contact mask 1376 covers half of the remaining hard mask openings 866 and exposes the other half of the remaining hard mask openings 866. In some embodiments, the third contact mask 1376 also covers half of the first subset of remaining contact openings 1070 and exposes the other half of the first subset of remaining contact openings 1070. In some embodiments, the third contact mask 1376 also covers half of the second subset of contact openings 1274 and exposes the other half of the second subset of contact openings 1274. In some embodiments, the third contact mask 1376 also covers half of the third subset of contact openings 1275 and exposes the other half of the third subset of contact openings 1275. In some embodiments, the third contact mask 1376 may include a photoresist material or a carbon-based polymer material and may be formed using a patterning process such as lithography.

[0088] 4, in process step S450, a fourth subset, a fifth subset, a sixth subset, and a seventh subset of contact openings are formed in the alternating dielectric stack, according to some embodiments of the present disclosure. An example 3D memory device in process step S450 is shown in FIG. 14A as 3D memory structure 1400. 3D memory structure 1400 includes a fourth subset of contact openings 1478, a fifth subset of contact openings 1479, a sixth subset of contact openings 1480, and a seventh subset of contact openings 1481 formed in the alternating dielectric stack 554, according to some embodiments of the present disclosure.

[0089] In some embodiments, the fourth, fifth, sixth, and seventh subsets of contact openings 1478-1481 can be formed by etching the four dielectric layer pairs 556 using the third contact mask 1376 shown in FIG. 13. In some embodiments, one or more of the dielectric layer pairs 556 can be etched using the third contact mask 1376. The etch process for the first dielectric layer 558 and the second dielectric layer 560 can be similar to the etch process used for the first subset of contact openings 1070, the second subset of contact openings 1274, and the third subset of contact openings 1275, and each dielectric layer pair 556 can be controllably etched with an etch stop at the underlying dielectric layer pair 556.

[0090] 14B illustrates the relationship between contact openings in various process steps according to some embodiments of the present disclosure. The dielectric layer pairs 556 (counted from top to bottom) to which each contact opening exposes are indicated in brackets. In some embodiments, the first contact mask 968, the second contact mask 1172, and the third contact mask 1376 may be designed such that a portion of the hard mask openings 866 may be converted into a first subset of contact openings 1070 in process step S430. A portion of the first subset of contact openings 1070 may be converted into a second subset of contact openings 1274 in process step S440, and then a portion of the second subset of contact openings 1274 may be converted into a fourth subset of contact openings 1478 in process step S450. Meanwhile, a portion of the remaining first subset of contact openings 1070 in process step S440 may be converted into a fifth subset of contact openings 1479 in process step S450. In this example, a portion of the remaining hard mask openings 866 in process step S430 may be converted to a third subset of contact openings 1275 in process step S440, while a portion of the third subset of contact openings 1275 may be converted to a seventh subset of contact openings 1481 in process step S450. A portion of the remaining hard mask openings 866 in process step S440 may be converted to a sixth subset of contact openings 1480 in process step S450. It is noted that the portion of the contact openings that undergo etching of the dielectric layer pairs 556 in each process step can be any suitable number and is not limited to the half or 50% shown in FIGS. 9-13 and 14A.

[0091] As discussed above, in some embodiments, there are N hard mask openings 866 after process step S420, and the 3D memory structure 1000 may have a first subset of N / 2 contact openings 1070 and N / 2 hard mask openings 866 after process step S420. The 3D memory structure 1200 may have a first subset of N / 4 contact openings 1070, a second subset of N / 4 contact openings 1274, a third subset of N / 4 contact openings 1275, and N / 4 hard mask openings 866 after process step S440. In some embodiments, the 3D memory structure 1400 may have a first subset of N / 8 contact openings 1070, a second subset of N / 8 contact openings 1274, a third subset of N / 8 contact openings 1275, a fourth subset of N / 8 contact openings 1478, a fifth subset of N / 8 contact openings 1479, a sixth subset of N / 8 contact openings 1480, a seventh subset of N / 8 contact openings 1481, and N / 8 hard mask openings 866.

[0092] As discussed above, in some embodiments, the hard mask opening 866 may be formed by etching through the hard mask 662 in process step S420, and the first subset of contact openings 1070 may be formed by etching one dielectric layer pair 556 in process step S430. Then, in process step S440, the second subset of contact openings 1274 and the third subset of contact openings 1275 may be formed by etching two dielectric layer pairs 556. Thus, the hard mask opening 866 may expose the first dielectric layer pair, i.e., the top dielectric layer pair. The first subset of contact openings 1070 converted from the hard mask opening 866 may extend through one dielectric layer pair 556 and may expose the second dielectric layer pair below the first dielectric layer pair. The second subset of contact openings 1274 and the third subset of contact openings 1275 converted from the first subset of contact openings 1070 and the hard mask openings 866, respectively, may extend through three and two dielectric layer pairs 556, respectively. Stated another way, the second subset of contact openings 1274 and the third subset of contact openings 1275 may expose the fourth and third dielectric layer pairs, respectively. With reference to FIGS. 14A and 14B, in some embodiments, the fourth through seventh subsets of contact openings 1478-1481 may be formed by etching through four dielectric layer pairs 556. As a result, after process step S450, the fourth subset of contact openings 1478 converted from the second subset of contact openings 1274 may extend through seven dielectric layer pairs 556 and may expose the top surface 1478-t of the eighth dielectric layer pair. A fifth subset of contact openings 1479 converted from the first subset of contact openings 1070 may extend through five dielectric layer pairs 556 and may expose a top surface 1479-t of a sixth dielectric layer pair.A sixth subset 1480 of contact openings converted from the hard mask openings 866 can extend through four dielectric layer pairs 556 and can expose a top surface 1480-t of the fifth dielectric layer pair. Similarly, a seventh subset 1481 of contact openings converted from the third subset 1070 of contact openings can extend through six dielectric layer pairs 556 and can expose a top surface 1481-t of the seventh dielectric layer pair.

[0093] It is noted that the arrangement of the first through seventh subsets of contact openings 1070, 1274-1275, 1478-1481, and hard mask openings 866 in Figures 14A and 14B is for illustration purposes only. The 3D memory structure 1400 may have different arrangements and different depths (i.e., etched dielectric layer pairs) in the first through seventh subsets of contact openings 1070, 1274-1275, 1478-1481, and hard mask openings 866. In other words, the aforementioned contact openings may be randomly distributed in the alternating dielectric stacks 554.

[0094] The fabrication process may continue by forming another contact mask in the 3D memory structure 1400 covering at least a portion of the contact holes, and then etching one or more of the dielectric layer pairs 556. These process steps may be repeated until a top surface of each of the dielectric layer pairs 556 is exposed inside at least one of the contact openings. In some embodiments, in the ith process step for forming one or more subsets of contact openings, where i=1, 2, 3, ..., each of the current subsets of contact openings may be divided into two groups, one group having a first contact hole and a second contact hole. (i-1) The i-th process step may then be followed by an etching process of the dielectric layer pairs to form a new subset of contact openings. The other groups in each of the current subsets of contact openings may be protected by a mask and exposed to the etching process. After the i-th process step, the first, second, ..., second iA top surface of the dielectric layer pair may be exposed inside at least one of the contact openings.

[0095] In some embodiments, each of the current subsets of contact openings can be split into two groups with an equal number of contact openings, with one group remaining the same as the current subset of contact openings and the other group forming a new subset of contact openings. For example, N hard mask openings can be split into N / 2 hard mask openings and a first subset of N / 2 contact openings. The first subset of contact openings can then be split into a second subset of N / 4 contact openings and the first subset of N / 4 contact openings, and so on. In this example, at least one contact opening can be expanded by a total of 20% using only n mask and etch steps. (n-1) An alternating dielectric stack with individual dielectric layer pairs can be formed for each dielectric layer pair.

[0096] After forming contact openings in the alternating dielectric stack 554, the hard mask 662 may be removed.

[0097] 4, according to some embodiments of the present disclosure, in process step S455, a fill material may be disposed inside the contact openings. An example 3D memory device in process step S455 is shown in FIG. 15 as 3D memory structure 1500. 3D memory structure 1500 includes contact fill 1584 formed by disposing fill material 1586 inside contact openings (labeled 1070, 1274-1275, 1478-1481) and hard mask openings 866 in 3D memory structure 1400 (shown in FIG. 14A). In some embodiments, contact fill 1584 also includes a liner 1587 disposed prior to deposition of fill material 1586.

[0098] The fill material 1586 and the liner 1587 may be any suitable material that may be selectively removed over the first dielectric layer 558 and / or the second dielectric layer 560 in subsequent processes. In some embodiments, the fill material 1586 and the liner 1587 may be an insulator, such as, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS, amorphous carbon, and / or combinations thereof. In some embodiments, the fill material 1586 may be silicon nitride and the liner 1587 may be silicon oxide. The fill material 1586 and the liner 1587 may be formed by CVD, PVD, sputtering, evaporation, and / or any combination thereof.

[0099] In some embodiments, the 3D memory structure 1500 can be planarized after depositing the fill material 1586 and the liner 1587 to form a coplanar upper surface.

[0100] 4, according to some embodiments of the present disclosure, in process step S460, multiple memory strings can be formed in alternating dielectric stacks. An example 3D memory device in process step S460 is shown as 3D memory structure 1600 in FIG. 16. 3D memory structure 1600 includes multiple memory strings (e.g., memory strings 212 in FIG. 2 and FIG. 3).

[0101] To form the memory strings 212, a plurality of channel holes (e.g., channel holes 336) may first be formed in the alternating dielectric stacks 554 and extend through the entire alternating dielectric stacks 554 to the substrate 330. In some embodiments, the formation of the channel holes 336 includes processes such as photolithography and etching. In some embodiments, a capping layer 1688 formed by a carbon-based polymer material, or a hard mask, may be used in addition to the photoresist for the etching process. The capping layer 1688 may include silicon oxide, silicon nitride, TEOS, silicon-containing anti-reflective coating (SiARC), amorphous silicon, polycrystalline silicon, or any combination thereof. The etching process for forming the channel holes 336 may include dry etching, wet etching, or a combination thereof. In some embodiments, the alternating dielectric stacks 554 may be etched using an anisotropic etch, such as reactive ion etching (RIE). In some embodiments, fluorine or chlorine based gases can be used, such as fluorocarbon (CF4), hexafluoroethane (C2F6), CHF3, C3F6, Cl2, BCl3, etc., or any combination thereof. The method and etchant for etching the first and second dielectric layers 558 / 560 should not be limited by the embodiments of the present disclosure.

[0102] In some embodiments, the 3D memory structure 1600 further comprises an epitaxial layer 1690 inside the channel hole 336. The epitaxial layer 1690 may include any suitable semiconductor material, such as silicon, silicon germanium, germanium, gallium arsenide, gallium nitride, III-V compounds, or any combination thereof. The epitaxial layer 1690 may be epitaxially grown from the substrate 330. In some embodiments, the epitaxial layer 1690 may be selectively grown from an exposed surface of the substrate 330 inside the channel hole 336. In some embodiments, the epitaxial layer 1690 may be a polycrystalline semiconductor material, such as polycrystalline silicon.

[0103] In some embodiments, the epitaxial layer 1690 may be epitaxially grown from doped regions (not shown in FIG. 16) in the substrate 330. The doped regions may be formed by ion implantation using p-type or n-type dopants, such as boron, phosphorous, arsenic, or any combination thereof. The ion implantation may be performed before deposition of the alternating dielectric stack 554. In some embodiments, the ion implantation may be performed after the channel hole etch.

[0104] After forming the channel holes 336 and the epitaxial layer 1690, a memory film (e.g., memory film 337 in FIG. 3) may be disposed on the sidewalls of each channel hole 336 and on the top surface of the epitaxial layer 1690. In some embodiments, the memory film 337 may be a composite layer including a tunnel layer, a storage layer (also known as a "charge trapping / storage layer"), and a block layer. Each channel hole 336 may have a cylindrical shape. The tunnel layer, storage layer, and block layer are disposed in the above order along a direction from the center of the channel hole toward the outside, according to some embodiments. The tunnel layer may include silicon oxide, silicon nitride, or any combination thereof. The block layer may include silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the memory film 337 comprises an ONO dielectric (e.g., a tunnel layer including silicon oxide, a storage layer including silicon nitride, and a block layer including silicon oxide).

[0105] Next, a channel layer 338 and a core fill film 339 may be disposed inside the channel holes 336. The channel layer 338 covers the sidewalls of the memory film 337 inside the channel holes 336 and is coupled with the epitaxial layer 1690. The channel layer 338 may be any suitable semiconductor material, such as silicon. In some embodiments, the channel layer 338 may be amorphous, polysilicon, or single crystal silicon. The channel layer 338 may be formed by any suitable thin film deposition process, including, but not limited to, CVD, PVD, ALD, or a combination thereof. In some embodiments, the thickness of the channel layer 338 may range from about 10 nm to about 30 nm. In some embodiments, the core fill film 339 may be disposed to fill each of the channel holes 336. In some embodiments, the middle of the core fill film 339 may include one or more voids. The core fill film 339 may be any suitable insulator, such as, for example, silicon oxide, silicon nitride, silicon oxynitride, spin-on glass, silicon oxide doped with boron or phosphorus, carbon doped oxide (CDO, SiOC, or SiOC:H), fluorine doped oxide (SiOF), or any combination thereof. The core fill film 339 may be deposited using, for example, ALD, PVD, CVD, spin coating, sputtering, or any other suitable film deposition technique. The core fill film 339 may be formed using a repeated deposition and etch-back process. The etch-back process may include, but is not limited to, wet etching, dry etching, or a combination thereof.

[0106] In some embodiments, the core fill film 339, the channel layer 338, and the capping layer 1688 may be coplanar in the 3D memory structure 1600. The planarization process includes chemical mechanical polishing, RIE, wet etching, or a combination thereof. The planarization process removes excess core fill film 339, the channel layer 338, and the memory film 337 outside the channel holes 336. Thus, the channel layer 338 and the memory film 337 may be decoupled between adjacent channel holes 336.

[0107] In some embodiments, multiple dummy memory strings (e.g., dummy memory string 222 in FIG. 2) may be formed in alternating dielectric stack 554 adjacent memory string 212 and / or contact openings 1070, 1274-1275, and 1478-1481. While memory string 212 may be used for memory storage, dummy memory string 222 may be used to provide structural support and improve process uniformity during fabrication. In some embodiments, dummy memory string 222 may also include core fill film 339 and may be formed using similar techniques as memory string 212.

[0108] FIG. 17 illustrates a 3D memory structure 1700 according to some embodiments of the present disclosure. The 3D memory structure 1700 includes a plurality of slit openings 1792 penetrating throughout the alternating dielectric stacks 554. In some embodiments, the slit openings 1792 may extend laterally along the WL direction in the xy plane parallel to the top surface 330f. The slit openings 1792 may form the slit structure 216 (FIGS. 2 and 3) in a subsequent fabrication process. The arrangement of the slit openings 1792 in FIG. 17 is for illustrative purposes only and is not so limited.

[0109] 4, according to some embodiments of the present disclosure, a film stack of alternating conductive and dielectric layers may be formed in process step S465. An example 3D memory device in process step S465 is shown in FIG. 18 as 3D memory structure 1800. 3D memory structure 1800 comprises a film stack of alternating conductive and dielectric layers, similar to film stack 335 in FIG.

[0110] After forming the slit openings 1792, the second dielectric layer 560 in the alternating dielectric stack 554 (FIG. 17) may be removed laterally from the slit openings 1792 to form lateral tunnels (not shown in FIG. 18). A conductive layer 1894 may then be disposed inside these lateral tunnels to form the membrane stack 335.

[0111] The second dielectric layer 560 (FIG. 17) may be removed by any suitable etching process, such as an isotropic dry etch or wet etch, that is selective across the alternating dielectric stack 554 such that the etch process has minimal impact on the first dielectric layer 558. In some embodiments, the second dielectric layer 560 may be silicon nitride. In this example, the second dielectric layer 560 may be removed by RIE using one or more of the following etchants: CF4, CHF3, C4F8, C4F6, and CH2F2. In some embodiments, the second dielectric layer 560 may be removed using a wet etch, such as phosphoric acid. After removing the second dielectric layer 560, the sidewalls of the memory film 337 may be exposed in the lateral tunnel.

[0112] In some embodiments, the conductive layer 1894 may include any suitable conductive material suitable for a gate electrode, such as, for example, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and / or any combination thereof. The conductive material may fill the lateral tunnel using a suitable deposition method, such as CVD, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, thermal evaporation, electron beam evaporation, metal organic chemical vapor deposition (MOCVD), and / or ALD. In some embodiments, the conductive layer 1894 includes tungsten (W) deposited by CVD.

[0113] In some embodiments, the conductive layer 1894 may be a polycrystalline semiconductor, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, any other suitable material, and / or combinations thereof. In some embodiments, the polycrystalline material may incorporate any suitable type of dopant, such as boron, phosphorous, or arsenic. In some embodiments, the conductive layer 1894 may be an amorphous semiconductor.

[0114] In some embodiments, the conductive layer 1894 is made of WSi x , CoSi x , NiSi x , or AlSi x and the like. Formation of the metal silicide material may include forming a metal layer and a polycrystalline semiconductor layer using similar techniques described above. Formation of the metal silicide may further include applying a thermal annealing process to the deposited metal layer and the polycrystalline semiconductor layer, followed by removal of unreacted metal.

[0115] In some embodiments, a gate dielectric layer may be disposed on the lateral tunnel prior to the formation of conductive layer 1894 (not shown in FIG. 18 ) to reduce leakage current between adjacent word lines (gate electrodes) and / or to reduce leakage current between the gate and the channel. The gate dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, and / or any suitable combination thereof. The gate dielectric layer may also include high-k dielectric materials such as hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The gate dielectric layer may be disposed by one or more suitable deposition processes such as CVD, PVD, and / or ALD.

[0116] The conductive layers 1894 can function as gate electrodes at their intersections with the memory strings 212. In Fig. 18, ten conductive layers 1894 can form ten gate electrodes for each memory string 212, such as TSG 334, LSG 332, and eight control gates 333. Corresponding to the eight control gates 333, each memory string 212 can have eight memory cells 340. It is noted that the number of memory strings and memory cells is shown in Fig. 18 for illustrative purposes and may be increased for larger storage capacity.

[0117] After forming the film stack 335 of alternating conductive and dielectric layers, the conductive material inside the slit openings 1792 during deposition may be removed. In some embodiments, an insulating material may be disposed inside some of the slit openings 1792 to form slit structures 216 that separate the memory blocks into a plurality of programmable and readable memory fingers (see FIGS. 2A-2B).

[0118] FIG. 19 illustrates a 3D memory structure 1900 according to some embodiments of the present disclosure. The 3D memory structure 1900 includes a plurality of contact holes 1996 formed by removing the fill material 1586 inside the contact fills 1584 in the 3D memory structure 1800 in FIG. 18. In some embodiments, the contact holes 1996 can be formed by lithography, wet chemical etching, dry etching, or a combination thereof. In some embodiments, the contact holes 1996 extend through the capping layer 1688 and one or more pairs of the conductive layer 1894 and the first dielectric layer 558. The contact holes 1996 can expose the conductive layer 1894 in the film stack 335. In some embodiments, the liner 1587 covers the sidewalls of each conductive layer 1894 inside each contact hole 1996 and exposes the top surface of the conductive layer 1894 at the bottom of each contact hole 1996.

[0119] In some embodiments, an isolation liner 1997 can be formed on the sidewalls of the slit opening 1792, with the isolation liner 1997 inside the slit opening 1792 covering the sidewalls of each conductive layer 1894 of the film stack 335. In some embodiments, the isolation liner 1997 can also be formed inside the contact hole 1996. The isolation liner 1997 can be any suitable insulator, such as, for example, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0120] Referring to FIG. 4, according to some embodiments of the present disclosure, in process step S470, contact structures may be formed to electrically couple with conductive layers in a film stack of alternating conductive and dielectric layers. An example 3D memory device in process step S470 is shown in FIG. 20 as 3D memory structure 2000. The 3D memory structure 2000 includes a plurality of contact structures similar to the contact structures 214 in FIG. 3, which provide electrical coupling with conductive layers 1894 in the film stack 335. In some embodiments, each contact structure 214 includes a liner surrounding the conductive material. In some embodiments, an isolation liner 1997 and / or liner 1587 covering the sidewalls of the contact structures 214 may electrically isolate the contact structures 214 from one or more conductive layers 1894 of the film stack 335. The 3D memory structure 2000 may also include a common source contact 2098 electrically coupled to the substrate 330. In some embodiments, an isolation liner 1997 can electrically isolate the common source contact 2098 from the conductive layer 1894 of the film stack 335 .

[0121] The contact structures 214 and the common source contact 2098 may be formed by disposing a conductive material inside the contact holes 1996 and the slit openings 1792. In some embodiments, the conductive material may include tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and / or any combination thereof. The conductive material may be disposed by CVD, PVD, PECVD, MOCVD, sputtering, thermal evaporation, e-beam evaporation, ALD, and / or combinations thereof. In some embodiments, the conductive material may be tungsten (W) deposited by CVD.

[0122] In some embodiments, the conductive material used for the contact structure 214 and the common source contact 2098 may be a polycrystalline semiconductor, such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium silicon, any other suitable material, and / or combinations thereof. In some embodiments, the polycrystalline material may incorporate any suitable type of dopant, such as boron, phosphorous, or arsenic. In some embodiments, the conductive material may be a non-crystalline semiconductor.

[0123] In some embodiments, the conductive material is WSi x , CoSi x , NiSi x , or AlSi x and the like. Formation of the metal silicide material may include forming a metal layer and a polycrystalline semiconductor layer using similar techniques described above. Formation of the metal silicide may further include applying a thermal annealing process to the deposited metal layer and the polycrystalline semiconductor layer, followed by removal of unreacted metal.

[0124] In some embodiments, excess conductive material outside the contact holes 1996 and slit openings 1792 may be removed after deposition by using an etching or planarization process. The etching process for removing excess conductive material may include wet chemical etching and / or dry etching (e.g., RIE). The planarization process may include chemical mechanical polishing (CMP).

[0125] Contact structure 214 in FIG. 20 and contact hole 1996 in FIG. 19 correspond to hard mask opening 866 and / or contact openings 1070, 1274-1275, 1478-1481 in FIG. 14A. As discussed above, in some embodiments, at least one contact opening is formed in a total of 200 Å using only n mask and etch steps. (n-1)3. The conductive layer 1894 of the film stack 335 may be formed for each dielectric layer pair in the alternating dielectric stack with the dielectric layer pairs. Also, according to the present disclosure, at least one contact structure 214 may be formed for each conductive layer 1894 in the film stack 335 without using a staircase structure. In this example, the contact structure 214 may be formed anywhere in the channel structure region 211 (shown in FIG. 2), i.e., inside the memory array, adjacent to the memory string 212, or surrounded by the memory string 212. In some embodiments, the contact structure 214 may be randomly distributed in the memory array adjacent to the memory string 212 and / or the dummy memory string 222. The conductive layer 1894 of the film stack 335 may function as a gate electrode, such as the control gate (word line) 333, the upper select gate 334, and the lower select gate 332 shown in FIG. 3. By moving the contact structure 214 closer to the memory string 212, the delay from the word line to the gate electrode of the memory cell 340 may be shortened accordingly. As a result, the performance of the 3D memory device may be improved. In some embodiments, the dummy memory strings 222 may be formed adjacent to the contact structures 214 and / or the memory strings 212 in the memory array.

[0126] In some embodiments, the contact mask used in the fabrication process 400 described in Figure 4 can have different designs and arrangements. Figures 21A-21N provide perspective views of the 3D memory structure at various process steps (e.g., process steps S410-S470) and show different methods for forming contact openings compared to the examples in Figures 5-13, 14A-14B, and 15-20. A detailed description of Figures 21A-21N is omitted herein because the methods shown are self-explanatory and can be understood by those skilled in the art from these figures.

[0127] FIG. 22 illustrates another exemplary fabrication process 2200 for forming a 3D memory device according to some embodiments of the present disclosure. FIGS. 23-29 illustrate cross-sectional views of a 3D memory device at various process steps according to the fabrication process 2200. It should be understood that the process steps illustrated in the fabrication process 2200 are not exhaustive and other process steps may be performed before, after, or between any of the illustrated process steps. In some embodiments, some process steps of the exemplary fabrication process 2200 may be omitted and other process steps may be included that are not described herein for brevity. In some embodiments, the process steps of the fabrication process 2200 may be performed in a different order and / or may be altered.

[0128] Only differences from Figures 4-13, 14A-14B, and 15-20 are shown in Figures 22-29. Similar process steps and structures can be referenced back to previous figures and corresponding descriptions.

[0129] 22, the fabrication process 2200 begins in process step S2210 where an alternating dielectric stack is disposed on a substrate. An example 3D memory structure 500 of a 3D memory device in process step S2210 is shown in FIG. The alternating dielectric stack 554 may comprise a first dielectric layer 558 and a second dielectric layer 560.

[0130] Referring to Figure 22, in process step S2220, channel holes and memory strings can be formed in the alternating dielectric stacks. An example 3D memory structure 2300 in process step S2220 is shown in Figure 23, where the channel holes 336 and memory strings 212 are similar to their counterparts in Figure 16 and can be formed using similar techniques. In process step S2220, dummy memory strings similar to the dummy memory strings 222 in Figure 16 can also be formed using similar techniques.

[0131] 22, in process step S2230, a plurality of contact openings can be formed in the alternating dielectric stack using a plurality of contact masks. An example 3D memory structure 2400 in process step S2230 is shown in FIG. 24, in which the hard mask opening 866, the first subset of contact openings 1070, the second and third subsets of contact openings 1274-1275, and the fourth through seventh subsets of contact openings 1478-1481 can be similar to their counterparts in FIG. 14A and can be formed using similar processes in process steps S415-S450 described in FIG. 4, FIG. 6-FIG. 13, and FIG. 14A-FIG. 14B.

[0132] Referring to Figure 22, in process step S2240, a liner is placed on the sidewall of each contact opening. An example 3D memory structure 2500 in process step S2240 is shown in Figure 25, where the liner 1587 is similar to that in Figure 15 and can be formed using similar techniques.

[0133] Referring to Figure 22, in process step S2250, slit openings can be formed in the alternating dielectric stacks. An example 3D memory structure 2600 in process step S2250 is shown in Figure 26, where the slit openings 1792 are similar to those in Figure 17 and can be formed using similar techniques.

[0134] 22, in process step S2260, a film stack of alternating conductive and dielectric layers may be formed. An example 3D memory structure 2700 in process step S2260 is shown in FIG 27, where the film stack 335 of alternating conductive and dielectric layers is similar to that in FIG 18 and may be formed using similar techniques.

[0135] FIG. 28 illustrates a 3D memory structure 2800 according to some embodiments of the present disclosure. The 3D memory structure 2800 includes an isolation liner 1997 formed on the sidewalls of the slit opening 1792. The isolation liner 1997 can be similar to that in FIG. 19 and can be formed using similar techniques. The 3D memory structure 2800 can also include a contact hole 1996 formed inside the contact openings (e.g., the hard mask opening 866, the first subset of contact openings 1070, the second and third subsets of contact openings 1274-1275, and the fourth through seventh subsets of contact openings 1478-1481) in FIG. 27. The contact hole 1996 exposes a top surface of the conductive layer 1894 and can be formed using similar techniques as shown in FIG.

[0136] 22, in process step S2270, contact structures may be formed to electrically couple with conductive layers in a film stack of alternating conductive and dielectric layers. An example 3D memory structure 2900 in process step S2270 is shown in FIG. 29, where the contact structures 214 are similar to those in FIG. 20 and may be formed using similar techniques. The 3D memory structure 2900 may also include a common source contact 2098, similar to that in FIG. 20.

[0137] Similar to fabrication process 400, fabrication process 2200 can also form at least one contact structure 214 for each conductive layer 1894 in the film stack 335 of alternating conductive and dielectric layers. These contact structures 214 can be formed inside the channel structure region 211 (FIGS. 2-3) and can be located adjacent to the memory strings 212.

[0138] In summary, this disclosure describes various embodiments of 3D memory devices and methods of making 3D memory devices.

[0139] A first aspect of the present disclosure provides a method for forming a three-dimensional (3D) memory device, comprising disposing an alternating dielectric stack on a substrate, the alternating dielectric stack comprising first and second dielectric layers alternately stacked on top of each other. The method also comprises forming a plurality of contact openings in the alternating dielectric stack such that the dielectric layer pair is exposed inside at least one of the plurality of contact openings, the dielectric layer pair comprising a pair of the first and second dielectric layers. The method further comprises replacing the second dielectric layer with a conductive layer to form a film stack of alternating conductive and dielectric layers, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

[0140] Forming the plurality of contact openings includes forming a plurality of openings in the alternating dielectric stack by etching N dielectric layer pairs, where N is an integer. A mask is then formed to protect a first group of the plurality of openings and expose a second group of the plurality of openings, where the first group of the plurality of openings is a first subset of openings that extends through the N dielectric layer pairs. Forming the plurality of contact openings further includes forming a second subset of openings in the second group of the plurality of openings by etching M dielectric layer pairs, where M is an integer. The second subset of openings extends through (N+M) dielectric layer pairs. By repeating the steps of forming the mask and etching for each of the subset of openings, a plurality of contact openings can be formed in the alternating dielectric stack.

[0141] A second aspect of the present disclosure provides a three-dimensional (3D) memory structure comprising a film stack disposed on a substrate, the film stack having conductive and dielectric layers alternately stacked on top of each other. The 3D memory structure also comprises a plurality of memory strings vertically penetrating the film stack, each memory string comprising a memory film, a channel layer, and a core fill film. The 3D memory structure also comprises a plurality of contact structures disposed inside the film stack, the plurality of contact structures vertically penetrating one or more conductive and dielectric layers such that each conductive layer of the film stack is electrically coupled to at least one of the plurality of contact structures. The plurality of contact structures are surrounded by the plurality of memory strings.

[0142] A third aspect of the present disclosure is a step of disposing an alternating dielectric stack on a substrate, the alternating dielectric stack comprising two n Another method for forming a three-dimensional (3D) memory structure is provided, the method including forming a plurality of contact openings using a repeated patterning process (n+1) times. The i-th patterning process is a repeat of the above two patterning processes. i The dielectric layer pairs are exposed inside the contact openings. (i-1) the first dielectric layer pairs, where i is an integer from 1 to n. The method of forming a 3D memory structure further includes replacing the second dielectric layer with a conductive layer to form a film stack of alternating conductive and dielectric layers, and forming a contact structure electrically coupled to the conductive layer in the film stack of alternating conductive and dielectric layers.

[0143] The above description of specific embodiments sufficiently reveals the general nature of the present disclosure so that others can easily modify and / or adapt such embodiments for various applications by applying the knowledge of those skilled in the art without undue experimentation and without departing from the broad concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments based on the present disclosure and guidance provided herein. It is understood that the expressions and terms in the present specification are for the purpose of description and not of limitation, as the terms and expressions in the present specification are interpreted by those skilled in the art in light of the present disclosure and guidance.

[0144] The embodiments of the present disclosure have been described above with the aid of functional components illustrating the performance of specified functions and their relationships. The boundaries of these functional components have been arbitrarily defined herein for convenience of description. Alternative boundaries may be defined so long as the specified functions and their relationships are appropriately performed.

[0145] The Summary and Abstract may describe one or more exemplary embodiments of the disclosure, but may not describe every exemplary embodiment of the disclosure as contemplated by the inventors, and thus are not intended to be in any way limiting of the disclosure and appended claims.

[0146] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. [Explanation of symbols]

[0147] 100 Three-dimensional (3D) memory devices 101 Memory Plane 103 Memory Blocks 105 Surrounding Areas 108 areas 210 Stairs area 211 Channel structure region 212 Memory String 214 Contact structure 216, 216-1, 216-2 Slit structure 218 Memory Finger 220 Upper selection gate cut section 222 Dummy memory string 224 Memory Slices 300 Three-dimensional (3D) memory array structure 330 Substrate 330f front, main surface, top surface 331 Insulating Film 332 Lower Selection Gate 333, 333-1, 333-2, 333-3 control gate, word line 334 Upper Selection Gate 335 Membrane Stack 336 Channel Hall 337 Memory Film 338 Channel Layer 339 Core-filled membrane 340, 340-1, 340-2, 340-3 memory cells 341 bit lines 343 Metal Interconnect Wire 344 Doped Source Line Region 500, 600, 700, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2300, 2400, 2500, 2600, 2700, 2800, 2900 3D Memory Structure 554 Dielectric Stack 556 Dielectric Layer Pair 558 First Dielectric Layer 560 Second dielectric layer, sacrificial layer 662 Hard Mask 764 Contact Definition Mask 866 Hard Mask Opening 866-t Top surface of first dielectric layer pair 968 First Contact Mask 1070 First Subset of Contact Openings 1070-t Top surface of second dielectric layer pair 1172 Second Contact Mask 1274 Second subset of contact openings 1274-t Top surface of fourth dielectric layer pair 1275 Third subset of contact openings 1275-t Top surface of third dielectric layer pair 1376 Third Contact Mask 1478 Fourth subset of contact openings 1478-t Top surface of eighth dielectric layer pair 1479 Fifth subset of contact openings 1479-t Top surface of sixth dielectric layer pair 1480 Sixth Subset of Contact Openings 1480-t Top surface of fifth dielectric layer pair 1481 Seventh subset of contact openings 1481-t Top surface of seventh dielectric layer pair 1584 Contact filling part 1586 Filling material 1587 Raina 1688 Capping Layer 1690 Epitaxial Layer 1792 Slit Aperture 1894 Conductive layer 1996 Contact Hole 1997 Separation Liner 2098 Common Source Contact BL Bit line direction WL Word Line Direction

Claims

1. a film stack including alternating conductive and dielectric layers; memory strings extending through the film stack, each of the memory strings including a memory film, a channel layer, and a core fill film; a bit line structure disposed on the film stack; a contact structure disposed within the film stack, the contact structure being disposed between the memory strings, each of the memory strings contacting one of the bit line structures; A three-dimensional (3D) memory structure comprising:

2. 10. The 3D memory structure of claim 1, wherein the contact structures extend through one or more of the dielectric layers and the conductive layers, one of the conductive layers being connected to at least one of the contact structures.

3. The 3D memory structure of claim 1 , wherein the contact structure comprises a liner surrounding a conductive material.

4. 4. The 3D memory structure of claim 3, wherein the liner comprises an insulator configured to separate the contact structure from one or more conductive layers of the film stack.

5. 10. The 3D memory structure of claim 1, further comprising a common source contact extending to said film stack, said common source contact being connected to a substrate.

6. 6. The 3D memory structure of claim 5, wherein the common source contact comprises an isolation liner configured to electrically isolate the common source contact from the conductive layers of the film stack.

7. 10. The 3D memory structure of claim 1, further comprising a substrate, the film stack disposed on the substrate, and a side of the contact structure away from the substrate is coplanar with a side of the film stack away from the substrate.

8. The 3D memory structure of claim 1 , wherein the contact structure is surrounded by the memory string.

9. 4. The 3D memory structure of claim 3, wherein the conductive material comprises tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and / or any combination thereof.

10. a film stack including conductive and dielectric layers alternately stacked on top of one another; a plurality of memory strings extending vertically through the film stack; a plurality of contact structures disposed within the film stack, the contact structures comprising a liner surrounding a conductive material; Equipped with the plurality of contact structures extend vertically through one or more of the dielectric layers, one of the conductive layers of the film stack being connected to at least one of the plurality of contact structures; A three-dimensional (3D) memory structure, wherein the contact structure is disposed between the memory strings.

11. 11. The 3D memory structure of claim 10, wherein the plurality of memory strings includes a memory film, a channel layer, and a core fill film.

12. 11. The 3D memory structure of claim 10, wherein the liner comprises an insulator configured to separate the plurality of contact structures from one or more conductive layers of the film stack.

13. 11. The 3D memory structure of claim 10, further comprising a common source contact extending vertically through said film stack, said common source contact connected to a substrate.

14. 14. The 3D memory structure of claim 13, wherein the common source contact comprises an isolation liner configured to isolate the common source contact from the conductive layers of the film stack.

15. 11. The 3D memory structure of claim 10, further comprising a substrate, the film stack disposed on the substrate, and a side of the contact structure away from the substrate is coplanar with a side of the film stack away from the substrate.

16. The 3D memory structure of claim 10 , wherein the contact structure is surrounded by the memory string.

17. 11. The 3D memory structure of claim 10, wherein the conductive material comprises tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and / or any combination thereof.

18. a film stack including conductive and dielectric layers alternately stacked on top of one another; a plurality of memory strings extending vertically through the film stack; a common source contact extending vertically through the film stack; a plurality of contact structures disposed within the film stack; Equipped with the plurality of contact structures extend vertically through one or more of the dielectric layers, one of the conductive layers of the film stack being connected to at least one of the plurality of contact structures; A three-dimensional (3D) memory structure, wherein the contact structure is disposed between the memory strings.

19. 20. The 3D memory structure of claim 18, wherein the plurality of memory strings comprises a memory film, a channel layer, and a core fill film.

20. 20. The 3D memory structure of claim 18, wherein the contact structure comprises a liner surrounding a conductive material.

21. 21. The 3D memory structure of claim 20, wherein the liner comprises an insulator configured to separate the plurality of contact structures from one or more conductive layers of the film stack.

22. 20. The 3D memory structure of claim 18, wherein the common source contact is connected to a substrate.

23. 23. The 3D memory structure of claim 22, wherein the common source contact comprises an isolation liner configured to isolate the common source contact from the conductive layers of the film stack.

24. 20. The 3D memory structure of claim 18, further comprising a substrate, the film stack disposed on the substrate, and a side of the contact structure away from the substrate is coplanar with a side of the film stack away from the substrate.

25. 20. The 3D memory structure of claim 18, wherein the contact structure is surrounded by the memory string.

26. 21. The 3D memory structure of claim 20, wherein the conductive material comprises tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and / or any combination thereof.

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