Semiconductor device and semiconductor module

Abstract

To reduce an inductance.SOLUTION: A semiconductor module 2 comprises: a semiconductor chip having an output electrode and an input electrode; a negative electrode terminal 41 that is contacted to a negative electrode conductive layer 54 of a wiring terminal 51, and is electrically connected to an output electrode of the semiconductor chip; and a positive electrode terminal 40 that is separated from the negative electrode terminal 41, is electrically contacted to a positive electrode conductive layer 53 that is parallel to the negative electrode terminal 41 and is of the wiring terminal 51, and is electrically connected to the input electrode of the semiconductor chip. The semiconductor module 2 further comprises a sealing body 10 in which the positive electrode terminal 40 and the negative electrode terminal 41 are extended to the outside from a long side surface 10a facing the wiring terminal 51 in the same direction from the long side surface 10a, fixes the semiconductor chip, the positive electrode terminal 40, and the negative electrode terminal 41, includes a housing groove 10g between the positive electrode terminal 40 and the negative electrode terminal 41 of the long side surface 10a, and of which an insulation end side of an insulation layer 52 of the wiring terminal 51 is inserted into the housing groove 10g.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a semiconductor module. [Background technology]

[0002] A semiconductor device includes a semiconductor module and a capacitor connected to the semiconductor module (see, for example, Patent Document 1). The semiconductor module includes a semiconductor chip, positive and negative terminals, and a sealing member that seals the semiconductor chip, with the positive and negative terminals extending outward from one surface of the sealing member (see, for example, Patent Documents 2, 3, and 4). Also, a method has been proposed for connecting a bus bar to a semiconductor module that does not rely on tightening bolts (see, for example, Patent Document 5). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-141729 A [Patent Document 2] JP 2019-117944 A [Patent Document 3] International Publication No. 2017 / 119226 [Patent Document 4] International Publication No. 2014 / 002442 [Patent Document 5] International Publication No. 2015 / 162712 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a semiconductor device and a semiconductor module with reduced inductance. [Means for solving the problem]

[0005] According to one aspect of the present invention, there is provided a wiring terminal including an insulating layer, a first conductive layer and a second conductive layer provided on one main surface and the other main surface of the insulating layer, respectively, and an insulating end side of the insulating layer extending outward beyond the conductive end sides of the first conductive layer and the second conductive layer, and a semiconductor module, the semiconductor module including a semiconductor chip having a first electrode and a second electrode, a first end having a first contact surface in contact with the first conductive layer of the wiring terminal, a first terminal electrically connected to the first electrode of the semiconductor chip, and a front end separated from the first end The present invention provides a semiconductor device comprising: a second terminal including a second end having a second contact surface that is parallel to the first contact surface and in electrical contact with the second conductive layer of the wiring terminal, the second terminal being electrically connected to the second electrode of the semiconductor chip; and a fixing portion having a base surface facing the wiring terminal, the first end and the second end extending in the same direction from the base surface to the outside, fixing the semiconductor chip, the first terminal and the second terminal, and having a recess between the first end and the second end on the base surface, and into which the insulating end edge of the insulating layer of the wiring terminal is inserted.

[0006] The fixing portion may be a sealing member. Furthermore, the first end and the second end may be flat, the first end and the second end may be provided on the base surface with a first width direction of the first end and a second width direction of the second end parallel to each other in a planar view, and the recess may be parallel to the first width direction and the second width direction in a planar view.

[0007] The recess may be formed across the base surface in parallel to the first width direction and the second width direction. The first end portion and the second end portion may be provided on the base surface so as to be offset in position in the first width direction and the second width direction, respectively, in a plan view.

[0008] The conductive end sides of the first conductive layer and the second conductive layer of the wiring terminal may be in contact with the base surface of the semiconductor module. The semiconductor device may further include a capacitor including the wiring terminal.

[0009] According to one aspect of the present invention, there is provided a semiconductor module comprising: a first semiconductor chip having a first electrode and a second electrode; a second semiconductor chip having a third electrode and a fourth electrode electrically connected to the first electrode of the first semiconductor chip; a first terminal including a first end having a first contact surface and electrically connected to the first electrode of the first semiconductor chip; a second terminal including a second end having a second contact surface spaced from the first end and parallel to the first contact surface and electrically connected to the fourth electrode of the second semiconductor chip; and a fixing portion, in which the first end and the second end extend outward from the base surface in the same direction from the base surface, fixing the first semiconductor chip, the second semiconductor chip, the first terminal, and the second terminal, and having a recess between the first end and the second end on the base surface.

[0010] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. Effect of the Invention

[0011] According to the disclosed technology, inductance is reduced. [Brief description of the drawings]

[0012] [Figure 1] 1 is a plan view of a semiconductor device according to an embodiment; [Diagram 2] 2 is a side view (XZ plane) of the semiconductor device according to the embodiment. [Diagram 3] 1 is a perspective view of a semiconductor module included in a semiconductor device according to an embodiment; [Figure 4] 2 is a side view (XZ plane) of a semiconductor module included in the semiconductor device of the embodiment. FIG. [Diagram 5] 2 is a side view (ZY plane) of a semiconductor module included in the semiconductor device of the embodiment. FIG. [Figure 6] 2 is a rear view of a semiconductor module included in the semiconductor device according to the embodiment; [Figure 7] 2 is a plan view of a semiconductor unit included in a semiconductor module according to an embodiment; [Figure 8] 2 is a cross-sectional view of a semiconductor unit included in a semiconductor module according to an embodiment; [Figure 9] 2 is a side view (ZY plane) of a semiconductor unit included in the semiconductor module of the embodiment. FIG. [Figure 10] 2 is a plan view of an insulating circuit board included in the semiconductor module according to the embodiment; [Figure 11] 1 is a perspective view of a capacitor included in a semiconductor device according to an embodiment; [Figure 12] 4 is a cross-sectional view of a connection portion of the semiconductor device according to the embodiment; [Figure 13] FIG. 2 is a side view (XZ plane) of the semiconductor device of the reference example. [Figure 14] 1 is a side view (ZY plane) of a semiconductor module included in a semiconductor device according to an embodiment (variation 1); [Figure 15] 1 is a cross-sectional view of a connection portion of a semiconductor device according to an embodiment (variation 1). [Figure 16] 11 is a side view (ZY plane) of a semiconductor module included in the semiconductor device of the embodiment (modification 2). FIG. [Figure 17] 11 is a cross-sectional view of a connection portion of a semiconductor device according to an embodiment (modification 2). FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, the embodiment will be described with reference to the drawings. In the following description, the terms "front surface" and "upper surface" refer to the XY surface facing upward (+Z direction) in the semiconductor device 1 of the drawing. Similarly, "up" refers to the upward (+Z direction) direction in the semiconductor device 1 of the drawing. The terms "rear surface" and "lower surface" refer to the XY surface facing downward (-Z direction) in the semiconductor device 1 of the drawing. Similarly, "lower" refers to the downward (-Z direction) direction in the semiconductor device 1 of the drawing. The same directionality as above is also used in other drawings as necessary. "High position" refers to the upper (+Z direction) position in the semiconductor device 1 of the drawing. Similarly, "low position" refers to the lower (-Z direction) position in the semiconductor device 1 of the drawing. The terms "front surface", "upper surface", "upper" and "rear surface", "lower surface", "lower" and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical idea of ​​the present invention. For example, "upper" and "lower" do not necessarily mean a vertical direction with respect to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. In the following description, "main component" refers to a content of 80 vol% or more. "Almost the same" means within a range of ±10%. "Perpendicular", "orthogonal" and "parallel" means within a range of ±10°.

[0014] [Embodiment Mode] A semiconductor device according to an embodiment will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a plan view of the semiconductor device according to the embodiment, and Fig. 2 is a side view (XZ plane) of the semiconductor device according to the embodiment. Fig. 2 is a side view of the semiconductor device 1 of Fig. 1 as viewed in the +Y direction.

[0015] The semiconductor device 1 includes three semiconductor modules 2a to 2c and a capacitor 5. The semiconductor modules 2a to 2c all have the same configuration and the same functions. In the following description, the semiconductor modules 2a to 2c will be referred to as semiconductor modules 2 when there is no need to distinguish between them.

[0016] A front side and a back side of a wiring terminal 51, which is included in the capacitor 5 and will be described later, are clamped by a positive terminal 40 and a negative terminal 41, which are included in the semiconductor module 2 and will be described later, respectively, to connect the semiconductor module 2 and the capacitor 5. The positive terminal 40 and the negative terminal 41 of the semiconductor module 2 are connected to the wiring terminal 51 of the capacitor 5 by nuts and bolts, respectively. The details of this connection will be described later.

[0017] Next, the appearance of the semiconductor module 2 of the embodiment will be described with reference to Figs. 3 to 6. Fig. 3 is a perspective view of the semiconductor module included in the semiconductor device of the embodiment. Fig. 4 is a side view (XZ plane) of the semiconductor module included in the semiconductor device of the embodiment. Fig. 5 is a side view (ZY plane) of the semiconductor module included in the semiconductor device of the embodiment. Fig. 6 is a rear view of the semiconductor module included in the semiconductor device of the embodiment.

[0018] 4 is a side view of the semiconductor module 2 in FIG. 3 as seen in the -Y direction, and FIG. 5 is a side view of the semiconductor module 2 in FIG. 3 as seen in the +X direction. FIG. 6 is a rear view of the semiconductor module 2 in FIG. 3 as seen in the +Z direction. FIG. 4 can be referred to for the side view of the semiconductor module 2 in FIG. 5 as seen in the -Y direction. Although the side view of the semiconductor module 2 in FIG. 3 as seen in the -X direction is omitted, only the output terminal 42 extends to the long side surface 10c.

[0019] The semiconductor module 2 includes a semiconductor unit 3 (FIGS. 8 to 10) described later and a sealing body 10 that seals the semiconductor unit 3. The sealing body 10 is an example of a fixing part, and fixes a semiconductor chip 30, a positive terminal 40, and a negative terminal 41 included in the semiconductor unit 3. The sealing body 10 is a cube and includes an upper surface 10e that is rectangular in a plan view and a bottom surface 10f that faces the upper surface 10e. The sealing body 10 further includes a long side surface 10a, a short side surface 10b, a long side surface 10c, and a short side surface 10d that surround the upper surface 10e and the bottom surface 10f in that order on all four sides.

[0020] The top surface 10e and the bottom surface 10f have substantially the same shape and are substantially the same size. The top surface 10e and the bottom surface 10f are each substantially smooth overall. The top surface 10e and the bottom surface 10f are also substantially parallel to each other. The control terminals 43a and 43b included in the semiconductor unit 3 each extend vertically upward (in the +Z direction) from the top surface 10e. The back surface of the metal layer 23 of the insulating circuit board 20 (described later) included in the semiconductor unit 3 is exposed from the bottom surface 10f. The metal layer 23 is substantially flush with the bottom surface 10f.

[0021] The long side surfaces 10a, 10c connect the long sides of the top surface 10e and the bottom surface 10f, respectively. The connection points form an approximately right angle. The connection points are not limited to right angles, and may be R-chamfered or C-chamfered. The long side surface 10a is a base surface, and the positive electrode terminal 40 and the negative electrode terminal 41 included in the semiconductor unit 3 each extend vertically (in the -X direction). In a side view (in the +X direction), the negative electrode terminal 41 is located on the top surface 10e side, and the positive electrode terminal 40 is located on the bottom surface 10f side.

[0022] In addition, the long side surface 10a has a storage groove 10g, which is a recess, formed between the positive terminal 40 and the negative terminal 41 (the upper surface 10e and the bottom surface 10f) in a side view (viewed in the +X direction). The storage groove 10g is formed in the long side surface 10a so as to cross the width of the long side surface 10a in the ±Y direction. In addition, the storage groove 10g is parallel to the width direction of each of the positive terminal 40 and the negative terminal 41 in a plan view. The depth (in the +X direction) and the width (in the ±Z direction) of the storage groove 10g may be a size that allows the tip of the insulating layer 52 protruding from the positive conductive layer 53 and the negative conductive layer 54 of the wiring terminal 51 of the capacitor 5, which will be described later, to be completely inserted. The depth (in the +X direction) of the storage groove 10g may be a depth that does not reach the connection region 41b (see FIG. 8) of the negative terminal 41 in the sealing body 10. In order to maintain the insulation of the connection region 41b of the negative electrode terminal 41, the distance (in the ±X direction) between the bottom of the storage groove 10g and the connection region 41b of the negative electrode terminal 41 in the sealing body 10 may be about 1 mm. The opening of the storage groove 10g may be R-chamfered or C-chamfered.

[0023] An output terminal 42 included in the semiconductor unit 3 extends vertically (in the +X direction) at the center of the long side surface 10c. The output terminal 42 may be located at approximately the same height as the positive terminal 40.

[0024] The short side surfaces 10b and 10d connect the short sides of the top surface 10e and the bottom surface 10f, respectively. Furthermore, the short side surfaces 10b and 10d connect both sides of the long side surfaces 10a and 10c, respectively (along the circumferential direction of the sealing body 10). The respective connection points form approximately right angles. The connection points are not limited to right angles, and may be R-chamfered or C-chamfered.

[0025] Such a sealing body 10 is mainly composed of a thermosetting resin. Examples of the thermosetting resin include epoxy resin, phenol resin, and maleimide resin. The thermosetting resin may also contain a filler. Examples of the filler include silicon oxide, aluminum oxide, boron nitride, and aluminum nitride.

[0026] Next, the semiconductor unit 3 will be described with reference to Figs. 7 to 10. Fig. 7 is a plan view of the semiconductor unit included in the semiconductor module of the embodiment, and Fig. 8 is a cross-sectional view of the semiconductor unit included in the semiconductor module of the embodiment. Fig. 9 is a side view (ZY plane) of the semiconductor unit included in the semiconductor module of the embodiment. Fig. 10 is a plan view of an insulating circuit board included in the semiconductor module of the embodiment. Fig. 8 is a cross-sectional view taken along dashed dotted line YY in Fig. 7. Fig. 9 is a side view of the semiconductor unit 3 of Fig. 7 as viewed in the +X direction. Also, Figs. 8 and 9 omit illustration of control terminals 43a, 43b and various wires.

[0027] The semiconductor unit 3 includes an insulating circuit board 20, a semiconductor chip 30, a control wire 36, a sense wire 37, a main current wire 38, a positive terminal 40, a negative terminal 41, an output terminal 42, and control terminals 43a, 43b.

[0028] The insulating circuit board 20 is rectangular in plan view. The insulating circuit board 20 has an insulating layer 21, a plurality of circuit pattern layers formed on the front surface of the insulating layer 21, and a metal layer 23 formed on the back surface of the insulating layer 21. The plurality of circuit pattern layers include a positive circuit pattern layer 22a, a negative circuit pattern layer 22b, an output circuit pattern layer 22c, control circuit pattern layers 22d and 22f, and sense circuit pattern layers 22e and 22g. Hereinafter, when there is no particular distinction between these, they will be referred to as circuit pattern layers. The outer shapes of the plurality of circuit pattern layers and the metal layer 23 are smaller than the outer shape of the insulating layer 21 in plan view, and are formed inside the insulating layer 21. The shapes, numbers, and sizes of the plurality of circuit pattern layers are merely examples.

[0029] The insulating layer 21 has a rectangular shape in a plan view. The corners of the insulating layer 21 may be chamfered. For example, the corners may be C-chamfered or R-chamfered. The insulating layer 21 is surrounded on all four sides by the long side 21a, the short side 21b, the long side 21c, and the short side 21d, which are the outer periphery. Such an insulating layer 21 is made of ceramics with good thermal conductivity. The ceramics are made of a material mainly composed of aluminum oxide, aluminum nitride, or silicon nitride, for example.

[0030] The metal layer 23 has a rectangular shape in a plan view. The corners may be, for example, C-chamfered or R-chamfered. The metal layer 23 is smaller than the size of the insulating layer 21 and is formed on the entire back surface of the insulating layer 21 except for the edges. The metal layer 23 is mainly composed of a metal having excellent thermal conductivity. The metal is, for example, copper, aluminum, or an alloy containing at least one of these. A plating process may be performed to improve the corrosion resistance of the metal plate. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy.

[0031] As described above, the multiple circuit pattern layers include the positive circuit pattern layer 22a, the negative circuit pattern layer 22b, the output circuit pattern layer 22c, the control circuit pattern layers 22d and 22f, and the sense circuit pattern layers 22e and 22g. The multiple circuit pattern layers are formed on the entire surface except for the edges of the insulating layer 21. Preferably, in a plan view, the ends of the multiple circuit pattern layers facing the outer periphery of the insulating layer 21 overlap with the end of the metal layer 23 on the outer periphery side of the insulating layer 21.

[0032] The multiple circuit pattern layers are made of a metal having excellent electrical conductivity. Such metals are, for example, copper, aluminum, or an alloy containing at least one of these. Furthermore, the surfaces of the multiple circuit pattern layers may be plated to improve corrosion resistance. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy.

[0033] The positive electrode circuit pattern layer 22a included in the multiple circuit pattern layers is F-shaped in a plan view and is formed facing the long side surface 21a of the insulating layer 21. The positive electrode circuit pattern layer 22a includes a terminal region 22a1 and chip regions 22a2 and 22a3.

[0034] The terminal region 22a1 has a rectangular shape in a plan view. The terminal region 22a1 is formed on the front surface of the insulating layer 21, extending parallel to the long side surface 21a (longitudinal direction). The end of the terminal region 22a1 in the -Y direction is a predetermined distance away from the center line C of the front surface of the insulating layer 21 toward the short side surface 21b. The center line C passes through the centers of the long sides 21a and 21c and is parallel to the short sides 21b and 21d. There is a gap between the end of the terminal region 22a1 in the +Y direction and the short side surface 21b. The terminal region 22a1 faces the long side surface 21a. The dashed line area (arrangement area Ta) shown in the terminal region 22a1 is the joining point of the positive electrode terminal 40.

[0035] The chip region 22a2 has a rectangular shape in a plan view. The chip region 22a2 extends from the end of the terminal region 22a1 in the +Y direction toward the long side surface 21c in parallel with the short side surfaces 21b and 21d (short direction). There is a gap between the end of the chip region 22a2 in the +X direction and the long side surface 21c. The end of the chip region 22a2 in the +Y direction and the end of the terminal region 22a1 in the +Y direction form the same plane. The two dashed line areas shown in the chip region 22a2 are the joining points of the semiconductor chip 30.

[0036] The chip region 22a3 has a rectangular shape in a plan view. The chip region 22a3 is connected to a position at a predetermined distance in the +Y direction from the end of the terminal region 22a1 in the -Y direction, and extends toward the long side surface 21c in parallel to the short side surfaces 21b and 21d. There is a gap between the end of the chip region 22a3 in the +X direction and the long side surface 21c. The ends of the chip regions 22a2 and 22a3 in the +X direction form the same plane. There is a gap between the end of the chip region 22a3 in the -Y direction and the center line C. There is a gap between the end of the chip region 22a2 in the -Y direction and the end of the chip region 22a3 in the +Y direction. The two dashed line regions shown in the chip region 22a3 are the joining points of the semiconductor chip 30. The width of the chip region 22a3 in the ±Y direction is approximately equal to the width of the chip region 22a2 in the same direction.

[0037] The negative electrode circuit pattern layer 22b included in the multiple circuit pattern layers is J-shaped in plan view and is formed facing the long side surface 21a of the insulating layer 21. The negative electrode circuit pattern layer 22b includes a terminal region 22b1 and wiring regions 22b2 and 22b3.

[0038] The terminal region 22b1 has a rectangular shape in a plan view. The terminal region 22b1 is formed on the front surface of the insulating layer 21, extending parallel to the long side surface 21a (longitudinal direction). The end of the terminal region 22b1 in the +Y direction is a predetermined distance away from the center line C of the front surface of the insulating layer 21 toward the short side surface 21d. The end of the terminal region 22b1 in the +Y direction and the end of the terminal region 22a1 in the -Y direction are symmetrical with respect to the center line C. The terminal region 22b1 faces the long side surface 21a. The dashed line area (arrangement area Tb) shown in the terminal region 22b1 is the joining point of the negative electrode terminal 41.

[0039] The wiring region 22b2 has a rectangular shape in a plan view. The wiring region 22b2 extends from the end of the terminal region 22b1 in the +Y direction toward the long side surface 21c in parallel with the short side surfaces 21b and 21d (short direction). A gap is provided between the end of the wiring region 22b2 in the +X direction and the long side surface 21c. The end of the wiring region 22b2 in the +Y direction and the end of the terminal region 22b1 in the +Y direction are flush with each other.

[0040] The wiring region 22b3 has a rectangular shape in a plan view. The wiring region 22b3 extends from the end of the terminal region 22b1 in the -Y direction toward the long side surface 21c in parallel with the short side surfaces 21b and 21d (short direction). The end of the wiring region 22b3 in the +X direction is formed with the edge of the long side surface 21c side left open. Furthermore, the end of the wiring region 22b3 in the -Y direction faces the short side surface 21d. The end of the wiring region 22b3 in the -Y direction and the end of the terminal region 22b1 in the -Y direction are flush with each other. The width of the wiring region 22b3 in the ±Y direction is approximately equal to the width of the wiring region 22b2 in the same direction.

[0041] The output circuit pattern layer 22c included in the multiple circuit pattern layers has a comb-like shape in a plan view and is formed facing the long side surface 21c of the insulating layer 21. The output circuit pattern layer 22c includes a terminal region 22c1, wiring regions 22c2 and 22c3, and chip regions 22c4 and 22c5.

[0042] The terminal region 22c1 has a rectangular shape in a plan view. The terminal region 22c1 is formed on the front surface of the insulating layer 21, extending parallel to the long side surface 21c (longitudinal direction). The end of the terminal region 22c1 in the +Y direction faces the short side surface 21b on the front surface of the insulating layer 21. The end of the terminal region 22c1 in the -Y direction is formed with a gap from the short side surface 21d. The terminal region 22c1 also faces the long side surface 21c. The dashed line area (arrangement area Tc) shown in the terminal region 22c1 is the joining point of the output terminal 42.

[0043] The wiring area 22c2 has a rectangular shape in a plan view. The wiring area 22c2 extends from the end of the terminal area 22c1 in the +Y direction toward the long side surface 21a in parallel to the short sides 21b and 21d (short direction). The end of the wiring area 22c2 in the -X direction faces the long side surface 21a. The end of the wiring area 22c2 in the +Y direction and the end of the terminal area 22c1 in the +Y direction are flush with each other.

[0044] The wiring region 22c3 has a rectangular shape in a plan view. The wiring region 22c3 is parallel to the short side surfaces 21b and 21d (short direction) from the terminal region 22c1 and extends between the chip region 22a3 and the wiring region 22b2 toward the long side surface 21a. The end of the wiring region 22c3 in the -X direction faces the terminal region 22a1. The width of the wiring region 22c3 in the ±Y direction corresponds to the distance between the chip region 22a3 and the wiring region 22b2 and is approximately equal to the width of the wiring region 22c2 in the same direction.

[0045] The chip region 22c4 has a rectangular shape in a plan view. The chip region 22c4 extends from the terminal region 22c1 between the wiring region 22b2 and the control circuit pattern layer 22f described later, parallel to the short sides 21b and 21d (short direction) toward the long side 21a. The end of the chip region 22c4 in the -X direction faces the terminal region 22b1. The two dashed line regions shown in the chip region 22c4 are the bonding points of the semiconductor chip 30.

[0046] The chip region 22c5 has a rectangular shape in a plan view. The chip region 22c5 extends from the end of the terminal region 22c1 in the -Y direction to the long side surface 21a in parallel with the short side surfaces 21b and 21d (short direction) between the wiring region 22b3 and the sense circuit pattern layer 22g described later. The end of the chip region 22c5 in the -X direction faces the terminal region 22b1. The ends of the chip regions 22c4 and 22c5 and the wiring region 22c3 in the -X direction form the same plane. The end of the chip region 22c5 in the -Y direction and the end of the terminal region 22c1 in the -Y direction form the same plane. The two dashed line regions shown in the chip region 22c5 are the joining points of the semiconductor chip 30. The width of the chip region 22c5 in the ±Y direction is approximately equal to the width of the chip region 22c4 in the same direction. The width of the gap between the end of chip region 22c5 in the +Y direction and the end of chip region 22c4 in the -Y direction is approximately equal to the width of chip regions 22c4 and 22c5 in the same direction.

[0047] The control circuit pattern layer 22d and the sense circuit pattern layer 22e included in the multiple circuit pattern layers are rectangular in plan view and are formed in parallel to the short side surfaces 21b, 21d (short side direction) in an area surrounded by the positive electrode circuit pattern layer 22a and the terminal area 22c1 of the output circuit pattern layer 22c. The widths in the ±Y directions of the control circuit pattern layer 22d and the sense circuit pattern layer 22e are smaller than the width in the same direction of the wiring area 22c2.

[0048] The control circuit pattern layer 22f and the sense circuit pattern layer 22g included in the multiple circuit pattern layers are rectangular in plan view and are formed in parallel to the short side surfaces 21b and 21d (short side direction) in an area surrounded by the terminal area 22b1 of the negative electrode circuit pattern layer 22b and the terminal area 22c1 and the chip areas 22c4 and 22c5 of the output circuit pattern layer 22c. The widths in the ±Y directions of the control circuit pattern layer 22f and the sense circuit pattern layer 22g are smaller than the width in the same direction of the wiring area 22c2.

[0049] For example, a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazed) board may be used as the insulating circuit board 20 having such a configuration. The insulating circuit board 20 dissipates heat by conducting heat generated in the semiconductor chip 30 to the back side of the insulating circuit board 20 via the positive circuit pattern layer 22a, the negative circuit pattern layer 22b, the insulating layer 21, and the metal layer 23.

[0050] The semiconductor chip 30 is a power device made of silicon carbide. An example of this power device is a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). In a power MOSFET, a body diode functions as a FWD (Free Wheeling Diode). The semiconductor chip 30 has a drain electrode as an input electrode on the back surface, and a gate electrode as a control electrode 31 and a source electrode as an output electrode on the front surface.

[0051] The semiconductor chip 30 may also be a power device made of silicon. In this case, the power device is, for example, an RC (Reverse Conducting)-IGBT (Insulated Gate Bipolar Transistor). The RC-IGBT is a circuit in which an IGBT, which is a switching element, and an FWD, which is a diode element, are connected in reverse parallel, and the circuit is configured within one chip. The semiconductor chip 30 has, for example, a collector electrode as an input electrode on the back surface, and a gate electrode as a control electrode and an emitter electrode as an output electrode on the front surface.

[0052] In this embodiment, a plurality of semiconductor chips 30 are arranged on the positive circuit pattern layer 22a and the output circuit pattern layer 22c via the bonding member 35. In this embodiment, two semiconductor chips 30 are arranged along the short side surfaces 21b and 21d in the chip areas 22a2 and 22a3 of the positive circuit pattern layer 22a and the chip areas 22c4 and 22c5 of the output circuit pattern layer 22c. In this embodiment, the two semiconductor chips 30 arranged in the chip areas 22a2 and 22a3 of the positive circuit pattern layer 22a and the chip areas 22c4 and 22c5 of the output circuit pattern layer 22c are arranged so that their control electrodes 31 face each other.

[0053] The positive electrode terminal 40, the negative electrode terminal 41, the output terminal 42, and the control terminals 43a and 43b are made of a metal having excellent electrical conductivity. Such metals are, for example, copper, copper alloys, aluminum, and aluminum alloys. In order to improve the corrosion resistance of the metal plates of the positive electrode terminal 40, the negative electrode terminal 41, the output terminal 42, and the control terminals 43a and 43b, a plating process may be performed. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy.

[0054] The positive terminal 40 has a flat plate shape. A positive electrode bonding area 40a, which is an inner end of the positive terminal 40, is bonded to an arrangement area Ta of a terminal area 22a1 of the positive circuit pattern layer 22a via a bonding member 35. That is, the positive terminal 40 is electrically connected to an input electrode on the back surface of the semiconductor chip 30. An outer end (first end) of the positive terminal 40 extends vertically (in the -X direction) from the terminal area 22a1 of the positive circuit pattern layer 22a. The corners of the outer end of the positive terminal 40 may be R-chamfered or C-chamfered. A contact surface 40c1 on the front surface side of the outer end of the positive terminal 40 contacts a positive conductive layer 53 included in a wiring terminal 51 of the capacitor 5 described later. In addition, a fastening hole 40d may be formed penetrating the outer end of the positive terminal 40. A bus bar may be attached using such a fastening hole 40d. The positive electrode terminal 40 has a generally uniform thickness and a uniform width (in the ±Y direction in FIG. 7). The thickness of the positive electrode terminal 40 is, for example, 0.4 mm or more and 0.6 mm or less. The length of the positive electrode terminal 40 extending from the long side surface 10a of the sealing body 10 in the −X direction is, for example, 20 mm or more and 30 mm or less.

[0055] The negative electrode terminal 41 includes a negative electrode bonding region 41a, a linking region 41b, and a wiring region 41c. The negative electrode bonding region 41a, the linking region 41b, and the wiring region 41c are all flat. The negative electrode terminal 41 has a generally uniform thickness and a uniform width (in the ±Y direction in FIG. 7). In a plan view, the width direction (±Y direction) of the negative electrode terminal 41 is parallel to the width direction (±Y direction) of the positive electrode terminal 40. Therefore, the width directions of the negative electrode terminal 41 and the positive electrode terminal 40 are parallel to the long side surface 10a of the sealing body 10. In addition, the negative electrode terminal 41 is misaligned in the width direction (±Y direction) with respect to the positive electrode terminal 40. The negative electrode bonding region 41a, which is the inner end of the negative electrode terminal 41, is bonded to the arrangement region Tb of the terminal region 22b1 of the negative electrode circuit pattern layer 22b via the bonding member 35. The linking region 41b is connected to the end (in the -X direction in FIG. 7) of the negative electrode bonding region 41a and extends vertically upward (in the +Z direction). The wiring region 41c is connected to the linking region 41b and extends vertically (in the -X direction) from the terminal region 22b1 of the negative electrode circuit pattern layer 22b. Therefore, the wiring region 41c of the negative electrode terminal 41 is separated in the +Z direction from the front surface of the insulating circuit board 20 by the height of the linking region 41b. In addition, the corners of the outer end of the wiring region 41c of the negative electrode terminal 41 may be R-chamfered or C-chamfered. A contact surface 41c1 on the back side of the outer end of the negative electrode terminal 41 (wiring region 41c) contacts a negative electrode conductive layer 54 included in a wiring terminal 51 of the capacitor 5 described later. The contact surface 41c1 of the negative electrode terminal 41 is parallel to the contact surface 40c1 of the positive electrode terminal 40 in a side view. A fastening hole 41d may be formed through an outer end of the negative electrode terminal 41. A wiring terminal 51 of the capacitor 5 described below may be attached using such fastening hole 41d. The thickness of the negative electrode terminal 41 is, for example, 0.4 mm or more and 0.6 mm or less. In addition, the length of the negative electrode terminal 41 extending in the -X direction from the long side surface 10a of the sealing body 10 is, for example, 20 mm or more and 30 mm or less.

[0056] The output terminal 42 is in the shape of a flat plate. An output joint area 42a, which is an inner end of the output terminal 42, is joined to an arrangement area Tc of the terminal area 22c1 of the output circuit pattern layer 22c via a joint member 35. The outer end of the output terminal 42 extends vertically (in the +X direction) from the terminal area 22c1 of the output circuit pattern layer 22c. The corners of the outer end of the output terminal 42 may be round-chamfered or C-chamfered. A through hole may be formed in the outer end of the output terminal 42. A bus bar may be attached using such a through hole. The output terminal 42 has a generally uniform thickness and a uniform width (in the ±Y direction in FIG. 7) as a whole.

[0057] The control terminals 43a and 43b are columnar. The columnar shape may be a polygonal, circular, or elliptical cross section. The lower end of the control terminal 43a is joined to the ends of the long side surfaces 21a of the control circuit pattern layer 22d and the sense circuit pattern layer 22e by a joining member 35 (not shown). The upper end of the control terminal 43a extends vertically upward (+Z direction) from the control circuit pattern layer 22d and the sense circuit pattern layer 22e. The lower end of the control terminal 43b is joined to the ends of the long side surfaces 21a of the control circuit pattern layer 22f and the sense circuit pattern layer 22g by a joining member 35 (not shown). The upper end of the control terminal 43b extends vertically upward (+Z direction) from the control circuit pattern layer 22f and the sense circuit pattern layer 22g.

[0058] The control wire 36, the sense wire 37, and the main current wire 38 are mainly made of a material having excellent electrical conductivity. Such a material is, for example, gold, copper, aluminum, or an alloy containing at least one of these. The diameter of the control wire 36 and the sense wire 37 may be smaller than the diameter of the main current wire 38.

[0059] The control wires 36 (on the +Y direction side in FIG. 7) directly connect the control electrodes 31 of each semiconductor chip 30 to the control circuit pattern layer 22d, respectively. The control wires 36 (on the -Y direction side in FIG. 7) directly connect the control electrodes 31 of each semiconductor chip 30 to the control circuit pattern layer 22f, respectively.

[0060] The sense wires 37 (on the +Y side in FIG. 7) directly connect the output electrodes of each semiconductor chip 30 to the sense circuit pattern layer 22e, respectively. The sense wires 37 (on the -Y side in FIG. 7) directly connect the output electrodes of each semiconductor chip 30 to the sense circuit pattern layer 22g, respectively.

[0061] The main current wires 38 (on the +Y direction side in FIG. 7) directly connect the output electrodes of each semiconductor chip 30 to the wiring regions 22c2, 22c3 of the output circuit pattern layer 22c. The main current wires 38 (on the -Y direction side in FIG. 7) directly connect the output electrodes of each semiconductor chip 30 to the wiring regions 22b2, 22b3 of the negative circuit pattern layer 22b. The main current wires 38 are wired in parallel to the long sides 21a, 21c.

[0062] Next, capacitor 5 will be described with reference to Fig. 11. Fig. 11 is a perspective view of a capacitor included in the semiconductor device of the embodiment. Capacitor 5 includes a housing 50 and a wiring terminal 51.

[0063] The housing 50 is a capacitor body. The housing 50 includes a top surface 50e, a bottom surface 50f, a long side surface 50a, a short side surface 50b, a long side surface 50c, and a short side surface 50d. The top surface 50e and the bottom surface 50f have the same shape and size, and form a rectangle in a plan view. The long side surface 50a, the short side surface 50b, the long side surface 50c, and the short side surface 50d surround the top surface 50e and the bottom surface 50f in order on all four sides. The long side surfaces 50a and 50c correspond to the long sides of the top surface 50e and the bottom surface 50f. The short side surfaces 50b and 50d correspond to the short sides of the top surface 50e and the bottom surface 50f. The material of the housing 50 is, for example, epoxy resin. A plurality of capacitor components having N poles and P poles (not shown) are stored in the housing 50.

[0064] The wiring terminal 51 includes an insulating layer 52, a positive electrode conductive layer 53, and a negative electrode conductive layer 54. The insulating layer 52 is made of an insulating material having insulating properties. Such insulating materials are mainly composed of, for example, insulating paper made of a wholly aromatic polyamide polymer, or a fluorine-based or polyimide-based resin material. The insulating layer 52 is formed in a sheet shape from such insulating material. The insulating layer 52 extends outward from the long side surface 50a of the housing 50. The insulating layer 52 is sandwiched between the positive electrode conductive layer 53 and the negative electrode conductive layer 54 as described later, and maintains the insulation of the positive electrode conductive layer 53 and the negative electrode conductive layer 54. The insulating layer 52 maintains the insulation between the positive electrode conductive layer 53 and the negative electrode conductive layer 54 even inside the housing 50. The insulating layer 52 has holes formed at locations facing the positive electrode fastening hole 53a, the negative electrode opening hole 53b, the negative electrode fastening hole 54a, and the positive electrode opening hole 54b described later.

[0065] The positive electrode conductive layer 53 is electrically connected to the P electrodes of the capacitor components in the housing 50, and extends outward from the long side surface 50a of the housing 50. The portion of the positive electrode conductive layer 53 that extends outward is flat and is provided on the back surface of the insulating layer 52. The positive electrode conductive layer 53 has a positive electrode fastening hole 53a and a negative electrode opening hole 53b formed therein (see FIG. 12). A set of the positive electrode fastening hole 53a and the negative electrode opening hole 53b is provided corresponding to the number of the semiconductor modules 2 to be attached to the wiring terminal 51. The positive electrode fastening hole 53a is fastened to the positive electrode terminal 40 of the semiconductor module 2 with a bolt. The negative electrode opening hole 53b has a diameter sufficiently larger than that of the positive electrode fastening hole 53a. A bolt for fastening the negative electrode terminal 41 of the semiconductor module 2 is inserted into the negative electrode opening hole 53b without touching it.

[0066] The negative electrode conductive layer 54 is electrically connected to the N poles of the capacitor components in the housing 50 and extends outward from the long side surface 50a of the housing 50. The negative electrode conductive layer 54 has a flat plate-like portion extending outward and is provided on the front surface side of the insulating layer 52. The portion of the negative electrode conductive layer 54 extending outward has the same shape and size as the portion of the positive electrode conductive layer 53 extending outward. The negative electrode conductive layer 54 has negative fastening holes 54a and positive opening holes 54b formed therein (see FIG. 12). A set of the negative fastening holes 54a and the positive opening holes 54b is provided corresponding to the number of the semiconductor modules 2 attached to the wiring terminal 51. The negative fastening holes 54a are fastened to the negative terminals 41 of the semiconductor modules 2 with bolts. The positive opening holes 54b have a diameter sufficiently larger than that of the negative fastening holes 54a. A bolt for fastening the positive electrode terminal 40 of the semiconductor module 2 is inserted through the positive electrode opening hole 54b without touching it.

[0067] In such a wiring terminal 51, the positive fastening hole 53a corresponds to the positive opening hole 54b, and the negative fastening hole 54a corresponds to the negative opening hole 53b in a plan view. The insulating layer 52 is larger than the positive conductive layer 53 and the negative conductive layer 54 at least in the outer portion of the long side surface 50a of the housing 50. Therefore, the outer edge (end side) of the insulating layer 52 sandwiched between the positive conductive layer 53 and the negative conductive layer 54 protrudes from the outer edges (end sides) of the positive conductive layer 53 and the negative conductive layer 54, respectively. The protruding length of the insulating layer 52 is, for example, 1.0 mm or more and 1.4 mm or less. Therefore, the insulation distance between the positive conductive layer 53 and the negative conductive layer 54 is maintained, and the insulation properties of the positive conductive layer 53 and the negative conductive layer 54 are maintained.

[0068] Next, the connection between the semiconductor module 2 and the capacitor 5 will be described with reference to Figs. 1, 2, and 12. Fig. 12 is a cross-sectional view of a connection portion of the semiconductor device according to the embodiment. Fig. 12 is a cross-sectional view taken along dashed line XX in Figs. 1 and 2 when the semiconductor module 2 and the capacitor 5 are connected by a bolt 55a and a nut 55b. Here, the bolt 55a and the nut 55b are made of, for example, a conductive metal.

[0069] The long side surfaces 10a of the plurality of (here, for example, three) semiconductor modules 2 are opposed to the long side surface 50a of the capacitor 5, and the plurality of semiconductor modules 2 are moved to the capacitor 5. As a result, as shown in FIG. 1 and FIG. 2, the wiring terminal 51 of the capacitor 5 is sandwiched between the positive terminal 40 and the negative terminal 41 of the plurality of semiconductor modules 2. That is, the positive terminal 40 of the plurality of semiconductor modules 2 contacts the back surface of the positive conductive layer 53 of the wiring terminal 51. At this time, the tip of the positive conductive layer 53 of the wiring terminal 51 contacts the long side surface 10a of the semiconductor module 2. The negative terminal 41 of the plurality of semiconductor modules 2 contacts the front surface of the negative conductive layer 54 of the wiring terminal 51. At this time, the tip of the negative conductive layer 54 of the wiring terminal 51 contacts the long side surface 10a of the semiconductor module 2. Furthermore, the tip of the insulating layer 52 enters (is stored in) the storage groove 10g of the long side surface 10a of the semiconductor module 2.

[0070] After the wiring terminal 51 of the capacitor 5 is attached between the positive terminal 40 and the negative terminal 41 of the semiconductor module 2, as shown in FIG. 12, the bolt 55a is inserted into the fastening hole 41d of the negative terminal 41 and the negative fastening hole 54a of the negative conductive layer 54 from the front side of the negative terminal 41. The lower end of the bolt 55a is exposed from the negative opening hole 53b of the positive conductive layer 53, and the nut 55b is fastened to the lower end in the negative opening hole 53b of the positive conductive layer 53. At this time, since the diameter of the negative opening hole 53b of the positive conductive layer 53 is sufficiently larger than the diameter of the nut 55b, the bolt 55a and the nut 55b do not come into contact with the positive conductive layer 53, and insulation is maintained. That is, insulation is maintained between the negative terminal 41 and the positive conductive layer 53.

[0071] Similarly, the bolt 55a is inserted through the positive electrode opening hole 54b of the negative electrode conductive layer 54, into the positive electrode fastening hole 53a of the positive electrode conductive layer 53 and into the fastening hole 40d of the positive electrode terminal 40. The lower end of the bolt 55a is exposed from the fastening hole 40d of the positive electrode terminal 40, and a nut 55b is fastened to the lower end. At this time, since the diameter of the positive electrode opening hole 54b of the negative electrode conductive layer 54 is sufficiently larger than the diameter of the bolt 55a, the bolt 55a and the negative electrode conductive layer 54 do not come into contact with each other, and insulation is maintained. That is, insulation is maintained between the positive electrode terminal 40 and the negative electrode conductive layer 54. As described above, the semiconductor device 1 is configured by mechanically and electrically connecting the semiconductor modules 2 and the capacitors 5 .

[0072] Here, a reference example of the semiconductor device 1 of the embodiment will be described. The semiconductor module included in the semiconductor device of the reference example does not have a storage groove 10g for the semiconductor module 2. Such a semiconductor device of the reference example will be described with reference to FIG. 13. FIG. 13 is a side view (XZ plane) of the semiconductor device of the reference example. Note that FIG. 13 corresponds to FIG. 2 in the semiconductor device 100 of the reference example.

[0073] The semiconductor device 100 includes a plurality of semiconductor modules 200 and a capacitor 5. The capacitor 5 is similar to the capacitor 5 of the embodiment. The semiconductor module 200 does not have a storage groove 10g formed on the long side surface 10a included in the semiconductor module 2 of the embodiment, and the entire long side surface 10a is flat. The semiconductor module 200 has the same configuration as the semiconductor module 2, except for the long side surface 10a.

[0074] The wiring terminal 51 of the capacitor 5 and the positive terminals 40 and negative terminals 41 of the semiconductor modules 200 are attached as shown in Fig. 13 (see also Fig. 1). In this case, the end (in the +X direction) of the wiring terminal 51 (insulating layer 52) abuts against the long side surface 10a of the semiconductor module 200. A gap G is provided between the ends (in the +X direction) of the positive conductive layer 53 and the negative conductive layer 54 and the long side surface 10a of the semiconductor module 200.

[0075] The inductance component of the semiconductor device 100 depends on the length between the wiring terminal 51 of the capacitor 5 and the positive terminal 40 and the negative terminal 41 of the semiconductor module 200. The wiring terminal 51 of the capacitor 5 has an insulating layer 52 sandwiched (laminated) between the positive conductive layer 53 and the negative conductive layer 54, thereby reducing the inductance. It is also desirable to laminate the positive terminal 40 and the negative terminal 41 of the semiconductor module 200 using such wiring terminal 51. This results in a positional relationship between the wiring terminal 51 and the positive terminal 40 and the negative terminal 41 such that the currents traveling back and forth in response to switching overlap each other. As a result, the magnetic fields are offset, thereby suppressing the inductance.

[0076] However, in the semiconductor module 200, the wiring terminal 51 cannot completely overlap with the positive terminal 40 and the negative terminal 41 in the gap G. For this reason, the inductance in the gap G cannot be reduced.

[0077] Meanwhile, the semiconductor device 1 of the embodiment includes a semiconductor module 2 and a capacitor 5. The capacitor 5 includes an insulating layer 52, a positive electrode conductive layer 53 and a negative electrode conductive layer 54 provided on one main surface and the other main surface of the insulating layer 52, respectively, and includes a wiring terminal 51 in which an insulating end side of the insulating layer 52 extends outward beyond each of the conductive end sides of the positive electrode conductive layer 53 and the negative electrode conductive layer 54.

[0078] The semiconductor module 2 includes a semiconductor chip 30 having an output electrode and an input electrode, a negative terminal 41 including a contact surface 41c1 in contact with a negative conductive layer 54 of a wiring terminal 51 and electrically connected to the output electrode of the semiconductor chip 30, and a positive terminal 40 separated from the negative terminal 41, parallel to the negative terminal 41, including a contact surface 40c1 in electrical contact with a positive conductive layer 53 of the wiring terminal 51, and electrically connected to the input electrode of the semiconductor chip 30. The semiconductor module 2 further includes a sealing body 10 in which the positive terminal 40 and the negative terminal 41 extend in the same direction from a long side surface 10a facing the wiring terminal 51 to the outside from the long side surface 10a, which fixes the semiconductor chip 30 to the positive terminal 40 and the negative terminal 41, and has a storage groove 10g between the positive terminal 40 and the negative terminal 41 on the long side surface 10a, and a tip of an insulating layer 52 of the wiring terminal 51 is inserted into the storage groove 10g. In this semiconductor device 1, the tip of the insulating layer 52 of the wiring terminal 51 of the capacitor 5 fits into the storage groove 10g in the long side surface 10a of the semiconductor module 2, thereby increasing the overlapping portion between the positive terminal 40 and the negative terminal 41 of the semiconductor module 2 and the wiring terminal 51 of the capacitor 5. This allows the inductance to be reduced more than that of the semiconductor device 100 of the reference example.

[0079] As the tip of the insulating layer 52 of the wiring terminal 51 enters deeper into the storage groove 10g of the long side surface 10a of the semiconductor module 2, the gap G in the reference example becomes smaller, and the inductance can be reduced. That is, if the tip of the insulating layer 52 of the wiring terminal 51 enters the storage groove 10g of the long side surface 10a of the semiconductor module 2 even a little and the gap G can be reduced, the inductance can be reduced. Therefore, the depth of the storage groove 10g of the long side surface 10a of the semiconductor module 2 is preferably a depth that allows the entire tip of the insulating layer 52 protruding from the positive electrode conductive layer 53 and the negative electrode conductive layer 54 of the wiring terminal 51 of the capacitor 5 to enter so that the gap G is eliminated.

[0080] (Variation 1) Modifications of the semiconductor device 1 will be described below. First, the semiconductor module 2 of Modification 1 will be described with reference to FIG. 14. FIG. 14 is a side view (ZY plane) of a semiconductor module included in the semiconductor device of the embodiment (Modification 1). In the semiconductor module 2 of Modification 1, as shown in FIG. 14, the positive electrode terminal 40 and the negative electrode terminal 41 extending from the long side surface 10a are provided facing each other in the semiconductor module 2 of the embodiment. Note that the shapes of the positive electrode terminal 40 and the negative electrode terminal 41 may be changed within the sealing body 10 of the semiconductor module 2 so that the positive electrode terminal 40 and the negative electrode terminal 41 are provided in this manner.

[0081] Next, the connection between the semiconductor module 2 and the capacitor 5 will be described with reference to Fig. 15. Fig. 15 is a cross-sectional view of a connection portion of the semiconductor device of the embodiment (variation 1). Fig. 15 corresponds to the cross-sectional view of Fig. 12 taken along dashed line XX in Figs. 1 and 2 when the semiconductor module 2 and the capacitor 5 of variation 1 are connected.

[0082] The wiring terminal 51 included in the capacitor 5 of the first modification also has an insulating layer 52 sandwiched between a positive electrode conductive layer 53 and a negative electrode conductive layer 54. The positive electrode conductive layer 53 and the negative electrode conductive layer 54 of the first modification are formed with a positive electrode fastening hole 53a and a negative electrode fastening hole 54a at positions corresponding to the positive electrode conductive layer 53 and the negative electrode conductive layer 54 of the embodiment. Moreover, the positive electrode conductive layer 53 and the negative electrode conductive layer 54 of the first modification are not formed with a negative electrode opening hole 53b and a positive electrode opening hole 54b.

[0083] The long side surfaces 10a of multiple (here, for example, three) semiconductor modules 2 are placed opposite the long side surface 50a of the capacitor 5, and the multiple semiconductor modules 2 are moved to the capacitor 5. The wiring terminals 51 of the capacitor 5 are sandwiched between the positive terminals 40 and the negative terminals 41 of the multiple semiconductor modules 2. At this time, the tip of the insulating layer 52 enters (is stored in) the storage groove 10g of the long side surface 10a of the semiconductor module 2.

[0084] 15, a bolt 55a is inserted through the fastening hole 41d of the negative terminal 41, the negative fastening hole 54a of the negative conductive layer 54, the positive fastening hole 53a of the positive conductive layer 53, and the fastening hole 40d of the positive terminal 40. The lower end of the bolt 55a is exposed from the fastening hole 40d of the positive terminal 40, and a nut 55b is fastened to the lower end.

[0085] The semiconductor device 1 including such a semiconductor module 2 and capacitor 5 can also reduce inductance, similarly to the embodiment. In the first modification, insulating members 55c, 55d, and 55e are provided between the bolt 55a and the negative electrode terminal 41, between the nut 55b and the positive electrode terminal 40, in the fastening hole 41d, the negative electrode fastening hole 54a, the positive electrode fastening hole 53a, and the fastening hole 40d. Therefore, the insulation between the negative electrode terminal 41 and the positive electrode terminal 40 is maintained.

[0086] (Variation 2) The semiconductor module 2 of the second modification will be described with reference to Fig. 16. Fig. 16 is a side view (ZY plane) of a semiconductor module included in the semiconductor device of the embodiment (second modification). In the semiconductor module 2 of the second modification, as shown in Fig. 16, the positive electrode terminal 40 and the negative electrode terminal 41 extending from the long side surface 10a in the semiconductor module 2 of the embodiment form the same plane in a side view. Note that the shapes of the positive electrode terminal 40 and the negative electrode terminal 41 may be changed within the sealing body 10 of the semiconductor module 2 so that the positive electrode terminal 40 and the negative electrode terminal 41 are provided in this manner.

[0087] Next, the connection between the semiconductor module 2 and the capacitor 5 will be described with reference to Fig. 17. Fig. 17 is a cross-sectional view of a connection portion of the semiconductor device according to the embodiment (variation 2). Fig. 17 corresponds to the cross-sectional view taken along dashed line XX in Fig. 12 when the semiconductor module 2 and the capacitor 5 according to variation 2 are connected.

[0088] The wiring terminal 51 included in the capacitor 5 of the second modification also has an insulating layer 52 sandwiched between a positive electrode conductive layer 53 and a negative electrode conductive layer 54. The positive electrode conductive layer 53 of the second modification is similar to the positive electrode conductive layer 53 of the embodiment. On the other hand, the negative electrode conductive layer 54 of the second modification is provided with a floating wiring 54d by opening a portion that contacts the positive electrode terminal 40, as compared with the negative electrode conductive layer 54 of the embodiment. The floating wiring 54d is separated from the other portion of the negative electrode conductive layer 54 and is electrically isolated. The thickness of the floating wiring 54d is the same as that of the negative electrode conductive layer 54. The floating wiring 54d has a floating fastening hole 54e formed therein. The negative electrode conductive layer 54 of the second modification does not have a positive electrode opening hole 54b formed therein.

[0089] In such a wiring terminal 51, the negative electrode fastening hole 54a of the negative electrode conductive layer 54 corresponds to the negative electrode opening hole 53b of the positive electrode conductive layer 53. Also, the floating fastening hole 54e of the floating wiring 54d included in the negative electrode conductive layer 54 corresponds to the positive electrode fastening hole 53a of the positive electrode conductive layer 53.

[0090] The long side surfaces 10a of the multiple (here, for example, three) semiconductor modules 2 are opposed to the long side surface 50a of the capacitor 5, and the multiple semiconductor modules 2 are moved to the capacitor 5. The positive electrode terminals 40 and the negative electrode terminals 41 of the multiple semiconductor modules 2 are arranged from the front side to the wiring terminals 51 of the capacitor 5. At this time, the tip of the insulating layer 52 enters (is stored in) the storage groove 10g of the long side surface 10a of the semiconductor module 2.

[0091] After the positive terminal 40 and the negative terminal 41 of the semiconductor module 2 are arranged on the wiring terminal 51 of the capacitor 5, as shown in Fig. 17, the bolt 55a is inserted through the fastening hole 41d of the negative terminal 41 and the negative fastening hole 54a of the negative conductive layer 54. The lower end of the bolt 55a is exposed from the negative opening hole 53b of the positive conductive layer 53, and a nut 55b is fastened to the lower end.

[0092] In addition, the bolt 55a is inserted through the fastening hole 40d of the positive terminal 40, the floating fastening hole 54e of the floating wire 54d, and the positive fastening hole 53a of the positive conductive layer 53. The lower end of the bolt 55a is exposed from the positive fastening hole 53a of the positive conductive layer 53, and a nut 55b is fastened to the lower end.

[0093] The semiconductor device 1 including such a semiconductor module 2 and capacitor 5 can also reduce the inductance, similarly to the embodiment. [Explanation of symbols]

[0094] 1 Semiconductor device 2, 2a, 2b, 2c Semiconductor Module 3 Semiconductor Unit 5 Capacitor 10 Sealing body 10a,10c long side 10b,10d short side 10e top 10f Bottom 10g Storage groove (recess) 20 Insulated circuit board 21 Insulating layer 21a,21c long side 21b,21d short side 22a Positive circuit pattern layer 22a1 Terminal area 22a2, 22a3 chip area 22b Negative circuit pattern layer 22b1 Terminal area 22b2,22b3 wiring area 22c Output circuit pattern layer 22c1 Terminal area 22c2,22c3 wiring area 22c4,22c5 chip area 22d, 22f Control circuit pattern layer 22e, 22g Sense circuit pattern layer 23 Metal layer 30 Semiconductor Chips 31 Control electrode 35 Joint materials 36 Control Wires 37 Sense Wire 38 Main Current Wire 40 Positive terminal 40a Positive electrode junction area 40c1 Contact surface 40d fastening hole 41 Negative terminal 41a Negative electrode junction area 41b Linkage Areas 41c wiring area 41c1 Contact surface 41d Fastening hole 42 Output terminal 42a Output junction area 43a, 43b Control terminal Ta,Tb,Tc placement area 50 Case 50a,50c long side 50b,50d short side 50e top 50f bottom 51 Wiring terminal 52 Insulating layer 53 Positive electrode conductive layer 53a Positive fastening hole 53b Negative electrode opening hole 54 Negative electrode conductive layer 54a Negative electrode fastening hole 54b Positive electrode opening hole 54d Floating wiring 54e Floating fastening hole 55a Bolt 55b Nut 55c, 55d, 55e Insulating materials

Claims

1. a wiring terminal including an insulating layer, a first conductive layer and a second conductive layer provided on one main surface and the other main surface of the insulating layer, respectively, and an insulating end side of the insulating layer extends outward beyond the conductive end sides of the first conductive layer and the second conductive layer; A semiconductor module; Equipped with The semiconductor module includes: a semiconductor chip having a first electrode and a second electrode; a first terminal including a first end having a first contact surface that contacts the first conductive layer of the wiring terminal and is electrically connected to the first electrode of the semiconductor chip; a second terminal including a second end portion spaced apart from the first end portion, parallel to the first contact surface, and having a second contact surface electrically in contact with the second conductive layer of the wiring terminal, the second terminal being electrically connected to the second electrode of the semiconductor chip; a fixing portion, the first end and the second end extending in the same direction from a base surface facing the wiring terminal to the outside from the base surface, fixing the semiconductor chip, the first terminal and the second terminal, the fixing portion having a recess between the first end and the second end of the base surface, the insulating end edge of the insulating layer of the wiring terminal being inserted into the recess; having Semiconductor device.

2. The fixing portion is a sealing member. The semiconductor device according to claim 1 .

3. The first end and the second end are flat, The first end portion and the second end portion are provided on the base surface such that a first width direction of the first end portion and a second width direction of the second end portion are parallel to each other in a plan view, The recess is parallel to the first width direction and the second width direction in a plan view. The semiconductor device according to claim 2 .

4. The recess is formed across the base surface in parallel to the first width direction and the second width direction. The semiconductor device according to claim 3 .

5. The first end portion and the second end portion are provided on the base surface so as to be offset from each other in the first width direction and the second width direction in a plan view. The semiconductor device according to claim 4.

6. the conductive end sides of the first conductive layer and the second conductive layer of the wiring terminal are in contact with the base surface of the semiconductor module; The semiconductor device according to claim 1 .

7. Further comprising a capacitor including the wiring terminal. The semiconductor device according to claim 1 .

8. a first semiconductor chip having a first electrode and a second electrode; a second semiconductor chip having a third electrode and a fourth electrode electrically connected to the first electrode of the first semiconductor chip; a first terminal including a first end having a first contact surface, the first terminal being electrically connected to the first electrode of the first semiconductor chip; a second terminal including a second end portion spaced apart from the first end portion and having a second contact surface parallel to the first contact surface, the second terminal being electrically connected to the fourth electrode of the second semiconductor chip; a fixing portion, the first end portion and the second end portion extending outward from the base surface in the same direction from the base surface, fixing the first semiconductor chip, the second semiconductor chip, the first terminal, and the second terminal, and having a recess between the first end portion and the second end portion on the base surface; A semiconductor module having the following:

Images