Insulation chip and signal transmission device

Abstract

To provide an insulation chip containing an improved connection wiring.SOLUTION: A first connection wiring 60A contains: a first layer wiring 62A that is arranged in an insulation body 84, and is close to an insulation lower surface 84r; a second layer wiring 63A that is arranged in the insulation body 84, is close to an insulation upper surface 84s, and is opposite to the first layer wiring 62A in a Z direction; and a penetration wiring 64A that electrically connects the first layer wiring 62A and the second layer wiring 63A. The insulation body 84 is formed between the first layer wiring 62A and the second layer wiring 63A in the Z direction, and contains a penetration hole 71A penetrating two or more insulation layers 85 of a plurality of insulation layers 85. The penetration wiring 64A is arranged in the penetration hole 71A. The penetration hole 71A has a circular shape in view of the Z direction.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to insulating tips and signal transmission devices. [Background technology]

[0002] Conventionally, signal transmission devices that transmit pulse signals while isolating input and output have been used in various applications such as power supplies and motor drive devices. As an example of a signal transmission device, an insulated gate driver that applies a gate voltage to the gate of a switching element such as a transistor is known. As an example of an insulating chip used in such a gate driver, a structure including a coil formed in an insulating layer stack structure is known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-78169 A

[0004] [overview] However, in an insulating chip used in a signal transmission device, a low-voltage pad formed on an insulating layer stack is connected to the insulating layer stack by a low-voltage wiring in the insulating layer stack. There is room for improvement in the low-voltage wiring.

[0005] an insulating chip according to one embodiment of the present disclosure, comprising: an insulator including an insulating lower surface and an insulating upper surface facing opposite each other in a thickness direction, the insulator being composed of a plurality of insulating layers stacked in the thickness direction; a first conductor disposed within the insulator and closer to the insulating lower surface; a second conductor disposed within the insulator and closer to the insulating upper surface and facing the first conductor in the thickness direction; a first electrode pad provided on the insulating upper surface; and a connection wiring electrically connecting the first conductor and the first electrode pad, the connection wiring including a first layer wiring disposed within the insulator and closer to the insulating lower surface; a second layer wiring disposed within the insulator and closer to the insulating upper surface and facing the first layer wiring in the thickness direction; and a through wiring electrically connecting the first layer wiring and the second layer wiring, the insulator including a through hole formed between the first layer wiring and the second layer wiring in the thickness direction and penetrating two or more of the plurality of insulating layers, the through wiring being disposed in the through hole, the through hole being circular when viewed from the thickness direction.

[0006] A signal transmission device according to one aspect of the present disclosure includes an insulating chip, a first die pad on which the insulating chip is mounted, and a sealing resin that seals the insulating chip and the first die pad. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a circuit diagram illustrating an example of the configuration of a signal transmission device. [Diagram 2] FIG. 2 is a schematic plan view showing the configuration of the signal transmission device of FIG. [Diagram 3] FIG. 3 is a schematic cross-sectional view showing the configuration of the signal transmission device of FIG. [Figure 4] FIG. 4 is a schematic perspective view showing the insulating tip of the first embodiment. [Diagram 5] FIG. 5 is a schematic plan view of the insulating chip of FIG. [Figure 6] FIG. 6 is a schematic plan view showing a first coil of the insulating chip of FIG. [Figure 7] FIG. 7 is a schematic plan view showing a second coil of the insulating chip of FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view of the insulating chip taken along line 8-8 in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of the insulating chip taken along line 9-9 in FIG. [Figure 10] FIG. 10 is a schematic plan view showing the first layer wiring and the through wiring of the connection wiring of FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing, in an enlarged scale, a part of the connection wiring taken along line 11-11 in FIG. [Figure 12] 12A to 12C are schematic cross-sectional views for explaining the manufacturing process of the connection wiring of FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 23] 23A to 23C are schematic cross-sectional views showing a process of forming a conductive layer for forming the through wiring of FIG. [Figure 24]24A to 24C are schematic cross-sectional views showing a process of forming a conductive layer for forming the through wiring of FIG. [Diagram 25] FIG. 25 is a schematic plan view showing a process of forming a conductive layer for forming the through wiring in FIG. [Figure 26] FIG. 26 is a schematic plan view showing a process of forming a conductive layer for forming the through wiring in FIG. [Figure 27] FIG. 27 is a schematic plan view showing a process of forming a conductive layer for forming the through wiring of FIG. [Figure 28] FIG. 28 is a schematic plan view showing a configuration of a connection wiring of a comparative example. [Figure 29] FIG. 29 is a schematic cross-sectional view showing an enlarged portion of the connection wiring of FIG. [Diagram 30] FIG. 30 is a schematic cross-sectional view showing a process of forming a conductive layer for forming the through wiring of the comparative example of FIG. [Diagram 31] FIG. 31 is a schematic cross-sectional view showing a process of forming a conductive layer for forming a through wiring of the comparative example of FIG. [Diagram 32] FIG. 32 is a schematic plan view showing a process of forming a conductive layer for forming the through wiring of the comparative example of FIG. [Diagram 33] FIG. 33 is a schematic plan view showing a process of forming a conductive layer for forming the through wiring of the comparative example of FIG. [Diagram 34] FIG. 34 is a schematic plan view showing a process of forming a conductive layer for forming the through wiring of the comparative example of FIG. [Diagram 35] FIG. 35 is a schematic cross-sectional view illustrating an insulating tip according to the second embodiment. [Diagram 36] FIG. 36 is a schematic plan view showing the first layer wiring and the through wiring of the connection wiring in FIG. [Figure 37] FIG. 37 is a schematic cross-sectional view showing the connection wiring taken along line 37-37 in FIG. [Figure 38] FIG. 38 is a schematic cross-sectional view for explaining a manufacturing process of the connection wiring of FIG. [Figure 39] FIG. 39 is a schematic cross-sectional view showing a manufacturing process following FIG. [Diagram 40] FIG. 40 is a schematic cross-sectional view showing a manufacturing process following FIG. [Diagram 41] FIG. 41 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Diagram 42] FIG. 42 is a schematic cross-sectional view showing a manufacturing process following FIG. [Diagram 43] FIG. 43 is a schematic cross-sectional view showing a manufacturing process following FIG. [Diagram 44] FIG. 44 is a schematic cross-sectional view illustrating an insulating tip according to the third embodiment. [Diagram 45] FIG. 45 is a schematic plan view showing the first layer wiring and the through wiring of the connection wiring in FIG. [Figure 46] 46A to 46C are schematic cross-sectional views for explaining the manufacturing process of the connection wiring of FIG. [Figure 47] FIG. 47 is a schematic cross-sectional view showing a manufacturing process following FIG. [Figure 48] FIG. 48 is a schematic cross-sectional view showing a manufacturing process following FIG. [Figure 49] FIG. 49 is a schematic cross-sectional view showing a manufacturing process following FIG. [Figure 50] FIG. 50 is a schematic cross-sectional view showing a manufacturing process following FIG. [Figure 51] FIG. 51 is a circuit diagram illustrating an example of the configuration of a signal transmission device. [Figure 52] FIG. 52 is a schematic cross-sectional view showing the configuration of the insulating chip of the fourth embodiment. [Diagram 53] FIG. 53 is a schematic cross-sectional view showing a configuration of an insulating tip according to a modified example. [Figure 54] FIG. 54 is a schematic cross-sectional view showing a configuration of an insulating tip according to a modified example. [Figure 55] FIG. 55 is a schematic cross-sectional view showing a configuration of a signal transmission device according to a modified example.

[0008] [Detailed Description] Hereinafter, some embodiments of the insulating chip and the signal transmission device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Also, hatching lines may be omitted in cross-sectional views to facilitate understanding. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure. Terms such as "first", "second", and "third" in the present disclosure are used merely to distinguish objects and do not rank the objects.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] (Outline of signal transmission device) The schematic configuration of a signal transmission device 10 will be described with reference to FIGS. Fig. 1 shows a schematic example of a circuit configuration of a signal transmission device 10. Fig. 2 shows a schematic example of a planar structure of the internal configuration of the signal transmission device 10. Fig. 3 shows a schematic example of a cross-sectional structure of a portion of the internal configuration of the signal transmission device 10. For convenience, hatched lines are omitted in Fig. 3.

[0011] 1, the signal transmission device 10 includes a plurality of first terminals 11 and a plurality of second terminals 12. The plurality of first terminals 11 and the plurality of second terminals 12 are external terminals of the signal transmission device 10. The plurality of first terminals 11 and the second terminals 12 are used as input / output terminals (input terminals, output terminals) of signals in the signal transmission device 10, power supply terminals for supplying driving power, ground terminals, and the like. The signal transmission device 10 is a device that transmits signals while electrically insulating the first terminal 11 and the second terminal 12 used as the input terminal and the output terminal. The signal transmission device 10 is, for example, a digital isolator.

[0012] The signal transmission device 10 includes a first circuit 20 electrically connected to a first terminal 11, a second circuit 30 electrically connected to a second terminal 12, and a transformer 40 connected between the first circuit 20 and the second circuit 30.

[0013] The first circuit 20 is a circuit configured to operate when a first voltage V1 is applied. The first circuit 20 is electrically connected to, for example, an external control device (not shown). The second circuit 30 is a circuit configured to operate when a second voltage V2 is applied. In one example, the second voltage V2 may be a voltage different from the first voltage V1. In one example, the second voltage V2 may be a voltage higher than the first voltage V1. Note that the second voltage V2 may be a voltage lower than the first voltage V1. Also, the second voltage V2 may be equal to the first voltage V1. The first voltage V1 and the second voltage V2 are DC voltages. The second circuit 30 is electrically connected to, for example, a drive circuit that is to be controlled by the control device. An example of the drive circuit is a switching circuit. Note that the second circuit 30 may include a drive circuit.

[0014] The ground of the second circuit 30 and the ground of the first circuit 20 are provided independently. In one example, the potentials of the grounds of the first circuit 20 and the second circuit 30 may be set as reference potentials. For example, the potential of the ground GND1 of the first circuit 20 may be set as a first reference potential, and the potential of the ground GND2 of the first circuit 20 may be set as a second reference potential. The first voltage V1 is a voltage from the first reference potential, and the second voltage V2 is a voltage from the second reference potential.

[0015] 1 shows a configuration in which two signals are output from the first circuit 20 to the second circuit 30. The transformer 40 includes two transformers 40A and 40B corresponding to the two signals.

[0016] The transformers 40A and 40B include a first coil 41 and a second coil 42. The first coil 41 and the second coil 42 are electrically insulated from each other and configured to be magnetically coupled. Therefore, it can be said that the first circuit 20 and the second circuit 30 are electrically insulated from each other. Moreover, it can be said that the first circuit 20 and the second circuit 30 are connected so as to be capable of transmitting signals due to the magnetic coupling between the first coil 41 and the second coil 42 of the transformers 40A and 40B.

[0017] The first coil 41 is connected to the first circuit 20. The second coil 42 is connected to the second circuit 30. In one example, the first circuit 20 receives a control signal from, for example, a control device through the first terminal 11. The first circuit 20 outputs a transmission signal corresponding to the control signal. The transmission signal is received by the second circuit 30 via transformers 40A and 40B. The second circuit 30 outputs a signal corresponding to the received signal, for example a gate drive signal, to the drive circuit. Note that the second circuit 30 may be configured to output a signal, and the first circuit 20 may be configured to receive a signal. Also, the first circuit 20 and the second circuit 30 may be configured to transmit signals to each other and receive signals.

[0018] As described above, in the signal transmission device 10, the first circuit 20 and the second circuit 30 are electrically insulated by the transformer 40. More specifically, the transformer 40 regulates the transmission of DC voltage between the first circuit 20 and the second circuit 30. Furthermore, the transformer 40 allows the transmission of a pulse signal between the first circuit 20 and the second circuit 30. The transformer 40 is an insulating element that electrically insulates the second circuit 30 from the first circuit 20 and transmits a signal between the second circuit 30 and the first circuit 20.

[0019] That is, the state in which the first circuit 20 and the second circuit 30 are insulated means a state in which the transmission of DC voltage between the first circuit 20 and the second circuit 30 is blocked, while the transmission of a pulse signal from the first circuit 20 to the second circuit 30 is permitted. In this manner, the second circuit 30 is configured to receive a signal from the first circuit 20.

[0020] The first circuit 20 and the second circuit 30 can also be referred to as a primary circuit and a secondary circuit with respect to the transformer 40. In one example, the second circuit 30 is a secondary circuit and the first circuit 20 is a primary circuit. The second circuit 30 may be a primary circuit and the first circuit 20 may be a secondary circuit. Furthermore, each of the second circuit 30 and the first circuit 20 may include a primary circuit and a secondary circuit.

[0021] FIG. 2 shows an example of the internal configuration of the signal transmission device 10. Note that FIG. 1 shows a simplified circuit configuration of the signal transmission device 10. Therefore, the number of external terminals of the signal transmission device 10 in FIG. 2 is greater than the number of external terminals of the signal transmission device 10 in FIG. 1. Here, the external terminals of the signal transmission device 10 include a connection terminal to which an external electronic component of the signal transmission device 10 can be connected, and a power supply terminal to supply a power supply voltage to the first circuit chip 160 and the second circuit chip 170 of the signal transmission device 10. Note that terminals that are not connected to the outside may be included as external terminals. FIG. 3 shows an example of a cross-sectional view showing the internal configuration of the signal transmission device 10. Note that FIG. 3 is a cross-sectional view showing the internal configuration of the signal transmission device 10 in a simplified manner. The cross-sectional structures of the first and second circuit chips and the insulating chip 80 are shown in a simplified manner. Therefore, the cross-sectional structure of the insulating chip 80 shown in FIG. 3 is different from the cross-sectional structure of the insulating chip 80 described later.

[0022] 2 and 3, the signal transmission device 10 is, in one example, a semiconductor device in which first and second circuit chips 160, 170 and an insulating chip 80 are packaged. The insulating chip 80 includes the transformers 40A, 40B shown in FIG. 1. In one example, the first circuit chip 160 may include the first circuit 20 shown in FIG. 1. In one example, the second circuit chip 170 may include the second circuit 30. The signal transmission device 10 may include chips other than the first and second circuit chips 160, 170 and the insulating chip 80.

[0023] The package format of the signal transmission device 10 is a small outline (SO) type, and is, for example, a small outline package (SOP). The package format of the signal transmission device 10 can be changed as desired. The package format is not limited to SOP, and may be a quad for non-lead package (QFN), dual flat package (DFP), dual inline package (DIP), quad flat package (QFP), single inline package (SIP), or small outline J-leaded package (SOJ), or various package structures similar to these.

[0024] The first circuit chip 160 is mounted on the first support member 110. The second circuit chip 170 is mounted on the second support member 120. In one example, the insulating chip 80 is mounted on the first support member 110. The sealing resin 130 seals the first support member 110 and a part of the second support member 120, the first and second circuit chips 160, 170, and the insulating chip 80. In addition, in FIG. 2, the sealing resin 130 is indicated by a two-dot chain line for the convenience of explaining the internal structure of the signal transmission device 10.

[0025] The sealing resin 130 is made of a material having electrical insulation properties. This resin is, for example, a resin containing epoxy resin. This resin may be colored black or the like. The sealing resin 130 is formed in a rectangular plate shape with the Z direction as the thickness direction. The sealing resin 130 includes four resin side surfaces 131 to 134. More specifically, the sealing resin 130 includes resin side surfaces 131 and 132 as both end faces in the X direction and resin side surfaces 133 and 134 as both end faces in the Y direction. The X direction and the Y direction are directions perpendicular to the Z direction. The X direction and the Y direction are perpendicular to each other. The X direction corresponds to the "first direction". The Y direction corresponds to the "second direction". In the following description, a plan view means a view from the Z direction.

[0026] The first support member 110 and the second support member 120 are each electrically conductive. The first support member 110 and the second support member 120 are made of a material containing Cu (copper), Fe (iron), etc. Each of the support members 110, 120 is provided across the inside and outside of the sealing resin 130.

[0027] The first support member 110 includes a first die pad 111 disposed in the sealing resin 130, and a plurality of first lead terminals 112 disposed across the inside and outside of the sealing resin 130. Both the first circuit chip 160 and the insulating chip 80 are mounted on the first die pad 111. In a plan view, the first die pad 111 is disposed such that its center in the Y direction is closer to the resin side surface 133 than the center in the Y direction of the sealing resin 130. The first die pad 111 is not exposed from the sealing resin 130. In a plan view, the shape of the first die pad 111 is rectangular with its long side direction in the X direction and its short side direction in the Y direction.

[0028] The multiple first lead terminals 112 are arranged spaced apart from each other in the X direction. Of the multiple first lead terminals 112, first lead terminals 112A arranged at both ends in the X direction are each integrated with the first die pad 111. A portion of each first lead terminal 112 protrudes from the resin side surface 133 toward the outside of the sealing resin 130.

[0029] The second support member 120 includes a second die pad 121 disposed in the sealing resin 130, and a plurality of second lead terminals 122 disposed across the inside and outside of the sealing resin 130. A second circuit chip 170 is mounted on the second die pad 121. In a plan view, the second die pad 121 is disposed closer to the resin side surface 134 in the Y direction than the first die pad 111. The second die pad 121 is not exposed from the sealing resin 130. In a plan view, the shape of the second die pad 121 is a rectangle whose long side direction is in the X direction and whose short side direction is in the Y direction.

[0030] The first die pad 111 and the second die pad 121 are arranged to be spaced apart from each other in the Y direction. Therefore, the Y direction can also be said to be the arrangement direction of both die pads 111, 121. The dimensions in the Y direction of first die pad 111 and second die pad 121 are set depending on the size and number of semiconductor chips to be mounted. First circuit chip 160 and insulating chip 80 are mounted on first die pad 111, and second circuit chip 170 is mounted on second die pad 121. For this reason, the dimension in the Y direction of first die pad 111 is larger than the dimension in the Y direction of second die pad 121.

[0031] The multiple second lead terminals 122 are arranged spaced apart from each other in the X direction. Two second lead terminals 122A of the multiple second lead terminals 122 are integrated with the second die pad 121. A portion of each second lead terminal 122 protrudes outward from the resin side surface 134 of the sealing resin 130.

[0032] The number of second lead terminals 122 is the same as the number of first lead terminals 112. As can be seen from Fig. 2, the multiple first lead terminals 112 and the multiple second lead terminals 122 are arranged in a direction (X direction) perpendicular to the arrangement direction (Y direction) of the first die pad 111 and the second die pad 121. Note that the number of second lead terminals 122 and the number of first lead terminals 112 can each be changed arbitrarily.

[0033] The first support member 110 and the second support member 120 are formed from a lead frame. In the manufacturing process of the signal transmission device 10, the first die pad 111, the multiple first lead terminals 112, the second die pad 121, and the multiple second lead terminals 122 are formed from the same lead frame.

[0034] The lead frame includes an outer frame formed to surround the first support member 110 and the second support member 120. The first lead terminal 112 and the second lead terminal 122 are connected to the outer frame. During the manufacturing process of the signal transmission device 10, the first lead terminal 112 and the second lead terminal 122 are cut off from the outer frame.

[0035] The first die pad 111 is connected to two first lead terminals 112A of the multiple first lead terminals 112. The first die pad 111 and the first lead terminal 112A are integrated into one body. The first die pad 111 is supported by the first lead terminal 112A. The second die pad 121 is connected to two second lead terminals 122A of the multiple second lead terminals 122. The second die pad 121 and the second lead terminal 122A are integrated into one body. The second die pad 121 is supported by the second lead terminal 122A. Therefore, the die pads 111 and 121 are not provided with hanging leads exposed from the resin side surfaces 131 and 132. Therefore, the insulation distance (creepage distance) between the first support member 110 and the second support member 120 can be made large.

[0036] The first die pad 111 may be supported by one first lead terminal 112A. In this case, the other first lead terminal 112 can be assigned to a signal input / output terminal or the like. Similarly, the second die pad 121 may be supported by one second lead terminal 122A. In this case, the other second lead terminal 122 can be assigned to a signal input / output terminal or the like.

[0037] The first circuit chip 160, the second circuit chip 170, and the insulating chip 80 are arranged at a distance from one another in the Y direction. The first circuit chip 160, the insulating chip 80, and the second circuit chip 170 are arranged in this order from the first lead terminal 112 to the second lead terminal 122 in the Y direction.

[0038] The first circuit chip 160 is rectangular in shape having short and long sides in a plan view and is mounted on the first die pad 111 with the long sides aligned in the X direction and the short sides aligned in the Y direction in a plan view.

[0039] 3, the first circuit chip 160 includes a chip main surface 160s and a chip back surface 160r that face opposite each other in the Z direction. The chip back surface 160r of the first circuit chip 160 is bonded to the first die pad 111 by a conductive bonding material SD. The conductive bonding material SD may be solder, Ag (silver) paste, or the like.

[0040] 2, a plurality of first electrode pads 161, a plurality of second electrode pads 162, and a plurality of third electrode pads 163 are formed on a chip main surface 160s of the first circuit chip 160. The first electrode pads 161, the second electrode pads 162, and the third electrode pads 163 are electrically connected to the first circuit 20.

[0041] The multiple first electrode pads 161 are arranged on the chip main surface 160s closer to the first lead terminal 112 than the center of the chip main surface 160s in the Y direction. The multiple first electrode pads 161 are arranged in the X direction. The multiple second electrode pads 162 are arranged on both ends of the chip main surface 160s in the X direction. The multiple third electrode pads 163 are arranged on the end closer to the insulating chip 80 of both ends of the chip main surface 160s in the Y direction. The multiple third electrode pads 163 are arranged in the X direction.

[0042] The second circuit chip 170 is rectangular in shape having short and long sides in a plan view and is mounted on the second die pad 121 with the long sides aligned in the X direction and the short sides aligned in the Y direction in a plan view.

[0043] 3, the second circuit chip 170 includes a chip main surface 170s and a chip back surface 170r that face opposite to each other in the Z direction. The chip back surface 170r of the second circuit chip 170 is bonded to the second die pad 121 by a conductive bonding material SD.

[0044] A plurality of first electrode pads 171, a plurality of second electrode pads 172, and a plurality of third electrode pads 173 are formed on a chip main surface 170s of the second circuit chip 170. The first electrode pads 171, the second electrode pads 172, and the third electrode pads 173 are electrically connected to the second circuit 30.

[0045] The first electrode pads 171 are arranged at the end farther from the insulating chip 80 among both ends in the Y direction of the chip main surface 170s. That is, the first electrode pads 171 are arranged at the end closer to the second lead terminal 122 among both ends in the Y direction of the chip main surface 170s. The first electrode pads 171 are arranged in the X direction. The second electrode pads 172 are arranged at both ends in the X direction of the chip main surface 170s. The third electrode pads 173 are arranged at the end closer to the insulating chip 80 among both ends in the Y direction of the chip main surface 170s. The third electrode pads 173 are arranged in the X direction.

[0046] The insulating chip 80 is mounted on the first die pad 111 with its long side aligned in the X direction and its short side aligned in the Y direction in plan view.

[0047] The insulating chip 80 is disposed adjacent to the first circuit chip 160 in the Y direction. The insulating chip 80 is disposed closer to the second circuit chip 170 than the first circuit chip 160. In other words, the insulating chip 80 is disposed between the first circuit chip 160 and the second circuit chip 170 in the Y direction.

[0048] 3, the insulating chip 80 includes a chip main surface 80s and a chip back surface 80r that face opposite each other in the Z direction. The chip back surface 80r of the insulating chip 80 is bonded to the first die pad 111 by a conductive bonding material SD.

[0049] 2, the insulating chip 80 includes a plurality of first electrode pads 81 and a plurality of second electrode pads 82. The first electrode pads 81 and the plurality of second electrode pads 82 are provided on a chip main surface 80s of the insulating chip 80. The plurality of first electrode pads 81 are arranged at one of both ends in the Y direction of the insulating chip 80 that is closer to the first circuit chip 160. The plurality of first electrode pads 81 are arranged in the X direction. The plurality of second electrode pads 82 are arranged near the center of the insulating chip 80 in the Y direction. The plurality of second electrode pads 82 are arranged in the X direction.

[0050] 2, in order to set the dielectric strength voltage of the signal transmission device 10 to a preset dielectric strength voltage, the first die pad 111 and the second die pad 121, which are closest to the support members 110, 120, need to be spaced apart from each other. For this reason, the distance between the second circuit chip 170 and the insulating chip 80 is greater than the distance between the first circuit chip 160 and the insulating chip 80 in a plan view.

[0051] A plurality of wires W1 to W4 are connected to each of the first circuit chip 160, the insulating chip 80, and the second circuit chip 170. Each of the wires W1 to W4 is a bonding wire formed by a wire bonding device, and is made of a conductor containing, for example, Au (gold), Al (aluminum), Cu, or the like.

[0052] The first circuit chip 160 is electrically connected to the first lead terminal 112 by the wire W1. More specifically, the first electrode pads 161 and the second electrode pads 162 of the first circuit chip 160 are connected to the first lead terminals 112 by the wire W1. The second electrode pads 162 of the first circuit chip 160 are connected to the first lead terminal 112A of the first lead terminals 112, which is integrated with the first die pad 111, by the wire W1. This electrically connects the first circuit 20 to the first lead terminals 112. The first lead terminal 112A integrated with the first die pad 111 constitutes a ground terminal, and the first circuit 20 and the first die pad 111 are electrically connected by the wire W1. For this reason, the first ground GND1 of the first circuit 20 shown in FIG. 1 has the same potential as the first die pad 111.

[0053] The second circuit chip 170 and the second lead terminals 122 of the second support member 120 are electrically connected to each other by wires W4. More specifically, the first electrode pads 171 and the second electrode pads 172 of the second circuit chip 170 are connected to the second lead terminals 122 by wires W4. This electrically connects the second circuit 30 to the second lead terminals 122. The second lead terminal 122A integrated with the second die pad 121 constitutes a ground terminal, and the second circuit 30 and the second die pad 121 are electrically connected to each other by wires W4. Therefore, the second ground GND2 of the second circuit 30 shown in FIG. 1 has the same potential as the second die pad 121.

[0054] The insulating chip 80 is connected to the first circuit chip 160 by wires W2. The insulating chip 80 is also connected to the second circuit chip 170 by wires W3. More specifically, the first electrode pads 81 of the insulating chip 80 are connected to the third electrode pads 163 of the first circuit chip 160 by wires W2. The second electrode pads 82 of the insulating chip 80 are connected to the third electrode pads 173 of the second circuit chip 170 by wires W3.

[0055] Both of the first coils 41 of the transformers 40A, 40B (see FIG. 1) are electrically connected to a first ground GND1 of the first circuit chip 160 by a wire W2. The second coils 42 of the transformers 40A, 40B (see FIG. 1) are electrically connected to a second ground GND2 of the second circuit chip 170 by a wire W3.

[0056] The configuration of the signal transmission device 10 shown in FIG. 1 is an example, and the circuit configurations included in the first circuit chip 160 and the second circuit chip 170 may be changed as appropriate. In one example, the first circuit 20 may include an analog-digital conversion circuit. In this case, the signal transmission device 10 is configured as an insulated A / D conversion device. In one example, the second circuit 30 may include a driver circuit that drives the gate of the switching element. The driver circuit may be connected to a terminal of the signal transmission device 10. In one example, the driver circuit may be connected to a second lead terminal 122 shown in FIG. 2. In this case, the signal transmission device 10 is configured as an insulated gate driver that drives the switching element. The switching element may be a power semiconductor element such as a Si Metal-Oxide-Semiconductor Field-Effect Transistor (SiMOSFET), a SiCMOSFET, or an IGBT (Insulated Gate Bipolar Transistor). The switching element is used in a motor driver circuit in an inverter device. The driver circuit generally uses a half-bridge circuit in which a low-side switching element and a high-side switching element are connected in a totem pole configuration.

[0057] The signal transmission device 10 used as an insulated gate driver applies a drive voltage signal to the control terminal of a switching element. In this case, the first circuit 20 converts a control signal input from, for example, a control device into a pulse signal. The driver circuit of the second circuit 30 outputs a drive voltage signal to the control terminal of the switching element based on a signal received through transformers 40A and 40B. The first circuit 20 and the second circuit 30 may be used to transmit a detection signal of, for example, a temperature sensor arranged near a motor to the control device.

[0058] In this way, the first circuit 20 of the signal transmission device 10 used as an insulated gate driver receives a signal from the control device, and the first voltage V1 of the first circuit 20 is 5V, 3.3V, etc., with respect to the ground potential. On the other hand, in the case of the second circuit 30 connected to the high-side switching element, a voltage equivalent to the voltage applied to the drain of the high-side switching element (for example, 600V or more) is transiently applied. For this reason, the signal transmission device 10 is required to have a withstand voltage between the first circuit 20 and the second circuit 30, specifically, between the first coil 41 and the second coil 42 of the transformers 40A and 40B. The required withstand voltage of the signal transmission device 10 is 2500Vrms or more and 7500Vrms or less. In one example, the withstand voltage of the signal transmission device 10 is about 5000Vrms. However, the specific value of the withstand voltage of the signal transmission device 10 is not limited to this and is arbitrary.

[0059] (Insulation chip configuration) The configuration of the insulating tip 80 of the first embodiment will be described with reference to FIGS. In the following description, the direction from the chip back surface 80r to the chip main surface 80s of the insulating chip 80 shown in FIGS. 8 and 9 is referred to as "upward," and the direction from the chip main surface 80s to the chip back surface 80r is referred to as "downward."

[0060] Fig. 4 is a perspective view showing the appearance of the insulating chip 80. Fig. 5 is a plan view of the insulating chip 80. For ease of explanation, the transformers 40A and 40B and the dummy pattern 55 are indicated by dashed lines in Fig. 5. Also, in Fig. 5, the first electrode pad 81 and the second electrode pad 82 are indicated by two-dot chain lines, and the resin openings of the resin layer 92 are indicated by solid lines.

[0061] Fig. 6 is a cross-sectional view of the insulating chip 80 taken along the xy plane at a position in the Z direction where the first coil 41 is disposed, and shows the connection relationship of the first coil 41. Fig. 7 is a cross-sectional view of the insulating chip 80 taken along the xy plane at a position in the Z direction where the second coil 42 is disposed, and shows the connection relationship of the second coil 42. For convenience, hatching is omitted in Figs. 6 and 7.

[0062] Fig. 8 is a cross-sectional view of the insulating chip 80 taken along line 8-8 in Fig. 5. Fig. 8 shows the cross-sectional structures of the insulator 84, the first coil 41, the second coil 42, the dummy pattern 55, the first electrode pad 81 (first pad 81A), the second electrode pad 82 (third pad 82A), and the first connection wiring 60A. Fig. 9 is a cross-sectional view of the insulating chip 80 taken along line 9-9 in Fig. 5. Fig. 9 shows the cross-sectional structures of the insulator 84, the dummy pattern 55, the first electrode pad 81 (second pad 81B), the second electrode pad 82 (fourth pad 82B), and the second connection wiring 60B.

[0063] 5, the insulating chip 80 includes two pairs of transformers 40A, 40B. More specifically, the insulating chip 80 is a semiconductor chip in which the two pairs of transformers 40A, 40B are integrated into a single chip. In other words, the insulating chip 80 is provided as a semiconductor chip different from the first circuit chip 160 and the second circuit chip 170 shown in FIG.

[0064] The transformers 40A and 40B are disposed near the center of the chip main surface 80s in the Y direction in a plan view. In one example, the first electrode pads 81 and the transformers 40A and 40B are disposed at positions not overlapping with each other in a plan view. The first electrode pads 81 and the second electrode pads 82 are electrically connected to the transformers 40A and 40B.

[0065] Each pair of transformers 40A, 40B has the same configuration. Furthermore, the transformer 40B has the same configuration as the transformer 40A. Therefore, the detailed structure of the transformer 40A will be described, and a description of the transformer 40B will be omitted.

[0066] As shown in FIG. 4 and FIG. 5, the insulating chip 80 has four chip side surfaces 801, 802, 803, and 804 that are perpendicular to both the chip main surface 80s and the chip back surface 80r. The chip side surfaces 801, 802, 803, and 804 are provided between the chip main surface 80s and the chip back surface 80r in the Z direction. The chip side surfaces 801 and 802 constitute both end faces of the insulating chip 80 in the Y direction, and the chip side surfaces 803 and 804 constitute both end faces of the insulating chip 80 in the X direction. In a plan view, the chip side surfaces 801 and 802 constitute the long sides of the insulating chip 80, and the chip side surfaces 803 and 804 constitute the short sides of the insulating chip 80. As shown in FIG. 2, the chip side surface 801 is closer to the second circuit chip 170 than the chip side surface 802, and the chip side surface 802 is closer to the first circuit chip 160 than the chip side surface 801.

[0067] As shown in FIGS. 4, 8 and 9, the insulating chip 80 includes a substrate 83 and an insulator 84 . The substrate 83 is, for example, a semiconductor substrate. The substrate 83 is a substrate formed from a material containing Si (silicon). Examples of the Si substrate used for the substrate 83 include a semiconductor substrate made of a single crystal intrinsic semiconductor material, a P-type semiconductor substrate containing an acceptor-type impurity, and an n-type semiconductor substrate containing a donor-type impurity.

[0068] The substrate 83 may be a semiconductor substrate made of a wide bandgap semiconductor or a compound semiconductor. Alternatively, the substrate 83 may be an insulating substrate made of a material containing glass, instead of a semiconductor substrate. The wide bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or more. Examples of wide bandgap semiconductors include SiC (silicon carbide), GaN (gallium nitride), Ga 2 O 3 The compound semiconductor may be a III-V group compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN, and GaAs (gallium arsenide).

[0069] The substrate 83 includes a substrate upper surface 83s and a substrate lower surface 83r that face opposite each other in the Z direction. The substrate lower surface 83r constitutes the chip back surface 80r of the insulating chip 80. The substrate 83 is formed in a quadrangular shape when viewed from the Z direction. In one example, the substrate 83 is formed in a rectangular shape when viewed from the Z direction.

[0070] 8 and 9, the insulator 84 is formed on a substrate upper surface 83s of the substrate 83. The insulator 84 includes an insulating upper surface 84s and an insulating lower surface 84r that face opposite each other in the Z direction. The insulating upper surface 84s of the insulator 84 faces the same direction as the substrate upper surface 83s of the substrate 83. The insulating lower surface 84r of the insulator 84 is in contact with the substrate upper surface 83s of the substrate 83.

[0071] The insulator 84 includes a plurality of insulating layers 85 arranged from the substrate upper surface 83s of the substrate 83 toward the Z direction. The plurality of insulating layers 85 are stacked on the substrate upper surface 83s of the substrate 83. It can be said that the insulator 84 includes a plurality of insulating layers 85 stacked in the Z direction from the substrate upper surface 83s. The Z direction can also be said to be the thickness direction of the insulator 84. The Z direction can also be said to be the stacking direction of the insulating layers 85.

[0072] The multiple insulating layers 85 include a lowermost insulating layer 85L, an uppermost insulating layer 85U, and multiple insulating layers 851-857 disposed between the lowermost insulating layer 85L and the uppermost insulating layer 85U.

[0073] The multiple insulating layers 85 include a first insulating layer 85A and a second insulating layer 85B formed on the first insulating layer 85A. The first insulating layer 85A is a thin film, and is, for example, an etching stopper layer. The first insulating layer 85A is formed of a material containing SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), or the like. The first insulating layer 85A is formed of a material containing SiN. The second insulating layer 85B is, for example, an interlayer insulating film. The second insulating layer 85B is, for example, a SiO 2 The second insulating layer 85B is formed of a material containing silicon oxide. The thickness of the second insulating layer 85B is thicker than the thickness of the first insulating layer 85A. The thickness of the first insulating layer 85A may be 100 nm or more and less than 1000 nm. The thickness of the second insulating layer 85B may be 1000 nm or more and 3000 nm or less. In one example, the thickness of the first insulating layer 85A is about 300 nm, and the thickness of the second insulating layer 85B is about 2300 nm.

[0074] The lower surface of the bottom insulating layer 85L constitutes the insulating lower surface 84r of the insulator 84. The upper surface of the top insulating layer 85U constitutes the insulating upper surface 84s. Both the bottom insulating layer 85L and the top insulating layer 85U, which are in contact with the substrate upper surface 83s of the substrate 83, are constituted by the second insulating layer 85B. In one example, the thicknesses of both the bottom insulating layer 85L and the top insulating layer 85U are thinner than the other insulating layers 85. The thicknesses of both the bottom insulating layer 85L and the top insulating layer 85U may be equal to or greater than the thickness of the first insulating layer 85A and equal to or less than the thickness of the second insulating layer 85B. The thicknesses of both the bottom insulating layer 85L and the top insulating layer 85U can be changed arbitrarily. In one example, the thickness of both the bottommost insulating layer 85L and the topmost insulating layer 85U may be thicker than the thickness of the second insulating layer 85B, and may be greater than or equal to the thickness of the insulating layer 85 formed by the first insulating layer 85A and the second insulating layer 85B.

[0075] (First conductor, second conductor) 6 to 9, the insulating chip 80 includes a first conductor 51 and a second conductor 52. The first conductor 51 and the second conductor 52 are embedded in an insulator 84. The first conductor 51 and the second conductor 52 are formed in different insulating layers 85 within the insulator 84. The first conductor 51 and the second conductor 52 face each other in the Z direction with two or more insulating layers 85 interposed therebetween.

[0076] (First conductor) As shown in FIG. 8 and FIG. 9, the first conductor 51 of the transformers 40A, 40B is configured as a conductive layer embedded in one insulating layer 85 included in the insulator 84. The first conductor 51 is embedded in an insulating layer 853 closer to the insulating lower surface 84r among the multiple insulating layers 85 constituting the insulator 84. The insulating layer 853 has a groove 8531 penetrating both the first insulating layer 85A and the second insulating layer 85B in the Z direction. The first conductor 51 is embedded in the groove 8531 of the insulating layer 853. The first conductor 51 and the insulating layer 853 are covered with an insulating layer 854.

[0077] As shown in FIGS. 6, 8 and 9, the first conductor 51 includes a first coil 41, an inner end wiring 51A and an outer end wiring 51B. As shown in FIG. 6, the first coil 41 is formed in a spiral shape in a plan view. In one example, the first coil 41 may be formed in an elliptical shape in a plan view. The first coil 41 is made of a material including one or more appropriately selected from Ti (titanium), TiN (titanium nitride), Au, Ag, Cu, Al, and W (tungsten). The inner end wiring 51A is disposed inside the first coil 41. The outer end wiring 51B is disposed outside the first coil 41. The first coil 41 includes a first end and a second end opposite to the first end. The first end of the first coil 41 is electrically connected to the inner end wiring 51A, and the second end of the first coil 41 is electrically connected to the outer end wiring 51B.

[0078] The inner end wiring 51A and the outer end wiring 51B are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The outer end wiring 51B is disposed between the first coil 41 of the transformer 40A and the first coil 41 of the transformer 40B. The outer end wiring 51B is configured as a common end wiring for the first coils 41 of the transformers 40A and 40B. Note that an outer end wiring may be provided for each of the first coils 41 of the transformers 40A and 40B.

[0079] (Second Conductor) As shown in FIGS. 8 and 9, the second conductor 52 is configured as a conductive layer embedded in one insulating layer 85 included in the insulator 84. The second conductor 52 is embedded in an insulating layer 857 closer to the insulating upper surface 84s among a plurality of insulating layers 851 to 857 constituting the insulator 84. The insulating layer 857 has a groove 8571 penetrating both the first insulating layer 85A and the second insulating layer 85B in the Z direction. The second conductor 52 is embedded in the groove 8571 of the insulating layer 851. The second conductor 52 and the insulating layer 857 are covered by an insulating layer 85U.

[0080] As shown in FIGS. 6, 8 and 9, the second conductor 52 includes a second coil 42, an inner end wiring 52A and an outer end wiring 52B. As shown in FIG. 6, the second coil 42 is formed in a spiral shape in a plan view. In one example, the second coil 42 may be formed in an elliptical shape in a plan view. The second coil 42 is made of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The inner end wiring 52A is disposed inside the second coil 42. The outer end wiring 52B is disposed outside the second coil 42. The second coil 42 includes a first end and a second end opposite to the first end. The first end of the second coil 42 is electrically connected to the inner end wiring 52A, and the second end of the second coil 42 is electrically connected to the outer end wiring 52B.

[0081] The inner end wiring 52A and the outer end wiring 52B are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The outer end wiring 52B is disposed between the second coil 42 of the transformer 40A and the second coil 42 of the transformer 40B. The outer end wiring 52B is configured as a common end wiring for the second coils 42 of the transformers 40A and 40B. Note that an outer end wiring may be provided for each of the second coils 42 of the transformers 40A and 40B.

[0082] As shown in FIG. 8, a plurality of insulating layers 85 are interposed between the first conductor 51 and the second conductor 52. In the insulating chip 80 of the first embodiment, three insulating layers 854, 855, and 856 are interposed between the first conductor 51 and the second conductor 52. Therefore, it can be said that the insulating chip 80 of the first embodiment includes a first insulator 841 including an insulating layer 853 in which the first conductor 51 is embedded, a second insulator 842 including an insulating layer 857 in which the second conductor 52 is embedded, and a third insulator 843 including insulating layers 854 to 856 arranged between the first insulator 841 and the second insulator 842. It can be said that the first conductor 51 embedded in the first insulator 841 is covered by the third insulator 843. It can be said that the second conductor 52 is formed on the third insulator 843 that covers the first conductor 51.

[0083] (First electrode pad, second electrode pad) 8 and 9, a first electrode pad 81 is formed on an insulating upper surface 84s of an insulator 84. The first electrode pad 81 is disposed on the insulating upper surface 84s, closer to the chip side surface 802. The first electrode pad 81 is disposed at a position not overlapping with the first conductor 51 and the second conductor 52 in a plan view. The first electrode pad 81 is made of a material containing one or more appropriately selected from Cu, Al, Ni (nickel), Pd (palladium), and W.

[0084] As shown in Fig. 5, Fig. 8, and Fig. 9, the first electrode pad 81 includes a first pad 81A and a second pad 81B. The first electrode pad 81 includes two first pads 81A and two second pads 81B connected to the first coil 41 of the transformer 40A. Similarly, the first electrode pad 81 includes two first pads 81A and two second pads 81B connected to the first coil 41 of the transformer 40B. The two first pads 81A are arranged side by side in the X direction. The two second pads 81B are arranged side by side in the X direction.

[0085] 8 and 9, the insulating chip 80 includes a connection wiring 60 that electrically connects the first conductor 51 and the first electrode pad 81. The connection wiring 60 includes a first connection wiring 60A shown in FIG. 8 and a second connection wiring 60B shown in FIG.

[0086] As shown in Fig. 8, the first pad 81A is electrically connected to the inner end wiring 51A of the first conductor 51 by a first connection wiring 60A. As shown in Fig. 9, the second pad 81B is electrically connected to the outer end wiring 51B of the first conductor 51 by a second connection wiring 60B.

[0087] 8 and 9, a second electrode pad 82 is formed on an insulating upper surface 84s of the insulator 84. The second electrode pad 82 is made of a material containing one or more appropriately selected from Cu, Al, Ni, Pd, and W.

[0088] As shown in FIGS. 5, 8 and 9, the second electrode pad 82 includes a third pad 82A and a fourth pad 82B. As shown in FIG. 5 and FIG. 8, the third pad 82A is disposed inside the second coil 42 of the second conductor 52 in a plan view. As shown in FIG. 8, the third pad 82A is disposed so as to overlap with the inner end wiring 52A of the second conductor 52 in a plan view. The fourth pad 82B is disposed outside the second coil 42 of the transformers 40A and 40B in a plan view. The fourth pad 82B is disposed between the second coil 42 of the transformer 40A and the second coil 42 of the transformer 40B. As shown in FIG. 9, the fourth pad 82B is disposed so as to overlap with the outer end wiring 52B of the second conductor 52 in a plan view.

[0089] As shown in Fig. 8, the third pad 82A is electrically connected to the inner end wiring 52A by a via wiring 57A that penetrates the uppermost insulating layer 85U. As shown in Fig. 9, the fourth pad 82B is electrically connected to the outer end wiring 52B by a via wiring 57B that penetrates the uppermost insulating layer 85U. The via wirings 57A and 57B are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0090] As shown in FIG. 5, the second electrode pad 82 includes two third pads 82A and two fourth pads 82B connected to the second coil 42 of the transformer 40A. The second electrode pad 82 also includes two third pads 82A and two fourth pads 82B connected to the second coil 42 of the transformer 40B. The two third pads 82A are arranged side by side in the X direction. The two fourth pads 82B are arranged side by side in the X direction. The two fourth pads 82B are electrically connected to the second coil 42 of the transformer 40A and the second coil 42 of the transformer 40B. Therefore, it can be said that the two fourth pads 82B are provided as common pads for the second coil 42 of the transformer 40A and the second coil 42 of the transformer 40B.

[0091] (passivation film, resin layer) As shown in FIGS. 9 and 10, the insulating chip 80 may include a passivation film 91. The passivation film 91 is formed on the insulating upper surface 84s of the insulator 84. The passivation film 91 is a film that protects the insulator 84. The passivation film 91 can be said to be a surface protection film for the insulating chip 80. The passivation film 91 is formed of, for example, SiO 2 The passivation film 91 is made of a material containing SiN. The passivation film 91 constitutes the chip main surface 80s of the insulating chip 80.

[0092] The first electrode pad 81 and the second electrode pad 82 are covered with a passivation film 91. The passivation film 91 has openings that expose parts of the first electrode pad 81 and the second electrode pad 82. As a result, the first electrode pad 81 has an exposed surface for connecting the wire W2. Also, the second electrode pad 82 has an exposed surface for connecting the wire W3.

[0093] The insulating chip 80 may include a resin layer 92 formed on a passivation film 91. The resin layer 92 may be formed of a material containing, for example, PI (polyimide). The resin layer 92 is separated into an inner resin layer 921 and an outer resin layer 922 by a separation groove 923. As shown in FIG. 4, the separation groove 923 is formed so as to surround the transformers 40A and 40B in a plan view. The resin layer 92 includes a first resin opening 924 exposing the first electrode pad 81 and a second resin opening 925 exposing the second electrode pad 82.

[0094] (Dummy pattern) 5, 7 to 9, the insulating chip 80 includes a dummy pattern 55 provided around the second coil 42 of the transformers 40A, 40B. The dummy pattern 55 may be omitted. As shown in FIGS. 8 and 9, the dummy pattern 55 is embedded in the insulating layer 857 of the insulator 84, similar to the second conductor 52.

[0095] 5 and 7, the dummy pattern 55 includes a first dummy pattern 55A, a second dummy pattern 55B, and a third dummy pattern 55C. The first dummy pattern 55A, the second dummy pattern 55B, and the third dummy pattern 55C are formed of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0096] As shown in FIG. 5 and FIG. 7, the first dummy pattern 55A is provided in a region between the second coil 42 of the transformer 40A and the second coil 42 of the transformer 40B in the X direction in a plan view. The first dummy pattern 55A is formed in a pattern different from that of the second coil 42. The first dummy pattern 55A is electrically connected to the outer end wiring 52B. It is sufficient that the first dummy pattern 55A is electrically connected to at least one of the two outer end wirings 52B. In this way, the first dummy pattern 55A has the same potential as the second coil 42. Therefore, as the second reference potential of the second coil 42 changes, the voltage of the first dummy pattern 55A may become higher than that of the first coil 41, similar to the second coil 42.

[0097] Although not shown, the first dummy pattern 55A is disposed at a position aligned with the second coil 42 in the Z direction. That is, the first dummy pattern 55A is disposed at a position farther from the substrate 83 than the first coil 41. In other words, it can be said that the dummy pattern 55 is provided around the coil of the transformer 40A, 40B that is closer to the chip main surface 80s of the insulating chip 80.

[0098] By making the first dummy pattern 55A have the same voltage as the second coil 42, it is possible to suppress the voltage drop between the second coil 42 and the first dummy pattern 55A. Therefore, electric field concentration on the second coil 42 can be suppressed.

[0099] 6, the third dummy pattern 55C is formed to surround the second coil 42 of the transformers 40A, 40B in a plan view. The third dummy pattern 55C is electrically connected to the first dummy pattern 55A. Therefore, similar to the first dummy pattern 55A, the voltage of the third dummy pattern 55C may become higher than that of the first coil 41 in accordance with a change in the second reference potential of the second coil 42.

[0100] 9, the third dummy pattern 55C is disposed at a position aligned with the second coil 42 in the Z direction. Although not shown, the third dummy pattern 55C is disposed at a position aligned with the second coil 42 in the Z direction. In other words, the third dummy pattern 55C is disposed at a position farther from the substrate 83 than the first coil 41. In this manner, the dummy patterns 55A to 55C are disposed at positions aligned with one another in the Z direction.

[0101] By causing the third dummy pattern 55C to have the same voltage as the second coil 42, it is possible to suppress a voltage drop between the second coil 42 and the third dummy pattern 55C. Therefore, electric field concentration on the second coil 42 can be suppressed.

[0102] 6, the second dummy pattern 55B is formed to surround the third dummy pattern 55C in a plan view. The second dummy pattern 55B is independent of the second coil 42. In other words, the second dummy pattern 55B is not electrically connected to the second coil 42.

[0103] 8 and 9, the second dummy pattern 55B is disposed at a position aligned with the second coil 42 in the Z direction. Although not shown, the second dummy pattern 55B is disposed at a position aligned with the second coil 42 in the Z direction. In other words, the second dummy pattern 55B is disposed at a position farther from the substrate 83 than the first coil 41. The second dummy pattern 55B can suppress an increase in the electric field intensity around the second coil 42 and suppress electric field concentration on the second electrode pads 82 (the third pad 82A and the fourth pad 82B).

[0104] (Configuration of the first connection wiring) 6, 7, and 8, the inner end wiring 51A is electrically connected to the first pad 81A by a first connection wiring 60A. The first connection wiring 60A is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0105] As shown in FIG. 8, the first connection wiring 60A includes a first wiring portion 61A extending in the Z direction so as to penetrate the multiple insulating layers 85, and a second wiring portion 65A extending in the Y direction. The first wiring portion 61A is disposed at a position overlapping with the first pad 81A in a plan view, and is connected to the first pad 81A. The first wiring portion 61A penetrates from an insulating layer 857 closer to the uppermost insulating layer 85U among the multiple insulating layers 85 to an insulating layer 853 closer to the lowermost insulating layer 85L.

[0106] The first wiring portion 61A includes a first layer wiring 62A, a second layer wiring 63A, and a through wiring 64A. The first layer wiring 62A is disposed in the insulator 84 and closer to the insulating lower surface 84r. In one example, the first layer wiring 62A may be disposed at the same position as the first conductor 51 in the Z direction. The first layer wiring 62A is embedded in the insulating layer 853. The first layer wiring 62A is embedded in a through hole 8532 penetrating the insulating layer 853 in the Z direction. The second layer wiring 63A is disposed in the insulator 84 and closer to the insulating upper surface 84s. The second layer wiring 63A faces the first layer wiring 62A in the Z direction. In one example, the second layer wiring 63A may be disposed at the same position as the second conductor 52 in the Z direction. The second layer wiring 63A is embedded in the insulating layer 857. The second layer wiring 63A is embedded in a through hole 8572 penetrating the insulating layer 857 in the Z direction. The first layer wiring 62A and the second layer wiring 63A are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The first layer wiring 62A and the second layer wiring 63A may be formed of the same material as the first conductor 51 and the second conductor 52.

[0107] Two or more insulating layers 85 are interposed between the first layer wiring 62A and the second layer wiring 63A. It can be said that the first layer wiring 62A and the second layer wiring 63A face each other in the Z direction with two or more insulating layers 85 interposed therebetween. In one example, three insulating layers 854, 855, and 856 are interposed between the first layer wiring 62A and the second layer wiring 63A.

[0108] The through wiring 64A electrically connects the first layer wiring 62A and the second layer wiring 63A. The through wiring 64A is disposed in a through hole 71A formed between the first layer wiring 62A and the second layer wiring 63A. The through hole 71A penetrates two or more insulating layers 85. In one example, the through hole 71A is formed penetrating three insulating layers 854-856 interposed between the first layer wiring 62A and the second layer wiring 63A. It can be said that the insulator 84 is formed between the first layer wiring 62A and the second layer wiring 63A in the Z direction and penetrates two or more insulating layers 85 out of the multiple insulating layers 85. The insulator 84 of the first embodiment includes a plurality of through holes 71A penetrating the insulating layers 854-856 between the first layer wiring 62A and the second layer wiring 63A. The through wiring 64A is formed in each of the multiple through holes 71A. Therefore, it can be said that the insulating chip 80 includes a plurality of through-wires 64A that electrically connect the first-layer wiring 62A and the second-layer wiring 63A. The through-wires 64A are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0109] The second wiring portion 65A includes a lead-out wiring 66A and via wirings 67A and 68A. The lead-out wiring 66A is provided closer to the substrate 83 than the first wiring portion 61A. The lead-out wiring 66A is provided closer to the substrate 83 than the first conductor 51.

[0110] The lead-out wiring 66A is provided in an insulating layer 851 that is one layer above the lowermost insulating layer 85L among the multiple insulating layers 85. A first end of the lead-out wiring 66A, which is closer to the chip side surface 802 of the insulating chip 80, is provided at a position overlapping the first wiring portion 61A in a plan view. The first end of the lead-out wiring 66A is electrically connected to the first layer wiring 62A by multiple via wirings 67A. A second end of the lead-out wiring 66A is provided at a position overlapping the inner end wiring 51A of the first conductor 51 in a plan view. The second end of the lead-out wiring 66A is electrically connected to the inner end wiring 51A by multiple via wirings 68A. The lead-out wiring 66A is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The lead-out wiring 66A may be formed of the same material as the first conductor 51. The via wirings 67A and 68A are made of a material containing one or more of Ti, TiN, Au, Ag, Cu, Al, and W appropriately selected.

[0111] (Configuration of the second connection wiring) 6, 7, and 9, the outer end wiring 51B is electrically connected to the second pad 81B by a second connection wiring 60B. The second connection wiring 60B is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0112] As shown in FIG. 9, the second connection wiring 60B includes a first wiring portion 61B that extends in the Z direction so as to penetrate the multiple insulating layers 85, and a second wiring portion 65B that extends in the Y direction. The first wiring portion 61B is disposed at a position overlapping with the second pad 81B in a plan view, and is connected to the second pad 81B. The first wiring portion 61B penetrates from an insulating layer 857 closer to the uppermost insulating layer 85U among the multiple insulating layers 85 to an insulating layer 853 closer to the lowermost insulating layer 85L.

[0113] The first wiring portion 61B includes a first layer wiring 62B, a second layer wiring 63B, and a through wiring 64B. The first layer wiring 62B is disposed in the insulator 84 and closer to the insulating lower surface 84r. In one example, the first layer wiring 62B may be disposed at the same position as the first conductor 51 in the Z direction. The first layer wiring 62B is embedded in the insulating layer 853. The first layer wiring 62B is embedded in a through hole 8532 penetrating the insulating layer 853 in the Z direction. The second layer wiring 63B is disposed in the insulator 84 and closer to the insulating upper surface 84s. The second layer wiring 63B faces the first layer wiring 62B in the Z direction. In one example, the second layer wiring 63B may be disposed at the same position as the second conductor 52 in the Z direction. The second layer wiring 63B is embedded in the insulating layer 857. The second layer wiring 63B is embedded in a through hole 8572 penetrating the insulating layer 857 in the Z direction. The first layer wiring 62B and the second layer wiring 63B are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The first layer wiring 62B and the second layer wiring 63B may be formed of the same material as the first conductor 51 and the second conductor 52.

[0114] Two or more insulating layers 85 are interposed between the first layer wiring 62B and the second layer wiring 63B. It can be said that the first layer wiring 62B and the second layer wiring 63B face each other in the Z direction with two or more insulating layers 85 interposed therebetween. In one example, three insulating layers 854, 855, and 856 are interposed between the first layer wiring 62B and the second layer wiring 63B.

[0115] The through wiring 64B electrically connects the first layer wiring 62B and the second layer wiring 63B. The through wiring 64B is disposed in a through hole 71B formed between the first layer wiring 62B and the second layer wiring 63B. The through hole 71B penetrates two or more insulating layers 85. In one example, the through hole 71B is formed penetrating three insulating layers 854-856 interposed between the first layer wiring 62B and the second layer wiring 63B. It can be said that the insulator 84 is formed between the first layer wiring 62B and the second layer wiring 63B in the Z direction and penetrates two or more insulating layers 85 out of the multiple insulating layers 85. The insulator 84 of the first embodiment includes a plurality of through holes 71B penetrating the insulating layers 854-856 between the first layer wiring 62B and the second layer wiring 63B. The through wiring 64B is formed in each of the multiple through holes 71B. Therefore, it can be said that the insulating chip 80 includes a plurality of through-wires 64B that electrically connect the first-layer wiring 62B and the second-layer wiring 63B. The through-wires 64B are made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

[0116] The second wiring portion 65B includes a lead-out wiring 66B and via wirings 67B and 68B. The lead-out wiring 66B is provided closer to the substrate 83 than the first wiring portion 61B. The lead-out wiring 66B is provided closer to the substrate 83 than the first conductor 51.

[0117] The lead-out wiring 66B is provided in an insulating layer 851 that is one layer above the lowermost insulating layer 85L among the multiple insulating layers 85. A first end of the lead-out wiring 66B, which is closer to the chip side surface 802 of the insulating chip 80, is provided at a position overlapping the first wiring portion 61B in a plan view. The first end of the lead-out wiring 66B is electrically connected to the first layer wiring 62B by multiple via wirings 67B. A second end of the lead-out wiring 66B is provided at a position overlapping the outer end wiring 51B of the first conductor 51 in a plan view. The second end of the lead-out wiring 66B is electrically connected to the outer end wiring 51B by multiple via wirings 68B. The lead-out wiring 66B is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The lead-out wiring 66B may be formed of the same material as the first conductor 51. The via wirings 67B and 68B are made of a material containing one or more of Ti, TiN, Au, Ag, Cu, Al, and W selected appropriately.

[0118] The lead wiring 66B of the second wiring portion 65B is electrically connected to the substrate 83 by a via wiring 69 that penetrates the lowermost insulating layer 85L. The via wiring 69 is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The via wiring 69 may be omitted.

[0119] (Connection wiring details) Fig. 10 is a schematic plan view showing the first layer wiring 62A and the through wiring 64A of the first connection wiring 60A. Fig. 11 shows a cross-sectional structure cut along line 11-11 in Fig. 10, showing the first layer wiring 62A, the through wiring 64A, and the second layer wiring 63A. The second connection wiring 60B is formed in the same shape as the first connection wiring 60A. For this reason, drawings and descriptions of the second connection wiring 60B are omitted.

[0120] 10, the first layer wiring 62A is formed in a substantially rectangular shape. In one example, the first layer wiring 62A is formed in a square shape with rounded corners. The first layer wiring 62A may include a frame portion 621 and a connection portion 622. The frame portion 621 is formed in a ring shape in a plan view. The frame portion 621 includes two first straight line portions 6211 arranged in the Y direction and extending in the X direction, two second straight line portions 6212 arranged in the X direction and extending in the Y direction, and a curved portion 6213 connecting the first straight line portions 6211 and the second straight line portions 6212. The outer side of the curved portion 6213 is formed in an arc shape.

[0121] 7, the second layer wiring 63A is formed in the same shape as the first layer wiring 62A. The second layer wiring 63A may include a frame portion 621 and a connection portion 622, similar to the first layer wiring 62A.

[0122] 10, the connection portion 622 is disposed inside the frame portion 621. The connection portion 622 includes a first connection portion that connects the two first straight portions 6211 to each other, and a second connection portion 6222 that intersects with the first connection portion 6221 and connects the two second straight portions 6212 to each other. In one example, the first connection portion 6221 and the second connection portion 6222 are perpendicular to each other.

[0123] The through hole 71A is formed in a circular shape in a plan view. In one example, the through hole 71A may include a first through hole 71A1 provided in correspondence with the frame portion 621 and a second through hole 71A2 provided in correspondence with the connection portion 622. The first through holes 71A1 are arranged in plurality along the frame portion 621. The second through hole 71A2 is arranged at a position where the first connection portion 6221 and the second connection portion 6222 intersect. The arrangement positions of the first through hole 71A1 and the second through hole 71A2 may be changed as appropriate.

[0124] The through wiring 64A is formed in each through hole 71A. The through wiring 64A is formed in a circular shape in a plan view. The through wiring 64A includes a first through wiring 64A1 provided in the first through hole 71A1 and a second through wiring 64A2 provided in the second through hole 71A2.

[0125] As shown in FIG. 11, the through hole 71A is formed so as to expose the upper surface of the first layer wiring 62A. A bottom surface 711 of the through hole 71A is formed by the first layer wiring 62A exposed by the through hole 71A. A side surface 712 constituting the through hole 71A is formed by the three insulating layers 854-856 in which the through hole 71A is formed. The side surface 712 of the through hole 71A is continuously formed across the three insulating layers 854-856. The side surface 712 of the through hole 71A is continuously formed from the first layer wiring 62A toward the second layer wiring 63A.

[0126] Diameter D1 of bottom surface 711 of through hole 71A is equal to or greater than depth H1 of through hole 71A in the Z direction. An aspect ratio, which is the ratio of depth H1 of through hole 71A to diameter D1 of bottom surface 711 of through hole 71A, is equal to or less than 1. The aspect ratio may be equal to or less than 0.5.

[0127] The depth H1 of the through hole 71A is determined by the thickness H2 in the Z direction of each of the three insulating layers 85 in which the through hole 71A is formed. In one example, the diameter of the bottom surface 711 of the through hole 71A may be 16 μm. In one example, the depth H1 of the through hole 71A may be 8 μm.

[0128] The inclination angle θ1 of the side surface 712 of the through hole 71A is defined as the angle between the bottom surface 854r of the insulating layers 854-856 having the through hole 71A and the side surface 712 of the through hole 71A. The inclination angle θ1 of the side surface 712 of the through hole 71A is not less than 70 degrees and not more than 90 degrees. In one example, the inclination angle θ1 is 80 degrees.

[0129] A diameter D1 of a bottom surface 711 of the through hole 71A is smaller than a width WL1 of a frame portion 621 of the first layer wiring 62A. A diameter D2 of an opening 713 at the upper end of the through hole 71A is smaller than a width WL2 of a frame portion 621 of the second layer wiring 63A.

[0130] (Insulating chip manufacturing method) Next, a method for manufacturing the insulating chip 80 shown in FIGS. 5 to 11 will be described. 12 to 22 are schematic cross-sectional views showing an exemplary manufacturing method of the first layer wiring 62A, the through wiring 64A, and the second layer wiring 63A of the connection wiring 60 (60A) of the insulating chip 80. Note that FIGS. 12 to 22 show a schematic cross-sectional structure of a part of the insulating chip 80 shown in FIG. 8, which corresponds to the cross-sectional structure of the first layer wiring 62A, the through wiring 64A, and the second layer wiring 63A shown in FIG. 11. For this reason, in FIGS. 12 to 22, members other than the first layer wiring 62A, the through wiring 64A, the second layer wiring 63A, and the surrounding insulating layer are omitted. Please refer to FIG. 8 for the reference numerals not shown in . Also, in FIGS. 12 to 22, for ease of understanding, the reference numerals in FIGS. 5 to 11 are partially shown in parentheses for members including the final components of the insulating chip 80 or members corresponding thereto.

[0131] 12, the method for manufacturing the insulating chip 80 includes a step of forming insulating layers 852 and 853. In one example, the insulating layers 852 and 853 are formed on the substrate upper surface 83s of the substrate 83 by chemical vapor deposition (CVD). In one example, the insulating layer 85L is formed on the substrate upper surface 83s of the substrate 83. Next, the insulating layers 851, 852, and 853 are formed by repeatedly stacking the first insulating layer 85A and the second insulating layer 85B.

[0132] As shown in FIGS. 13 to 15, the method for manufacturing the insulating chip 80 includes a step of forming the first layer wiring 62A. As shown in FIG. 13, through holes 8532 are formed in the insulating layer 853, for example, by selectively etching the insulating layer 853.

[0133] 14, a conductive layer 1901 is formed by, for example, plating so as to cover the insulating layers 852 and 853. The conductive layer 1901 may include, for example, a seed layer and a plating layer. For example, a seed layer is formed by, for example, sputtering so as to cover the inner surface of the through hole 8532 of the insulating layer 853 and the upper surface of the insulating layer 852. Next, a conductive material containing, for example, Cu is plated and grown from the seed layer to form the conductive layer 1901. The conductive layer 1901 is formed so as to fill the through hole 8532 of the insulating layer 853.

[0134] 15, the first layer wiring 62A is formed. For example, the conductive layer 1901 is planarized by isotropic dry etching or chemical mechanical polishing (CMP) to remove the conductive layer 1901 on the insulating layer 853. In this manner, the first layer wiring 62A is formed.

[0135] 16, the method for manufacturing the insulating chip 80 includes the steps of forming the insulating layers 854, 855, and 856. For example, the insulating layers 854, 855, and 856 are formed by alternately stacking the first insulating layer 85A and the second insulating layer 85B by CVD.

[0136] 17 to 19, the method for manufacturing the insulating chip 80 includes a step of forming the through hole 71 A. For example, the insulating layers 854 to 856 are selectively etched all at once to form the through hole 71 A in the insulating layers 854 to 856 so as to expose a part of the upper surface 62As of the first-layer wiring 62A.

[0137] As shown in FIGS. 18 and 19, the method for manufacturing the insulating chip 80 includes a step of forming the through wiring 64A. 18, a conductive layer 1902 is formed by, for example, plating so as to cover the bottom surface 711 and side surface 712 of the through hole 71A and the insulating layer 856. The conductive layer 1902 may include, for example, a seed layer and a plating layer. For example, a seed layer is formed by, for example, sputtering so as to cover the bottom surface 711 and side surface 712 of the through hole 71A and the upper surface of the insulating layer 856. Next, a conductive material containing, for example, Cu is plated and grown from the seed layer to form the conductive layer 1902. The conductive layer 1902 is formed so as to fill the through hole 71A which collectively penetrates the insulating layers 854 to 856.

[0138] 19, the through wiring 64A is formed. For example, the conductive layer 1902 is planarized by isotropic dry etching or CMP, thereby removing the conductive layer 1902 on the insulating layer 856. In this manner, the through wiring 64A is formed.

[0139] 20, the method for manufacturing the insulating chip 80 includes a step of forming an insulating layer 857. For example, by CVD, a first insulating layer 85A and a second insulating layer 85B are stacked to form the insulating layer 857 so as to cover the upper surface of the insulating layer 856 and the upper surface 64As of the through-wire 64A.

[0140] As shown in FIGS. 21 and 22, the method for manufacturing the insulating chip 80 includes a step of forming the second layer wiring 63A. As shown in FIG. 21, for example, the insulating layer 857 is selectively etched to form a through hole 8572 in the insulating layer 857 so as to expose the upper surface 64As of the through wiring 64A.

[0141] A conductive layer is formed by, for example, plating so as to cover the insulating layers 856 and 857 and the upper surface 64As of the through wiring 64A. The conductive layer may include, for example, a seed layer and a plating layer. A seed layer is formed by, for example, sputtering so as to cover the upper surface 64As of the through wiring 64A, the inner surface of the through hole 8572 of the insulating layer 856, and the upper surface of the insulating layer 857. Next, a conductive material including, for example, Cu is plated and grown from the seed layer to form a conductive layer. The conductive layer is formed so as to fill the through hole 8572 of the insulating layer 857.

[0142] 22, the second layer wiring 63A is formed. For example, the conductive layer is planarized by isotropic dry etching or CMP, thereby removing the conductive layer on the insulating layer 857. In this manner, the second layer wiring 63A is formed.

[0143] (action) Next, the operation of the insulating tip 80 of the first embodiment will be described. First, a comparative insulating chip 80 will be described. The insulating chip 80X of the comparative example differs from the insulating chip 80 of the first embodiment in the shapes of the through holes 71AX and the through wirings 64AX. Therefore, the insulating chip 80X of the comparative example will be labeled with the same reference numerals as the insulating chip 80 of the first embodiment for the same components.

[0144] Fig. 28 is a schematic plan view showing the first layer wiring 62A and the through wiring 64AX in an insulating chip 80X of a comparative example. Fig. 29 is a schematic cross-sectional view showing the first layer wiring 62A, the through wiring 64AX, and the second layer wiring 63A of the comparative example.

[0145] As shown in Fig. 28, through hole 71AX of the comparative example is formed in a square shape in a plan view. As shown in Fig. 29, through hole 71AX of the comparative example has an aspect ratio, which is the ratio of depth H1X of through hole 71AX to length L1X of bottom surface 711 in X direction perpendicular to the Z direction, of "2" or more.

[0146] The through wiring 64AX of the comparative example is formed in the through hole 71AX of the comparative example. In this case, a void (air gap) 71AB may be generated in the through wiring 64AX of the comparative example. The void 71AB may be a cause of an increase in resistance in the through wiring 64AX.

[0147] The through wiring 64AX of the comparative example will be described with reference to FIGS. Figures 30 and 31 are schematic cross-sectional views showing a process of forming the through wiring 64AX of the comparative example shown in Figures 28 and 29. Figures 32 to 34 are schematic plan views showing a process of forming the through wiring 64AX of the comparative example.

[0148] 30, a conductive layer 1902X is formed so as to cover the bottom surface 711 and side surface 712 of the through hole 71AX and the upper surface 856s of the insulating layer 856. The conductive layer 1902X gradually grows by plating from the bottom surface 711 and side surface 712 of the through hole 71AX and the upper surface 856s of the insulating layer 856. The conductive layer 1902X includes a first portion X1 covering the bottom surface 711 of the through hole 71AX, a second portion X2 covering the side surface 712 of the through hole 71AX, and a third portion X3 covering the upper surface 856s of the insulating layer 856. The space formed by the first portion X1 and the second portion X2 of the conductive layer 1902X becomes smaller as the conductive layer 1902X grows. Therefore, the first portion X1 covering the bottom surface 711 of the through hole 71AX is more difficult to receive plating liquid and to grow than the second portion X2 covering the side surface 712 of the through hole 71AX and the third portion X3 covering the upper surface 856s of the insulating layer 856. That is, the plating growth of the conductive layer 1902X generated in the through hole 71AX varies. Then, as shown in FIG. 31, the opening of the through hole 71AX is blocked by the second portion X2 covering the side surface 712 of the through hole 71AX. Therefore, a void 71AB is generated inside the through hole 71AX.

[0149] 32, the conductive layer 1902X covering each side surface 712 of the through hole 71AX grows from each side surface 712 toward the center. As shown in FIG. 33, the central portion of each side surface 712 is closer to the center of the through hole 71AX than the corner portions formed by each side surface 712. That is, the plating growth of the conductive layer 1902X generated in the through hole 71AX varies. As shown in FIG. 34, gaps are generated at the locations corresponding to the corner portions, so voids are likely to occur.

[0150] In contrast to these, the insulating chip 80 of the first embodiment can suppress the occurrence of voids in the through wiring 64 A. The through wiring 64 A of the first embodiment will be described with reference to Figs.

[0151] Figures 23 and 24 are schematic cross-sectional views showing a process for forming the through wiring 64A of the first embodiment shown in Figures 10 and 11. Figures 25 to 27 are schematic plan views showing a process for forming the through wiring 64A of the first embodiment.

[0152] As shown in FIG. 23, a conductive layer 1902 is formed to cover the bottom surface 711 and side surface 712 of the through hole 71A and the upper surface 856s of the insulating layer 856. The conductive layer 1902 gradually grows by plating from the bottom surface 711 and side surface 712 of the through hole 71A and the upper surface 856s of the insulating layer 856. The conductive layer 1902 includes a first portion A1 covering the bottom surface 711 of the through hole 71A, a second portion A2 covering the side surface 712 of the through hole 71A, and a third portion A3 covering the upper surface 856s of the insulating layer 856. The space formed by the first portion A1 and the second portion A2 of the conductive layer 1902 becomes smaller as the conductive layer 1902 grows, but is larger than that of the comparative example. For this reason, a sufficient plating solution enters the first portion A1 covering the bottom surface 711 of the through hole 71A, so that it grows in the same manner as the second portion A2 and the third portion A3. That is, it is possible to suppress variations in plating growth in conductive layer 1902 generated in through hole 71A. Therefore, as shown in Fig. 24, through hole 71A can be filled with conductive layer 1902. This makes it possible to suppress the occurrence of voids in through wiring 64A.

[0153] 25, the conductive layer 1902 covering the side surface 712 of the through hole 71A grows from the side surface 712 toward the center. As shown in FIGS. 26 and 27, the conductive layer 1902 approaches the center of the through hole 71A from the side surface 712. That is, it is possible to suppress the variation in plating growth in the conductive layer 1902 generated in the through hole 71A. Therefore, gaps such as those in the conductive layer 1902X of the comparative example shown in FIG. 34 are unlikely to occur. Therefore, it is possible to suppress the occurrence of voids in the through wiring 64A.

[0154] The through wiring 64AX of the comparative example shown in Fig. 28 is formed in a rectangular shape in a plan view. That is, the through hole 71AX of the comparative example is formed in a rectangular shape in a plan view. Stress caused by temperature changes in the insulator 84 or stress remaining during the manufacturing process may concentrate on the corners of the through wiring 64AX of the comparative example. The stress concentration on the corners may cause cracks to occur in the insulator 84.

[0155] In contrast, the through wire 64A in the first embodiment is formed in a circular shape in a plan view. Therefore, in the insulating chip 80 of the first embodiment, stress concentration can be alleviated. As a result, the occurrence of cracks in the insulator 84 can be suppressed.

[0156] The through hole 71A in the first embodiment is formed by collectively processing the three insulating layers 854 to 856. Therefore, the number of steps required for processing can be reduced compared to the case where a through hole and a through wiring are formed for each of the insulating layers 854 to 856.

[0157] (effect) As described above, according to the first embodiment, the following effects are achieved. (1-1) The insulating chip 80 includes an insulator 84, a first conductor 51, a second conductor 52, a first electrode pad 81, and a first connection wiring 60A. The insulator 84 includes an insulating lower surface 84r and an insulating upper surface 84s facing opposite sides in the Z direction, and is composed of a plurality of insulating layers 85 stacked in the Z direction. The first conductor 51 is disposed in the insulator 84 and closer to the insulating lower surface 84r. The second conductor 52 is disposed in the insulator 84 and closer to the insulating upper surface 84s, and faces the first conductor 51 in the Z direction. The first electrode pad 81 is provided on the insulating upper surface 84s. The first connection wiring 60A electrically connects the first conductor 51 and the first electrode pad 81.

[0158] The first connection wiring 60A includes a first layer wiring 62A arranged in the insulator 84 and closer to the insulating lower surface 84r, a second layer wiring 63A arranged in the insulator 84 and closer to the insulating upper surface 84s and facing the first layer wiring 62A in the Z direction, and a through wiring 64A electrically connecting the first layer wiring 62A and the second layer wiring 63A. The insulator 84 includes a through hole 71A formed between the first layer wiring 62A and the second layer wiring 63A in the Z direction and penetrating two or more of the insulating layers 85. The through wiring 64A is arranged in the through hole 71A. The through hole 71A is circular when viewed from the Z direction.

[0159] The through wire 64A disposed in the through hole 71A is formed in a circular shape in a plan view. Therefore, in the insulating chip 80 of the first embodiment, stress concentration can be alleviated. As a result, the occurrence of cracks in the insulator 84 can be suppressed.

[0160] (1-2) In the first embodiment, the aspect ratio of the through hole 71A, which is the ratio of the depth H1 of the through hole 71A to the diameter D1 of the bottom surface 711 of the through hole 71A, is equal to or less than 1. Therefore, the generation of the voids 71AB in the through wiring 64A can be suppressed.

[0161] (1-3) The through hole 71A in the first embodiment is formed by collectively processing the three insulating layers 854 to 856. Therefore, compared to forming a through hole and a through wiring for each of the insulating layers 854 to 856, the number of steps involved in the manufacturing process of the insulating chip 80 can be reduced.

[0162] Second embodiment 35 to 37, an insulating tip 280 of a second embodiment will be described. The insulating chip 280 of the second embodiment is different from the insulating chip 80 of the first embodiment in the shape of the through wiring 260. The following describes in detail the differences from the insulating chip 80 of the first embodiment. Also, the same reference numerals are used to designate components common to the insulating chip 80 of the first embodiment, and detailed descriptions thereof will be omitted.

[0163] FIG. 35 is a schematic cross-sectional view of an insulating tip 280 according to the second embodiment, and corresponds to the schematic cross-section of the insulating tip 80 of the first embodiment shown in FIG. In the insulating chip 280 of the second embodiment, the first wiring portion 61A of the first connection wiring 60A includes a through wiring 260 arranged between the first layer wiring 62A and the second layer wiring 63A. The through wiring 260 is arranged in a through hole 71A formed by penetrating the insulating layers 854 to 856 of the insulator 84. The through wiring 260 electrically connects the first layer wiring 62A and the second layer wiring 63A.

[0164] (Details of through-wiring and through-holes) Fig. 36 is a schematic plan view showing the first layer wiring 62A of the first connection wiring 60A and the through wiring 260. Fig. 37 shows a cross-sectional structure cut along line 37-37 in Fig. 36, and shows the first layer wiring 62A, the through wiring 260, and the second layer wiring 63A.

[0165] In one example, the through hole 71A may be formed in a circular shape in a plan view. The shape of the through hole 71A in a plan view may be changed as desired. In one example, the through hole 71A may be formed in any rectangular shape, such as a square shape or a rectangular shape, in a plan view.

[0166] The through wiring 260 is formed in each through hole 71A. In one example, the through wiring 260 may be formed in a circular shape in a planar view. The shape of the through wiring 260 in a planar view may be changed arbitrarily. In one example, the through wiring 260 may be an arbitrary rectangular shape such as a square shape or a rectangular shape in a planar view.

[0167] As shown in FIG. 37, the through hole 71A is formed so as to expose the upper surface of the first layer wiring 62A. A bottom surface 711 of the through hole 71A is formed by the first layer wiring 62A exposed by the through hole 71A. A side surface 712 of the through hole 71A is formed by the three insulating layers 854-856 in which the through hole 71A is formed. The side surface 712 of the through hole 71A is continuously formed across the three insulating layers 854-856. The side surface 712 of the through hole 71A is continuously formed from the first layer wiring 62A toward the second layer wiring 63A.

[0168] Diameter D1 of bottom surface 711 of through hole 71A may be smaller than depth H1 of through hole 71A in the Z direction. An aspect ratio, which is the ratio of depth H1 of through hole 71A to diameter D1 of bottom surface 711 of through hole 71A, is equal to or less than 3. The aspect ratio may be equal to or less than 2.

[0169] The inclination angle θ1 of the side surface 712 of the through hole 71A is defined as the angle between the bottom surface 854r of the insulating layers 854-856 having the through hole 71A and the side surface 712 of the through hole 71A. The inclination angle θ1 of the side surface 712 of the through hole 71A is not less than 70 degrees and not more than 90 degrees. In one example, the inclination angle θ1 is 80 degrees.

[0170] The through wiring 260 includes a first via portion 261 and a second via portion 267 . The first via portion 261 is formed so as to cover the bottom surface 711 and the side surface 712 of the through hole 71A. The first via portion 261 includes a bottom surface 262 that contacts the bottom surface 711 of the through hole 71A, and a via recess 263 that is recessed toward the bottom surface 262 on the opposite side to the bottom surface 262. The via recess 263 includes a recess bottom surface 264 that is smaller than the bottom surface 711 of the through hole 71A, and a recess side surface 265 that is formed at an inclination angle θ2 that is smaller than the inclination angle θ1 of the side surface 712 that constitutes the through hole 71A. The recess bottom surface 264 is formed in a circular shape in a plan view. A diameter D21 of the recess bottom surface 264 is smaller than a diameter D1 of the bottom surface 711 of the through hole 71A. A depth H21 of the via recess 263 is smaller than a depth H1 of the through hole 71A. The first via portion 261 is made of a material containing one or more of Ti, TiN, Au, Ag, Cu, Al, and W selected appropriately.

[0171] The second via portion 267 is embedded in the via recess 263 of the first via portion 261. The second via portion 267 is made of a material including one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The first via portion 261 and the second via portion 267 may be made of the same material. Also, the first via portion 261 and the second via portion 267 may be made of different materials.

[0172] (Insulating chip manufacturing method) A method for manufacturing the through wiring 260 of the first wiring portion 61A of the insulating chip 280 will be described with reference to FIGS.

[0173] FIG. 38 shows the first layer wiring 62A and three insulating layers 854 to 856 that cover the first layer wiring 62A. 39, the method for manufacturing the insulating chip 280 includes a step of forming a through hole 71 A. For example, the insulating layers 854-856 are selectively etched all at once to form the through hole 71 A in the insulating layers 854-856 so as to expose a part of the upper surface 62As of the first layer wiring 62A.

[0174] As shown in FIGS. 40 and 41, the method for manufacturing the insulating chip 280 includes a step of forming the first via portion 261. 40, a first conductive layer 1911 is formed by, for example, plating so as to cover the bottom surface 711 and side surface 712 of the through hole 71A and the insulating layer 856. The first conductive layer 1911 may include, for example, a seed layer and a plating layer. For example, a seed layer is formed by, for example, sputtering so as to cover the bottom surface 711 and side surface 712 of the through hole 71A and the upper surface 856s of the insulating layer 856. Next, a conductive material including, for example, Cu is plated from the seed layer to form the first conductive layer 1911. The first conductive layer 1911 is formed so as to cover the bottom surface 711 and side surface 712 of the through hole 71A.

[0175] As shown in FIG. 41, the first conductive layer 1911 is etched to form the first via portion 261. For example, anisotropic etching can be used as the etching for the first conductive layer 1911. By the anisotropic etching, the portion of the first conductive layer 1911 that covers the insulating layer 856 is mainly etched. Furthermore, the first conductive layer 1911 is etched such that the thickness of the portion 1911X (see FIG. 40) that covers the side surface 712 of the through hole 71A becomes thinner from the bottom surface 711 of the through hole 71A toward the upper surface 856s of the insulating layer 856. In this manner, the first via portion 261 including the via recess 263 is formed.

[0176] As shown in FIGS. 42 and 43, the method for manufacturing the insulating chip 280 includes a step of forming the second via portion 267. As shown in FIG. 42, a second conductive layer 1912 is formed by, for example, plating so as to cover the upper surface 856s of the insulating layer 856 and the recess bottom surface 264 and recess side surface 265 of the first via portion 261. The second conductive layer 1912 may include, for example, a seed layer and a plating layer. For example, a seed layer is formed by, for example, sputtering so as to cover the recess bottom surface 264 and recess side surface 265 of the via recess 263 and the upper surface 856s of the insulating layer 856. Next, a conductive material including, for example, Cu is plated and grown from the seed layer to form the second conductive layer 1912. The second conductive layer 1912 is formed so as to fill the via recess 263 of the first via portion 261.

[0177] 43, the second via portion 267 is formed. For example, the second conductive layer 1912 is planarized by isotropic dry etching or a CMP method, thereby removing the second conductive layer 1912 on the insulating layer 856. In this manner, the second via portion 267 is formed. Then, the through wiring 260 is formed by the second via portion 267 and the first via portion 261.

[0178] (action) Next, the operation of the insulating tip 280 of the second embodiment will be described. The through wiring 260 of the second embodiment is formed by a first via portion 261 and a second via portion 267. The first via portion 261 covers the bottom surface 711 and the side surface 712 of the through hole 71A. The first via portion 261 includes a via recess 263 including a recess bottom surface 264 smaller than the bottom surface of the through hole 71A and a recess side surface 265 formed at an inclination angle θ2 smaller than the inclination angle θ1 of the side surface 712 constituting the through hole 71A. The depth H21 of this via recess 263 is smaller than the depth H1 of the through hole 71A. Therefore, when forming the second conductive layer 1912 constituting the second via portion 267, the second conductive layer 1912 growing by plating from the recess bottom surface 264 approaches the opening of the through hole 71A compared to the case where the second conductive layer 1912 grows by plating from the bottom surface 711 of the through hole 71A. Further, the inclination angle θ2 of the recess side surface 265 of the via recess 263 is smaller than the inclination angle θ1 of the side surface 712 constituting the through hole 71A. Therefore, when forming the second conductive layer constituting the second via portion 267, the second conductive layer 1912 growing by plating from the recess side surface 265 is unlikely to block the opening of the via recess 263, i.e., the opening of the through hole 71A. Therefore, the through wiring 260 constituted by the first via portion 261 and the second via portion 267 can suppress the occurrence of voids inside the through wiring 260.

[0179] (effect) As described above, according to the second embodiment, the following effects are achieved. (2-1) The insulating tip 280 of the second embodiment has the same effects as the insulating tip 80 of the first embodiment.

[0180] (2-2) The through wiring 260 of the insulating chip 280 of the second embodiment includes a first via portion 261 including a via recess 263 that covers the bottom surface 711 and the side surface 712 of the through hole 71A and includes a recess bottom surface 264 that is smaller than the bottom surface 711 of the through hole 71A and a recess side surface 265 that is formed at an inclination angle θ2 that is smaller than the inclination angle θ1 of the side surface 712 that constitutes the through hole 71A, and a second via portion 267 embedded in the via recess 263 of the first via portion 261. With this configuration, the insulating chip 280 can suppress the occurrence of voids inside the through wiring 260.

[0181] Third embodiment An insulating tip 380 of the third embodiment will be described with reference to FIGS. The insulating chip 380 of the third embodiment is different from the insulating chip 80 of the first embodiment in the shape of the through wiring 360. The following describes in detail the differences from the insulating chip 80 of the first embodiment. Also, the same reference numerals are used to designate components common to the insulating chip 80 of the first embodiment, and detailed descriptions thereof will be omitted.

[0182] FIG. 44 is a schematic cross-sectional view of an insulating tip 380 according to the third embodiment, and corresponds to the schematic cross-section of the insulating tip 80 of the first embodiment shown in FIG. In the insulating chip 380 of the third embodiment, the first wiring portion 61A of the first connection wiring 60A includes a through wiring 360 arranged between the first layer wiring 62A and the second layer wiring 63A. The through wiring 360 is arranged in a through hole 370 formed by penetrating the insulating layers 854 to 856 of the insulator 84. The through wiring 360 electrically connects the first layer wiring 62A and the second layer wiring 63A.

[0183] As shown in FIG. 45, the through hole 370 includes a first portion 371 closer to the first layer wiring 62A and a second portion 372 closer to the second layer wiring 63A. The first portion 371 extends from the upper surface 62As of the first layer wiring 62A toward the second layer wiring 63A. The first portion 371 may be formed such that the distance between both side surfaces in a direction perpendicular to the Z direction, for example, in the X direction, gradually increases toward the second layer wiring. Also, the distance between both side surfaces of the first portion 371 in a direction perpendicular to the Z direction, for example, in the X direction, may be constant in the Z direction. In one example, the through hole 370 is formed to be circular in plan view. In the through hole 370 that is circular in plan view, the distance between both side surfaces in a direction perpendicular to the Z direction, for example, in the X direction, may be the diameter of the through hole 370. That is, the first portion 371 may be formed such that the diameter D31 gradually increases toward the second layer wiring. Also, the diameter D31 of the first portion 371 may be constant in the Z direction.

[0184] The second portion 372 is formed such that a diameter D32, which is the distance between both side surfaces in a direction perpendicular to the Z direction, for example, in the X direction, gradually increases toward the second layer wiring. The inclination angle θ32 of the side surface 3721 of the second portion 372 is formed smaller than the inclination angle θ31 of the side surface 3711 of the first portion 371. It can be said that the inclination angle θ31 of the side surface 3711 of the first portion 371 is larger than the inclination angle θ32 of the side surface 3721 of the second portion 372.

[0185] The through wiring 360 is disposed in the through hole 370. The through wiring 360 includes a first portion 361 close to the first layer wiring 62A and a second portion 362 close to the second layer wiring 63A. The first portion 361 of the through wiring 360 is a portion formed in the first portion 371 of the through hole 370, and the second portion 362 of the through wiring 360 is a portion formed by the second portion 372 of the through hole 370. The diameter of the through wiring 360 in a direction perpendicular to the Z direction, for example, in the X direction, is equal to the diameter of the through hole 370, and a diameter D31 at the upper end of the first portion 361 of the through wiring 360 is equal to a diameter D32 at the lower end of the second portion 362 of the through wiring 360.

[0186] (Insulating chip manufacturing method) A method for manufacturing the through wiring 360 of the first wiring portion 61A of the insulating chip 380 will be described with reference to FIGS.

[0187] FIG. 46 shows the first layer wiring 62A and three insulating layers 854 to 856 that cover the first layer wiring 62A. 47 and 48, a method for manufacturing an insulating chip 380 includes a step of forming a through hole 370. The through hole 370 includes a first portion 371 close to the first layer wiring 62A and a second portion 372 on the opposite side of the first layer wiring 62A with respect to the first portion 371. 47, for example, the insulating layers 854-856 are etched together to form a first through hole 370A in the insulating layers 854-856 so as to expose a part of the upper surface 62As of the first layer wiring 62A. The first through hole 370A includes a first portion 371 closer to the first layer wiring 62A. The insulating layers 854-856 are etched together to form the first portion 371.

[0188] As shown in FIG. 48, the insulating layers 854-856 are selectively etched to form the second portion 372. For example, anisotropic etching can be used to form the second portion. The opening of the first through hole 370A is removed by anisotropic etching to form the second portion 372. In this manner, the through hole 370 including the first portion 371 and the second portion 372 is formed.

[0189] As shown in FIGS. 49 and 50, the method for manufacturing an insulating chip 380 includes a step of forming a through-wire 360. As shown in FIG. 49, a conductive layer 1921 is formed by, for example, plating so as to cover the bottom and side surfaces of the through-hole 370 and the insulating layer 856. The conductive layer 1921 may include, for example, a seed layer and a plating layer. A seed layer is formed by, for example, sputtering so as to cover the bottom and inner surfaces of the through-hole 370 and the upper surface 856s of the insulating layer 856. Next, a conductive material including, for example, Cu is plated from the seed layer to form the conductive layer 1921. The conductive layer 1921 is formed so as to fill the through-hole 370 of the insulating layers 854-856.

[0190] Here, the second portion 372 of the through hole 370 is formed such that a diameter D32, which is the distance between both side surfaces in a direction perpendicular to the Z direction, for example, in the X direction, becomes gradually larger from the upper end of the first portion 371 toward the opening end of the through hole 370. Therefore, the conductive layer 1921 growing by plating from the side surface 3721 of the second portion 372 is unlikely to block the opening of the through hole 370. Therefore, the generation of voids in the conductive layer 1921 filling the through hole 370 can be suppressed.

[0191] 50, the through wiring 360 is formed. For example, the conductive layer 1921 is planarized by isotropic dry etching or CMP, thereby removing the conductive layer 1921 on the insulating layer 856. In this manner, the through wiring 360 is formed.

[0192] (effect) As described above, according to the third embodiment, the following effects are achieved. (3-1) The insulating tip 380 of the third embodiment has the same effects as the insulating tip 80 of the first embodiment.

[0193] (3-2) The through hole 370 of the third embodiment includes a first portion 371 close to the first layer wiring 62A and a second portion 372 close to the second layer wiring 63A. The second portion 372 is formed such that a diameter D32, which is the distance between both side surfaces in a direction perpendicular to the Z direction, for example, in the X direction, becomes gradually larger from the upper end of the first portion 371 toward the second layer wiring 63A. Therefore, the conductive layer 1921 that grows by plating from the side surface 3721 of the second portion 372 is unlikely to block the opening of the through hole 370. Therefore, the conductive layer 1921 filling the through hole 370, that is, the through wiring 360, can suppress the occurrence of voids.

[0194] (Fourth embodiment) A signal transmission device 410 including an insulating tip 480 according to a fourth embodiment will be described with reference to FIGS.

[0195] 51 is a schematic diagram showing an example of a circuit configuration of a signal transmission device 410. This signal transmission device 410 differs from the signal transmission device 10 shown in FIG.

[0196] 51, the signal transmission device 410 includes a capacitor 440 connected between the first circuit 20 and the second circuit 30. The signal transmission device 410 includes two capacitors 440 corresponding to two signals transmitted between the first circuit 20 and the second circuit 30. When it is necessary to distinguish between the two capacitors 440, they will be described as a first capacitor 440A and a second capacitor 440B.

[0197] The first circuit 20 and the second circuit 30 are connected by a first capacitor 440A and a second capacitor 440B. The signal transmission device 410 is configured to transmit a signal between the first circuit 20 and the second circuit 30 through the first capacitor 440A and the second capacitor 440B.

[0198] The first capacitor 440A and the second capacitor 440B include a first electrode plate 441 and a second electrode plate 442. The first electrode plate 441 is connected to the first circuit 20, and the second electrode plate 442 is connected to the second circuit 30.

[0199] (Insulation chip configuration) 52 is a schematic cross-sectional view of an insulating chip 480 of the fourth embodiment. The insulating chip 480 of the fourth embodiment is mainly different from the insulating chip 80 of the first embodiment in that it includes electrode plates 441, 442. In the following description, the differences from the insulating chip 80 of the first embodiment will be described in detail. Note that the same components as those of the insulating chip 80 of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0200] The insulating chip 480 shown in Fig. 52 is used in place of the insulating chip 80 shown in Fig. 2 and Fig. 3. Therefore, a signal transmission device 410 including the insulating chip 480 of the fourth embodiment is configured to include the first circuit chip 160 and the second circuit chip 170 shown in Fig. 2.

[0201] The insulating tip 480 includes a first conductor 451 and a second conductor 452 . The first conductor 451 includes a first electrode plate 441. In one example, the first electrode plate 441 is formed in an elliptical shape that is long in the X direction in a plan view. The shape of the first electrode plate 441 can be changed arbitrarily. The first electrode plate 441 is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The first electrode plate 441 is electrically connected to the first electrode pad 81 by a first connection wiring 60A.

[0202] The second conductor 452 includes a second electrode plate 442. The second electrode plate 442 faces the first electrode plate 441 in the Z direction. In one example, the second electrode plate 442 is formed in an elliptical shape that is long in the X direction in a plan view. The shape of the second electrode plate 442 can be changed arbitrarily. In one example, the second electrode plate 442 is formed to have the same size as the first electrode plate 441 in a plan view. The second electrode plate 442 may be formed to have a size different from that of the first electrode plate. The second electrode plate 442 is made of a material containing one or more appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The second electrode plate 442 is electrically connected to the second electrode pad 82 by the via wiring 57A.

[0203] (effect) As described above, according to the fourth embodiment, the following effects are achieved. (4-1) The insulating tip 480 of the fourth embodiment has the same effects as the insulating tip 80 of the first embodiment.

[0204] (4-2) The signal transmission device 410 including the insulating tip 480 of the fourth embodiment has the same effects as the signal transmission device 10 including the insulating tip 80 of the first embodiment. (Example of change) The above embodiment can be modified, for example, as follows. The above embodiment and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, the same reference numerals as in the above embodiment are used for the parts common to the above embodiment, and the description thereof will be omitted.

[0205] The number of insulating layers 85 constituting the insulator 84 can be changed as appropriate. FIG. 53 is a schematic cross-sectional view showing the configuration of an insulating tip 580 according to a modified example. The insulator 84 includes a lowermost insulating layer 85L, an uppermost insulating layer 85U, and insulating layers 851-859 between the lowermost insulating layer 85L and the uppermost insulating layer 85U.

[0206] Insulating layers 854, 855, 856, 857, and 858 are interposed between the first conductor 51 and the second conductor 52. The insulating chip 580 has a dielectric strength voltage due to the insulating layers 854 to 858 between the first conductor 51 and the second conductor 52.

[0207] Between the first layer wiring 62A and the second layer wiring 63A, insulating layers 854 to 858 are interposed. Between the first layer wiring 62A and the second layer wiring 63A, a through wiring 561 arranged in a through hole 571 that penetrates the insulating layers 854, 855, and 856, and a through wiring 562 arranged in a through hole 572 that penetrates the insulating layers 857 and 858 are arranged.

[0208] The first layer wiring 62A and the second layer wiring 63A are electrically connected by two through wirings 561, 562 arranged between the first layer wiring 62A and the second layer wiring 63A in the Z direction. In one example, each of the through holes 571, 572 is formed in the same manner as the through hole 71A of the first embodiment. The through holes 571, 572 may be formed in the same manner as the through hole 370 of the third embodiment. In one example, the through wirings 561, 562 are formed in the same manner as the through wiring 64A of the first embodiment. The through wirings 561, 562 may include a first via portion and a second via portion in the same manner as the through wiring 260 of the second embodiment.

[0209] The shape of the electrode pad can be changed as appropriate. FIG. 54 is a schematic cross-sectional view showing a configuration of an insulating tip 680 according to a modified example. The insulating chip 680 includes a first electrode pad 681 and a second electrode pad 682. The first electrode pad 681 and the second electrode pad 682 are formed on the insulating upper surface 84s of the insulator 84. The insulating layer 85U of the insulator 84 has an opening 85U1 that exposes a part of the upper surface of the second layer wiring 63A. The first electrode pad 681 is electrically connected to the second layer wiring 63A by contacting the upper surface of the second layer wiring 63A in the opening 85U1 of the insulating layer 85U. The insulating layer 85U of the insulator 84 has an opening 85U2 that exposes a part of the upper surface of the inner end wiring 52A. The second electrode pad 682 is electrically connected to the inner end wiring 52A by contacting the upper surface of the inner end wiring 52A in the opening 85U2 of the insulating layer 85U.

[0210] The configuration of the signal transmission device may be changed as appropriate. The signal transmission device may be configured to transmit signals between the first circuit chip 160 and the second circuit chip 170 through a plurality of insulating chips.

[0211] FIG. 55 is a schematic cross-sectional view showing a configuration of a signal transmission device 10A according to a modified example. The signal transmission device 10A includes a first circuit chip 160, a second circuit chip 170, and two insulating chips 80A and 80B. In one example, the two insulating chips 80A and 80B have the same configuration as the insulating chip 80. The first circuit chip 160, the first insulating chip 80A, the second insulating chip 80B, and the second circuit chip 170 are arranged apart from each other in the Y direction. The first circuit chip 160, the first insulating chip 80A, the second insulating chip 80B, and the second circuit chip 170 are arranged in the X direction, which is the arrangement direction of the first die pad 111 and the second die pad 121. In the modification example shown in FIG. 55, the first circuit chip 160, the first insulating chip 80A, the second insulating chip 80B, and the second circuit chip 170 are arranged in this order from the first lead terminal 112 toward the second lead terminal 122.

[0212] Both the first circuit chip 160 and the first insulating chip 80A are mounted on a first die pad 111 of a first support member 110. Both the second circuit chip 170 and the second insulating chip 80B are mounted on a second die pad 121 of a second support member 120.

[0213] The first electrode pads 81 of the second insulating chip 80B are electrically connected to the second circuit chip 170 by wires W3. The second electrode pads 82 of the second insulating chip 80B are electrically connected to the second electrode pads 82 of the first insulating chip 80A by wires W5. In other words, the first insulating chip 80A and the second insulating chip 80B are connected in series between the first circuit chip 160 and the second circuit chip 170.

[0214] The second insulating chip 80B has the same configuration as the first insulating chip 80A. Therefore, the second insulating chip 80B has the same dielectric strength voltage as the first insulating chip 80A. The signal transmission device 10A has a dielectric strength voltage according to the dielectric strength voltages of the first insulating chip 80A and the second insulating chip 80B connected in series.

[0215] In the insulating chip 80 of the first embodiment, the through hole 71A and the through wiring 64A may be formed in a rectangular shape in a plan view. In one example, the through hole 71A and the through wiring 64A may be formed in a square shape in a plan view. Similarly, in the insulating chip 280 of the second embodiment, the through hole 71A and the through wiring 260 may be formed in a rectangular shape in a plan view. Moreover, in the insulating chip 380 of the third embodiment, the through hole 370 and the through wiring 360 may be formed in a rectangular shape in a plan view.

[0216] The term "at least one" as used in this disclosure means "one or more" of the desired options. As an example, the term "at least one" as used herein means "only one option" or "both of two options" if the number of options is two. As another example, the term "at least one" as used herein means "only one option" or "any combination of two or more options" if the number of options is three or more.

[0217] The term "on" as used in this disclosure includes both the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. That is, the term "on" does not exclude a structure in which another layer is formed between the first layer and the second layer.

[0218] The Z-axis direction used in the present disclosure does not necessarily have to be a vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to the present disclosure (for example, the structure shown in FIG. 1) are not limited to the "up" and "down" of the Z-axis direction described in this specification being "up" and "down" of the vertical direction. For example, the X-axis direction may be a vertical direction, or the Y-axis direction may be a vertical direction.

[0219] (Additional Note) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding, not for the purpose of limitation, the components described in the appendices are given the reference symbols of the corresponding components in the embodiments. The reference symbols are shown as examples for the purpose of aiding understanding, and the components described in each appendix should not be limited to the components indicated by the reference symbols.

[0220] (Appendix 1) an insulator (84) including an insulating lower surface and an insulating upper surface facing in opposite directions in the thickness direction and constituted by a plurality of insulating layers stacked in the thickness direction; a first conductor (51) disposed within the insulator (84) and toward a lower surface of the insulator; a second conductor (52) disposed within the insulator (84) and adjacent to an upper surface of the insulator and facing the first conductor (51) in the thickness direction; a first electrode pad (81) provided on the insulating upper surface; a connection wiring that electrically connects the first conductor (51) and the first electrode pad (81); Including, The connection wiring (60) is a first layer wiring (62A) disposed within the insulator (84) and adjacent to the lower surface of the insulator; a second layer wiring (63A) disposed in the insulator (84) and close to the upper surface of the insulator and facing the first layer wiring (62A) in the thickness direction; a through-hole wiring (64A) electrically connecting the first layer wiring (62A) and the second layer wiring (63A); Including, the insulator (84) is formed between the first layer wiring (62A) and the second layer wiring (63A) in the thickness direction, and includes a through hole (71A) penetrating two or more of the plurality of insulating layers; the through wiring (64A) is disposed in the through hole (71A), The through hole (71A) has a circular shape when viewed from the thickness direction. Insulated tip.

[0221] (Appendix 2) An aspect ratio, which is a ratio of the depth of the through hole (71A) to the diameter of the bottom surface of the through hole (71A), is 1 or less. 2. The insulated tip of claim 1.

[0222] (Appendix 3) The aspect ratio of the through hole (71A) is 0.5 or less. 2. The insulated tip of claim 2.

[0223] (Appendix 4) The side surface of the through hole (71A) is continuously formed across two or more of the insulating layers. 4. The insulated tip of any one of claims 1 to 3.

[0224] (Appendix 5) The through hole (71A) is formed so that the diameter gradually increases toward the second layer wiring (63A). 5. The insulated tip of any one of claims 1 to 4.

[0225] (Appendix 6) the through hole (370) includes a first portion (371) closer to the first layer wiring (62A) and a second portion (372) closer to the second layer wiring (63A); The second portion (372) is formed so that the diameter gradually increases toward the second layer wiring (63A). 5. The insulated tip of any one of claims 1 to 4.

[0226] (Appendix 7) The first portion is formed so that the diameter gradually increases toward the second layer wiring (63A), A first inclination angle of a side surface of the first portion is greater than a second inclination angle of a side surface of the second portion. 7. The insulated tip of claim 6.

[0227] (Appendix 8) The diameter of the first portion is constant in the thickness direction. 7. The insulated tip of claim 6.

[0228] (Appendix 9) The through hole (71A) is formed through the three insulating layers. 9. The insulated tip of any one of claims 1 to 8.

[0229] (Appendix 10) Four or more of the insulating layers are disposed between the first layer wiring (62A) and the second layer wiring (63A), the first layer wiring (62A) and the second layer wiring (63A) are electrically connected by a plurality of the through wirings (64A) arranged in the thickness direction; 9. The insulated tip of any one of claims 1 to 8.

[0230] (Appendix 11) the first layer wiring (62A) is disposed at the same position as the first conductor (51) in the thickness direction; the second layer wiring (63A) is disposed at the same position as the second conductor (52) in the thickness direction. 11. The insulated tip of any one of claims 1 to 10.

[0231] (Appendix 12) the first layer wiring (62A) is electrically connected to the first conductor (51) by a lead wiring arranged closer to the insulating lower surface than the first layer wiring (62A) and the first conductor (51); 12. The insulated tip of any one of claims 1 to 11.

[0232] (Appendix 13) The first layer wiring (62A) and the second layer wiring (63A) are A frame portion formed in an annular shape when viewed from the thickness direction; A connection portion disposed within the frame portion; Including, 13. The insulated tip of any one of claims 1 to 12.

[0233] (Appendix 14) a second electrode pad provided on the insulating upper surface and electrically connected to the second conductor (52); 14. The insulated tip of any one of claims 1 to 13.

[0234] (Appendix 15) The insulator (84) includes a top insulating layer that forms the insulating upper surface, The second electrode pad is electrically connected to the second conductor (52) by a via wiring that penetrates the uppermost insulating layer. 15. The insulated tip of claim 14.

[0235] (Appendix 16) The insulator (84) includes a top insulating layer that forms the insulating upper surface, the uppermost insulating layer has an opening exposing a portion of the second conductor (52); The second electrode pad is electrically connected to the second conductor (52) through the opening. 15. The insulated tip of claim 14.

[0236] (Appendix 17) The first conductor (51) and the second conductor (52) are spiral coils. 17. The insulated tip of any one of claims 1 to 16.

[0237] (Appendix 18) The first conductor (51) and the second conductor (52) are electrode plates. 17. The insulated tip of any one of claims 1 to 16.

[0238] (Appendix 19) an insulator (84) including an insulating lower surface and an insulating upper surface facing in opposite directions in the thickness direction and constituted by a plurality of insulating layers stacked in the thickness direction; a first conductor (51) disposed within the insulator (84) and toward a lower surface of the insulator; a second conductor (52) disposed within the insulator (84) and adjacent to an upper surface of the insulator and facing the first conductor (51) in the thickness direction; a first electrode pad (81) provided on the insulating upper surface; a connection wiring (60) that electrically connects the first conductor (51) and the first electrode pad (81); Including, The connection wiring (60) is a first layer wiring (62A) disposed within the insulator (84) and adjacent to the lower surface of the insulator; a second layer wiring (63A) disposed in the insulator (84) and close to the upper surface of the insulator and facing the first layer wiring (62A) in the thickness direction; a through-hole wiring (64A) electrically connecting the first layer wiring (62A) and the second layer wiring (63A); Including, the insulator (84) is formed between the first layer wiring (62A) and the second layer wiring (63A) in the thickness direction, the insulator (84) is formed penetrating two or more of the plurality of insulating layers, and includes a through hole (71A) in which the through wiring (64A) is disposed, The through hole (71A) has a rectangular shape when viewed from the thickness direction, the through hole (71A) includes a first portion closer to the first layer wiring (62A) and a second portion closer to the second layer wiring (63A); The second portion is formed such that a side-to-side distance between two side surfaces facing each other in the first direction as viewed from the thickness direction gradually increases from an upper end of the first portion toward the second layer wiring (63A). Insulated tip.

[0239] (Appendix 20) an aspect ratio, which is a ratio of the depth of the through hole (71A) to the length of the bottom surface of the through hole (71A), is 1 or more and 4 or less; 20. The insulated tip of claim 19.

[0240] (Appendix 21) The side surface of the through hole (71A) is continuously formed across two or more of the insulating layers. 21. The insulated tip of claim 19 or 20.

[0241] (Appendix 22) the first portion is formed such that the distance between the side surfaces gradually increases toward the second layer wiring (63A); A first inclination angle of a side surface of the first portion is greater than a second inclination angle of a side surface of the second portion. 22. The insulated tip of any one of claims 19 to 21.

[0242] (Appendix 23) The distance between the side surfaces of the first portion is constant in the thickness direction. 22. The insulated tip of any one of claims 19 to 21.

[0243] (Appendix 24) The through hole (71A) is formed through the three insulating layers. 24. The insulated tip of any one of claims 19 to 23.

[0244] (Appendix 25) Four or more of the insulating layers are disposed between the first layer wiring (62A) and the second layer wiring (63A), the first layer wiring (62A) and the second layer wiring (63A) are electrically connected by a plurality of the through wirings (64A) arranged in the thickness direction; 25. The insulated tip of any one of claims 19 to 24.

[0245] (Appendix 26) the first layer wiring (62A) is disposed at the same position as the first conductor (51) in the thickness direction; the second layer wiring (63A) is disposed at the same position as the second conductor (52) in the thickness direction. 26. The insulated tip of any one of claims 19 to 25.

[0246] (Appendix 27) the first layer wiring (62A) is electrically connected to the first conductor (51) by a lead wiring arranged closer to the insulating lower surface than the first layer wiring (62A) and the first conductor (51); 27. The insulated tip of any one of claims 19 to 26.

[0247] (Appendix 28) The first layer wiring (62A) and the second layer wiring (63A) are A frame portion formed in an annular shape when viewed from the thickness direction; A connection portion disposed within the frame portion; Including, 28. The insulated tip of any one of claims 19 to 27.

[0248] (Appendix 29) a second electrode pad provided on the insulating upper surface and electrically connected to the second conductor (52); 29. The insulated tip of any one of claims 19 to 28.

[0249] (Appendix 30) The insulator (84) includes a top insulating layer that forms the insulating upper surface, The second electrode pad is electrically connected to the second conductor (52) by a via wiring that penetrates the uppermost insulating layer. 29. The insulated tip of claim 29.

[0250] (Appendix 31) The insulator (84) includes a top insulating layer that forms the insulating upper surface, the uppermost insulating layer has an opening exposing a portion of the second conductor (52); The second electrode pad is electrically connected to the second conductor (52) through the opening. 29. The insulated tip of claim 29.

[0251] (Appendix 32) The first conductor (51) and the second conductor (52) are spiral coils. 32. The insulated tip of any one of claims 19 to 31.

[0252] (Appendix 33) The first conductor (51) and the second conductor (52) are electrode plates. 32. The insulated tip of any one of claims 19 to 31.

[0253] (Appendix 34) an insulator (84) including an insulating lower surface and an insulating upper surface facing in opposite directions in the thickness direction and constituted by a plurality of insulating layers stacked in the thickness direction; a first conductor (51) disposed within the insulator (84) and toward a lower surface of the insulator; a second conductor (52) disposed within the insulator (84) and adjacent to an upper surface of the insulator and facing the first conductor (51) in the thickness direction; a first electrode pad (81) provided on the insulating upper surface; a connection wiring (60) that electrically connects the first conductor (51) and the first electrode pad (81); Including, The connection wiring (60) is a first layer wiring (62A) disposed within the insulator (84) and adjacent to the lower surface of the insulator; a second layer wiring (63A) disposed in the insulator (84) and close to the upper surface of the insulator and facing the first layer wiring (62A) in the thickness direction; a through-hole wiring (64A) electrically connecting the first layer wiring (62A) and the second layer wiring (63A); Including, the insulator (84) is formed between the first layer wiring (62A) and the second layer wiring (63A) in the thickness direction, the insulator (84) is formed penetrating two or more of the plurality of insulating layers, and includes a through hole (71A) in which the through wiring (64A) is disposed, The through hole (71A) has a rectangular shape when viewed from the thickness direction, side surfaces of the through hole (71A), as viewed in the thickness direction, are formed such that a side-to-side distance between two side surfaces facing each other in a first direction gradually increases from the first layer wiring (62A) toward the second layer wiring (63A); The through wiring (64A) is a first via portion having a via recess covering a bottom surface and a side surface of the through hole (71A) and including a recess bottom surface smaller than the bottom surface of the through hole (71A) and a recess side surface formed at an inclination angle smaller than the inclination angle of the side surface constituting the through hole (71A); a second via portion embedded in the via recess of the first via portion; Including, Insulated tip.

[0254] (Appendix 35) The first via portion and the second via portion are formed of the same material. 35. The insulated tip of claim 34.

[0255] (Appendix 36) The first via portion and the second via portion are formed of different materials. 35. The insulated tip of claim 34.

[0256] (Appendix 37) an aspect ratio, which is a ratio of the depth of the through hole (71A) to the length of the bottom surface of the through hole (71A), is 1 or more and 4 or less; 37. The insulated tip of any one of claims 34 to 36.

[0257] (Appendix 38) The side surface of the through hole (71A) is continuously formed across two or more of the insulating layers. 38. The insulated tip of any one of claims 34 to 37.

[0258] (Appendix 39) The through hole (71A) is formed through the three insulating layers. 39. The insulated tip of any one of claims 34 to 38.

[0259] (Appendix 40) Four or more of the insulating layers are disposed between the first layer wiring (62A) and the second layer wiring (63A), the first layer wiring (62A) and the second layer wiring (63A) are electrically connected by a plurality of the through wirings (64A) arranged in the thickness direction; 39. The insulated tip of any one of claims 34 to 38.

[0260] (Appendix 41) the first layer wiring (62A) is disposed at the same position as the first conductor (51) in the thickness direction; the second layer wiring (63A) is disposed at the same position as the second conductor (52) in the thickness direction. 41. The insulated tip of any one of claims 34 to 40.

[0261] (Appendix 42) the first layer wiring (62A) is electrically connected to the first conductor (51) by a lead wiring arranged closer to the insulating lower surface than the first layer wiring (62A) and the first conductor (51); 42. The insulated tip of any one of claims 34 to 41.

[0262] (Appendix 43) The first layer wiring (62A) and the second layer wiring (63A) are A frame portion formed in an annular shape when viewed from the thickness direction; a connection portion disposed within the frame portion and formed by wirings perpendicular to each other when viewed from the thickness direction; Including, 43. The insulated tip of any one of claims 34 to 42.

[0263] (Appendix 44) a second electrode pad provided on the insulating upper surface and electrically connected to the second conductor (52); 44. The insulated tip of any one of claims 34 to 43.

[0264] (Appendix 45) The insulator (84) includes a top insulating layer that forms the insulating upper surface, The second electrode pad is electrically connected to the second conductor (52) by a via wiring that penetrates the uppermost insulating layer. 45. The insulated tip of claim 44.

[0265] (Appendix 46) The insulator (84) includes a top insulating layer that forms the insulating upper surface, the uppermost insulating layer has an opening exposing a portion of the second conductor (52); The second electrode pad is electrically connected to the second conductor (52) through the opening. 45. The insulated tip of claim 44.

[0266] (Appendix 47) The first conductor (51) and the second conductor (52) are spiral coils. 47. The insulated tip of any one of claims 34 to 46.

[0267] (Appendix 48) The first conductor (51) and the second conductor (52) are electrode plates. 47. The insulated tip of any one of claims 34 to 46.

[0268] (Appendix 49) an insulating chip including a first conductor (51) and a second conductor (52); a first die pad on which the insulating chip is mounted; a sealing resin that seals the insulating chip and the first die pad; A signal transmission device comprising:

[0269] (Appendix 50) a first circuit chip mounted on the first die pad; the first circuit chip includes a first circuit electrically connected to the first conductor (51); 50. The signal transmission device of claim 49.

[0270] (Appendix 51) a second die pad disposed apart from the first die pad; a second circuit chip mounted on the second die pad; Including, the second circuit chip includes a second circuit electrically connected to the second conductor (52); 51. A signal transmission device according to claim 49 or 50.

[0271] (Appendix 52) forming a first insulating layer; forming a first conductor (51) and a first layer wiring (62A) on the first insulating layer; forming a plurality of second insulating layers on the first insulating layer to cover the first conductor (51) and the first layer wiring (62A); forming through holes (71A) penetrating the plurality of second insulating layers; forming a through-wire (64A) in the through-hole (71A); forming a third insulating layer on the second insulating layer to cover the through wiring (64A); forming, in the third insulating layer, a second conductor (52) facing the first conductor (51) and a second layer wiring (63A) facing the first layer wiring (62A) in a thickness direction of the plurality of second insulating layers; Including, The through hole (71A) has a circular shape when viewed from the thickness direction. A method for manufacturing an insulating tip.

[0272] (Appendix 53) An aspect ratio, which is a ratio of the depth of the through hole (71A) to the diameter of the bottom surface of the through hole (71A), is 1 or less. 53. A method for producing an insulating tip according to claim 52.

[0273] (Appendix 54) The aspect ratio of the through hole (71A) is 0.5 or less. 54. A method for producing an insulating tip according to claim 53.

[0274] (Appendix 55) forming a first insulating layer; forming a first conductor (51) and a first layer wiring (62A) on the first insulating layer; forming a plurality of second insulating layers on the first insulating layer to cover the first conductor (51) and the first layer wiring (62A); forming through holes (71A) penetrating the plurality of second insulating layers; forming a through-wire (64A) in the through-hole (71A); forming a third insulating layer on the second insulating layer to cover the through wiring (64A); forming, in the third insulating layer, a second conductor (52) facing the first conductor (51) and a second layer wiring (63A) facing the first layer wiring (62A) in a thickness direction of the plurality of second insulating layers; Including, the through hole (71A) includes a first portion closer to the first layer wiring (62A) and a second portion closer to the second layer wiring (63A); The second portion is formed such that a side-to-side distance between two side surfaces facing each other in the first direction as viewed from the thickness direction gradually increases from an upper end of the first portion toward the second layer wiring (63A). A method for manufacturing an insulating tip.

[0275] (Appendix 56) the first portion is formed such that a distance between side surfaces in a first direction perpendicular to the thickness direction gradually increases toward the second layer wiring (63A); A first inclination angle of a side surface of the first portion is greater than a second inclination angle of a side surface of the second portion. 55. A method for producing an insulating tip according to claim 54.

[0276] (Appendix 57) The first portion has a constant distance between side surfaces in a first direction perpendicular to the thickness direction. 56. A method for producing an insulating tip according to claim 55.

[0277] (Appendix 58) The through hole (71A) has a circular shape when viewed from the thickness direction. 58. A method for producing an insulating chip according to any one of claims 55 to 57.

[0278] (Appendix 59) The through hole (71A) has a rectangular shape when viewed from the thickness direction. 58. A method for producing an insulating chip according to any one of claims 55 to 57.

[0279] (Appendix 60) forming a first insulating layer; forming a first conductor (51) and a first layer wiring (62A) on the first insulating layer; forming a plurality of second insulating layers on the first insulating layer to cover the first conductor (51) and the first layer wiring (62A); forming a through hole (71A) that penetrates the plurality of second insulating layers and includes a bottom surface at which a portion of the first layer wiring (62A) is exposed and a side surface that is continuously formed on the plurality of second insulating layers; forming a through wiring (64A) including a first via portion having a via recess including a recess bottom surface smaller than a bottom surface of the through hole (71A) and a recess side surface formed at an inclination angle smaller than an inclination angle of a side surface constituting the through hole (71A), and a second via portion embedded in the via recess of the first via portion; forming a third insulating layer on the second insulating layer to cover the through wiring (64A); forming, in the third insulating layer, a second conductor (52) facing the first conductor (51) and a second layer wiring (63A) facing the first layer wiring (62A) in a thickness direction of the plurality of second insulating layers; Including, A method for manufacturing an insulating tip.

[0280] (Appendix 61) forming a first conductive film covering a bottom surface of the through hole (71A), a side surface of the through hole (71A), and an upper surface of a topmost second insulating layer of the plurality of second insulating layers; forming the first via portion by partially removing the first conductive film; Including, 61. A method for producing an insulating tip according to claim 60.

[0281] (Appendix 62) forming a second conductive film covering a bottom surface of the via recess, a side surface of the via recess, and an upper surface of a topmost second insulating layer of the plurality of second insulating layers; forming the second via portion by partially removing the second conductive film; Including, 62. A method for producing an insulating tip according to claim 61.

[0282] (Appendix 63) The through hole (71A) has a circular shape when viewed from the thickness direction. 63. A method for producing an insulating chip according to any one of claims 60 to 62.

[0283] (Appendix 64) The through hole (71A) has a rectangular shape when viewed from the thickness direction. 63. A method for producing an insulating chip according to any one of claims 60 to 62.

[0284] The above description is merely illustrative. Those skilled in the art may recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of describing the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and alterations that fall within the scope of the present disclosure, including the scope of the claims. [Explanation of symbols]

[0285] 10,10A Signal transmission device 20 1st circuit 30 2nd circuit 40 Trans 40A transformer 40B transformer 41 First coil 42 Second coil 51 First conductor 52 Second Conductor 55 Dummy Pattern 57A, 57B Via wiring 60 Connection Wiring 60A 1st connection wire 60B Second connection wiring 61A 1st wiring section 61B 1st wiring section 62A 1st layer wiring 62As top surface 62B 1st layer wiring 63A 2nd layer wiring 63B 2nd layer wiring 64A through wiring 64A1 First through wiring 64A2 2nd through wiring 64As top surface 64B through wiring 65A 2nd wiring section 65B 2nd wiring section 66A pull-out wiring 66B Pull-out wiring 67A via wiring 67B Via wiring 68A via wiring 68B Via wiring 69 Via Wiring 71A Through hole 71A1 1st through hole 71A2 2nd through hole 71AB Void 71B Through hole 80 Insulated Tip 80A 1st Insulation Tip 80A Insulated Tip 80B 2nd Insulation Tip 80B Insulation Tip 80r Chip back 80s chip main surface 81 First electrode pad 81A 1st Pad 81B 2nd Pad 82 Second electrode pad 82A 3rd Pad 82B 4th Pad 83 Substrate 83r Bottom side of board 83s board top surface 84 Insulators 84r Insulated bottom 84s Insulated top 85 Insulating Layer 85A First Insulation Layer 85B Second insulating layer 85L insulation layer 85U Insulation layer 851~859 Insulation layer 91 Passivation Film 92 Resin layer 924 First resin opening 925 Second resin opening 110 First support member 111 First die pad 112 First lead terminal 120 Second support member 121 Second die pad 122 Second lead terminal 130 Sealing resin 160 First Circuit Chip 170 Second Circuit Chip 260 Through Wiring 261 First Via Section 262 Bottom 263 Via recess 264 Bottom of recess 265 Recessed side 267 2nd Via Section 280 Insulated Tip 360 Through Wiring 361 Part 1 362 Part 2 370 Through hole 370A 1st through hole 371 Part 1 372 Part 2 380 Insulated Tip 410 Signal transmission device 440 Capacitor 440A 1st Capacitor 440B Second Capacitor 441 Electrode plate 441 1st electrode plate 442 Electrode plate 442 Second electrode plate 451 First Conductor 452 Second Conductor 480 Insulated Tip 561 Through Wiring 562 Through Wiring 571 Through hole 572 Through hole 580 Insulated Tip 621 Frame 622 Connection 680 Insulated Tip 681 First electrode pad 682 Second electrode pad 711 Bottom 712 Side 713 Opening 957 Insulation Layer 1901 Conductive layer 1902 Conductive layer 1911 First conductive layer 1911X part 1912 Second conductive layer 1921 Conductive layer θ1, θ2 Tilt angle D1,D2 diameter θ31, θ32 Inclination angle D21,D31,D32 Diameter H1,H21 Depth WL1,WL2 width

Claims

1. an insulator including an insulating lower surface and an insulating upper surface facing in opposite directions in a thickness direction, the insulator being composed of a plurality of insulating layers stacked in the thickness direction; A first conductor disposed within the insulator and proximate a lower surface of the insulator; a second conductor disposed within the insulator and closer to an upper surface of the insulator, the second conductor facing the first conductor in the thickness direction; a first electrode pad provided on the insulating upper surface; a connection wiring that electrically connects the first conductor and the first electrode pad; Including, The connection wiring is a first layer wiring disposed within the insulator and close to a lower surface of the insulator; a second layer wiring disposed within the insulator and close to an upper surface of the insulator, the second layer wiring facing the first layer wiring in the thickness direction; a through wiring electrically connecting the first layer wiring and the second layer wiring; Including, the insulator includes a through hole formed between the first layer wiring and the second layer wiring in the thickness direction and penetrating two or more of the plurality of insulating layers; the through wiring is disposed in the through hole, The through hole has a circular shape when viewed from the thickness direction. Insulated tip.

2. An aspect ratio, which is a ratio of the depth of the through hole to the diameter of the bottom surface of the through hole, is 1 or less. The insulating tip of claim 1 .

3. The aspect ratio of the through hole is 0.5 or less. The insulating tip of claim 2.

4. a side surface of the through hole is continuously formed across two or more of the insulating layers; The insulating tip of claim 1 .

5. The through hole is formed so that the diameter gradually increases toward the second layer wiring. The insulating tip of claim 1 .

6. the through hole includes a first portion closer to the first layer wiring and a second portion closer to the second layer wiring, the second portion is formed so as to have a gradually increasing diameter toward the second layer wiring; The insulating tip of claim 1 .

7. the first portion is formed so as to have a gradually increasing diameter toward the second layer wiring, A first inclination angle of a side surface of the first portion is greater than a second inclination angle of a side surface of the second portion. The insulating tip of claim 6.

8. The through hole is formed through the three insulating layers. The insulating tip of claim 1 .

9. four or more of the insulating layers are disposed between the first layer wiring and the second layer wiring; the first layer wiring and the second layer wiring are electrically connected to each other by a plurality of the through wirings arranged in the thickness direction; The insulating tip of claim 1 .

10. the first layer wiring is disposed at the same position as the first conductor in the thickness direction; the second layer wiring is disposed at the same position as the second conductor in the thickness direction; The insulating tip of claim 1 .

11. the first layer wiring is electrically connected to the first conductor by a lead wiring disposed closer to the insulating lower surface than the first layer wiring and the first conductor; The insulating tip of claim 1 .

12. The first layer wiring and the second layer wiring are A frame portion formed in an annular shape when viewed from the thickness direction; a connection portion disposed within the frame portion and formed by wirings perpendicular to each other when viewed from the thickness direction; Including, The insulating tip of claim 1 .

13. a second electrode pad provided on the insulating upper surface and electrically connected to the second conductor; The insulating tip of claim 1 .

14. the insulator includes a top insulating layer that constitutes the insulating upper surface, the second electrode pad is electrically connected to the second conductor by a via wiring that penetrates the uppermost insulating layer; 14. The insulating tip of claim 13.

15. the insulator includes a top insulating layer that constitutes the insulating upper surface, the uppermost insulating layer has an opening exposing a portion of the second conductor; the second electrode pad is electrically connected to the second conductor through the opening; 14. The insulating tip of claim 13.

16. The first conductor and the second conductor are spiral coils. The insulating tip of claim 1 .

17. The first conductor and the second conductor are electrode plates. The insulating tip of claim 1 .

18. an insulator including an insulating lower surface and an insulating upper surface facing in opposite directions in a thickness direction, the insulator being composed of a plurality of insulating layers stacked in the thickness direction; A first conductor disposed within the insulator and proximate a lower surface of the insulator; a second conductor disposed within the insulator and closer to an upper surface of the insulator, the second conductor facing the first conductor in the thickness direction; a first electrode pad provided on the insulating upper surface; a connection wiring that electrically connects the first conductor and the first electrode pad; Including, The connection wiring is a first layer wiring disposed within the insulator and close to a lower surface of the insulator; a second layer wiring disposed within the insulator and close to an upper surface of the insulator, the second layer wiring facing the first layer wiring in the thickness direction; a through wiring electrically connecting the first layer wiring and the second layer wiring; Including, the insulator is formed between the first layer wiring and the second layer wiring in the thickness direction, the insulator is formed to penetrate two or more of the plurality of insulating layers, and includes a through hole in which the through wiring is disposed, The through hole has a rectangular shape when viewed from the thickness direction, the through hole includes a first portion closer to the first layer wiring and a second portion closer to the second layer wiring, the second portion is formed such that a side-to-side distance between two side surfaces facing each other in the first direction as viewed in the thickness direction gradually increases from an upper end of the first portion toward the second layer wiring. Insulated tip.

19. an insulator including an insulating lower surface and an insulating upper surface facing in opposite directions in a thickness direction, the insulator being composed of a plurality of insulating layers stacked in the thickness direction; A first conductor disposed within the insulator and proximate a lower surface of the insulator; a second conductor disposed within the insulator and closer to an upper surface of the insulator, the second conductor facing the first conductor in the thickness direction; a first electrode pad provided on the insulating upper surface; a connection wiring that electrically connects the first conductor and the first electrode pad; Including, The connection wiring is a first layer wiring disposed within the insulator and close to a lower surface of the insulator; a second layer wiring disposed within the insulator and close to an upper surface of the insulator, the second layer wiring facing the first layer wiring in the thickness direction; a through wiring electrically connecting the first layer wiring and the second layer wiring; Including, the insulator is formed between the first layer wiring and the second layer wiring in the thickness direction, the insulator is formed to penetrate two or more of the plurality of insulating layers, and includes a through hole in which the through wiring is disposed, The through hole has a rectangular shape when viewed from the thickness direction, the side surfaces of the through hole are formed such that, as viewed from the thickness direction, a side-to-side distance between two side surfaces facing each other in a first direction gradually increases from the first layer wiring toward the second layer wiring, The through wiring is a first via portion having a via recess covering a bottom surface and a side surface of the through hole, the via recess including a bottom surface of the recess smaller than the bottom surface of the through hole and a side surface of the recess formed at an inclination angle smaller than an inclination angle of the side surface constituting the through hole; a second via portion embedded in the via recess of the first via portion; Including, Insulated tip.

20. An insulating tip according to any one of claims 1 to 19; a first die pad on which the insulating chip is mounted; a sealing resin that seals the insulating chip and the first die pad; A signal transmission device comprising:

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