Semiconductor module and manufacturing method of the semiconductor module
By using a three-layer sealing resin structure with increasing hardness in the semiconductor module, the balance problem between watertightness and insulation is solved, and higher watertightness and insulation are achieved, while reducing cracks and bubbles caused by thermal stress.
Patent Information
- Application Number
- JP2023117058
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-07-18
- Publication Date
- 2025-01-30
AI Technical Summary
The prior art is difficult to prevent insulation damage of semiconductor modules while improving watertightness.
A three-layer sealing resin structure is adopted, including the first, second and third sealing layers with increasing hardness, which are composed of different materials respectively to ensure that the hardness, watertightness and thermal expansion rate of the sealing resin decrease layer by layer and prevent damage to the insulating layer.
Through the three-layer sealing resin structure, the watertightness and insulation of the semiconductor module are improved, the damage of the insulating layer is prevented, and cracks and bubbles caused by thermal stress are reduced.
Smart Images
Figure 2025014476000001_ABST
Abstract
Description
[Technical field]
[0001] The present invention relates to a semiconductor module and a method for manufacturing the semiconductor module. [Background technology]
[0002] Patent Document 1 describes a semiconductor module provided with "a second sealing material 8 containing a resin composition according to the first embodiment in an aspect of covering a first sealing material 7," Patent Document 2 describes a semiconductor module having a configuration in which "a protective layer 21 is provided in contact with a sealing layer 20," and Patent Document 3 describes a semiconductor module including a second resin 44 that is relatively softer than a first resin 42, and a third resin 46 that is relatively harder than the second resin 44. [Prior art document] [Patent documents] [Patent Document 1] JP 2017-171714 A [Patent Document 2] JP 2022-148684 A [Patent Document 3] JP 2022-64191 A Summary of the Invention [Problem to be solved by the invention]
[0003] It is desirable to improve waterproofing while preventing dielectric breakdown of a semiconductor module. [Means for solving the problem]
[0004] In a first aspect of the present invention, a semiconductor module is provided, comprising: a laminated substrate; a plurality of semiconductor chips provided on the laminated substrate; bonding wires connected to the plurality of semiconductor chips; a housing accommodating the plurality of semiconductor chips, the bonding wires and the laminated substrate; and inside the housing, a first sealing layer covering the plurality of semiconductor chips, the bonding wires and the laminated substrate; a second sealing layer provided above the first sealing layer; and a third sealing layer provided above the second sealing layer, wherein the first sealing layer is filled inside the housing to a position higher than the upper surface of the bonding wires, and the hardness of the second sealing layer is greater than the hardness of the first sealing layer and less than the hardness of the third sealing layer.
[0005] In the above semiconductor module, the distance between an upper end of the first sealing layer and an upper end of the bonding wire may be 0.5 mm or more and 1.5 mm or less.
[0006] In any of the semiconductor modules described above, the first sealing layer may have a thickness of 3.5 mm or more and 4.5 mm or less.
[0007] In any of the semiconductor modules described above, the first sealing layer may include a silicone gel material or a fluorine gel material.
[0008] In any of the semiconductor modules described above, the second encapsulating layer may include a silicone elastomer material.
[0009] In any of the semiconductor modules described above, a thickness of the second encapsulating layer may be smaller than a thickness of the first encapsulating layer.
[0010] In any of the semiconductor modules described above, the third sealing layer may include a silicone gel material.
[0011] In any of the semiconductor modules described above, a thickness of the third encapsulating layer may be smaller than a thickness of the first encapsulating layer.
[0012] In any of the semiconductor modules described above, a thickness of the third sealing layer may be the same as a thickness of the second sealing layer.
[0013] In any of the semiconductor modules described above, a coefficient of thermal expansion of the second sealing layer may be smaller than a coefficient of thermal expansion of the first sealing layer and may be larger than a coefficient of thermal expansion of the third sealing layer.
[0014] Any of the semiconductor modules described above may further include a primer layer provided between the first sealing layer and the plurality of semiconductor chips, the bonding wires, and the laminated substrate.
[0015] In a second aspect of the present invention, a method for manufacturing a semiconductor module is provided, the method including the steps of providing a laminated substrate, providing a plurality of semiconductor chips on the laminated substrate, connecting bonding wires to the plurality of semiconductor chips, accommodating the plurality of semiconductor chips, the bonding wires and the laminated substrate inside a housing, filling a first sealing layer inside the housing so as to cover the plurality of semiconductor chips, the bonding wires and the laminated substrate, filling a second sealing layer so as to cover above the first sealing layer, and filling a third sealing layer so as to cover above the second sealing layer, wherein the first sealing layer is filled inside the housing to a position higher than the upper surface of the bonding wires, and the hardness of the second sealing layer is greater than the hardness of the first sealing layer and less than the hardness of the third sealing layer.
[0016] In the above-mentioned semiconductor module manufacturing method, the method may include a first annealing step for hardening the first sealing layer after the step of filling the first sealing layer and before the step of filling the second sealing layer, a second annealing step for hardening the second sealing layer after the step of filling the second sealing layer and before the step of filling the third sealing layer, and a third annealing step for hardening the third sealing layer after the step of filling the third sealing layer.
[0017] The above summary of the invention does not list all of the features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]
[0018] [Figure 1A] 1 shows an example of a top view of a semiconductor chip 100 according to a first embodiment. [Figure 1B] 1 shows an example of a top view of a semiconductor chip 100. [Figure 1C] 1C shows an example of a cross section taken along line aa' in FIG. 1B. [Diagram 2] 2 shows an example of the configuration of a semiconductor module 200. [Figure 3A] An example of a method for manufacturing the semiconductor module 200 will be described. [Figure 3B] An example of the step of filling the sealing resin 220 is shown. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0019] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.
[0020] In this specification, one side in the thickness direction of the semiconductor chip 100 is referred to as "upper" and the other side as "lower". Of the two main surfaces of an element, substrate, layer, film or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity. In this example, the up-down direction is referred to as the Z-axis direction, and two directions perpendicular to the plane perpendicular to the Z-axis direction are referred to as the X-axis direction and the Y-axis direction. The XYZ axes form a right-handed system. A top view refers to a case where the semiconductor chip 100 is viewed from the positive direction of the Z axis.
[0021] In each embodiment, the first conductivity type is N type and the second conductivity type is P type, but the first conductivity type may be P type and the second conductivity type may be N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment are reversed. In layers and regions marked with N or P, electrons or holes are the majority carriers, respectively. In addition, + and - attached to N and P respectively mean that the doping concentration is higher and lower than that of layers or regions not marked with them.
[0022] 1A illustrates an example of a top view of a semiconductor chip 100 according to a first embodiment. The semiconductor chip 100 includes a transistor section 70 and a diode section 80.
[0023] The transistor section 70 includes a transistor such as an IGBT (Insulated Gate Bipolar Transistor). The diode section 80 includes a diode such as a free wheel diode (FWD). The semiconductor chip 100 of this example is a reverse conducting IGBT (RC-IGBT) having the transistor section 70 and the diode section 80 on the same chip.
[0024] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. In this example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an active region 110 and a peripheral region 120.
[0025] The transistor section 70 is a region obtained by projecting a collector region provided on the lower surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region has the second conductivity type. For example, the collector region is a P+ type.
[0026] The diode section 80 is a region obtained by projecting a cathode region provided on the lower surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region has a first conductivity type. In this example, the cathode region is, for example, an N+ type.
[0027] The transistor sections 70 and the diode sections 80 may be alternately and periodically arranged in the XY plane. The transistor sections 70 and the diode sections 80 in this example include a plurality of transistor sections and a plurality of diode sections. In a region between the transistor sections 70 and the diode sections 80, a gate metal layer 50 may be provided above the semiconductor substrate 10.
[0028] In addition, the transistor section 70 and the diode section 80 of this example have trench sections extending in the Y-axis direction. However, the transistor section 70 and the diode section 80 may have trench sections extending in the X-axis direction.
[0029] The active region 110 has a transistor section 70 and a diode section 80. The active region 110 is a region where a main current flows between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor chip 100 is controlled to be in an on-state. That is, the active region 110 is a region where a current flows in the depth direction inside the semiconductor substrate 10 from the upper surface to the lower surface or from the lower surface to the upper surface of the semiconductor substrate 10. In this specification, the transistor section 70 and the diode section 80 are referred to as an element section or an element region, respectively.
[0030] In addition, when viewed from above, the region sandwiched between the two element portions is also defined as the active region 110. In this example, the active region 110 also includes the region sandwiched between the element portions and in which the gate metal layer 50 is provided.
[0031] The gate metal layer 50 is formed of a material containing a metal. For example, the gate metal layer 50 is formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The gate metal layer 50 is electrically connected to the gate conductive portion of the transistor portion 70 and supplies a gate voltage to the transistor portion 70. The gate metal layer 50 is provided so as to surround the periphery of the active region 110 in a top view. The gate metal layer 50 is electrically connected to a gate pad 130 provided in the peripheral region 120. The gate metal layer 50 may be provided along the peripheral edge of the semiconductor substrate 10. The gate metal layer 50 may also be provided between the transistor portion 70 and the diode portion 80 in a top view.
[0032] The peripheral region 120 is a region between the active region 110 and the peripheral edge of the semiconductor substrate 10 in a top view. The peripheral region 120 is provided to surround the active region 110 in a top view. One or more metal pads for connecting the semiconductor chip 100 to an external device with a wire or the like may be arranged in the peripheral region 120. The peripheral region 120 may have an edge termination structure. The edge termination structure relieves electric field concentration on the top surface side of the semiconductor substrate 10. For example, the edge termination structure has a guard ring, a field plate, a resurf, or a structure that combines these.
[0033] The gate pad 130 is electrically connected to the gate conductive portion of the transistor section 70 via the gate metal layer 50. The gate pad 130 is set to a gate potential. The gate pad 130 in this example has a rectangular shape when viewed from above.
[0034] 1B shows an example of a top view of semiconductor chip 100. In this example, a close-up view of the edge of active area 110 is shown.
[0035] The transistor section 70 is a region obtained by projecting the collector region 22 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 has a second conductivity type. In this example, the collector region 22 is a P+ type, for example. The transistor section 70 includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80.
[0036] The diode portion 80 is a region obtained by projecting a cathode region 82 provided on the back surface side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. In this example, the cathode region 82 is, for example, an N+ type.
[0037] The semiconductor chip 100 of this example includes, on the front surface of the semiconductor substrate 10, a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17. The semiconductor chip 100 of this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface of the semiconductor substrate 10.
[0038] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. The gate metal layer 50 is provided above the gate trench portion 40 and the well region 17. The emitter electrode 52 in this example is set to the emitter potential of the transistor portion 70. The emitter electrode 52 is an example of a front surface electrode that is provided above the semiconductor substrate 10 and is electrically connected to the transistor portion 70 and the diode portion 80.
[0039] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. For example, at least a portion of the emitter electrode 52 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 may have a barrier metal formed of titanium, a titanium compound, or the like under the region formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.
[0040] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with an interlayer insulating film 38 therebetween. The interlayer insulating film 38 is omitted in Fig. 1B. A contact hole 54, a contact hole 55, and a contact hole 56 are provided penetrating the interlayer insulating film 38.
[0041] The contact hole 55 connects the gate metal layer 50 and a gate conductive portion in the transistor portion 70. Inside the contact hole 55, a plug made of tungsten or the like may be formed.
[0042] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a plug made of tungsten or the like may be formed.
[0043] The connection portion 25 electrically connects the emitter electrode 52 or the gate metal layer 50, etc., to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with impurities. Here, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is provided above the front surface of the semiconductor substrate 10 via an insulating film such as an oxide film, etc.
[0044] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). The gate trench portions 40 in this example may have two extension portions 41 extending along an extension direction (the Y-axis direction in this example) parallel to the front surface of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 connecting the two extension portions 41.
[0045] It is preferable that at least a portion of the connection portion 43 is formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, it is possible to alleviate electric field concentration at the ends of the extension portions 41. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 may be connected to the gate conductive portion.
[0046] The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. The dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example) similarly to the gate trench portions 40. The dummy trench portions 30 in this example may have a U-shape on the front surface of the semiconductor substrate 10 similarly to the gate trench portions 40. That is, the dummy trench portion 30 may have two extension portions 31 extending along the extension direction and a connection portion 33 connecting the two extension portions 31.
[0047] The transistor section 70 of this example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 of this example has the gate trench sections 40 and the dummy trench sections 30 in a ratio of 2:3. For example, the transistor section 70 has one extension section 31 between two extension sections 41. The transistor section 70 also has two extension sections 31 adjacent to the gate trench section 40.
[0048] However, the ratio of the gate trench portions 40 to the dummy trench portions 30 is not limited to this example. The ratio of the gate trench portions 40 to the dummy trench portions 30 may be 1:1 or 2:4. Also, the transistor portion 70 may not include the dummy trench portions 30, and may be entirely made up of gate trench portions 40.
[0049] The well region 17 is a second conductive type region provided on the front surface side of the semiconductor substrate 10 relative to the drift region 18 described later. The well region 17 is an example of a well region provided on the edge side of the semiconductor chip 100. The well region 17 is, for example, a P+ type. The well region 17 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. Part of the regions of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side are formed in the well region 17. The bottoms of the ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction may be covered by the well region 17.
[0050] The contact holes 54 are formed above the emitter region 12 and the contact region 15 in the transistor section 70. The contact holes 54 are also provided above the base region 14 in the diode section 80. The contact holes 54 are provided above the contact region 15 in the boundary section 90. The contact holes 54 are provided above the base region 14 in the diode section 80. None of the contact holes 54 are provided above the well regions 17 provided at both ends in the Y-axis direction. In this manner, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the extension direction.
[0051] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact region 15. The boundary portion 90 in this example does not have an emitter region 12. In one example, the trench portion of the boundary portion 90 is a dummy trench portion 30. The boundary portion 90 in this example is arranged so that both ends in the X-axis direction are dummy trench portions 30.
[0052] The mesa portion 71, the mesa portion 91, and the mesa portion 81 are mesa portions provided adjacent to the trench portion in a plane parallel to the front surface of the semiconductor substrate 10. The mesa portion is a portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and may be a portion from the front surface of the semiconductor substrate 10 to the deepest bottom of each trench portion. The extension portion of each trench portion may be one trench portion. In other words, the region sandwiched between the two extension portions may be a mesa portion.
[0053] The mesa portion 71 is provided in the transistor portion 70 adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40. The mesa portion 71 has a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front surface of the semiconductor substrate 10. In the mesa portion 71, the emitter regions 12 and the contact regions 15 are provided alternately in the extension direction.
[0054] The mesa portion 91 is provided in the boundary portion 90. The mesa portion 91 has a contact region 15 and a well region 17 on the front surface of the semiconductor substrate 10.
[0055] The mesa portion 81 is provided in a region of the diode portion 80 that is sandwiched between adjacent dummy trench portions 30. The mesa portion 81 has a base region 14, a contact region 15, and a well region 17 on the front surface of the semiconductor substrate 10.
[0056] The base region 14 is a second conductivity type region provided on the front surface side of the semiconductor substrate 10 in the transistor portion 70 and the diode portion 80. The base region 14 is a P-type, for example. The base region 14 may be provided on both ends in the Y-axis direction of the mesa portion 71 and the mesa portion 91 on the front surface of the semiconductor substrate 10. Note that FIG. 1B shows only one end of the base region 14 in the Y-axis direction.
[0057] The emitter region 12 is a region of a first conductivity type having a higher doping concentration than the drift region 18. In this example, the emitter region 12 is, for example, an N+ type. An example of a dopant for the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface of the mesa portion 71 in contact with the gate trench portion 40. The emitter region 12 may be provided extending in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 to the other. The emitter region 12 is also provided below the contact hole 54.
[0058] Moreover, the emitter region 12 may or may not be in contact with the dummy trench portion 30. The emitter region 12 in this example is in contact with the dummy trench portion 30. The emitter region 12 does not need to be provided in the mesa portion 91 of the boundary portion 90.
[0059] The contact region 15 is a region of a second conductivity type having a higher doping concentration than the base region 14. The contact region 15 in this example is, for example, a P+ type. The contact region 15 in this example is provided on the front surface of the mesa portion 71 and the mesa portion 91. The contact region 15 may be provided in the X-axis direction from one of the two trench portions sandwiching the mesa portion 71 or the mesa portion 91 to the other. The contact region 15 may or may not be in contact with the gate trench portion 40. In addition, the contact region 15 may or may not be in contact with the dummy trench portion 30. In this example, the contact region 15 is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54. The contact region 15 may also be provided in the mesa portion 81.
[0060] Fig. 1C is a diagram showing an example of the a-a' cross section in Fig. 1B. The a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor section 70. In the a-a' cross section, the semiconductor chip 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.
[0061] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. In this example, the drift region 18 is, for example, an N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doped regions being formed therein. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.
[0062] The buffer region 20 is a region of a first conductivity type provided below the drift region 18. In this example, the buffer region 20 is, for example, an N-type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents a depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.
[0063] The collector region 22 is provided below the buffer region 20 in the transistor section 70. The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80.
[0064] The collector electrode 24 is formed on the rear surface 23 of the semiconductor substrate 10. The collector electrode 24 is made of a conductive material such as a metal.
[0065] The base region 14 is a second conductivity type region provided above the drift region 18 in the mesa portion 71, the mesa portion 91, and the mesa portion 81. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.
[0066] The emitter region 12 is provided between the base region 14 and the front surface 21 in the mesa portion 71. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. The emitter region 12 does not have to be provided in the mesa portion 91.
[0067] The contact region 15 is provided above the base region 14 in the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In another cross section, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.
[0068] The accumulation region 16 is a region of a first conductivity type provided closer to the front surface 21 of the semiconductor substrate 10 than the drift region 18. The accumulation region 16 in this example is an N+ type, for example. The accumulation region 16 is provided in the transistor section 70 and the diode section 80. The accumulation region 16 in this example is also provided in the boundary section 90. This allows the semiconductor chip 100 to avoid mask misalignment of the accumulation region 16.
[0069] Moreover, the accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.
[0070] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In a region where at least one of the emitter region 12, the base region 14, the contact region 15, and the accumulation region 16 is provided, each trench portion also penetrates these regions to reach the drift region 18. The trench portion penetrating the doping region is not limited to a case where the trench portion is formed in the order of forming the doping region and then the trench portion. A case where the trench portion is formed and then the doping region is formed between the trench portions is also included in the case where the trench portion penetrates the doping region.
[0071] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 formed on the front surface 21. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate insulating film 42 inside the gate trench. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.
[0072] The gate conductive portion 44 includes a region facing the adjacent base region 14 on the mesa portion 71 side, across the gate insulating film 42, in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel due to an electron inversion layer is formed in the surface layer of the interface of the base region 14 that contacts the gate trench.
[0073] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front surface 21 with an interlayer insulating film 38.
[0074] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided penetrating the interlayer insulating film 38.
[0075] 2 shows an example of the configuration of a semiconductor module 200. The semiconductor module 200 of this example includes a semiconductor chip 100, a laminated substrate 150, a housing 210, a sealing resin 220, a lead frame 230, bonding wires 240, and a base substrate 250.
[0076] The housing 210 accommodates the semiconductor chip 100. The shape of the housing 210 in this example is a rectangular parallelepiped, but is not limited to this. The side walls and the bottom of the housing 210 may be composed of separate members. For example, the material of the housing 210 is an insulating material such as a resin. The resin may be selected from polyphenylene sulfide (PPS), polybutylene terephthalate (PBT), polybutyl acrylate (PBA), polyamide (PA), acrylonitrile butadiene styrene (ABS), liquid crystal polymer (LCP), polyether ether ketone (PEEK), polybutylene succinate (PBS), urethane, silicone, and the like. The housing 210 in this example accommodates a semiconductor assembly 260 consisting of a plurality of semiconductor chips 100, bonding wires 240, and a laminated substrate 150.
[0077] The laminated substrate 150 is provided on an upper surface of the base substrate 250. A plurality of semiconductor chips 100 may be provided on the laminated substrate 150. The laminated substrate 150 includes a first metal layer 151, an insulating plate 152, and a second metal layer 153. For example, the laminated substrate 150 may be a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazing) substrate.
[0078] The insulating plate 152 is formed of an insulating material such as ceramics, such as alumina (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), etc. The first metal layer 151 is provided on the lower surface of the insulating plate 152, and may be fixed to the upper surface of the substrate base via a solder part 160.
[0079] The second metal layer 153 is a conductive member provided on the upper surface of the insulating plate 152. The second metal layer 153 may include metal wiring or pads, etc. The first metal layer 151 and the second metal layer 153 may be formed of a plate containing a metal material such as copper or a copper alloy. The material of the second metal layer 153 may be the same as or different from the material of the first metal layer 151. The first metal layer 151 and the second metal layer 153 may be fixed to the surface of the insulating plate 152 by solder, brazing, etc. The second metal layer 153 is electrically connected to the semiconductor chip 100 by the solder portion 160. In addition, the second metal layer 153 is electrically connected to the lead frame 230 by the bonding wire 240.
[0080] The base substrate 250 is provided below the laminated substrate 150. A cooling device (not shown), such as a heat sink, may be provided below the base substrate 250. A thermally conductive material, such as a TIM (Thermal Interface Material), may be applied to the base substrate 250.
[0081] The solder portion 160 fixes the semiconductor chip 100 to the second metal layer 153. The solder portion 160 electrically and mechanically connects the semiconductor chip 100 and the second metal layer 153. The solder portion 160 connects a pad included in the second metal layer 153 to the collector electrode 24 of the semiconductor chip 100. For example, the material of the solder portion 160 is a Sn-Cu based or Sn-Sb based solder.
[0082] The lead frame 230 is provided so as to be exposed to the outside of the housing 210 in order to electrically connect the semiconductor chip 100 to an external control device or the like. The lead frame 230 is provided so as to penetrate the housing 210 and extend to the inside of the housing 210.
[0083] The bonding wires 240 are connected to the multiple semiconductor chips 100. The bonding wires 240 may electrically connect the multiple semiconductor chips 100 to each other. The bonding wires 240 may electrically connect the semiconductor chips 100 and the lead frame 230. The bonding wires 240 may electrically connect the second metal layer 153 and the lead frame 230.
[0084] The sealing resin 220 includes a first sealing layer 221 that covers a semiconductor assembly 260 including a plurality of semiconductor chips 100, bonding wires 240, and a laminated substrate 150 inside the housing 210. The sealing resin 220 includes a second sealing layer 222 provided above the first sealing layer 221. The sealing resin 220 includes a third sealing layer 223 provided above the second sealing layer. The sealing resin 220 seals the semiconductor assembly 260 inside the housing 210, and maintains the insulation of the semiconductor module 200 while maintaining waterproofness, thereby preventing dielectric breakdown due to the intrusion of moisture, gas, or the like into the interior of the semiconductor module 200.
[0085] The sealing resin 220 of this example has a three-layer structure consisting of a first sealing layer 221, a second sealing layer 222, and a third sealing layer 223, which are made of different materials. The sealing resin 220 may have a four or more layer structure consisting of different materials. The sealing resin 220 of this example has a three-layer structure consisting of different materials, and is formed so that the hardness and waterproofness improve from the bottom to the top of the semiconductor module 200. This makes it possible to improve the waterproofness while preventing dielectric breakdown of the semiconductor module 200. The sealing resin 220 may be formed so that the glass transition temperature and the elastic modulus improve from the bottom to the top of the semiconductor module 200.
[0086] Each sealing layer may be provided so that the hardness and waterproofness change gradually from the bottom to the top of the semiconductor module 200, or so that the properties are uniform throughout the sealing layer. This allows the hardness and waterproofness of the entire sealing resin 220 to be finely adjusted to meet the required properties.
[0087] The sealing resin 220 in this example has a three-layer structure made of different materials, and is formed so that the coefficient of thermal expansion decreases from the bottom to the top of the semiconductor module 200. This makes it possible to prevent the sealing resin 220 from cracking when heat is repeatedly applied to the semiconductor module 200.
[0088] The sealing resin 220 may or may not contain an inorganic filler as a material. The sealing resin 220 of this example does not contain an inorganic filler as a material. The sealing resin 220 does not need to contain a silica filler containing SiO2 as a material. This keeps the brittleness of the sealing resin 220 low, and suppresses the occurrence of cracks in the sealing resin 220.
[0089] First sealing layer 221 is filled inside housing 210 up to a position higher than the upper surface of bonding wire 240. In this example, distance d between the upper end of first sealing layer 221 and the upper end of bonding wire 240 is 0.5 mm or more and 1.5 mm or less. Distance d may be the shortest distance between the upper end of first sealing layer 221 and the upper end of bonding wire 240, and may be the distance in the stacking direction of sealing resin 220.
[0090] Filling first sealing layer 221 to a position higher than the upper surface of bonding wire 240 suppresses the occurrence of air bubbles and cracks at the interface between first sealing layer 221 and second sealing layer 222, and prevents dielectric breakdown of semiconductor module 200. Furthermore, by separating the upper end of first sealing layer 221 from the upper end of bonding wire 240 by distance d, even if semiconductor module 200 is thermally deformed, it is possible to prevent bonding wire 240 from contacting second sealing layer 222, and thus prevent dielectric breakdown of semiconductor module 200.
[0091] The thickness T1 of the first sealing layer 221 is thicker than the thickness T2 of the second sealing layer 222 and thicker than the thickness T3 of the third sealing layer 223. In this specification, the thickness of each sealing layer may be the average thickness in the stacking direction of the sealing resin 220, or may be the maximum thickness. The thickness T1 of the first sealing layer 221 may be the average distance from the bottom end to the top end of the first sealing layer 221 in the stacking direction (Z-axis direction) of the sealing resin 220, or may be the maximum value. The thickness T1 of the first sealing layer 221 may be 50% or more and 70% or less of the thickness of the entire sealing resin 220. As an example, the thickness of the entire sealing resin 220 is 6.5 mm, and the thickness T1 of the first sealing layer 221 is 3.5 mm or more and 4.5 mm or less.
[0092] The first sealing layer 221 is made of a material having a higher insulating property than the other sealing layers. In one example, the first sealing layer 221 includes a silicone gel material or a fluorine gel material. By making the first sealing layer 221 of a material having a higher insulating property, it is possible to prevent insulation failure between conductive components in the semiconductor module 200 when the semiconductor module 200 is operated.
[0093] Second sealing layer 222 is provided on the upper surface of first sealing layer 221. Second sealing layer 222 is made of a material having a higher hardness than first sealing layer 221. In this specification, hardness may be penetration hardness. The hardness of second sealing layer 222 may be the penetration hardness of second sealing layer 222 in a state after being hardened through an annealing process.
[0094] The second sealing layer 222 is made of a material having a smaller coefficient of thermal expansion than the first sealing layer 221. The second sealing layer 222 is made of a material having better heat resistance and stress relaxation properties than the first sealing layer 221. In one example, the second sealing layer 222 includes a silicone elastomer material. This makes it possible to prevent the third sealing layer 223 from being affected even if the first sealing layer 221 is deteriorated or cracked due to thermal deformation.
[0095] The second sealing layer 222 may be made of a material having a higher glass transition temperature than the first sealing layer 221. The second sealing layer 222 may be made of a material having a higher elastic modulus than the first sealing layer 221. This can achieve the effect of reducing cracks caused by repeated thermal history.
[0096] The thickness T2 of the second sealing layer 222 is thinner than the thickness T1 of the first sealing layer 221. The thickness T2 of the second sealing layer 222 may be the average value or the maximum value of the distance from the bottom end to the top end of the second sealing layer 222 in the stacking direction (Z-axis direction) of the sealing resin 220. The thickness T2 of the second sealing layer 222 may be the same as or different from the thickness T3 of the third sealing layer 223.
[0097] Third sealing layer 223 is provided on the upper surface of second sealing layer 222. Third sealing layer 223 is made of a material having a higher hardness than second sealing layer 222. That is, second sealing layer 222 is made of a material having a lower hardness than third sealing layer 223. By making the hardness of third sealing layer 223 higher than the hardness of first sealing layer 221 and second sealing layer 222, the influence of deterioration, cracks, and the like that occur inside semiconductor module 200 can be suppressed, and the insulation properties of semiconductor module 200 can be improved.
[0098] Third sealing layer 223 is made of a material having a smaller coefficient of thermal expansion than second sealing layer 222. That is, second sealing layer 222 is made of a material having a larger coefficient of thermal expansion than third sealing layer 223.
[0099] The third sealing layer 223 is made of a material that is more waterproof than the other sealing layers. In one example, the third sealing layer 223 includes a silicone gel material. By making the third sealing layer 223 out of a material that is more waterproof, the waterproofness of the semiconductor module 200 can be maintained even when the semiconductor module 200 is used under high humidity conditions, such as on a ship.
[0100] Third sealing layer 223 may be made of a material having a higher glass transition temperature than second sealing layer 222. Third sealing layer 223 may be made of a material having a higher elastic modulus than second sealing layer 222. This can achieve the effect of reducing cracks caused by repeated thermal history.
[0101] The thickness T3 of the third sealing layer 223 is thinner than the thickness T1 of the first sealing layer 221. The thickness T3 of the third sealing layer 223 may be the average value or the maximum value of the distance from the bottom end to the top end of the third sealing layer 223 in the stacking direction (Z-axis direction) of the sealing resin 220. The thickness T3 of the third sealing layer 223 may be the same as the thickness T2 of the second sealing layer 222. In this specification, the sealing layers having the same thickness means that the difference in thickness is within 0.5%.
[0102] The semiconductor module 200 may include a primer layer 224 provided between the first sealing layer 221 and the multiple semiconductor chips 100, the bonding wires 240, and the laminated substrate 150. The primer layer 224 may be provided on an inner side wall of the housing 210. The thickness of the primer layer 224 may be thinner than the thickness T1 of the first sealing layer 221, thinner than the thickness T2 of the second sealing layer 222, and thinner than the thickness T3 of the third sealing layer 223. In one example, the thickness of the primer layer 224 is 0 μm or more and 10 μm or less.
[0103] The primer layer 224 is made of a material that functions as a sulfuration inhibitor. In one example, the primer layer 224 includes a polyamide-based material, a polyimide-based material, or an amide-imide-based material. By providing the primer layer 224, the operational stability of the semiconductor module 200 can be improved.
[0104] FIG. 3A is a flowchart showing an example of a manufacturing method of the semiconductor module 200. The manufacturing method of this example includes a step S100 of providing a laminated substrate 150. The manufacturing method of this example includes a step S110 of providing a plurality of semiconductor chips 100 on the laminated substrate 150. The manufacturing method of this example includes a step S120 of connecting bonding wires 240 to the plurality of semiconductor chips 100. The manufacturing method of this example includes a step S130 of housing a semiconductor assembly 260 consisting of the plurality of semiconductor chips 100, the bonding wires 240, and the laminated substrate 150 inside the housing 210. The manufacturing method of this example includes a step S140 of filling the sealing resin 220. Of the steps, the steps other than the step S140 of filling the sealing resin 220 may be performed by a normal method that can be understood by a person skilled in the art, and therefore will not be described in this specification.
[0105] 3B is a flowchart showing an example of step S140 of filling the sealing resin 220. The step S140 of filling the sealing resin 220 includes a step S141 of forming a primer layer 224, a step S142 of filling the first sealing layer 221, a first annealing step S143, a step S144 of filling the second sealing layer 222, a second annealing step S145, a step S146 of filling the third sealing layer 223, and a third annealing step S147.
[0106] In step S141 of forming the primer layer 224, the primer layer 224 is laminated on the surface of the semiconductor assembly 260 housed inside the housing 210. The primer layer 224 may be laminated by a CVD (Chemical Vapor Deposition) method or the like. This allows the primer layer 224 to be formed uniformly. Step S141 of forming the primer layer 224 may be omitted.
[0107] In step S142 of filling the first sealing layer 221, resin for forming the first sealing layer 221 is filled inside the housing 210. In step S142 of filling the first sealing layer 221, the resin is filled so that the first sealing layer 221 covers the multiple semiconductor chips 100, the bonding wires 240, and the laminated substrate 150 inside the housing 210. That is, the first sealing layer 221 is filled inside the housing 210 up to a position higher than the upper surface of the bonding wires 240.
[0108] In the first annealing step S143, the first sealing layer 221 is cured. The first annealing step S143 is performed after the step S142 of filling the first sealing layer 221 and before the step S144 of filling the second sealing layer 222. In the first annealing step S143, the first sealing layer 221 does not have to be completely cured. The conditions of the first annealing step S143 may be a lower temperature than the conditions under which the first sealing layer 221 is completely cured, and the heating time may be shorter than the conditions under which the first sealing layer 221 is completely cured. By shortening the time of the first annealing step S143, the time required to form the sealing resin 220 can be shortened. The temperature of the first annealing step S143 is, for example, 50°C or higher and 65°C or lower.
[0109] In step S144 of filling the second sealing layer 222, a resin for forming the second sealing layer 222 is filled into the housing 210. Since the first sealing layer 221 is cured or provisionally cured in the first annealing step S143, the second sealing layer 222 can be formed to cover the upper part of the first sealing layer 221.
[0110] In the second annealing step S145, the second sealing layer 222 is cured. The second annealing step S145 is performed after the step S144 of filling the second sealing layer 222 and before the step S146 of filling the third sealing layer 223. In the second annealing step S145, the first sealing layer 221 and the second sealing layer 222 may not be completely cured. The conditions of the second annealing step S145 may be a lower temperature than the conditions under which the first sealing layer 221 and the second sealing layer 222 are completely cured, and the heating time may be shorter than the conditions under which the first sealing layer 221 and the second sealing layer 222 are completely cured. By shortening the time of the second annealing step S145, the time required to form the sealing resin 220 can be shortened. The temperature of the second annealing step S145 is, for example, 50° C. or higher and 65° C. or lower.
[0111] In step S146 of filling the third sealing layer 223, a resin for forming the third sealing layer 223 is filled into the housing 210. Since the second sealing layer 222 is cured or provisionally cured in the first annealing step S143 and the second annealing step S145, the third sealing layer 223 can be formed so as to cover the upper part of the second sealing layer 222. The third sealing layer 223 may be filled from above the second sealing layer 222 to the same height as the upper surface of the housing 210.
[0112] In the third annealing step S147, the third sealing layer 223 is cured. The third annealing step S147 is performed after the step S146 of filling the third sealing layer 223. In the third annealing step S147, the first sealing layer 221, the second sealing layer 222, and the third sealing layer 223 may not be completely cured. The conditions of the third annealing step S147 may be a lower temperature than the conditions under which the first sealing layer 221, the second sealing layer 222, and the third sealing layer 223 are completely cured, and the heating time may be shorter than the conditions under which the first sealing layer 221, the second sealing layer 222, and the third sealing layer 223 are completely cured. By shortening the time of the third annealing step S147, the time required to form the sealing resin 220 can be shortened. The temperature of the third annealing step S147 is, for example, 50° C. or higher and 65° C. or lower.
[0113] After the third annealing step S147, an additional annealing step may be included to harden the first encapsulation layer 221, the second encapsulation layer 222 and the third encapsulation layer 223. The temperature of the additional annealing step is, for example, 185°C.
[0114] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.
[0115] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]
[0116] REFERENCE SIGNS LIST 10 semiconductor substrate, 12 emitter region, 14 base region, 15 contact region, 16 accumulation region, 17 well region, 18 drift region, 20 buffer region, 21 front surface, 22 collector region, 23 back surface, 24 collector electrode, 25 connection portion, 30 dummy trench portion, 31 extension portion, 32 dummy insulating film, 33 connection portion, 34 dummy conductive portion, 38 interlayer insulating film, 40 gate trench portion, 41 extension portion, 42 gate insulating film, 43 connection portion, 44 gate conductive portion, 50 gate metal layer, 52 emitter electrode, 54 contact hole, 55 contact hole, 56 Contact hole, 70, transistor portion, 71, mesa portion, 80, diode portion, 81, mesa portion, 82, cathode region, 90, boundary portion, 91, mesa portion, 100, semiconductor chip, 110, active region, 120, peripheral region, 130, gate pad, 150, laminated substrate, 151, first metal layer, 152, insulating layer Edge plate, 153... second metal layer, 160... solder portion, 200... semiconductor module, 210... housing, 220... sealing resin, 221... first sealing layer, 222... second sealing layer, 223... third sealing layer, 224... primer layer, 230... lead frame, 240... bonding wire, 250... base substrate, 260... semiconductor assembly
Claims
1. A semiconductor module, comprising: A laminated substrate; A plurality of semiconductor chips provided on the laminated substrate; bonding wires connected to the plurality of semiconductor chips; a housing that houses the semiconductor chips, the bonding wires, and the laminated substrate; a first sealing layer that covers the semiconductor chips, the bonding wires, and the laminated substrate inside the housing; a second sealing layer provided above the first sealing layer; a third sealing layer provided above the second sealing layer; Equipped with the first sealing layer is filled in the interior of the housing to a position higher than an upper surface of the bonding wires; The hardness of the second sealing layer is greater than the hardness of the first sealing layer and less than the hardness of the third sealing layer. Semiconductor module.
2. The distance between the upper end of the first sealing layer and the upper end of the bonding wire is 0.5 mm or more and 1.5 mm or less. The semiconductor module according to claim 1 .
3. The first sealing layer has a thickness of 3.5 mm or more and 4.5 mm or less. The semiconductor module according to claim 1 .
4. The first sealing layer includes a silicone gel material or a fluorine gel material. The semiconductor module according to claim 1 .
5. The second sealing layer comprises a silicone elastomer material. The semiconductor module according to claim 1 .
6. The second sealing layer has a thickness smaller than that of the first sealing layer. The semiconductor module according to claim 1 .
7. The third sealing layer comprises a silicone gel material. The semiconductor module according to claim 1 .
8. The third sealing layer has a thickness smaller than that of the first sealing layer. The semiconductor module according to claim 1 .
9. The thickness of the third sealing layer is the same as the thickness of the second sealing layer. The semiconductor module according to claim 1 .
10. The second sealing layer has a coefficient of thermal expansion smaller than that of the first sealing layer and larger than that of the third sealing layer. The semiconductor module according to claim 1 .
11. A primer layer is provided between the first sealing layer, the plurality of semiconductor chips, the bonding wires, and the laminated substrate. The semiconductor module according to claim 1 .
12. A method for manufacturing a semiconductor module, comprising the steps of: providing a laminate substrate; providing a plurality of semiconductor chips on the laminate substrate; connecting bonding wires to the plurality of semiconductor chips; housing the semiconductor chips, the bonding wires, and the laminated substrate inside a housing; filling a first sealing layer inside the housing so as to cover the semiconductor chips, the bonding wires, and the laminated substrate; filling a second sealing layer so as to cover the upper part of the first sealing layer; filling a third sealing layer so as to cover the upper part of the second sealing layer; Equipped with the first sealing layer is filled in the interior of the housing to a position higher than an upper surface of the bonding wires; The hardness of the second sealing layer is greater than the hardness of the first sealing layer and less than the hardness of the third sealing layer. A method for manufacturing a semiconductor module.
13. a first annealing step after the step of filling the first encapsulation layer and before the step of filling the second encapsulation layer to harden the first encapsulation layer; a second annealing step after the step of filling the second encapsulation layer and before the step of filling the third encapsulation layer to harden the second encapsulation layer; a third annealing step for hardening the third encapsulation layer after the step of filling the third encapsulation layer; The method for manufacturing a semiconductor module according to claim 12 , comprising: