Semiconductor device

Abstract

To reduce a circuit area.SOLUTION: A memory device comprises a memory cell for storing data as stored data, an output signal line, and wiring to which voltage is applied. The memory cell includes a comparison circuit performing a comparison operation between the stored data and search data and taking a conduction state or a non-conduction state in accordance with the operation result, and a field-effect transistor controlling writing and holding of the stored data. Voltage of the output signal line is equal to the voltage of the wiring when the comparison circuit is in the conduction state.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One aspect of the present invention relates to a storage device. [Background technology]

[0002] In recent years, development of data rewritable storage devices has progressed.

[0003] The storage device may be, for example, an associative memory.

[0004] Associative memory is not just a method of rewriting data, but also a method of storing search data in memory cells. It is a storage device that can determine what type of data is stored in it. .

[0005] The associative memory is used, for example, as a cache memory of a set associative system. The set associative method is a data storage structure that consists of multiple tags. Associative memory is used as the tag. By using associative memory for the cache memory, This makes it possible to speed up data communication between the CPU and cache memory.

[0006] A memory cell in an associative memory is, for example, a storage circuit for storing data. It is configured by using a plurality of comparison circuits that compare the data stored in the memory with specific data (for example, See, for example, Patent Document 1.

[0007] In Patent Document 1, a magnitude comparison circuit and a match detection circuit are used to decode multi-bit data. It is possible to distinguish the data. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2004-295967 A Summary of the Invention [Problem to be solved by the invention]

[0009] Conventional associative memories have a problem in that the circuit area of ​​each memory cell is large. For example, in the associative memory shown in Patent Document 1, the number of transistors in each memory cell is 11. The circuit area is large.

[0010] In addition, in conventional associative memories, the leakage current of transistors in the off state causes the retention There was a problem that the data stored in the memory cell in the state changed. For example, in the associative memory shown in Patent Document 1, when the supply of power is stopped, the transistor leads Data will be lost due to a current drain, etc. Therefore, while data is being held, the power supply should be turned off. This requires a continuous supply of power, resulting in high power consumption.

[0011] In one aspect of the present invention, the circuit area is reduced, and the memory cell in the retention state is written One or more of the objectives is to suppress fluctuations in stored data. [Means for solving the problem]

[0012] In one aspect of the present invention, a comparison circuit for comparing data stored in a memory cell with search data is provided. The memory cell is configured by using a control transistor that controls the setting of the data stored in the memory cell. By configuring the memory cell, the number of transistors in the memory cell can be reduced, resulting in a reduction in the circuit area. To aim for small.

[0013] In one embodiment of the present invention, the control transistor is a transistor having a wide gate insulating film such as an oxide semiconductor. By using a field effect transistor including a channel forming layer using a gap semiconductor, The leakage current of the control transistor in the off state is reduced, and the control transistor is turned off. The present invention aims to suppress fluctuations in data stored in memory cells when By suppressing data fluctuations, for example, it is possible to supply power while retaining data in memory cells. Since the supply can be stopped as needed, power consumption can also be reduced.

[0014] One embodiment of the present invention is a memory cell that stores data as memory data, an output signal line, and and a wiring to which a voltage is applied, and the memory cell performs a comparison operation between the stored data and the search data. When the value of the stored data is smaller than the value of the search data, the storage data is in a conductive state. When the value of the stored data matches the search data, or when the value of the stored data is greater than the search data, A comparator circuit that is turned off when the input is turned on and a field effect transistor that controls the writing and retention of stored data. When the comparator circuit is in a conductive state, the voltage value of the output signal line is equal to the voltage of the wiring. It is a storage device that has a value equivalent to

[0015] One embodiment of the present invention is a memory cell that stores data as memory data, an output signal line, and and a wiring to which a voltage is applied, and the memory cell performs a comparison operation between the stored data and the search data. When the value of the stored data is greater than the value of the search data, the storage data is in a conductive state. When the value of the stored data matches the search data, or when the value of the stored data is smaller than the search data, A comparator circuit that is turned off when the input is turned on and a field effect transistor that controls the writing and retention of stored data. When the comparator circuit is in a conductive state, the voltage value of the output signal line is equal to the voltage of the wiring. It is a storage device that has a value equivalent to

[0016] In one embodiment of the present invention, there is provided an N-stage memory device, each of which stores one bit of data as storage data. (N is a natural number of 2 or more) memory cells, a first output signal line, a second output signal line, and a A voltage supply line and first to (N-1)th connection wirings, each of the N stages of memory cells A first comparison operation is performed between 1 bit of stored data and 1 bit of search data, and 1 bit of stored data is When the data value is smaller than the value of the 1-bit search data, the transistor is in a conductive state. When the value of the stored data matches one bit of search data, or when the value of one bit of stored data a first comparison circuit which is turned off when the value of the first comparison circuit is greater than the value of the 1-bit search data; A second comparison operation is performed between the 1-bit stored data and the 1-bit search data. When the value of the data is smaller than the value of the 1-bit search data, or when the value of the 1-bit storage data When the value of the search data matches that of the 1-bit, the transistor is in a conductive state. a second comparison circuit that is non-conductive when the value is greater than the value of the one-bit search data; A field effect transistor that controls writing and holding of one bit of memory data; The first comparison circuit of the first stage memory cell is turned on or off to detect the current. a first-stage memory cell having a function of controlling an electrical connection between the voltage supply line and the first output signal line; The second comparison circuit is turned on or off to determine whether the voltage supply line is connected to the first connection. It has the function of controlling the electrical connection with the connecting wiring, and is the Kth stage (K is a natural number between 2 and N-1). The first comparison circuit of the memory cell K-1 is turned on or off to determine whether the first comparison circuit of the memory cell K-1 is in a conductive state or a non-conductive state. a function of controlling an electrical connection between the connection wiring and the first output signal line, The second comparison circuit of the K-1st connecting wire is turned on or off by the K-1st connecting wire. and a Kth connection wiring, and a first ratio of the Nth stage memory cell The comparator circuit is in a conductive state or a non-conductive state to compare the N-1th connection wiring and the first output The second comparison circuit of the Nth stage memory cell has a function of controlling an electrical connection with the signal line, By being in a conductive state or a non-conductive state, It is a memory device that has the function of controlling electrical connections.

[0017] In one embodiment of the present invention, there is provided an N-stage memory device, each of which stores one bit of data as storage data. (N is a natural number of 2 or more) memory cells, a first output signal line, a second output signal line, and a A voltage supply line and first to (N-1)th connection wirings, each of the N stages of memory cells A first comparison operation is performed between 1 bit of stored data and 1 bit of search data, and 1 bit of stored data is When the data value is greater than the value of the 1-bit search data, the transistor is in a conductive state. When the value of the stored data matches one bit of search data, or when the value of one bit of stored data a first comparison circuit which is turned off when the value of the first comparison circuit is smaller than the value of the 1-bit search data; A second comparison operation is performed between the 1-bit stored data and the 1-bit search data. When the value of the data is greater than the value of the 1-bit search data, or when the value of the 1-bit storage data When the value of the search data matches that of the 1-bit, the transistor is in a conductive state. a second comparison circuit that is non-conductive when the value is smaller than the value of the 1-bit search data; A field effect transistor that controls writing and holding of one bit of memory data; The first comparison circuit of the first stage memory cell is turned on or off to detect the current. a first-stage memory cell having a function of controlling an electrical connection between the voltage supply line and the first output signal line; The second comparison circuit is turned on or off to determine whether the voltage supply line is connected to the first connection. It has the function of controlling the electrical connection with the connecting wiring, and is the Kth stage (K is a natural number between 2 and N-1). The first comparison circuit of the memory cell K-1 is turned on or off to determine whether the first comparison circuit of the memory cell K-1 is in a conductive state or a non-conductive state. a function of controlling an electrical connection between the connection wiring and the first output signal line, The second comparison circuit of the K-1st connecting wire is turned on or off by the K-1st connecting wire. and a Kth connection wiring, and a first ratio of the Nth stage memory cell The comparator circuit is in a conductive state or a non-conductive state to compare the N-1th connection wiring and the first output The second comparison circuit of the Nth stage memory cell has a function of controlling an electrical connection with the signal line, By being in a conductive state or a non-conductive state, It is a memory device that has the function of controlling electrical connections.

[0018] In one embodiment of the present invention, a field effect transistor is formed by using an oxide semiconductor in which a channel is formed. The structure may include a body layer. Effect of the Invention

[0019] According to one embodiment of the present invention, the number of transistors in a memory cell is reduced, and the circuit area is reduced. According to one embodiment of the present invention, when the control transistor is in an off state, When the voltage is applied to the memory cell, the fluctuation of the data stored in the memory cell can be suppressed. [Brief description of the drawings]

[0020] [Figure 1] 1A and 1B are diagrams illustrating examples of storage devices. [Diagram 2] 1A and 1B are diagrams illustrating examples of storage devices. [Diagram 3] 1A and 1B are diagrams illustrating examples of storage devices. [Figure 4] 1A and 1B are diagrams illustrating examples of storage devices. [Diagram 5] 1A to 1C are schematic cross-sectional views illustrating examples of the structure of a transistor. [Figure 6] 1A to 1C are schematic cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 7] 1A and 1B are diagrams illustrating examples of the structure of a memory device. [Figure 8] FIG. 1 is a diagram for explaining an example of a processor; [Figure 9] 1A to 1C are diagrams illustrating examples of electronic devices. [Figure 10] 1A to 1C are diagrams illustrating the crystal structure of an oxide material. [Figure 11] 1A to 1C are diagrams illustrating the crystal structure of an oxide material. [Figure 12] 1A to 1C are diagrams illustrating the crystal structure of an oxide material. [Figure 13] FIG. 13 is a graph for explaining the gate voltage dependence of mobility obtained by calculation. [Figure 14] FIG. 1 is a graph showing the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 15] FIG. 1 is a graph showing the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 16] FIG. 1 is a graph showing the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 17] 1A and 1B are diagrams illustrating cross-sectional structures of transistors used in calculation. [Figure 18] FIG. 13 shows characteristics of a transistor. [Figure 19] FIG. 13 shows characteristics of a transistor. [Figure 20] FIG. 13 shows characteristics of a transistor. [Figure 21] FIG. 13 shows characteristics of a transistor. [Figure 22] FIG. 13 shows characteristics of a transistor. [Diagram 23] FIG. 1 shows an XRD spectrum of an oxide material. [Figure 24] FIG. 13 shows characteristics of a transistor. [Diagram 25] 1A and 1B are a cross-sectional view and a plan view of a semiconductor device. [Figure 26] 1A and 1B are a cross-sectional view and a plan view of a semiconductor device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] An embodiment of the present invention will be described below with reference to the accompanying drawings. The contents of the embodiments may be modified without departing from the spirit and scope of the present invention. It would be easy for a person skilled in the art to understand. Therefore, the present invention is not limited to the description of the following embodiments. Not done.

[0022] The contents of each embodiment can be appropriately combined with each other. The contents of can be substituted for each other.

[0023] In addition, ordinal numbers such as 1st and 2nd are used to avoid confusion between components. The number of is not limited to the number of ordinal numbers.

[0024] (Embodiment 1) In this embodiment, an example of a storage device capable of determining stored data will be described.

[0025] The memory device according to the present embodiment includes a memory cell and an output signal line. The rule performs a comparison operation between stored data (also called memory data) and search data. The memory cell array has a function of determining the data stored therein. The number of memory cells may be multiple. The stored data and the search data may each be: One bit of data can be used. The output signal line is This is a wiring to which a voltage value is set according to a calculation. The voltage of the output signal line becomes the output signal.

[0026] Further, an example of a memory cell will be described with reference to FIG. 1 and FIG.

[0027] As shown in FIG. 1 and FIG. 2A, the memory cell includes a comparator circuit 101 (also called Comp1). ), a comparison circuit 102 (also referred to as Comp2), and a transistor 131. The comparison circuit 102 is not necessarily provided. For example, if the memory device has a plurality of memory cells In this case, a comparison circuit 102 is provided to discriminate data of multiple bits. In this case, the comparison circuit 102 can be configured as shown in FIG. The conduction state between the memory cell indicated by the bit line and other memory cells is controlled.

[0028] As the transistor, for example, a field effect transistor can be used.

[0029] The comparison circuit 101 compares the stored data (also called data Dm) stored in the memory cell with the search data A first comparison operation is performed using the data (also called data Dsch), and the output is determined according to the result of the operation. It has a function to control whether or not to change the voltage value of the output signal line OUT. For example, 101 indicates a voltage of the output signal line OUT when the value of the data Dm is smaller than the value of the data Dsch. A function to change the pressure value, or output when the value of data Dm is greater than the value of data Dsch It has the function of changing the voltage value of the signal line OUT.

[0030] The comparison circuit 101 can be configured using transistors. For example, As shown, the comparison circuit 101 includes a transistor 111 and a transistor 112. At this time, the transistor 111 is an N-channel transistor. The transistor 111 has a source and a drain 112. A voltage Vx is applied to one of the terminals, and the voltage of the gate of the transistor 111 is the data Dsch In addition, one of the source and drain of the transistor 112 is connected to the transistor 111. the other of the source and drain of the transistor 112. The other input is electrically connected to the output signal line OUT, and the gate voltage of the transistor 112 is The pressure becomes the data Dm.

[0031] The comparison circuit 102 compares the stored data (data Dm) stored in the memory cell with the search data ( The second comparison operation is performed using the data Dsch.

[0032] The comparison circuit 102 can be configured using transistors. For example, As shown, the comparison circuit 102 includes a transistor 121 and a transistor 122. At this time, the transistor 121 is an N-channel transistor. The transistor 121 has a source and a drain 122. A voltage Vx is applied to one of the terminals, and the voltage of the gate of the transistor 121 is the data Dsch In addition, one of the source and drain of the transistor 122 is connected to the transistor 121. 1, and the source and drain of the transistor 122 are electrically connected to one of the source and drain of the transistor 122. The other input is electrically connected to the other of the source and drain of the transistor 121. The voltage of the gate of the transistor 122 is the data Dm. The value of the voltage Vx is and is appropriately set according to the polarity of the transistors in the comparison circuit 102.

[0033] The transistor 131 has a function of controlling writing and holding of data Dm. For example, A data signal is input to one of the source and drain of the transistor 131. The other of the source and drain of the transistor 131 is connected to the transistor 112 (comparison circuit 101). The gate of the transistor 122 (comparison circuit 102) is electrically connected to the gate of the transistor 122. The transistor 131 is also called a control transistor. One of a pair of electrodes of a capacitance element is electrically connected to the other of the source and drain of the transistor 131. In this case, the voltage of the other of the pair of electrodes of the capacitance element is set to a value equivalent to the ground potential. Or it can be a voltage of any value.

[0034] The transistor 131 is, for example, a transistor including an oxide semiconductor layer in which a channel is formed. The oxide semiconductor layer has a band gap larger than that of silicon. is high, for example, 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. do.

[0035] Furthermore, the transistor including the oxide semiconductor layer has a low off-state current and a channel width of 1 μm per 10aA (1×10 -17 A) or less, preferably 1 aA ( 1×10 -18 A) or less, and more preferably 10zA (1×10 -20 A) or less, and more preferably 1zA (1×10 -21 A) More preferably, the current is 100 yA (1×10 -22 A) Below be.

[0036] Furthermore, as shown in FIG. 1 and FIG. 2(A), the storage device according to the present embodiment includes The data line Data and the word line Word.

[0037] The data line Data is a wiring for transmitting data to and from the memory cell. A data signal is input to the Data line. For example, the data line Data shown in FIG. The gate of transistor 111, the gate of transistor 121, and the gate of transistor 1 31. This reduces the number of wirings. In addition, one of the source and drain of the transistor 131 can be connected to the data line D. It is also possible to electrically connect the data line Data to another wiring instead of ata. A first data signal is input to one wiring, and a second data signal is input to another wiring. The other wiring is called a bit line.

[0038] The word line Word receives a signal that controls writing and holding data in a memory cell. The word line Word is electrically connected to the gate of the transistor 131. will be done.

[0039] In general, voltage refers to the difference in electric potential (also called potential difference) between two points. However, voltage and potential values ​​are often expressed in volts (V) in circuit diagrams, etc. Therefore, in this specification, unless otherwise specified, The potential difference between the potential at a point and the reference potential (also called the reference potential) is called the voltage at that point. It may be used.

[0040] Next, as an example of a method for driving the memory device in this embodiment, the memory device shown in FIG. An example of a driving method will be described. Here, as an example, a data signal is set to a high level and a low level. When the voltage Vx is at a high level, the digital The voltage of the data signal when it is at a high level is equal to the voltage of the data signal. The voltage of the data signal when it is at a low level represents data (1), and the voltage of the data signal when it is at a low level represents data (0). However, this is not limited to this, and the voltage of the data signal when it is at a high level represents data (0), and The voltage of the data signal when at the low level may represent data (1).

[0041] In the example of the method for driving the memory device according to this embodiment, first, the transistor 131 is turned on. The data signal changes the voltage of the gates of transistors 112 and 122, The value of the data Dm is set. This causes the data to be written to the memory cell. Then, the transistor 131 is turned off, so that the transistors 112 and The voltage of the gate of the memory cell 122 (the value of the data Dm) is held. At this time, the supply of voltage Vx to the memory cell may be stopped. For example, by using a switch, etc., the power consumption can be reduced. The supply of Vx can be controlled.

[0042] Next, the data signal changes the voltage of the gates of transistors 111 and 121, That is, the data Dsch is set.

[0043] At this time, the comparison circuit 101 and the comparison circuit 102 are determined based on the value of the data Dm and the value of the data Dsch. The state of 102 changes. Each state will be explained with reference to FIG. 2(B). (B) shows the value of data Dm, the value of data Dsch, the comparator circuit 101, and the comparator circuit 102. FIG.

[0044] As shown in FIG. 2B, when the value of the data Dm is (0) and the value of the data Dsch is ( In the case of 1), that is, when the value of the data Dm is smaller than the value of the data Dsch, the transistor The transistors 111 and 112 are turned on, and the comparator circuit 101 is turned on (state pa ss), and otherwise, the transistors 111 and 112 At least one of them is turned off, and the comparator circuit 101 is in a non-conducting state (also called state x). When the comparator circuit 101 is in a conductive state, the voltage value of the output signal line OUT changes and becomes a voltage Vx. When the comparator circuit 101 is in a non-conducting state, the voltage value of the output signal line OUT becomes equal to Therefore, the data D It is possible to determine whether the value of m is smaller than the value of the data Dsch.

[0045] Also, when the value of the data Dm is (1) and the value of the data Dsch is (0), that is, When the value of the data Dm is greater than the value of the data Dsch, the transistors 121 and When the transistor 122 is turned off, the comparator circuit 102 is turned off. At least one of the transistors 121 and 122 is turned on, and the comparison circuit For example, when the memory device has a plurality of memory cells, the comparison circuit When the line 102 is in a conductive state, the memory cell in which it is provided is electrically conductive to other memory cells. When the comparator circuit 102 is in a non-conductive state, the memory cell in which it is provided and the other memory cells There is no electrical continuity between the memory cell and the

[0046] The above is a description of the example of the method for driving the memory device according to this embodiment.

[0047] Note that the configuration of the memory cell is not limited to the configuration shown in FIG. For example, as shown in FIG. 3A, the transistor 111 is a P-channel transistor. The transistor 112 is an N-channel transistor, and the transistor 121 is a P-channel transistor. The transistor 121 may be an N-channel transistor. When the value of data Dm is greater than the value of data Dsch, as shown in FIG. 3(B), The comparator circuit 101 is in a conductive state at all other times and is in a non-conductive state at all other times. When the value of m is smaller than the value of the data Dsch, the comparator circuit 102 is in a non-conducting state. Therefore, it is not a matter of whether the voltage value of the output signal line OUT changes. This makes it possible to determine whether the value of data Dm is greater than the value of data Dsch. The comparator circuits 101 and 102 have the same configurations as those shown in FIG. 2(A) and FIG. 3(A). The present invention is not limited to this configuration, and other configurations may be used as long as they have the same functions.

[0048] As described with reference to FIGS. 1 to 3, in the example of the storage device according to the present embodiment, and a control transistor that controls the setting of the value of the data stored in the memory cell. By configuring a memory cell capable of determining data, Since the number of capacitors can be reduced, the circuit area can be reduced.

[0049] In the example of the memory device according to the present embodiment, the control transistor is a channel By using a transistor including an oxide semiconductor layer in which The leakage current of the transistor can be reduced. In addition, the fluctuation of the data stored in the memory cell can be suppressed when the memory cell is in the non-volatile state. By suppressing fluctuations in the data stored in the memory cell, data can be retained in the memory cell. Since the power supply can be stopped appropriately while the device is running, power consumption can be reduced.

[0050] (Embodiment 2) In this embodiment, an example of a storage device capable of determining multi-bit data will be described.

[0051] An example of a storage device in this embodiment will be described with reference to FIG.

[0052] The memory device shown in FIG. 4 has N stages (N is a natural number of 2 or more) of memory cells 201 (memory cells 2 01_1 to 201_N), an output signal line OUT1, and an output signal line OUT2. , the connection wirings CL_1 to CL_N-1, the wiring VL to which a voltage is applied, and the transistor 2 02, a transistor 203, a buffer 204, and a buffer 205. A circuit configured using N stages of memory cells 201 is used as a memory circuit for one row. A configuration may be adopted in which a plurality of circuits are provided to include a plurality of rows of memory circuits.

[0053] As each of the N stages of memory cells 201, a memory cell having the configuration shown in FIG. Each of the N stages of memory cells 201 includes a comparison circuit 101, a comparison circuit 102, and For example, each of the N stages of memory cells 201 includes a memory cell 201 and a transistor 131. One bit of data is stored as memory data.

[0054] In each of the N stages of memory cells 201, the comparator circuit 101 stores 1-bit stored data A first comparison operation is performed between the data Dm and the 1-bit search data Dsch, It has a function to control whether or not to change the voltage value of the output signal line OUT1 depending on the calculation result. For example, when the value of the data Dm is smaller than the value of the data Dsch, the comparator circuit 101 When the value of the data Dm matches the value of the data Dsch, or when the value of the data D When the value of m is greater than the value of data Dsch, the transistor is in a non-conductive state. However, the comparison circuit 101 may determine that the value of the data Dm is greater than the value of the data Dsch. When the value of data Dm is equal to the value of data Dsch, or when the value of data Dm is equal to the value of data Dsch, When the value of data Dm is smaller than the value of data Dsch, the transistor is turned off. In addition, the comparison circuit 101 (the other of the source and drain of the transistor 112) may be , and is electrically connected to the output signal line OUT1.

[0055] In each of the N stages of memory cells 201, the comparator circuit 102 stores one bit of data. A second comparison operation is performed between the data (data Dm) and the 1-bit search data (data Dsch). For example, the memory cell 20 in the Kth stage (K is a natural number between 2 and N-1) At 1_K, the comparator 102 determines that the value of the data Dm is smaller than the value of the data Dsch. When the memory cell 201_K-1 in the K-1th row and the memory cell 201_K+1 in the K+1th row are When the value of data Dm is greater than the value of data Dsch, Between the memory cell 201_K-1 in the K-1th stage and the memory cell 201_K+1 in the K+1th stage For example, the comparator circuit 102 has a function of making the data Dm non-conductive. When the value of data Dm is smaller than the value of data Dsch, or when the value of data Dm is equal to the value of data Dsch When the value of data Dm is greater than the value of data Dsch, the transistor is in a non-conducting state. However, the present invention is not limited to this, and the comparison circuit 102 may also determine whether the value of the data Dm is When the value of data Dm is greater than the value of data Dsch, or when the value of data Dm is equal to the value of data Dsch When the value of data Dm is smaller than the value of data Dsch, the transistor is in a conductive state. In addition, the memory cell 201_K in the Kth stage may have a function of being in a normal state. The comparator circuit 102 is a comparator circuit 102 in the memory cell 201_K-1 in the (K-1)th stage and a It is connected to the comparison circuit 102 in the memory cell 201_K+1 in the +1th stage.

[0056] Also, the comparison circuit 101 of the memory cell 201_1 in the first stage is in a conductive or non-conductive state. This provides a function of controlling the electrical connection between the wiring VL and the output signal line OUT1.

[0057] Also, the comparison circuit 102 of the memory cell 201_1 in the first stage is in a conductive or non-conductive state. By this, the electric connection between the wiring VL and the first connection wiring CL_1 is controlled. do.

[0058] Also, the comparison circuit 101 of the Kth stage memory cell 201_K is in a conductive or non-conductive state. As a result, the electrical connection between the K-1st connection wiring CL_K-1 and the output signal line OUT1 is It has the function of controlling.

[0059] In addition, the comparison circuit 102 of the memory cell 201_K in the Kth stage is in a conductive or non-conductive state. As a result, the electrical connection between the (K-1)th connection wiring CL_K-1 and the Kth connection wiring CL_K is It has the function of controlling the connection.

[0060] Also, the comparison circuit 101 of the memory cell 201_N in the Nth stage is in a conductive state or a non-conductive state. This allows electrical connection between the (N-1)th connection wiring CL_N-1 and the output signal line OUT1 to be established. It has the function of controlling.

[0061] In addition, the comparison circuit 102 of the memory cell 201_N in the Nth stage is in a conductive state or a non-conductive state. This allows electrical connection between the (N-1)th connection wiring CL_N-1 and the output signal line OUT2 to be established. It has the function of controlling.

[0062] In each of the N stages of memory cells 201, the source and drain of the transistor 131 One of the two is electrically connected to a different data line Data, The gate of the transistor 131 is connected to a common The input terminal is electrically connected to the word line Word.

[0063] In the first-stage memory cell 201_1, the comparator circuit 101 (the transistor 111 one of the source and drain of the transistor 121) and the comparator circuit 102 (the source and drain of the transistor 121) A wiring VL is connected to the input of the transistor 121 and one of the source and drain of the transistor 122. Therefore, the output signal line OUT2 is connected to the memory cell 201 of the Nth stage. Each of the voltages is connected to a line to which a voltage Va is applied via a comparison circuit 102. The voltage Va is appropriately set according to the polarity of the transistors that constitute the memory cell 201.

[0064] The output signal line OUT1 and the output signal line OUT2 are connected to the respective memory cells 201 in the Nth stage. The output signal line OUT2 is a line whose voltage value is set according to the comparison operation in The second memory cell 201_N (the other of the source and drain of the transistor 121, The other of the source and drain of the transistor 122 is electrically connected to the ground potential.

[0065] For the explanation of the other components, the explanation in the first embodiment will be cited as appropriate.

[0066] The transistor 202 controls whether or not the voltage of the output signal line OUT1 is set to the reference voltage. For example, one of the source and drain of the transistor 202 is connected to a reference voltage The other of the source and drain of the transistor 202 is connected to the output signal line OUT1. A control signal is input to the gate of the transistor 202. The value of the sub-voltage is appropriately set depending on, for example, the polarity of a transistor in the memory device.

[0067] The transistor 203 controls whether or not the voltage of the output signal line OUT2 is set to the reference voltage. For example, one of the source and drain of the transistor 203 is connected to a reference voltage The other of the source and drain of the transistor 203 is connected to the output signal line OUT2. A control signal is input to the gate of the transistor 203. The control signal and the reference voltage may be the same as for transistor 202.

[0068] The buffer 204 adjusts the voltage value on the output signal line OUT1 and outputs the adjusted voltage to the output signal line OUT2. It should be noted that the buffer 204 is not necessarily provided.

[0069] The buffer 205 adjusts the voltage value on the output signal line OUT2 and outputs the adjusted voltage to the output signal line OUT3. It should be noted that the buffer 205 is not necessarily provided.

[0070] Next, as an example of a method for driving a storage device according to this embodiment, a method for driving a storage device shown in FIG. Here, as an example, a data signal is divided into a high level and a low level. The digital signal is a binary (1 bit) signal, and the voltage of the data signal when it is at a high level is When the data signal is at a low level, the voltage of the data signal represents data (1), and when the data signal is at a low level, the voltage of the data signal represents data (0).

[0071] First, the memory cells 201_1 to 201_N are driven by the first data signal to the N-th data signal. Data is written to each of the memory cells 201_N, and stored in each of the memory cells 201. Set the value of the data Dm. Here, write data for each bit in each memory cell 201. By writing N bits of data into the memory cells 201_1 to 201_N, At this time, the supply of the voltage Va to the first-stage memory cell 201_1 is stopped. This can reduce power consumption. For example, by using a switch, The supply of voltage Va can be controlled by this.

[0072] Next, the transistor 202 is turned on to turn on the output signal line OUT1 and the output signal line OUT2 The voltage is set to the reference voltage.

[0073] Next, the memory cells 201_1 to 201_N are read out by the first data signal to the N-th data signal. The data Dsch in each of the cells 201_N is set. By setting the data Dsch to data for each bit, the memory cells 201_1 to In memory cell 201_N, N-bit search data can be set.

[0074] At this time, in each memory cell 201, the value of data Dm and the value of data Dsch are , the states of the comparison circuit 101 and the comparison circuit 102 change.

[0075] For example, when the value of the data Dm is smaller than the value of the data Dsch, the comparator circuit 101 is in a conductive state. When the comparator circuit 101 is in the ON state, the comparator circuit 101 is in the OFF state at other times. When the comparator circuit 101 is in a conductive state, the voltage value of the output signal line OUT1 changes. In the on state, the voltage value of the output signal line OUT1 does not change.

[0076] When the value of the data Dm is greater than the value of the data Dsch, the comparator circuit 102 is in a non-conductive state. In other cases, the comparator circuit 102 is in a conductive state. When the comparator circuit 102 in the resistor 201_K is in a conductive state, the Kth stage memory cell 201 The Kth memory cell 201_K+1 is electrically connected to the Kth memory cell 201_K+1. When the comparison circuit 102 in the K-th memory cell 201_K is in a non-conductive state, A non-conductive state is created between the K and K+1th stage memory cells 201_K+1.

[0077] As an example of the above operation, from the storage data Dm stored in each memory cell 201, The value of N-bit data is calculated from the data Dsch set in each memory cell 201. When the value of the N-bit data is larger than or smaller than the value of the N-bit data, the output signal line OUT1 At other times, the voltage value of the output signal line OUT1 does not change.

[0078] In addition, the value of N-bit data consisting of data Dm stored in each memory cell 201 is The value of the N-bit data consisting of the data Dsch set in the memory cell 201 is smaller than the value of the N-bit data consisting of the data Dsch set in the memory cell 201. When the number of memory cells 201 is small or large, the memory cells 201 in adjacent rows are not electrically connected to each other. , the data stored in each memory cell 201 in the N stages The value of N-bit data consisting of Dm is data Ds set in each memory cell 201. When the values ​​of the N-bit data consisting of ch are equal, the voltage value of the output signal line OUT2 changes. To become.

[0079] Furthermore, by a comparison operation in each memory cell 201, the output signal line OUT1 and the output signal By setting the voltage value of the signal line OUT2, the voltages stored in the memory cells 201 are Then, N-bit data consisting of the data Dm is determined.

[0080] For example, the voltage value of the output signal line OUT1 is a value representing data (1), and the voltage value of the output signal line OUT When the voltage value of 2 is a value representing data (1) or data (0), The N-bit data consisting of the stored data Dm is the N-bit data to be searched. is judged to be smaller than

[0081] The voltage value of the output signal line OUT1 represents data (0), and the voltage value of the output signal line OUT2 When the voltage value of is a value representing data (1), the data D stored in each memory cell 201 The N-bit data consisting of m is judged to be equal to the N-bit data to be searched. For example, in each of the memory cells 201 in the Nth stage, the value of the data Dm is changed to the value of the data Ds When the voltage value of the output signal line OUT2 is equal to the value of ch, the voltage value of the output signal line OUT2 becomes a value representing data (1).

[0082] The voltage value of the output signal line OUT1 represents data (0), and the voltage value of the output signal line OUT2 When the voltage value of is a value representing data (0), the data D stored in each memory cell 201 The N-bit data consisting of m is determined to be larger than the N-bit data to be searched. can be.

[0083] In addition, in the same manner as in the memory device shown in the first embodiment, in each memory cell 201, a comparison circuit 10 If the polarity of the transistors in the comparator circuit 102 and the voltage Va are reversed, the output The magnitude relationship between the voltage values ​​of the input signal line OUT1 and the output signal line OUT2 and the determination result is reversed.

[0084] As described above, whether the voltage values ​​of the output signal lines OUT1 and OUT2 change or not Therefore, the N-bit data consisting of the data Dm stored in each memory cell 201 can be discriminated. It is possible.

[0085] In addition, when a plurality of memory circuits each configured using N stages of memory cells 201 are provided, all The setting operation of the data Dsch in each of the memory cells 201 may be performed simultaneously. stomach.

[0086] The above is a description of the example of the method for driving the memory device according to this embodiment.

[0087] As described with reference to FIG. 4, a multi-stage memory cell is formed by using the memory cells having the configuration shown in the first embodiment. By configuring a storage device having a memory cell, it is possible to determine data of multiple bits. A storage device can be provided.

[0088] (Embodiment 3) In this embodiment, an oxide semiconductor which can be used for the transistor of the memory device described in the above embodiment will be described. An example of a transistor including a conductor layer will now be described.

[0089] An example of a structure of a transistor including an oxide semiconductor layer will be described with reference to FIG. 1 is a schematic cross-sectional view illustrating a structural example of a transistor according to this embodiment.

[0090] The transistor shown in FIG. 5A includes a conductive layer 601_a, an insulating layer 602_a, and a semiconductor layer 603_a, a conductive layer 605a_a, a conductive layer 605b_a, an insulating layer 606_a, and a conductive and a conductive layer 608_a.

[0091] The conductive layer 601_a is provided on an element formation layer 600_a.

[0092] The insulating layer 602_a is provided on the conductive layer 601_a.

[0093] The semiconductor layer 603_a overlaps with the conductive layer 601_a with the insulating layer 602_a interposed therebetween.

[0094] Each of the conductive layer 605a_a and the conductive layer 605b_a is provided on the semiconductor layer 603_a. and is electrically connected to the semiconductor layer 603_a.

[0095] The insulating layer 606_a is a semiconductor layer 603_a, a conductive layer 605a_a, and a conductive layer 605b_ It is placed on top of a.

[0096] The conductive layer 608_a overlaps with the semiconductor layer 603_a with the insulating layer 606_a interposed therebetween.

[0097] Note that it is not always necessary to provide one of the conductive layer 601_a and the conductive layer 608_a. When the conductive layer 608_a is not provided, the insulating layer 606_a does not have to be provided.

[0098] The transistor shown in FIG. 5B includes a conductive layer 601_b, an insulating layer 602_b, and a semiconductor layer 603_b, conductive layer 605a_b, conductive layer 605b_b, insulating layer 606_b, and conductive and a conductive layer 608_b.

[0099] The conductive layer 601_b is provided on an element formation layer 600_b.

[0100] An insulating layer 602_b is provided on the conductive layer 601_b.

[0101] Each of the conductive layer 605a_b and the conductive layer 605b_b is formed on a part of the insulating layer 602_b. It will be established.

[0102] The semiconductor layer 603_b is provided on the conductive layer 605a_b and the conductive layer 605b_b. The semiconductor layer 603 is electrically connected to the conductive layer 605a_b and the conductive layer 605b_b. _b overlaps with the conductive layer 601_b via an insulating layer 602_b.

[0103] The insulating layer 606_b is a semiconductor layer 603_b, a conductive layer 605a_b, and a conductive layer 605b_ It is provided on top of b.

[0104] The conductive layer 608_b overlaps with the semiconductor layer 603_b with the insulating layer 606_b interposed therebetween.

[0105] Note that it is not always necessary to provide either the conductive layer 601_b or the conductive layer 608_b. If the layer 608_b is not provided, the insulating layer 606_b does not need to be provided.

[0106] The transistor shown in FIG. 5C includes a conductive layer 601_c, an insulating layer 602_c, and a semiconductor layer 603_c, conductive layer 605a_c, and conductive layer 605b_c.

[0107] The semiconductor layer 603_c includes a region 604a_c and a region 604b_c. Regions 604b_c and 604b_c are spaced apart from each other and are doped with dopants. The region between the region 604a_c and the region 604b_c becomes a channel formation region. The semiconductor layer 603_c is provided on the element formation layer 600_c. The regions 604a_c and 604b_c may not be provided.

[0108] The conductive layer 605a_c and the conductive layer 605b_c are provided on the semiconductor layer 603_c. The conductive layer 605a_c and the conductive layer 605b are electrically connected to each other. The side of _c is tapered.

[0109] In addition, the conductive layer 605a_c overlaps a part of the region 604a_c, but this is not necessarily limited to this. By overlapping the conductive layer 605a_c with a part of the region 604a_c, the conductive layer The resistance between the conductive layer 605a_c and the region 604a_c can be reduced. The entire region of the semiconductor layer 603_c overlapping the conductive layer 605a_c is the region 604a_c. good.

[0110] In addition, the conductive layer 605b_c overlaps a part of the region 604b_c, but this is not necessarily limited to this. By overlapping a part of the conductive layer 605b_c with the region 604b_c, the conductive layer The resistance between the conductive layer 605b_c and the region 604b_c can be reduced. The entire region of the semiconductor layer 603_c overlapping the conductive layer 605b_c may be the region 604b_c. stomach.

[0111] The insulating layer 602_c is made up of a semiconductor layer 603_c, a conductive layer 605a_c, and a conductive layer 605b_c. It is placed on top of c.

[0112] The conductive layer 601_c overlaps with the semiconductor layer 603_c with an insulating layer 602_c interposed therebetween. A region of the semiconductor layer 603_c overlapping with the conductive layer 601_c via the conductive layer 602_c is a channel-shaped It becomes a growing field.

[0113] The transistor shown in FIG. 5D includes a conductive layer 601_d, an insulating layer 602_d, and a semiconductor It includes a conductor layer 603_d, a conductive layer 605a_d, and a conductive layer 605b_d.

[0114] The conductive layer 605a_d and the conductive layer 605b_d are provided on the element formation layer 600_d. In addition, the side surfaces of the conductive layers 605a_d and 605b_d are tapered.

[0115] The semiconductor layer 603_d includes a region 604a_d and a region 604b_d. Regions 604a_d and 604b_d are spaced apart from each other and are doped with dopants. The region between the region 604a_d and the region 604b_d is a channel formation region. The semiconductor layer 603_d includes, for example, a conductive layer 605a_d, a conductive layer 605b_d, and a substrate. The conductive layer 605a_d and the conductive layer 605b_d are electrically connected to each other. It is not necessary to provide the regions 604a_d and 604b_d. good.

[0116] Regions 604a_d are electrically connected to conductive layers 605a_d.

[0117] Region 604b_d is electrically connected to conductive layer 605b_d.

[0118] An insulating layer 602_d is provided on the semiconductor layer 603_d.

[0119] The conductive layer 601_d overlaps with the semiconductor layer 603_d with an insulating layer 602_d interposed therebetween. A region of the semiconductor layer 603_d overlapping with the conductive layer 601_d via the conductive layer 602_d is a channel-shaped It becomes a growing field.

[0120] Furthermore, each of the components shown in FIG. 5(A) to FIG. 5(D) will be described.

[0121] The element formation layers 600_a to 600_d may be, for example, insulating layers or insulating A substrate having a surface can be used. The layers 600_a to 600_d can also be used as the element formation layers.

[0122] Each of the conductive layers 601_a to 601_d functions as a gate of a transistor. The layer functioning as the gate of a transistor is called a gate electrode or a gate This is also called wiring.

[0123] The conductive layers 601_a to 601_d can be formed using, for example, molybdenum, magnesium, or titanium. Tantalum, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium For example, a layer of a metal material such as zinc or an alloy material containing this as a main component can be used. In addition, layers of materials applicable to the formation of the conductive layers 601_a to 601_d are stacked. , the conductive layers 601_a to 601_d can also be formed.

[0124] Each of the insulating layers 602_a to 602_d serves as a gate insulating layer of a transistor. It has all the functions.

[0125] The insulating layers 602_a to 602_d may be, for example, a silicon oxide layer or a silicon nitride layer. layer, silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer, aluminum nitride layer, aluminum oxide nitride layer, aluminum oxide nitride layer, hafnium oxide layer, or la oxide layer. In addition, the insulating layers 602_a to 602_d can be used. Alternatively, the insulating layers 602_a to 602_d may be formed by stacking layers of a material that can be used for the insulating layers 602_a to 602_d. do.

[0126] The insulating layers 602_a to 602_d may be, for example, An insulating layer made of a material containing a group 3 element and an oxygen element may also be used. For example, the semiconductor layer 60 When the semiconductor layers 603_a to 603_d contain a Group 13 element, By using an insulating layer containing a Group 13 element as the insulating layer in contact with the conductor layer 603_d, The state of the interface between the insulating layer and the oxide semiconductor layer can be improved.

[0127] Examples of materials containing a Group 13 element and an oxygen element include gallium oxide and aluminum oxide. , aluminum gallium oxide, and aluminum gallium oxide. Aluminum gallium is a material that has a higher aluminum content (atomic percent) than the gallium content (atomic percent). Gallium aluminum oxide is a substance with a high gallium content (atomic percent). A material with an aluminum content (atomic percent) equal to or greater than the aluminum content (atomic percent). For example, AlO x (x=3+α, α is a value greater than 0 and less than 1), Ga2O x (x=3+α, α is less than 0 (a value greater than 1 and smaller than 1) or Ga x Al 2-x O 3+α (x is greater than 0 and less than 2 A material expressed as a function of the thermal expansion coefficient (α) can also be used.

[0128] In addition, layers of materials applicable to the insulating layers 602_a to 602_d are stacked to form insulating layers For example, a plurality of GaO x in The insulating layers 602_a to 602_d are formed by stacking layers containing gallium oxide as shown. Also, GaO x The insulating layer contains gallium oxide, and AlO x The insulating layers 602_a to 602_b are stacked to form insulating layers each containing aluminum oxide. 602_d may be configured.

[0129] Each of the semiconductor layers 603_a to 603_d is a layer in which a channel of a transistor is formed. The semiconductor layers 603_a to 603_d can be used Examples of oxide semiconductors that can be used include quaternary metal oxides, ternary metal oxides, and binary metal oxides. For example, a metal oxide or a single element metal oxide can be used.

[0130] The oxide semiconductor must contain at least indium (In) or zinc (Zn). It is preferable that the oxide semiconductor contains In and Zn. In addition, a gas is used as a stabilizer to reduce the variation in the electrical characteristics of the transistors. It is preferable that the alloy contains tin (Sn) as a stabilizer. It is preferable to have hafnium (Hf) as a stabilizer. It is also preferable to have aluminum (Al) as a stabilizer.

[0131] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0132] Examples of quaternary metal oxides include In-Sn-Ga-Zn-O metal oxides, In-H f-Ga-Zn-O metal oxides, In-Al-Ga-Zn-O metal oxides, In-S n-Al-Zn-O metal oxide, In-Sn-Hf-Zn-O metal oxide, In-H For example, f-Al-Zn-O based metal oxides can be used.

[0133] Ternary metal oxides include, for example, In-Ga-Zn-O metal oxides and In-Sn-Z nO metal oxide, In-Al-Zn-O metal oxide, Sn-Ga-Zn-O metal oxide, Al-Ga-Zn-O based metal oxide, or Sn-Al-Zn-O based metal oxide; In-Hf-Zn-O metal oxides, In-La-Zn-O metal oxides, In-Ce- Zn-O metal oxide, In-Pr-Zn-O metal oxide, In-Nd-Zn-O gold metal oxides, In-Sm-Zn-O metal oxides, In-Eu-Zn-O metal oxides, I n-Gd-Zn-O metal oxide, In-Tb-Zn-O metal oxide, In-Dy-Z nO metal oxide, In-Ho-Zn-O metal oxide, In-Er-Zn-O metal Oxides, In-Tm-Zn-O metal oxides, In-Yb-Zn-O metal oxides, In -Lu-Zn-O based metal oxides and the like can be used.

[0134] Examples of binary metal oxides include In-Zn-O-based metal oxides and Sn-Zn-O-based metal oxides. Oxides, Al-Zn-O metal oxides, Zn-Mg-O metal oxides, Sn-Mg-O metal oxides Metal oxide, In-Mg-O metal oxide, In-Sn-O metal oxide, or In-G aO-based metal oxides and the like can be used.

[0135] Examples of single-element metal oxides include In-O-based metal oxides, Sn-O-based metal oxides, and Zn-O-based metal oxides can also be used. Possible metal oxides may include silicon oxide.

[0136] In-Ga-Zn-O-based metal oxides are those that contain In, Ga, and Zn as the main components. It means metal oxide, and the ratio of In, Ga, and Zn does not matter. Metal elements other than Zn may be included.

[0137] In the case of using an In-Zn-O based metal oxide, for example, In:Zn=50:1 or In:Z n=1:2 (converted to a molar ratio of In2O3:ZnO=25:1 or In2O3:Zn O=1:4), preferably In:Zn=20:1 to In:Zn=1:1 (in terms of molar ratio). In2O3:ZnO=10:1 to In2O3:ZnO=1:2), more preferably Or In:Zn=15:1 or In:Zn=1.5:1 (converted to a molar ratio of In2 The oxide target has a composition ratio of In2O3:ZnO=15:2 or In2O3:ZnO=3:4. A semiconductor layer of In-Zn-O based metal oxide can be formed using the above method. For example, The target used for forming the In-Zn-O oxide semiconductor has an atomic ratio of In:Zn:O =S:U:R, R>1.5S+U. By increasing the amount of In, The mobility of the transistor can be improved.

[0138] The composition ratio of the target used for the In-Sn-Zn-O metal oxide is, in terms of atomic ratio, In:Sn:Zn=1:2:2, In:Sn:Zn=2:1:3, In:Sn:Zn=1 :1:1, or In:Sn:Zn=20:45:35, etc. do.

[0139] In addition, as an oxide semiconductor, InLO3(ZnO) m (m is a number greater than 0, and m Materials expressed as InLO3(ZnO) can also be used. m The L in , Ga, Fe, Al, Mn, and Co. Also, , In3SnO5(ZnO) as oxide semiconductor n (n is a number greater than 0, and n is Materials expressed as a (integer) may also be used.

[0140] Also, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:Ga : In-Ga-Zn-O system with an atomic ratio of Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Metal oxides or oxides close to the metal oxides can be used. Alternatively, In:Sn:Z n=1:1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) Use In-Sn-Zn-O metal oxides with the atomic ratio of 8) or oxides with a composition close to that. It is good.

[0141] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In order to obtain the required semiconductor characteristics, Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to set the degree, etc., appropriately.

[0142] For example, it is relatively easy to obtain high mobility in In-Sn-Zn-O metal oxides. However, it is possible to reduce the bulk defect density in In-Ga-Zn-O metal oxides. This can increase the mobility.

[0143] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with the atomic ratio of In:Ga:Zn=A:B:C (A+B+C = 1), a, b, and c are in the vicinity of the oxide composition (a-A). 2 +(b-B) 2 + (c-C) 2 ≦r 2 It means that the following condition is satisfied. For example, r can be set to 0.05. The same is true for other oxides.

[0144] The oxide semiconductor may be single-crystalline or non-single-crystalline. In the latter case, it may be amorphous or polycrystalline. In addition, the structure may include a portion having crystallinity in the amorphous state, or a non-amorphous structure. That's fine too.

[0145] Since it is relatively easy to obtain a flat surface for an amorphous oxide semiconductor, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high quality. Therefore, high mobility can be obtained.

[0146] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility equal to or higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form the surface on a thickness of 0.1 nm or less.

[0147] In addition, Ra is the center line average roughness defined in JIS B0601 that can be applied to the surface. This is a three-dimensional extension of the method, which is based on the principle of averaging the absolute value of the deviation from the reference surface to the specified surface. This can be expressed as the "value obtained by dividing the total number of bits by the number of bits" and is defined by the following formula:

[0148]

number

[0149] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y1 )(x2,y2) is the rectangular area bounded by the four points, and Z0 is It refers to the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). The measurement surface is the surface shown by all the measurement data. It consists of three parameters (x, y, z) and is expressed as z = F(x, y). Note that the range of x (and y) is 0 to xMAX (and yMAX), and the range of z is is zMIN to zMAX.

[0150] In addition, at least the regions in which channels are formed of the semiconductor layers 603_a to 603_d The regions are crystalline, non-single crystals, and have a triangular or hexagonal shape when viewed from a direction perpendicular to the ab plane. , equilateral triangle, or equilateral hexagonal atomic arrangement, and viewed from a direction perpendicular to the c-axis direction, A phase in which atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers when viewed from the direction perpendicular to the c-axis direction. The material having the above phase may be called CAAC (c axis aligned). It is also called ned crystal.

[0151] In addition, when the channel length of the transistor is 30 nm, the semiconductor layers 603_a to The thickness of the semiconductor layers 603_a to 603_d may be set to, for example, about 5 nm. If the semiconductor layer 603_d is an oxide semiconductor layer of CAAC, the short channel of the transistor The Neumann effect can be suppressed.

[0152] Regions 604a_c, 604b_c, 604a_d, and 604b_d are N A dopant that gives a P-type or P-type conductivity is added to form the source or drain of the transistor. As a dopant, for example, an element in group 13 of the periodic table can be used. (e.g. boron), group 15 elements in the periodic table (e.g. nitrogen, phosphorus, and arsenic) one or more of the rare gas elements (e.g., one or more of helium, argon, and xenon) In addition, one or more of the functions as the source of the transistor can be used. The region having the function as the drain of a transistor is also called a source region. The regions 604a_c, 604b_c, 604a_d, and By adding a dopant to the regions 604b_d, the contact resistance with the conductive layer is reduced. This allows the transistors to be miniaturized.

[0153] The conductive layers 605a_a to 605a_d and the conductive layers 605b_a to 605 Each of b and d functions as a source or drain of a transistor. The layer that functions as the source of a transistor is also called a source electrode or a source wiring. The layer that functions as the drain of a transistor is also called a drain electrode or a drain wiring. .

[0154] The conductive layers 605a_a to 605a_d and the conductive layers 605b_a to 605 Examples of b_d include aluminum, magnesium, chromium, copper, tantalum, titanium, Metallic materials such as molybdenum or tungsten, or materials mainly composed of these metallic materials For example, a layer of an alloy material containing copper, magnesium, and aluminum can be used. The conductive layers 605a_a to 605a_d and the conductive layer 60 The conductive layers 605a_a to 605b_d can be formed. Materials applicable to the conductive layers 605a_d and the conductive layers 605b_a to 605b_d By stacking the layers of the material, the conductive layers 605a_a to 605a_d and the conductive layer 605b The conductive layers 605a to 605b can also be formed of, for example, copper, magnesium, and The conductive layers 605a_a to 605b are formed by laminating layers of an alloy material containing aluminum and layers containing copper. The conductive layers 605a_d and 605b_a to 605b_d can be formed. Cut.

[0155] In addition, the conductive layers 605a_a to 605a_d and the conductive layers 605b_a to 605b_d A layer containing a conductive metal oxide may be used as 605b_d. Examples of metal oxides include indium oxide, tin oxide, zinc oxide, indium oxide tin oxide, and zinc oxide. In addition, the conductive layers 605a to 605c can be formed of zinc oxide, indium oxide, or indium zinc oxide. Conductive layers 605a_d and 605b_a to 605b_d can be applied The reactive metal oxide may include silicon oxide.

[0156] The insulating layers 606_a to 606_b are the insulating layers 602_a to 602_b. A layer of a material applicable to the insulating layer 606_a and the insulating layer 606_b can be used. The insulating layer 606_a and the insulating layer 606_b are formed by laminating materials applicable to 6_b. For example, the insulating layer 606_a and the insulating layer 606_b may be formed of a silicon oxide layer, an aluminum oxide layer, or the like. For example, an aluminum oxide layer may be used to form the insulating layer 606_b. In addition, the effect of suppressing the intrusion of impurities into the semiconductor layer 603_a and the semiconductor layer 603_b can be further improved. In addition, the effect of suppressing the desorption of oxygen from the semiconductor layer 603_a and the semiconductor layer 603_b can be obtained. It can be improved.

[0157] Each of the conductive layer 608_a and the conductive layer 608_b functions as a gate of a transistor. Note that when a transistor includes both the conductive layer 601_a and the conductive layer 608_a, or In the case of a structure including both the conductive layer 601_b and the conductive layer 608_b, the conductive layer 601_a and the conductive layer 608_a, or the conductive layer 601_b and the conductive layer 608_b, It is also called a back gate, back gate electrode, or back gate wiring. By providing a plurality of conductive layers having the same structure with a channel formation layer interposed therebetween, the threshold voltage of the transistor can be reduced. This makes it easier to control the pressure.

[0158] The conductive layer 608_a and the conductive layer 608_b are, for example, the conductive layers 601_a to 6 A layer of a material applicable to the conductive layer 608_a and the conductive layer 608_d can be used. The conductive layer 608_a and the conductive layer 608_b are formed by stacking layers of a material applicable to the layer 608_b. may be configured as follows.

[0159] Note that the transistor of this embodiment is formed by using an oxide semiconductor having a function as a channel formation layer. The insulating layer is provided on a portion of the semiconductor layer, and the insulating layer is disposed on the oxide semiconductor layer. A structure including a conductive layer having a function as a source or a drain may be used. In this case, the insulating layer is a layer that protects the channel formation layer of the transistor (also called a channel protection layer). The insulating layer having the function of a channel protection layer is, for example, A layer of a material applicable to the insulating layers 602_a to 602_d can be used. In addition, the insulating layers 602_a to 602_d are laminated with materials applicable to the channel protection. An insulating layer having a function as a layer may be formed.

[0160] In addition, a base layer is formed on the element formation layers 600_a to 600_d, A transistor may be formed on the ground layer. In this case, the base layer may be, for example, an insulating layer 6. A layer of a material applicable to the insulating layers 602_a to 602_d can be used. The underlayer may be formed by stacking materials applicable to the layers 602_a to 602_d. For example, the underlayer may be formed by laminating an aluminum oxide layer and a silicon oxide layer. As a result, oxygen contained in the underlayer is released through the semiconductor layers 603_a to 603_d. It is possible to suppress the separation.

[0161] As an example of a method for manufacturing a transistor in this embodiment, a transistor shown in FIG. An example of a method for manufacturing a transistor shown in FIG. 1A to 1C are schematic cross-sectional views for explaining an example of a method for manufacturing a transistor.

[0162] First, as shown in FIG. 6A, a device formation layer 600_a is prepared. A first conductive film is formed on the a, and a part of the first conductive film is etched to form a conductive film. A layer 601_a is formed.

[0163] For example, a film of a material applicable to the conductive layer 601_a is formed by using a sputtering method. The first conductive film can be formed by the above. The first conductive film can also be formed by stacking films.

[0164] The sputtering gas may contain impurities such as hydrogen, water, hydroxyl groups, or hydrides. By using a high-purity gas from which impurities have been removed, the impurity concentration in the film formed is reduced. It is possible.

[0165] Before forming a film by sputtering, a preheating chamber of the sputtering device is By carrying out the preheating treatment, hydrogen, moisture, etc. can be prevented. Which impurities can be eliminated?

[0166] In addition, before forming a film by sputtering, for example, argon, nitrogen, helium, Alternatively, in an oxygen atmosphere, no voltage is applied to the target side, and a voltage is applied to the substrate side using an RF power source. A process is then performed to modify the surface to be treated by applying a plasma (also called reverse sputtering). By performing reverse sputtering, powdery substances (particles) adhering to the surface to be formed can be removed. , also called garbage) can be removed.

[0167] In addition, when forming a film using a sputtering method, a suction type vacuum pump or the like is used. It is possible to remove residual moisture in the film forming chamber. For example, a cryopump, an ion pump, or a titanium sublimation pump may be used. In addition, a turbo molecular pump equipped with a cold trap is used to evaporate the gas in the deposition chamber. Residual moisture can also be removed. By using the above vacuum pump, the exhaust containing impurities can be It is possible to reduce backflow of air.

[0168] In addition, as in the method for forming the conductive layer 601_a, In the example of the manufacturing method, when a layer is formed by etching a part of a film, for example, photolithography is used. A resist mask is formed on a part of the film by a lithography process, and the film is printed using the resist mask. In this case, after the layer is formed, Then, the resist mask is removed.

[0169] Alternatively, the resist mask may be formed by using an inkjet method. By using this method, a photomask is no longer necessary, which reduces manufacturing costs. In addition, an exposure mask having multiple regions with different transmittance (also called a multi-tone mask) is used. A resist mask may be formed by using a multi-tone mask. A resist mask having a region can be formed, and the resist used for manufacturing a transistor can be The number of masks can be reduced.

[0170] Next, as shown in FIG. 6(B), a first insulating film is formed on the conductive layer 601_a. This forms an insulating layer 602_a.

[0171] For example, the insulating layer 602_a can be formed by using a sputtering method or a plasma CVD method. The first insulating film can be formed by forming a film of such a material. The first insulating film can also be formed by stacking films of a material applicable to 02_a. In addition, high density plasma CVD (e.g., microwave (e.g., 2.45 GHz frequency) A film of a material applicable to the insulating layer 602_a using a high-density plasma CVD method using a wave By forming the insulating layer 602_a, the insulating layer 602_a can be made dense. The dielectric strength can be improved.

[0172] Next, as shown in FIG. 6C, an oxide semiconductor film is formed over the insulating layer 602_a. Then, a part of the oxide semiconductor film is etched to form a semiconductor layer 603_a.

[0173] For example, a sputtering method is used to deposit an oxide semiconductor material applicable to the semiconductor layer 603_a. By forming a film under a rare gas atmosphere, an oxide semiconductor film can be formed. The oxide semiconductor film may be formed under an oxygen atmosphere or a mixed atmosphere of a rare gas and oxygen. In addition, when an oxide semiconductor layer containing CAAC is formed as the semiconductor layer 603_a, The temperature of the element formation layer on which the oxide semiconductor film is to be formed is set to 100° C. or higher and 50° C. or lower. The oxide semiconductor film is formed at a temperature of 0° C. or lower, preferably 200° C. or higher and 350° C. or lower. In this case, it is preferable that the concentration of impurities such as hydrogen or water in the sputtering apparatus is extremely low. For example, by performing heat treatment before the formation of the oxide semiconductor film, In addition, the concentration of impurities such as hydrogen or water in the insulating layer 60 can be reduced. It is preferable that the insulating layer 602_a is flat. For example, the average surface roughness of the insulating layer 602_a is 0.5 It is preferably less than nm, and more preferably 0.1 nm or less.

[0174] In addition, the sputtering target was In2O3:Ga2O3:ZnO=1:1:1. An oxide semiconductor film is formed using an oxide target having a composition ratio of [molar ratio]. For example, In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] The oxide semiconductor film may be formed using an oxide target having the above composition ratio.

[0175] In addition, when a sputtering method is used, for example, under a rare gas (typically argon) atmosphere, The semiconductor layer 603_a is formed in an oxygen atmosphere or in a mixed atmosphere of a rare gas and oxygen. In the case where the semiconductor layer 603_a is formed under a mixed atmosphere of rare gas and oxygen, the rare gas It is preferable that the amount of oxygen is large relative to the amount of water.

[0176] Next, as shown in FIG. 6(D), a second A conductive film is formed, and a part of the second conductive film is etched to form the conductive layer 605a_a and Then, a conductive layer 605b_a is formed.

[0177] For example, a sputtering method or the like is used to form the conductive layer 605a_a and the conductive layer 605b_a. The second conductive film can be formed by forming a film of a material that can be used for the conductive film. By laminating a film of a material applicable to the conductive layer 605a_a and the conductive layer 605b_a, A second conductive film may also be formed.

[0178] Next, as shown in FIG. 6(E), an insulating layer 606_a is formed so as to be in contact with the semiconductor layer 603_a. Form.

[0179] For example, in a rare gas (typically argon) atmosphere, in an oxygen atmosphere, or in a mixture of rare gas and oxygen, In a suitable atmosphere, a film applicable to the insulating layer 606_a is formed by sputtering. In this way, the insulating layer 606_a can be formed. By forming 606_a, it functions as a back channel of a transistor. The decrease in resistance in the semiconductor layer 603_a can be suppressed. The substrate temperature during the formation of 06_a is preferably from room temperature to 300° C. inclusive.

[0180] In addition, before forming the insulating layer 606_a, a plasma treatment using a gas such as N2O, N2, or Ar is performed. A Zuma process is performed to remove adsorbed water and the like adhering to the surface of the exposed semiconductor layer 603_a. In the case where the plasma treatment is performed, the insulating layer 606 may be removed without being exposed to the air. It is preferred to form a.

[0181] In addition, in the example of the method for manufacturing the transistor shown in FIG. Heat treatment is performed at a temperature below 0°C or above 600°C but below the distortion point of the substrate. For example, After forming a semiconductor film, a part of the oxide semiconductor film is etched, and then a second conductive film is formed. After that, after a part of the second conductive film is etched, or after the insulating layer 606_a is formed, The above heat treatment is carried out.

[0182] The heat treatment device for the heat treatment may be an electric furnace or a heating element such as a resistance heating element. A device that heats the workpiece by thermal conduction or thermal radiation from a GR TA (Gas Rapid Thermal Annealing) equipment or LRTA ( RTA (Ra Lamp Rapid Thermal Annealing) equipment pid Thermal Annealing (LRTA) equipment can be used. The lamps are, for example, halogen lamps, metal halide lamps, xenon arc lamps, carbon Light emitted from lamps such as arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps ( The GRTA device is a device that heats the workpiece by radiating high-temperature electromagnetic waves. This is a device that performs heat treatment using gas. The high-temperature gas is, for example, a rare gas or a heating An inert gas (eg, nitrogen) that does not react with the workpiece during the treatment can be used.

[0183] After the above heat treatment, the heating temperature is maintained or the temperature is decreased from the heating temperature. In the process of the heating process, high-purity oxygen gas, high-purity N2O gas, or Alternatively, ultra-dry air (with a dew point of -40°C or less, preferably -60°C or less) may be introduced. In this case, it is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. In addition, the purity of the oxygen gas or N2O gas introduced into the heat treatment device is set to 6N or more, preferably 7N or more. N or more, that is, the impurity concentration in oxygen gas or N2O gas is 1 ppm or less, preferably It is preferable to keep the concentration below 0.1 ppm. Oxygen is supplied to the layer 603_a, reducing defects caused by oxygen deficiency in the semiconductor layer 603_a. The high purity oxygen gas, high purity N2O gas, or ultra-dry air can be used. The introduction may be carried out during the heat treatment.

[0184] After the insulating layer 602_a is formed, an oxide semiconductor film is formed, and then a source electrode or a drain electrode is formed. After forming a conductive layer to be a source electrode or a drain electrode, after forming an insulating layer on the conductive layer to be a source electrode or a drain electrode, or After the heat treatment, an oxygen doping treatment using oxygen plasma may be performed. For example, 2.45 G The oxygen doping process may be performed by using a high-density plasma of 1000 Hz. The oxygen doping treatment may be performed using oxygen. For example, the variation in the electrical characteristics of the oxygen-doped transistor can be reduced. A bonding process is performed to form the insulating layer 602_a and / or the insulating layer 606_a into a stoichiometric Create a state in which there is more oxygen than the composition ratio.

[0185] By making the oxygen in the insulating layer in contact with the semiconductor layer 603_a excessive, the semiconductor layer 603_ Therefore, the semiconductor layer 603_a, the insulating layer 602_a, and the insulating layer 603_b are easily supplied with the Reducing oxygen defects at the interface between one or both of the edge layers 606_a and the semiconductor layer 603_a Therefore, the carrier concentration of the semiconductor layer 603_a can be further reduced. In addition, the present invention is not limited to this, and the oxygen contained in the semiconductor layer 603_a may be excessively removed during the manufacturing process. Even if the semiconductor layer 603_a is exposed to the heat, the insulating layer in contact with the semiconductor layer 603_a prevents the semiconductor layer 603_a from being damaged. It is possible to suppress the desorption of oxygen from a.

[0186] For example, gallium oxide may be used as one or both of the insulating layer 602_a and the insulating layer 606_a. When forming an insulating layer containing gallium oxide, oxygen is supplied to the insulating layer to change the composition of gallium oxide to GaO. x It can be.

[0187] In addition, one or both of the insulating layer 602_a and the insulating layer 606_a may be made of aluminum oxide. When forming an insulating layer containing aluminum oxide, oxygen is supplied to the insulating layer to change the composition of aluminum oxide to Al. 2O x It can be.

[0188] In addition, one or both of the insulating layer 602_a and the insulating layer 606_a may be made of gallium oxide. When forming an insulating layer containing aluminum or aluminum gallium oxide, oxygen is added to the insulating layer. The composition of gallium aluminum oxide or aluminum gallium oxide is Ga x Al2 -x O 3+α It can be said that:

[0189] Through the above steps, hydrogen, water, hydroxyl groups, or hydrides (hydrogenated compounds) are removed from the semiconductor layer 603_a. By removing impurities such as ions (also called "compounds") and supplying oxygen to the semiconductor layer 603_a, As a result, the oxide semiconductor layer can be highly purified.

[0190] Furthermore, in addition to the above heat treatment, after forming the insulating layer 606_a, or heat treatment in an oxygen gas atmosphere (preferably at 200° C. or higher and 600° C. or lower, for example, at 25 0°C or higher and 350°C or lower) may be performed.

[0191] Further, as shown in FIG. 6(E), a third conductive film is formed on the insulating layer 606_a. The conductive film is partly etched to form a conductive layer 608_a.

[0192] For example, a film of a material applicable to the conductive layer 608_a is formed by using a sputtering method. The third conductive film can be formed by the above. Films can also be stacked to form a third conductive film.

[0193] Note that although an example of a method for manufacturing the transistor illustrated in FIG. 5A has been described, the present invention is not limited to this example. For example, among the components shown in FIG. 5B to FIG. 5D, the names of the components shown in FIG. 5A may be the same as those of the components shown in FIG. If the elements are the same as those shown in FIG. 5(A) and at least a part of the functions are the same as those shown in FIG. For example, the description of the example of the method for manufacturing the transistor in FIG. 5A can be referred to as appropriate.

[0194] As shown in FIG. 5C and FIG. 5D, the regions 604a_c and 604a_d In the case where the regions 604b_c to 604b_d are formed, the regions 604b_c to 604b_d function as gates. A semiconductor layer is formed on the side where the conductive layer having the above function is formed through an insulating layer having a function as a gate insulating layer. By adding dopants to the conductor layer, regions 604a_c and 604b are formed in a self-aligned manner. a_d, and regions 604b_c and 604b_d are formed.

[0195] For example, dopants can be added using an ion doping device or an ion implantation device. can.

[0196] As described with reference to FIGS. 5 and 6, an example of a transistor in this embodiment is a gate A conductive layer having a function as a gate, an insulating layer having a function as a gate insulating layer, and a gate A conductive layer having a function as a gate is overlapped with an insulating layer having a function as a gate insulating layer. The oxide semiconductor layer in which a channel is formed and the source A conductive layer that functions as one of a source and a drain and a and a conductive layer having a function as the other of the source and drain.

[0197] The oxide semiconductor layer in which the channel is formed is highly purified to have an i-type or substantially The oxide semiconductor layer is an I-type oxide semiconductor layer. The carrier concentration of the compound semiconductor layer is 1×10 14 / cm 3 Less than 1 x 10 12 / c m 3 less than 1×10 11 / cm 3 It is also possible to make the above By adopting this structure, the off-current per 1 μm of channel width is reduced to 10 aA (1 × 10 -17 A) or less, and further, the off-current per 1 μm of channel width must be kept below 1 aA (1 × 10 - 18 A) or less, and further, the off-current per 1 μm of channel width is to be reduced to 10 zA (1 × 10 -20 A) or less, and further, the off-current per 1 μm of channel width is to be reduced to 1 zA (1 × 10 -21 A) Below Furthermore, the off-current per 1 μm of channel width is reduced to 100 yA (1×10 -22 A) Below The lower the off-state current of the transistor, the better. The lower limit of the off-state current of a transistor in this state is about 10 -30 It is estimated to be A / μm. can be.

[0198] The transistor including the oxide semiconductor layer of this embodiment may be, for example, By using it as a control transistor in a memory device, data retention in a memory cell can be improved. The period can be extended.

[0199] (Embodiment 4) In this embodiment mode, a structural example of the storage device in the above embodiment mode will be described.

[0200] The memory device according to the present embodiment is a semiconductor device having a channel formed therein, the semiconductor device being made of a material selected from the group 14 of the periodic table. A transistor includes a semiconductor layer containing a semiconductor (such as silicon), and a channel is formed. In this case, a channel is formed in the transistor. The transistor including the oxide semiconductor layer is a semiconductor of Group 14 of the periodic table (silicon It can be stacked on a transistor including a semiconductor layer containing the element A transistor that includes a semiconductor layer containing a semiconductor from Group 14 of the periodic table (such as silicon). The transistors are suitable for the transistors in the comparison circuits 101 and 102 in FIG. It is used.

[0201] A transistor containing a semiconductor layer containing a semiconductor of Group 14 of the periodic table (such as silicon). An example of stacking a transistor including an oxide semiconductor layer in which a channel is formed on a transistor is described below. This is shown in Fig. 7. Note that Fig. 7 includes components which are not of actual size.

[0202] In FIG. 7, a semiconductor layer 780, an insulating layer 784a, an insulating layer 784b, and a conductive layer 785a are , a conductive layer 785b, an insulating layer 786a, an insulating layer 786b, an insulating layer 786c, and an insulating layer 786d, an insulating layer 788, a semiconductor layer 753, a conductive layer 754a, and a conductive layer 754b. , an insulating layer 755, a conductive layer 756, an insulating layer 757a, an insulating layer 757b, and an insulating layer 75 8, insulating layer 759, conductive layer 760a, and conductive layer 760b form a A P-channel transistor including a semiconductor layer containing a semiconductor of Group 14 (such as silicon) 2A) and an N-channel transistor (e.g., the transistor 111 shown in FIG. 2A) and an oxide semiconductor in which a channel is formed. A transistor including a conductor layer (e.g., transistor 131 shown in FIG. 2A) is configured. will be done.

[0203] Further, the semiconductor layer 780 includes a region 782a, a region 782b, a region 782c, and a region 78 The semiconductor layer 780 is divided into insulating regions 781a to 781c. , each transistor is electrically isolated.

[0204] The semiconductor layer 780 may be, for example, a semiconductor substrate. Alternatively, the semiconductor layer provided in the semiconductor layer 780 may be used.

[0205] In addition, in the semiconductor layer 780, an insulating isolation region may be provided in the region between the multiple memory cells. stomach.

[0206] The regions 782a and 782b are spaced apart from each other and are doped with a P-type conductivity. The regions 782a and 782b are regions to which a p-type It functions as a source region or drain region of a transistor. For example, region 782 Each of the regions 782a and 782b may be electrically connected to a separately provided conductive layer.

[0207] The regions 782c and 782d are spaced apart from each other and are doped with N-type conductivity. The regions 782c and 782d are regions where a p-type It functions as a source region or drain region of a transistor. For example, region 782 Each of the regions 782c and 782d is a separately provided conductive layer (for example, a layer that functions as a data line). The conductive layer may be electrically connected to the conductive layer having a

[0208] Note that low-concentration regions may be provided in parts of the regions 782a to 782d. The depth of the degree region may be smaller than the depth of the other regions 782a to 782d. Good, but not limited to this.

[0209] The insulating layer 784a is a region of the semiconductor layer 780 sandwiched between the insulating region 781a and the insulating region 781b. The insulating layer 784a is disposed on the region. It has a function as a layer.

[0210] The insulating layer 784b is a region of the semiconductor layer 780 sandwiched between the insulating region 781b and the insulating region 781c. The insulating layer 784b is provided on the region. It has a function as a layer.

[0211] The insulating layer 784a and the insulating layer 784b may be, for example, silicon oxide, silicon nitride, or silicon oxide. Silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride aluminum oxide, aluminum nitride, hafnium oxide, organic insulating materials (e.g. polyimide or The insulating layer 784a and the insulating layer 784b may be made of a material such as acrylic. The insulating layer 784a and the insulating layer 784b are formed by stacking materials applicable to the layer 784b. Good too.

[0212] The conductive layer 785a overlaps with the semiconductor layer 780 with the insulating layer 784a interposed therebetween. The region of the semiconductor layer 780 overlapping the P-channel transistor is the channel formation region of the P-channel transistor. The conductive layer 785a functions as the gate of the P-channel transistor. .

[0213] The conductive layer 785b overlaps with the semiconductor layer 780 with the insulating layer 784b interposed therebetween. The region of the semiconductor layer 780 overlapping the above-mentioned N-channel transistor is the channel formation region. The conductive layer 785b functions as the gate of the N-channel transistor. .

[0214] The conductive layers 785a and 785b can be made of, for example, molybdenum, magnesium, or titanium. , chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium A layer of a metal material such as aluminum or an alloy material containing these as a main component can be used. The conductive layers 785a and 785b are formed by stacking materials applicable to the conductive layers 785a and 785b. The conductive layer 785b may also be formed.

[0215] The insulating layer 786a is provided on the insulating layer 784a and is formed on the conductive layer 785a. It contacts one of the pair of sides facing each other.

[0216] The insulating layer 786b is provided on the insulating layer 784a and is disposed on the opposing surfaces of the conductive layer 785a. The other of the pair of side surfaces facing each other is in contact with the other of the pair of side surfaces facing each other.

[0217] The insulating layer 786c is provided on the insulating layer 784b and is formed on the opposing surfaces of the conductive layer 785b. It contacts one of the pair of sides facing each other.

[0218] The insulating layer 786d is provided on the insulating layer 784b and is formed on the opposing surfaces of the conductive layer 785b. The other of the pair of side surfaces facing each other is in contact with the other of the pair of side surfaces facing each other.

[0219] The insulating layer 788 includes an insulating layer 786a, an insulating layer 786b, an insulating layer 786c, and an insulating layer 786. It is placed on top of d.

[0220] The insulating layers 786a to 786d and the insulating layer 788 include the insulating layer 784a and the insulating layer 784b. Among the materials applicable to the edge layer 784b, the materials applied to the insulating layer 784a and the insulating layer 784b are The insulating layers 786a to 786c may be made of the same material as the insulating layer 786a or different materials. The insulating layers 786a to 786d are stacked with a material suitable for the insulating layer 788. Insulating layer 786d and insulating layer 788 may also be formed.

[0221] The semiconductor layer 753 is provided on the insulating layer 788. The semiconductor layer 753 includes a region 752a and Regions 752a and 752b are doped regions. The dopant is selected from the group consisting of the dopant described above and the dopant functioning as a source region or a drain region. A dopant applicable to the transistor including the oxide semiconductor layer in the embodiment is appropriately used. It is possible.

[0222] The semiconductor layer 753 may be made of a material that can be used for the semiconductor layer 603_a shown in FIG. A layer of the above can be used.

[0223] An insulating layer 755 is provided on the semiconductor layer 753 .

[0224] The insulating layer 755 functions as a gate insulating layer of the transistor.

[0225] The insulating layer 755 may be, for example, a layer of a material applicable to the insulating layer 602_a shown in FIG. In addition, the insulating layer 755 can be formed by stacking materials applicable to the insulating layer 755. may be configured as follows.

[0226] The conductive layer 756 overlaps with the semiconductor layer 753 with the insulating layer 755 interposed therebetween. It functions as the gate of a transistor.

[0227] The conductive layer 756 is, for example, a layer of a material applicable to the conductive layer 601_a shown in FIG. In addition, the conductive layer 756 can be formed by stacking materials applicable to the conductive layer 756. may be configured as follows.

[0228] The insulating layer 757a and the insulating layer 757b are in contact with the side surfaces of the conductive layer 756 and are disposed on the insulating layer 755. It will be established.

[0229] The conductive layer 754a is in contact with and electrically connected to the semiconductor layer 753. The conductive layer 754a is electrically connected to the conductive layer 785a. The gate electrode functions as a source or drain of a transistor.

[0230] The conductive layer 754b is in contact with and electrically connected to the semiconductor layer 753. The conductive layer 754b is electrically connected to the conductive layer 785b. The gate electrode functions as a source or drain of a transistor.

[0231] As the conductive layer 754a and the conductive layer 754b, for example, the conductive layer 605a-605b shown in FIG. A layer of a material applicable to the conductive layer 7a and the conductive layer 605b_a can be used. The conductive layers 754a and 754b are laminated with a material suitable for the conductive layers 754a and 754b. 4b may be constructed.

[0232] The insulating layer 758 is made of the conductive layer 756, the insulating layer 757a, the insulating layer 757b, the conductive layer 754a, and and conductive layer 754b.

[0233] The insulating layer 758 may be, for example, a layer of a material applicable to the insulating layer 602_a shown in FIG. In addition, the insulating layer 758 can be formed by stacking materials applicable to the insulating layer 758. The insulating layer 758 has a function as a protective layer that suppresses the intrusion of impurities. do.

[0234] An insulating layer 759 is provided on top of the insulating layer 758 .

[0235] The insulating layer 759 is, for example, a layer of a material applicable to the insulating layer 602_a shown in FIG. In addition, the insulating layer 759 can be formed by stacking materials that can be used for the insulating layer 759. may be configured as follows.

[0236] The conductive layer 760a is formed on the conductive layer 760 via an opening provided in the insulating layer 758 and the insulating layer 759. The conductive layer 760a is electrically connected to the gate insulating layer 54a of the transistor including an oxide semiconductor layer. It functions as a source or drain.

[0237] The conductive layer 760b is formed on the conductive layer 760 via an opening provided in the insulating layer 758 and the insulating layer 759. The conductive layer 760b is electrically connected to the gate insulating layer 54b of the transistor including an oxide semiconductor layer. It functions as a source or drain.

[0238] As the conductive layer 760a and the conductive layer 760b, for example, the conductive layer 605a-605b shown in FIG. A layer of a material applicable to the conductive layer 7a and the conductive layer 605b_a can be used. The conductive layers 760a and 760b are formed by laminating the applicable material. 0b may be configured.

[0239] The above is an explanation of the example structure of the storage device shown in FIG.

[0240] As described with reference to FIG. 7, in the example of the structure of the memory device according to the present embodiment, By stacking transistors using semiconductor layers, a memory device can be constructed. can be made smaller.

[0241] (Embodiment 5) In this embodiment, an example of a processing unit such as a CPU will be described.

[0242] An example of the arithmetic processing device according to this embodiment will be described with reference to FIG.

[0243] The arithmetic processing device shown in FIG. 8 includes a bus interface (also called IF) 801 and a control device. (also called CTL) 802, a cache memory (also called CACH) 803, and M M is a natural number equal to or greater than 3) A register 804_M), an instruction decoder (also called IDecoder) 805, and an arithmetic logic and an ALU 806.

[0244] The bus interface 801 is used for exchanging signals with the outside and for connecting each circuit in the arithmetic processing unit. It has the function of exchanging signals with the

[0245] The control device 802 has a function of controlling the operation of each circuit in the arithmetic processing device.

[0246] The cache memory 803 is controlled by the control device 802 and is used to For example, the primary cache and secondary cache have the function of temporarily storing data. As a cache, a plurality of cache memories 803 may be provided in the arithmetic processing device. For example, The storage device according to the above embodiment is used as an associative memory in the cache memory 803. This can be done.

[0247] The M registers 804 are controlled by the control device 802 and store data used in arithmetic processing. For example, a register 804 can be used as a register for an arithmetic logic unit 806. 803 may be used as a register for the instruction decoder 805, and another register 804 may be used as a register for the instruction decoder 805.

[0248] The command decoder 805 has a function of translating the command signal that is read. The command signal is input to a control device 802, which then arithmetically generates a control signal in response to the command signal. The signal is output to the processing unit 806.

[0249] The arithmetic logic unit 806 is controlled by the control device 802 and operates in response to input command signals. It has the function of performing calculations using the

[0250] As described with reference to FIG. 8, in the arithmetic processing device according to the present embodiment, By reducing the area of ​​the memory, the area of ​​the processor can be reduced.

[0251] In addition, in one example of the arithmetic processing device according to the present embodiment, the cache memory is By using the storage device in this state, the data stored in the cache memory according to the search data is A function for selecting whether or not to output data can be added to the cache memory.

[0252] In addition, in the arithmetic processing device according to the present embodiment, when the supply of the power supply voltage is stopped, However, the cache memory retains some of the internal data that was there immediately before the supply of power voltage was stopped. When the supply of the power supply voltage is resumed, the state of the arithmetic processing unit can be maintained. Therefore, the supply of the power supply voltage can be selectively stopped and the power supply can be restored to the state immediately before the supply of the power supply voltage was stopped. Even if the power consumption is reduced by the power supply, normal operation will not start until the supply of power voltage is resumed. This can shorten the time it takes to

[0253] (Embodiment 6) In this embodiment, the c-axis is oriented and has a triangular or It has a hexagonal atomic arrangement, and the metal atoms are layered or the metal atoms and oxygen atoms are arranged in layers along the c axis. The layers are arranged in a layered fashion, and the orientation of the a-axis or b-axis is different on the ab plane (rotation around the c-axis Hereinafter, oxides containing the CAAC phase (oxides containing CAAC) will be described.

[0254] In a broad sense, oxides containing CAAC are non-single crystals that are not crystalline when viewed from a direction perpendicular to the ab plane. The atomic arrangement is a triangle, a hexagon, a regular triangle, or a regular hexagon, and the direction perpendicular to the c-axis direction is When viewed from the opposite direction, it is an oxide containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. This refers to.

[0255] CAAC is not a single crystal, but it is not composed of only amorphous matter. AC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is not clearly defined. Sometimes it is not possible to determine with certainty.

[0256] When oxygen is contained in CAAC, a part of the oxygen may be replaced with nitrogen. The c-axes of the individual crystal parts that make up the CAAC are aligned in a certain direction (e.g., the substrate surface on which the CAAC is formed, The CAAC may be aligned in a direction perpendicular to the surface of the CAAC. The normal to the ab plane of the crystal part of the CAAC is in a certain direction (for example, the substrate surface on which the CAAC is formed, C) may be oriented in a direction perpendicular to the surface.

[0257] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Also, depending on the composition, it may be transparent or opaque to visible light. To do.

[0258] An example of such a CAAC is a film-like CAAC that is formed in a direction perpendicular to the film surface or the supporting substrate surface. When observed from the side, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, List crystals in which layered arrangements of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) are observed. It is also possible.

[0259] An example of a crystal structure contained in CAAC will be described in detail with reference to FIGS. 10 to 12, the upward direction is the c-axis direction, and the The plane that is the boundary between the two is called the ab plane. In Figure 10, the circled O represents a 4-coordinate O, and the The circled O indicates a three-coordinate O.

[0260] In Fig. 10(A), one hexacoordinate In atom and six tetracoordinate oxygen atoms (hereafter referred to as 4) adjacent to the In atom are shown. The structure shown here has one metal atom and one nearby oxygen atom. The structure shown in Fig. 10(A) is an octahedral structure, but it is easy to For simplicity, the structure is shown in a plan view. Each small group has four-coordinated O atoms. The small group shown in Figure 10(A) has a zero charge.

[0261] In Figure 10(B), one pentagonal Ga atom and three trigonal oxygen atoms (hereafter referred to as 3) adjacent to the Ga atom are shown. The structure shows a 3-coordinate O and two adjacent 4-coordinate O. In the upper and lower halves of Figure 10(B), there is one tetracoordinate O atom. In addition, since In also has a 5-coordinate structure, it can have the structure shown in FIG. 10(B). The small group shown in B) has a charge of zero.

[0262] FIG. 10(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 10(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. In addition, there are three 4-coordinate Os in the upper half of Figure 10(C) and one 4-coordinate O in the lower half. Coordinated O may be present. The small group shown in Figure 10(C) has a charge of 0.

[0263] FIG. 10(D) shows a structure having one hexacoordinate Sn atom and six tetracoordinate O atoms adjacent to the Sn atom. The upper half of Figure 10(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 10(D) has a charge of +1.

[0264] Figure 10(E) shows a small group containing two Zn atoms. The upper half of Figure 10(E) shows one Zn atom. The small group shown in Figure 10(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0265] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a These are called large groups (also called unit cells).

[0266] Here, we will explain the rules for combining these small groups. The three O's in the upper half of the 6-coordinate In have three adjacent In's in the downward direction, and the three in the lower half Each O has three In neighbors in the upward direction. One O in the upper half of the five-coordinate Ga is It has one adjacent Ga in the downward direction, and one O in the lower half has one adjacent Ga in the upward direction. One O atom in the upper half of the 4-coordinated Zn has one neighboring Zn atom downward, and the three O atoms in the lower half There are three neighboring Zn atoms in the upward direction. Thus, the four-coordinate O atoms in the upward direction of the metal atom The number of adjacent metal atoms below the O is equal to the number of adjacent metal atoms below the O. The number of coordinated O atoms is equal to the number of adjacent metal atoms above the O atoms. Since O atoms are 4-coordinated, The sum of the number of adjacent metal atoms in the downward direction and the number of adjacent metal atoms in the upward direction is 4. Therefore, The number of 4-coordinated O atoms above a metal atom and the number of 4-coordinated O atoms below another metal atom are When the sum of the number of metal atoms is 4, the two small groups containing metal atoms can bond together. For example, a hexacoordinated metal atom (In or Sn) is bonded via a tetracoordinated oxygen atom in the lower half. In this case, there are three tetracoordinated O atoms, so there are five-coordinated metal atoms (Ga or In) or four-coordinated gold atoms. It will bond to one of the group atoms (Zn).

[0267] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinate oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0268] Figure 11(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 11(B) shows a large group consisting of three medium groups. FIG. 11C shows the atomic arrangement when the layer structure of FIG. 11B is observed from the c-axis direction.

[0269] In FIG. 11(A), for simplicity, the tricoordinate O is omitted, and only the number of the tetracoordinate O is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate O atoms, as shown in the circle. Similarly, in FIG. 11(A), the upper and lower halves of In are Each has one 4-coordinate O atom, which is shown as 1 in a circle. ) in which the lower half has one tetracoordinate O and the upper half has three tetracoordinate O. n and Zn, which has one tetrahedral O atom in the upper half and three tetrahedral O atoms in the lower half. It shows.

[0270] In FIG. 11(A), the middle group, which is composed of an In-Sn-Zn-O system layer structure, is Sn has three tetracoordinate O atoms in the upper half and one in the lower half, and Sn has one tetracoordinate O atom in the upper half. The In bonds to the Zn with three tetracoordinate O in the upper half. The Zn is bonded to the upper half and the lower half of the Zn via one tetracoordinate O. It bonds to In in the lower half, and the In is transferred to two Zn atoms with one tetrahedral O in the upper half. The small group is bonded to a tetracoordinate O atom via one tetracoordinate O atom in the lower half of the small group. The structure is such that three O are bonded to Sn in the upper half and three Sn in the lower half. Multiple units are combined to form larger groups.

[0271] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.66. 7, -0.5. For example, In (6 or 5 coordinates), Zn (4 coordinates ), Sn (5- or 6-coordinate) have charges of +3, +2, and +4, respectively. Therefore, S The small group containing n has a charge of +1. Therefore, to form a layer structure containing Sn, A charge of -1 is required to cancel the charge of +1. The structure that takes the charge of -1 is shown in Figure 10 (E As shown in Fig. 1, there are two small groups containing Zn. For example, there are small groups containing Sn. If there is one small group containing two Zn atoms for each group, the charges are cancelled out. , the total charge of the layer structure can be zero.

[0272] Specifically, the large group shown in FIG. 11(B) is repeated to form the In-Sn-Zn In-Sn-ZnO crystals (In2SnZn3O8) can be obtained. -The layered structure of the Zn-O system is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) It can be expressed by the following formula:

[0273] In addition, there are also four-component metal oxides, such as In-Sn-Ga-Zn-O metal oxides. and In-Ga-Zn-O metal oxide (also written as IGZO), which is an oxide of a ternary metal. ), In-Al-Zn-O metal oxides, Sn-Ga-Zn-O metal oxides, A In-Ga-Zn-O metal oxides, Sn-Al-Zn-O metal oxides, In-Hf- Zn-O metal oxide, In-La-Zn-O metal oxide, In-Ce-Zn-O gold Metal oxides, In-Pr-Zn-O metal oxides, In-Nd-Zn-O metal oxides, I n-Sm-Zn-O metal oxide, In-Eu-Zn-O metal oxide, In-Gd-Z nO-based metal oxides, In-Tb-Zn-O-based metal oxides, In-Dy-Zn-O-based metals Oxides, In-Ho-Zn-O metal oxides, In-Er-Zn-O metal oxides, In -Tm-Zn-O metal oxide, In-Yb-Zn-O metal oxide, In-Lu-Zn -O-based metal oxides, binary metal oxides such as In-Zn-O-based metal oxides, Sn-Z nO metal oxide, Al-Zn-O metal oxide, Zn-Mg-O metal oxide, Sn -Mg-O based metal oxides, In-Mg-O based metal oxides, and In-Ga-O based metal oxides In-O-based metal oxides, Sn-O-based metal oxides, Zn-O-based metal oxides, etc. The same applies when metal oxides or the like are used.

[0274] For example, Figure 12(A) shows a model of the middle group consisting of an In-Ga-Zn-O layer structure. A diagram of the rule is shown.

[0275] In FIG. 12(A), the middle group, which is made up of an In-Ga-Zn-O-based layer structure, is In the upper half and lower half, there are three tetracoordinate O atoms, and in the lower half, there is one tetracoordinate O atom. It bonds to a certain Zn, and one of the four-coordinate O atoms is connected to the lower half of the Zn via the three four-coordinate O atoms. It bonds to Ga in the upper and lower halves of the two, and through one tetracoordinate O in the lower half of the Ga. In this structure, three tetracoordinate O atoms are bonded to In atoms in the upper and lower halves. Multiple groups combine to form larger groups.

[0276] Figure 12(B) shows a large group consisting of three medium groups. Figure 12(C) shows 12B is observed from the c-axis direction.

[0277] Here, the charges of In (6 or 5 coordinates), Zn (4 coordinates), and Ga (5 coordinates) are respectively Since the charge levels are +3, +2, and +3, the small group containing In, Zn, and Ga is Therefore, if these small groups are combined, the total of the medium groups will be The charge is always 0.

[0278] The middle group, which is made up of an In-Ga-Zn-O-based layer structure, is shown in FIG. Not limited to the middle group, large-scale combination of middle groups with different arrangements of In, Ga, and Zn Groups are also possible.

[0279] (Embodiment 7) In this embodiment, the field-effect mobility of a transistor will be described.

[0280] The field effect mobility of insulated gate transistors, not limited to oxide semiconductors, is actually measured as However, due to various reasons, the mobility becomes lower than it should be. The factors that reduce the mobility are There are defects inside the semiconductor and at the interface between the semiconductor and the insulating film, but the Levinson model Using this method, we can theoretically derive the field effect mobility assuming that there are no defects inside the semiconductor. Can.

[0281] The inherent mobility of the semiconductor is μ0, and the measured field-effect mobility is μ. Assuming the existence of potential barriers (such as grain boundaries), this can be expressed by the following equation:

[0282]

number

[0283] where E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. In addition, if we assume that the potential barrier originates from defects, the Levinson model gives , expressed by the following formula:

[0284]

number

[0285] Here, e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the is the dielectric constant, n is the number of carriers contained in the channel per unit area, and Cox is the where V is the gate voltage, and t is the channel thickness. In the case of a semiconductor layer, the thickness of the channel may be the same as the thickness of the semiconductor layer. The drain current Id in is expressed by the following formula:

[0286]

number

[0287] Here, L is the channel length and W is the channel width, where L=W=10 μm. Also, Vd is the drain voltage. Dividing both sides of the above equation by Vg and then taking the logarithm of both sides gives , the result is as follows:

[0288]

number

[0289] The right-hand side of equation 5 is a function of Vg. As can be seen from this equation, the vertical axis is ln(Id / Vg), The defect density N can be calculated from the slope of the line with the horizontal axis being 1 / Vg. The defect density can be evaluated from the Id-Vg characteristics of the oxide semiconductor. In the case where the ratio of In, tin (Sn), and zinc (Zn) is In:Sn:Zn=1:1:1, The defect density N is 1×10 12 / cm 2 That's about it.

[0290] Based on the defect density thus obtained, equations 2 and 3 are used to calculate μ0 = 120 cm 2 / Vs The mobility measured in the defective In-Sn-Zn oxide is 35 cm 2 / V However, oxide semiconductors without defects inside the semiconductor or at the interface between the semiconductor and the insulating film Body mobility μ0 is 120cm 2 It can be expected that / Vs.

[0291] However, even if there are no defects inside the semiconductor, the electrons may be scattered at the interface between the channel and the gate insulating layer. The transport properties of the transistor are affected by the interface between the channel and the gate insulating layer. The mobility μ1 at a distance x from the target is expressed by the following equation:

[0292]

number

[0293] Here, D is the electric field in the gate direction, and B and G are constants. B and G are determined from actual measurement results. From the above measurement results, B = 4.75 × 10 7 cm / s, G=10n m (depth of interface scattering). As D increases (i.e., gate voltage increases), It can be seen that the mobility μ1 decreases because the second term of Equation 6 increases.

[0294] Mobility of a transistor using an ideal oxide semiconductor channel with no internal defects The results of calculating μ2 are shown in Figure 13. The calculation was performed using a Synopsys device simulator. Sentaurus Device is a software that can be used to measure the bandgap of oxide semiconductors. The top, electron affinity, dielectric constant, and thickness are 2.8 eV, 4.7 eV, and These values ​​were measured for thin films formed by sputtering. This was obtained by

[0295] In addition, the work functions of the gate, source, and drain are set to 5.5 eV and 4.6 eV, respectively. The gate insulating layer had a thickness of 100 nm and a dielectric constant of 4.6 eV. was set to 4.1. The channel length and width were both 10 μm, and the drain voltage Vd was 0. It is 1V.

[0296] As shown in Figure 13, the mobility is 100 cm at a gate voltage of just over 1 V. 2 Peaks above / Vs However, if the gate voltage is increased further, the interface scattering increases and the mobility decreases. In order to reduce interface scattering, the surface of the semiconductor layer must be flattened at the atomic level (At omic layer flatness is preferred.

[0297] The characteristics of a miniaturized transistor manufactured using an oxide semiconductor having such mobility are as follows: The results of the calculation of the characteristics are shown in FIG. 14 to FIG. 16. The structure of the transistor shown in FIG. + Conductivity type of The semiconductor region 2103a and the semiconductor region 2103c are The resistivity of the conductor region 2103c is 2×10 -3 Let it be Ωcm.

[0298] The transistor shown in FIG. 17A includes a base insulating layer 2101 and a A buried insulating material 2102 made of aluminum oxide is formed on the buried insulating material 2102. The transistor is made up of a semiconductor region 2103a, a semiconductor region 2103c, and a semiconductor region 2103b sandwiched therebetween. The gate 2105 and an intrinsic semiconductor region 2103 b serving as a channel formation region are provided. The width of the gate 2105 is set to 33 nm.

[0299] Between the gate 2105 and the semiconductor region 2103b, there is a gate insulating layer 2104. On both sides of the gate 2105, there are sidewall insulators 2106a and 2106b. On the top of 105, there is an insulator 2107 to prevent short circuit between the gate 2105 and other wiring. The width of the sidewall insulator is set to 5 nm. In contact with 2103c, a source 2108a and a drain 2108b are provided. The channel width of the transistor is set to 40 nm.

[0300] The transistor shown in FIG. 17B has a base insulating layer 2101 and a thin film transistor made of aluminum oxide. A semiconductor region 2103a and a semiconductor region 2103c are formed on the buried insulator 2102. The intrinsic semiconductor region 2103b is sandwiched between the gate 2105 and the gate 2106. The sidewall insulator 2106a and the sidewall insulator 2106b and the insulator 2107 are 17A in that it has a source 2108a and a drain 2108b. It is the same as .

[0301] The transistor shown in FIG. 17(A) and the transistor shown in FIG. 17(B) differ in that the sidewall insulation The conductivity type of the semiconductor region under the edge 2106a and the sidewall insulator 2106b. In the transistor shown in FIG. 2, the semiconductor under the sidewall insulator 2106a and the sidewall insulator 2106b is The body region is n + The semiconductor regions 2103a and 2103c have the same conductivity type. In the transistor shown in FIG. 17B, the intrinsic semiconductor region 2103b is the intrinsic semiconductor region 2103b. The semiconductor region 2103a (semiconductor region 2103c) and the gate 2105 overlap by Loff. This area is called the offset area, and its width Loff is the offset. As is clear from the figure, the offset length is the sidewall insulator 2106a (sidewall insulator The width of the second slit is equal to the width of the first slit (2106b).

[0302] The other parameters used in the calculation are as described above. We used the Sentaurus Device simulation software. Figure 14 shows the The drain current (Id, solid line) and mobility ( μ, dotted line) on the gate voltage (Vg, potential difference between the gate and source). Id is the drain voltage (potential difference between the drain and source) of +1V, and the mobility μ is the drain The voltage is calculated as +0.1V.

[0303] FIG. 14(A) shows a gate insulating layer with a thickness of 15 nm, and FIG. 14(B) shows a gate insulating layer with a thickness of 10 nm. In Fig. 14(C), the thickness is set to 5 nm. The gate insulating layer becomes thinner. As the temperature increases, the drain current Id (off-state current) in the off state drops significantly. There is no noticeable change in the peak value of μ or the drain current Id (on-state current) in the on-state. It was shown that the drain current exceeded 10 μA at a gate voltage of around 1 V.

[0304] FIG. 15 shows a transistor having the structure shown in FIG. 17B, in which the offset length Loff is set to 5n Dependence of drain current Id (solid line) and mobility μ (dotted line) on gate voltage Vg for m The drain current Id is calculated by setting the drain voltage to +1V, and the mobility μ is calculated by setting the drain voltage to + The calculation was performed with the gate insulating layer thickness set to 15 nm. FIG. 15(B) shows a case where the thickness is 10 nm, and FIG. 15(C) shows a case where the thickness is 5 nm. It is something.

[0305] FIG. 16 shows the offset length Loff The gate voltage dependence of the drain current Id (solid line) and the mobility μ (dotted line) for the 15 nm The drain current Id is the drain voltage +1V, and the mobility μ is the drain voltage The calculation was performed with the gate insulating layer thickness set to +0.1V. FIG. 16(B) is for 10 nm, and FIG. 16(C) is for 5 nm. This is what was done.

[0306] In both cases, the thinner the gate insulating layer, the more significantly the off-state current decreases, while the peak of the mobility μ There is no noticeable change in the on-state current or the on-state voltage.

[0307] In addition, the peak of the mobility μ is 80 cm in FIG. 2 / Vs, but in Figure 15, cm 2 / Vs, 40 cm in Figure 16 2 As / Vs and offset length Loff increase, The off-current also has a similar tendency. On the other hand, the on-current decreases with increasing offset length Lo It decreases as ff increases, but the decrease is much slower than the decrease in the off-current. In addition, it was shown that the drain current exceeded 10 μA at a gate voltage of around 1 V. .

[0308] (Embodiment 8) In this embodiment, an oxide semiconductor containing In, Sn, and Zn as main components is used. The transistors used will be described.

[0309] A transistor that uses an oxide semiconductor containing In, Sn, and Zn as its main components for the channel formation region is The oxide semiconductor film is formed by heating the substrate. By forming the layer and then performing heat treatment, good characteristics can be obtained. An element that is contained in a mixture at a concentration of 5 atomic % or more.

[0310] Intentionally heating the substrate after forming an oxide semiconductor film mainly composed of In, Sn, and Zn Therefore, it is possible to improve the field effect mobility of the transistor. It is possible to positively shift the threshold voltage of the transistor and make it normally off.

[0311] For example, Figs. 18(A) to (C) show a semiconductor device with a channel length L of 3 μm, which is mainly composed of In, Sn, and Zn. The oxide semiconductor film has a channel width W of 10 μm and a gate insulating layer with a thickness of 100 nm. These are the characteristics of the transistors used. Note that Vd was set to 10V.

[0312] Figure 18(A) shows a sputtering method in which the main components In, Sn, and Zn were deposited on the substrate without intentionally heating it. The field-effect mobility (field effect mobility) of the transistor is shown in FIG. Degree is 18.8cm 2 On the other hand, the substrate was intentionally heated to obtain In, S By forming an oxide semiconductor film mainly composed of n and Zn, it is possible to improve the field effect mobility. FIG. 18(B) shows the formation of a GaN film mainly composed of In, Sn, and Zn by heating the substrate to 200°C. The transistor characteristics when an oxide semiconductor film is formed are shown. The field-effect mobility is 32.2 cm 2 / Vsec is obtained.

[0313] The field effect mobility was measured by forming an oxide semiconductor film mainly composed of In, Sn, and Zn and then performing heat treatment. Fig. 18(C) shows the results of the experiments using In, Sn, and Zn The oxide semiconductor film mainly composed of is formed by sputtering at 200°C, and then heat-treated at 650°C. The transistor characteristics are shown below. In this case, the field effect mobility is 34.5 cm 2 / V sec is obtained.

[0314] By intentionally heating the substrate, moisture is absorbed into the oxide semiconductor film during sputtering. In addition, by performing a heat treatment after the film formation, the effect of reducing the amount of oxidation can be expected. Hydrogen, hydroxyl groups, or moisture can be released and removed from the compound semiconductor film, as described above. Such an improvement in the field effect mobility can be achieved by dehydration. Not only does hydrogenation and dehydrogenation remove impurities, but the interatomic distances become shorter due to the increased density. It is also estimated that crystallization can be promoted by removing impurities from an oxide semiconductor and purifying it. Such a highly purified non-single-crystal oxide semiconductor can be ideally 0cm 2 It is estimated that it will be possible to achieve a field effect mobility of more than 1 / Vsec.

[0315] Oxygen ions are implanted into an oxide semiconductor whose main components are In, Sn, and Zn, and the oxide is then converted into The hydrogen, hydroxyl groups, or moisture contained in the oxide semiconductor is released, and the heat treatment is performed simultaneously or in conjunction with the heat treatment. The oxide semiconductor may be crystallized by subsequent heat treatment. By the crystallization treatment, a non-single-crystal oxide semiconductor with good crystallinity can be obtained.

[0316] The effect of intentionally heating the substrate during film formation and / or heat treatment after film formation is that the electric field This not only improves the effective mobility but also contributes to making the transistor normally off. The oxide semiconductor, which is mainly composed of In, Sn, and Zn, was formed without intentionally heating the substrate. A transistor with a conductive film as the channel formation region has a negative shift in threshold voltage. However, when an oxide semiconductor film is used that is formed by intentionally heating a substrate, In this case, the negative shift of the threshold voltage is eliminated. This tendency is shown in Figures 18(A) and 18(B). ) can also be confirmed by comparing

[0317] The threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. It is possible to obtain a transistor with a composition ratio of In:Sn:Zn=2:1:3. In addition, the composition ratio of the target is In:Sn:Zn By adjusting the ratio of the carbon nanotube diameter to the carbon nanotube diameter, an oxide semiconductor film with high crystallinity can be obtained.

[0318] The intentional substrate heating temperature or heat treatment temperature is 150° C. or higher, preferably 200° C. or higher. The temperature is preferably 400° C. or higher. By forming the film or performing heat treatment at a higher temperature, the transistor can be easily formed. This makes it possible to make the resistor normally off.

[0319] In addition, the gate bianode can be formed by intentionally heating the substrate and / or by carrying out heat treatment after the film formation. It can improve the stability against ass-stress. For example, 2MV / cm, 150℃ , and 1 hour application, the drift is less than ±1.5V, preferably 1.0V You can get less than that.

[0320] In fact, Sample 1 was not subjected to heat treatment after the oxide semiconductor film was formed, and Sample 2 was subjected to heat treatment at 650° C. The BT test was performed on the transistor of sample 2 that had been subjected to the above.

[0321] First, the substrate temperature was set to 25°C, Vd was set to 10V, and the Vg-Id characteristics of the transistor were measured. Next, the substrate temperature was set to 150°C and Vd was set to 0.1 V. Next, the gate insulating layer was Apply 20V to Vg so that the applied electric field strength is 2MV / cm, and leave it as it is for 1 hour. Next, Vg was set to 0 V. Next, the substrate temperature was set to 25° C., Vd was set to 10 V, and the The Vg-Id of the transistor was measured. This is called the Plus BT test.

[0322] Similarly, first, set the substrate temperature to 25°C, Vd to 10V, and measure the Vg-Id characteristics of the transistor. Next, the substrate temperature was set to 150°C and Vd was set to 0.1V. Next, the gate Apply -20V to Vg so that the electric field strength applied to the insulating layer is -2MV / cm. The substrate temperature was then set to 25°C and Vd was set to 1 The Vg-Id of the transistor was measured at 0 V. This is called a negative BT test.

[0323] The results of the positive BT test of sample 1 are shown in FIG. 19(A), and the results of the negative BT test are shown in FIG. The results of the positive BT test of sample 2 are shown in FIG. 20(A), and the results of the negative BT test are shown in FIG. The results are shown in Figure 20(B).

[0324] The threshold voltage shifts of sample 1 due to the positive BT test and the negative BT test were 1 The positive and negative BT tests of sample 2 were also The experimental threshold voltage shifts were 0.79 V and 0.76 V, respectively. In both samples 1 and 2, the change in threshold voltage before and after the BT test was small, indicating high reliability. It can be seen that.

[0325] The heat treatment can be carried out in an oxygen atmosphere, but it is first carried out in a nitrogen or inert gas atmosphere, or under reduced pressure. It is also possible to perform heat treatment in an atmosphere containing oxygen after performing heat treatment in the atmosphere containing oxygen. By adding oxygen to the oxide semiconductor after oxidation, the effect of the heat treatment can be further improved. To add oxygen later, oxygen ions can be accelerated by an electric field and then added to the oxide semiconductor film. An injection method may also be applied.

[0326] Defects due to oxygen vacancies are easily generated in oxide semiconductors and at the interface with the stacked films. By making the oxide semiconductor contain excess oxygen through such heat treatment, The excess oxygen is mainly contained in the interstitial The oxygen concentration is 1×10 16 / cm 3 More than 2×10 20 / cm 3 If the above conditions are met, the compound can be incorporated into the oxide semiconductor without causing distortion or the like to the crystal. .

[0327] In addition, by making the oxide semiconductor contain crystals at least in part through heat treatment, For example, when the composition ratio of In:Sn:Zn=1, a more stable oxide semiconductor film can be obtained. The oxide film was sputtered using a 1:1 target without intentionally heating the substrate. The semiconductor film was found to have a halo pattern by X-ray diffraction (XRD). The oxide semiconductor film thus formed is crystallized by heat treatment. The heat treatment temperature can be selected as desired, but for example, by performing heat treatment at 650°C, X-ray A clear diffraction peak can be observed by diffraction.

[0328] In fact, we performed XRD analysis of the In-Sn-Zn-O film. Using the AXS X-ray diffraction device D8 ADVANCE, the out-of-plane method was used. Measured.

[0329] Samples A and B were prepared for XRD analysis. A method for producing the above will be described.

[0330] An In-Sn-Zn-O film was formed to a thickness of 100 nm on a dehydrogenated quartz substrate. .

[0331] The In-Sn-Zn-O film was formed by sputtering in an oxygen atmosphere at a power of 100 W ( The target was In:Sn:Zn=1:1:1 [atomic ratio]. An n-Sn-Zn-O target was used. The substrate heating temperature during film formation was 200°C. The sample thus prepared was designated as sample A.

[0332] Next, a sample prepared in the same manner as sample A was subjected to a heat treatment at a temperature of 650°C. The heat treatment is first performed in a nitrogen atmosphere for one hour, and then in an oxygen atmosphere without lowering the temperature. The sample was then subjected to an additional heat treatment for 1 hour.

[0333] Figure 23 shows the XRD spectra of sample A and sample B. In sample A, the peaks derived from crystals In sample B, 2θ was observed at around 35 deg and 37 deg to 38 deg. A peak derived from crystals was observed.

[0334] In this way, oxide semiconductors mainly composed of In, Sn, and Zn are intentionally heated during film formation. and / or by subjecting the film to heat treatment after deposition, the characteristics of the transistor can be improved. Cut.

[0335] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. In other words, it has the effect of preventing oxides from being included in the film or removing them from the film. By removing hydrogen, which acts as a donor impurity in semiconductors, high purification can be achieved. This allows the transistor to be normally off, and the oxide semiconductor is highly purified. By this, the off-current can be reduced to 1 aA / μm or less. The unit indicates the current value per 1 μm of channel width.

[0336] Figure 24 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. For simplicity, the reciprocal of the substrate temperature during measurement is multiplied by 1000 (1000 / T) is the horizontal axis.

[0337] Specifically, as shown in FIG. 24, when the substrate temperature is 125° C., the current is 1 aA / μm (1×1 0 -18 A / μm) or less, and at 85°C it is 100zA / μm (1×10 -19 A / μm ) or less, and at room temperature (27°C), it is 1zA / μm (1×10 -21 A / μm or less Preferably, the resistance is 0.1 aA / μm (1×10 -19 A / μ m) or less at 85°C, -20 A / μm) at room temperature At 0.1zA / μm (1×10 -22 These can be reduced to less than 100 A / μm. The off-state current is extremely low compared to that of a transistor using Si as a semiconductor film. It is clear that

[0338] However, in order to prevent hydrogen and moisture from being mixed into the oxide semiconductor film during the formation of the film, The leakage from the deposition chamber and the outgassing from the inner walls of the deposition chamber are sufficiently suppressed, and the sputtering gas is highly purified. For example, it is preferable that the sputtering gas has a dew point of -70°C or lower so that moisture is not included in the film. It is preferable to use a gas that is within the range of 1000 to 2000 nm. It is preferable to use a target that has been highly purified so that it does not contain any impurities. Oxide semiconductors that are mainly composed of In, Sn, and Zn can be heat-treated to remove moisture from the film. However, the temperature at which moisture is released is higher than that of oxide semiconductors whose main components are In, Ga, and Zn. Therefore, it is preferable to form a film that does not contain moisture from the beginning.

[0339] In addition, in the case of the sample transistor that was subjected to heat treatment at 650° C. after the formation of the oxide semiconductor film, The relationship between the substrate temperature and the electrical characteristics was evaluated.

[0340] The transistor used for the measurement had a channel length L of 3 μm, a channel width W of 10 μm, and Lov The thickness is 0 μm and dW is 0 μm. Vd is 10 V. The substrate temperature is -40°C. The tests were performed at temperatures of -25°C, 25°C, 75°C, 125°C and 150°C. In this case, the width of the overlap between the gate electrode and the pair of electrodes is called Lov, and the width of the overlap between the gate electrode and the pair of electrodes is called Lov. The protrusion of the pair of electrodes is called dW.

[0341] FIG. 21 shows the Vg dependence of Id (solid line) and field effect mobility (dotted line). Fig. 22(A) shows the relationship between the substrate temperature and the threshold voltage, and Fig. 22(B) shows the relationship between the substrate temperature and the field effect mobility. Show the relationship.

[0342] From FIG. 22(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The range was 1.09V to -0.23V from -40℃ to 150℃.

[0343] Moreover, from FIG. 22(B), it can be seen that the higher the substrate temperature, the lower the field effect mobility. The range is -40℃ to 150℃ and the temperature is 36cm 2 / Vs~32cm 2 / Vs. Therefore, it is understood that the fluctuation of the electrical characteristics is small within the above-mentioned temperature range.

[0344] The above-mentioned oxide semiconductor mainly composed of In, Sn, and Zn is used as a channel forming region. According to the transistor, the field effect mobility is increased to 30c while keeping the off-current below 1aA / μm. m 2 / Vsec or more, preferably 40cm 2 / Vsec or more, preferably 60cm 2 / Vsec or more, and the on-current value required by the LSI can be satisfied. For example, A FET with L / W=33nm / 40nm, gate voltage 2.7V, drain voltage 1.0V When the on-state current is 12μA or more, the on-state current required for the transistor to operate is 12μA or more. Even in a wide temperature range, sufficient electrical characteristics can be ensured. For example, a transistor made of oxide semiconductor is embedded in an integrated circuit made of silicon semiconductor. Even if the chip is used in a large number of chips, it is possible to realize an integrated circuit with new functions without sacrificing the operating speed. Cut.

[0345] An example of a transistor using an In-Sn-Zn-O film as an oxide semiconductor film is shown below. explain.

[0346] Figure 25 shows the top of a coplanar top-gate top-contact transistor. FIG. 25(A) shows a top view of a transistor. FIG. 25(B) shows a top view of a transistor. 25(A) shows a cross section AB corresponding to the dashed line AB in FIG. 25(A).

[0347] The transistor shown in FIG. 25B includes a substrate 1200 and a base film provided over the substrate 1200. An insulating layer 1202, a protective insulating film 1204 provided around the base insulating layer 1202, and a base A high resistance region 1206a and a low resistance region 1206b are provided on the insulating layer 1202 and the protective insulating film 1204. The oxide semiconductor film 1206 having the region 1206b and the a gate insulating layer 1208 and an oxide semiconductor film 1206 with the gate insulating layer 1208 interposed therebetween; A gate electrode 1210 is provided so as to overlap with the gate electrode 1210. A pair of electrodes are provided in contact with at least the low resistance region 1206b. At least an oxide semiconductor film 1206, a gate electrode 1210, and a pair of electrodes An interlayer insulating film 1216 is provided to cover the insulating film 1214, and an opening is provided in the interlayer insulating film 1216. A wiring 1218 is provided so as to be connected to at least one of a pair of electrodes 1214 via the opening. , has.

[0348] Although not shown, a protective film is provided to cover the interlayer insulating film 1216 and the wiring 1218. By providing the protective film, the surface conduction of the interlayer insulating film 1216 can be prevented. This can reduce the minute leakage current that occurs due to the gate insulating film, and can reduce the off-state current of the transistor. This can be done.

[0349] In addition, a transistor using an In-Sn-Zn-O film as an oxide semiconductor film, which is different from the above, was Another example will be described.

[0350] FIG. 26 is a top view and a cross-sectional view illustrating a structure of a transistor. FIG. 26(B) is a cross-sectional view corresponding to the dashed line AB in FIG. 26(A). FIG.

[0351] The transistor shown in FIG. 26B includes a substrate 1600 and a base film provided over the substrate 1600. An insulating layer 1602, an oxide semiconductor film 1606 provided over the base insulating layer 1602, and an oxide A pair of electrodes 1614 in contact with the oxide semiconductor film 1606, A gate insulating layer 1608 is provided on the electrode 1614, and an oxide semiconductor layer is formed on the gate insulating layer 1608. A gate electrode 1610 is provided so as to overlap the nitride semiconductor film 1606, and a gate insulating layer 160 is provided. An interlayer insulating film 1616 is provided to cover the gate electrode 1610 and the insulating film 161 6, a wiring 1618 connected to a pair of electrodes 1614 through an opening provided in the and a protective film 1620 provided to cover the film 1616 and the wiring 1618.

[0352] The substrate 1600 is a glass substrate, the base insulating layer 1602 is a silicon oxide film, and The compound semiconductor film 1606 is an In-Sn-Zn-O film, and the pair of electrodes 1614 is A tungsten film is used as the gate insulating layer 1608, a silicon oxide film is used as the gate electrode 161, 0 is a laminated structure of a tantalum nitride film and a tungsten film, and the interlayer insulating film 1616 is The layer structure is a silicon oxynitride film and a polyimide film, and the wiring 1618 is a titanium film. The laminated structure in which an aluminum film and a titanium film are formed in this order is used as the protective film 1620. A polyimide film was used, respectively.

[0353] In the transistor having the structure shown in FIG. 26A, a gate electrode 1610 and a pair of electrodes The width of the overlap with the electrode 1614 is called Lov. The protrusion of the counter electrode 1614 is called dW.

[0354] (Embodiment 9) In this embodiment, an example of an electronic device including the arithmetic processing device in the above embodiment will be described. explain.

[0355] Configuration examples of electronic devices in this embodiment will be described with reference to FIGS. Reveal.

[0356] The electronic device shown in FIG. 9(A) is an example of a portable information terminal. The terminal includes a housing 1001a and a display unit 1002a provided in the housing 1001a. do.

[0357] The side surface 1003a of the housing 1001a is provided with a connection terminal for connecting to an external device. One or more of the buttons for operating the portable information terminal shown in A) may be provided. .

[0358] The portable information terminal shown in FIG. 9A includes a CPU, a memory circuit, and an external An interface that transmits and receives signals between the internal equipment and the CPU and memory circuit, and an interface that transmits and receives signals between the internal equipment and the CPU and memory circuit and an antenna for transmitting and receiving signals.

[0359] The portable information terminal shown in FIG. 9(A) is, for example, a telephone, an electronic book, a personal computer, etc. , and has the function of one or more of the gaming machines.

[0360] The electronic device shown in FIG. 9(B) is an example of a folding portable information terminal. The portable information terminal includes a housing 1001b and a display unit 1002b provided in the housing 1001b. a housing 1004; a display unit 1005 provided on the housing 1004; a housing 1001b; and a shaft portion 1006 that connects to the housing 1004.

[0361] In the portable information terminal shown in FIG. 9B, the shaft portion 1006 is connected to the housing 1001b or the housing By moving the body 1004, the housing 1001b can be superimposed on the housing 1004. do.

[0362] In addition, a side surface 1003b of the housing 1001b or a side surface 1007 of the housing 1004 is connected to an external device. A connection terminal for connecting the device to the mobile information terminal shown in FIG. 9(B) and a button for operating the mobile information terminal shown in FIG. One or more may be provided.

[0363] Also, the display unit 1002b and the display unit 1005 may display different images or a series of images. The display unit 1005 is not necessarily provided. Alternatively, a keyboard may be provided as an input device.

[0364] The portable information terminal shown in FIG. 9B includes a CPU and a processor in a housing 1001b or a housing 1004. A memory circuit and an interface for transmitting and receiving signals between an external device and the CPU and memory circuit. In addition, the portable information terminal shown in FIG. An antenna may also be provided.

[0365] The portable information terminal shown in FIG. 9B is, for example, a telephone, an electronic book, a personal computer, , and has the function of one or more of the gaming machines.

[0366] The electronic device shown in FIG. 9C is an example of a stationary information terminal. The terminal includes a housing 1001c and a display unit 1002c provided in the housing 1001c. do.

[0367] The display unit 1002c may be provided on the deck portion 1008 of the housing 1001c. do.

[0368] The stationary information terminal shown in FIG. 9C includes a CPU and a memory circuit in a housing 1001c. and an interface for transmitting and receiving signals between an external device and the CPU and memory circuit. In addition, an antenna for transmitting and receiving signals to and from the outside is attached to the stationary information terminal shown in FIG. It may be provided.

[0369] Furthermore, a ticket is attached to a side surface 1003c of a housing 1001c of a stationary information terminal shown in FIG. One or more of a ticket output section, a coin insertion section, and a bill insertion section that output the above may be provided.

[0370] The stationary information terminal shown in FIG. 9(C) is, for example, an automated teller machine, a device for ordering tickets, etc. It also functions as an information and communication terminal (also called a multimedia station) for the purpose of playing games. Yes.

[0371] FIG. 9(D) is an example of a stationary information terminal. The stationary information terminal shown in FIG. 9(D) has a housing 1. The display unit 1002d is provided on the housing 1001d. A support stand may be provided to support 1001d.

[0372] The side surface 1003d of the housing 1001d is provided with a connection terminal for connecting to an external device. D) One or more buttons for operating the stationary information terminal may be provided. .

[0373] In addition, the stationary information terminal shown in FIG. 9(D) includes a CPU and a memory circuit in a housing 1001d. and an interface for transmitting and receiving signals between an external device and the CPU and memory circuit. In addition, an amplifier for transmitting and receiving signals to and from the outside may be provided in the stationary information terminal shown in FIG. A retainer may be provided.

[0374] The stationary information terminal shown in FIG. 9(D) is, for example, a digital photo frame, a monitor, or a television. It functions as a vision device.

[0375] The arithmetic processing device of the above embodiment is a CPU of the electronic device shown in FIG. 9(A) to FIG. 9(D). It is used as such.

[0376] As described with reference to FIG. 9, an example of the electronic device according to the present embodiment includes a The configuration includes the arithmetic processing device according to the embodiment.

[0377] By using the above configuration, the information in the electronic device can be periodically read even when the power is not supplied. This allows the time from when power is supplied until normal operation begins quickly. In addition, power consumption can be reduced. [Explanation of symbols]

[0378] 101 Comparison circuit 102 Comparison circuit 111 Transistor 112 Transistor 121 Transistor 122 Transistor 131 Transistor 201 Memory Cell 202 Transistor 203 Transistor 204 Buffer 205 Buffer 600 Device formation layer 601 Conductive layer 602 Insulating layer 603 Semiconductor Layer 604a area 604b area 605a Conductive layer 605b conductive layer 606 Insulating layer 608 Conductive layer 751 Conductive layer 752 Insulation layer 752a area 752b area 753 Semiconductor Layer 754a conductive layer 754b Conductive layer 755 Insulation Layer 756 Conductive Layer 757a Insulating layer 757b Insulating layer 758 Insulating layer 759 Insulation Layer 760a Conductive layer 760b conductive layer 761a Insulating layer 761b Insulating layer 780 Semiconductor Layer 781a Insulation Area 781b Insulation Area 781c Insulation Area 782a area 782b area 782c area 782d area 783a area 783b area 784a Insulating layer 784b Insulating layer 785a conductive layer 785b Conductive layer 786a Insulating layer 786b Insulating layer 786c Insulating layer 786d Insulating layer 788 Insulation Layer 801 Bus Interface 802 Control device 803 Cache Memory 804 Register 805 Instruction Decoder 806 Arithmetic Logic Unit 1001a Case 1001b Case 1001c Case 1001d case 1002a Display section 1002b Display section 1002c Display section 1002d Display section 1003a side 1003b Side 1003c side 1003d side 1004 Case 1005 Display section 1006 Shaft 1007 Side 1008 Deck section 1200 Board 1202 Undercoat insulation layer 1204 Protective insulating film 1206 Oxide Semiconductor Film 1206a High resistance area 1206b Low resistance region 1208 Gate Insulation Layer 1210 Gate electrode 1212 Sidewall insulating film 1214 Electrode 1216 Interlayer insulating film 1218 Wiring 1600 Board 1602 Undercoat insulation layer 1606 Oxide semiconductor film 1608 Gate insulation layer 1610 Gate electrode 1614 Electrode 1616 Interlayer insulating film 1618 Wiring 1620 Protective film 2101 Undercoat insulation layer 2102 Insulation 2103a Semiconductor area 2103b Semiconductor area 2103c Semiconductor area 2104 Gate insulation layer 2105 Gate 2106a Sidewall insulation 2106b Sidewall insulation 2107 Insulation 2108a Source 2108b Drain

Claims

1. A first transistor and a second transistor, A semiconductor device in which one of a source and a drain of the first transistor is always electrically connected to a gate of the second transistor, an oxide semiconductor layer and first to fifth conductive layers; the first transistor has a channel formation region in the oxide semiconductor layer, the first conductive layer functions as a gate of the first transistor and has a region located above the oxide semiconductor layer; the second conductive layer functions as one of a source and a drain of the first transistor and has a region located above the oxide semiconductor layer; the third conductive layer functions as the other of the source and the drain of the first transistor and has a region located above the oxide semiconductor layer; the fourth conductive layer is disposed above the second conductive layer and is always in electrical contact with the second conductive layer; the fifth conductive layer functions as a gate of the second transistor; the fifth conductive layer has a region disposed below the second conductive layer; the oxide semiconductor layer has a region disposed above an insulating layer having a region facing a side surface of the fifth conductive layer; a region of the second conductive layer that is in contact with the fourth conductive layer overlaps with the fifth conductive layer; Semiconductor device.

2. A first transistor, a second transistor, and a capacitor element, the capacitance element is always electrically connected to the gate of the second transistor; A semiconductor device in which one of a source and a drain of the first transistor is always electrically connected to a gate of the second transistor, an oxide semiconductor layer and first to fifth conductive layers; the first transistor has a channel formation region in the oxide semiconductor layer, the first conductive layer functions as a gate of the first transistor and has a region located above the oxide semiconductor layer; the second conductive layer functions as one of a source and a drain of the first transistor and has a region located above the oxide semiconductor layer; the third conductive layer functions as the other of the source and the drain of the first transistor and has a region located above the oxide semiconductor layer; the fourth conductive layer is disposed above the second conductive layer and is always in electrical contact with the second conductive layer; the fifth conductive layer functions as a gate of the second transistor; the fifth conductive layer has a region disposed below the second conductive layer; the oxide semiconductor layer has a region disposed above an insulating layer having a region facing a side surface of the fifth conductive layer; a region of the second conductive layer that is in contact with the fourth conductive layer overlaps with the fifth conductive layer; Semiconductor device.

3. A first transistor and a second transistor, A semiconductor device in which one of a source and a drain of the first transistor is always electrically connected to a gate of the second transistor, an oxide semiconductor layer and first to fifth conductive layers; the first transistor has a channel formation region in the oxide semiconductor layer, the first conductive layer functions as a gate of the first transistor and has a region located above the oxide semiconductor layer; the second conductive layer functions as one of a source and a drain of the first transistor and has a region located above the oxide semiconductor layer; the third conductive layer functions as the other of the source and the drain of the first transistor and has a region located above the oxide semiconductor layer; the fourth conductive layer is disposed above the second conductive layer and is always in electrical contact with the second conductive layer; the fifth conductive layer functions as a gate of the second transistor; the fifth conductive layer has a region disposed below the second conductive layer; the second conductive layer has a region separated from the oxide semiconductor layer and in contact with the fifth conductive layer; the oxide semiconductor layer has a region disposed above an insulating layer having a region facing a side surface of the fifth conductive layer; a region of the second conductive layer that is in contact with the fourth conductive layer overlaps with the fifth conductive layer; Semiconductor device.

4. A first transistor, a second transistor, and a capacitor element, the capacitance element is always electrically connected to the gate of the second transistor; A semiconductor device in which one of a source and a drain of the first transistor is always electrically connected to a gate of the second transistor, an oxide semiconductor layer and first to fifth conductive layers; the first transistor has a channel formation region in the oxide semiconductor layer, the first conductive layer functions as a gate of the first transistor and has a region located above the oxide semiconductor layer; the second conductive layer functions as one of a source and a drain of the first transistor and has a region located above the oxide semiconductor layer; the third conductive layer functions as the other of the source and the drain of the first transistor and has a region located above the oxide semiconductor layer; the fourth conductive layer is disposed above the second conductive layer and is always in electrical contact with the second conductive layer; the fifth conductive layer functions as a gate of the second transistor; the fifth conductive layer has a region disposed below the second conductive layer; the second conductive layer has a region separated from the oxide semiconductor layer and in contact with the fifth conductive layer; the oxide semiconductor layer has a region disposed above an insulating layer having a region facing a side surface of the fifth conductive layer; a region of the second conductive layer that is in contact with the fourth conductive layer overlaps with the fifth conductive layer; Semiconductor device.

5. In any one of claims 1 to 4, a region of the oxide semiconductor layer that overlaps with the first conductive layer is separated from a region of the oxide semiconductor layer that overlaps with the second conductive layer in a cross-sectional view of the first transistor in a channel length direction, a region of the oxide semiconductor layer overlapping with the first conductive layer is separated from a region of the oxide semiconductor layer overlapping with the third conductive layer in a cross-sectional view of the first transistor in a channel length direction. Semiconductor device.

6. In any one of claims 1 to 5, the oxide semiconductor layer has an oxide semiconductor that is an In—O-based metal oxide; Semiconductor device.

Images