Control program, control method, and control system

Abstract

To suppress performance deterioration of an application.SOLUTION: A control system 100 refers to profile information 110 indicating variation in latency accompanying an increase of bandwidths used by memories 102 and 103 to determine respective target latencies and target bandwidths of the memories 102 and 103 on the basis of current latencies of the memories 102 and 103 so that a difference between latencies of the memories 102 and 103 is eliminated. On the basis of access frequencies per unit time of respective pages allocated to applications in the memories 102 and 103, the control system 100 calculates estimated bandwidths for the respective pages in the memories 102 and 103 at the determined target latencies of the memories 102 and 103 . On the basis of the calculated estimated bandwidths for the respective pages, the control system 100 changes allocation of pages in the memories 102 and 103 so as to satisfy the target bandwidths of the memories 102 and 103.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a control program, a control method, and a control system. [Background technology]

[0002] Memory bandwidth is a resource shared by applications in a system. Because high-bandwidth memory such as HBM (High Bandwidth Memory) is expensive, CXL (Compute Express Link) memory, which can expand memory bandwidth while keeping costs down by combining it with local node memory, is attracting attention.

[0003] Prior art includes techniques for scheduling memory requests for issue to two different memory types, and a controller receiving a data write request from a processor external to the HBM generating an indication that the data bus is available for operation during the cycle time of the data write request based on the data write request including sparse data or data value similarity.

[0004] Also, there is a high-bandwidth memory system including an HBM device and a logic circuit that converts a command received from a host device into an in-memory processing command that is sent to the HBM device via an interface. Also, there is a technology that receives a memory write request to a physical address in a system memory by a compression memory controller, generates a compression indicator (CI) for the write data based on a compression pattern of the write data, and updates a master directory and ECC bits of the physical address with the generated CI. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Special Publication No. 2021-507399 [Patent Document 2] JP 2020-184338 A [Patent Document 3] US Patent Application Publication No. 2021 / 0117103 [Patent Document 4] US Patent Application Publication No. 2015 / 0339239 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the conventional technology, when multiple applications are running, contention for the system's memory bandwidth may occur, increasing memory access latency and degrading application performance.

[0007] In one aspect, the present invention aims to suppress degradation of application performance. [Means for solving the problem]

[0008] In one embodiment, a control program is provided that refers to profile information indicating a change in latency associated with an increase in the bandwidth used for each of a plurality of types of memories having different transmission paths to a CPU, and determines a target latency and target bandwidth for each of the memories based on the current latency of each of the memories so as to eliminate the latency difference for each of the memories; calculates an estimated bandwidth for each page in each of the memories at the determined target latency for each of the memories based on the number of accesses per unit time for each page assigned to each application in each of the memories; and changes the arrangement of the pages in each of the memories based on the calculated estimated bandwidth for each page so as to satisfy the determined target bandwidth for each of the memories. Effect of the Invention

[0009] Advantageous Effects of Invention According to one aspect of the present invention, an effect is achieved in that degradation of application performance can be suppressed. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is an explanatory diagram illustrating an example of a control method according to an embodiment. [Diagram 2] FIG. 2 is an explanatory diagram showing an example of the system configuration of the system 200. As shown in FIG. [Diagram 3] FIG. 3 is a block diagram showing an example of the hardware configuration of the node 201. As shown in FIG. [Figure 4] FIG. 4 is an explanatory diagram (part 1) showing a specific example of profile information. [Diagram 5] FIG. 5 is an explanatory diagram (part 2) showing a specific example of profile information. [Figure 6] FIG. 6 is an explanatory diagram (part 3) showing a specific example of profile information. [Figure 7] FIG. 7 is a block diagram showing an example of the functional configuration of the node 201. As shown in FIG. [Figure 8] FIG. 8 is an explanatory diagram (part 1) showing an example of bandwidth control of the node 201. In FIG. [Figure 9] FIG. 9 is an explanatory diagram (part 2) showing an example of bandwidth control of the node 201. In FIG. [Figure 10] FIG. 10 is an explanatory diagram showing an example of determining a target latency and a target bandwidth. [Figure 11] FIG. 11 is an explanatory diagram (part 1) showing a specific example of information on the number of accesses per second. [Figure 12] FIG. 12 is an explanatory diagram (part 2) showing a specific example of the access count per second information. [Figure 13] FIG. 13 is an explanatory diagram showing a specific example of the application use bandwidth information. [Figure 14] FIG. 14 is an explanatory diagram showing an example of an estimated bandwidth for each page. [Figure 15] FIG. 15 is an explanatory diagram showing an example of latency control. [Figure 16] FIG. 16 is a flowchart showing an example of a bandwidth control process procedure of the node 201. [Figure 17]FIG. 17 is a flowchart illustrating an example of a specific processing procedure of the target latency / target bandwidth determination processing. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a control program, a control method, and a control system according to the present invention will be described in detail with reference to the accompanying drawings.

[0012] (Embodiment) Fig. 1 is an explanatory diagram showing an example of a control method according to an embodiment. In Fig. 1, a control system 100 is a computer system including a CPU (Central Processing Unit) 101 and multiple types of memories having different transmission paths to the CPU 101, and controlling the bandwidth of each of the multiple types of memories. Here, the multiple types of memories are two types of memories 102 and 103.

[0013] Of the two types of memories 102 and 103, memory 102 (first memory) is, for example, a local memory. Memory 103 (second memory) is, for example, a CXL (Compute Express Link) memory. The local memory is a memory that is locally connected to a CPU (for example, CPU 101). The CXL memory is a memory that is connected via CXL, which is an interconnect standard that connects between a CPU (for example, CPU 101) and memories, etc.

[0014] Here, when multiple applications are running in a system, the total ideal memory bandwidth each application wants to use may exceed the memory bandwidth of the entire system, resulting in memory bandwidth contention. Memory bandwidth represents, for example, the amount of data that can be transferred between a CPU and memory per unit time. When memory bandwidth contention occurs, memory access latency increases significantly, resulting in a decrease in application performance.

[0015] To solve the memory bandwidth contention problem, CXL memory, which can be introduced at a lower cost than the expensive HBM, has been attracting attention. With CXL memory, memories connected via CXL can be used using normal physical address space, and by combining it with local memory, for example, it is possible to expand the memory capacity and memory bandwidth of the entire system.

[0016] However, CXL memory tends to have longer latency (memory access latency) than local memory. Latency is the time (delay time) from when an access request (read / write command) is issued until the result is obtained. For example, latency is the time from when a read command is issued until the data is actually prepared.

[0017] For example, the CXL memory is used as a hierarchical memory including a local memory and a CXL memory, and is connected to the CPU via a transmission path different from that of the local memory. In this case, which memory to allocate which page of the running application to is important for the performance of the application.

[0018] For example, it is conceivable to allocate pages of highly important applications to local memory, and allocate pages that are used for background processing and do not cause problems even if they are slow to load in CXL memory.Specifically, for example, when the memory capacity load is high, there is a conventional technology that moves pages of local memory to CXL memory without swapping them to disk, thereby securing free space, while allocating hot pages with high access frequency to local memory.

[0019] However, in the conventional technology, by allocating hot pages to local memory, contention for memory bandwidth may occur even if the total memory bandwidth of the entire system is not exceeded. When contention for memory bandwidth occurs, memory access latency increases, and the performance of the application (page) placed in the local memory may decrease.

[0020] In addition, the conventional technology cannot control the memory bandwidth by changing the layout of pages. For example, the conventional technology does not know the amount of memory bandwidth used by accessing each page, so it is not possible to predict the amount of memory bandwidth that will change due to the rearrangement of pages, and therefore it is not possible to control the memory bandwidth.

[0021] Therefore, in this embodiment, a control method is described in which the bandwidth (memory bandwidth) used by each page is estimated, and pages are arranged so as to control the latency of each of the memories 102 and 103, thereby suppressing the degradation of application performance. Below, a process example (corresponding to the following processes (1) to (3)) of the control system 100 is described.

[0022] (1) The control system 100 refers to the profile information 110 and determines the target latency and target bandwidth of each of the memories 102, 103 so as to eliminate the latency difference between the memories 102, 103 based on the current latency of each of the memories 102, 103. Here, the profile information 110 represents the change in latency associated with an increase in the used bandwidth of each of the memories 102, 103.

[0023] The usage bandwidth of each memory 102, 103 is the memory bandwidth used by each memory 102, 103, and is represented, for example, by the sum of the memory bandwidths that applications running using each memory 102, 103 wish to use. The latency is memory access latency, and represents, for example, the time from when a read command is given to each memory 102, 103 until the data is actually prepared.

[0024] The profile information 110 is created in advance by measuring the latency under load on each of the memories 102, 103, for example, at the time of initial startup of the control system 100. The target latency is the target latency of each of the memories 102, 103, and corresponds to the latency at the target bandwidth. The target bandwidth is the target memory bandwidth of each of the memories 102, 103, and is determined to be, for example, a value that does not cause contention of the memory bandwidth.

[0025] Specifically, for example, the control system 100 measures the current latency of each of the memories 102 and 103. Next, the control system 100 determines a target latency for each of the memories 102 and 103 based on the measured current latency of each of the memories 102 and 103 such that the latency difference between the memories 102 and 103 is eliminated.

[0026] For example, the control system 100 may determine a latency intermediate between the current latency of the memory 102 and the current latency of the memory 103 as the target latency of each of the memories 102 and 103. Then, the control system 100 refers to the profile information 110 and determines the usage bandwidth corresponding to the determined target latency of each of the memories 102 and 103 as the target bandwidth of each of the memories 102 and 103.

[0027] The target latency and target bandwidth of each of the memories 102 and 103 are determined, for example, when the current latency of the memory 102 becomes greater than the current latency of the memory 103. However, in normal times when no bandwidth contention is occurring, the memory 103 tends to have a greater memory access latency than the memory 102 due to differences in the transmission path to the CPU 101, etc.

[0028] In the example of FIG. 1, it is assumed that the current latency of memory 102 is greater than the current latency of memory 103, and a target latency and a target bandwidth for each of memories 102 and 103 have been determined.

[0029] (2) The control system 100 calculates an estimated bandwidth for each page in each memory 102, 103 at the determined target latency for each memory 102, 103, based on the number of accesses per unit time for each page assigned to each application in each memory 102, 103. The estimated bandwidth corresponds to the memory bandwidth used for accessing each page.

[0030] Here, the number of accesses per unit time for each page indicates how many times each page was accessed (read / written) per unit time. For example, a value equivalent to the current specification bandwidth per unit time for each page can be obtained by multiplying the number of accesses per unit time for each page by the cache line size. The cache line size indicates the size of data to be stored in the cache. The cache line size is determined, for example, according to the specifications of the CPU 101.

[0031] It is also assumed that the memory bandwidth available for each page increases as the latency of each of the memories 102 and 103 increases, whereas it is assumed that the memory bandwidth available for each page decreases as the latency of each of the memories 102 and 103 decreases.

[0032] Therefore, the control system 100 may calculate an estimated bandwidth for each page based on a first value and a second value. The first value is a value obtained by multiplying the number of accesses per unit time for each page by the cache line size. The second value represents a ratio of the current latency of each memory 102, 103 to the target latency of each memory 102, 103. The estimated bandwidth is calculated to be larger in proportion to the second value, for example.

[0033] In addition, when a state where memory bandwidth contention occurs is transitioned to a state where memory bandwidth contention does not occur, it is expected that the used bandwidth will increase. Therefore, the control system 100 may calculate an estimated bandwidth for each page based on the first value, the second value, and the third value.

[0034] The third value is a value representing the ratio of the bandwidth used by each application when it is executed alone to the current bandwidth used by each application in each memory 102, 103. The estimated bandwidth is calculated, for example, so as to be larger in proportion to the third value. The bandwidth used by each application when it is executed alone is obtained in advance, for example, by analyzing the performance of past executions or the bandwidth used when each application is executed using data specified by the user.

[0035] 1, for example, pages 121-124 allocated to application App0 and pages 125-127 allocated to application App2 are arranged in memory 102. Furthermore, for example, pages 131-133 allocated to application App1 and pages 134 and 135 allocated to application App3 are arranged in memory 103. In this case, an estimated bandwidth is calculated for each of pages 121-127 and 131-135.

[0036] (3) Based on the calculated estimated bandwidth for each page, the control system 100 changes the allocation of pages in each of the memories 102, 103 so as to satisfy the determined target bandwidth for each of the memories 102, 103. Specifically, for example, the control system 100 refers to the profile information 110 and identifies the current usage bandwidth of each of the memories 102, 103 from the current latency of each of the memories 102, 103.

[0037] Then, the control system 100 changes the allocation of pages based on the estimated bandwidth for each page so that the used bandwidth of each of the memories 102 and 103 becomes the target bandwidth. To explain in more detail, for example, the control system 100 may move a page from the memory 102 to the memory 103 or move a page from the memory 103 to the memory 102 so that the used bandwidth completely matches the target bandwidth.

[0038] 1, it is assumed that moving pages 121 and 127 from memory 102 to memory 103 satisfies the target bandwidth of each of memories 102 and 103. In this case, the control system 100 changes the allocation of pages 121 and 127 from memory 102 to memory 103.

[0039] In this way, according to the control system 100, by controlling the bandwidth (memory bandwidth) used by each memory 102, 103, it is possible to prevent an increase in latency (memory access latency) due to bandwidth contention and suppress a decrease in application performance.

[0040] 1, when the latency of memory 102 (e.g., local memory) becomes greater than that of memory 103 (e.g., CXL memory) due to bandwidth contention of memory 102, the control system 100 can move pages 121 and 127 from memory 102 to memory 103 to adjust the latency of each of memories 102 and 103. This enables the control system 100 to suppress a decrease in performance of applications App0 and App2 caused by an increase in latency due to bandwidth contention.

[0041] (System configuration example of system 200) Next, a system configuration example of a system 200 including the control system 100 shown in Fig. 1 will be described. Here, a case where the control system 100 shown in Fig. 1 is applied to a node 201 in the system 200 will be described as an example.

[0042] Fig. 2 is an explanatory diagram showing an example of a system configuration of a system 200. In Fig. 2, the system 200 includes a node 201 and a plurality of client devices 202. In the system 200, the node 201 and the client devices 202 are connected via a wired or wireless network 210. The network 210 is, for example, the Internet, a local area network (LAN), or a wide area network (WAN).

[0043] Here, the node 201 is a computer system that executes various applications. The node 201 also has a function of controlling the bandwidth (memory bandwidth) of each memory (for example, a local memory 310 and a CXL memory 320 shown in FIG. 3 described later). The node 201 is, for example, a server.

[0044] The client device 202 is a computer used by a user of the system 200. The user is, for example, a person who executes various applications using the system 200. The user may also be an administrator of the system 200. The client device 202 is, for example, a PC (Personal Computer), a tablet PC, or the like.

[0045] In this embodiment, the node 201 and the client device 202 are provided separately, but the present invention is not limited to this. For example, the node 201 may be realized by the client device 202. Furthermore, the system 200 may include a plurality of nodes 201.

[0046] (Example of hardware configuration for node 201) Next, an example of the hardware configuration of the node 201 will be described.

[0047] Fig. 3 is a block diagram showing an example of a hardware configuration of a node 201. In Fig. 3, the node 201 has a CPU 301, a memory 302, a communication I / F (Interface) 303, a disk drive 304, and a disk 305. In addition, each component is connected to each other via a bus 300.

[0048] Here, the CPU 301 is responsible for the overall control of the node 201. The CPU 301 may have multiple cores. The CPU 101 shown in Fig. 1 corresponds to the CPU 301, for example. The memory 302 includes, for example, a read only memory (ROM), a random access memory (RAM), and a flash ROM.

[0049] For example, the flash ROM stores an OS (Operating System) program, the ROM stores application programs, and the RAM is used as a work area for the CPU 301. The programs stored in the memory 302 are loaded into the CPU 301 to cause the CPU 301 to execute the coded processes.

[0050] In the following description, a "local memory 310" and a "CXL memory 320" are taken as examples of multiple types of memories having different transmission paths to the CPU 301.

[0051] The memory 302 includes a local memory 310 and a CXL memory 320. The local memory 310 and the CXL memory 320 have different transmission paths (e.g., memory buses) to the CPU 301. The local memory 310 and the CXL memory 320 are realized by, for example, a dynamic random access memory (DRAM). The memories 102 and 103 shown in FIG. 1 correspond to, for example, the local memory 310 and the CXL memory 320.

[0052] The communication I / F 303 is connected to the network 210 through a communication line, and is connected to an external computer (e.g., the client device 202 shown in FIG. 2) via the network 210. The communication I / F 303 manages the interface between the network 210 and the inside of the device, and controls input and output of data from the external computer. The communication I / F 303 is, for example, a modem or a LAN adapter.

[0053] The disk drive 304 controls reading / writing of data from / to the disk 305 under the control of the CPU 301. The disk 305 stores data written under the control of the disk drive 304. The disk 305 is, for example, a magnetic disk, an optical disk, or the like.

[0054] In addition to the above-mentioned components, node 201 may have, for example, an input device, a display, a portable recording medium I / F, a portable recording medium, etc. Also, client device 202 shown in Fig. 2 can be realized with the same hardware configuration as node 201. However, client device 202 has, for example, an input device, a display, etc. in addition to the above-mentioned components.

[0055] (Examples of profile information) Next, a specific example of the profile information used by the node 201 will be described. First, a specific example of the profile information in the local memory 310 shown in FIG.

[0056] Fig. 4 is an explanatory diagram (part 1) showing a specific example of profile information. In Fig. 4, profile information 400 is information that indicates a change in latency accompanying an increase in the bandwidth used by the local memory 310. The bandwidth used by the local memory 310 is the memory bandwidth used by the local memory 310.

[0057] In the profile information 400, the increase in latency of the local memory 310 becomes large once the bandwidth usage exceeds "120 GB / s."

[0058] Next, a specific example of the profile information in the CXL memory 320 shown in FIG. 3 will be described with reference to FIG.

[0059] Fig. 5 is an explanatory diagram (part 2) showing a specific example of profile information. In Fig. 5, profile information 500 is information that indicates a change in latency accompanying an increase in the bandwidth used by the CXL memory 320. The bandwidth used by the CXL memory 320 is the memory bandwidth used by the CXL memory 320.

[0060] In the profile information 500, the increase in latency of the CXL memory 320 becomes large once the bandwidth usage exceeds "60 GB / s."

[0061] The profile information 400, 500 shown in FIG. 4 and FIG. 5 is created by measuring the latency when a load is applied to each memory (local memory 310, CXL memory 320) at a timing such as the initial startup of the node 201, for example.

[0062] Next, a specific example of profile information of an application will be described with reference to Fig. 6. An application is an application to be executed in the node 201. The application to be executed may be specified by the user of the client device 202, for example.

[0063] Fig. 6 is an explanatory diagram (part 3) showing a specific example of profile information. In Fig. 6, profile information 600 is information that indicates the bandwidth used by each application. The application name is the name of the application. The bandwidth used is the bandwidth used when each application is executed alone.

[0064] The bandwidth used by each application corresponds to the maximum memory bandwidth used by each application. The profile information 600 is created, for example, by analyzing the bandwidth used when each application is executed using the past execution results of each application and data specified by the user.

[0065] (Example of functional configuration of node 201) Next, an example of the functional configuration of the node 201 will be described.

[0066] FIG. 7 is a block diagram showing an example of a functional configuration of the node 201. In FIG. 7, the node 201 includes an acquisition unit 701, a determination unit 702, a calculation unit 703, and an arrangement unit 704. The acquisition unit 701 to the arrangement unit 704 are functions that constitute the control unit 700, and specifically, the functions are realized by, for example, having the CPU 301 execute a program stored in a storage device such as the memory 302 or the disk 305 shown in FIG. 3, or by the communication I / F 303. To explain in more detail, for example, each functional unit is realized by the kernel of the OS. The processing results of each functional unit are stored in a storage device such as the memory 302 or the disk 305.

[0067] In the following description, the local memory 310 may be simply referred to as "memory 310," and the CXL memory 320 may be simply referred to as "memory 320."

[0068] The acquiring unit 701 acquires profile information of each of the memories 310, 320. Here, the profile information of each of the memories 310, 320 is information that indicates a change in latency accompanying an increase in the bandwidth used by each of the memories 310, 320. The profile information of the memory 310 is, for example, the profile information 400 shown in Fig. 4. Moreover, the profile information of the memory 320 is, for example, the profile information 500 shown in Fig. 5.

[0069] Specifically, for example, the acquiring unit 701 may acquire the profile information 400, 500 by creating it in its own node. Also, the acquiring unit 701 may acquire the profile information 400, 500 by receiving it from the client device 202 shown in Fig. 2. Also, the acquiring unit 701 may acquire the profile information 400, 500 by, for example, a user's operation input using an input device (not shown).

[0070] The acquiring unit 701 also acquires profile information of each application. Here, the profile information of each application is information that indicates the bandwidth used by each application. The profile information of each application is, for example, the profile information 600 shown in FIG. 6.

[0071] Specifically, for example, the acquiring unit 701 may acquire the profile information 600 by creating it in its own node. Also, the acquiring unit 701 may acquire the profile information 600 by receiving it from the client device 202 shown in Fig. 2. Also, the acquiring unit 701 may acquire the profile information 600 by, for example, a user's operation input using an input device (not shown).

[0072] The determination unit 702 refers to the acquired profile information of each of the memories 310, 320, and determines the target latency and target bandwidth of each of the memories 310, 320 based on the current latency of each of the memories 310, 320 so that the latency difference between the memories 310, 320 is eliminated.

[0073] Here, the target latency is the target latency of each memory 310, 320, and corresponds to the latency at the target bandwidth. The target bandwidth is the target memory bandwidth of each memory 310, 320, and is determined to be, for example, a value that does not cause contention of the memory bandwidth in each memory 310, 320.

[0074] Specifically, for example, the determination unit 702 measures the current latency of each of the memories 310 and 320. For example, when contention for memory bandwidth occurs in the local memory 310, the latency of the local memory 310 tends to be greater than the latency of the CXL memory 320.

[0075] Therefore, the determination unit 702 may determine whether the measured current latency of the local memory 310 is greater than the measured current latency of the CXL memory 320. Here, if the current latency of the local memory 310 is equal to or less than the current latency of the CXL memory 320, the determination unit 702 may not need to determine the target latency and the target bandwidth.

[0076] On the other hand, if the current latency of the local memory 310 is greater than the current latency of the CXL memory 320, the determination unit 702 determines the target latency of each of the memories 310, 320 based on the measured current latency of each of the memories 310, 320 so as to eliminate the latency difference between the memories 310, 320. However, the target latency of the local memory 310 is determined to be smaller than the current latency of the local memory 310.

[0077] For example, assume that under normal circumstances, an operation is performed in which frequently accessed pages are preferentially allocated to the local memory 310 using existing technology. In this case, for example, when bandwidth contention occurs in the local memory 310, the frequently accessed page may be moved to the CXL memory 320 by bandwidth control by the node 201. In this case, if the target latency of the CXL memory 320 is made significantly larger (longer) than that of the local memory 310, the performance of the application of the frequently accessed page may be degraded. For this reason, the determination unit 702 determines the target latency so as to eliminate the latency difference between the memories 310, 320.

[0078] To explain in more detail, for example, the determination unit 702 may determine a latency intermediate between the current latency of the local memory 310 and the current latency of the CXL memory 320 as the target latency of each of the memories 310, 320. Then, the determination unit 702 refers to the profile information of each of the memories 310, 320, and determines the usage bandwidth corresponding to the determined target latency of each of the memories 310, 320 as the target bandwidth of each of the memories 310, 320.

[0079] The target latency of each memory 310, 320 does not have to be the same. For example, the determination unit 702 may determine the target latency of the local memory 310 to be a predetermined value lower than the target latency of the CXL memory 320. Also, the case where the target latency and the target bandwidth are determined when the current latency of the local memory 310 is higher than the current latency of the CXL memory 320 has been described as an example, but this is not limiting. For example, the determination unit 702 may determine the target latency and the target bandwidth when the measured current latency of the local memory 310 is equal to or higher than a threshold value. The threshold value can be set arbitrarily.

[0080] The calculation unit 703 calculates an estimated bandwidth for each page in each memory 310, 320 when the determined target latency for each memory 310, 320 is achieved, based on the number of accesses per unit time for each page in each memory 310, 320 assigned to each application.

[0081] Specifically, for example, the calculation unit 703 acquires the current number of accesses per unit time for each page allocated to each application in each of the memories 310 and 320. The number of accesses per unit time for each page may be measured by the calculation unit 703, or may be measured by a memory management unit (MMU) (not shown).

[0082] For example, if the unit time is "1 second," the current number of accesses per page per unit time may be the number of accesses to each page in the most recent second, or the current number of accesses per page per unit time may be the average number of accesses per second to each page in the past 10 seconds.

[0083] To explain in more detail, for example, the calculation unit 703 may acquire information 1100, 1200 of the number of accesses per second as shown in Fig. 11 and Fig. 12, which will be described later. The information 1100, 1200 of the number of accesses per second indicates the number of accesses per second for each page allocated to each application in each memory 310, 320.

[0084] The calculation unit 703 may then calculate an estimated bandwidth for each page in each of the memories 310, 320 based on the first value and the second value. Here, the first value is a value obtained by multiplying the number of accesses per unit time for each page by the cache line size. The cache line size is set in advance according to the specifications of the CPU 301, for example. The second value represents a ratio of the current latency of each of the memories 310, 320 to the determined target latency of each of the memories 310, 320.

[0085] Furthermore, the calculation unit 703 may calculate an estimated bandwidth for each page in each of the memories 310, 320 based on the first value, the second value, and the third value. Here, the third value is a value representing a ratio of a bandwidth used by each application when it is executed alone to a current bandwidth used by each application in each of the memories 310, 320.

[0086] The bandwidth used by each application when it is executed alone is identified, for example, from the profile information of each application that has been acquired. The current bandwidth used by each application may be measured, for example, by the calculation unit 703, or may be measured by an MMU (not shown). To explain in more detail, for example, the calculation unit 703 may acquire application bandwidth information 1300 as shown in FIG. 13 that will be described later. The application bandwidth information 1300 indicates the current bandwidth used by each application in each memory 310, 320.

[0087] Furthermore, the calculation unit 703 may calculate an estimated bandwidth for each page in each of the memories 310, 320 based on the first value, the second value, the third value, and the fourth value. The fourth value is a value that represents a performance difference between the memories 310, 320. The performance difference between the memories 310, 320 is, for example, a read / write speed or a memory capacity. The fourth value is set in advance for each of the memories 310, 320, taking into account, for example, the performance difference between the memories 310, 320.

[0088] More specifically, for example, the calculation unit 703 can calculate the estimated bandwidth for each page in each memory 310, 320 using the following formula (1). Here, the estimated bandwidth is the estimated bandwidth of each page. The number of accesses per second is the current number of accesses per unit time of each page. S is the cache line size. The bandwidth used during standalone execution is the bandwidth used during standalone execution of the application corresponding to each page. The current bandwidth used is the current bandwidth used by the application corresponding to each page. The current latency is the current latency of the memory in which each page is located. The target latency is the target latency of the memory in which each page is located. The correction value represents the performance difference between the memories 310, 320.

[0089] Estimated bandwidth = number of accesses per second × S × bandwidth used when running alone / current bandwidth used × current latency / target latency × correction value (1)

[0090] "Number of accesses per second x S" in the above formula (1) corresponds to the first value. "Current latency / target latency" in the above formula (1) corresponds to the second value. "Bandwidth used during standalone execution / current bandwidth used" in the above formula (1) corresponds to the third value. "Correction value" in the above formula (1) corresponds to the fourth value.

[0091] However, the correction value is set for each of the memories 310 and 320. For example, if there is no difference in performance between the memories 310 and 320, the correction values ​​for both memories 310 and 320 are set to "1." Also, assume that the local memory 310 has higher memory performance than the CXL memory 320. In this case, for example, the correction value for the local memory 310 is set to "1," and the correction value for the CXL memory 320 is set to a value greater than 1.

[0092] Based on the calculated estimated bandwidth for each page, the allocation unit 704 changes the allocation of pages in each of the memories 310, 320 so as to satisfy the determined target bandwidth of each of the memories 310, 320. Here, changing the allocation of pages so as to satisfy the target bandwidth means, for example, changing the allocation of pages so that the usage bandwidth of each of the memories 310, 320 completely matches the target bandwidth or is as close as possible to the target bandwidth.

[0093] Specifically, for example, the placement unit 704 refers to the profile information of each of the memories 310, 320, and identifies the current bandwidth usage of each of the memories 310, 320 from the current latency of each of the memories 310, 320. Then, the placement unit 704 changes the placement of pages based on the estimated bandwidth for each page, so that the bandwidth usage of each of the memories 310, 320 becomes the target bandwidth.

[0094] To explain in more detail, for example, the placement unit 704 may move pages from the local memory 310 to the CXL memory 320 so as to completely match the target bandwidth. At this time, the placement unit 704 may, for example, prioritize pages with a larger calculated estimated bandwidth as pages to be moved among the pages placed in the local memory 310. This allows the placement unit 704 to reduce the number of page moves and suppress the overhead involved in moving pages.

[0095] In addition, the placement unit 704 may adjust the usage bandwidth of each memory 310, 320 by moving pages from the local memory 310 to the CXL memory 320 and also by moving pages from the CXL memory 320 to the local memory 310 so that the bandwidth matches the target bandwidth exactly.

[0096] However, even if the page allocation between the memories 310, 320 is changed, it may not completely match the target bandwidth of each memory 310, 320. In this case, the allocation unit 704 may move pages from the local memory 310 to the CXL memory 320, or move pages from the CXL memory 320 to the local memory 310, so as to come as close as possible to the target bandwidth.

[0097] In the above description, the estimated bandwidth for each page in each of the memories 310 and 320 is calculated, but this is not limiting. For example, when changing the page allocation because the latency of the local memory 310 becomes greater than the latency of the CXL memory 320, pages may be moved only from the local memory 310 to the CXL memory 320.

[0098] In this case, the calculation unit 703 calculates an estimated bandwidth for each page in the local memory 310 when the determined target latency for the local memory 310 is achieved, for example, based on the number of accesses per unit time for each page assigned to each application in the local memory 310.

[0099] Then, the allocation unit 704 changes the allocation of pages by moving the pages from the local memory 310 to the CXL memory 320 based on the estimated bandwidth for each page so that the usage bandwidth of each memory 310, 320 becomes the target bandwidth. This allows the node 201 to reduce the load imposed on the node 201 in calculating the estimated bandwidth for each page, although page movement is limited to the direction from the local memory 310 to the CXL memory 320.

[0100] (Example of bandwidth control for node 201) Next, an example of bandwidth control of the node 201 will be described.

[0101] Fig. 8 and Fig. 9 are explanatory diagrams showing an example of bandwidth control of node 201. Fig. 8 shows CPU 301, local memory 310, and CXL memory 320 in node 201. In Fig. 8 and Fig. 9, App0 to App3 indicate the names of applications currently being executed in node 201. The square symbols in each memory 310, 320 indicate pages. The numbers in the squares indicate page numbers.

[0102] 8, pages 0 to 5 of application App0 and pages 6 to 9 of application App1 are arranged in the local memory 310. Furthermore, pages 10 to 12 of application App2 and pages 13 to 15 of application App3 are arranged in the CXL memory 320.

[0103] However, some of the pages of the applications App0 to App3 are excerpted and displayed in Figures 8 and 9. In the following explanation, an example of bandwidth control of the node 201 will be explained, focusing on pages 0 to 15 of the applications App0 to App3.

[0104] Here, assume that the latency of the local memory 310 becomes greater than the latency of the CXL memory 320. In this case, it can be said that a bandwidth contention for the local memory 310 is occurring or that a bandwidth contention for the local memory 310 is about to occur.

[0105] Here, it is assumed that the current latency of the local memory 310 is "330 ns" and the current latency of the CXL memory 320 is "175 ns." It is also assumed that the profile information 400, 500 shown in Fig. 4 and Fig. 5 has been acquired as the profile information of each memory 310, 320. It is also assumed that the profile information 600 shown in Fig. 6 has been acquired as the profile information of each application.

[0106] In this case, first, the node 201 determines the target latency and target bandwidth of each of the memories 310 and 320 when controlling the bandwidth of each of the memories 310 and 320 .

[0107] 10 is an explanatory diagram showing an example of determining a target latency and a target bandwidth. In FIG. 10, a graph 1001 shows a change in latency with an increase in the bandwidth used by the local memory 310. The graph 1001 is specified by the profile information 400. A graph 1002 shows a change in latency with an increase in the bandwidth used by the CXL memory 320. The graph 1002 is specified by the profile information 500.

[0108] The node 201 measures the current latency of each of the memories 310 and 320. Here, the current latency of the local memory 310 is "330 ns." The current latency of the CXL memory 320 is "175 ns."

[0109] The node 201 refers to the graph 1001 (profile information 400) to identify the current used bandwidth of the local memory 310. Here, the used bandwidth of "180 GB / s" corresponding to the current latency of the local memory 310 of "330 ns" is identified as the current used bandwidth of the local memory 310.

[0110] The node 201 refers to the graph 1002 (profile information 500) to identify the current used bandwidth of the CXL memory 320. Here, the used bandwidth of "40 GB / s" corresponding to the current latency of the CXL memory 320 of "175 ns" is identified as the current used bandwidth of the CXL memory 320.

[0111] The node 201 determines a target latency for each of the memories 310, 320 based on the current latency of each of the memories 310, 320 so as to eliminate the latency difference between the memories 310, 320. Here, it is assumed that the target latency for each of the memories 310, 320 is determined to be "250 ns", which is approximately the midpoint between the current latency of the local memory 310, "330 ns", and the current latency of the CXL memory 320, "175 ns".

[0112] Then, the node 201 refers to the graph 1001 (profile information 400 ) and determines the usage bandwidth “150 GB / s” corresponding to the determined target latency of the local memory 310 of “250 ns” as the target bandwidth of the local memory 310 .

[0113] Furthermore, the node 201 refers to the graph 1002 (profile information 500 ) and determines the usage bandwidth “70 GB / s” corresponding to the determined target latency “250 ns” of the CXL memory 320 as the target bandwidth of the CXL memory 320 .

[0114] Next, the node 201 acquires the current number of accesses per unit time for each page allocated to each application in each memory 310, 320. Here, it is assumed that the access count information per second 1100, 1200 as shown in Fig. 11 and Fig. 12 has been acquired.

[0115] 11 and 12 are explanatory diagrams showing a specific example of the access count per second information. In Fig. 11, the access count per second information 1100 indicates the number of accesses per second for each page allocated to each application App0, App1 in the local memory 310. The access count per second is the number of accesses per second.

[0116] For example, the number of accesses per second to page 0 of application App0 is “300M.” Also, the number of accesses per second to page 6 of application App1 is “50M.” Note that information indicating the correspondence between applications and pages is stored in, for example, memory 302.

[0117] 12, the access count per second information 1200 indicates the access count per second for each page assigned to each of the applications App2 and App3 in the CXL memory 320. For example, the access count per second for page 10 of the application App2 is "100M." Also, the access count per second for page 13 of the application App3 is "200K."

[0118] Next, the node 201 acquires the current bandwidth usage of each application in each of the memories 310 and 320. Here, it is assumed that the application usage bandwidth information 1300 as shown in FIG.

[0119] Fig. 13 is an explanatory diagram showing a specific example of application usage bandwidth information. In Fig. 13, application usage bandwidth information 1300 indicates the current usage bandwidth of each application in each of memories 310 and 320. For example, the current usage bandwidth of application App0 in local memory 310 is "80 GB / s". In addition, the current usage bandwidth of application App2 in CXL memory 320 is "10 GB / s".

[0120] Next, the node 201 calculates an estimated bandwidth for each page in each of the memories 310, 320, for example, using the above formula (1). Here, the number of accesses per second is identified from the number of accesses per second information 1100, 1200 shown in Figs. 11 and 12. S (cache line size) is assumed to be "64B". The bandwidth used during standalone execution is identified from the profile information 600 shown in Fig. 6. The current bandwidth used is identified from the application usage bandwidth information 1300 shown in Fig. 13. It is also assumed that the memory performance of the memories 310, 320 is the same, and the correction value is set to "1".

[0121] In this case, taking page 0 of application App0 as an example, the estimated bandwidth for page 0 is:

[0122] Estimated Bandwidth for Page 0 = 300[M times] × 64[B] × (120[GB / s] / 80[GB / s]) ×(330[ns] / 250[ns) × 1 =37.125[GB / s]

[0123] Fig. 14 is an explanatory diagram showing an example of the estimated bandwidth for each page. In Fig. 14, the estimated bandwidths of the top three pages 0, 3, and 8, which have the largest calculated estimated bandwidths, among pages 0 to 9 arranged in the local memory 310, are shown in descending order.

[0124] Here, the current latency and bandwidth usage of the local memory 310 are "330 ns" and "180 GB / s", and the current latency and bandwidth usage of the CXL memory 320 are "175 ns" and "40 GB / s".

[0125] The target latency and target bandwidth of the local memory 310 are "250 ns" and "150 GB / s." The target latency and target bandwidth of the CXL memory 320 are "250 ns" and "70 GB / s."

[0126] In this case, node 201 changes the allocation of pages so that the bandwidth used by local memory 310 becomes "150 GB / s" from "180 GB / s". At this time, node 201 changes the allocation of pages so that the bandwidth used by CXL memory 320 becomes "70 GB / s" from "40 GB / s".

[0127] Here, assume that a page is moved from the local memory 310 to the CXL memory 320. Here, the estimated bandwidth of page 0 is "37.125 GB / s", and if page 0 is moved, the used bandwidth of the local memory 310 will be "7.125 GB / s" smaller than the target bandwidth.

[0128] On the other hand, the sum of the estimated bandwidth of page 3 and the estimated bandwidth of page 8 is "30.9375 GB / s", and if pages 3 and 8 are moved from local memory 310 to CXL memory 320, the used bandwidth of each memory 310, 320 will almost match the target bandwidth. Therefore, node 201 determines pages 3 and 8 arranged in local memory 310 as the pages to be moved.

[0129] 9, node 201 migrates pages 3 and 8, which have been determined as migration targets, from local memory 310 to CXL memory 320. As a result, the bandwidth usage of local memory 310 becomes "149.0625 GB / s", which is expected to satisfy the target latency of "250 ns". Also, the bandwidth usage of CXL memory 320 becomes "70.9375 GB / s", which is expected to satisfy the target latency of "250 ns".

[0130] It is assumed that the estimated bandwidth of page 10 arranged in CXL memory 320 is "7.125 GB / s." In this case, node 201 may determine page 10 arranged in CXL memory 320 as the pages to be moved, together with page 1 arranged in local memory 310. Then, node 201 may move page 1 from local memory 310 to CXL memory 320, and move page 10 from CXL memory 320 to local memory 310. This allows node 201 to match the usage bandwidth of each memory 310, 320 with its respective target bandwidth.

[0131] (Latency control example) Here, an example of controlling the latency of each of the memories 320 and 330 will be described.

[0132] Fig. 15 is an explanatory diagram showing an example of latency control. In Fig. 15, a graph 1501 represents a change in latency associated with an increase in the bandwidth used by the local memory 310. A graph 1502 represents a change in latency associated with an increase in the bandwidth used by the CXL memory 320.

[0133] Here, it is assumed that the performance of the application allocated to the local memory 310 is degraded due to bandwidth contention. At this point, the bandwidth used by the local memory 310 is "a1" and the latency is "L1". In addition, the bandwidth used by the CXL memory 320 is "b1" and the latency is "L2".

[0134] Here, assume that node 201 has performed bandwidth control for each of memories 310 and 320. As a result, the bandwidth used by local memory 310 becomes "a2", the bandwidth used by CXL memory 320 becomes "b2", and the latency of each of memories 310 and 320 becomes "L3".

[0135] In this way, according to node 201, when a bandwidth contention occurs, the CXL memory 320 is used to rearrange pages so as to eliminate the latency difference between memories 310 and 320, thereby reducing the overall latency and suppressing degradation of application performance.

[0136] (Bandwidth control procedure of node 201) Next, the bandwidth control process of the node 201 will be described.

[0137] Fig. 16 is a flowchart showing an example of a bandwidth control processing procedure of the node 201. In the flowchart of Fig. 16, first, it is determined whether or not the current latency of the local memory 310 is greater than the current latency of the CXL memory 320 (step S1601).

[0138] Here, node 201 waits for the current latency of local memory 310 to become greater than the current latency of CXL memory 320 (step S1601: No). Then, when the current latency of local memory 310 becomes greater than the current latency of CXL memory 320 (step S1601: Yes), node 201 reads the profile information of each memory 310, 320 (step S1602).

[0139] Next, the node 201 reads profile information of each application being executed (step S1603), and executes a target latency / target bandwidth determination process to determine the target latency and target bandwidth of each of the memories 310 and 320 (step S1604).

[0140] The specific processing procedure for the target latency / target bandwidth determination processing will be described later with reference to FIG.

[0141] Next, the node 201 acquires the number of accesses per second for each page allocated to each application in each memory 310, 320 (step S1605). Next, the node 201 acquires the current bandwidth used by each application in each memory 310, 320 (step S1606).

[0142] Then, the node 201 uses the above formula (1) to calculate an estimated bandwidth for each page in each memory 310, 320 when the determined target latency for each memory 310, 320 is achieved (step S1607). The estimated bandwidth is calculated based on, for example, profile information of each memory 310, 320, profile information of each application, the number of accesses per second for each page, the currently used bandwidth of each application, the current latency and target latency of each memory 310, 320, etc.

[0143] Next, the node 201 determines a page to be moved based on the calculated estimated bandwidth for each page and the currently used bandwidth of each memory 310, 320 so as to satisfy the determined target bandwidth of each memory 310, 320 (step S1608). Then, the node 201 changes the placement of the determined page to be moved (step S1609) and ends the series of processes according to this flowchart.

[0144] This allows the node 201 to control the bandwidth of each of the memories 310 and 320 and adjust the latency of each of the memories 310 and 320.

[0145] Next, a specific procedure for the target latency / target bandwidth determination process in step S1604 will be described with reference to FIG.

[0146] Fig. 17 is a flowchart showing an example of a specific processing procedure of the target latency / target bandwidth determination processing. In the flowchart of Fig. 17, first, the node 201 identifies the current latency of each of the memories 310, 320 (step S1701). Then, the node 201 refers to the profile information of each of the memories 310, 320 to identify the current usage bandwidth of each of the memories 310, 320 (step S1702).

[0147] Next, the node 201 determines a target latency for each of the memories 310, 320 based on the current latency of each of the identified memories 310, 320 so that the latency difference between the memories 310, 320 is eliminated (step S1703).

[0148] Then, node 201 refers to the profile information of each memory 310, 320, and determines the usage bandwidth corresponding to the determined target latency of each memory 310, 320 as the target bandwidth of each memory 310, 320 (step S1704), and returns to the step that called the target latency / target bandwidth determination process.

[0149] This allows the node 201 to determine a target latency and a target bandwidth that keeps the latency of memory access for an application low.

[0150] As described above, the node 201 according to the embodiment can determine the target latency and target bandwidth of each memory 310, 320 based on the current latency of each memory 310, 320 by referring to the profile information of each memory 310, 320 so that the latency difference of each memory 310, 320 is eliminated. The profile information of each memory 310, 320 indicates the change in latency (memory access latency) associated with an increase in the usage bandwidth (memory bandwidth) of each memory 310, 320. Furthermore, the node 201 can calculate an estimated bandwidth for each page in each memory 310, 320 at the determined target latency of each memory 310, 320 based on the number of accesses per unit time for each page assigned to each application in each memory 310, 320. Then, the node 201 can change the arrangement of pages in each memory 310, 320 so as to satisfy the determined target bandwidth of each memory 310, 320 based on the calculated estimated bandwidth for each page.

[0151] In this way, the node 201 can prevent an increase in latency (memory access latency) due to bandwidth contention by controlling the bandwidth (memory bandwidth) used by each of the memories 310 and 320, thereby suppressing degradation of application performance.

[0152] In addition, according to node 201, an estimated bandwidth for each page can be calculated based on a first value obtained by multiplying the number of accesses per unit time for each page by the cache line size, and a second value representing the ratio of the current latency of each memory 310, 320 to the determined target latency for each memory 310, 320.

[0153] This allows the node 201 to calculate an estimated bandwidth for each page at the target latency based on the current bandwidth used for each page estimated from the number of accesses per unit time for each page. Also, the node 201 can calculate an estimated bandwidth for each page, taking into consideration an increase or decrease in the bandwidth available for each page due to a change in latency (current latency ⇒ target latency) of each memory 310, 320. This allows the node 201 to improve the accuracy of prediction of the bandwidth used for each memory 310, 320 after the page allocation is changed.

[0154] In addition, according to node 201, an estimated bandwidth for each page can be calculated based on the first value, the second value, and a third value representing the ratio of the bandwidth used by each application when it is executed alone to the current bandwidth used by each application in each memory 310, 320.

[0155] This allows the node 201 to calculate an estimated bandwidth for each page, taking into consideration that the bandwidth usage increases when a transition is made from a state in which memory bandwidth contention occurs to a state in which memory bandwidth contention does not occur. This allows the node 201 to improve the accuracy of prediction of the bandwidth usage of each of the memories 310 and 320 after the page allocation is changed.

[0156] In addition, according to node 201, an estimated bandwidth for each page can be calculated based on the first value, the second value, the third value, and a fourth value (correction value) representing the performance difference between memories 310 and 320.

[0157] This allows the node 201 to calculate an estimated bandwidth for each page, taking into account the performance difference between the memories 310 and 320.

[0158] Additionally, node 201 can determine a target latency and a target bandwidth for each memory 310 , 320 if the current latency of local memory 310 is greater than the current latency of CXL memory 320 .

[0159] In this way, the node 201 can adjust the latency by controlling the bandwidth of each of the memories 310 and 320 in response to an increase in latency due to bandwidth contention occurring in the local memory 310.

[0160] For these reasons, according to the node 201, by adjusting the latency through bandwidth control of the memories 310 and 320, it is possible to keep the memory access latency of each application low and suppress performance degradation due to bandwidth contention.

[0161] For example, the node 201 can maintain uniform memory access latencies for multiple applications by implementing fine latency control through page allocation using the estimated bandwidth of the page. In addition, the node 201 can perform real-time allocation changes while keeping the cost of bandwidth control low because it changes the allocation on a page-by-page basis.

[0162] In addition, due to the bandwidth control of each memory 310, 320, a so-called hot page may be allocated to the CXL memory 320. However, even in this case, it is possible to suppress the degradation of application performance compared to the case where a bandwidth contention occurs by preferentially allocating a hot page to a local memory as in the conventional technology.

[0163] The control method described in this embodiment can be realized by executing a prepared program on a computer such as a personal computer or a workstation. This control program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD (Compact Disc)-ROM, a DVD (Digital Versatile Disk), or a USB (Universal Serial Bus) memory, and is executed by being read from the recording medium by the computer. This control program may also be distributed via a network such as the Internet.

[0164] In addition, the control system 100 (node ​​201) described in this embodiment can also be realized, for example, by application-specific ICs such as standard cells or structured ASICs (Application Specific Integrated Circuits) or PLDs (Programmable Logic Devices) such as FPGAs.

[0165] The following supplementary notes are further disclosed regarding the above-described embodiment.

[0166] (Note 1) By referring to profile information that indicates a change in latency associated with an increase in the bandwidth used for each of a plurality of types of memories having different transmission paths to the CPU, a target latency and a target bandwidth for each of the memories are determined based on the current latency of each of the memories so that the latency difference between the memories is eliminated; Calculating an estimated bandwidth for each of the pages in each of the memories at the determined target latency for each of the memories based on the number of accesses per unit time for each page allocated to each application in each of the memories; changing an arrangement of the pages in each of the memories so as to satisfy the determined target bandwidth for each of the memories based on the calculated estimated bandwidth for each of the pages; A control program that causes a computer to execute a process.

[0167] (Appendix 2) The calculation process is The control program described in Appendix 1, characterized in that it calculates an estimated bandwidth for each page based on a first value obtained by multiplying the number of accesses per unit time for each page by a cache line size, and a second value representing a ratio of the current latency of each of the memories to the determined target latency for each of the memories.

[0168] (Appendix 3) The calculation process is The control program described in Appendix 2, characterized in that it calculates the estimated bandwidth for each page based on the first value, the second value, and a third value representing a ratio of the bandwidth used by each of the applications when executed alone to the current bandwidth used by each of the applications in each of the memories.

[0169] (Appendix 4) The calculation process is and calculating an estimated bandwidth for each page based on the first value, the second value, the third value, and a fourth value representing a performance difference between the multiple types of memories.

[0170] (Note 5) The plurality of types of memories include a first memory locally connected to the CPU and a second memory connected to the CPU via a Compute Express Link (CXL); The process of determining includes: The control program according to any one of claims 1 to 4, further comprising determining a target latency and a target bandwidth for each of the memories when the current latency of the first memory is greater than the current latency of the second memory.

[0171] (Appendix 6) By referring to profile information that indicates a change in latency associated with an increase in the bandwidth used for each of a plurality of types of memories having different transmission paths to the CPU, a target latency and a target bandwidth for each of the memories are determined based on the current latency of each of the memories so that the latency difference between the memories is eliminated; Calculating an estimated bandwidth for each of the pages in each of the memories at the determined target latency for each of the memories based on the number of accesses per unit time for each page allocated to each application in each of the memories; changing an arrangement of the pages in each of the memories so as to satisfy the determined target bandwidth for each of the memories based on the calculated estimated bandwidth for each of the pages; A control method characterized in that the processing is executed by a computer.

[0172] (Appendix 7) A determination unit that refers to profile information that indicates a change in latency associated with an increase in the bandwidth used for each of a plurality of types of memories having different transmission paths to a CPU, and determines a target latency and a target bandwidth for each of the memories based on the current latency of each of the memories so that the latency difference between the memories is eliminated; a calculation unit that calculates an estimated bandwidth for each page in each of the memories at a target latency for each of the memories determined by the determination unit, based on an access count per unit time for each page allocated to each application in each of the memories; an allocation unit that changes an allocation of the pages in each of the memories so as to satisfy the determined target bandwidth of each of the memories based on the calculated estimated bandwidth for each of the pages; A control system comprising: [Explanation of symbols]

[0173] 100 Control System 101,301 CPU 102,103,302,310,320 Memory 110,400,500,600 Profile Information 200 Systems 201 nodes 202 Client device 210 Network 300 Bus 303 Communication I / F 304 Disk Drive 305 Disc 310 Local Memory 320 CXL Memory 700 Control section 701 Acquisition Department 702 Decision Section 703 Calculation Unit 704 Placement section 1001,1002,1501,1502 graph Access count information for 1100 and 1200 seconds 1300 App bandwidth usage information

Claims

1. determining a target latency and a target bandwidth for each of a plurality of types of memories having different transmission paths to the CPU, based on the current latency of each of the memories, so as to eliminate a latency difference between the memories; Calculating an estimated bandwidth for each of the pages in each of the memories at the determined target latency for each of the memories based on the number of accesses per unit time for each page allocated to each application in each of the memories; changing an arrangement of the pages in each of the memories so as to satisfy the determined target bandwidth for each of the memories based on the calculated estimated bandwidth for each of the pages; A control program that causes a computer to execute a process.

2. The calculation process includes:

2. The control program according to claim 1, further comprising: calculating an estimated bandwidth for each page based on a first value obtained by multiplying the number of accesses per unit time for each page by a cache line size, and a second value representing a ratio of a current latency of each of the memories to a determined target latency for each of the memories.

3. The calculation process includes:

3. The control program according to claim 2, further comprising: calculating the estimated bandwidth for each page based on the first value, the second value, and a third value representing a ratio of the bandwidth used by each application when it is executed alone to the current bandwidth used by each application in each memory.

4. the plurality of types of memories are a first memory locally connected to the CPU and a second memory connected to the CPU via a CXL (Compute Express Link), The process of determining includes:

4. The control program according to claim 1, further comprising: determining a target latency and a target bandwidth for each of the memories when a current latency of the first memory is greater than a current latency of the second memory.

5. determining a target latency and a target bandwidth for each of a plurality of types of memories having different transmission paths to the CPU, based on the current latency of each of the memories, so as to eliminate a latency difference between the memories; Calculating an estimated bandwidth for each of the pages in each of the memories at the determined target latency for each of the memories based on the number of accesses per unit time for each page allocated to each application in each of the memories; changing an arrangement of the pages in each of the memories so as to satisfy the determined target bandwidth for each of the memories based on the calculated estimated bandwidth for each of the pages; A control method characterized in that the processing is executed by a computer.

6. a determination unit that refers to profile information that indicates a change in latency associated with an increase in the bandwidth used for each of a plurality of types of memories having different transmission paths to a CPU, and determines a target latency and a target bandwidth for each of the memories based on a current latency of each of the memories so that a latency difference between the memories is eliminated; a calculation unit that calculates an estimated bandwidth for each page in each of the memories at a target latency for each of the memories determined by the determination unit, based on an access count per unit time for each page allocated to each application in each of the memories; an allocation unit that changes an allocation of the pages in each of the memories so as to satisfy the determined target bandwidth of each of the memories based on the calculated estimated bandwidth for each of the pages; A control system comprising:

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