Display device

Abstract

To provide a semiconductor device including a capacitative element having increased charge capacity without reduction in opening ratio.SOLUTION: A capacitative element 105 includes a pair of electrodes and a dielectric film. The pair of electrodes and the dielectric film are formed of a material having translucency. One of the pair of electrodes functions as an electrode by adding impurities to a semiconductor film 111 having translucency. The other of the pair of electrodes included in the capacitative element is formed by using a conductive film such as a pixel electrode 121b having translucency so as to function as an electrode. There are further provided a scanning line 107, and a capacitance line 115 extending in a direction parallel to the scanning line 107 and provided on the same surface as the scanning line 107. Openings 123b reaching a capacitance line 115 and the conductive film are simultaneously formed on the capacitance line 115 and in an insulation film 131 which can be formed when a source electrode 629 or a drain electrode 639 of a transistor 103 is formed.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a product, a machine, a manufacture, a composition, etc. (conposition of matter), and methods (processes. Simple methods and production In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, The present invention relates to a power storage device, a driving method thereof, or a manufacturing method thereof. The present invention relates to a semiconductor device, a display device, or a light-emitting device including an oxide semiconductor. [Background technology]

[0002] In recent years, flat panel displays such as liquid crystal displays (LCDs) have become widespread. In display devices such as flat panel displays, In each pixel, for example, a transistor serving as a switching element and a A liquid crystal element electrically connected to the transistor, and a capacitance element connected in parallel to the liquid crystal element. It is provided.

[0003] The semiconductor material constituting the semiconductor film of the transistor is amorphous. Silicon semiconductors such as silicon or polysilicon (polycrystalline) are widely used.

[0004] In addition, metal oxides that exhibit semiconductor characteristics (hereinafter referred to as oxide semiconductors) can be used as It is a semiconductor material that can be applied to semiconductor films. For example, zinc oxide or In-Ga-Zn oxide Techniques for fabricating transistors using nitride semiconductors have been disclosed (Patent Documents 1 and See Patent Document 2. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0006] The capacitance element has a pair of electrodes and a dielectric film between them. The other electrode is a gate electrode, a source electrode, a drain electrode, or the like that constitutes a transistor. In many cases, the light-shielding film is made of a conductive film having light-shielding properties such as a light-blocking film.

[0007] In addition, the larger the capacitance of the capacitance element, the more the liquid crystal element will dissipate when an electric field is applied. The period during which the orientation of the crystal molecules can be kept constant can be extended. In a display device in which the period can be extended, the number of times that image data is rewritten can be reduced. This makes it possible to reduce power consumption.

[0008] In order to increase the charge capacity of the capacitance element, the area occupied by the capacitance element is increased. However, there is a method for increasing the area where the pair of electrodes overlap. In a display device, a light-shielding conductive film is used to increase the area where a pair of electrodes overlap. If the area of ​​the conductive film is increased, the aperture ratio of the pixel is reduced, and the display quality of the image is degraded.

[0009] In view of the above problems, one aspect of the present invention is to provide a liquid crystal display device having a high aperture ratio and an increased charge capacity. It is an object of the present invention to provide a semiconductor device or the like that has a capacitor that can be used for a semiconductor device.

[0010] Alternatively, one embodiment of the present invention is to reduce the number of masks used in a manufacturing process and reduce manufacturing costs. It is an object of the present invention to provide a semiconductor device or the like with reduced noise.

[0011] Another object of one embodiment of the present invention is to provide a semiconductor device or the like with low off-state current. Another object of one embodiment of the present invention is to provide a semiconductor device or the like with low power consumption. Another object of one embodiment of the present invention is to provide a display device or the like that is easy on the eyes. Another embodiment of the present invention is to provide a semiconductor device using a transparent semiconductor film. Another aspect of the present invention is to provide a semiconductor device using a highly reliable semiconductor film. Another object of one embodiment of the present invention is to provide a semiconductor film having a low impurity concentration. Another object of the present invention is to provide a semiconductor device or the like using the same. Another object of the present invention is to provide a semiconductor device or the like using an electrode having high electrical conductivity. The object of the present invention is to provide a semiconductor device or the like that is easily normally-off. An object of one embodiment of the present invention is to provide a novel semiconductor device or the like. The description of the problem does not preclude the existence of other problems. It is not necessary to solve all of these problems. Problems other than these can be solved by the specification, This is self-evident from the description in the drawings, claims, etc. From each description, it is possible to extract other issues. [Means for solving the problem]

[0012] One embodiment of the present invention is a semiconductor device including a transistor and a light-transmitting capacitor. Specifically, the pair of electrodes and the dielectric film constituting the capacitance element are formed by a light-transmitting One of the pair of electrodes is formed of a light-transmitting semiconductor film containing impurities. The other of the pair of electrodes constituting the capacitor element is The pixel electrode is formed using a light-transmitting conductive film and functions as an electrode. A scanning line and a capacitance line extending in a direction parallel to the scanning line and provided on the same surface as the scanning line are provided. The capacitor line and the source or drain electrode of the transistor are formed. When the insulating film is formed on the conductive film, an opening that reaches the capacitance line and the conductive film is formed. are formed simultaneously.

[0013] Further, one embodiment of the present invention is a semiconductor device having a gate electrode, a source electrode, a drain electrode, and a light-transmitting a transistor including a semiconductor film, and a capacitor element including a pair of electrodes and a dielectric film provided between the pair of electrodes; A pixel electrode electrically connected to the transistor and a capacitor formed on the same surface as the gate electrode The amount of light emitted from the pixel electrode is measured. a conductive film formed on one surface of the capacitor; A light-transmitting conductive film formed on the same surface as the semiconductor film is used as one of a pair of electrodes. The pixel electrode functions as the other of the pair of electrodes and is provided on a conductive film having light-transmitting properties. The insulating film formed on the capacitive element functions as a dielectric film, and the capacitive line is connected to the capacitive element via the electrodes and the conductive film. The light-transmitting conductive film of the capacitor is electrically connected to the light-transmitting conductive film of the transistor. The semiconductor device has a region having a higher electrical conductivity than a light-transmitting semiconductor film of a transistor.

[0014] The light-transmitting semiconductor film can be formed using an oxide semiconductor. Semiconductors have a large energy gap of 3.0 eV or more, and have high transmittance for visible light. This is because it is loud.

[0015] In addition, stable electrical characteristics are imparted to transistors in which a channel is formed in an oxide semiconductor film. In order to achieve this, for example, a multilayer film including an oxide semiconductor film is required to have a channel formed therein. It is effective to reduce the impurity concentration in the film to make it highly pure and intrinsic. This refers to reducing the impurity concentration in the oxide semiconductor film to make it intrinsic or substantially intrinsic. Note that when an oxide semiconductor film is substantially intrinsic, the carrier density of the oxide semiconductor film is 1×10 17 / cm 3 Less than 1 x 10 15 / cm 3 less than 1×10 13 / cm 3 In the oxide semiconductor film, hydrogen, nitrogen, carbon, silicon, and other components than the main component are In order to reduce the impurity concentration in the oxide semiconductor film, It is also preferable to reduce the impurity concentration in the film.

[0016] For example, silicon in an oxide semiconductor film forms an impurity level. The oxides become traps and can degrade the electrical characteristics of the transistor. The silicon concentration of the semiconductor film is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than The gate insulating film of the transistor may be a silicon oxide film or a silicon oxynitride film. Silicon-containing insulating films such as silicon oxide film, silicon nitride film, and silicon oxynitride film are often used. Therefore, it is preferable to form the channel of the oxide semiconductor film in a layer that is not in contact with the gate insulating film. .

[0017] In addition, hydrogen and nitrogen in the oxide semiconductor film form donor levels and increase the carrier density. It will be a big deal.

[0018] In addition, when a channel is formed at the interface between the gate insulating film and the oxide semiconductor film, Interface scattering occurs, and the field effect mobility of the transistor decreases. The channel of the oxide semiconductor film is preferably formed in a layer that is not in contact with the gate insulating film.

[0019] In order to separate the channel of the transistor from the gate insulating film, for example, For example, the multilayer film may include a first oxide film, an oxide semiconductor film, and a second oxide film. The oxide semiconductor film is a first oxide film, an oxide semiconductor film, and a second oxide film. The constituent elements of the film may be the same, but the atomic ratio of each may be different. The oxide semiconductor film which serves as a channel of a transistor can be separated from the gate insulating film.

[0020] In addition, the term "channel" used in this specification refers to, for example, a portion through which carriers flow. The term "channel formation region" refers to, for example, a region in which a channel can be formed.

[0021] A light-transmitting capacitor element can be manufactured by utilizing a manufacturing process for a transistor. One electrode of the capacitor can be formed by using the process for forming a semiconductor film of a transistor. The dielectric film can be formed by a process for forming an insulating film provided on a semiconductor film of a transistor; The other electrode of the capacitor element is formed by a process of forming a pixel electrode electrically connected to the transistor. It can be used.

[0022] The semiconductor film formed in the process of forming the semiconductor film of the transistor is used as one electrode of the capacitor element. When a semiconductor film is used, the conductivity of the semiconductor film is increased to form a light-transmitting conductive film. For example, hydrogen, boron, nitrogen, fluorine, aluminum, phosphorus, arsenic, indium, tin, One or more elements selected from antimony and rare gas elements are semiconductor films (later transparent conductive films). It is preferable that the element is contained in the semiconductor film. The semiconductor film is formed by ion implantation or ion doping. The above elements can also be added by exposing the element to plasma containing the element. The conductivity of the transparent conductive film, which is one of the electrodes, is 10 S / cm or more and 1000 S / cm or more. and preferably from 100 S / cm to 1000 S / cm.

[0023] Further, one embodiment of the present invention is a semiconductor device having a gate electrode, a source electrode, a drain electrode, and a light-transmitting a transistor including a semiconductor film, and a capacitor element including a pair of electrodes and a dielectric film provided between the pair of electrodes; A pixel electrode electrically connected to the transistor and a capacitor formed on the same surface as the gate electrode The amount of light emitted from the pixel electrode is measured. a conductive film formed on one surface of the transistor; An insulating film is provided on the film, in which an oxide insulating film and a nitride insulating film are laminated in this order, and a capacitance element In the present invention, a light-transmitting semiconductor film having a light-transmitting property is formed on the same surface as a light-transmitting semiconductor film of a transistor. The conductive film is in contact with the nitride insulating film of the insulating film and functions as one of a pair of electrodes. The element electrode functions as the other of a pair of electrodes, the nitride insulating film functions as a dielectric film, and the capacitance line is electrically connected to the light-transmitting conductive film of the capacitor element through an electrode and a conductive film, The light-transmitting conductive film of the capacitor is more conductive than the light-transmitting semiconductor film of the transistor. The semiconductor device has a region with a high conductivity.

[0024] In addition, in the capacitor, a nitride insulating film is formed on a light-transmitting conductive film which functions as one of the electrodes. By making the film contact structure, the above elements can be introduced by ion implantation or ion doping. This allows the step of adding the element to be omitted, improving the yield of semiconductor devices and reducing manufacturing costs. It can be reduced.

[0025] With the above structure, the capacitor element has a light-transmitting property, and therefore the transistor in the pixel is formed Therefore, the aperture ratio can be increased. As a result, a semiconductor device having an improved display quality can be obtained. Thus, a semiconductor device having such a structure can be obtained.

[0026] In the semiconductor device, an insulating film provided over an oxide semiconductor film of a transistor is In the case where a stacked structure of an oxide insulating film and a nitride insulating film is used, the oxide insulating film is difficult to transmit nitrogen. That is, it is preferable that the material has a barrier property against nitrogen.

[0027] In this manner, nitrogen and water are not added to the oxide semiconductor film, which is the semiconductor film of the transistor. This can suppress the diffusion of one or both of the elements, thereby suppressing the fluctuation of the electrical characteristics of the transistor. It is possible.

[0028] In addition, a semiconductor device according to one embodiment of the present invention includes a gate electrode of a transistor and a A capacitance line is provided on the same surface as the scanning line and extends in a direction parallel to the scanning line. One electrode of the capacitor (a light-transmitting conductive film) is connected to a source electrode of a transistor or The capacitor line is electrically connected to the conductive film that can be formed when forming the drain electrode. This is being continued.

[0029] Furthermore, in the driving circuit section, the capacitance line and the source electrode or drain electrode of the transistor A mask is formed on the insulating film on the conductive film that can be formed when forming the drain electrode, The dots and the openings reaching the conductive film are formed at the same time. After the formation, the pixel electrodes are In this step, a capacitance line and an electrode electrically connected to the conductive film can be formed.

[0030] By doing so, the process of forming an opening in the insulating film on the capacitance line and the process of forming the transistor An insulating film on a conductive film that can be formed when forming a source electrode or a drain electrode Since the process of forming the openings can be performed in the same process, the number of masks used in the manufacturing process can be reduced. This can reduce the manufacturing cost.

[0031] Note that a manufacturing method of a semiconductor device according to one embodiment of the present invention is also is included. Effect of the Invention

[0032] According to one embodiment of the present invention, there is provided a semiconductor device having a capacitor element with an increased aperture ratio and an increased charge capacity. In addition, the number of masks used in the manufacturing process can be reduced, and the manufacturing process can be simplified. It is possible to provide a semiconductor device at reduced cost. [Brief description of the drawings]

[0033] [Figure 1] 1A to 1C are a diagram illustrating a semiconductor device which is one embodiment of the present invention and a circuit diagram illustrating a pixel. [Diagram 2] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Diagram 3] 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Diagram 5] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 7] 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 11] 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 13] 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A and 1B are a cross-sectional view and a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device which is one embodiment of the present invention. [Figure 16] 1A to 1C are diagrams illustrating electronic devices using a semiconductor device which is one embodiment of the present invention. [Figure 17] FIG. 2 is a schematic diagram showing a state of sputtering particles peeling off from a sputtering target. [Figure 18] FIG. 2 is a diagram for explaining a discharge state during sputtering using an AC power source. [Figure 19] FIG. 2 is a schematic diagram showing how electrically charged sputtered particles reach a deposition surface. [Figure 20] 1A to 1C are diagrams illustrating a touch sensor according to an embodiment; [Figure 21] 1A to 1C are diagrams illustrating examples of the configuration of a touch panel and an electronic device according to an embodiment. [Figure 22] 1A to 1C are diagrams illustrating a pixel including a touch sensor according to an embodiment. [Diagram 23] 4A to 4C are diagrams illustrating operations of a touch sensor and a pixel according to an embodiment. [Figure 24] 1A to 1C illustrate a pixel configuration according to an embodiment. [Diagram 25] FIG. 2 is a flow diagram showing an example of a method for producing a sputtering target. [Figure 26] Diagram explaining nervous system eye fatigue. [Figure 27] A diagram explaining muscle fatigue. [Figure 28] 1 is a block diagram illustrating a configuration of an information processing device having a display function according to an embodiment. [Figure 29] 1A and 1B are a block diagram and a circuit diagram illustrating a configuration of a display portion of a display device according to an embodiment. [Diagram 30] FIG. 11 is a graph for explaining the relationship between wavelength and transmittance of a sample of a reference example. [Diagram 31] 13A and 13B show CPM measurement results of an oxide semiconductor film. [Diagram 32] 13A and 13B show CPM measurement results of an oxide semiconductor film. [Diagram 33] Cross-sectional TEM image of CAAC-OS film. [Diagram 34] Electron diffraction pattern of CAAC-OS film. [Diagram 35] Cross-sectional TEM image of CAAC-OS film. [Diagram 36]Cross-sectional TEM image and X-ray diffraction spectrum of the CAAC-OS film. [Figure 37] Electron diffraction pattern of CAAC-OS film. [Figure 38] Cross-sectional TEM image and X-ray diffraction spectrum of the CAAC-OS film. [Figure 39] Electron diffraction pattern of CAAC-OS film. [Diagram 40] Cross-sectional TEM image and X-ray diffraction spectrum of the CAAC-OS film. [Diagram 41] Electron diffraction pattern of CAAC-OS film. [Diagram 42] Cross-sectional TEM image and electron diffraction pattern of a nanocrystalline oxide semiconductor film. [Diagram 43] Electron diffraction pattern of nanocrystalline oxide semiconductor film. [Diagram 44] Schematic diagram of electron beam diffraction intensity distribution. [Diagram 45] Ultrafine electron diffraction pattern of a quartz glass substrate. [Figure 46] Electron diffraction pattern of nanocrystalline oxide semiconductor film. [Figure 47] Cross-sectional TEM image of a nanocrystalline oxide semiconductor film. [Figure 48] X-ray diffraction analysis results of metal oxide films of nanocrystalline oxide semiconductor films. [Figure 49] FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and it is understood by those skilled in the art that various changes can be made in form and detail. The present invention is not limited to the description of the following embodiments. It is not something that is done.

[0035] In the configuration of the present invention described below, the same parts or parts having similar functions are designated by the same reference numerals. The same reference numerals are used in common among different drawings, and the repeated explanations are omitted. When referring to a part having a function, the hatch pattern shall be the same and no symbol shall be attached. There is.

[0036] In each figure described in this specification, the size of each structure, the thickness of the film, or the area is not shown for clarity. The figures may be exaggerated for illustrative purposes and are not necessarily limited to that scale.

[0037] In this specification and elsewhere, ordinal numbers such as 1st, 2nd, etc. are used for convenience. The order of steps or stacking is not intended to indicate the order of steps or stacking. It does not indicate a specific name for the purpose of reference.

[0038] Voltage is the potential difference between two points, and potential is the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in a particle. Generally, the potential difference between a potential at a certain point and a reference potential (for example, ground potential) This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification and the like, unless otherwise specified, potential may be read as voltage. However, voltage may be read as potential.

[0039] In this specification, when etching is performed after photolithography is performed The mask formed by the photolithography process is removed.

[0040] (Embodiment 1) In this embodiment, a semiconductor device which is one embodiment of the present invention will be described with reference to drawings. Note that in this embodiment, a liquid crystal display device is used as an example of a semiconductor device according to one embodiment of the present invention. explain.

[0041] <Configuration of Semiconductor Device> FIG. 1A shows an example of a semiconductor device. The semiconductor device shown in FIG. 0, a scanning line driving circuit 104, and a signal line driving circuit 106 are arranged in parallel or approximately in parallel. m scanning lines 107 are provided and the potentials of which are controlled by a scanning line driving circuit 104, The individual electrodes are arranged in parallel or approximately in parallel, and the potential is controlled by a signal line driver circuit 106. The pixel section 100 has n signal lines 109. The pixel array 101 has a number of pixels 101. The pixels 101 are arranged parallel or approximately parallel to each other along a scanning line 107. The capacitance lines 115 are arranged along the signal lines 109. They may be arranged in rows or substantially parallel.

[0042] Each scanning line 107 corresponds to one of the pixels 101 arranged in m rows and n columns in the pixel section 100. The signal lines 109 are electrically connected to the n pixels 101 arranged in any one row. is m pixels 101 arranged in m rows and n columns, and m pixels 101 arranged in any one of the columns 1. m and n are both integers of 1 or more. is n pixels 101 arranged in any one of the rows among the pixels 101 arranged in m rows and n columns. 1. Capacitor lines 115 are arranged parallel to each other along the signal line 109. In the case where the pixels 101 are arranged in m rows and n columns, any one of the pixels 101 may be arranged in a matrix of m rows and n columns. The pixel array 101 is electrically connected to m pixels 101 arranged in a column.

[0043] FIG. 1B is an example of a circuit diagram of a pixel 101 included in the semiconductor device shown in FIG. The pixel 101 shown in FIG. 1B is electrically connected to a scanning line 107 and a signal line 109. A transistor 103 is connected to the drain electrode of the transistor 103. a capacitor element having the other electrode electrically connected to a capacitor line 115 which supplies a constant potential 105, and the pixel electrode is a drain electrode of the transistor 103 and one of the capacitor elements 105. An electrode (counter electrode) that is electrically connected to the pixel electrode and faces the pixel electrode provides a counter potential. and a liquid crystal element 108 electrically connected to the supply wiring.

[0044] The liquid crystal element 108 is made up of a substrate on which the transistor 103 and the pixel electrode are formed, and a counter electrode The optical modulation effect of the liquid crystal sandwiched between the substrate on which the light is formed determines whether the light is transmitted or not. The optical modulation effect of liquid crystal is achieved by controlling the electric field (vertical electric field) applied to the liquid crystal. The pixel electrodes are formed on a substrate. When an opposing electrode (also called a common electrode) is formed in the liquid crystal, the electric field applied to the liquid crystal is This becomes an electric field.

[0045] Next, a specific example of the pixel 101 of the liquid crystal display device will be described. This is shown in Fig. 2. Note that the counter electrode and the liquid crystal element are omitted in Fig. 2.

[0046] In FIG. 2, the scanning lines 107 extend in a direction substantially perpendicular to the signal lines 109 (the left-right direction in the figure). The signal lines 109 extend in a direction substantially perpendicular to the scanning lines 107 (the vertical direction in the figure). The capacitance line 115 is provided so as to extend in a direction parallel to the scanning line 107. The scanning line 107 and the capacitance line 115 are connected to a scanning line driving circuit 104 (FIG. 1( A)), and the signal line 109 is electrically connected to a signal line driver circuit 106 (see FIG. 1( A) is electrically connected to the

[0047] The transistor 103 is provided in the area where the scanning line 107 and the signal line 109 intersect. The transistor 103 includes at least a semiconductor film 111 having a channel formation region and A gate electrode, a gate insulating film (not shown in FIG. 2), a source electrode, and a drain electrode In addition, the region of the scanning line 107 that overlaps with the semiconductor film 111 is a transistor. The gate electrode of the signal line 109 overlaps with the semiconductor film 111. The conductive film 113 functions as a source electrode of the transistor 103. The area overlapping with the body membrane 111 functions as the drain electrode of the transistor 103. Therefore, the gate electrode, the source electrode, and the drain electrode are connected to the scanning line 107, the signal line 108, and the 2, the scanning line 107 is sometimes referred to as a conductive film 113. In terms of the surface shape, the end is located outside the end of the semiconductor film. This functions as a light-shielding film that blocks light from light sources such as backlights. The semiconductor film 111 included in the semiconductor layer 111 is not irradiated with light, and fluctuations in the electrical characteristics of the transistor are suppressed. This can be done.

[0048] In addition, when oxide semiconductors are treated under appropriate conditions, the off-state current of transistors can be reduced significantly. In one embodiment of the present invention, an oxide semiconductor is used for the semiconductor film 111 because the semiconductor film 111 can reduce the This makes it possible to reduce the power consumption of the semiconductor device.

[0049] In addition, an oxide semiconductor is preferable because it has a tendency to absorb blue light. The light emitted from the cornea reaches the retina without being absorbed by the cornea or lens of the eye, so it has no long-term effect on the retina. The effects of blue light on the eyes (e.g. age-related macular degeneration) and the circadian rhythm of blue light exposure late at night For this reason, it is necessary to absorb blue light using oxide semiconductors. This can reduce eye fatigue of the user of the semiconductor device.

[0050] The conductive film 113 is a pixel electrode formed of a conductive film having a light-transmitting property through the opening 117. In FIG. 2, the pixel electrode 121b is hatched. The diagram omits the wiring.

[0051] The capacitance element 105 is disposed in a region surrounded by the capacitance line 115 and the signal line 109 in the pixel 101. The capacitor element 105 is provided with electrodes provided in the openings 123a and 123b. The capacitor element is electrically connected to the capacitor line 115 through the conductive film 125. The light-transmitting oxide semiconductor 105 has a high electrical conductivity. A conductive film 120, a pixel electrode 121b having light transmission properties, and a dielectric film, 03 and a light-transmitting insulating film (not shown in FIG. 2). The capacitive element 105 is transparent.

[0052] Since the conductive film 120 has a light-transmitting property, the capacitor element 105 can be formed large in the pixel 101. Therefore, the aperture ratio can be increased, typically to 55% or more. A semiconductor having an increased charge capacity and preferably 60% or more. For example, a semiconductor device with high resolution, such as a liquid crystal display device, can be obtained. In this case, the area of ​​the pixel is smaller, and the area of ​​the capacitance element is also smaller. In the semiconductor device, the charge capacity stored in the capacitive element is reduced. Since the capacitor 105 shown in the embodiment has a light-transmitting property, the capacitor can be provided in a pixel. Thus, it is possible to increase the aperture ratio while obtaining a sufficient charge capacity in each pixel. A high-resolution semiconductor device having a pixel density of 200 ppi or more, or even 300 ppi or more. In addition, one embodiment of the present invention can be suitably used in a high-resolution display device. This allows for a higher aperture ratio, making it possible to efficiently use light from light sources such as backlights. This makes it possible to reduce the power consumption of the display device.

[0053] Here, the characteristics of a transistor using an oxide semiconductor will be described. The transistor used is an n-channel transistor. Oxygen vacancies can generate carriers, which can degrade the electrical characteristics and reliability of transistors. For example, the threshold voltage of a transistor may be shifted in the negative direction, causing a gate When the gate voltage is 0V, the drain current may flow. When the gate voltage is 0V, the drain current flows. This is called a normally-on characteristic. The normally-off characteristic is that no drain current flows when the drain voltage is 0V. He said.

[0054] Therefore, when an oxide semiconductor is used for the semiconductor film 111, It is preferable that defects, typically oxygen vacancies, contained in the membrane are reduced as much as possible. For example, the g value of the electron spin resonance method, which applies a magnetic field parallel to the film surface, is 1.9. The spin density of 3 (corresponding to the defect density in the oxide semiconductor film) is the lower limit of detection by the measuring instrument. Defects contained in the oxide semiconductor film, typically, oxide By reducing the pixel deficiency as much as possible, the transistor 103 has a normally-on characteristic. This can suppress the generation of the oxide film, thereby improving the electrical characteristics and reliability of the semiconductor device. .

[0055] The negative shift in the threshold voltage of a transistor is not only due to oxygen vacancies, but also due to oxide It can also be caused by hydrogen (including hydrogen compounds such as water) contained in semiconductors. The hydrogen contained in the oxide semiconductor reacts with the oxygen that is bonded to the metal atom to form water, and A defect (which can also be called an oxygen vacancy) is formed in the lattice where oxygen has been removed (or in the part where oxygen has been removed). In addition, some of the hydrogen reacts with oxygen to generate electrons, which act as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen has normally-on characteristics. It is easy to become.

[0056] In order to prevent this, when an oxide semiconductor is used for the semiconductor film 111, the oxide semiconductor film is Specifically, in the semiconductor film 111, the secondary ion species is preferably reduced. Secondary Ion Mass Spectrometer (SIMS) The hydrogen concentration obtained by y) is 5 × 10 18 atoms / cm 3 Less than 1x, preferably 10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 below , and more preferably 1×10 16 atoms / cm 3 The following applies.

[0057] The semiconductor film 111 is also formed of an alkali metal or alkali metal oxide obtained by secondary ion mass spectrometry. The concentration of alkaline earth metals is increased by 1×10 18 atoms / cm 3 Less than or equal to 2×10 1 6 atoms / cm 3 Alkali metals and alkaline earth metals are oxide semiconductors. When the ions are bonded to the body, carriers may be generated, which increases the off-state current of the transistor 103. This can sometimes be done.

[0058] In addition, when nitrogen is contained in the oxide semiconductor film that is the semiconductor film 111, the carrier Electrons are generated, the carrier density increases, and it becomes easier to make the material n-type. Transistors using oxide semiconductors tend to be normally-on. In the semiconductor film, it is preferable that the nitrogen is reduced as much as possible. For example, Degrees are 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0059] In this way, impurities (hydrogen, nitrogen, alkali metals or alkaline earth metals, etc.) can be removed. The oxide semiconductor film 111 is purified as much as possible to reduce the amount of ions in the oxide semiconductor film. This can prevent the transistor 103 from becoming normally on, and the off-state current of the transistor 103 can be reduced. Therefore, a semiconductor device having good electrical characteristics can be manufactured. In addition, a semiconductor device with improved reliability can be manufactured.

[0060] The reason why the off-state current of a transistor using a highly purified oxide semiconductor film is low is that This can be proved by various experiments. For example, when the channel width W is 1×10 6 Channel length in μm Even with an element with L of 10 μm, the voltage between the source and drain electrodes (drain voltage) In the range of 1V to 10V, the off-state current is below the measurement limit of the semiconductor parameter analyzer. Bottom, i.e. 1×10 -13 In this case, the transistor The off-state current, which is equivalent to the value divided by the channel width of the MOSFET, must be 100zA / μm or less. In addition, by connecting the capacitor and the transistor, The off-state current was measured using a circuit that controls the charge flowing out of the transistor. In the measurement, a highly purified oxide semiconductor film was used as a channel formation region of the transistor. The off-state current of the transistor is measured based on the change in the amount of charge per unit time of the capacitor. As a result, when the voltage between the source and drain electrodes of the transistor is 3V, It was found that an even lower off-current of several tens of yA / μm could be obtained. A transistor including an oxide semiconductor film having a fluorinated oxide is extremely low in off-state current.

[0061] Next, between dashed lines A1 and A2, between dashed lines B1 and B2, and between dashed lines C1 and C2 in FIG. 1A is a cross-sectional view of a transistor provided in a scanning line driver circuit 104 (see FIG. 1A). 3. Here, a top view of the scanning line driving circuit 104 is omitted, and A cross-sectional view of the wiring 104 is shown in FIG. The transistor is also provided in the signal line driver circuit 106. It is possible.

[0062] First, the dashed lines A1 and A2 of the pixel 101, the dashed lines B1 and B2, and the dashed lines The structure between the lines C1 and C2 will be described. The gate of the transistor 103 is disposed on the substrate 102. A scanning line 107 including an electrode, a capacitance line 115 provided on the same surface as the scanning line 107, A gate insulating film 127 is provided on the scanning line 107 and the capacitance line 115. A semiconductor film 111 is provided on a region of the gate insulating film 127 that overlaps with the scanning line 107. A conductive film 120 is provided on the gate insulating film 127. and a signal line 109 including a source electrode of the transistor 103 on the gate insulating film 127; A conductive film 113 including a drain electrode of the transistor 103 is provided. A conductive film 125 is provided on the gate insulating film 127, the signal line 109, and the semiconductor The conductive film 111, the conductive film 113, the conductive film 125, and the conductive film 120 of the transistor 103 are An insulating film 129, an insulating film 131, and an insulating film 133 that function as protective insulating films are provided. The gate insulating film 127, the insulating film 129, the insulating film 131 and the insulating film 133 have a capacitance. An opening 123a is provided that reaches the line 115. In addition, the insulating film 129, the insulating film 131, and An opening 123b is provided in the insulating film 133, and the opening 123b reaches the conductive film 125. 3a, the opening 123b, the capacitor line 115, the conductive film 125 and the insulating film 133. The insulating film 129, the insulating film 131, and the insulating film 133 are provided with a conductive film 11. 3 (see FIG. 2 ), and the opening 117 and the insulating film 133 A pixel electrode 121b is provided on the pixel electrode 121b.

[0063] In the capacitor 105 shown in this embodiment, one of a pair of electrodes is a semiconductor film 111. The conductive film 120 is formed in the same manner as in the above and has an increased conductivity. The electrode is a pixel electrode 121b, the dielectric film provided between the pair of electrodes is an insulating film 129, The insulating film 133 is an insulating film 131 .

[0064] Next, the structure of a transistor provided in the scanning line driver circuit 104 will be described. A gate electrode 627 of the transistor 623 is provided on the gate electrode 62 A gate insulating film 127 is provided on the gate electrode 627 of the gate insulating film 127. A semiconductor film 628 is provided on the overlapping region. A source electrode 629 and a drain electrode 639 of the transistor 623 are provided on the insulating film 127. On the gate insulating film 127, on the source electrode 629, on the semiconductor film 628, An insulating film 129 that functions as a protective insulating film for a transistor 623 is formed on a drain electrode 639. An insulating film 131 and an insulating film 133 are provided. A conductive film 641 is provided on the insulating film 133. It is provided.

[0065] The substrate 102, the scanning line 107, the capacitance line 115, the gate electrode 627, the gate insulating film A base insulating film may be provided between the insulating film 127 and the insulating film 127 .

[0066] In the transistor 623, a conductor overlapping the gate electrode 627 through a semiconductor film 628 is By providing the conductive film 641, the on-current rise gate The variation in voltage can be reduced. In the above plane, the current flowing between the source electrode 629 and the drain electrode 639 is controlled. This makes it possible to reduce the variation in electrical characteristics between different transistors. In addition, by providing the conductive film 641, the change in the surrounding electric field is applied to the semiconductor film 628. This can reduce the influence of the conductive film 64 and improve the reliability of the transistor. The potential of 1 is set to the minimum potential (Vss, for example, the potential of the source electrode 629) of the driving circuit. In this case, the potential of the transistor is set to the same potential as the potential of the source electrode 629. It is possible to reduce the variation in the threshold voltage of the transistor, thereby improving the reliability of the transistor. However, in some cases or depending on the situation, the conductive film 641 may not be provided. It is also possible.

[0067] The insulating film 129 and the insulating film 131 are made of, for example, silicon oxide, silicon oxynitride, or alumina. oxide, hafnium oxide, gallium oxide, or Ga-Zn-based metal oxides The border material may be provided in a single layer or laminated structure.

[0068] The thickness of the insulating film 129 is 5 nm or more and 150 nm or less, preferably 5 nm or more and 50 nm or less. The thickness of the insulating film 131 can be set to 10 nm or less and preferably 30 nm or less. The thickness can be set to 30 nm or more and 500 nm or less, preferably 150 nm or more and 400 nm or less. Cut.

[0069] The insulating film 133 may be made of, for example, silicon oxynitride, silicon nitride, aluminum nitride, It can be provided in a single layer structure or a multilayer structure using a nitride insulating material such as aluminum oxide nitride. This can be done.

[0070] As the insulating film 133, a nitride insulating film with a low hydrogen content may be provided. For example, the following can be measured by thermal desorption spectrometry (hereinafter referred to as TDS analysis): Heat treatment at a surface temperature of 100°C to 700°C, preferably 100°C to 500°C The amount of hydrogen molecules released at 21 molecule / cm 3 less than 3 .0×10 21 molecule / cm 3 and more preferably less than 1.0×10 21 molecule / cm 3 It is a nitride insulating film having a thickness of less than 100 nm.

[0071] The insulating film 133 has a thickness capable of suppressing the intrusion of impurities such as hydrogen and water from the outside. For example, the thickness is 50 nm or more and 200 nm or less, preferably 50 nm or more and 150 nm or less. The thickness can be set to 50 nm or less and more preferably 100 nm or less.

[0072] In addition, an insulating film 13, which is a nitride insulating film, is formed on the transistor 103 and the transistor 623. By providing the insulating film 133, impurities such as carbon contained in the silicon oxide film are blocked by the insulating film 133. The semiconductor film 111 and the semiconductor film 112 of the transistor 103 and the transistor 623 are Since the migration of impurities into the semiconductor film 628 is reduced, the variation in the electrical characteristics of the transistors is reduced. It is possible to reduce

[0073] Furthermore, one or both of the insulating film 129 and the insulating film 131 may have a stoichiometric composition. It is preferable that the oxide insulating film contains more oxygen than the oxygen that is contained in the insulating film. In addition, oxygen is prevented from being released from the oxide semiconductor film, and the oxygen contained in the oxygen-excess region is prevented from being released from the oxide semiconductor film. The oxygen can be moved to the oxide semiconductor film to fill the oxygen vacancies. The surface temperature measured by DS analysis is 100°C or more and 700°C or less, preferably 100 The amount of oxygen molecules released during heat treatment at 500°C or higher is 1.0×10 18 molecule / c m 3 By using the above oxide insulating film, oxygen vacancies in the oxide semiconductor film can be filled. Note that in one or both of the insulating film 129 and the insulating film 131, An acid that has regions that contain more oxygen than the stoichiometric composition (oxygen excess regions) The insulating film may be an oxygen-excess region at least in a region overlapping with the semiconductor film 111. By providing the oxide semiconductor film with the oxygen-excess region, it is possible to prevent oxygen from being released from the oxide semiconductor film and to form an oxygen-excess region. The oxygen contained in the oxide semiconductor film can be moved to the oxide semiconductor film to fill the oxygen vacancies. .

[0074] The insulating film 131 is an oxide insulating film containing more oxygen than the oxygen that satisfies the stoichiometric composition. In this case, the insulating film 129 is preferably an oxide insulating film that transmits oxygen. In the insulating film 129, all oxygen that enters the insulating film 129 from the outside passes through the insulating film 129 and migrates. Some oxygen does not move and remains in the insulating film 129. Some oxygen migrates from the insulating film 129 to the outside. It is preferable that the insulating oxide film has a large coefficient.

[0075] The insulating film 129 is in contact with the semiconductor film 111 and the oxide semiconductor film that is the semiconductor film 628. Therefore, not only oxygen can be transmitted, but also the interface state density with the semiconductor film 111 is low. For example, the insulating film 129 has a smaller intermediate layer than the insulating film 131. It is preferable that the oxide insulating film has a low defect density. The spin density at g-value = 2.001 (E´-center) is 3.0×10 17 spin s / cm 3 Less than or equal to 5.0×10 16 spins / cm 3 The following oxide insulating film is used: The spin density at g value = 2.001 measured by electron spin resonance is It corresponds to the amount of dangling bonds present.

[0076] In addition, one or both of the insulating film 129 and the insulating film 131 have a barrier property against nitrogen. For example, a dense oxide insulating film is preferably used to prevent the formation of nitrogen. Specifically, the barrier properties of the film can be obtained by using 0.5% by weight of hydrofluoric acid at 25°C. It is preferable that the oxide insulating film has an etching rate of 10 nm / min or less when etched with an etchant.

[0077] One or both of the insulating film 129 and the insulating film 131 may be formed of silicon oxynitride or When using an oxide insulating film containing nitrogen, such as silicon nitride oxide, the nitrogen concentration obtained by SIMS is The degree is 3×10 above the lower limit of detection by SIMS. 20 atoms / cm 3 Less than 1 x 10 18 atoms / cm 3 More than 1×10 20 atoms / cm 3 The following is the case. This reduces the amount of nitrogen transferred to the semiconductor film 111 included in the transistor 103. In addition, by doing so, the number of defects in the oxide insulating film itself containing nitrogen can be reduced. It can be made easier.

[0078] The components of the above structure are described in detail below.

[0079] There is no particular restriction on the material of the substrate 102, but at least in the manufacturing process of the semiconductor device, For example, a glass substrate, There are ceramic substrates, plastic substrates, etc., and glass substrates are barium borosilicate Non-alkali glass such as acid glass, aluminoborosilicate glass or aluminosilicate glass Alternatively, a substrate that does not have light transmission properties, such as a stainless steel alloy, may be used. In this case, it is preferable to provide an insulating film on the surface of the substrate. 2. Quartz substrate, sapphire substrate, single crystal semiconductor substrate, polycrystalline semiconductor substrate, compound semiconductor substrate It is also possible to use a solid substrate, SOI (Silicon On Insulator) substrate, etc. can.

[0080] The scanning line 107, the capacitance line 115, and the gate electrode 627 are made of a metal film because they carry a large current. It is preferable to form the ferroelectric thin film by using molybdenum (Mo), titanium (Ti), tungsten (Tn), etc. Tantalum (W), Tantalum (Ta), Aluminum (Al), Copper (Cu), Chromium (Cr), Nickel (Ni) Metallic materials such as neodymium (Nd) and scandium (Sc), or alloys that contain these as their main components The insulating layer 110 may have a single layer structure or a laminate structure using the material.

[0081] An example of the scanning line 107, the capacitance line 115, and the gate electrode 627 includes silicon. A single-layer structure using aluminum containing titanium, a two-layer structure with titanium laminated on aluminum, and titanium nitride Two-layer structure with titanium laminated on tungsten, two-layer structure with tungsten laminated on titanium nitride, Two-layer structure of tungsten laminated on tantalum nitride, copper-magnesium-aluminum alloy Two-layer structure with copper layered on gold, copper layered on titanium nitride, and tungsten layered on top of that There are three-layer structures that form

[0082] In addition, the scanning line 107, the capacitance line 115, and the gate electrode 627 are made of the same material as the pixel electrode A light-transmitting conductive material applicable to 121b can be used.

[0083] Furthermore, the scanning line 107, the capacitance line 115, and the gate electrode 627 are made of nitrogen. Metal oxides containing nitrogen, specifically, In-Ga-Zn oxides containing nitrogen and In -Sn-based oxides, In-Ga-based oxides containing nitrogen, In-Zn-based oxides containing nitrogen, , Sn-based oxides containing nitrogen, In-based oxides containing nitrogen, and metal nitride films (InN, SnN These materials have a work function of 5 eV (electron volts) or more. When an oxide semiconductor is used for the semiconductor film 111 of the transistor 103, By using a metal oxide containing nitrogen as the gate electrode of the transistor 103, The threshold voltage of the transistor 103 can be changed in the positive direction, so that the For example, a nitrogen-containing In-Ga-Zn oxide transistor can be realized. In the case of using a material having a nitrogen concentration higher than that of the oxide semiconductor film which is the semiconductor film 111, Specifically, an In-Ga-Zn oxide having a nitrogen concentration of 7 atomic % or more can be used.

[0084] The scanning line 107, the capacitance line 115, and the gate electrode 627 are made of a low resistance material, i.e., a It is preferable to use aluminum or copper. By using aluminum or copper, the signal delay can be reduced. It is possible to reduce the heat resistance of aluminum and improve the display quality. The aluminum alloy is prone to defects due to whiskers or migration. To prevent migration, aluminum is mixed with molybdenum, titanium, tungsten, etc. It is preferable to laminate a metal material having a higher melting point than aluminum. In this case, molybdenum, titanium, and It is preferable to deposit a metal material having a higher melting point than copper, such as tungsten.

[0085] The gate insulating film 127 is made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or Ga-Zn-based gold The semiconductor film 1 is provided in a single layer structure or a multilayer structure using an insulating material such as a metal oxide. In order to improve the interface characteristics with the oxide semiconductor film 11, the gate insulating film 127 is At least a region in contact with the semiconductor film 111 is preferably formed using an oxide insulating film.

[0086] In addition, the gate insulating film 127 is formed of an insulating film having a barrier property against oxygen, hydrogen, water, etc. By providing the insulating layer, oxygen can be diffused from the oxide semiconductor film, which is the semiconductor film 111, to the outside and Therefore, it is possible to prevent hydrogen, water, and the like from entering the oxide semiconductor film. Examples of insulating films that have a barrier property against these include aluminum oxide films and aluminum oxynitride films. film, gallium oxide film, gallium oxynitride film, yttrium oxide film, yttrium oxynitride film Examples of the film include hafnium oxide film, hafnium oxynitride film, and silicon nitride film.

[0087] The gate insulating film 127 is made of hafnium silicate (HfSi x O y ), nitrogen Hafnium silicate (HfSi x O y ), hafnium aluminate with nitrogen (HfAl x O y ), hafnium oxide, yttrium oxide, and other high-k materials are used. This can reduce the gate leakage of the transistor 103.

[0088] The gate insulating film 127 preferably has the following laminated structure: A silicon nitride film with few defects is provided as a contact film, and a second silicon nitride film is formed on the first silicon nitride film. A silicon nitride film with a small amount of hydrogen desorption and ammonia desorption was used. On the second silicon nitride film, any one of the oxide insulating films listed in the gate insulating film 127 is formed. It is preferable to provide a

[0089] The second silicon nitride film is a film that has a hydrogen molecule desorption rate of 5.0 or more in thermal desorption gas spectrometry. ×10 21 molecules / cm 3 Less than 3 x 10 21 molecules / cm 3 The following is more preferable: 1×10 21 molecules / cm 3 The number of ammonia molecules released is less than 1×10 22 molecule / cm 3 Less than 5 x 10 21 molecules / cm 3 Less than 1×10, more preferably 2 1 molecules / cm 3 It is preferable to use a nitride insulating film having the following properties: The silicon nitride film and the second silicon nitride film are used as a part of the gate insulating film 127. The insulating film 127 is made of a gate insulating film having a small amount of defects and a small amount of desorption of hydrogen and ammonia. As a result, hydrogen and The amount of nitrogen that moves to the semiconductor film 111 can be reduced.

[0090] In a transistor using an oxide semiconductor, If trap states (also called interface states) exist on the surface or gate insulating film, the transistor The shift in threshold voltage, typically in the negative direction, and the The sub-series shows the gate voltage required to change the drain current by one order of magnitude when the transistor is turned on. This causes the threshold coefficient (S value) to increase. As a result, the electrical characteristics of each transistor For this reason, silicon nitride with fewer defects is used as the gate insulating film. By using a silicon film and providing an oxide insulating film in the region in contact with the semiconductor film 111, This reduces the negative shift of the threshold voltage and suppresses the increase in the S value. do.

[0091] The thickness of the gate insulating film 127 is preferably 5 nm or more and 400 nm or less, more preferably 10 nm or less. The thickness is preferably at most 300 nm, and more preferably at least 50 nm and at most 250 nm.

[0092] The semiconductor film 111 and the semiconductor film 628 are oxide semiconductor films. The conductive film 120 may have an amorphous structure, a single crystal structure, or a polycrystalline structure. The semiconductor film 111 is formed so as to have an increased electrical conductivity. 1 nm or more and 100 nm or less, preferably 1 nm or more and 50 nm or less, more preferably 1 nm or more The thickness is preferably from 3 nm to 30 nm, and more preferably from 3 nm to 20 nm.

[0093] As an oxide semiconductor that can be used for the semiconductor film 111 and the semiconductor film 628, The gap is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. As shown in FIG. 1, by using an oxide semiconductor with a wide energy gap, The off-state current can be reduced.

[0094] The oxide semiconductor applicable to the semiconductor film 111 and the semiconductor film 628 is at least indium. It is preferable that the alloy contains aluminum (In) or zinc (Zn). Alternatively, the alloy contains both In and Zn. In addition, it is preferable that the oxide semiconductor be included in the transistor. It is preferable to have one or more stabilizers with them to reduce the .

[0095] The stabilizers are gallium (Ga), tin (Sn), hafnium (Hf), and aluminium. Aluminum (Al) or zirconium (Zr), etc. Also, other stabilizers The lanthanides lanthanum (La), cerium (Ce), and praseodymium ( Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er) Er, Thulium, Ytterbium, Lutetium, etc. be.

[0096] Examples of oxide semiconductors that can be used for the semiconductor film 111 and the semiconductor film 628 include oxide semiconductors such as oxide Indium oxide, tin oxide, zinc oxide, In-Zn oxide, which is an oxide containing two kinds of metals substances, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides In-Mg oxide, In-Ga oxide, and In- Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-G a-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf -Zn-based oxide, In-Zr-Zn-based oxide, In-Ti-Zn-based oxide, In-Sc- Zn-based oxide, In-Y-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides Oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn ​​oxides In-Sn-Ga-Zn oxides, which are oxides containing four types of metals, and In-Hf-Ga -Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide and In-Hf-Al-Zn oxide can be used. do.

[0097] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as the main components. The ratio of In, Ga, and Zn does not matter. The metal elements may be included.

[0098] In addition, InMO 3 (ZnO) mUsing materials expressed as (m>0) M may be a metal element selected from Ga, Fe, Mn, and Co, or A plurality of metal elements or the above-mentioned elements as a stabilizer are shown.

[0099] For example, In:Ga:Zn=1:1:1, In:Ga:Zn=2:2:1, or I It is possible to use an In-Ga-Zn-based metal oxide with an atomic ratio of n:Ga:Zn=3:1:2. Alternatively, In:Sn:Zn=1:1:1 or In:Sn:Zn=2:1:3. Alternatively, an In-Sn-Zn metal oxide with an atomic ratio of In:Sn:Zn=2:1:5 is used. The atomic ratio of the metal oxide should be ±2% of the above atomic ratio as an error. Includes 0% variation.

[0100] However, the present invention is not limited to these, and the semiconductor properties and electrical properties required (field effect mobility, The appropriate atomic ratio should be used according to the required semiconductor material (e.g., threshold voltage). In order to obtain the physical properties, the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, It is preferable to make the interatomic distance, density, etc. appropriate. For example, In-Sn-Zn system It is relatively easy to obtain high field effect mobility in oxides. Even in n-type oxides, the field effect mobility can be increased by lowering the defect density in the bulk. can be done.

[0101] A signal line 109 including the source electrode of the transistor 103, a drain electrode of the transistor 103 The conductive film 113 including the electrodes and the conductive film 120 of the capacitor element 105 are electrically connected to the capacitor line 115. The conductive film 125, which is electrically connected to the source electrode 629 and the drain electrode 639, is A single layer structure using materials applicable to the line 107, the capacitance line 115, and the gate electrode 627. Alternatively, it may be provided in a laminated structure.

[0102] The electrode 121a, the pixel electrode 121b and the conductive film 641 are made of indium tin oxide, tin oxide, etc. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc Conductive materials with translucency, such as lead oxide or indium tin oxide with added silicon oxide. is formed.

[0103] Here, the connections of the components included in the pixel 101 shown in this embodiment are shown in FIG. The circuit diagram shown in FIG.

[0104] FIG. 1C is an example of a detailed circuit diagram of a pixel 101 included in the semiconductor device shown in FIG. As shown in FIG. 1C and FIG. 3, the transistor 103 includes a gate electrode. A scanning line 107, a signal line 109 including a source electrode, and a conductive film 113 including a drain electrode. has.

[0105] The capacitor element 105 is connected to the capacitor line 115 via the electrode 121a and the conductive film 125. The conductive film 120 connected to the drain electrode functions as one of the electrodes. The pixel electrode 121b connected to the conductive film 120 and the pixel electrode 121b connected to the conductive film 120 function as the other electrode. The insulating film 129, the insulating film 131, and the insulating film 133 are provided between the pixel electrodes 121b. It functions as a dielectric film.

[0106] The liquid crystal element 108 includes a pixel electrode 121b, a counter electrode 154, and a and a liquid crystal layer provided between the liquid crystal layer and a counter electrode 154.

[0107] In the capacitor 105, the conductive film 120 has the same structure as the semiconductor film 111, and is doped with a dopant. The pixel electrode 121b is added to the gate electrode 121b to function as an electrode of the capacitance element 105. The gate electrode, the insulating film 129, the insulating film 131 and the insulating film 133 are formed as a gate insulating film and a capacitance line 115. can function as a source electrode or a drain electrode, resulting in a capacitance element 1 05 can be operated like a transistor to turn on the conductive film 120. That is, the capacitance element 105 is a MOS (Metal Oxide Semiconductor). ctor capacitors. MOS capacitors have a threshold voltage (V th) is applied to one of the electrodes constituting the MOS capacitor (capacitance element 105). When a potential is applied to the pixel electrode 121b, the pixel electrode 121b is charged. By controlling the voltage Vcc, the conductive film 120 is brought into a conductive state, and the conductive film 120 is connected to one electrode of the capacitance element. In this case, the potential applied to the capacitance line 115 is as follows: The potential of the pixel electrode 121b is set to a value that drives the liquid crystal element 108 (see FIG. 1C). , fluctuates in the positive and negative directions with respect to the central potential of the video signal. In order to keep the element 105 (MOS capacitor) in a constant conductive state, the capacitance line 115 The potential applied to the capacitance element 105 (MOS capacitance) is always higher than the potential applied to the pixel electrode 121b. However, in the capacitor 105, The conductive film 120 functioning as one electrode is of n-type and has high conductivity, so that the threshold The voltage shifts in the negative direction. The pixel electrode (P) is changed in response to the amount of shift of the threshold voltage of the capacitance element 105 in the negative direction. The potential of the capacitance element 10 can be increased from the lowest potential that the capacitance element 10 can have. When the threshold voltage of the pixel electrode 121b is a large negative value, the potential of the capacitance line 115 is In this way, the conductive film 120 is always in a conductive state. It is possible to make the capacitance element 105 (MOS capacitor) conductive. can.

[0108] In addition, the insulating film 129 provided over the semiconductor film 111 and the semiconductor film 628 is made of an oxygen-permeable material. The interface state density between the semiconductor film 111 and the semiconductor film 628 is reduced. The insulating film 131 is an oxide insulating film including an oxygen excess region or an insulating film having a stoichiometric composition. By using an oxide insulating film containing more oxygen than the semiconductor film 111, This makes it easier to supply oxygen to the oxide semiconductor film 628. and prevents oxygen from being released from the insulating film 131. By this, oxygen vacancies in the oxide semiconductor film can be filled. This can prevent the transistor 103 from becoming normally on. A capacitance line 115 is connected so that the capacitance element 105 (MOS capacitor) is always in a conductive state. Since it is possible to control the potential applied to the It can be improved.

[0109] In addition, by using a nitride insulating film as the insulating film 133 provided over the insulating film 131, The semiconductor film 111 and the conductive film 120 are prevented from being infiltrated by impurities such as hydrogen and water from the outside. Furthermore, by providing a nitride insulating film with a low hydrogen content as the insulating film 133, As a result, the electric characteristic fluctuation of the transistor 103 and the capacitance element 105 (MOS capacitor) is suppressed. It can be suppressed.

[0110] In addition, the capacitance element 105 can be formed large (with a large area) within the pixel 101. As a result, a semiconductor device having an increased aperture ratio and an increased charge capacity can be obtained. As a result, a semiconductor device with excellent display quality can be obtained.

[0111] <Method for manufacturing semiconductor device> Next, a method for manufacturing an element portion provided on the substrate 102 shown in the above semiconductor device will be described. This will be explained with reference to FIG. 4 and FIG.

[0112] First, the scanning line 107, the capacitance line 115, and the gate electrode 627 are formed on the substrate 102. Then, a gate insulating film is formed to cover the scanning line 107, the capacitance line 115, and the gate electrode 627. An insulating film 126 is formed to be processed into a region 127, and the insulating film 126 overlaps with the scanning line 107. Then, the semiconductor film 111 is formed so as to overlap the region where the pixel electrode 121b is to be formed later. A conductive film 119 is formed. A semiconductor film 628 is formed in a region overlapping with the gate electrode 627. (See FIG. 4(A)).

[0113] The scanning line 107, the capacitance line 115, and the gate electrode 627 are made of the materials listed above. A conductive film is formed, a mask is formed on the conductive film, and processing is performed using the mask. The conductive film can be formed by a deposition method, a CVD method, a sputtering method, a spin coating method, etc. The thickness of the conductive film is not particularly limited, and the shape of the conductive film may be any suitable method. The mask can be determined by taking into consideration the time required for forming the mask and the desired resistivity. The resist mask may be formed by a photolithography process. The conductive film is processed by either dry etching or wet etching or both. It is possible to do so.

[0114] The insulating film 126 is formed by CVD or spa using a material that can be used for the gate insulating film 127. The insulating film can be formed by using various film formation methods such as a tar deposition method.

[0115] In addition, when gallium oxide is used for the gate insulating film 127, MOCVD (Metal Using the Organic Chemical Vapor Deposition method An insulating film 126 can be formed.

[0116] The semiconductor film 111, the semiconductor film 119, and the semiconductor film 628 are the above-listed oxide semiconductors. an oxide semiconductor film is formed using a material having a thickness of 100 nm, a mask is formed over the oxide semiconductor film, and the mask is The oxide semiconductor film can be formed by processing the oxide semiconductor film using a sputtering method, It can be formed using a coating method, a pulsed laser deposition method, a laser ablation method, etc. In addition, by using a printing method, the semiconductor film 111 and the semiconductor film 1 The oxide semiconductor 19 can be formed directly on the insulating film 126 by sputtering. When forming a plasma, the power supply for generating the plasma is an RF power supply or an AC power supply. A sputtering device or a DC power supply device can be used as appropriate. The sputtering gas is a rare gas. (Typically, argon), oxygen, a rare gas, and a mixed gas of oxygen are appropriately used. In the case of a mixture of rare gas and oxygen, it is preferable to increase the gas ratio of oxygen to rare gas. Further, the target may be appropriately selected depending on the composition of the oxide semiconductor film to be formed. The mask is, for example, a resist mask formed by a photolithography process. The oxide semiconductor film can be processed by dry etching and wet etching. This can be done by either etching or both. It can be etched into the desired shape. Therefore, the etching conditions (etching gas, etching solution, etching time, etc.) should be adjusted according to the material. , temperature, etc.) as appropriate.

[0117] After the semiconductor film 111, the semiconductor film 119, and the semiconductor film 628 are formed, a heat treatment is performed. , dehydration of the oxide semiconductor films, which are the semiconductor film 111, the semiconductor film 119, and the semiconductor film 628. The temperature of the heat treatment is typically 150° C. or higher but lower than the substrate distortion point, preferably 200° C. or higher but lower than 450° C., and more preferably 300° C. Note that the heat treatment is performed at a temperature of 450° C. or lower. This may be performed on an oxide semiconductor film before processing.

[0118] In this heat treatment, the heat treatment device is not limited to an electric furnace, and a medium such as heated gas may be used. The device may be a device that heats the workpiece by thermal conduction or thermal radiation from the workpiece. For example, , LRTA (Lamp Rapid Thermal Anneal) equipment, GRTA ( Gas Rapid Thermal Annealing (RTA) equipment The LRTA device can be used with a halogen laser. lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high pressure nato The exposure to light (electromagnetic waves) emitted from lamps such as lithium lamps and high-pressure mercury lamps can cause The GRTA device is a device that uses high-temperature gas to heat materials. be.

[0119] The heat treatment is carried out in the presence of nitrogen, oxygen, or ultra-dry air (with a water content of 20 ppm or less, preferably Air at less than 1 ppm, preferably less than 10 ppb), or rare gases (argon, helium The above-mentioned nitrogen, oxygen, ultra-dry air, or rare gas may be added to hydrogen. It is preferable that the mixture does not contain water or the like. After heating in an inert gas atmosphere, it is heated in an oxygen atmosphere. The treatment time is from 3 minutes to 24 hours.

[0120] The substrate 102, the scanning line 107, the capacitance line 115, and the insulating film 126 (later When a base insulating film is provided between the gate insulating film 127) and the insulating film 128, the base insulating film is preferably made of silicon oxide. , silicon oxynitride, silicon nitride, silicon nitride oxide, gallium oxide, hafnium oxide It can be formed of yttrium oxide, aluminum oxide, aluminum oxide nitride, etc. The insulating base film can be made of silicon nitride, gallium oxide, hafnium oxide, or indium oxide. By forming the SiO 2 layer using tritium, aluminum oxide, etc., impurities, typically Alkaline metals, water, hydrogen, etc., are mixed into the semiconductor film 111, the semiconductor film 119, and the semiconductor film 6. The base insulating film is formed by sputtering or CVD. It can be formed by

[0121] Next, a dopant is added to the semiconductor film 119 to form a conductive film 120 having high conductivity ( See Figure 4(B).

[0122] The method of adding a dopant to the semiconductor film 119 is to provide a mask on the region other than the semiconductor film 119. By using the mask, hydrogen, boron, nitrogen, fluorine, aluminum, phosphorus, arsenic , indium, tin, antimony and one or more dopants selected from rare gas elements. The doping is performed by ion implantation or ion doping. Instead of the doping method, the semiconductor film 119 is exposed to plasma containing the dopant. The dopant may be added. After the dopant is added, a heat treatment is performed. It is also possible.

[0123] The process of adding the dopant is performed on the signal line 109, the conductive film 113, the conductive film 125, and the sole. This may be done after forming the source electrode 629 and the drain electrode 639. The area of ​​conductive film 120 that contacts conductive film 125 is not doped with dopant.

[0124] Note that both the oxide semiconductor film and the light-transmitting conductive film are made of an oxide semiconductor material containing In or Ga. The impurity concentration of the oxide semiconductor film is different from that of the oxide semiconductor film. For example, the impurity concentration of the light-transmitting conductive film is high. is 5 x 10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1 x 10 18 atoms / cm 3 Less than or equal to 5×10 17 a toms / cm 3Less than 1×10, more preferably 16 atoms / cm 3 is as follows: The hydrogen concentration in the light-transmitting conductive film is 8×10 19 atoms / cm 3 That's all good Preferably 1×10 20 atoms / cm 3 More preferably, 5×10 20 atoms / cm 3 In addition, compared with an oxide semiconductor film, The hydrogen concentration is 2 times, preferably 10 times or more.

[0125] In addition, the light-transmitting conductive film has a lower resistivity than the oxide semiconductor film. The resistivity of the oxide semiconductor film is 1×10 -8 more than 1x10 -1 Less than double It is preferable to use a concentration of 1×10 -3 Ωcm or more 1×10 4 Less than Ωcm, even better Preferably, the resistivity is 1×10 -3 Ωcm or more 1×10 -1 It is preferable that the resistivity is less than Ωcm.

[0126] Next, on the insulating film 126, a signal line 109 including a source electrode of the transistor 103, The conductive film 113 including the drain electrode of the transistor 103 and the conductive film 120 are electrically connected to the capacitance line 115. A conductive film 125 for electrically connecting the source electrode 629 and the drain electrode 6 Form 39.

[0127] A signal line 109, a conductive film 113, a conductive film 125, a source electrode 629, and a drain electrode 639 is applied to the signal line 109, the conductive film 113, the conductive film 125, and the gate electrode 627. A conductive film is formed using a material that can be used for the conductive film, a mask is formed on the conductive film, and the mask is used to The mask and the processing are performed on the scanning line 107, the capacitance line 115 and the gate electrode 627 can be performed in the same manner.

[0128] Next, the semiconductor film 111, the conductive film 120, the semiconductor film 628, the signal line 109, the conductive film 1 13, the conductive film 125, the source electrode 629, the drain electrode 639, and the insulating film 12 6, an insulating film 128 is formed on the insulating film 128, and an insulating film 130 is formed on the insulating film 130. Then, an insulating film 132 is formed on the insulating film 128 (see FIG. 5A). It is preferable that the insulating film 12 and the insulating film 132 are formed continuously. 8. Impurities can be prevented from being mixed into the interfaces between the insulating film 130 and the insulating film 132. Cut.

[0129] The insulating film 128 is formed by CVD or sputtering using a material that can be applied to the insulating film 129. The insulating film 130 can be formed by various film forming methods such as a deposition method. Using materials applicable to the above, various film formation methods such as CVD and sputtering are used. The insulating film 132 can be formed by using a material applicable to the insulating film 133, using a CVD method or It can be formed by various film formation methods such as a sputtering method.

[0130] In the case where an oxide insulating film having a low interface state density with the semiconductor film 111 is used as the insulating film 129, The insulating film 128 can be formed under the following conditions. The case where a silicon oxide film or a silicon oxynitride film is formed will be described. The formation conditions were as follows: the substrate was placed in the evacuated processing chamber of the plasma CVD apparatus and heated to 180°C. The temperature is kept at 400°C or higher, and more preferably 200°C or higher and 370°C or lower. The pressure in the processing chamber is increased by introducing a silicon-containing deposition gas and an oxidizing gas. The pressure in the processing chamber is set to 0 Pa or more and 250 Pa or less, and more preferably 40 Pa or more and 200 Pa or less. This is a condition for supplying high frequency power to an electrode provided inside the

[0131] Representative examples of silicon-containing deposition gases include silane, disilane, trisilane, and fluoride. Silane, etc. Oxidizing gases include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc. There is.

[0132] In addition, by increasing the amount of oxidizing gas to 100 times or more the amount of deposition gas containing silicon, It is possible to reduce the hydrogen content in the insulating film 128 (later insulating film 129). At the same time, the dangling bonds contained in the insulating film 128 (later insulating film 129) are reduced. The oxygen that moves from the insulating film 130 (later the insulating film 131) is transferred to the insulating film 128. (later insulating film 129) may capture the dangling bonds. Therefore, the number of dangling bonds contained in the insulating film 128 (later insulating film 129) is reduced. Then, oxygen contained in the insulating film 130 (later insulating film 131) is efficiently transferred to the semiconductor film 111. By moving the oxygen atoms, oxygen vacancies in the oxide semiconductor film, which is the semiconductor film 111, can be filled. As a result, the amount of hydrogen mixed into the oxide semiconductor film can be reduced, and the oxide semiconductor film can be It is possible to reduce oxygen vacancies contained in the conductive film.

[0133] The insulating film 131 is an oxide insulating film including the oxygen excess region or an oxide having a stoichiometric composition. In the case where the insulating film 130 is an oxide insulating film containing more oxygen than the silicon, the insulating film 130 is formed under the following conditions. Note that the oxide insulating film here can be formed of a silicon oxide film or a silicon oxynitride film. The formation of a silicon film will be described below. The formation conditions are as follows: The substrate placed in the evacuated processing chamber is heated to 180° C. or higher and 260° C. or lower, more preferably 1 The temperature is kept between 80°C and 230°C, and the raw material gas is introduced into the treatment chamber to adjust the pressure in the treatment chamber. 100 Pa or more and 250 Pa or less, more preferably 100 Pa or more and 200 Pa or less, 0.17 W / cm2 on the electrode installed in the treatment chamber 2 More than 0.5W / cm 2 The following are more preferred Or 0.25W / cm 2 More than 0.35W / cm 2 The following high frequency power is supplied:

[0134] The source gas for the insulating film 130 may be a source gas that can be used for the insulating film 128 .

[0135] The conditions for forming the insulating film 130 are as follows: high frequency power of the above power density in a processing chamber at the above pressure. By supplying power, the efficiency of decomposition of the source gas in the plasma increases, and the number of oxygen radicals increases. As the oxidation of the source gas progresses, the oxygen content in the insulating film 130 becomes lower than the stoichiometric composition. However, when the substrate temperature is set to the above temperature, the bonding strength between silicon and oxygen becomes As a result, the oxygen in the stoichiometric composition is less than that of the oxygen in the stoichiometric composition. It is possible to form an oxide insulating film that contains more oxygen than the silicon oxide film and from which some of the oxygen is released by heating. In addition, oxygen can be added to the insulating film 130 by ion implantation or the like to increase the oxygen content. In addition, an insulating film 128 is provided over the semiconductor film 111. In the process of forming the film 130, the insulating film 128 serves as a protective film for the semiconductor film 111. Even if the insulating film 130 is formed using high-frequency power with a high power density, the semiconductor film 111 and In addition, damage to the semiconductor film 628 can be suppressed.

[0136] In addition, by increasing the thickness of the insulating film 130, the amount of oxygen desorbed by heating is increased. Therefore, it is preferable that the insulating film 130 be thicker than the insulating film 128. By providing the insulating film 128, good coverage can be achieved even when the insulating film 130 is provided thick. can be done.

[0137] In the case where the insulating film 133 is a nitride insulating film with a low hydrogen content, the insulating film 132 has the following shape. In this embodiment, a silicon nitride film is used as the nitride insulating film. The formation conditions are as follows: The substrate placed in the treatment chamber is heated to 80°C or higher and 400°C or lower, and more preferably 200°C or higher and 37°C or lower. The temperature is kept below 0°C, and the raw material gas is introduced into the processing chamber to make the pressure in the processing chamber 100 Pa or more. The pressure is set to 250 Pa or less, preferably 100 Pa or more and 200 Pa or less. High frequency power is supplied to the electrodes.

[0138] The source gas for the insulating film 132 is a deposition gas containing silicon, nitrogen, and ammonia. Representative examples of deposition gases containing silicon include silane, disilane, and the like. The nitrogen flow rate is the same as the ammonia flow rate. It is preferable to set the ratio to 5 to 50 times, and more preferably to 10 to 50 times. By using ammonia as the source gas, the deposition gas containing silicon and the nitrogen This is because ammonia is decomposed by plasma energy or thermal energy. The energy released by the dissociation breaks down the bonds of the deposition gas molecules, including silicon. This is because it contributes to breaking down the bonds of nitrogen molecules. Silicon nitride film has low adhesion and can suppress the intrusion of impurities such as hydrogen and water from the outside. can be formed.

[0139] After forming at least the insulating film 130, a heat treatment is performed to form the insulating film 128 or the insulating film 1 The excess oxygen contained in the semiconductor film 111 and the semiconductor film 628 is transferred to the semiconductor film 130. It is preferable that oxygen vacancies in the oxide semiconductor film 11 and the semiconductor film 628 be filled. The heat treatment for dehydrogenating or dehydrating the semiconductor film 111 will be described in detail in This can be done by referring to the above.

[0140] Next, the insulating film 126, the insulating film 128, the insulating film 130 and the insulating film 132 are formed on the capacitance line 115. An opening 123a reaching the capacitance line 115 is formed in the region overlapping the insulating film 128 and the insulating film 130. An opening 123 reaching the conductive film 125 is formed in a region of the insulating film 132 overlapping with the conductive film 125. b are formed, and a gate insulating film 127, an insulating film 129, an insulating film 131, and An insulating film 133 is formed (see FIG. 5(B)).

[0141] The opening 123a is a container for the insulating films 126, 128, 130, and 132. The opening 123b is formed by insulating film 128 so that a part of the region overlapping with the dose line 115 is exposed. The insulating film 130 and the insulating film 132 are formed such that a part of the region overlapping with the conductive film 125 is exposed. The insulating layer can be formed by forming a mask and processing the insulating layer using the mask. The conductive film 113 is formed in the region of the insulating film 128, the insulating film 130, and the insulating film 132 that overlaps with the conductive film 113. 13. The opening 117 (see FIG. 2) is formed so as to extend from the opening 12. The mask and the opening 123b can be formed in the same manner. The processing is performed in the same manner as the scanning line 107, the capacitance line 115, and the gate electrode 627. It is possible.

[0142] Conventionally, the opening that reaches the capacitance line and the opening that reaches the conductive film (drain electrode) are made separately. In the past, a mask was formed for each process of forming the openings. By forming the insulating film 128, the insulating film 130, and the insulating film 132, a conductive film is formed. After forming the opening 123b reaching the conductive film 125 and the opening 117 reaching the conductive film 113, In order to form an opening 123a reaching the capacitance line 115, the insulating film 126 is subsequently etched. However, the conductive film 125 and the conductive film 126 are made of metal in the openings 123b and 117. Since the capacitor line 113 is exposed, no further etching is performed. an opening 123 a reaching the conductive film 125, an opening 123 b reaching the conductive film 113, and 17 can be formed using the same mask, reducing the number of masks used in the manufacturing process. This allows the manufacturing costs to be reduced.

[0143] In addition, the conductive film 120 is connected to an electrode 121a to be formed later via the conductive film 125. Therefore, in the opening 123b, the conductive film 125 also serves as an etching protection film for the conductive film 120. For this purpose, after the opening 123b and the opening 117 are formed, the opening 123a is formed. During this process, etching of the conductive film 120 can be prevented. It is possible to increase it.

[0144] Finally, the electrode 121a, the pixel electrode 121b, and the conductive film 641 are formed to form the substrate. The element portion to be provided in the electrode 121a can be fabricated (see FIG. 3). The conductive film in contact with the capacitance line 115 and the conductive film 125 through the opening 123a and the opening 123b is The conductive film is then processed by forming a mask on the conductive film. The pixel electrode 121b is formed of a conductive film that contacts the conductive film 113 through the opening 117. The conductive film can be formed by forming a mask on the conductive film and processing the conductive film using the mask. The mask and processing are the same as those for the scanning line 107 and the capacitance line 115. This can be done.

[0145] <Variation 1> In the semiconductor device according to one embodiment of the present invention, one electrode of the capacitor 105 is The upper surface shape of the conductive film 125 that electrically connects the conductive film 120 and the capacitance line 115 is appropriately changed. For example, the contact resistance between the conductive film 120 and the conductive film 125 can be reduced. Therefore, the conductive film 125 can be provided in contact with the outer periphery of the conductive film 120. The conductive film 125 is connected to the signal line 109 including the source electrode of the transistor 103 and the The conductive film 113 including the drain electrode of the transistor 103 is formed in the same formation process. Since the insulating layer may have a light-shielding effect, it is preferable to form the insulating layer in a loop shape.

[0146] <Variation 2> In addition, in the pixel 101 shown above, the semiconductor film includes a gate insulating film and a source electrode. A transistor is used that is located between the signal line 109 and the conductive film 113 including the drain electrode. Instead, the semiconductor film includes a signal line including a source electrode and a drain electrode. A transistor located between the conductive film and the insulating film 129 can be used.

[0147] <Modification 3> In the pixel 101 shown above, a channel etch type transistor is used as a transistor. Although a channel-protected transistor is shown, a channel-protected transistor can be used instead. By providing the channel protection film, the surface of the semiconductor film 111 is in the shape of the signal line and the conductive film. The semiconductor film 111 and the channel are not exposed to the etchant or etching gas used in the deposition process. As a result, the impurities between the source electrode and the drain electrode of the transistor can be reduced. It is possible to reduce the leakage current flowing between the gate electrodes.

[0148] <Variation 4> In the pixel 101 shown above, a transistor having one gate electrode is used. The transistor has two gate electrodes facing each other through a semiconductor film 111. A transistor can be used.

[0149] The transistor is a transistor 103 having a conductor formed on the insulating film 133 thereof. The conductive film overlaps at least a channel formation region of the semiconductor film 111. By providing the conductive film at a position overlapping with a channel formation region of the semiconductor film 111, It is preferable that the potential is set to the lowest potential of the video signal input to the signal line 109. On the surface of the semiconductor film 111 facing the conductive film, a source electrode and a drain electrode are It is possible to control the flow of current, reducing the variation in the electrical characteristics of transistors. In addition, by providing a conductive film, a change in the surrounding electric field is applied to the semiconductor film 111. This reduces the effect of the short circuit and improves the reliability of the transistor.

[0150] The conductive film is made of the same material and in the same manner as the scanning lines 107, the signal lines 109, the pixel electrodes 121b, etc. The method can be carried out.

[0151] As described above, one electrode of the capacitor element is formed of the same material as the semiconductor film included in the transistor. By using a semiconductor film formed in the process, the aperture ratio is increased and the charge capacity is increased. As a result, a semiconductor device having a high display quality can be manufactured. The device can be obtained.

[0152] In addition, oxygen vacancies are reduced in an oxide semiconductor film, which is a semiconductor film included in a transistor. Since impurities such as hydrogen are reduced, the semiconductor device according to one embodiment of the present invention can be favorably This results in a semiconductor device having excellent electrical characteristics.

[0153] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used.

[0154] (Embodiment 2) This embodiment describes a semiconductor device according to one embodiment of the present invention, which has a structure different from that of the above embodiment. The semiconductor device will be described with reference to the drawings. In this embodiment, a liquid crystal display device is taken as an example. In addition, the semiconductor device according to one embodiment of the present invention will be described. The device has a different structure of the capacitance element compared to the above embodiment. In the semiconductor device according to the present invention, the same configuration as the semiconductor device described in the above embodiment is The embodiment can be referred to.

[0155] <Configuration of Semiconductor Device> A top view of a pixel 201 described in this embodiment is shown in FIG. 6. The pixel 201 shown in FIG. In the region enclosed by the dashed line, the insulating film 229 (not shown) and the insulating film 231 (not shown) are ) is not provided on the conductive film 220. The end of the film 231 (not shown) is located at the pixel 201 shown in FIG. 05 is a conductive film 220 which is one electrode, a pixel electrode 221b which is the other electrode, and a dielectric and an insulating film 233 (not shown) which is a protective film.

[0156] Next, between dashed lines A1 and A2, between dashed lines B1 and B2, and between dashed lines C1 and C2 in FIG. 1A is a cross-sectional view of a transistor provided in a scanning line driver circuit 104 (see FIG. 1A). 7. In this example, a top view of the scanning line driving circuit 104 is omitted, and A cross-sectional view of the wiring 104 is shown in FIG. A cross-sectional view of a transistor is shown, which is provided in the signal line driver circuit 106. It is possible.

[0157] The cross-sectional structure of the pixel 201 in this embodiment is as follows. A scanning line 107 including a gate electrode of the transistor 103 and a gate electrode 104 provided on the same surface as the scanning line 107. A gate electrode is provided on the scanning line 107 and the capacitance line 115. A gate insulating film 227 is provided on the gate insulating film 227. A semiconductor film 111 is provided on the gate insulating film 227, and a conductive film 220 is provided on the gate insulating film 227. The source electrode of the transistor 103 is formed on the semiconductor film 111 and the gate insulating film 227. A signal line 109 including a drain electrode and a conductive film 113 including a drain electrode of the transistor 103 are provided. A conductive film 125 is provided on the conductive film 220. A gate insulating film 227 is provided on the conductive film 220. , on the signal line 109, on the semiconductor film 111, on the conductive film 113, on the conductive film 125, on the conductive film 220 An insulating film 229 and an insulating film 231 which function as protective insulating films for the transistor 103 are provided thereon. An insulating film 233 is provided. In addition, at least in the region that will become the capacitor element 205, An insulating film 233 is provided on and in contact with the conductive film 220. 29, an opening 223a reaching the capacitance line 115 is provided in the insulating film 231 and the insulating film 233. The insulating film 229, the insulating film 231, and the insulating film 233 are provided with a conductive film 125. An opening 223b is provided, which reaches the opening 223a, the opening 223b, and the capacitor line 115. The electrode 221a is provided on the conductive film 125 and the insulating film 233. In the insulating film 231 and the insulating film 233, an opening 117 (see FIG. 6) is formed that reaches the conductive film 113. A pixel electrode 221b is provided on the opening 117 and the insulating film 233. In addition, the substrate 102, the scanning line 107, the capacitance line 115, and the gate insulating film 227 A base insulating film may be provided between them.

[0158] The gate insulating film 227 is an insulating film similar to the gate insulating film 127 described in the first embodiment. The insulating film 229 is the same as the insulating film 129 described in the first embodiment. The insulating film 231 is an insulating film similar to the insulating film 131 described in the first embodiment. The insulating film 3 is the same as the insulating film 133 described in the first embodiment. , which is a pixel electrode similar to the pixel electrode 121b described in the first embodiment.

[0159] As in the case of the capacitor element 205 in this embodiment, a conductive film 220 which is one electrode and a By using the insulating film 233 as the dielectric film provided between the pixel electrode 221b, which is the first electrode, The thickness of the dielectric film is made thinner than that of the dielectric film of the capacitance element 105 in the first embodiment. Therefore, the capacitance element 205 in this embodiment can be obtained by the same method as in the first embodiment. The charge capacity can be increased as compared to the capacitor 105 .

[0160] The insulating film 233 is a nitride insulating film similar to the insulating film 133 of the first embodiment. Since the insulating film 233 is in contact with the semiconductor film 119 (later the conductive film 220), Nitrogen and further hydrogen contained in the nitride insulating film can be moved to the semiconductor film 119. The semiconductor film 119 is made of n-type material, and the conductivity can be increased. The insulating film 233 is then subjected to heat treatment while in contact with the semiconductor film 119. Nitrogen and further hydrogen contained in the nitride insulating film are transferred to the semiconductor film 119, and the conductive film 220 is formed. can be formed.

[0161] Note that both the oxide semiconductor film and the light-transmitting conductive film are made of an oxide semiconductor material containing In or Ga. The impurity concentration of the oxide semiconductor film is different from that of the oxide semiconductor film. For example, the impurity concentration of the light-transmitting conductive film is high. is 5 x 1019 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1 x 10 18 atoms / cm 3 Less than or equal to 5×10 17 a toms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 is as follows: The hydrogen concentration in the light-transmitting conductive film is 8×10 19 atoms / cm 3 That's all good Preferably 1×10 20 atoms / cm 3 More preferably, 5×10 20 atoms / cm 3 In addition, compared with an oxide semiconductor film, The hydrogen concentration is 2 times, preferably 10 times or more.

[0162] In addition, the light-transmitting conductive film has a lower resistivity than the oxide semiconductor film. The resistivity of the oxide semiconductor film is 1×10 -8 more than 1x10 -1 Less than double It is preferable to use a concentration of 1×10 -3 Ωcm or more 1×10 4 Less than Ωcm, even better Preferably, the resistivity is 1×10 -3 Ωcm or more 1×10 -1 It is preferable that the resistivity is less than Ωcm.

[0163] In addition, the conductive film 220 has a region having a higher conductivity than the semiconductor film 111. At least the region of the conductive film 220 that is in contact with the insulating film 233 is n-type, and the semiconductor film 111 The region has a higher conductivity than the region in contact with the insulating film 229 .

[0164] In the semiconductor device according to the present embodiment, the method for operating the capacitive element 205 is as follows: The capacitance element 205 is operated in the same manner as the capacitance element 105 described in the first embodiment. During the period in which the potential of the conductive film 220 (in other words, the potential of the capacitance line 115) is normally In addition, the threshold voltage of the capacitance element 205 (MOS capacitor) is higher than the potential of the pixel electrode 221b. However, in the capacitor 205, the voltage Vth is set to be lower than that of the other electrode. The conductive film 220 is of n-type and has high conductivity, so the threshold voltage shifts in the negative direction. The potential of the conductive film 220 (in other words, the potential of the capacitance line 115) is The maximum possible state of the pixel electrode 221b is determined according to the amount of shift of the threshold voltage in the negative direction. The potential can be increased from a low potential. When the potential of the capacitance line 115 indicates a negative value, the potential of the capacitance line 115 is higher than the potential of the pixel electrode 221b. can be done.

[0165] As in this embodiment, the conductive film 220 which is one electrode of the capacitor element 205 is made to be an n-type. By increasing the conductivity, it is possible to shift the threshold voltage in the negative direction. Therefore, in order to operate the capacitor 205, as compared with the capacitor 105 of the first embodiment, Therefore, in this embodiment, the capacitance element 205 is This is preferable because the capacitor element 205 can be operated stably during the operation period. It is.

[0166] In addition, the conductive film 220 included in the capacitor element 205 is of n-type and has high conductivity. Even if the planar area of ​​the element 205 is reduced, a sufficient charge capacity can be obtained. The oxide semiconductor has a visible light transmittance of 80 to 90%. By reducing the area and providing a region in the pixel where the conductive film 220 is not formed, the backlight The transmittance of light emitted from a light source such as a light source can be increased.

[0167] <Method for manufacturing semiconductor device> Next, a method for manufacturing an element portion provided on a substrate 102 shown in this embodiment will be described with reference to FIG. 8 and 9.

[0168] First, the scanning line 107, the capacitance line 115, and the gate electrode 627 are formed on the substrate 102. A gate insulating film is formed on the substrate 102, the scanning line 107, the capacitance line 115, and the gate electrode 627. An insulating film 226 to be processed into a film 227 is formed, and a semiconductor film 111 and a semiconductor The insulating film 119 and the semiconductor film 628 are formed, and the semiconductor film 628 is formed on the insulating film 226. a signal line 109 including a source electrode; a conductive film 113 including a drain electrode of the transistor 103; After that, a conductive film 125 is formed to electrically connect the conductive film 220 and the capacitance line 115. The source electrode 629 and the drain electrode 639 are formed at the same time as the conductive film 125. , semiconductor film 111, semiconductor film 119 (later conductive film 220) and semiconductor film 628, signal Line 109, conductive film 113, conductive film 125, source electrode 629, and drain electrode 639 In addition, an insulating film 228 is formed on the insulating film 226, and an insulating film 230 is formed on the insulating film 228. (See FIG. 8(A)). Note that the steps up to this point are performed with reference to the first embodiment. can be done.

[0169] Next, a mask is formed on at least a region of the insulating film 230 that overlaps with the semiconductor film 119, The insulating film 228 and the insulating film 230 are processed using the mask to expose the semiconductor film 119. (See FIG. 8(B)). The mask is a resist pattern formed by a photolithography process. A mask can be used, and the processing can be performed by dry etching and wet etching. This can be done by one or both of the above.

[0170] Next, an insulating film 232 is formed on the exposed region of the semiconductor film 119 and on the insulating film 230. The insulating film 232 is the same as the insulating film 132 described in the first embodiment (see FIG. 9A). After the insulating film 232 is formed, the insulating film 232 is The heat treatment may be performed in a state where the substrate is in contact with the substrate. This can be done by referring to the following:

[0171] The insulating film 232 is a nitride insulating film, similar to the insulating film 132 of the first embodiment. Since the insulating film 232 is in contact with the semiconductor film 119, hydrogen contained in the nitride insulating film can be removed by the insulating film 232. Alternatively, nitrogen can be transferred to the semiconductor film 119 to make the semiconductor film 119 n-type. As a result, a conductive film 220 having increased conductivity can be formed.

[0172] Note that both the oxide semiconductor film and the light-transmitting conductive film are made of an oxide semiconductor material containing In or Ga. The impurity concentration of the oxide semiconductor film is different from that of the oxide semiconductor film. For example, the impurity concentration of the light-transmitting conductive film is high. is 5 x 10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1 x 10 18 atoms / cm3 Less than or equal to 5×10 17 a toms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 is as follows: The hydrogen concentration in the light-transmitting conductive film is 8×10 19 atoms / cm 3 That's all good Preferably 1×10 20 atoms / cm 3 More preferably, 5×10 20 atoms / cm 3 In addition, compared with an oxide semiconductor film, The hydrogen concentration is 2 times, preferably 10 times or more.

[0173] In addition, the light-transmitting conductive film has a lower resistivity than the oxide semiconductor film. The resistivity of the oxide semiconductor film is 1×10 -8 more than 1x10 -1 Less than double It is preferable to use a concentration of 1×10 -3 Ωcm or more 1×10 4 Less than Ωcm, even better Preferably, the resistivity is 1×10 -3 Ωcm or more 1×10 -1 It is preferable that the resistivity is less than Ωcm.

[0174] Next, the insulating film 226, the insulating film 228, the insulating film 230, and the insulating film 232 are removed from the capacitance line 115. An opening 223a reaching the capacitance line 115 is formed in the region overlapping the insulating film 228 and the insulating film 230. An opening 223 reaching the conductive film 125 is formed in a region of the insulating film 232 overlapping with the conductive film 125. b are formed, and a gate insulating film 227, an insulating film 229, an insulating film 231 and an insulating film 232 are formed. The border membrane 233 is formed (see FIG. 9(B)).

[0175] The opening 223a is a container for the insulating films 226, 228, 230, and 232. The opening 223b is formed by insulating film 228 so that a part of the region overlapping with the dose line 115 is exposed. The insulating film 230 and the insulating film 232 are formed such that a part of the region overlapping with the conductive film 125 is exposed. The insulating layer can be formed by forming a mask and processing the insulating layer using the mask. The conductive film 113 is overlapped with the insulating film 228, the insulating film 230, and the insulating film 232. 13. The opening 117 (see FIG. 6) is formed so as to extend beyond the opening 22. The mask and the opening 223b can be formed in the same manner. The processing is performed in the same manner as the scanning line 107, the capacitance line 115, and the gate electrode 627. It is possible.

[0176] Conventionally, the opening that reaches the capacitance line and the opening that reaches the conductive film (drain electrode) are made separately. In the past, a mask was formed for each process of forming the openings. By forming the insulating film 228, the insulating film 230, and the insulating film 232, a conductive film is formed. After forming the opening 223b reaching the conductive film 125 and the opening 117 reaching the conductive film 113, Since the conductive film 125 and the conductive film 113, which are also metals, remain, the etching is not performed any further. On the other hand, the insulating film 226 on the capacitance line 115 is etched to form an opening 22 reaching the capacitance line 115. That is, an opening 223a reaching the capacitance line 115 and an opening 3a reaching the conductive film 125 are formed. The opening 223b and the opening 117 reaching the conductive film 113 can be formed using the same mask. Therefore, the number of masks used in the manufacturing process can be reduced, and manufacturing costs can be reduced. .

[0177] In addition, the conductive film 220 is connected to an electrode 221a to be formed later via the conductive film 125. Therefore, in the opening 223b, the conductive film 125 also serves as an etching protection film for the conductive film 220. For this reason, after the opening 223b and the opening 117 are formed, the opening 223a is formed. During this process, etching of the conductive film 220 can be prevented. It is possible to increase it.

[0178] Finally, the electrode 221a, the pixel electrode 221b, and the conductive film 641 are formed to form the substrate. The element portion to be provided in 102 can be fabricated (see FIG. 7). This can also be carried out with reference to the first embodiment.

[0179] Through the above steps, the semiconductor device of this embodiment mode can be manufactured.

[0180] <Modification> In the semiconductor device according to one embodiment of the present invention, the structure of the capacitor can be changed as appropriate. A specific example of this structure will be described with reference to FIG. 10. Note that, in this case, FIG. 6 and FIG. Only the capacitive element 245, which is different from the capacitive element 205 described in 7, will be described.

[0181] In order to make the semiconductor film 119 n-type and increase the conductivity, the gate insulating film 227 is nitrided. The insulating film 225 and the insulating film 226 are stacked together. In the region where the semiconductor film 119 is provided, only the insulating film 225, which is a nitride insulating film, is provided. With this structure, the nitride insulating film, which is the insulating film 225, is formed on the lower surface of the semiconductor film 119. The semiconductor film 119 is made n-type, and a conductive film 220 with increased conductivity is formed. In this case, the dielectric film of the capacitance element 245 is the insulating film 129, the insulating film 1 31 and the insulating film 133. The insulating film 225 and the insulating film 226 are gate insulating films. The insulating film 225 may be the same as the insulating film 133. In order to realize this configuration, the following steps may be taken with reference to the first embodiment: By forming the structure shown in FIG. Since the insulating film 131 is not etched, it is possible to prevent the thickness of the semiconductor film 119 from decreasing. Therefore, the yield is improved as compared with the semiconductor device shown in FIG. 6 and FIG.

[0182] In the configuration shown in FIG. 10, the upper surface of the conductive film 220 is in contact with the insulating film 133. That is, in the insulating film 129 and the insulating film 131 shown in FIG. The region in contact with 220 may be removed. In this case, the dielectric film of the capacitance element 245 is an insulating film. 133. By configuring the upper and lower surfaces of the conductive film 220 to be in contact with the nitride insulating film, The semiconductor film is made n-type more efficiently and sufficiently than when it is in contact with the nitride insulating film only on one side, and the conductivity is increased. It can be made bigger.

[0183] Note that both the oxide semiconductor film and the light-transmitting conductive film are made of an oxide semiconductor material containing In or Ga. The impurity concentration of the oxide semiconductor film is different from that of the oxide semiconductor film. For example, the impurity concentration of the light-transmitting conductive film is high. is 5 x 10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1 x 10 18 atoms / cm3 Less than or equal to 5×10 17 a toms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 is as follows: The hydrogen concentration in the light-transmitting conductive film is 8×10 19 atoms / cm 3 That's all good Preferably 1×10 20 atoms / cm 3 More preferably, 5×10 20 atoms / cm 3 In addition, compared with an oxide semiconductor film, The hydrogen concentration is 2 times, preferably 10 times or more.

[0184] As described above, one electrode of the capacitor element is formed of the same material as the semiconductor film included in the transistor. By using the semiconductor film formed in the process, the aperture ratio can be increased, typically to 55% or more. Preferably, the capacitance can be increased to 60% or more, and the charge capacity of the capacitance element can be increased. As a result, a semiconductor device having excellent display quality can be obtained. It is possible.

[0185] In addition, oxygen vacancies are reduced in an oxide semiconductor film, which is a semiconductor film included in a transistor. Since impurities such as hydrogen are reduced, the semiconductor device according to one embodiment of the present invention can be favorably This results in a semiconductor device having excellent electrical characteristics.

[0186] The configurations shown in this embodiment may be used in conjunction with the configurations shown in other embodiments and their modified examples. They can be used in appropriate combination.

[0187] (Embodiment 3) In this embodiment, a transistor included in the semiconductor device described in the above embodiment is Another embodiment of a capacitor that can be applied to an oxide semiconductor film that is a semiconductor film will be described. Reveal.

[0188] Oxide semiconductor films are roughly classified into single-crystal oxide semiconductor films and non-single-crystal oxide semiconductor films. The non-single-crystal oxide semiconductor film includes an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, and a polycrystalline oxide semiconductor film. Compound semiconductor film, CAAC-OS (C Axis Aligned Crystallin e Oxide Semiconductor film, etc.

[0189] The amorphous oxide semiconductor film has irregular atomic arrangement and does not contain crystalline components. The oxide semiconductor film does not have any crystal parts even in a microscopic region, and the entire film has a completely amorphous structure. A typical example is an oxide semiconductor film.

[0190] The microcrystalline oxide semiconductor film is, for example, a microcrystal (nanocrystal) having a size of 1 nm or more and less than 10 nm. Therefore, the microcrystalline oxide semiconductor film has a higher crystallinity than the amorphous oxide semiconductor film. The atomic arrangement is highly regular. Therefore, the microcrystalline oxide semiconductor film has a higher atomic order than the amorphous oxide semiconductor film. It has the advantage of having a lower density of defect states than silicon.

[0191] The CAAC-OS film is one of the oxide semiconductor films that has multiple crystal parts. The crystal part is small enough to fit inside a cube with one side less than 100 nm. The crystal parts contained in the OS film are cubes with one side less than 10 nm, 5 nm, or 3 nm. The CAAC-OS film has a smaller size than the microcrystalline oxide semiconductor film. The defect density is low. The CAAC-OS film is described in detail below. cormorant.

[0192] The CAAC-OS film was observed under a transmission electron microscope (TEM). When observed using a quartz crystal microscope, clear boundaries between the crystals were observed. It is not possible to confirm the grain boundary. It can be said that the AAC-OS film is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0193] The CAAC-OS film was observed by TEM from a direction roughly parallel to the sample surface (cross-sectional TEM observation). When the metal atoms are observed, it can be confirmed that they are arranged in layers in the crystal part. Each layer of the CAAC-OS film is formed on a surface on which the film is to be formed (also called a surface on which the film is to be formed) or on a concave surface on the upper surface. The shape reflects a convexity, and is aligned parallel to the surface on which the CAAC-OS film is formed or the upper surface.

[0194] On the other hand, the CAAC-OS film was observed by TEM from a direction roughly perpendicular to the sample surface (plane T EM observation reveals that metal atoms are arranged in triangular or hexagonal shapes in the crystals. However, no regularity was observed in the arrangement of metal atoms between different crystal regions. do not have.

[0195] Cross-sectional and planar TEM observations revealed that the crystals in the CAAC-OS film had an orientation. It can be seen that...

[0196] X-ray diffraction (XRD) of CAAC-OS film When the structure is analyzed using the device, for example, InGaZnO 4 CAAC-OS with crystals of In the out-of-plane analysis of the film, the diffraction angle (2θ) peaked at around 31°. This peak may appear in InGaZnO 4 It is assigned to the (009) plane of the crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis faces the surface on which the film is formed or the upper surface. It can be seen that it is oriented in a roughly vertical direction.

[0197] On the other hand, in-p X-rays are incident on the CAAC-OS film from a direction approximately perpendicular to the c-axis. In the lane method, a peak may appear at 2θ around 56°. InGaZnO 4 It is attributed to the (110) plane of the InGaZnO crystal. 4 Single crystal of acid In the case of a nitride semiconductor film, 2θ is fixed at around 56°, and the normal vector of the sample surface is the axis (φ axis). When the sample is rotated and analyzed (φ scan), a crystal plane equivalent to the (110) plane is detected. In contrast, in the case of the CAAC-OS film, six peaks are observed, which are assigned to Even when φ is fixed at around 56° and scanned, no clear peak appears.

[0198] From the above, it is considered that the orientation of the a-axis and b-axis is uniform between different crystal regions in the CAAC-OS film. Although it is irregular, it has a c-axis orientation, and the c-axis is parallel to the normal vector of the surface on which it is formed or the upper surface. Therefore, the layered structure confirmed by the cross-sectional TEM observation mentioned above is consistent with the Each layer of arranged metal atoms is in a plane parallel to the ab plane of the crystal.

[0199] The crystalline part is formed when the CAAC-OS film is formed or after a crystallization process such as a heat treatment. As described above, the c-axis of the crystal is aligned to the surface on which the CAAC-OS film is to be formed. For example, in the CAAC-OS film, When the shape is changed by etching, the c-axis of the crystal is aligned with the CAAC-OS film. It may not be parallel to the face or top surface normal vector.

[0200] In addition, the crystallinity in the CAAC-OS film does not have to be uniform. When the crystalline part of the film is formed by crystal growth from the vicinity of the top surface of the CAAC-OS film, The area near the surface may have a higher crystallinity than the area near the surface on which it is formed. When impurities are added to the AC-OS film, the crystallinity of the region to which the impurities are added changes, resulting in a partial In some cases, regions of differing crystallinity may be formed.

[0201] In addition, InGaZnO 4 Out-of-plane crystallographic structure of CAAC-OS film In the analysis by the method, in addition to the peak at 2θ near 31°, a peak also appeared at 2θ near 36°. The peak at 2θ of around 36° may be due to the c-axis orientation in some parts of the CAAC-OS film. The CAAC-OS film contains crystals that do not have the 2θ value of about 31°. It is preferable that the spectrum shows a peak at 2θ of about 36° and does not show a peak at 2θ of about 36°.

[0202] The electrical characteristics of transistors using CAAC-OS films change when irradiated with visible or ultraviolet light. Therefore, the transistor has high reliability.

[0203] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, or a C The AAC-OS film may be a laminate film having two or more kinds of AAC-OS films.

[0204] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. refers to the state in which two straight lines are arranged at an angle of 80° or more and 100° or less. , including cases where the angle is between 85° and 95°.

[0205] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0206] In addition, the CAAC-OS film can be formed by sputtering a polycrystalline oxide semiconductor target. It is preferable to use the sputtering target and form a film by a sputtering method. When ions collide with the sputtering target, the crystalline regions in the sputtering target form ab-plane Sputtered particles in the form of plates or pellets cleaved from the ab plane In this case, the plate-shaped or pellet-shaped sputtering particles may peel off. The molecules reach the deposition surface while maintaining their crystalline state, forming a CAAC-OS film. It is possible.

[0207] For example, the equivalent circle diameter of a plane parallel to the ab plane is 3 nm or more. 10 nm or less, and the thickness (length in the direction perpendicular to the ab plane) is 0.7 nm or more and less than 1 nm In addition, the flat sputtered particles have a surface parallel to the ab plane that is an equilateral triangle or hexagon. Here, the circle-equivalent diameter of a face refers to the diameter of a perfect circle that is equal to the area of ​​the face.

[0208] In addition, the following conditions are preferably applied to form the CAAC-OS film.

[0209] By increasing the substrate temperature during film formation, migration of sputtered particles after reaching the substrate is suppressed. Specifically, the substrate temperature is set to 100° C. or higher and 740° C. or lower, preferably 200° C. or lower. The film is formed at a temperature of 500°C or less. By increasing the substrate temperature during film formation, a flat sputtering When the sputtering particles reach the substrate, migration occurs on the substrate, and the sputtering particles The flat surface of the sputtered particles is then attached to the substrate. At this time, the sputtered particles become positively charged, The sputtered particles adhere to the substrate while repelling each other, so the sputtered particles are unevenly distributed. Therefore, a CAAC-OS film having a uniform thickness can be formed without uneven overlapping.

[0210] By reducing the amount of impurities mixed in during film formation, it is possible to prevent the crystal state from being destroyed by impurities. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the deposition chamber can be In addition, the impurity concentration in the deposition gas may be reduced. The temperature is -80°C or lower, preferably -100°C or lower, and more preferably -120°C or lower. A membrane gas is used.

[0211] In addition, when forming a film by the sputtering method, a suction type vacuum pump is used to The vacuum pump can remove residual moisture in the deposition chamber where the film is deposited. For example, a cryopump, ion pump, or titanium sublimation pump can be used. In addition, a turbo molecular pump equipped with a cold trap is used to evaporate the gas in the deposition chamber. Residual moisture can also be removed. By using the above vacuum pump, the exhaust containing impurities can be It is possible to reduce backflow of air.

[0212] In addition, when forming a film using the sputtering method, in order to prevent an increase in the number of particles, It is preferable to use a target containing indium. Also, the atomic ratio of gallium is relatively high. It is preferable to use small oxide targets, especially targets containing indium. When using this method, the conductivity of the target can be increased and DC discharge becomes easier, so that a large surface area can be This makes it easier to handle substrates with large thicknesses, thereby improving the productivity of semiconductor devices.

[0213] In addition, by increasing the oxygen ratio in the deposition gas and optimizing the power, plasma damage during deposition is reduced. The oxygen ratio in the deposition gas is preferably 30% by volume or more, and more preferably 100% by volume or more. Expressed as volume percent.

[0214] After the CAAC-OS film is formed, heat treatment may be performed. The temperature is from 200°C to 500°C. The heating time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is performed in an inert atmosphere. After that, heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the -OS film can be reduced in a short time. In this case, oxygen vacancies may be generated in the CAAC-OS film due to the oxidation atmosphere. The oxygen vacancies can be reduced by the heat treatment at . The crystallinity of the CAAC-OS film can be further improved by the heat treatment at 1000P. The pressure may be reduced to a or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. At a lower temperature, the impurity concentration of the CAAC-OS film can be reduced in a shorter time.

[0215] As an example of a sputtering target, an In-Ga-Zn-O compound target is used. The details are shown below.

[0216] InO X powder, GaO Y Powder and ZnO Z The powders are mixed in a specified molar ratio and pressurized. After the treatment, the In- Pb thin film is heated at a temperature between 1000 and 1500°C to produce a polycrystalline In- The target is a Ga-Zn-based metal oxide. The pressure treatment is performed after cooling (or cooling naturally). The reaction may be performed while heating or while heating. Here, the predetermined molar ratio is, for example, InO X powder, GaO Y Powder and Z nO Z The powder is InO X :GaO Y :ZnO Z =2:2:1, 8:4:3, 3:1:1, The ratio is 1:1:1, 4:2:3 or 3:1:2. The powder type and the mixture The molar ratio may be appropriately changed depending on the sputtering target to be prepared.

[0217] Here, oxide semiconductors (referred to as OS) and silicon semiconductors (Si The comparison of the oxide semiconductors is shown in Table 1. Use.

[0218] [Table 1]

[0219] The crystalline state of the oxide semiconductor can be, for example, an amorphous oxide semiconductor (a- OS, a-OS:H), microcrystalline oxide semiconductors (nc-OS, μc-OS), polycrystalline oxide Semiconductor (polycrystalline OS), Continuous-Atom Crystal Oxide Semiconductor (CAAC-OS), Single-Crystal Oxide Semiconductor (single crystal OS) and others. The crystal state of silicon can be classified into the following types, as shown in Table 1. , amorphous silicon (a-Si and a-Si:H), microcrystalline silicon (nc-Si, μc-S i), polycrystalline silicon (polycrystalline Si), continuous crystal silicon (CG (Continuous Examples include single grain silicon, and single crystal silicon (single crystal Si).

[0220] For oxide semiconductors in each crystal state, the electron beam diameter was focused to 10 nmφ or less. When electron beam diffraction (ultrafine electron beam diffraction) is performed using a ray, the following electron beam diffraction pattern ( In amorphous oxide semiconductors, a halo pattern ( This phenomenon is also called rolling or halo.) is observed. In the case of polycrystalline oxide semiconductor, spots and / or ring patterns are observed. In the case of a continuous crystal oxide semiconductor, spots are observed. In the case of a single crystal oxide semiconductor, spots are observed.

[0221] In addition, the ultrafine electron diffraction pattern shows that the crystal part of the microcrystalline oxide semiconductor is nanometer ( The diameter of the polycrystalline oxide semiconductor is in the range of nm to micrometers (μm). It can be seen that there are grain boundaries between the crystal parts, and the boundaries are discontinuous. Continuous crystal oxide It can be seen that no boundaries are observed between the crystalline regions of the semiconductor, and the crystalline regions are continuously connected.

[0222] The density of an oxide semiconductor in each crystalline state will be described. The density of the microcrystalline oxide semiconductor is low. The density of the continuous crystalline oxide semiconductor is medium. That is, the density of the continuous crystal oxide semiconductor is higher than that of the microcrystalline oxide semiconductor. The density of the amorphous semiconductor is higher than that of the amorphous oxide semiconductor.

[0223] The DOS (density of state) in oxide semiconductors in each crystal state e) The feature of amorphous oxide semiconductors is that they have a high DOS. Microcrystalline oxide semiconductors have a high DOS. S is somewhat low. Continuous crystal oxide semiconductors have a low DOS. Single crystal oxide semiconductors have an extremely low DOS. That is, the DOS of a single crystal oxide semiconductor is lower than that of a continuous crystal oxide semiconductor. Crystalline oxide semiconductors have a lower DOS than microcrystalline oxide semiconductors, and microcrystalline oxide semiconductors have a lower DOS than amorphous oxide semiconductors. The DOS is lower than that of nitride semiconductors.

[0224] The CAAC-OS film is formed by the following method.

[0225] First, a first oxide semiconductor film is formed to a thickness of 1 nm or more and less than 10 nm. The semiconductor film is formed by sputtering. Specifically, the substrate temperature is set to 100°C or higher. The temperature is set to 500° C. or less, preferably 150° C. to 450° C., and the oxygen ratio in the deposition gas is set to 30 % by volume or more, preferably 100% by volume.

[0226] Next, heat treatment is performed to convert the first oxide semiconductor film into a first CAAC-OS film having high crystallinity. The temperature of the heat treatment is 350°C or higher and 740°C or lower, preferably 450°C or higher and 650°C or lower. The heat treatment time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Alternatively, heat treatment is performed in an inert atmosphere, and then heat treatment is performed in an oxidizing atmosphere. By the heat treatment in the atmosphere, the impurity concentration of the first oxide semiconductor film can be reduced in a short time. On the other hand, oxygen vacancies are generated in the first oxide semiconductor film by heat treatment in an inert atmosphere. In this case, the oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere. Heat treatment can be performed at 1000 Pa or less, 100 Pa or less, 10 Pa or less, or The step of removing the oxide semiconductor film from the first oxide semiconductor film may be performed under a reduced pressure of 1 Pa or less. can be reduced in an even shorter time.

[0227] The first oxide semiconductor film has a thickness of 1 nm or more and less than 10 nm. Compared with a thickness of 0 nm or more, it can be easily crystallized by heat treatment.

[0228] Next, a second oxide semiconductor film having the same composition as the first oxide semiconductor film is formed to a thickness of 10 nm or more. The second oxide semiconductor film is formed to a thickness of 0 nm or less by a sputtering method. Specifically, the substrate temperature is set to 100° C. or higher and 500° C. or lower, preferably 150° C. or higher and 450° C. or lower. The oxygen ratio in the deposition gas is set to 30% by volume or more, preferably 100% by volume. To film.

[0229] Next, heat treatment is performed to grow a second oxide semiconductor film from the first CAAC-OS film through solid phase epitaxial growth. The second CAAC-OS film is formed with high crystallinity by the heat treatment at a temperature of 350 The temperature is from 450°C to 650°C, preferably from 450°C to 650°C. The heating time is from 1 minute to 24 hours, preferably from 6 minutes to 4 hours. The heat treatment may be performed in an inert atmosphere or an oxidizing atmosphere. Preferably, the heat treatment is performed in an inert atmosphere. After that, a heat treatment is performed in an oxidizing atmosphere. The impurity concentration of the nitride semiconductor film can be reduced in a short time. Oxygen vacancies may be generated in the second oxide semiconductor film by the heat treatment. The oxygen vacancies can be reduced by heat treatment in a reactive atmosphere. The pressure may be reduced to 000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. Under reduced pressure, the impurity concentration in the second oxide semiconductor film can be reduced in a shorter time. Cut.

[0230] The oxide semiconductor film may have a structure in which a plurality of oxide semiconductor films are stacked. For example, The oxide semiconductor film is a stack of a first oxide semiconductor film and a second oxide semiconductor film. The oxide semiconductor film and the second oxide semiconductor film may each be made of a metal oxide having a different atomic ratio. For example, the first oxide semiconductor film may include an oxide containing two kinds of metals or an oxide containing three kinds of metals. The first oxide semiconductor film is formed by using one of the oxides containing four kinds of metals. Semiconductor film and oxide containing two different metals, oxide containing three different metals, oxide containing four different metals An oxide containing the following may also be used.

[0231] The oxide semiconductor film has a two-layer structure including a first oxide semiconductor film and a second oxide semiconductor film. The elements may be the same, but the atomic ratio of the elements may be different. The atomic ratio of the second oxide semiconductor film is In:Ga:Zn=3:1:2. The atomic ratio of the first oxide semiconductor film may be In:Ga:Zn=1:1:1. The atomic ratio of the second oxide semiconductor film was In:Ga:Zn=2:1:3. It may be 1:3:2. The atomic ratio of each oxide semiconductor film includes fluctuations of plus or minus 20% of the above atomic ratio as an error. In this case, among the first oxide semiconductor film and the second oxide semiconductor film, the atomic ratio of In and Ga in the oxide semiconductor film on the side closer to the gate electrode (channel side) may be In ≥ Ga. Also,

[0232] the atomic ratio of In and Ga in the oxide semiconductor film on the side farther from the gate electrode (back channel side) may be In < Ga. With these laminated structures, a transistor with high field-effect mobility can be fabricated. On the other hand, by setting the atomic ratio of In and Ga in the oxide semiconductor film on the side closer to the gate electrode (channel side) to In < Ga and the atomic ratio of In and Ga in the oxide semiconductor film on the back channel side to In ≥ Ga, the variation amount of the threshold voltage due to the change over time of the transistor and the reliability test can be reduced. The first oxide semiconductor film with an atomic ratio of In:Ga:Zn = 1:3:2 can be formed by a sputtering method using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:2. With the substrate temperature at room temperature, it can be formed using argon or a mixed gas of argon and oxygen as the sputtering gas. The second oxide semiconductor film with an atomic ratio of In:Ga:Zn = 3:1: 2 can be formed in the same manner as the first oxide semiconductor film using an oxide target with an atomic ratio of In:Ga:Zn = 3:1:2. In addition, in order to impart stable electrical characteristics to a transistor in which a channel is formed in the oxide semiconductor film, for example, in a multilayer film including the oxide semiconductor film, where the channel is formed the variation amount of the threshold voltage due to the change over time of the transistor and the reliability test can be reduced.

[0233] The first oxide semiconductor film with an atomic ratio of In:Ga:Zn = 1:3:2 can be formed by a sputtering method using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:2. With the substrate temperature at room temperature, it can be formed using argon or a mixed gas of argon and oxygen as the sputtering gas. The second oxide semiconductor film with an atomic ratio of In:Ga:Zn = 3:1: 2 can be formed in the same manner as the first oxide semiconductor film using an oxide target with an atomic ratio of In:Ga:Zn = 3:1:2. 2 can be formed in the same manner as the first oxide semiconductor film using an oxide target with an atomic ratio of In:Ga:Zn = 3:1:2. The second oxide semiconductor film with an atomic ratio of In:Ga:Zn = 3:1:2 can be formed using an oxide target with an atomic ratio of In:Ga:Zn = 3:1:2, in the same way as the first oxide semiconductor film. In addition, in order to impart stable electrical characteristics to a transistor in which a channel is formed in the oxide semiconductor film, for example, in a multilayer film including the oxide semiconductor film, where the channel is formed

[0234] In order to impart stable electrical characteristics to a transistor in which a channel is formed in the oxide semiconductor film, for example, in a multilayer film including the oxide semiconductor film, where the channel is formed the atomic ratio of In and Ga in the oxide semiconductor film on the side closer to the gate electrode (channel side) may be In ≥ Ga. Also, It is effective to reduce the impurity concentration in the layer to be treated and make it highly intrinsic. This refers to reducing the impurity concentration in the oxide semiconductor film to make it intrinsic or substantially intrinsic. Note that when an oxide semiconductor film is substantially intrinsic, the carrier density of the oxide semiconductor film is 1×10 17 cm 3 Less than 1 x 10 15 cm 3 less than 1×10 13 cm 3 Less than In the oxide semiconductor film, hydrogen, nitrogen, carbon, silicon, and a metal other than the main component are In order to reduce the impurity concentration in the oxide semiconductor film, It is also preferable to reduce the impurity concentration of the above.

[0235] For example, silicon in an oxide semiconductor film forms an impurity level. The oxides become traps and can degrade the electrical characteristics of the transistor. The silicon concentration of the semiconductor film is 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than The gate insulating film of the transistor is made of silicon oxide, silicon oxynitride, Silicon-containing insulating films such as silicon nitride and silicon oxynitride are widely used, so It is preferable to form the channel of the compound semiconductor film in a layer that is not in contact with the gate insulating film.

[0236] In addition, hydrogen and nitrogen in the oxide semiconductor film form donor levels and increase the carrier density. It will be a big deal.

[0237] In addition, when a channel is formed at the interface between the gate insulating film and the oxide semiconductor film, Interface scattering occurs, and the field effect mobility of the transistor decreases. The channel of the oxide semiconductor film is preferably formed in a layer that is not in contact with the gate insulating film.

[0238] In order to separate the channel of the transistor from the gate insulating film, for example, For example, the multilayer film may include a first oxide film, an oxide semiconductor film, and a second oxide film. The oxide semiconductor film is a first oxide film, an oxide semiconductor film, and a second oxide film. The constituent elements may be the same, but the atomic ratio of each may be different. The oxide semiconductor film which serves as a channel of the transistor can be separated from the gate insulating film.

[0239] In addition, in the capacitance element, at least the oxide semiconductor is Since carriers are induced in the layer formed of the same layer as the body membrane, it functions as part of the electrode. In addition, a layer formed of the same layer as the first oxide film, a layer formed of the same layer as the second oxide film However, since the carrier density is sufficiently high compared to the insulating film such as the gate insulating film, It functions as a part.

[0240] Here, a structure of a multilayer film including an oxide semiconductor film will be described with reference to FIGS.

[0241] The transistor illustrated in FIG. 11 includes a first oxide film 199a, an oxide semiconductor film 199b, and A second oxide film 199c is laminated in this order from the gate insulating film 127 side.

[0242] The material constituting the first oxide film 199a and the second oxide film 199c is InM 1x Zinc y O z (x≧1, y>1, z>0, M 1 Use materials that can be expressed as Ga, Hf, etc. However, the material constituting the first oxide film 199a and the second oxide film 199c does not include Ga. When containing InM, the proportion of Ga is high. 1x Zinc y O z In the notation If the material can be used with a film thickness of more than 10, powder may be generated during film formation, making this unsuitable.

[0243] The material forming the oxide semiconductor film 199b is InM 2x Zinc y O z (x≧1, y ≧x, z>0, M 2 Use materials that can be expressed as (Ga, Sn, etc.).

[0244] The lower end of the conduction band of the first oxide film 199a and the lower end of the conduction band of the second oxide film 199c The well in which the bottom of the conduction band of the oxide semiconductor film 199b is the deepest from the vacuum level compared to the well in which ... oxide semiconductor film 199b is the deepest from the vacuum level compared The materials of the first oxide film, the oxide semiconductor film, and the second oxide film are arranged to form a type structure. Select the fee appropriately.

[0245] Note that the first oxide film 199a, the oxide semiconductor film 199b, and the second oxide film 199 c shows a U-shaped well (U Shape W) where the energy of the conduction band edge changes continuously. It can also be called ell.

[0246] When silicon or carbon, which is one of the Group 14 elements, diffuses into the oxide semiconductor film, Therefore, when silicon or carbon is contained in the oxide semiconductor film, the oxide semiconductor film is oxidized. In particular, the oxide semiconductor film 199b is doped with a large amount of Group 14 elements. The first oxide film 199a and the second oxide film 199c are formed to prevent the carrier particles from entering the It is preferable that the oxide semiconductor film 199b serving as the base be sandwiched or surrounded by the insulating film 199. The first oxide film 199a and the second oxide film 199c are made of Group 14 elements such as silicon and carbon. The oxide semiconductor film 199b can also be called a barrier film that prevents elements from entering the oxide semiconductor film 199b.

[0247] In addition, the first oxide film 199a, the oxide semiconductor film 199b, and the second oxide film 199 In the oxide semiconductor film, oxygen diffuses between the two layers, reducing oxygen vacancies in the oxide semiconductor film that serves as the channel. can be done.

[0248] For example, when the atomic ratio of the first oxide film 199a is In:Ga:Zn=1:3:2, In: Ga:Zn=1:3:4, In:Ga:Zn=1:6:2 or In:Ga:Zn=1: The atomic ratio of the oxide semiconductor film 199b is In:Ga:Zn=3:1:2. Alternatively, the atomic ratio of the second oxide film 199c may be In:Ga:Zn=1:1:1. The second oxide film 199c is an oxide having an atomic ratio of In:Ga:Zn=1:1:1. It can be formed by a sputtering method using a target.

[0249] Alternatively, the first oxide film 199a may be formed by a method in which the atomic ratio of In:Ga:Zn is 1:3:2, In :Ga:Zn=1:3:4, In:Ga:Zn=1:6:2 or In:Ga:Zn=1 The oxide semiconductor film 199b has an atomic ratio of In:Ga:Zn=1:1:1. Alternatively, the atomic ratio of In:Ga:Zn is 1:3:2, and the second oxide film 199c is :Ga:Zn=1:3:2, In:Ga:Zn=1:3:4, In:Ga:Zn=1:6 Alternatively, a three-layer structure with In:Ga:Zn=1:6:10 may be used.

[0250] The structure of the first oxide film 199a, the oxide semiconductor film 199b, and the second oxide film 199c Since the components are the same, the oxide semiconductor film 199b has a uniform thickness at the interface with the first oxide film 199a. In particular, the defect level (trap level) in is smaller than the defect level at the interface between the gate insulating film 127 and the first oxide film 199a. Therefore, by using a multilayer film as described above, it is possible to reduce deterioration over time and to perform reliability tests on the transistor. Therefore, the amount of variation in the threshold voltage due to the change in the capacitance can be reduced.

[0251] In addition, the lower end of the conduction band of the first oxide film 199a and the lower end of the conduction band of the second oxide film 199c The bottom of the conduction band of the oxide semiconductor film 199b is shallowest from the vacuum level compared to the bottom of the conduction band of the oxide semiconductor film 199b. The first oxide film, the oxide semiconductor film, and the second oxide film are arranged so as to form a well structure. By appropriately selecting the film material, it is possible to increase the field effect mobility of the transistor. At the same time, it reduces the amount of variation in threshold voltage caused by aging and reliability testing of transistors. It is possible.

[0252] In addition, the first oxide film 199a, the oxide semiconductor film 199b, and the second oxide film 199 c may be made of oxide semiconductors with different crystallinity. A structure in which a polycrystalline oxide semiconductor, an amorphous oxide semiconductor, and a CAAC-OS are appropriately combined In addition, the first oxide film 199a, the oxide semiconductor film 199b, and the second oxide film 199c may be formed in a substantially rectangular shape. When an amorphous oxide semiconductor is used for any one of the oxide films 199c, This reduces the internal stress and external stress, reducing the variation in transistor characteristics. This makes it possible to reduce the amount of variation in threshold voltage due to deterioration over time of a transistor or due to reliability testing.

[0253] At least the oxide semiconductor film 199b which can become a channel is a CAAC-OS film. In addition, in this embodiment, the oxide semiconductor film on the back channel side is preferably a second The oxide film 199c is preferably an amorphous or CAAC-OS film. By adopting such a structure, the threshold voltage of the transistor can be prevented from changing over time or due to reliability testing. The amount of fluctuation can be reduced.

[0254] Here, the localized states of the oxide semiconductor film will be described. The results were evaluated using PM (Constant Photocurrent Method) measurements. The results will be explained.

[0255] First, the structure of the measurement sample will be described.

[0256] The measurement sample was a sample having an oxide semiconductor film provided over a glass substrate and a sample having a thickness of 100 nm and a thickness of 100 nm. The pixel includes a pair of electrodes and an insulating film that covers the oxide semiconductor film and the pair of electrodes.

[0257] Next, a method for forming the oxide semiconductor film included in the measurement sample will be described.

[0258] The target is In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]). The deposition gas was argon gas at 30 sccm and oxygen gas at 15 sccm. The conditions used were a pressure of 0.4 Pa, a substrate temperature of room temperature, and a DC power of 0.5 kW. The first oxide semiconductor film was formed by a sputtering method using a The conductive film is a microcrystalline oxide semiconductor film.

[0259] The first oxide semiconductor film was heated in a nitrogen atmosphere at 450° C. for 1 hour and then The first oxide semiconductor film is heated in an oxygen atmosphere for one hour to release hydrogen from the first oxide semiconductor film. and a treatment of supplying oxygen to the first oxide semiconductor film to form a second oxide semiconductor film. Note that the second oxide semiconductor film was a microcrystalline oxide semiconductor film.

[0260] Next, a measurement sample having a first oxide semiconductor film and a measurement sample having a second oxide semiconductor film were The measurement sample was subjected to CPM measurement. With a voltage applied between the electrodes, the measurement sample surface between the terminals is irradiated with light so that the photocurrent value is constant. The amount of light irradiated was adjusted, and the absorption coefficient was derived from the amount of irradiated light in a desired wavelength range.

[0261] The absorption coefficients of each sample were measured using CPM, and the absorption coefficients due to the band tail were subtracted from the absorption coefficients. The absorption coefficients due to defects are shown in FIG. 31. In FIG. 31, the horizontal axis is the absorption 31 represents the coefficient, and the vertical axis represents the light energy. The lower end of the conduction band is set to 0 eV, and the upper end of the valence band is set to 3.15 eV. In this figure, each curve indicates the relationship between the absorption coefficient and the light energy, and corresponds to a defect level.

[0262] FIG. 31A shows the measurement results of the measurement sample including the first oxide semiconductor film. The absorption coefficient is 5.28×10 -1 cm -1 FIG. 31(B) shows the second oxidation The absorption coefficient due to defect levels is 1.75× 10 -2 cm -1 It was.

[0263] Therefore, defects in the oxide semiconductor film can be reduced by the heat treatment.

[0264] The first oxide semiconductor film and the second oxide semiconductor film were measured by X-ray reflectometry (XR The film density was measured using X-ray Reflectometry (R). The film density of the oxide semiconductor film is 5.9 g / cm 3 and the film density of the second oxide semiconductor film is is 6.1g / cm 3 It was.

[0265] Therefore, the film density of the oxide semiconductor film can be increased by the heat treatment.

[0266] That is, in an oxide semiconductor film, the higher the film density, the fewer defects contained in the film. I understand.

[0267] Here, the localized states of the oxide semiconductor film will be described. The results were evaluated using PM (Constant Photocurrent Method) measurements. The results will be explained.

[0268] First, the structure of the sample measured by CPM will be described.

[0269] The measurement sample was a sample having an oxide semiconductor film provided over a glass substrate and a sample having a thickness of 100 nm and a thickness of 100 nm. The pixel includes a pair of electrodes and an insulating film that covers the oxide semiconductor film and the pair of electrodes.

[0270] Next, a method for forming the oxide semiconductor film included in the measurement sample will be described.

[0271] The target is In-Ga-Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]). The deposition gas was argon gas at 30 sccm and oxygen gas at 15 sccm. The conditions were: pressure 0.4 Pa, substrate temperature 400°C, and DC power 0.5 kW. Next, an oxide semiconductor film was formed by sputtering using a nitrogen atmosphere at 450° C. After heating in an oxygen atmosphere at 450° C. for 1 hour, the oxide semiconductor film was heated in an oxygen atmosphere at 450° C. for 1 hour. A treatment for releasing hydrogen contained in the oxide semiconductor film and a treatment for supplying oxygen to the oxide semiconductor film were performed. The oxide semiconductor film is a CAAC-OS film.

[0272] Next, a CPM measurement was performed on a measurement sample having an oxide semiconductor film. A photoelectric conversion element is generated when a voltage is applied between a first electrode and a second electrode provided in contact with the semiconductor film. The amount of light irradiated onto the sample surface between the terminals is adjusted so that the current value is constant, and the desired wavelength range is obtained. The absorption coefficient was derived from the amount of irradiated light.

[0273] The absorption coefficient due to the band tail was removed from the absorption coefficient obtained by CPM measurement of the measurement sample. The absorption coefficient, i.e., the absorption coefficient due to defects, is shown in FIG. 32. In FIG. 32, the horizontal axis is the absorption coefficient The vertical axis of FIG. 32 represents the number of times the oxide semiconductor film is heated, and the vertical axis represents the light energy. The lower end of the conduction band is set to 0 eV, and the upper end of the valence band is set to 3.15 eV. Each curve indicates the relationship between the absorption coefficient and the light energy, and corresponds to a defect level.

[0274] In the curve shown in FIG. 32, the absorption coefficient due to the defect level is 5.86×10 -4 cm -1 That is, the CAAC-OS film has an absorption coefficient due to defect levels of 1×10 -3 cm -1 Less than 1 x 10 -4 cm -1 This means that the film has a low defect level density.

[0275] Regarding the oxide semiconductor film, X-ray reflectometry (XRR) was used. The film density of the oxide semiconductor film was measured using a dc sintering method. cm 3 That is, the CAAC-OS film has a high film density.

[0276] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used.

[0277] (Embodiment 4) In this embodiment, a CA A model of crystal growth of an AC-OS film will be described with reference to FIGS.

[0278] FIG. 17(A) shows a state in which ions 601 collide with a sputtering target 600, causing sputtering. FIG. 6 is a schematic diagram showing the state in which a sputtering particle 602 is peeled off. 02 may be a hexagonal prism whose hexagonal faces are parallel to the ab plane, or a triangular prism. In this case, the direction perpendicular to the hexagonal or triangular faces is the c-axis direction (see FIG. 1). 7(B). The sputtering particles 602 vary depending on the type of oxide, but -b The diameter (equivalent circle diameter) of the surface parallel to the surface is 1 nm or more and 30 nm or less, or 1 nm or more and 10 The size of the ions 601 is about 1 nm or less. In addition to the ions, argon cations may be used. In addition, cations of other rare gases may also be used.

[0279] By using oxygen cations as ions 601, plasma damage during film formation is reduced. Therefore, the ions 601 can be incident on the surface of the sputtering target 600. When the sputtering target 600 is struck, the crystallinity of the sputtering target 600 decreases, or the sputtering target 600 becomes amorphous. This can prevent the deterioration of the quality of the product.

[0280] The detached sputtered particles 602 are preferably positively charged. The timing at which the sputtering particles 602 are positively charged is not particularly important. The electrostatic particles 602 may become positively charged by being exposed to the plasma. It may become positively charged by receiving a charge when it collides with an oxygen atom. Ions 601 bond to the side, top or bottom surface of sputtered particles 602. This can cause the material to become positively charged.

[0281] The sputtered particles 602 have positive charges at the corners of the hexagonal faces. By having positive charges at the corners of the tubular surface, the positive charges repel each other and the tubular shape is maintained. It can be held.

[0282] In order for the corners of the hexagonal faces of the sputtering particle 602 to have a positive charge, It is preferable to use a direct current (DC) power source. Note that a radio frequency (RF) power source or an alternating current (AC) power source is also not applicable. However, the RF power supply is not suitable for sputtering, which can deposit films on large-area substrates. In addition, DC power is preferable to AC power for the following reasons: This is considered desirable.

[0283] When an AC power source is used, adjacent targets alternate between cathode and anode potentials. In the period A shown in FIG. 18(A), the target 1 is captured as shown in FIG. 18(B1). The cathode functions as a cathode, and the target 2 functions as an anode. In period B, as shown in FIG. 18(B2), target 1 functions as an anode, and target Get 2 functions as a cathode. The total duration of period A and period B is 20 to 50 μs. Periods A and B are repeated at regular intervals.

[0284] When the sputtering particles 602 are positively charged, they repel each other, It can maintain its flat shape. However, when using an AC power source, the electric field momentarily Since there is a time when the charge is not applied, the charge on the sputtering particle 602 disappears. However, the structure of the sputtered particles may be destroyed (see FIG. 18(C)). It can be seen that using a DC power supply is preferable to using an AC power supply.

[0285] The manner in which sputtered particles are deposited on a film-forming surface will be described below with reference to FIG. FIG. 19(A) shows the case where the film was formed with the substrate heated, and FIG. 19(B) shows the case where the film was formed without the substrate heated. The figure shows the case where a film was formed by

[0286] As shown in FIG. 19A, when the substrate is heated, the sputtering particles 602 are directed toward the deposition surface 60 In 3, other sputtered particles 602 move to areas where they are not deposited, and migration occurs. The particles accumulate by bonding next to already deposited particles through the movement of the particles.

[0287] The CAAC-OS film obtained by this mechanism has an amorphous surface and an amorphous insulating film surface. Even the surface of an amorphous oxide film has high crystallinity.

[0288] As shown in FIG. 19B, when the substrate is not heated, the sputtered particles 602 are deposited on the deposition surface 603. Therefore, the sputtered particles 602 are already falling on other sputtered particles. The oxides are deposited randomly, including in the area where 602 is deposited. The oxide film thus obtained is not uniform in thickness and has a random crystal orientation. The film maintains the crystallinity of the flat sputtered particles 602 to some extent, so that the resulting film The oxide film has crystal parts.

[0289] As described above, the sputtering particles 602 are, for example, perpendicular to a plane parallel to the ab plane. The diameter is about 1 nm to 30 nm, or 1 nm to 10 nm, and the film is formed. The crystals in the oxide film may be smaller than the sputtered particles 602. For example, the oxide film may have crystal parts of 10 nm or less, or 5 nm or less. The oxide film having such crystal parts is called nanocrystallin (nc). e) It is called an oxide film.

[0290] A nanocrystalline oxide film is equivalent to a film with a macroscopically disordered atomic arrangement. , a wide measurement range (e.g., a beam diameter larger than the sputtering particles 602) X-ray diffraction (XRD) analysis shows that the peaks indicate orientation. In addition, the beam diameter may be larger than the sputtering particle 602. In the electron diffraction pattern obtained by using an electron beam having the above structure, a halo pattern is observed. In this case, for example, the beam diameter of the electron beam is set to be sufficiently larger than the sputtering particles 602. The electron microbeam diffraction pattern obtained by measuring the nanocrystalline oxide film with a very small diameter You can observe spots (bright points) here.

[0291] Here, regarding the electron diffraction patterns of the nanocrystalline oxide semiconductor film, FIGS. The following description will be given using this.

[0292] The nanocrystalline oxide semiconductor film was analyzed by electron beam diffraction (ultrafine electron beam) with a beam diameter of 10 nmφ or less. In the electron diffraction pattern obtained by the electron beam diffraction method, a halo pattern indicating an amorphous state is also observed. Unlike regular spots that indicate a crystalline state oriented in a certain plane, 1 is an oxide semiconductor film in which spots are observed.

[0293] Figure 42(A) shows a cross-sectional TEM (Transmission Emission Spectroscopy) image of a nanocrystalline oxide semiconductor film. The transmission electron microscopy images are shown in FIG. (B) shows the electron diffraction pattern measured using a microelectron diffraction microscope at point 1 in Figure 42(A). The pattern is shown in FIG. 42(C) by using ultramicro electron beam diffraction at point 2 in FIG. 42(A). The measured electron beam diffraction pattern is shown in FIG. 42(D) at point 3 in FIG. 42(A). The electron diffraction patterns measured using electron diffraction are shown.

[0294] In Fig. 42, an In-Ga-Zn oxide film is used as an example of a nanocrystalline oxide semiconductor film. A sample was prepared by depositing a film of 50 nm on a quartz glass substrate. The deposition conditions for the conductor film were as follows: oxide target with In:Ga:Zn=1:1:1 (atomic ratio) The experiment was carried out under an oxygen atmosphere (flow rate 45 sccm), pressure 0.4 Pa, and DC power supply 0 The power consumption was 1.5 kW and the substrate temperature was room temperature. The specimen is then sliced ​​to a width of 100 mm or less (e.g., 40 nm ± 10 nm) and a cross-sectional TEM image is taken. The electron diffraction pattern was obtained by folding.

[0295] Figure 42(A) shows the results of a transmission electron microscope (Hitachi High-Technologies Corporation's H-9000NAR Nanocrystalline oxide semiconductor photographed at an accelerating voltage of 300 kV and a magnification of 2 million times. 42(B) to 42(D) are TEM images of the cross section of the membrane. (Hitachi High-Technologies Corporation "HF-2000") was used, and the accelerating voltage was 200 kV. The electron diffraction pattern was obtained by ultrafine electron diffraction with a diameter of about 1 nmφ. The measurement range of ultrafine electron diffraction with a beam diameter of approximately 1 nmφ is 5 nmφ or more. It is less than 0 nmφ.

[0296] As shown in FIG. 42B, the nanocrystalline oxide semiconductor film was analyzed by electron microscopy using electron diffraction. In the X-ray diffraction pattern, multiple spots (bright spots) arranged in a circular pattern are observed. In other words, in the nanocrystalline oxide semiconductor film, multiple spots are distributed in a circumferential (concentric) shape. Alternatively, multiple spots distributed in a circular pattern are observed forming multiple concentric circles. It can also be said that it will be achieved.

[0297] In addition, FIG. 42(D) shows the vicinity of the interface with the quartz glass substrate, and FIG. In the center of the thickness direction of FIG. 42(C), multiple circumferentially distributed In FIG. 42(C), a circular spot is observed from the main spot. The distance to the surface was 3.88 / nm to 4.93 / nm. Converted to interplanar spacing, it is 0. 203nm to 0.257nm.

[0298] From the ultrafine electron diffraction pattern in FIG. 42, the nanocrystalline oxide semiconductor film has irregular plane orientation. It can be seen that the film contains a mixture of crystal parts of different sizes.

[0299] Next, FIG. 43(A) shows a planar TEM image of the nanocrystalline oxide semiconductor film. In (B), the area circled in FIG. 43(A) was measured using selected area electron diffraction. The electron diffraction pattern is shown.

[0300] In Fig. 43, an In-Ga-Zn oxide film is used as an example of a nanocrystalline oxide semiconductor film. A sample was prepared by depositing a film of 30 nm on a quartz glass substrate. The deposition conditions for the conductor film were as follows: oxide target with In:Ga:Zn=1:1:1 (atomic ratio) The experiment was carried out under an oxygen atmosphere (flow rate 45 sccm), pressure 0.4 Pa, and DC power supply 0 The power was set to 0.5 kW and the substrate temperature was room temperature. The samples were then sliced ​​and the nanocrystalline oxide semiconductor films were Plan-view TEM images and selected area electron diffraction patterns were obtained.

[0301] Figure 43(A) shows the results of a transmission electron microscope (Hitachi High-Technologies Corporation's H-9000NAR Nanocrystalline oxide semiconductor photographed using a 300kV accelerating voltage and 500,000x magnification. FIG. 43(B) is a planar TEM photograph of the film. This is an electron beam diffraction pattern obtained by X-ray diffraction. The measurement range is 300 nmφ or more.

[0302] As shown in FIG. 43(B), in the nanocrystalline oxide semiconductor film, the measurement In the electron diffraction pattern using the wide range selected area electron diffraction, The multiple spots observed in the previous study are no longer seen, and a halo pattern is observed.

[0303] Next, FIG. 44 shows an outline of the distribution of diffraction intensity in the electron beam diffraction patterns of FIG. 42 and FIG. FIG. 44(A) shows the ultrafine electron beam diffraction patterns shown in FIG. 42(B) to FIG. 42(D). FIG. 44(B) is a schematic diagram of the distribution of diffraction intensity in the beam. FIG. 44( C) is the concept of the distribution of diffraction intensities in the electron diffraction pattern of a single crystal or polycrystalline structure. FIG.

[0304] In FIG. 44, the vertical axis is the electron beam diffraction intensity (arbitrary unit) which shows the distribution of spots, etc., and the horizontal axis is indicates the distance from the main spot.

[0305] In the single crystal structure or polycrystalline structure shown in FIG. 44(C), the plane in which the crystal part is oriented The spots are found at a specific distance from the main spot depending on the spacing (d value).

[0306] On the other hand, as shown in FIG. 42, the electron microbeam diffraction pattern of the nanocrystalline oxide semiconductor film The circumferential area formed by the multiple spots has a relatively large width. FIG. 44(A) shows a discrete distribution. Also, in the electron microbeam diffraction pattern, It can be seen that there are areas of high brightness between the circular areas, although they are not clearly defined spots. .

[0307] In addition, as shown in FIG. 44(B), the selected area electron diffraction pattern of the nanocrystalline oxide semiconductor film was The electron diffraction intensity distribution in the image shows a continuous intensity distribution. Since the electron beam diffraction intensity distribution shown in (A) can be approximated by the results of observing the intensity over a wide area, It can be considered that the spots overlap and connect to obtain a continuous intensity distribution.

[0308] As shown in FIG. 44A to FIG. 44C, the nanocrystalline oxide semiconductor film has an irregular plane orientation. A film having a plurality of regular crystal parts of different sizes, and the crystal parts are , so fine that no spots are observed in the selected area electron diffraction pattern. This suggests that...

[0309] In FIG. 42, where multiple spots were observed, the nanocrystalline oxide semiconductor film was 50 nm or less. In addition, the electron beam diameter is converged to 1 nmφ, so the measurement range is 5 nm Therefore, the crystal part included in the nanocrystalline oxide semiconductor film is 50n m or less, for example, is estimated to be 10 nm or less, or 5 nm or less.

[0310] Here, FIG. 45 shows a micro-electron diffraction pattern on a quartz glass substrate. The measurement conditions were the same as those for the electron beam diffraction patterns shown in Figures 42(B) to 42(D).

[0311] As shown in FIG. 45, the quartz glass substrate having an amorphous structure does not have a specific spot. First, a halo pattern with a continuously changing brightness is observed from the main spot. In addition, in a film having an amorphous structure, even if electron beam diffraction is performed on a very small area, Unlike the case of a crystalline oxide semiconductor film, a plurality of spots distributed in a circumferential shape are not observed. Therefore, the multiple spots distributed in a circular shape observed in Figures 42(B) to 42(D) It is confirmed that this phenomenon is unique to nanocrystalline oxide semiconductor films.

[0312] Also, in FIG. 46, the beam diameter is converged to about 1 nmφ at point 2 shown in FIG. 42(A). The electron beam diffraction pattern was measured after irradiating the sample with an electron beam for 1 minute.

[0313] The electron beam diffraction pattern shown in FIG. 46 is similar to the electron beam diffraction pattern shown in FIG. Multiple spots distributed in a circular pattern were observed, and no significant differences were found between the two measurement results. This is because the crystals confirmed in the electron diffraction pattern in Figure 42(C) are oxide semiconductors. This means that the conductor film is present from the time of its formation, and is formed by irradiating it with a focused electron beam. This means that no crystal parts are formed.

[0314] Next, FIG. 47 shows a partially enlarged view of the cross-sectional TEM image shown in FIG. 42(A). The image shows the vicinity of point 1 in FIG. 42(A) (the surface of the nanocrystalline oxide semiconductor film) at a magnification of 8 million times. FIG. 47(B) shows a cross-sectional TEM image of the vicinity of point 2 in FIG. 42(A). Cross-sectional TEM image of the center of the nanocrystalline oxide semiconductor film in the thickness direction at 8 million times magnification. It is a statue.

[0315] The cross-sectional TEM image shown in Figure 47 clearly shows the crystal structure in the nanocrystalline oxide semiconductor film. cannot be confirmed.

[0316] In addition, the nanocrystals of the present embodiment were formed on the quartz glass substrate used in the observations of FIGS. The sample on which the oxide semiconductor film was formed was analyzed by X-ray diffraction (XRD). Figure 48 shows the XRD spectrum obtained using the out-of-plane method. The results of measuring the

[0317] In FIG. 48, the vertical axis represents the X-ray diffraction intensity (arbitrary unit), and the horizontal axis represents the diffraction angle 2θ (deg The XRD spectrum was measured using a Bruker AXS X-ray diffractometer. D-8 ADVANCE was used.

[0318] As shown in FIG. 48, a peak due to quartz is observed in the vicinity of 2θ=20 to 23°. However, no peaks due to the crystal parts contained in the nanocrystalline oxide semiconductor film can be confirmed.

[0319] From the results of FIG. 47 and FIG. 48, it can be seen that the crystal parts contained in the nanocrystalline oxide semiconductor film are extremely fine. This suggests that it is a crystalline part.

[0320] As described above, in the nanocrystalline oxide semiconductor film of this embodiment, X-rays having a wide measurement range can be used. Diffraction (XRD: X-ray diffraction) analysis shows peaks indicating orientation The electron diffraction patterns obtained by the selected area electron diffraction with a wide measurement range were not detected. A halo pattern is observed in the turn. Macroscopically, a biological membrane can be considered to be equivalent to a membrane with disordered atomic arrangement. By using ultrafine electron beam diffraction with a sufficiently small electron beam diameter (for example, 10 nmφ or less), By measuring the nanocrystalline oxide semiconductor film using the electron microbeam diffraction pattern, Therefore, the nanocrystalline oxide semiconductor film of this embodiment can be observed. is a very small crystal part with irregular crystal orientation (for example, grain size is 10 nm or less, or 5 nm or less, It can be assumed that the film is formed by the aggregation of extremely fine crystals (or crystals of 3 nm or less). The nanocrystalline region containing the portion is included in the entire region in the thickness direction of the nanocrystalline oxide semiconductor film. can be.

[0321] It is preferable that the film-forming surface 603 has an insulating surface. By this, the positive charge is dissipated from the sputtering particles 602 deposited on the film-forming surface 603. However, the deposition rate of the sputtering particles 602 is faster than the dissipation of the positive charge. In the case where the speed is slow, the film-forming surface 603 may be conductive. , an amorphous surface, or an amorphous insulating surface is preferred.

[0322] By using a sputtering target in the above manner, the thickness is uniform and In this way, an oxide film with uniform crystal orientation can be formed.

[0323] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used.

[0324] (Embodiment 5) In this embodiment, a sputtering target according to one embodiment of the present invention will be described. do.

[0325] The sputtering target preferably has a relative density of 90% or more, 95% or more, or is over 99%.

[0326] The sputtering target includes a polycrystalline oxide having a plurality of crystal grains. The average grain size is 3 μm or less, preferably 2.5 μm or less, and more preferably 2 μm or less. It is.

[0327] Alternatively, the sputtering target includes a polycrystalline oxide having a plurality of crystal grains, Among the multiple crystal grains, the ratio of crystal grains having a grain size of 0.4 μm or more and 1 μm or less is 8% or more, It is preferably 15% or more, and more preferably 25% or more.

[0328] The grain size of the crystal grains is measured, for example, by electron backscatter diffraction (EBSD) method. It can be measured by Scatter Diffraction (SCD). The grain size indicated by is the size of one grain measured from the grain map obtained by EBSD. The cross-sectional area of ​​the crystal grain is converted into the diameter when the crystal grain is assumed to be a perfect circle. When the cross-sectional area of ​​the grain is S and the radius of the grain is r, S = πr 2 Calculate the radius r from the relationship The particle diameter is defined as twice the radius r.

[0329] Moreover, the crystal grains contained in the sputtering target have a cleavage plane. The plane is, for example, a plane parallel to the ab plane.

[0330] The small grain size of the multiple crystal grains allows ions to collide with the sputtering target. When the sputtering is performed, the sputtered particles are peeled off from the cleavage plane. The crystal grains are small in size, and the upper and lower surfaces are parallel to the cleavage plane. This causes distortion in the crystal, making it more likely to peel off from the cleavage plane.

[0331] In addition, when the crystal grains contained in the sputtering target are hexagonal, The sputtered particles have upper and lower surfaces that are roughly regular hexagons with internal angles of 120°. It becomes a hexagonal column shape.

[0332] In addition, sputtering particles are ideally single crystals, but some of them are affected by ion collisions. It does not matter if the material is amorphous due to some reason.

[0333] The polycrystalline oxides contained in such sputtering targets include In, M (M are Ga, Sn, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu) and Zn. And oxides containing Zn are also referred to as In-M-Zn oxides.

[0334] In addition, the atomic ratio of In, M, and Zn in the In-M-Zn oxide is stoichiometric. The composition of In, M and Zn contained in the In-M-Zn oxide is preferably close to the above range. The atomic ratio of the In-M-Zn oxide is close to the stoichiometric composition. The crystallinity can be improved.

[0335] In the In-M-Zn oxide, the cleavage plane is parallel to the ab plane where M and Zn are mixed. This is often the case.

[0336] A method for producing the above-mentioned sputtering target will be described with reference to FIG.

[0337] In FIG. 25(A), an oxide powder containing a plurality of metal elements is used as a sputtering target. First, in step S101, the oxide powder is weighed.

[0338] Here, as the oxide powder containing multiple metal elements, an oxide powder containing In, M, and Zn is used. The following describes the preparation of the In-M-Zn oxide powder. InO X Oxide powder, MO Y Oxide powder and ZnO Z Using oxide powder Note that X, Y, and Z are any positive numbers. For example, X is 1.5, Y is 1.5, Z is Of course, the oxide powders mentioned above are just examples, and in order to obtain a desired composition, The oxide powder can be appropriately selected. M is Ga, Sn, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb or Lu In this embodiment, an example using three types of oxide powder is shown, but the present invention is not limited to this. For example, This embodiment may be applied to the case where four or more kinds of oxide powders are used, or one or This may also be applied when two types of oxide powder are used.

[0339] Next, InO X Oxide powder, MO Y Oxide powder and ZnO Z The oxide powder is mixed with a predetermined mo Mix in l ratio.

[0340] The predetermined molar ratio is, for example, InO X Oxide powder, MO Y Oxide powder and Z nO Z The oxide powders are 2:2:1, 8:4:3, 3:1:1, 1:1:1, 4:2:3, 1:1:2, 3:1:4, 1:3:2, 1:3:4, 1:3:6, 1:3:8, 1:3: 10, 1:3:12, 1:6:4, 1:6:6, 1:6:8, 1:6:10, 1:6:1 2, 1:6:14, 1:6:16, 1:6:20 or 3:1:2. By adjusting the ol ratio, a sputtering target containing a highly crystalline polycrystalline oxide can be obtained. It becomes easier to obtain

[0341] Next, in step S102, InO X Oxide powder, MO Y acid ZnO powder and ZnO Z The oxide powder is subjected to the first firing to obtain In-M-Zn oxide. get.

[0342] The first firing is carried out in an inert atmosphere, an oxidizing atmosphere, or a reduced pressure atmosphere at a temperature of 4 The temperature is from 00°C to 1700°C, preferably from 900°C to 1500°C. The time is, for example, from 3 minutes to 24 hours, preferably from 30 minutes to 17 hours, and more preferably Preferably, the first baking is performed for 30 minutes to 5 hours. This suppresses unnecessary reactions other than the desired reaction, and reduces the concentration of impurities in the In-M-Zn oxide powder. Therefore, by increasing the crystallinity of the In-M-Zn oxide powder, can be done.

[0343] The first baking may be performed multiple times by changing the temperature and / or atmosphere. For example, the In-M-Zn oxide powder is held at a first temperature in a first atmosphere, and then heated in a second atmosphere. Specifically, the first atmosphere may be an inert atmosphere or an inert gas atmosphere. It is preferable that the first atmosphere is a reduced pressure atmosphere and the second atmosphere is an oxidizing atmosphere. In-M-Zn oxide powder is used to reduce impurities in the powder in an atmospheric environment. This is because oxygen deficiency may occur in the material. It is preferable to reduce oxygen vacancies in the In-M-Zn oxide. By reducing the impurity concentration and oxygen vacancies, the In-M-Zn oxide powder The crystallinity can be increased.

[0344] Next, in step S103, the In-M-Zn oxide is crushed to obtain an In-M-Zn oxide. A powder product is obtained.

[0345] The In-M-Zn oxide contains many surface structures parallel to the ab plane. The In-M-Zn oxide powder is a plate-like grain with upper and lower surfaces parallel to the ab plane. In-M-Zn oxide crystals tend to be hexagonal. Therefore, the aforementioned plate-like crystal grains are hexagonal columns with roughly regular hexagonal faces with internal angles of 120°. It is often in this form.

[0346] Next, the particle size of the obtained In-M-Zn oxide powder is confirmed in step S104. The average particle size of the In-M-Zn oxide powder is 3 μm or less, preferably 2.5 μm or less, more preferably 2.5 μm or less. More preferably, it is confirmed that the thickness is 2 μm or less. Using a particle size filter, the particle size is 3 μm or less, preferably 2.5 μm or less, and more preferably It is also possible to select only the In-M-Zn oxide powder having a particle size of 2 μm or less. The oxide powder has a particle size of 3 μm or less, preferably 2.5 μm or less, and more preferably 2 μm or less. By selecting the particles to be less than 3 μm, the average particle size of the In-M-Zn oxide powder is ensured to be less than 3 μm. It is preferably 2.5 μm or less, and more preferably 2 μm or less.

[0347] In step S104, if the average particle size of the In-M-Zn oxide powder exceeds a predetermined value, Returning to step S103, the In-M-Zn oxide powder is pulverized again.

[0348] In this manner, the average particle size is 3 μm or less, preferably 2.5 μm or less, and more preferably In-M-Zn oxide powder having an average particle size of about 2 μm or less can be obtained. In-M- is 3 μm or less, preferably 2.5 μm or less, and more preferably 2 μm or less. By obtaining Zn oxide powder, the crystals contained in the sputtering target to be prepared later can be obtained. The particle size can be reduced.

[0349] Next, in FIG. 25(B), the In-MZ obtained by the flowchart shown in FIG. A sputtering target is prepared using n-oxide powder.

[0350] In step S111, the In-M-Zn oxide powder is spread in a mold and molded. The molding refers to spreading the In-M-Zn oxide in a uniform thickness on the mold. The powder is introduced and then molded by applying vibration from the outside. Zn oxide powder is introduced and formed to a uniform thickness using a roller or the like. In step S111, the In-M-Zn oxide powder is mixed with water, a dispersant, and a binder. The slurry may be molded by pouring it into a mold and then suctioning it from the bottom of the mold. Then, the molded body after suction is dried. It is preferable to dry the molded product naturally, as this makes it less likely to crack. Heat treatment at temperatures below 700℃ removes residual moisture that could not be removed by natural drying. Remove.

[0351] In-M-Zn oxide containing many plate-like crystal grains with upper and lower surfaces parallel to the ab plane By spreading the oxide powder in a mold and molding it, the crystal grains are aligned so that the planes parallel to the ab plane face upwards. Therefore, by spreading and molding the obtained In-M-Zn oxide powder, -b The ratio of the surface structure of the plane parallel to the plane can be increased. may be made of oxide and have a rectangular or round top surface shape.

[0352] Next, in step S112, the In-M-Zn oxide powder is subjected to a first pressure treatment. Then, in step S113, a second firing is performed to obtain plate-like In-M-Zn oxide. The firing may be performed under the same conditions and by the same method as the first firing. The crystallinity of the -M-Zn oxide can be improved.

[0353] The first pressure treatment is sufficient if it can compress and compact the In-M-Zn oxide powder. For example, a weight of the same type as the mold may be used. Alternatively, compressed air or the like may be used. Alternatively, the first pressure treatment may be performed using a known technique. The first pressure treatment may be carried out simultaneously with the second baking.

[0354] A planarization process may be performed after the first pressure treatment. The planarization process may be performed by chemical mechanical polishing (CMP). Chemical Mechanical Polishing (P) treatment is used. Good.

[0355] The plate-like In-M-Zn oxide thus obtained is a polycrystalline oxide with high crystallinity.

[0356] Next, in step S114, the thickness of the obtained plate-like In-M-Zn oxide is confirmed. If the thickness of the In-M-Zn oxide is thinner than the desired thickness, the process returns to step S111 and the plate-shaped In-M The In-M-Zn oxide powder is spread on the In-Zn oxide and molded. When the oxide has a desired thickness, the plate-shaped In-M-Zn oxide is sputtered. The following is a case where the plate-shaped In-M-Zn oxide is thinner than the desired thickness. The following describes the case.

[0357] Next, in step S112, a plate-shaped In-M-Zn oxide and a plate-shaped In-M-Zn oxide are The In-M-Zn oxide powder on the substrate is subjected to a second pressure treatment. Then, in step S113, Then, a third firing is performed to obtain a plate-like In-M-Zn oxide powder having a thickness increased by the amount of the In-M-Zn oxide powder. Zn oxide is obtained. The plate-like In-M-Zn oxide with increased thickness is called the plate-like In-M-Zn oxide. Since the material is grown by using a seed crystal as a seed crystal, the oxide becomes a highly crystalline polycrystalline oxide.

[0358] The third baking may be performed under the same conditions and by the same method as the second baking. The pressure treatment may be carried out under the same conditions and by the same method as the first pressure treatment. This may be carried out simultaneously with the firing of the second component.

[0359] Again, in step S114, the thickness of the obtained plate-shaped In-M-Zn oxide is confirmed.

[0360] Through the above process, the crystal orientation is improved and the plate-shaped In-M-Zn oxide is gradually thickened. It is possible.

[0361] By repeating this process of thickening the plate-shaped In-M-Zn oxide n times (n is a natural number), A desired thickness (t), for example, 2 mm or more and 20 mm or less, preferably 3 mm or more and 20 mm or less The plate-like In-M-Zn oxide can be obtained. , as a sputtering target.

[0362] After that, a planarization process may be performed.

[0363] The resulting sputtering target may be subjected to a fourth firing. The fourth firing may be performed under the same conditions and by the same method as the first firing. Furthermore, a sputtering target containing a highly crystalline polycrystalline oxide can be obtained. do.

[0364] In this manner, a polycrystalline oxide having a cleavage plane parallel to the ab plane and a plurality of crystal grains was obtained. To prepare a sputtering target containing a plurality of crystal grains having a small average grain size. can be done.

[0365] In addition, the sputtering target prepared in this manner can be made highly dense. The high density of the sputtering target allows the deposition density to be high. Specifically, the relative density of the sputtering target is 90% or more, 95% or more, or It can be made 99% or more.

[0366] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0367] (Embodiment 6) In this embodiment, a CAAC-OS film that can be used in one embodiment of the present invention will be described. The results of observing the electron beam diffraction pattern will now be described.

[0368] The CAAC-OS film used in this embodiment is an In-Ga-Zn oxide (In:Ga:Z n=1:1:1 [atomic ratio]) and a deposition gas containing oxygen. This is an In-Ga-Zn oxide film formed by sputtering. For the detailed description of a manufacturing method or the like, the above embodiment can be referred to.

[0369] Figure 33 shows a cross-sectional TEM (Transmission Electron Microscopy) image of the CAAC-OS film. The microscopy (transmission electron microscope) image of the point in FIG. 33 is shown in FIG. 34. The electron diffraction patterns measured at points 1 to 4 are shown. .

[0370] The cross-sectional TEM image shown in Fig. 33 was taken using a transmission electron microscope (Hitachi High-Technologies Corporation, H- The image was taken using a 3000NAR 1000-2000 Hz microscope at an accelerating voltage of 300 kV and a magnification of 2 million times. The electron beam diffraction pattern shown in FIG. 34 was obtained using a transmission electron microscope (Hitachi High-Technologies Corporation). The accelerating voltage was 200 kV and the beam diameter was about 1 nmφ. The electron diffraction pattern is for a beam diameter of about 50 nm. The electron diffraction method is sometimes called ultrafine electron diffraction. In this case, the measurement range by electron beam diffraction is 5 nmφ or more and 10 nmφ or less.

[0371] Point 1 (film surface side), point 2 (film center), and point 3 (film base side) shown in Figure 33 ) correspond to Figure 34(A), (B), and (C), respectively. The electron beam diameter is about 1 nmφ. The electron diffraction pattern for the sample 4 (whole film) is shown in FIG. 34(D). The electron beam diameter is approximately This is an electron beam diffraction pattern with a diameter of 50 nm.

[0372] The electron diffraction patterns of point 1 (film surface side) and point 2 (film center) are The formation of a pattern by bright spots can be seen, but at point 3 (on the film substrate side), The turn is broken. This is because the crystal state is different in the thickness direction of the CAAC-OS film. In addition, at point 4 (whole film), the spot (bright point) Since the formation of a pattern can be confirmed, the film as a whole is a CAAC-OS film, or , it can be said that the film includes a CAAC-OS film.

[0373] Figure 35 is an enlarged photograph of the vicinity of point 1 (film surface side) in Figure 33. Interlayer insulation A clear lattice image showing the orientation of the CAAC-OS film was confirmed up to the interface with the SiON film. It is possible.

[0374] 36(A) and (B) show the structure of the CAAC-OS film, which is different from the CAAC-OS film used in the cross-sectional TEM observation in FIG. The cross-sectional TEM photograph and X-ray diffraction spectrum of the CAAC-OS film are shown in Fig. 1. There are various forms, and a peak indicating a crystalline component is observed around 2θ=31° as shown in FIG. 36(B). A appears. Note that this peak may not appear clearly.

[0375] In the region shown by the concentric circles in FIG. 36(A) on the CAAC-OS film, the electron beam diameter is set to 1 The results of electron beam diffraction for the following diameters are shown in Fig. 37: (A), (B), (C), and (D). When the electron beam diameter is 1 nmφ, 4. Confirm the formation of a pattern with clear spots (bright points) as in (A) and (B). If the electron beam diameter is increased, the spot (bright point) becomes slightly unclear. From the diffraction pattern, it can be confirmed that the film as a whole is a CAAC-OS film, or It can be said that the film includes a CAAC-OS film.

[0376] 38(A) and (B) show the CAAC-OS film used in the cross-sectional TEM observation of FIG. 36(A). These are cross-sectional TEM photographs and X-ray diffraction spectra after annealing at 450°C.

[0377] In the region shown by the concentric circles in FIG. 38(A) on the CAAC-OS film, the electron beam diameter is set to 1 The results of electron beam diffraction for the following diameters are shown in Fig. 39: (A), (B), (C), and (D). As in the results shown in Fig. 37, the electron beam At a diameter of 1 nm, the formation of a pattern consisting of clear spots (bright points) is confirmed. Also, when the electron beam diameter is increased, the spot (bright point) becomes slightly unclear. However, the diffraction pattern can be confirmed, and the film as a whole is a CAAC-OS film. Or, it can be said that the film includes a CAAC-OS film.

[0378] 40(A) and (B) show the CAAC-OS film used in the cross-sectional TEM photograph of FIG. The CAAC-OS film used in the cross-sectional TEM observation of FIG. The cross-sectional TEM photograph and X-ray diffraction spectrum of the CAAC-OS film are shown in Fig. 1. The CAAC-OS film has various morphologies. As shown in FIG. 40(B), peak A indicating a crystalline component appears near 2θ=31°. In some cases, peak B due to the spinel crystal structure appears.

[0379] In the region shown by the concentric circles in FIG. 40(A) on the CAAC-OS film, the electron beam diameter is set to 1 The results of electron beam diffraction for the following diameters are shown in Fig. 41: (A), (B), (C), and (D). When the electron beam diameter is 1 nmφ, The formation of a pattern with bright spots can be seen. As the diameter of the lens is increased, the spots become slightly less clear, but the diffraction pattern can still be seen. In addition, with a beam diameter of 90 nm, a clearer spot (bright point) can be confirmed. Therefore, the film as a whole is a CAAC-OS film or a CAAC It can be said that the film contains an -OS film.

[0380] Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification. do.

[0381] (Embodiment 7) A display device including the transistor and the capacitor described in the above embodiment A semiconductor device (also called a display device) can be manufactured. A part or the whole of the operating circuit is formed on the same substrate as the pixel section to form a system on panel. In this embodiment, the transistors shown as examples in the above embodiments can be An example of the display device used will be described with reference to Figs. 12 to 14. 12(B) is a cross-sectional view showing the cross-sectional configuration of the portion indicated by the dashed line MN in FIG. 13, only a part of the structure of the pixel portion is shown.

[0382] In FIG. 12A, a pixel portion 902 provided on a first substrate 901 is surrounded by a A sealant 905 is provided and the substrate is sealed with a second substrate 906. ) is different from the region surrounded by the sealant 905 on the first substrate 901. A signal line formed of a single crystal semiconductor or a polycrystalline semiconductor on a separately prepared substrate is placed in the region where the A driver circuit 903 and a scanning line driver circuit 904 are mounted. 903, a scanning line driver circuit 904, or various signals and potentials applied to the pixel portion 902 are , FPC (Flexible Printed Circuit)918a, FPC91 Powered by 8b.

[0383] In FIG. 12B and FIG. 12C, a pixel portion 901 is provided on a first substrate 901. A sealant 905 is provided so as to surround the gate electrode 902 and the scanning line driver circuit 904 . In addition, a second substrate 906 is provided over the pixel portion 902 and the scanning line driver circuit 904 . Therefore, the pixel portion 902 and the scanning line driver circuit 904 are formed by the first substrate 901 and the sealing material 905. The display element is sealed by the second substrate 906. In FIG. 12(C), a region surrounded by a sealant 905 on a first substrate 901 A single crystal semiconductor or a polycrystalline semiconductor is formed on a separately prepared substrate in a region different from the above. A signal line driver circuit 903 is mounted. In FIG. 12(B) and FIG. 12(C), , the signal line driver circuit 903, the scanning line driver circuit 904, or various Signals and potentials are supplied from FPC918.

[0384] In addition, in FIG. 12B and FIG. 12C, a signal line driver circuit 903 is separately formed. Although an example in which the scanning lens is mounted on the first substrate 901 is shown, the present invention is not limited to this configuration. A signal line driver circuit may be formed separately and mounted, or a part of a signal line driver circuit or a scanning line driver circuit may be mounted. Alternatively, only a part of the path may be formed separately and implemented.

[0385] The method of connecting the separately formed drive circuit is not particularly limited, and may be any method such as COG ( hip on glass method, wire bonding method, or TAB (Tape The Automated Bonding method can be used. This is an example in which a signal line driver circuit 903 and a scanning line driver circuit 904 are mounted by the COG method. FIG. 12B shows an example in which a signal line driver circuit 903 is mounted by the COG method. C) is an example in which a signal line driver circuit 903 is mounted by the TAB method.

[0386] The display device includes a panel in which a display element is sealed, and a controller for the panel. This includes modules in which ICs, etc., including lasers, are mounted.

[0387] In this specification, the display device refers to an image display device or a display device. In addition, it can function as a light source (including a lighting device) instead of a display device. Connectors, such as FPC or TCP-mounted modules, and TCP-mounted modules A module with a printed wiring board or a display element is mounted with an IC (integrated circuit) by the COG method. The display device also includes all modules in which a display circuit (or other circuit) is directly mounted.

[0388] In addition, the pixel portion and the scanning line driver circuit provided on the first substrate include a plurality of transistors. The transistor described in the above embodiment can be applied to the semiconductor device.

[0389] Examples of display elements provided in the display device include liquid crystal elements (also called liquid crystal display elements), light-emitting elements, and the like. The light-emitting element can be turned on by a current or a voltage. This category includes elements whose brightness can be controlled, specifically inorganic EL (Electroluminescent) Luminescence elements, organic electroluminescence elements, etc. Also, electronic ink, A display medium in which the contrast is changed by electrical action can also be used. An example of a liquid crystal display device using a liquid crystal element as a display element will be described.

[0390] The liquid crystal display device shown in FIG. 13 is a vertical electric field type liquid crystal display device. The connecting terminal electrode 915 and the terminal electrode 916 are The electrode 916 is electrically connected to a terminal of the FPC 918 via an anisotropic conductive material 919. is.

[0391] The connection terminal electrode 915 is formed from the same conductive film as the first electrode 930a. 6 is the same as the source electrode and drain electrode of the transistor 910 and the transistor 911 It is formed of a conductive film.

[0392] A pixel portion 902 and a scanning line driver circuit 904 provided on a first substrate 901 are A transistor 910 included in a pixel portion 902 has a plurality of transistors. The transistors 910 and 911 included in the circuit 904 are illustrated. The insulating film 129, the insulating film 131, and the insulating film 132 shown in Embodiment 1 are formed over the transistor 911. An insulating film 924 corresponding to the film 133 is provided. It is a functional insulating film.

[0393] In this embodiment, the transistor 910 is the transistor described in any of Embodiments 1 to 3. The transistor provided in the pixel shown in FIG. 1, the transistor provided in the scanning line driver circuit shown in any of the above-mentioned Embodiments 1 to 3 is In addition, the oxide semiconductor film 927, the insulating film 924, and The first electrode 930a is used to form a capacitor 936. is connected to a capacitance line 929 via an electrode 928 and an electrode 930b. The same conductive film as the source and drain electrodes of the transistors 910 and 911 The electrode 930b is formed from the same conductive film as the first electrode 930a. The quantity line 929 is formed from the same conductive film as the gate electrodes of the transistors 910 and 911. Note that the capacitor shown in Embodiment 1 is used as the capacitor 926 here. However, the capacitor elements shown in the other embodiments can be used as appropriate.

[0394] The transistor 910 provided in the pixel portion 902 is electrically connected to a display element. The display element is not particularly limited as long as it can display an image. It can be used.

[0395] The liquid crystal element 913, which is a display element, includes a first electrode 930a, a second electrode 931, and a liquid crystal layer. The liquid crystal layer 908 is sandwiched between insulating films 9 32, an insulating film 933 is provided. The second electrode 931 is provided on the second substrate 906 side. The first electrode 930a and the second electrode 931 are overlapped with each other via the liquid crystal layer 908. It is as follows.

[0396] A first electrode and a second electrode (a pixel electrode, a common electrode, a counter electrode) for applying a voltage to a display element In the case of a photodiode, the direction of the light to be extracted, the location of the electrode, and the The light transmission or reflectivity can be selected depending on the pattern structure.

[0397] The first electrode 930a and the second electrode 931 are the same as the electrodes 121a and 121b shown in the first embodiment. The same material as the pixel electrode 121b can be used appropriately.

[0398] The spacer 935 is a columnar spacer obtained by selectively etching an insulating film. The distance (cell gap) between the first electrode 930a and the second electrode 931 is controlled by the It should be noted that a spherical spacer may also be used.

[0399] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. Liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials can exhibit cholesteric, smectic, cubic, and chromatic phases depending on the conditions. It shows an isotropic phase, an isotropic phase, etc.

[0400] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. When the temperature of the cholesteric liquid crystal is increased, the cholesteric phase transitions to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to improve the alignment, a liquid crystal composition containing a chiral agent is used for the liquid crystal layer. The organic resin is made of an organic resin, and the organic resin contains hydrogen or water. In this case, the electrical characteristics of the transistor of the semiconductor device may be deteriorated. By using a blue phase as a crystal layer, the semiconductor device according to one embodiment of the present invention can be manufactured without using an organic resin. Thus, a highly reliable semiconductor device can be obtained.

[0401] The first substrate 901 and the second substrate 906 are fixed together by a sealant 925 . The sealant 925 may be made of an organic resin such as a thermosetting resin or a photocurable resin. The sealant 925 is in contact with the insulating film 924. It corresponds to the sealing material 905 .

[0402] The sealant 925 is provided on the insulating film 924. The uppermost layer of the insulating film 924 is a nitride insulating film. This is an insulating film that can prevent impurities such as hydrogen and water from entering from the outside. Therefore, fluctuations in the electrical characteristics of the transistors 910 and 911 can be suppressed. Cut.

[0403] In addition, in liquid crystal display devices, black matrices (light-shielding films), polarizing members, and phase difference members Optical members (optical substrates) such as anti-reflection members are provided as appropriate. For example, a polarizing substrate and Circularly polarized light produced by a retardation substrate may be used. etc. may also be used.

[0404] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the drive circuit is It is preferable to provide a protection circuit using a non-linear element.

[0405] FIG. 14 shows the second electrode 906 provided on the substrate 906 in the liquid crystal display device shown in FIG. 31 is formed on the substrate 901. show.

[0406] The common connection portion is disposed at a position overlapping with the seal material for bonding the substrate 901 and the substrate 906. and is electrically connected to the second electrode 931 via conductive particles contained in the sealing material. Or, provide a common connection part in a place that does not overlap with the sealing material (excluding the pixel part) and A paste containing conductive particles is provided separately from the sealing material so as to overlap the connection portion, and a second electrode 9 is formed. 31 may be electrically connected.

[0407] FIG. 14(A) is a cross-sectional view of the common connection portion, which corresponds to IJ in the top view shown in FIG. 14(B). Correct.

[0408] The common potential line 975 is provided on the gate insulating film 922 and is connected to the transistor 9 shown in FIG. 10. The source electrode 971 or the drain electrode 973 is made of the same material and in the same process. do.

[0409] The common potential line 975 is covered with an insulating film 924. 5. The openings are for connecting the source and drain electrodes of the transistors 910. A contact that connects one of the drain electrode 971 or the drain electrode 973 to the first electrode 930a. It is made using the same process as a tohole.

[0410] In addition, the common potential line 975 and the common electrode 977 are connected at the opening. 7 is provided on the insulating film 934, and is connected to the connection terminal electrode 915 and the first electrode 930a of the pixel portion. It is made of the same materials and in the same process.

[0411] In this manner, the common connection portion is formed in the same manufacturing process as the switching element of the pixel portion 902. It can be manufactured.

[0412] The common electrode 977 is an electrode that comes into contact with the conductive particles contained in the sealing material, and is disposed on the substrate 906. An electrical connection is made with the second electrode 931 of the first electrode 931 .

[0413] 14C, a common potential line 985 is connected to the gate of a transistor 910. They may be made of the same material and in the same process as the electrodes.

[0414] In the common connection portion shown in FIG. 14C, a common potential line 985 is connected to the gate insulating film 922 and The gate insulating film 922 and the insulating film 924 are disposed below the common electrode 921 and the insulating film 924. The openings are located at positions overlapping with the position line 985. A contact that connects one of the electrode 971 or the drain electrode 973 to the first electrode 930a. After etching the insulating film 924 in the same process as the hole, the gate insulating film 922 is further selected. It is formed by selective etching.

[0415] In addition, the common potential line 985 and the common electrode 987 are connected at the opening. 7 is provided on the insulating film 924, and includes a connection terminal electrode 915 and a first electrode 930a of the pixel portion. It is made of the same materials and in the same process.

[0416] As described above, by using the transistor and the capacitor described in the above embodiment, It is possible to provide a semiconductor device having a capacitive element with an increased charge capacity while increasing the aperture ratio. As a result, a semiconductor device with excellent display quality can be obtained.

[0417] In addition, oxygen vacancies are reduced in an oxide semiconductor film, which is a semiconductor film included in a transistor. Since impurities such as hydrogen are reduced, the semiconductor device according to one embodiment of the present invention can be favorably This results in a semiconductor device having excellent electrical characteristics.

[0418] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used.

[0419] (Embodiment 8) In this embodiment, a human body to which the semiconductor device of one embodiment of the present invention can be applied is The interface will be explained. In particular, the sensor that can detect the proximity or contact of the object to be detected will be described. A configuration example of a touch sensor will be described below.

[0420] Touch sensors include capacitive, resistive, surface elastic, infrared, and optical. Various methods can be used, such as the method.

[0421] Representative examples of capacitive touch sensors include surface capacitive touch sensors and projected capacitive touch sensors. In addition, the projected capacitive type has a self-driving function, which is mainly due to the difference in the driving method. There are capacitance type, mutual capacitance type, etc. Here, when using the mutual capacitance type, multiple points can be detected simultaneously. This is preferable because it enables multiple points to be detected (also called multi-touch).

[0422] Here, we will explain the touch sensor in detail, but in addition to this, cameras (infrared cameras The system detects the movement (gesture) of the object to be detected (e.g., finger or hand) and the user's gaze. Sensors that can detect point movements are used as a human interface. It is also possible.

[0423] [Example of sensor detection method] 20(A) and (B) are schematic diagrams showing the configuration of a mutual capacitance type touch sensor and input / output The touch sensor has a capacitance having a pair of electrodes. An input voltage is input to one of the electrodes. A current (or current flowing through the other electrode) flows through the other electrode. The device is equipped with a detection circuit that detects the potential of the electrode.

[0424] For example, as shown in FIG. 20(A), when a square wave is used as the input voltage waveform, the output voltage A waveform having a sharp peak is detected as a flow waveform.

[0425] As shown in FIG. 20(B), when a conductive object to be detected approaches or comes into contact with the capacitance, In this case, the capacitance between the electrodes decreases, and the output current value decreases accordingly.

[0426] In this way, the change in capacitance can be calculated using the change in output current (or potential) relative to the input voltage. By detecting the object, the proximity or contact of the object to be detected can be detected.

[0427] [Touch sensor configuration example] FIG. 20C shows a configuration example of a touch sensor having a plurality of capacitors arranged in a matrix. Shows.

[0428] The touch sensor is made up of a number of wirings extending in the X direction (horizontal direction of the paper) and The wiring has a plurality of wirings that intersect and extend in the Y direction (the vertical direction of the paper). A capacitance is formed in the

[0429] In addition, the wiring extending in the X direction is used to carry the input voltage or common potential (including the ground potential and reference potential). In addition, a detection circuit (for example , source meter, sense amplifier, etc.) are electrically connected, and the current (or is the electric potential).

[0430] The touch sensor is designed so that the input voltage is input in sequence to multiple wirings extending in the X direction. By scanning in the Y direction and detecting changes in the current (or potential) flowing through the wiring extending in the Y direction, This enables two-dimensional sensing of the object to be detected.

[0431] [Touch panel configuration example] Below, a configuration example of a touch panel including a display unit having a plurality of pixels and a touch sensor will be described. An example in which the touch panel is incorporated into an electronic device will be described.

[0432] FIG. 21(A) is a schematic cross-sectional view of an electronic device equipped with a touch panel.

[0433] The electronic device 3530 includes a housing 3531 and at least a touch panel 3532 disposed in the housing 3531. 532, a battery 3533, and a control unit 3534. The touch panel 3532 is The display unit 3534 is electrically connected to the control unit 3534 via wiring 3535. The display of images on the touch sensor and the sensing operation of the touch sensor are controlled. 3 is electrically connected to the control unit 3534 via wiring 3536 and supplies power to the control unit 3534. can be supplied.

[0434] The touch panel 3532 is provided so that its display surface is exposed to the outside. The exposed surface of the sensor 3532 displays an image and detects objects that come into contact with or are in close proximity to the sensor. It is possible.

[0435] 21B to 21E show configuration examples of a touch panel.

[0436] The touch panel 3532 shown in FIG. 21B includes a first substrate 3541 and a second substrate 354. A display panel 3540 having a display unit 3542 and a touch sensor 3544 are provided between the display panel 3540 and the touch sensor 3544. It includes a third substrate 3545 and a protection substrate 3546 .

[0437] The display panel 3540 may be a liquid crystal element, an organic EL (Electro Luminescence) It can be used in a variety of display devices, such as display devices using a Cence element and electronic paper. The touch panel 3532 may be configured with a backlight or polarizer depending on the configuration of the display panel 3540. A light plate or the like may be provided separately.

[0438] Since the object to be detected comes into contact with or is close to one surface of the protective substrate 3546, at least that surface It is preferable that the mechanical strength of the surface is increased. For example, the surface is strengthened by ion exchange or air cooling. The glass is physically or chemically treated to apply compressive stress to its surface. It can be used for a protective substrate 3546. Or, it can be used for a plastic substrate with a coated surface. A flexible substrate such as a plastic film may be used. A film may also be provided.

[0439] The touch sensor 3544 is provided on at least one surface of the third substrate 3545. Alternatively, a pair of electrodes constituting the touch sensor 3544 is formed on both sides of the third substrate 3545. In order to make the touch panel thinner, a flexible film may be used as the third substrate 3545. The touch sensor 3544 may be formed on a pair of substrates (including a film). A clamped configuration may also be used.

[0440] In FIG. 21B, a third substrate 35 having a protection substrate 3546 and a touch sensor 3544 is shown. 45 are bonded with an adhesive layer 3547, they are not necessarily bonded. In addition, the third substrate 3545 and the display panel 3540 may not be bonded to each other by an adhesive layer 354. 7 may be used for bonding.

[0441] The touch panel 3532 shown in FIG. 21B is a display panel and a substrate having a touch sensor. The touch panel having such a configuration is called an external touch panel. This type of configuration allows the display panel and touch sensor to be By stacking these, the touch sensor function is realized on the display panel. This allows touch panels to be easily manufactured without any special manufacturing process. It can be manufactured.

[0442] The touch panel 3532 shown in FIG. 21C has a touch sensor 3544 on the second substrate 35. The touch panel having such a configuration is provided on the surface of the protection substrate 3546 of the touch panel 43. This can also be called an on-cell type touch panel. This reduces the number of sheets, making it possible to achieve a thinner and lighter touch panel.

[0443] In the touch panel 3532 shown in FIG. 21(D), a touch sensor 3544 is disposed on a protection substrate 354. With this configuration, the display panel and the touch panel are Since the sensors can be made separately, touch panels can be easily made. Furthermore, the number of substrates required can be reduced, making the touch panel thinner and lighter. This can be achieved.

[0444] The touch panel 3532 shown in FIG. 21(E) has a touch sensor 3544 connected to the display panel 35. The touch panel having such a configuration is provided on the inner side of the pair of substrates of 40. This can also be called a cell-type touch panel. With this type of configuration, the number of substrates required is reduced. Since the number of touch panels can be reduced, the touch panel can be made thinner and lighter. The panel is, for example, a first display panel using transistors, wiring, electrodes, and the like provided in the display portion 3542. A circuit that functions as a touch sensor is fabricated on the substrate 3541 or the second substrate 3543. In addition, when an optical touch sensor is used, a photoelectric conversion element The configuration may include the following.

[0445] [Example of in-cell touch panel configuration] The following describes the configuration of a touch panel in which a touch sensor is incorporated in a display unit having multiple pixels. Here, a liquid crystal element is used as a display element provided in a pixel. Here is an example.

[0446] FIG. 22(A) shows one of the pixel circuits provided in the display unit of the touch panel exemplified in this configuration example. FIG. 1 is an equivalent circuit diagram of a portion

[0447] One pixel has at least a transistor 3503 and a liquid crystal element 3504. A wiring 3501 is connected to the gate of the transistor 3503, and a wiring 3502 is connected to either the source or drain. 02 are electrically connected to each other.

[0448] The pixel circuit includes a plurality of wirings extending in the X direction (for example, wiring 3510_1, wiring 3510_2, _2) and a plurality of wirings (for example, wiring 3511) extending in the Y direction, which are mutually The electrodes are disposed so as to intersect with each other, and a capacitance is formed therebetween.

[0449] In addition, among the pixels provided in the pixel circuit, some adjacent pixels are The electrodes of the liquid crystal elements are electrically connected to each other to form one block. The lock is divided into island blocks (e.g., block 3515_1, block 3515_2) and , a linear block extending in the Y direction (e.g., block 3516) In addition, although FIG. 22(A) shows only a part of the pixel circuit, in reality, Two types of blocks are repeatedly arranged in the X and Y directions.

[0450] The wiring 3510_1 (or wiring 3510_2) extending in the X direction is an island-shaped block 3 515_1 (or block 3515_2). The wiring 3510_1 extending in the X direction is not necessarily connected along the X direction via a linear block. A plurality of island-shaped blocks 3515_1 arranged in succession are electrically connected. The wiring 3511 extending in the direction perpendicular to the substrate 3511 is electrically connected to a linear block 3516 .

[0451] FIG. 22B shows a plurality of wirings 3510 extending in the X direction and a plurality of wirings 3510 extending in the Y direction. FIG. 3 is an equivalent circuit diagram showing a connection configuration of the wiring 3511. An input voltage or a common potential can be input to the wiring 3 extending in the Y direction. A ground potential is input to each of the wirings 3511, or the wiring 3511 is electrically connected to the detection circuit. It is possible.

[0452] [Touch panel operation example] Hereinafter, the operation of the above-mentioned touch panel will be described with reference to FIG.

[0453] As shown in FIG. 23(A), one frame period is divided into a writing period and a detection period. The write period is a period during which image data is written to the pixels, and the wiring 3510 (gate line On the other hand, during the detection period, sensing is performed by the touch sensor. During this period, the wirings 3510 extending in the X direction are selected in sequence and an input voltage is input.

[0454] FIG. 23B is an equivalent circuit diagram during the writing period. A common potential is input to both the wiring 3510 extending in the Y direction and the wiring 3511 extending in the Y direction. can be.

[0455] FIG. 23(C) is an equivalent circuit diagram at a certain point in the detection period. Each of the wirings 3511 extending in the X direction is electrically connected to a detection circuit. Of the wiring 3510, the input voltage is input to the selected one, and the other A common potential is input.

[0456] In this way, the image writing period and the period for sensing by the touch sensor are separated. This prevents touch noise caused by pixel writing noise. The decrease in sensitivity of the sensor can be suppressed.

[0457] [Pixel configuration example] An example of the configuration of a pixel that can be used in the above-mentioned touch panel will be described below.

[0458] Figure 24(A) shows the FFS (Fringe Field Switching) mode. FIG. 2 is a schematic cross-sectional view showing a part of a pixel to which the present invention is applied.

[0459] The pixel includes a transistor 3521, an electrode 3522, an electrode 3523, and a liquid crystal 3524. , and a color filter 3525. The electrode 3523 having an opening is connected to the transistor 3 521. The electrode 3523 is electrically connected to either the source or drain of the The electrode 3523 and the electrode 3522 are provided on the liquid crystal layer. It functions as one of the electrodes of the element, and by applying a voltage between them, the alignment of the liquid crystal can be controlled. Can be controlled.

[0460] For example, the electrode 3522 is electrically connected to the wiring 3510 or the wiring 3511 described above. In this way, the above-mentioned pixels of the touch panel can be formed.

[0461] The electrode 3522 can be provided on the electrode 3523. In that case, the electrode 3522 The insulating layer may be provided over the electrode 3523 with an insulating layer interposed therebetween.

[0462] Figure 24(B) shows the case where the IPS (In-Plane-Switching) mode is applied. FIG. 2 is a schematic cross-sectional view showing a part of a pixel.

[0463] The electrodes 3523 and 3522 provided in the pixel each have a comb-like shape. The teeth are provided in a coplanar manner so as to interlock and are spaced apart from each other.

[0464] For example, the electrode 3522 is electrically connected to the wiring 3510 or the wiring 3511 described above. In this way, the above-mentioned pixels of the touch panel can be formed.

[0465] Figure 24(C) shows the VA (Vertical Alignment) mode applied. FIG. 2 is a schematic cross-sectional view showing a part of a pixel.

[0466] The electrode 3522 is provided so as to face the electrode 3523 with the liquid crystal 3524 interposed therebetween. In addition, a wiring 3526 is provided so as to overlap the electrode 3522. The wiring 3526 is, for example, In order to electrically connect blocks different from the block to which the pixel shown in FIG. 24(C) belongs, It can be provided in.

[0467] For example, the electrode 3522 is electrically connected to the wiring 3510 or the wiring 3511 described above. In this way, the above-mentioned pixels of the touch panel can be formed.

[0468] This embodiment may be implemented in appropriate combination with other embodiment modes described in this specification. This can be done.

[0469] (Embodiment 9) In this embodiment, a data processing device using a transistor described as an example of one embodiment of the present invention will be described. The configuration of the above will be described with reference to the drawings.

[0470] Specifically, the G signal for selecting pixels is preferably set to a frequency of 30 Hz (30 times per second) or more. Usually output at a frequency between 60Hz (60 times per second) and 960Hz (960 times per second) The first mode is 11.6μHz (once a day) or more and 0.1Hz (0.1 times per second). ) frequency, preferably 0.28mHz (once per hour) or more and 1Hz (once per second) An information processing device having a second mode in which the information is output with a frequency of less than 10 ...

[0471] When a still image is displayed using this information processing device, the refresh rate is set to less than 1 Hz, preferably Preferably, the frequency can be set to 0.2Hz or less, providing a display that is easy on the user's eyes and reduces eye fatigue. It is possible to display information that reduces the burden on the user's eyes and does not strain the user's eyes. The displayed image can be refreshed at an optimal frequency depending on the nature of the image to be displayed. Specifically, refresh is performed less frequently than when displaying video smoothly. This makes it possible to display still images with less flicker. In addition, it also reduces power consumption. It also has the effect of

[0472] FIG. 26 is a diagram for explaining nervous system eye fatigue.

[0473] FIG. 27 is a diagram for explaining eye fatigue caused by the muscular system.

[0474] <About eye fatigue> Here we will explain eye fatigue. There are two types of eye fatigue: nervous system fatigue and muscular system fatigue. There are similar ones.

[0475] Nervous system fatigue can be caused by staring at a flashing display or light emitted by the display for a long period of time. , which stimulates the retina, nerves, or brain, causing fatigue. The phenomenon in which the display flashes rapidly is called flicker, but this type of flickering is not caused by the nervous system. Causes fatigue.

[0476] Muscular fatigue is caused by overuse of the ciliary muscles, which are used for focusing. It is meant to make people do so.

[0477] FIG. 26(A) is a schematic diagram showing a display of a conventional display unit. In the display of the conventional display unit, The image is refreshed 60 times per second. Looking at such a screen for a long time may cause eye fatigue by stimulating the retina, nerves, or brain of the user. there were.

[0478] FIG. 26B is a schematic diagram showing a display of the information processing device described in this embodiment. The information processing device described in the embodiment changes the frequency of outputting a G signal that selects a pixel. In particular, a transistor with an extremely small off-state current can be used in the pixel portion of the display unit. This makes it possible to reduce the frame frequency while suppressing the occurrence of flicker. For example, ,The image can be rewritten once every 5 seconds, so it is possible to see the same image. This reduces the flickering of the screen that is visible to the user. This reduces the flickering of the screen that is visible to the user's retina and nerves. Or brain stimulation is reduced, reducing nervous system fatigue.

[0479] An example of a transistor with extremely low off-state current is a transistor using an oxide semiconductor. A transistor, in particular a transistor using a CAAC-OS film, is preferable.

[0480] Also, as shown in FIG. 27(A), when the size of one pixel is large (for example, when the resolution is 15 If the resolution is less than 100 ppi, the characters displayed on the display will be blurred. When you look at blurry text for a long time, the ciliary muscles constantly move to focus. Even though you are using your eyes, you will still have difficulty focusing, which will put strain on your eyes. There was a risk of it getting damaged.

[0481] In contrast, as shown in FIG. 27B, in a display device according to one embodiment of the present invention, A small pixel size and high resolution display with a resolution of 150ppi (preferably 200ppi or higher) This allows for a detailed and smooth display. However, it is easier to focus, which reduces muscle fatigue. can be expressed using pixel density (ppi: pixels per inch). Pixel density is the number of pixels per inch. A pixel is the unit that makes up an image. .

[0482] Methods for quantitatively measuring eye fatigue are currently being considered. The value index is the Critical Flicker Frequency (CFF). In addition, the evaluation index of muscle fatigue is known as Known examples of such factors include adjustment time and adjustment near point distance.

[0483] Other methods for assessing eye fatigue include electroencephalography, thermography, and blink count. Measurement of eye movement, tear volume evaluation, pupil contraction reaction rate evaluation, questionnaire to investigate subjective symptoms There are also other projects.

[0484] The information processing device 605 having a display function described in this embodiment includes a display device 640, It has a computing device 620 and an input means 500 (see FIG. 28).

[0485] <1. Configuration of the display device 640> The display device 640 includes a display unit 630 and a control unit 610 (see FIG. 28). The image signal 625_V and the primary control signal 625_C may be provided to a display device 640. The device 640 can display the image information on the display 630 .

[0486] The primary image signal 625_V includes, in addition to the gradation information (which can also be called luminance information) of the image, e.g., chromaticity information, Includes information, etc.

[0487] The primary control signal 625_C controls, for example, the timing of the scanning operation of the display device 640. This includes signals for

[0488] The power supply potential and the like are supplied to the control unit 610 and the display unit 630 of the display device 640 .

[0489] [1.1 Control unit 610] The control unit 610 has a function of controlling the display unit 630. For example, the secondary image signal 615 _V and / or secondary control signal 615_C, etc.

[0490] For example, the control unit 610 may be configured to include a polarity determination circuit. The polarity of the signal can be inverted every frame.

[0491] The polarity determination circuit notifies the timing for inverting the polarity of the secondary image signal 615_V, The control unit 610 has a function of inverting the polarity of the secondary image signal 615_V according to the timing. The polarity of the secondary image signal 615_V may be controlled in the control unit 610. Alternatively, the image may be inverted in the display unit 630 in accordance with a command from the control unit 610. This is also fine.

[0492] The polarity determination circuit has a counter and a signal generation circuit, and generates a secondary image signal using the synchronization signal. It may also have a function of determining the timing for inverting the polarity of 615_V.

[0493] The counter has the function of counting the number of frame periods using the pulses of the horizontal sync signal. The signal generating circuit also determines the timing for inverting the polarity of the secondary image signal 615_V. The counter has a function of notifying the control unit 610 of the frame number obtained by the counter. Using the information on the number of frame periods, the secondary image signal 615_V is The polarity can be reversed.

[0494] [1.1.1 Secondary image signal] The secondary image signal 615_V may include image information.

[0495] For example, the control unit 610 generates a secondary image signal 615_V from a primary image signal 625_V. Then, the secondary image signal 615_V may be output.

[0496] In addition, the control unit 610 sets the difference between the primary image signal 625_V and the reference potential Vsc as the amplitude, A signal whose polarity is inverted for each frame may be generated as the secondary image signal 615_V.

[0497] [1.1.2 Secondary control signals] The secondary control signal 615_C includes a first drive circuit (also called a G drive circuit 632) of the display unit 630. A signal for controlling the second driver circuit (also referred to as S driver circuit 633) A signal for detecting the presence of a signal may be included.

[0498] For example, the control unit 610 controls the primary control including synchronization signals such as a vertical synchronization signal and a horizontal synchronization signal. A secondary control signal 615_C may be generated from signal 625_C.

[0499] The secondary control signal 615_C includes, for example, a start pulse signal SP, a latch signal LP, a pulse The width control signal PWC and the clock signal CK are included.

[0500] Specifically, the secondary control signal 615_C includes an S drive circuit 633 that controls the operation of the S drive circuit 633. The start pulse signal SP for the S circuit, the clock signal CK for the S drive circuit, the latch signal LP, etc. In addition, a starter for the G drive circuit that controls the operation of the G drive circuit 632 can be included. The clock signal SP for the G drive circuit, the clock signal CK for the G drive circuit, the pulse width control signal PWC, etc. It can be included.

[0501] [1.2 Configuration of the display unit 630] The display unit 630 includes a pixel unit 631, a first driver circuit (also referred to as a G driver circuit 632), and The second driver circuit (also referred to as an S driver circuit 633) is provided.

[0502] The pixel section 631 has a display light that does not include light with a wavelength shorter than 420 nm and has a resolution of 150 ppi or more. A plurality of pixels 631p provided with a resolution of Each pixel 631p is connected to at least one of the scanning lines G and a signal line S The type and number of wirings are the same as those of the pixel 631p. Depends on configuration, number and placement.

[0503] For example, pixels 631p are arranged in a pixel section 631 in a matrix of x columns and y rows. In this case, the signal lines S1 to Sx and the scanning lines G1 to Gy are arranged in the pixel portion 631. (See FIG. 29(A-1)). A number of scanning lines (G1 to Gy) provide G signals for each row. A plurality of signal lines (S1 to Sx) can supply S signals to a plurality of pixels. This can be done.

[0504] The G driving circuit 632 controls the supply of the G signal 632_G to select the scanning line G (see FIG. 28).

[0505] For example, the pixel section 631 is divided into a plurality of regions (specifically, a first region 631a, a second region 631b, and the third region 631c) and driven (see FIG. 29(A-2)).

[0506] Each region includes a plurality of pixels 631p, a plurality of scan lines for selecting the pixels 631p for each row. A scan line G and a number of signal lines for supplying S signals 633_S to the selected pixels 631p. S can be provided.

[0507] In addition, a plurality of G drive circuits (specifically, a first G drive circuit 632a, a second G drive circuit 632 b and a 3G drive circuit 632c) may also be provided.

[0508] The G driving circuit controls the supply of the G signal 632_G to drive the scanning lines G (including Specifically, the first G driving circuit 632a drives the scanning lines G1 to Gj, and the second G driving circuit 632b drives the scanning The third G driver circuit 632c selects the scanning lines Gj+1 to G2j, and the third G driver circuit 632c selects the scanning lines G2j+1 to Gy. You can choose.

[0509] [1.2.1G drive circuit] The G driving circuit outputs a first driving signal (also called a G signal) 632_ that selects the pixel circuit 634. The G driving circuit 632 outputs a G signal 632 for selecting each scanning line to the pixel circuit 634. _G for each scanning line at a frequency of 30Hz (30 times per second) or more, preferably 60Hz (1 second A first mode outputs at a frequency of 60 times per second (Hz) or more but less than 960Hz (Hz), A frequency of 11.6μHz (once a day) or more but less than 0.1Hz (0.1 times per second) is preferred. The frequency is usually between 0.28mHz (once per hour) and 1Hz (once per second). It has a second mode.

[0510] The G drive circuit 632 can operate in a first mode and a second mode by switching between them. For example, the secondary control signal 615_C or the secondary control signal 615 _C, the first start pulse signal for the G drive circuit 632 is used. Specifically, the control unit 610 outputs The output frequency of the start pulse signal for the G drive circuit may be controlled.

[0511] The G signal 632_G is generated by the G driving circuit 632. The pixel 631p is selected row by row.

[0512] [1.2.2S drive circuit] The display unit 630 may include an S drive circuit 633. The S drive circuit outputs a second drive signal (also referred to as S signal 633_S) is generated from the secondary image signal 615_V, and the S signal 633 _S to signal lines S (specifically, S1 to Sx).

[0513] The S signal 633_S includes image gradation information, etc. It is supplied to the selected pixel 631p.

[0514] [1.2.3 Details of the configuration of pixel unit 631] The pixel section 631 has a plurality of pixels 631p.

[0515] The pixel 631p includes a display element 635 and a pixel circuit 634 including the display element 635. (See Figure 28).

[0516] The pixel circuit 634 holds the supplied S signal 633_S and outputs image information to the display element 635. A part of the image is displayed. It can be used in the element circuit 634.

[0517] [1.2.3.1 Pixel circuit] As an example of the pixel circuit 634, a liquid crystal element 635LC is applied to the display element 635. Shown in Figure 29(B-1).

[0518] The pixel circuit 634 has a gate electrode to which a G signal 632_G is input and a gate electrode to which an S signal is input. A transistor 634t having a first electrode and a second electrode of the transistor 634t. A liquid crystal element 63 having a first electrode electrically connected to the liquid crystal element 63 and a second electrode to which a common potential is supplied. 5LC and.

[0519] The pixel circuit 634 includes a transistor that controls the supply of the S signal 633_S to the display element 635. It has 634t.

[0520] The gate of the transistor 634t is connected to one of the scanning lines G1 to Gy. One of the source and drain of the transistor 634t is connected to a signal line S1. The other of the source and drain of the transistor 634t is connected to one of the lines Sx. is connected to the first electrode of the display element 635.

[0521] The pixel 631p controls the input of the S signal 633_S to the pixel 631p by using a transistor 634t. In addition, multiple transistors are used as a switching element to control the The above-mentioned multiple transistors may be connected in parallel to form a single switch. They can be used as switching elements, connected in series, or in a combination of series and parallel. A connected connection may also be used.

[0522] The pixel 631p maintains a voltage between the first electrode and the second electrode of the liquid crystal element 635LC as necessary. In addition to the capacitance element 634c for holding the resistance, a transistor, a diode, a resistance element, a capacitance element, The second electrode of the display element 635 may include other circuit elements such as an inductor. A predetermined common potential Vcom is applied to each of the first and second electrodes.

[0523] The capacitance of the capacitor 634c may be adjusted as appropriate. For example, in the second mode described later, In the case where the S signal 633_S is held for a relatively long period (specifically, 1 / 60 sec or more), In this case, a capacitor 634c is provided. The capacitance of the circuit 634 may be adjusted. For example, the first electrode and the second electrode of the liquid crystal element 635LC may be adjusted. The electrodes may be stacked to substantially form a capacitance element.

[0524] As another example of a pixel circuit, a configuration in which an EL element 635EL is applied to a display element 635 is shown in FIG. 29(B-2).

[0525] The pixel circuit 634EL has a gate electrode to which a G signal 632_G is input and a gate electrode to which an S signal is input. a first electrode electrically connected to the first electrode of the capacitor 634c; and a second electrode electrically connected to the first electrode of the capacitor 634c. The first transistor 634t_1 has a first transistor a gate electrode electrically connected to the second electrode of the capacitor 634c; A first electrode electrically connected to the first electrode of the EL element 635EL A second electrode of the capacitor 6 A power supply potential is applied to the second electrode of the second transistor 634c and the first electrode of the second transistor 634t_2. A common potential is supplied to the second electrode of the EL element 635EL. The potential difference between the potential and the common potential is greater than the light emission start voltage of the EL element 635EL.

[0526] [1.2.3.2 Transistors] In the pixel circuit 634, a transistor 634t supplies the potential of the signal line S to a display element 635 The first electrode is then supplied with a second potential.

[0527] Note that a transistor including an oxide semiconductor is suitable for a display device of one embodiment of the present invention. A transistor using an oxide semiconductor can be used. For this, the description of the above embodiment can be referred to.

[0528] In a transistor using an oxide semiconductor film, leakage current between the source and drain in an off state The off-state current (OFF current) is extremely low compared to conventional silicon transistors. A transistor with an extremely low off-state current can be used in the pixel portion of the display unit. As a result, the frame frequency can be reduced while suppressing the occurrence of flicker.

[0529] [1.2.3.3 Display element] The display element 635 is not limited to a liquid crystal element 635LC, but may be, for example, an electrostatic OLED element that generates electroluminescence Various display elements can be applied, such as liquid crystal displays (LCDs) using liquid crystal displays (LCDs) or electronic ink using electrophoresis.

[0530] For example, the transmittance of polarized light through the liquid crystal element 635LC is controlled by the potential of the S signal 633_S. This makes it possible to display gradations.

[0531] [1.2.4 Light supply unit] For example, when a transmissive liquid crystal element is applied to the display element 635, the light supply unit 650 is The light supply unit 650 has a light source. The control unit 610 can be provided in the light supply The driving of the light source included in the display unit 650 is controlled. and acts as a backlight.

[0532] The light source of the light supply unit 650 may be a cold cathode fluorescent lamp, a light emitting diode (LED), or an OL An ED element or the like can be used.

[0533] In particular, it is preferable to configure the light source so that the intensity of the blue light emitted by the light source is weaker than the intensity of the light of the other colors. The blue light contained in the light emitted by the source is not absorbed by the cornea or lens of the eye and reaches the retina. This means that there are long-term effects on the retina (e.g. age-related macular degeneration) and the blue light can be visible until midnight. Circadian rhythms in response to light exposure thm) can be reduced. Specifically, it is 400 nm or less, preferably 420 It does not include light with a wavelength of 440 nm or less (also known as UVA). A light source with low light intensity is preferred.

[0534] <2. Arithmetic device> The computing device 620 outputs a primary control signal including a primary image signal 625_V and a mode switching signal. Generates signal 625_C.

[0535] [Example 1 of primary control signals including mode switching signals] The mode switching signal may be generated, for example, by a command from the user of the information processing device 605. good.

[0536] The user of the information processing device 605 issues a command to switch the display using the input means 500. The image switching signal 500_C is supplied to the arithmetic unit 620, and the arithmetic unit 62 0 may be configured to output a primary control signal 625_C that includes a mode switching signal.

[0537] A primary control signal 625_C including a mode switching signal is input to the control unit 610 of the display device 640. and the control unit outputs a primary control signal 625_C including a mode switching signal.

[0538] For example, a primary control signal including a mode switching signal for switching from a second mode to a first mode. When the control signal 625_C is supplied to the G drive circuit 632, the G drive circuit 632 operates in the second mode. Then, the G driving circuit 632 outputs the G signal for one frame or more. The upper output is then switched to the second mode.

[0539] Specifically, when the input unit 500 detects a page turning operation, an image switching signal 500_C may be configured to be output to the arithmetic device 620.

[0540] The computing device 620 generates a primary image signal 625_V including a page turning action, A primary control signal 625_C including a mode switching signal is output together with a next image signal 625_V. do.

[0541] A control unit 610 to which the primary image signal 625_V and the primary control signal 625_C are supplied 615_C includes a secondary control signal including a mode switching signal, and a secondary control signal including a page turning operation. Provides an image signal 615_V.

[0542] The G drive circuit 632 to which the secondary control signal 615_C including the mode switching signal is supplied The mode is switched from the second mode to the first mode, and the G signal 632_G is output with high frequency.

[0543] The S driver circuit 633 to which the secondary image signal 615_V including the page turning operation is supplied An S signal 633 _S generated from the secondary image signal 615 _V is output to a pixel circuit 634 .

[0544] As a result, pixel 631p can capture a large number of frame images including page turning operations at high frequency. As a result, the secondary image signal 615_V including the page turning action can be rewritten as can be displayed smoothly.

[0545] [Example 2 of primary control signals including mode switching signals] The arithmetic unit 620 determines whether the primary image signal 625_V to be output to the display unit 630 is a moving image or a still image. and outputs a primary control signal 625_C including a mode switching signal according to the result of the determination. may be configured to output

[0546] Specifically, when the primary image signal 625_V is a moving image, the arithmetic unit 62 0 outputs a switching signal to select the first mode, and in the case of a still image, The computing device 620 may be configured to output a switching signal for selecting the second mode.

[0547] In addition, the method for determining whether a moving image is a still image is based on the The difference between the signal of a frame and the frames before and after it is greater than a predetermined difference. When the image quality is above this threshold, it is determined that the image is a moving image, and when the image quality is below this threshold, it is determined that the image is a still image.

[0548] When the control unit 610 switches the operation mode of the G drive circuit from one mode to another mode, When switching from the second mode to the first mode (for example), the G drive circuit It may be configured to switch to another mode after outputting 32_G once or more times. stomach.

[0549] <3. Input method> The input means 500 may be a touch panel, a touch pad, a mouse, a joystick, A trackball, a data glove, an imaging device, etc. can be used. can associate an electrical signal input from the input means 500 with the coordinates of the display unit. This allows the user to input commands to process the information displayed on the display unit. can be done.

[0550] The information input by the user through the input means 500 is, for example, an image displayed on the display unit. Drag to change the image display position, advance the displayed image and display the next image. commands to swipe to display images, scroll to advance through strips of images, Instructions for selecting pictures, pinch in to change the size of the picture, pinch out In addition to commands to output, commands to input handwritten characters can also be given.

[0551] Illuminance is the amount of light incident on a unit area of ​​an illuminated surface per unit time, taking into account the spectral sensitivity of the eye. is the amount of light received.

[0552] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used.

[0553] (Embodiment 10) The semiconductor device according to one embodiment of the present invention can be applied to various electronic devices (including game machines). The electronic equipment includes a television set (television or television receiver) (also called a monitor), computer monitors, digital cameras, digital video cameras , digital photo frames, mobile phones, portable game machines, personal digital assistants, audio playback devices , gaming machines (pachinko machines, slot machines, etc.), and game cabinets. An example of the device is shown in Figure 15.

[0554] FIG. 15A shows a table 9000 having a display section. A display unit 9003 is built into the housing 9001, and an image is displayed on the display unit 9003. It is possible to support the housing 9001 with four legs 9002. The housing 9001 also includes a power cord 9005 for supplying power.

[0555] The semiconductor device described in any of the above embodiments can be used for the display portion 9003. Therefore, the display quality of the display portion 9003 can be improved.

[0556] The display unit 9003 has a touch input function. By touching the display button 9004 displayed on the screen with a finger or the like, the screen can be operated or information can be input. It also allows communication with and control of other home appliances, It may also be used as a control device to control other home appliances by operating the screen. If a semiconductor device having a touch sensor function is used, the display portion 9003 can have a touch input function. It is possible.

[0557] In addition, the screen of the display unit 9003 can be fixed to the floor by a hinge provided in the housing 9001. It can also be placed vertically and used as a television set. A large-screen television set will take up a lot of free space, but it can be placed on a table. If the display unit is built into the device, the space in the room can be used more effectively.

[0558] FIG. 15B shows a television device 9100. A display unit 9103 is incorporated in a housing 9101, and an image is displayed on the display unit 9103. In this example, the housing 9101 is supported by a stand 9105. The figure shows a configuration in which

[0559] The television device 9100 can be operated using an operation switch provided on the housing 9101 or a separate remote control. This can be done by using a remote control operation device 9110. The channel and volume can be controlled by the 9109, and the display 9103 shows The remote control device 9110 can control the video. A display unit 9107 for displaying information output from the device 9110 may be provided.

[0560] A television device 9100 shown in FIG. 15(B) includes a receiver, a modem, and the like. The television device 9100 can receive general television broadcasts using a receiver. Furthermore, by connecting to a wired or wireless communication network via a modem, Either directional (from sender to receiver) or bidirectional (between sender and receiver, or between receivers, etc.) ) information communication is also possible.

[0561] The semiconductor device described in any of the above embodiments is used for the display portion 9103 and the display portion 9107. Therefore, the display quality of the television device can be improved. do.

[0562] FIG. 15C shows a computer 9200, which includes a main body 9201, a housing 9202, a display unit 9 203, keyboard 9204, external connection port 9205, pointing device 920 6, etc.

[0563] The semiconductor device described in any of the above embodiments can be used for the display portion 9203. Therefore, the display quality of the computer 9200 can be improved.

[0564] The display unit 9203 has a touch input function. 03 Touch the display buttons with your finger to operate the screen or input information. It can also communicate with other home appliances or control them, making the screen The control device may be a control device that controls other home appliances by the operation. If a semiconductor device having an image sensor function as shown in FIG. 5 is used, the display portion 9203 can be touched. It can have an input function.

[0565] FIG. 16(A) and FIG. 16(B) show a tablet-type terminal that can be folded in two. A) is an open state of the tablet terminal. The tablet terminal includes a housing 9630, a display unit 9631a, and a display unit 9631b. display unit 9631b, a display mode changeover switch 9034, a power switch 9035, a power saving It has a mode changeover switch 9036, a fastener 9033, and an operation switch 9038.

[0566] The semiconductor device described in any of the above embodiments includes a display portion 9631a and a display portion 9631b. Therefore, it is possible to improve the display quality of tablet devices. Cut.

[0567] A part of the display unit 9631a can be used as a touch panel area 9632a. By touching the operation keys 9638 displayed on the display unit 96, data can be input. In 31a, as an example, half of the area has a display function only, and the other half The display unit 96 has a touch panel function, but is not limited to this. The entire area of ​​the display unit 931a may have a touch panel function. The entire surface of 631a is made to display keyboard buttons to serve as a touch panel, and the display section 9631b is made to display It can be used as a display screen.

[0568] In addition, in the display unit 9631b, as in the display unit 9631a, The part of the touch panel can be the area 9632b of the touch panel. Touch the area where the mode display switch button 9639 is displayed with your finger or a stylus. A keyboard button can be displayed on the display portion 9631b.

[0569] In addition, the touch panel area 9632a and the touch panel area 9632b are simultaneously You can also use touch input.

[0570] A display mode changeover switch 9034 is used to change the display orientation, such as portrait or landscape. You can switch between black and white and color display. The switch 9036 is a switch that turns on and off when the tablet terminal is in use and is detected by a light sensor built into the tablet terminal. The brightness of the display can be optimized according to the amount of light. In addition to sensors, other detection devices such as gyros, acceleration sensors, etc. that detect tilt may be incorporated.

[0571] FIG. 16A shows an example in which the display area of ​​the display portion 9631b is the same as that of the display portion 9631a. However, there is no particular limitation, and one size may be different from the other size. The quality of the display may also be different. For example, one display panel may provide a higher resolution display than the other. It may also be used as a rule.

[0572] FIG. 16B shows the tablet terminal in a closed state. The tablet terminal includes a housing 9630 and a solar cell 9 16B, the charge / discharge control circuit 96 As an example of the 34, a configuration having a battery 9635 and a DC-DC converter 9636 is described below. This is shown.

[0573] In addition, since the tablet device can be folded in half, the case 9630 can be folded when not in use. Therefore, the display portions 9631a and 9631b can be protected. This makes it possible to provide a tablet device that is highly durable and reliable even when used for a long period of time.

[0574] In addition, the tablet terminals shown in Fig. 16(A) and Fig. 16(B) are used in various Functions that display important information (still images, videos, text images, etc.), calendars, dates or times A function to display time and other information on the display, and to operate or edit the information displayed on the display by touch input. Touch input function, function to control processing by various software (programs), etc. It is possible to have.

[0575] The solar cell 9633 attached to the surface of the tablet device supplies power to the touch panel. The solar cell 9633 can supply the light to a display unit, a video signal processor, or the like. The battery 9635 can be efficiently charged by providing a light-emitting diode (LED) on one or both sides of the housing 9630. This is preferable because it can be configured to perform the operation in a simple manner. The use of lithium ion batteries has the advantage of enabling miniaturization.

[0576] The configuration and operation of the charge / discharge control circuit 9634 shown in FIG. A block diagram is shown in (C) and explained. Figure 16(C) shows a solar cell 9633, a battery 9635, DC-DC converter 9636, converter 9637, switches SW1 to SW 3. The display unit 9631, the battery 9635, the DCDC converter 96 36, the converter 9637, and the switches SW1 to SW3 are shown in FIG. This corresponds to the charge / discharge control circuit 9634 .

[0577] First, an example of operation when power is generated by the solar cell 9633 due to external light will be described. The power generated by the solar cell is converted to a voltage to charge the Battery 9635. The CDC converter 9636 steps up or steps down the voltage. When power is supplied from the solar cell 9633, switch SW1 is turned on and the converter The voltage is increased or decreased by a voltage converter 9637 to a voltage required for the display unit 9631. When no display is to be made on the display unit 9631, the switch SW1 is turned off and the switch SW2 is turned on. It is sufficient to configure it so that the power is turned on and the battery 9635 is charged.

[0578] The solar cell 9633 is shown as an example of a power generating means, but is not limited thereto. , and other power generation methods such as piezoelectric elements and thermoelectric conversion elements (Peltier elements) For example, the battery 9635 may be charged. It is possible to combine a non-contact power transmission module that transmits and receives power to charge, or other charging methods. The configuration may be as follows.

[0579] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used.

[0580] [Example] In this embodiment, one of a pair of electrodes constituting a capacitor is formed using a light-transmitting semiconductor film. The image was displayed using electrodes containing impurities. The displayed image is shown in Figure 49.

[0581] As shown in FIG. 49, a capacitor element having an electrode in which an impurity is contained in a light-transmitting semiconductor film is used. It was confirmed that the image can be displayed even if the

[0582] [Reference example] To confirm that the oxide semiconductor absorbs blue light, the relationship between wavelength and transmittance was Shows.

[0583] Sample 1 is a silicon nitride film of 400 nm and a silicon oxynitride film on the silicon nitride film. 50 nm, In-Ga-Zn oxide film on silicon oxynitride film 35 nm, and In-G 100 nm silicon nitride film on a-Zn oxide film and silicon oxide film on silicon nitride film and 100 nm of an indium tin oxide compound.

[0584] Sample 2 is a 400 nm silicon nitride film and an In-Ga-Zn system on the silicon nitride film. The oxide film is 35 nm, and the silicon oxide film on the In-Ga-Zn oxide film is 450 nm. Silicon nitride film 100 nm on silicon oxide film, silicon oxide on silicon nitride film, and 100 nm of indium tin oxide compound.

[0585] Sample 3 is a silicon nitride film of 400 nm and a silicon oxynitride film on the silicon nitride film. 50 nm, In-Ga-Zn oxide film on silicon oxynitride film 35 nm, and In-G A silicon oxide film on an a-Zn oxide film is 450 nm thick, and a silicon nitride film on a silicon oxide film is 450 nm thick. The compound of silicon oxide and indium tin oxide on the silicon nitride film was 00 nm.

[0586] Here, the relationship between wavelength and transmittance is shown in Figure 30. The solid line in the figure indicates sample 1, and the dotted line indicates sample The dashed line indicates sample 2, and the dashed line indicates sample 3. As shown in Fig. 30, the wavelengths were 4 In the region from 00 nm to 460 nm, the transmittance is reduced compared to other visible light regions. It was confirmed that the sample had a reduced transmittance at 400 nm to 46 This suggests that the material absorbs light in the 0 nm region. [Explanation of symbols]

[0587] 100 pixels 101 pixels 102 Substrate 103 Transistor 104 Scanning line driving circuit 105 Capacitive element 106 Signal line driver circuit 107 Scan Lines 108 Liquid crystal element 109 Signal Line 111 Semiconductor film 113 Conductive Film 115 Capacitive Line 117 Aperture 119 Semiconductor Film 120 Conductive film 121a electrode 121b Pixel electrode 123a aperture 123b aperture 125 Conductive Film 126 Insulating Film 127 Gate insulating film 128 Insulating film 129 Insulating Film 130 Insulating film 131 Insulating film 132 Insulating film 133 Insulating Film 154 Counter Electrode 199a First oxide film 199b Oxide semiconductor film 199c Second oxide film 201 pixels 205 Capacitive element 220 Conductive Film 221a electrode 221b Pixel electrode 223a aperture 223b aperture 225 Insulating Film 226 Insulating Film 227 Gate insulating film 228 Insulating Film 229 Insulating Film 230 Insulating film 231 Insulating Film 232 Insulating film 233 Insulating Film 245 Capacitive element 500 Input Method 500_C signal 600 Sputtering Target 601 ION 602 Sputtering particles 603 Coating surface 605 Information Processing Equipment 610 Control section 615_C Secondary control signal 615_V Secondary image signal 620 Arithmetic equipment 623 Transistor 625_C Primary control signal 625_V Primary image signal 627 Gate electrode 628 Semiconductor Film 629 Source Electrode 630 Display section 631 Pixel section 631a area 631b area 631c area 631p pixels 632 G drive circuit 632_G G signal 632a G drive circuit 632b G driver circuit 632c G drive circuit 633 S drive circuit 633_S S signal 634 Pixel circuit 634c Capacitive element 634EL pixel circuit 634t Transistor 634t_1 Transistor 634t_2 Transistor 635 Display element 635EL EL element 635LC Liquid crystal element 639 Drain Electrode 640 Display device 641 Conductive Film 901 Board 902 Pixel section 903 Signal line driver circuit 904 Scanning line driver circuit 905 Sealing material 906 Substrate 908 Liquid crystal layer 910 Transistor 911 Transistor 913 Liquid crystal element 915 Connection terminal electrode 916 Terminal electrode 918 FPC 918a FPC 918b FPC 919 Anisotropic conductive agent 922 Gate insulating film 923 Insulating film 924 Insulating film 925 Sealing material 926 Capacitor 927 Oxide Semiconductor Film 928 Electrode 929 Capacitance Line 930a First electrode 930b electrode 931 Second electrode 932 Insulating film 933 Insulating film 934 Insulating film 935 Spacer 936 Capacitor 971 Source Electrode 973 Drain electrode 975 Common potential line 977 Common electrode 985 Common potential line 987 Common electrode 3501 Wiring 3502 Wiring 3503 Transistor 3504 Liquid crystal elements 3510 Wiring 3510_1 Wiring 3510_2 Wiring 3511 Wiring 3515_1 Block 3515_2 Block 3516 Block 3521 Transistor 3522 Electrode 3523 Electrode 3524 Liquid crystal 3525 Color Filter 3526 Wiring 3530 Electronic equipment 3531 Case 3532 Touch Panel 3533 Battery 3534 Control Unit 3535 Wiring 3536 Wiring 3540 Display Panel 3541 Circuit Board 3542 Display section 3543 Circuit Board 3544 Touch Sensor 3545 Circuit Board 3546 Protection Board 3547 Adhesive layer 9000 Table 9001 Case 9002 Legs 9003 Display section 9004 Display button 9005 Power Cord 9033 Fastener 9034 Switch 9035 Power Switch 9036 Switch 9038 Operation switch 9100 Television equipment 9101 Case 9103 Display section 9105 Stand 9107 Display section 9109 Operation key 9110 Remote control device 9200 Computer 9201 Main unit 9202 Case 9203 Display section 9204 Keyboard 9205 External connection port 9206 Pointing Device 9630 Case 9631 Display section 9631a Display section 9631b Display section 9632a area 9632b area 9633 Solar Cells 9634 Charge / discharge control circuit 9635 Battery 9636 DC-DC Converter 9637 Converter 9638 Operation key 9639 Button

Claims

1. A transistor; a capacitance element electrically connected to the transistor; a display device including a pixel having a display element electrically connected to the transistor, A first conductive film; a first insulating film on the first conductive film; a first oxide semiconductor film and a second oxide semiconductor film on the first insulating film; a second conductive film having a region in contact with an upper surface of the first oxide semiconductor film; a third conductive film having a region in contact with an upper surface of the first oxide semiconductor film; a fourth conductive film having a region in contact with an upper surface of the third conductive film; a fifth conductive film having a region in contact with an upper surface of the second oxide semiconductor film, the first oxide semiconductor film and the second oxide semiconductor film each have a region in contact with an upper surface of the first insulating film; the first oxide semiconductor film has a region overlapping with the first conductive film, the second conductive film has a region overlapping with the fourth conductive film; the fifth conductive film has a first region in contact with an upper surface of the second oxide semiconductor film, the first region has a region overlapping with the fourth conductive film, the first oxide semiconductor film includes a channel formation region of the transistor, the second conductive film functions as one of a source electrode and a drain electrode of the transistor, the third conductive film functions as the other of the source electrode and the drain electrode of the transistor, the fourth conductive film has a region that functions as a pixel electrode of the display element, the fourth conductive film has a region that functions as one electrode of the capacitor element, the second oxide semiconductor film has a region that functions as the other electrode of the capacitor, an area of ​​the second oxide semiconductor film is larger than an area of ​​the first oxide semiconductor film; the first oxide semiconductor film contains In, Ga, and Zn; The second oxide semiconductor film contains In, Ga, and Zn.

2. In claim 1, A display device, wherein the second oxide semiconductor film has a region having a higher electrical conductivity than a channel formation region of the first oxide semiconductor film.

3. In claim 1 or 2, The display element is a display device having an organic electroluminescence (EL).

4. In any one of claims 1 to 3, A second insulating film is provided, the second insulating film has a region located above the second conductive film, a region located above the third conductive film, and a region located above the fifth conductive film; The second insulating film has a region located below the fourth conductive film.

Images