Lead frame and manufacturing method thereof

Abstract

To provide a lead frame and a manufacturing method thereof that enhance the adhesive strength between a die pad portion, a lead portion and a sealing portion.SOLUTION: A lead frame (100) includes a plurality of lead portions (110), and at least a portion of the top surface of the lead portions (110) and the side wall surfaces of the lead portions (110) are roughened surfaces, and the rough surfaces have an a* value in the CIELab color space in the range of 12 to 19 and a b* value in the range of 12 to 17.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a leadframe and a method for manufacturing the same. [Background technology]

[0002] In recent years, there has been a demand for smaller and thinner semiconductor devices mounted on a substrate. In order to meet such demands, various types of so-called QFN (Quad Flat Non-leaded package) type semiconductor devices have been proposed. A QFN type semiconductor device is configured such that a semiconductor element mounted on the mounting surface of a lead frame is sealed with sealing resin, and a part of the lead is exposed on the back side.

[0003] Conventionally, flip-chip type semiconductor devices have been known (see Patent Document 1). In a flip-chip type semiconductor device, when a semiconductor element is mounted on a mounting substrate, the semiconductor element and the mounting substrate are connected to each other by bumps. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2002-110849 A [Patent Document 2] JP 2019-40994 A

[0005] Generally, in a flip-chip type semiconductor device, the path through which moisture contained in the outside air can penetrate, which is the distance from the periphery of the semiconductor device to the electrodes of the semiconductor element, tends to be short. Therefore, there is a risk that moisture in the air will penetrate from the periphery of the semiconductor device to the electrodes of the semiconductor element.

[0006] Conventionally, when manufacturing a semiconductor package for vehicle mounting or one that requires high reliability, a semiconductor element is mounted on a die pad using a die attach film. In recent years, in such semiconductor packages, a cheaper die attach paste has also been used when mounting a semiconductor element on a die pad.

[0007] However, in the past, when a die attach paste was applied to a die pad, a semiconductor element was mounted, and then the paste was heated and cured, a phenomenon occurred in which the epoxy resin component in the die attach paste seeped out due to capillary action (bleed-out) (see Patent Document 2).

[0008] The present embodiment provides a lead frame capable of manufacturing a semiconductor device capable of suppressing the intrusion of moisture in the air to the electrodes of a semiconductor element, and a manufacturing method thereof.

[0009] The present embodiment provides a lead frame and a manufacturing method thereof that can satisfactorily connect a bump and a lead frame and prevent moisture from penetrating from the periphery of a semiconductor device toward an electrode of a semiconductor element.

[0010] The present embodiment provides a lead frame and a manufacturing method thereof that enable a lead frame having a rough surface to be manufactured at low cost.

[0011] The present embodiment provides a lead frame and a manufacturing method thereof that can prevent moisture from penetrating from the periphery of a semiconductor device toward electrodes of a semiconductor element.

[0012] The present embodiment provides a lead frame and a manufacturing method thereof that can suppress bleed-out and also suppress the intrusion of moisture from the periphery of a semiconductor device toward the electrodes of a semiconductor element. DISCLOSURE OF THEINVENTION

[0013] The embodiments of the present disclosure relate to the following [1] to

[51] .

[0014] [1] A plurality of lead portions are provided, and at least a part of the upper surface of each lead portion and a side wall surface of each lead portion are roughened surfaces, and the rough surface has a color space of a * The value is in the range of 12 to 19, and b * Lead frame, with values ​​ranging from 12 to 17.

[0015] [2] A lead frame comprising a plurality of lead portions, at least a portion of an upper surface of each of the lead portions and a side wall surface of each of the lead portions being roughened surfaces, and the arithmetic mean curvature Spc of the peaks of each of the rough surfaces being 700 mm-1 or more.

[0016] [3] The lead frame according to [2], wherein the rough surface has an arithmetic mean height Sa of 0.12 μm or more.

[0017] [4] A lead frame described in any one of [1] to [3], in which a portion of an upper surface of the lead portion and a side wall surface of the lead portion are rough surfaces, and a metal plating layer is provided on the non-rough surface of the upper surface of the lead portion.

[0018] [5] The lead frame according to [4], wherein the metal plating layer includes at least one of an Ag plating layer, a Ni plating layer, a Pd plating layer, and an Au plating layer.

[0019] [6] The lead frame described in any one of [1] to [5], wherein the lead portion includes an inner lead portion that is thinned from the lower surface side of the lead portion, and the lower surface of the inner lead portion is the rough surface.

[0020] [7] The lead frame described in any one of [1] to [5], further comprising a die pad portion for mounting a semiconductor element, the plurality of lead portions being arranged around the die pad portion, and an upper surface of the die pad portion and a side wall surface of the die pad portion being the rough surface.

[0021] [8] The lead frame is used for manufacturing a semiconductor device having a sealing portion that seals at least the multiple lead portions, and the top surface and side wall surface of the lead portion that contact the sealing portion are roughened surfaces. The lead frame described in any one of [1] to [7].

[0022] [9] A method for manufacturing a metal substrate, comprising: a metal substrate preparing step of preparing a metal substrate having a first surface and a second surface opposite to the first surface; a metal substrate processing step of forming a plurality of lead portions by processing the metal substrate; and a rough surface forming step of roughening at least a part of the upper surface of the lead portions and a side wall surface of the lead portions to form a rough surface, wherein in the rough surface forming step, * Values ​​range from 12 to 19, b * A method for manufacturing a lead frame, comprising roughening the surface roughness so that the surface roughness value is in the range of 12 to 17.

[0023]

[10] A method for manufacturing a semiconductor device comprising the steps of: preparing a metal substrate having a first surface and a second surface opposite to the first surface; processing the metal substrate to form a plurality of lead portions; and roughening at least a portion of the upper surface of the lead portions and a side wall surface of the lead portions to form a rough surface, wherein in the rough surface forming step, the arithmetic mean curvature Spc of the peaks of the rough surface is 700 mm or less. -1 The method for manufacturing a lead frame includes roughening the lead frame to the above-mentioned degree.

[0024]

[11] The method for manufacturing a lead frame according to

[10] , wherein in the rough surface forming step, the rough surface is roughened so that the arithmetic mean height Sa of the rough surface is 0.12 μm or more.

[0025]

[12] The method for producing a lead frame according to any one of [9] to

[11] , further comprising the step of: subjecting the lead portion to an alkali treatment after the rough surface forming step.

[0026]

[13] A method for manufacturing a lead frame described in any one of [9] to

[12] , wherein a metal plating layer is provided on a portion of the upper surface of the lead portion, and in the rough surface forming process, the upper surface and the side wall surface of the lead portion on which the metal plating layer is not provided are roughened.

[0027]

[14] The method for manufacturing a lead frame according to

[13] , wherein the metal plating layer includes at least one of an Ag plating layer, a Ni plating layer, a Pd plating layer, and an Au plating layer.

[0028]

[15] A method for manufacturing a lead frame described in any one of [9] to

[14] , wherein in the metal substrate processing step, the lead portion is formed including an inner lead portion that is thinned from the underside of the lead portion, and in the rough surface forming step, the rough surface is formed on the underside of the inner lead portion.

[0029]

[16] A method for manufacturing a lead frame described in any one of [9] to

[15] , comprising: in the metal substrate processing step, forming a die pad portion for mounting a semiconductor element so that the plurality of lead portions are arranged around the die pad portion; and in the rough surface forming step, roughening an upper surface and a side wall surface of the die pad portion, as well as at least a portion of an upper surface of the lead portions and a side wall surface of the lead portions to form the rough surface.

[0030]

[17] A lead frame comprising: a die pad on which a semiconductor element is mounted; and lead portions located around the die pad, wherein a smooth surface area is formed on a surface of the die pad or a surface of the lead portions; and a rough surface area is present surrounding the entire periphery of the smooth surface area.

[0031]

[18] The lead frame described in

[17] , wherein the rough surface area is formed along the entire periphery of the die pad or the entire periphery of the lead portion in a planar view.

[0032]

[19] The lead frame described in

[17] or

[18] , wherein the lead portion has an inner lead thinned from the back surface side, an inner lead surface is formed on the front surface side of the inner lead, an inner lead back surface is formed on the back surface side of the inner lead, an inner lead tip surface is formed on the surface of the inner lead facing the die pad, an external terminal is formed on the non-thinned portion of the back surface of the lead portion, the inner lead back surface and the inner lead tip surface are rough surfaces, and the external terminal is a smooth surface.

[0033]

[20] The lead frame according to any one of

[17] to

[19] , wherein a back surface of the die pad is a smooth surface and a side surface of the die pad is a rough surface.

[0034]

[21] The lead frame according to any one of

[17] to

[20] , wherein the smooth surface region is circular, elliptical or oval in plan view.

[0035]

[22] The lead frame according to any one of

[17] to

[20] , wherein the smooth surface area is square or rectangular in plan view.

[0036]

[23] The lead frame according to any one of

[17] to

[20] , wherein the smooth surface region is a closed figure including curves and line segments in a plan view.

[0037]

[24] The lead frame according to any one of

[17] to

[23] , wherein the shortest distance between the smooth surface region and the periphery of the die pad or the lead portion is 0.025 mm or more and 1.0 mm or less.

[0038]

[25] The lead frame according to any one of

[17] to

[24] , wherein the rough surface has an S-ratio of 1.30 or more, and the smooth surface has an S-ratio of less than 1.30.

[0039]

[26] A method for manufacturing a lead frame, comprising the steps of: preparing a metal substrate; etching the metal substrate to form a die pad and a lead portion located around the die pad; forming a plating layer on a portion of the metal substrate; forming a rough surface on a portion of the metal substrate that is not covered by the plating layer; and removing the plating layer, wherein a smooth surface area is formed on a surface of the die pad or a surface of the lead portion, and the rough surface area exists so as to surround the entire periphery of the smooth surface area.

[0040]

[27] A method for manufacturing a lead frame, comprising the steps of: preparing a metal substrate having a die pad and a lead portion located around the die pad; forming a plating layer on the outer periphery of the metal substrate except for at least a portion of the front surface; leaving the plating layer present on at least the rear surface of the metal substrate and removing the other plating layers; forming a rough surface on the portion of the metal substrate that is not covered by the plating layer; and removing the plating layer.

[0041]

[28] The method for manufacturing a lead frame according to

[27] , wherein in the step of forming the plating layer, the plating layer is not formed over the entire surface of the metal substrate.

[0042]

[29] A method for manufacturing a lead frame as described in

[27] , wherein in the step of forming the plating layer, the plating layer is formed on a portion of the surface of the lead portion, and in the step of removing the other plating layer, the plating layer present on a portion of the surface of the lead portion is left.

[0043]

[30] A method for manufacturing a lead frame according to

[29] , further comprising the step of forming a metal layer on a portion of the surface of the metal substrate after the step of removing the plating layer.

[0044]

[31] The method for producing a lead frame according to any one of

[27] to

[30] , wherein the rough surface has an S-ratio of 1.30 or more.

[0045]

[32] A lead frame comprising: a die pad on which a semiconductor element is mounted; and a lead portion located around the die pad, the lead portion having an inner lead thinned from a back surface side, an inner lead surface formed on a front surface side of the inner lead, an inner lead back surface formed on a back surface side of the inner lead, an inner lead tip surface formed on a surface of the inner lead facing the die pad, and an external terminal formed on a portion of the back surface of the lead portion that is not thinned, at least a portion of the inner lead surface, the inner lead back surface, and the inner lead tip surface have rough surfaces, and the external terminal has a smooth surface.

[0046]

[33] The lead frame according to

[32] , wherein the entire surface of the inner lead is rough.

[0047]

[34] The lead frame according to

[32] , wherein a metal layer is formed on a surface of the inner lead, and the portion of the surface of the inner lead on which the metal layer is formed is a smooth surface.

[0048]

[35] A lead frame comprising: a die pad on which a semiconductor element is mounted; and a lead portion located around the die pad, the lead portion being partially thinned from its back surface, the thinned portion of the back surface of the lead portion being a rough surface, and the non-thinned portion being a smooth surface.

[0049]

[36] A lead frame as described in

[35] , wherein a metal layer is located on a surface of the lead portion, and a first surface portion of the surface of the lead portion adjacent to the outside of the metal layer is a smooth surface, and a second surface portion of the surface of the lead portion adjacent to the outside of the first surface portion is a rough surface.

[0050]

[37] A lead frame as described in

[35] , wherein a metal layer is located on the surface of the lead portion, a recess is formed on the outside of the metal layer on the surface of the lead portion, a third surface portion adjacent to the outside of the recess is a rough surface, and an inner surface of the recess is a smooth surface.

[0051]

[38] A lead frame as described in

[35] , wherein a metal layer is located on a surface of the lead portion, a recess is formed on the outside of the metal layer on the surface of the lead portion, a third surface portion adjacent to the outside of the recess is roughened, and an inner surface of the recess is roughened.

[0052]

[39] The lead frame according to any one of

[35] to

[38] , wherein the front and back surfaces of the die pad are each smooth, and the side surface of the die pad is rough.

[0053]

[40] The lead frame described in any one of

[35] to

[39] , wherein the lead portion has an inner lead that is thinned from the back surface side, and an inner lead tip surface is formed on the surface of the inner lead that faces the die pad, and the inner lead tip surface is a rough surface.

[0054]

[41] The lead frame according to any one of

[35] to

[40] , wherein the rough surface has an S-ratio of 1.30 or more, and the smooth surface has an S-ratio of less than 1.30.

[0055]

[42] A method for manufacturing a lead frame, comprising the steps of: preparing a metal substrate; etching the metal substrate to form a die pad and a lead portion located around the die pad and partially thinned from the back surface side; forming a plating layer around the metal substrate; removing a portion of the plating layer present in an area where a rough surface is to be formed; forming a rough surface on a portion of the metal substrate that is not covered by the plating layer; and removing the plating layer, wherein the thinned portion of the back surface of the lead portion becomes a rough surface and the non-thinned portion becomes a smooth surface.

[0056]

[43] A lead frame comprising: a die pad on which a semiconductor element is mounted; and a lead portion located around the die pad, wherein a first rough surface is formed on at least a portion of a surface of the die pad; and a second rough surface is formed on at least a portion of a surface of the lead portion, and the roughness of the second rough surface of the lead portion is coarser than the roughness of the first rough surface of the die pad.

[0057]

[44] The lead frame described in

[43] , wherein a third rough surface is formed on a side surface of the die pad, and the roughness of the third rough surface of the die pad is coarser than the roughness of the first rough surface of the die pad.

[0058]

[45] The lead frame described in

[43] or

[44] , wherein the lead portion has an inner lead thinned from the back surface side, an inner lead back surface is formed on the back surface side of the inner lead, a fourth rough surface is formed on the back surface of the inner lead, and roughness of the fourth rough surface of the lead portion is coarser than roughness of the first rough surface of the die pad.

[0059]

[46] The lead frame described in any one of

[43] to

[45] , wherein the lead portion has an inner lead thinned from the back surface side, an inner lead tip surface is formed on the surface of the inner lead facing the die pad, and a fifth rough surface is formed on the inner lead tip surface, and the roughness of the fifth rough surface of the lead portion is coarser than the roughness of the first rough surface of the die pad.

[0060]

[47] The lead frame according to any one of

[43] to

[46] , wherein a smooth surface area is formed on the surface of the lead portion.

[0061]

[48] ​​The lead frame according to

[47] , wherein a metal layer is formed on the smooth surface area.

[0062]

[49] The lead frame described in

[47] , wherein the smooth surface area is exposed to the outside.

[0063]

[50] The lead frame described in any one of

[43] to

[49] , wherein the S-ratio of the first rough surface is 1.10 or more and less than 1.30, and the S-ratio of the second rough surface is 1.30 or more and 2.30 or less.

[0064]

[51] A method for manufacturing a lead frame, comprising the steps of: preparing a metal substrate; etching the metal substrate to form a die pad and lead portions located around the die pad; forming a coating layer on the die pad and the lead portions; removing the coating layer present on at least a portion of a surface of the die pad; forming a first rough surface on portions of the die pad that are not covered by the coating layer; removing the coating layer present on at least a portion of a surface of the lead portions; and forming a second rough surface on portions of the lead portions that are not covered by the coating layer, wherein the roughness of the second rough surface of the lead portions is coarser than the roughness of the first rough surface of the die pad.

[0065] According to this embodiment, it is possible to manufacture a semiconductor device capable of preventing moisture in the air from penetrating to the electrodes of the semiconductor element.

[0066] According to this embodiment, the bumps and the lead frame can be well connected, and moisture can be prevented from penetrating from the periphery of the semiconductor device toward the electrodes of the semiconductor element.

[0067] According to this embodiment, a lead frame having a rough surface can be manufactured at low cost.

[0068] According to this embodiment, it is possible to prevent moisture from penetrating from the periphery of the semiconductor device toward the electrodes of the semiconductor element.

[0069] According to this embodiment, it is possible to suppress bleed-out and also to suppress the intrusion of moisture from the periphery of the semiconductor device toward the electrodes of the semiconductor element. [Brief description of the drawings]

[0070] [Figure 1] FIG. 1 is a plan view showing a lead frame according to the first embodiment. [Diagram 2] FIG. 2 is a partial cutaway end view of the lead frame according to the first embodiment. [Diagram 3] FIG. 3 is a plan view showing the semiconductor device according to the first embodiment. [Figure 4] FIG. 4 is a partial cutaway end view of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 5 is a partial cutaway end view of a semiconductor device according to a modified example of the first embodiment. [Figure 6A] FIG. 6A is a process diagram for explaining the method for manufacturing the lead frame according to the first embodiment. [Figure 6B] FIG. 6B is a process diagram continuing from FIG. 6A, for explaining the method for manufacturing the lead frame according to the first embodiment. [Figure 6C] FIG. 6C is a process diagram continuing from FIG. 6B for explaining the method for manufacturing the lead frame according to the first embodiment. [Figure 6D] FIG. 6D is a process diagram continuing from FIG. 6C for explaining the method for manufacturing the lead frame according to the first embodiment. [Figure 6E] FIG. 6E is a process diagram continuing from FIG. 6D, for explaining the method for manufacturing the lead frame according to the first embodiment. [Figure 6F] FIG. 6F is a process diagram continuing from FIG. 6E for explaining the method for manufacturing the lead frame according to the first embodiment. [Figure 6G] FIG. 6G is a process diagram continuing from FIG. 6F, for explaining the method for manufacturing the lead frame according to the first embodiment. [Figure 6H] FIG. 6H is a process diagram continuing from FIG. 6G, for explaining the method for manufacturing the lead frame according to the first embodiment. [Figure 7A] FIG. 7A is a process diagram for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7B]FIG. 7B is a process diagram continuing from FIG. 7A, for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7C] FIG. 7C is a process diagram continuing from FIG. 7B, for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7D] FIG. 7D is a process diagram continuing from FIG. 7C, for explaining the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a plan view showing a lead frame according to the second embodiment. [Figure 9] FIG. 9 is a cross-sectional view showing a lead frame according to the second embodiment (a cross-sectional view taken along line IX-IX in FIG. 8). [Figure 10] 10(a) and 10(b) are enlarged plan views showing the surface of the die pad and the surface of the lead portion, respectively. [Figure 11] FIG. 11 is a plan view showing the semiconductor device according to the second embodiment. [Figure 12] FIG. 12 is a cross-sectional view (cross-sectional view taken along line XII-XII in FIG. 11) showing the semiconductor device according to the second embodiment. [Figure 13] 13(a) and 13(b) are enlarged cross-sectional views each showing a bump as a connecting portion. [Figure 14] 14(a)-(i) are cross-sectional views showing a method for manufacturing a lead frame according to the second embodiment. [Figure 15] 15(a) to 15(d) are cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment. [Figure 16] FIG. 16 is a partial enlarged cross-sectional view showing the semiconductor device according to the second embodiment. [Figure 17] 17(a)-(d) are enlarged plan views showing the surface of a die pad and the surface of a lead portion according to a modification of the second embodiment, respectively. [Figure 18] FIG. 18 is a plan view showing a lead frame according to the third embodiment. [Figure 19] FIG. 19 is a cross-sectional view showing a lead frame according to the third embodiment (a cross-sectional view taken along line XIX-XIX in FIG. 18). [Figure 20] FIG. 20 is a plan view showing a semiconductor device according to the third embodiment. [Figure 21] FIG. 21 is a cross-sectional view showing a semiconductor device according to the third embodiment (a cross-sectional view taken along line XXI-XXI in FIG. 20). [Figure 22] FIG. 22 is an enlarged cross-sectional view showing a bump as a connecting portion. [Figure 23] 23(a)-(i) are cross-sectional views showing a method for manufacturing a lead frame according to the third embodiment. [Figure 24] 24(a) to (d) are cross-sectional views showing a method for manufacturing the semiconductor device according to the third embodiment. [Diagram 25] FIG. 25 is a partial enlarged cross-sectional view showing the semiconductor device according to the third embodiment. [Figure 26] FIG. 26 is a cross-sectional view showing a lead frame according to the fourth embodiment. [Figure 27] FIG. 27 is a cross-sectional view showing a semiconductor device according to the fourth embodiment. [Figure 28] 28(a)-(j) are cross-sectional views showing a method for manufacturing a lead frame according to the fourth embodiment. [Figure 29] FIG. 29 is a partial enlarged cross-sectional view showing the semiconductor device according to the fourth embodiment. [Diagram 30] FIG. 30 is a plan view showing a lead frame according to a fifth embodiment. [Diagram 31] FIG. 31 is a cross-sectional view showing a lead frame according to a fifth embodiment (a cross-sectional view taken along line XXXI-XXXI in FIG. 30). [Diagram 32] FIG. 32 is a plan view showing a semiconductor device according to a fifth embodiment. [Diagram 33] FIG. 33 is a cross-sectional view showing a semiconductor device according to a fifth embodiment (a cross-sectional view taken along line XXXIII-XXXIII in FIG. 32). [Diagram 34] FIG. 34 is an enlarged cross-sectional view showing a bump as a connection portion. [Diagram 35] 35(a)-(j) are cross-sectional views showing a manufacturing method of a lead frame according to the fifth embodiment. [Diagram 36] 36(a) to 36(d) are cross-sectional views showing a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 37] FIG. 37 is a partially enlarged cross-sectional view showing a semiconductor device according to a fifth embodiment. [Figure 38] FIG. 38 is a cross-sectional view showing a lead frame according to a sixth embodiment. [Figure 39] FIG. 39 is a cross-sectional view showing a semiconductor device according to a sixth embodiment. [Diagram 40] 40(a)-(j) are cross-sectional views showing a method for manufacturing a lead frame according to the sixth embodiment. [Diagram 41] FIG. 41 is a partially enlarged cross-sectional view showing a semiconductor device according to a sixth embodiment. [Diagram 42] FIG. 42 is a cross-sectional view showing a lead frame according to a seventh embodiment. [Diagram 43] FIG. 43 is a cross-sectional view showing a semiconductor device according to a seventh embodiment. [Diagram 44] 44(a)-(j) are cross-sectional views showing a manufacturing method of a lead frame according to the seventh embodiment. [Diagram 45] FIG. 45 is a partially enlarged cross-sectional view showing a semiconductor device according to a seventh embodiment. [Figure 46] FIG. 46 is a cross-sectional view showing a lead frame according to an eighth embodiment. [Figure 47] FIG. 47 is a cross-sectional view showing a semiconductor device according to an eighth embodiment. [Figure 48] 48(a)-(j) are cross-sectional views showing a manufacturing method of a lead frame according to the eighth embodiment. [Figure 49] FIG. 49 is a partially enlarged cross-sectional view showing a semiconductor device according to an eighth embodiment. [Figure 50] FIG. 50 is a plan view showing a lead frame according to a ninth embodiment. [Figure 51] FIG. 51 is a cross-sectional view showing a lead frame according to a ninth embodiment (a cross-sectional view taken along line LI-LI in FIG. 50). [Figure 52] FIG. 52 is a plan view showing a semiconductor device according to a ninth embodiment. [Figure 53] FIG. 53 is a cross-sectional view showing a semiconductor device according to a ninth embodiment (a cross-sectional view taken along line LIII-LIII in FIG. 52). [Figure 54] 54(a)-(e) are cross-sectional views showing a manufacturing method of a lead frame according to a ninth embodiment. [Figure 55] 55(a)-(h) are cross-sectional views showing a manufacturing method of a lead frame according to a ninth embodiment. [Figure 56] 56(a) to (e) are cross-sectional views showing a method for manufacturing a semiconductor device according to a ninth embodiment. [Figure 57] FIG. 57 is a partially enlarged cross-sectional view showing a semiconductor device according to a ninth embodiment. [Figure 58] FIG. 58 is a cross-sectional view showing a lead frame according to a modified example of the ninth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0071] (First embodiment) Hereinafter, the first embodiment will be described with reference to Figs. 1 to 7D. Hereinafter, the embodiment of the present disclosure will be described with reference to the drawings. The drawings are schematic or conceptual, and the dimensions of each member, the size ratio between members, etc. are not necessarily the same as the actual ones. Even when the same members are shown, the dimensions and ratios between the members may be different depending on the drawing. In addition, in the drawings attached to this specification, the shape, scale, aspect ratio, etc. of each part may be changed or exaggerated from the actual ones in order to make it easier to understand.

[0072] In this specification, a numerical range expressed using "to" means that the range includes the numerical values ​​written before and after "to" as the lower and upper limits, respectively. Furthermore, in this specification, terms such as "film," "sheet," and "plate" are not distinguished from one another based on differences in names. For example, "plate" is a concept that includes members that can be generally called "sheet" and "film."

[0073] [Lead frame] An embodiment of the lead frame of the present disclosure will be described. The lead frame 100 according to this embodiment is used to fabricate a semiconductor device 200 (see Figs. 3 and 4). The lead frame 100 includes a plurality of package areas 100A. The package areas 100A are arranged in multiple rows and multiple stages (in a matrix). Note that Fig. 1 shows only a portion of the lead frame 100, centered on one package area 100A.

[0074] The package area 100A corresponds to a semiconductor device 200 described later, and is an area surrounded by a rectangular imaginary line (dashed line shown in FIG. 1) (see FIG. 1). In the present embodiment, the lead frame 100 includes a plurality of package areas 100A, but the lead frame 100 is not limited to this embodiment, and may include only one package area 100A.

[0075] In this specification, the terms "inside" and "inner side" refer to the side toward the center of each package area 100A, and the terms "outside" and "outer side" refer to the side away from the center of each package area 100A (the connecting bar 130 side). Additionally, the term "top surface" refers to the surface on which the semiconductor element 210 is mounted, the term "bottom surface" refers to the surface opposite the "top surface" that is connected to an external mounting board (not shown), and the term "side wall surface" refers to the surface located between the "top surface" and the "bottom surface" that constitutes the thickness of the lead frame 100 (metal substrate 310).

[0076] In this specification and the like, half-etching refers to etching the material to be etched halfway in the thickness direction. The thickness of the material to be etched after half-etching is 30% to 70%, preferably 40% to 60%, of the thickness of the material to be etched before half-etching.

[0077] As shown in FIG. 1 and FIG. 2, each package area 100A of the lead frame 100 includes a plurality of lead portions 110, a die pad portion 120, and a connecting bar 130 that connects the lead portions 110. The lead portion 110 may include an inner lead portion 111 and a terminal portion 113. The inner lead portion 111 is a portion that is thinned from the lower surface side, and is located on the inner side (the die pad portion 120 side) in each package area 100A. The terminal portion 113 is located on the outer side (the connecting bar 130 side) in each package area 100A. The inner lead portion 111 extends from the terminal portion 113 to the die pad portion 120 side. An internal terminal is formed on the upper surface side of the inner lead portion 111. This internal terminal is an area that is electrically connected to the semiconductor element 210 via a connection member 220 as described later. A metal plating layer 112 is provided on the internal terminal to improve adhesion with the connection member 220.

[0078] Each lead portion 110 is connected to the semiconductor element 210 via a connecting member 220 as described below, and is disposed with a space between it and the die pad portion 120 (see FIGS. 4 and 5). The multiple lead portions 110 are disposed at intervals from one another along the longitudinal direction of the connecting bar 130. Each lead portion 110 extends from the connecting bar 130.

[0079] The lead portion 110 is disposed along the periphery of the die pad portion 120. A portion of the lead portion 110 is thinned from the lower surface side. This portion thinned from the lower surface side is an inner lead portion 111. The portion of the lead portion 110 that is not thinned from the lower surface side is a terminal portion 113, and an external terminal 150 is formed on the lower surface of the terminal portion 113. The external terminal 150 is a portion that is electrically connected to an external mounting board (not shown). The external terminal 150 is a portion that is exposed to the outside of the semiconductor device 200 described later.

[0080] The inner lead portion 111 is thinned from the lower surface side by, for example, half etching. The inner lead portion 111 has an inner lead portion upper surface 111A, an inner lead portion lower surface 111B facing the inner lead portion upper surface 111A, and an inner lead portion side wall surface. The inner lead portion upper surface 111A is a part of the upper surface of the lead portion 110. The inner lead side wall surface includes a die pad portion facing surface 111C facing the die pad portion 120 side, and an opposing surface of the adjacent lead portion 110. The inner lead portion lower surface 111B is located below the lead portion 110.

[0081] The terminal portion 113 is located on the connecting bar 130 side. The terminal portion 113 is connected to the connecting bar 130. The lower surface of the terminal portion 113 constitutes the above-mentioned external terminal 150. The terminal portion 113 is not half-etched and has the same thickness as the die pad portion 120. Note that a part of the lower surface side of the terminal portion 113 located on the connecting bar 130 side may be thinned to constitute a connection portion with the connecting bar 130.

[0082] At least a part of the upper surface and the side wall surface of the lead portion 110 are roughened surfaces, and the lower surface of the lead portion 110 (terminal portion 113) is a non-roughened surface. The lower surface 111B of the inner lead portion is a roughened surface. In FIG. 1 and other figures, the roughened surface is indicated by a thick dashed line.

[0083] In this embodiment, when simply referring to a "rough surface", the rough surface means a roughened surface, preferably a roughened surface roughened by microetching or the like.

[0084] The thinned portion of the lower surface of the lead portion 110 is a roughened surface. Specifically, the inner lead portion lower surface 111B is a roughened surface over its entirety. On the other hand, the non-thinned portion of the lower surface of the lead portion 110 is a non-roughened surface. Specifically, the terminal portion 113 is not thinned from the lower surface side, and the external terminal 150 located on the lower surface side of the terminal portion 113 is a non-roughened surface over its entirety. The inner lead portion side wall surface including the die pad portion facing surface 111C is a roughened surface over its entirety.

[0085] Of the upper surface of the lead portion 110 (inner lead portion 111), a portion of the region located on the die pad portion 120 side may be a non-roughened surface, and the non-roughened surface may be provided with a metal plating layer 112. The metal plating layer 112 may be formed by, for example, an electrolytic plating method. The thickness of the metal plating layer 112 may be in the range of 1 μm to 10 μm. The metal plating layer 112 may be, for example, an Ag plating layer, an Ag alloy plating layer, an Au plating layer, an Au alloy plating layer, a Pt plating layer, a Cu plating layer, a Cu alloy plating layer, a Pd plating layer, a Ni plating layer, or the like, and may include one or more of these. The metal plating layer 112 preferably includes at least one of an Ag plating layer, a Ni plating layer, a Pd plating layer, and an Au plating layer. In addition, when underplating is required depending on the components constituting the metal plating layer 112, a known underplating may be applied. For example, a Ni plating layer, a Cu plating layer, or the like can be used as the underplating.

[0086] As described below, a semiconductor element 210 is mounted on the upper surface of the die pad portion 120. In addition, a plurality of lead portions 110 may be arranged around the periphery of the die pad portion 120. The upper surface and side wall surfaces of the die pad portion 120 may be roughened surfaces, and the lower surface of the die pad portion 120 may be a non-roughened surface (see FIG. 2).

[0087] The upper surface of the die pad portion 120 is a region (internal terminal) that is bonded to the semiconductor element 210 via an adhesive 240 such as a die attach paste, as described later. The lower surface of the die pad portion 120 is not thinned by, for example, half etching, and is a non-roughened surface that is not roughened like the metal substrate 310 before processing, as described later. The lower surface of the die pad portion 120 is exposed to the outside in the semiconductor device 200, which will be described later.

[0088] The package areas 100A are connected to each other via connecting bars 130, which extend along the X and Y directions, respectively. The X and Y directions are two directions parallel to each side of the package area 100A within the plane of the lead frame 100, and the X and Y directions are perpendicular to each other.

[0089] Each connecting bar 130 is disposed around the package area 100A and outside the package area 100A. Each connecting bar 130 has a long and thin rod shape in a plan view. The width W of each connecting bar 130 (the distance in a direction perpendicular to the longitudinal direction of the connecting bar 130) is not particularly limited, but may be appropriately set within a range of, for example, 95 μm to 250 μm. A plurality of lead parts 110 are connected to each connecting bar 130 at a predetermined interval along the longitudinal direction of the connecting bar 130, and the die pad part 120 is supported by the connecting bar 130 via the hanging lead 140. Note that the connecting bar 130 in this embodiment is not thinned, but is not limited to this aspect. For example, the connecting bar 130 may be thinned from its lower surface side by half etching. In this case, the thickness of the connecting bar 130 can be set in consideration of the configuration of the semiconductor device 200. The thickness of the connecting bar 130 can be appropriately set within the range of, for example, 80 μm to 200 μm.

[0090] The lead frame 100 according to the present embodiment is used to manufacture a semiconductor device 200 having a sealing portion 230 described later, and the upper surface of the lead portion 110 and the side wall surface of the lead portion 110 that contacts the sealing portion 230 may be roughened. In addition, the upper surface of the lead portion 110 and the side wall surface of the lead portion 110 located outside the package area 100A, as well as the connecting bar 130 may be roughened or may be a non-roughened surface. When manufacturing the semiconductor device 200 using the lead frame 100, dicing is performed along the connecting bar 130. At this time, if each package area 100A is molded and diced individually, there is a risk that foreign matter will be generated when dicing the lead frame 100 if the upper surface of the connecting bar 130 is a roughened surface. Therefore, by making the upper surface of the connecting bar 130 a non-roughened surface, the generation of foreign matter can be suppressed when manufacturing the semiconductor device 200.

[0091] In the rough surface of the lead frame 100 according to this embodiment, * The value is in the range of 12 to 19, and b * The value is in the range of 12 to 17, preferably a * The value is in the range of 13 to 18, and b * The value is in the range of 12 to 16. As will be apparent from the examples described later, in the CIELab color space of the rough surface of the lead frame 100 according to this embodiment, * value and b * When the value is within a predetermined range, the surface area ratio becomes high. Therefore, in a semiconductor device that can be manufactured using the lead frame 100, the adhesive strength with the molding resin increases. This makes it possible to prevent moisture in the air from penetrating to the electrodes of the semiconductor element. That is, in the a of the CIELab color space of the rough surface of the lead frame 100 according to this embodiment, * value and b * By setting the value within the above range, it is possible to manufacture a semiconductor device capable of suppressing the infiltration of moisture in the air to the electrodes of the semiconductor element. *value and b * The values ​​are measured using a spectrodensitometer eXact (manufactured by X-rite).

[0092] Here, the CIELab color space (L * a * b * This section explains color space. * a * b * The color space is the CIELab chromaticity diagram recommended by the CIE. * represents the lightness, and a * represents the degree of red / magenta or green, and b * represents the degree of yellow or blue. * The more negative the value, the closer it is to green, and the more positive the value, the closer it is to red. * The more negative the value, the closer it is to blue, and the more positive the value, the closer it is to yellow. * A value of 100 indicates white (total reflection), and L * A value of 0 indicates black (total absorption), and the center of these three values ​​is the intermediate color (gray). That is, L * Axial movement indicates a change in brightness, a * b * Movement on the plane indicates a change in hue. * a * b * The spatial distance corresponds to the closeness of the colors, and the closer the distance, the closer the colors are. * The value is between red / magenta and green, b * It can be said that the value corresponds to the above-mentioned predetermined range between yellow and blue.

[0093] In the lead frame 100 according to this embodiment, the arithmetic mean curvature Spc of the peaks of the rough surface is 700 mm -1 More than 1000 mm, preferably -1 ~5000mm -1 and more preferably 2000 mm -1 ~4000mm -1As is clear from the examples described later, when the arithmetic mean curvature Spc of the peaks of the rough surface of the lead frame 100 according to this embodiment is within a predetermined range, the point of contact with the contacted body is sharp. In this case, in a semiconductor device manufactured using the lead frame 100, the adhesive strength with the molding resin is increased, and it is possible to suppress the moisture in the air from penetrating to the electrodes of the semiconductor element. That is, when the arithmetic mean curvature Spc of the peaks of the rough surface of the lead frame 100 according to this embodiment is within the above range, it is possible to manufacture a semiconductor device that can suppress the moisture in the air from penetrating to the electrodes of the semiconductor element. Furthermore, the arithmetic mean height Sa of the rough surface is preferably 0.12 μm or more, and more preferably in the range of 0.12 μm to 0.34 μm. When the arithmetic mean curvature Spc of the peaks of the rough surface is 700 mm -1 As described above, by setting the arithmetic mean height Sa of the rough surface within a predetermined range, a semiconductor device can be manufactured that can effectively prevent moisture in the air from penetrating to the electrodes of the semiconductor element. The arithmetic mean curvature Spc of the apex represents the average of the principal curvatures of the apex of the object, and the sharper the apex, the larger the value of the arithmetic mean curvature Spc of the apex. The arithmetic mean height Sa is a parameter that expands the arithmetic mean height Ra of the line to three dimensions, i.e., a surface, and is a numerical value that represents the average of the absolute value of the difference in height of each point with respect to the average surface of the surface. In this embodiment, the arithmetic mean curvature Spc and the arithmetic mean height Sa of the apex are measured using a laser microscope VK-X260 (manufactured by Keyence Corporation, measurement unit) and a laser microscope VK-X250 (manufactured by Keyence Corporation, controller unit).

[0094] In general, in recent years, there has been a demand for smaller and thinner lead frames used in QFN (Quad Flat Non-leaded package) type semiconductor devices. In such semiconductor devices, the path through which moisture contained in the outside air can penetrate, which is the distance from the outer periphery to the electrodes of the semiconductor element, tends to become short, and moisture in the air may penetrate to the electrodes of the semiconductor element, causing the semiconductor device to malfunction.

[0095] Therefore, the inventors realized that the state of the roughened surface of the lead frame used in the semiconductor device is important. From the viewpoint of the reliability required for the semiconductor device, the inventors realized that the CIELab color space or the arithmetic mean curvature Spc and the arithmetic mean height Sa of the peak should be focused on as an index showing the state of the rough surface. * The value is in the range of 12 to 19, and b * If the value is in the range of 12 to 17, or the arithmetic mean curvature Spc of the peaks of the rough surface is 700 mm -1 As described above, the present inventors have realized that when the arithmetic mean height Sa of the rough surface is 0.12 μm or more, a lead frame with the high reliability required for a semiconductor device can be obtained, and have thus completed the present invention.

[0096] The roughened surface according to this embodiment may be formed, for example, by roughening the metal substrate 310 described below with a micro-etching solution. Examples of the micro-etching solution that can be used in this embodiment include those containing sulfuric acid or hydrochloric acid as a main component, and those containing hydrogen peroxide and sulfuric acid as main components.

[0097] In this embodiment, the rough surface is a * The value is in the range of 12 to 19, and b * The value is in the range of 12 to 17. In addition, the arithmetic mean curvature Spc of the peak of the rough surface is 700 mm -1 The arithmetic mean height Sa of the rough surface is 0.12 μm or more. By having a rough surface within such a predetermined range, a semiconductor device can be manufactured that can prevent moisture in the air from penetrating to the electrodes of the semiconductor element.

[0098] The lead frame 100 described above is made of a metal such as copper, a copper alloy, a Ni alloy, etc. The thickness of the lead frame 100 can be set in consideration of the configuration of the semiconductor device 200, and can be appropriately set within the range of, for example, 80 μm to 300 μm.

[0099] In this embodiment, the lead portions 110 are arranged along all four sides of the package area 100A, but this is not limited to this and may be arranged, for example, along only two opposing sides of the package area 100A.

[0100] The lead frame 100 shown in Figures 1 and 2 has been described as having a die pad portion 120, but this is not limited to this and may not have a die pad portion 120. For example, each lead portion 110 may be connected to a semiconductor element 210 via a bump as a connecting member 220, as described below (see Figure 5).

[0101] [Semiconductor Device] An embodiment of the semiconductor device of the present disclosure will be described. As shown in Figures 3 and 4, the semiconductor device 200 includes a plurality of lead portions 110, a die pad portion 120, a semiconductor element 210, a connection member 220, and a sealing portion 230.

[0102] The semiconductor device 200 in this embodiment is manufactured using the lead frame 100 described above. Therefore, the lead portion 110 and the die pad portion 120 in the semiconductor device 200 are provided on the lead frame 100 described above. Therefore, the upper surface of the lead portion 110 on the outer side (the side farther from the die pad portion 120) than the metal plating layer 112 and the side wall surface of the lead portion 110 are roughened rough surfaces. In addition, the upper surface of the die pad portion 120 and the side wall surface of the die pad portion 120 are also roughened rough surfaces. As shown in FIG. 4, the lead portion 110 includes an inner lead portion 111 thinned from the lower surface side of the lead portion 110, and the inner lead portion lower surface 111B is a rough surface. The sealing portion 230 is in close contact with the inner lead portion lower surface 111B. The terminal portion 113 of the lead portion 110 is not thinned from the lower surface side. The external terminal 150 located on the lower surface of the terminal portion 113 is a non-roughened surface. The external terminals 150 are exposed from the sealing portion 230 .

[0103] a in the CIELab color space for the above rough surface * The value is in the range of 12 to 19, and b *The value ranges from 12 to 17. * value and b * By keeping the value within the above range, it is possible to prevent moisture in the air from penetrating to the electrodes of the semiconductor element 210 .

[0104] In addition, the arithmetic mean curvature Spc of the peaks of the rough surface is 700 mm -1 The arithmetic mean curvature Spc of the peak is 700 mm. -1 By setting the roughness at 0.12 μm or more, it is possible to prevent moisture in the air from penetrating to the electrodes of the semiconductor element 210. Furthermore, the arithmetic mean height Sa of the rough surface is preferably 0.12 μm or more, and more preferably in the range of 0.12 μm to 0.34 μm. The arithmetic mean curvature Spc of the peaks of the rough surface is 700 mm -1 As described above, by having the arithmetic mean height Sa of the rough surface be within a predetermined range, it is possible to more effectively prevent moisture in the air from penetrating to the electrodes of the semiconductor element 210.

[0105] The semiconductor element 210 can be any of various semiconductor elements commonly used in the past, and is not particularly limited, but can be, for example, an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, a diode, etc. This semiconductor element 210 has a plurality of electrodes 210A to which each of the connection members 220 is attached.

[0106] Each connection member 220 is made of a metal material with good conductivity, such as copper or gold, and one end of each connection member 220 is electrically connected to the electrode 210A of the semiconductor element 210, and the other end is electrically connected to the metal plating layer 112 located on each lead portion 110. Examples of connection members 220 include conductors such as bonding wires and bumps.

[0107] The sealing portion 230 seals at least the lead portion 110, the die pad portion 120, the semiconductor element 210, and the connection member 220. The sealing portion 230 may be made of a resin, such as a thermosetting resin, such as a silicone resin or an epoxy resin, or a thermoplastic resin, such as a PPS resin. The thickness of the entire sealing portion 230 is not particularly limited, but may be appropriately set within a range of about 300 μm to 1500 μm, for example. In addition, in a plan view of the semiconductor device 200, the length of one side of the sealing portion 230 (one side of the semiconductor device 200) is not particularly limited, but may be appropriately set within a range of about 0.2 mm to 20 mm, for example.

[0108] The semiconductor device 200 shown in Figures 3 and 4 has been described as having a die pad portion 120, but this is not limited to this and may not have a die pad portion 120. For example, each lead portion 110 may be connected to an electrode 210A of the semiconductor element 210 via a bump as a connecting member 220 (see Figure 5).

[0109] [Lead frame manufacturing method] The method for manufacturing the leadframe 100 shown in Figures 1 and 2 will be described as an example. Figures 6A to 6H are process diagrams for explaining the method for manufacturing the leadframe according to this embodiment.

[0110] <Metal substrate preparation process> As shown in Figures 6A and 6B, a metal substrate 310 having a first surface 310A and a second surface 310B facing the first surface 310A is prepared (see Figure 6A). Note that, examples of the metal substrate 310 that can be used in this embodiment include a pure copper substrate, a copper alloy substrate, and a 42 alloy (Ni42% Fe alloy) substrate, but a pure copper substrate or a copper alloy substrate is preferable. In addition, the metal substrate 310 may be one that has been subjected to degreasing and cleaning treatment on the first surface 310A and the second surface 310B.

[0111] <Metal substrate processing process> Next, photosensitive resist 320 is applied to each of first surface 310A and second surface 310B of metal substrate 310, and then dried (see FIG. 6B). Note that the photosensitive resist 320 that can be used in this embodiment may be a conventionally known one.

[0112] Subsequently, the metal substrate 310 is exposed through a photomask and developed to form a resist layer 340 having desired openings 330 (see FIG. 6C).

[0113] Next, the metal substrate 310 is etched with an etchant using the resist layer 340 as a corrosion-resistant film (see FIG. 6D). The etchant can be appropriately selected depending on the material of the metal substrate 310 to be used. For example, when a pure copper substrate is used as the metal substrate 310, a ferric chloride aqueous solution is usually used as the etchant, and spray etching may be performed on both the first surface 310A and the second surface 310B of the metal substrate 310. This forms the outlines of the lead portion 110, the die pad portion 120, and the connecting bar 130. At this time, the lower surface of a part of the lead portion 110 may be thinned by half etching, and the inner lead portion 111 and the terminal portion 113 may be formed.

[0114] Next, the resist layer 340 is peeled off and the coating layer 350 is formed on the surface of the etched metal substrate 310 (see FIG. 6E). As a result, the coating layer 350 is formed on the entire circumference of the lead portion 110, the die pad portion 120, and the connecting bar 130. The thickness of the coating layer 350 is not particularly limited, but may be, for example, more than 0 μm and 2 μm or less. The metal forming the coating layer 350 is not particularly limited, but may be, for example, silver. When the coating layer 350 is made of a silver plating layer, a silver plating solution containing silver cyanide and potassium cyanide as main components can be used as the plating solution for electrolytic plating. It is preferable not to form the coating layer 350 on the external terminal 150 on the lower surface of the lead portion 110 (terminal portion 113) and the lower surface of the die pad portion 120. In order to avoid forming a covering layer 350 on the underside of the external terminal 150 on the underside of the lead portion 110 (terminal portion 113) and the underside of the die pad portion 120, the formation of the covering layer 350 may be avoided, for example, by forming a resist layer 400 on the underside of the external terminal 150 on the underside of the lead portion 110 (terminal portion 113) and the underside of the die pad portion 120 (see Figure 6E).

[0115] Next, the coating layer 350 present in the region forming the rough surface is removed. Specifically, the coating layer 350 formed on the upper surface of the lead portion 110 other than the region where the metal plating layer 112 is provided, the sidewall surface of the lead portion 110, the lower surface of the inner lead portion 111, the upper surface of the die pad portion 120, and the sidewall surface of the die pad portion 120 is removed (see FIG. 6F). During this, as shown in FIG. 6F, elastic members 410 such as rubber packings are placed on the first surface 310A and the second surface 310B of the metal substrate 310, and the metal substrate 310 is sandwiched by a jig 420 via the elastic members 410. Next, the coating layer 350 in the portion not covered by the elastic members 410 is peeled off and removed. As a result, the upper surface of the upper surface of the lead portion 110 other than the region where the metal plating layer 112 is provided, the sidewall surface of the lead portion 110, the lower surface of the inner lead portion 111, the upper surface of the die pad portion 120, and the sidewall surface of the die pad portion 120 are exposed. On the other hand, the upper surface of the lead portion 110 covered with the elastic member 410 in the region where the metal plating layer 112 is to be formed and the covering layer 350 on the connecting bar 130 remain.

[0116] <Rough surface formation process> Next, a support layer 360 that supports the metal substrate 310 is provided on the lower surface side of the metal substrate 310 (see FIG. 6G). The support layer 360 may be, for example, a resist layer. After providing the support layer 360, the portion of the metal substrate 310 that is not covered by the coating layer 350 is roughened to form a rough surface (see FIG. 6G). Specifically, the rough surfaces are formed on the upper surface of the lead portion 110 that is outside (the side farther from the die pad portion 120) of the region where the metal plating layer 112 is formed, the sidewall surface of the lead portion 110, the lower surface of the inner lead portion 111, the upper surface of the die pad portion 120, and the sidewall surface of the die pad portion 120. To form the rough surface, for example, a microetching solution is supplied to the metal substrate 310. This allows the rough surface to be formed on the entire metal substrate 310 except for the portion covered by the coating layer 350. The microetching solution is a surface treatment agent that can slightly dissolve the metal surface and form a rough surface with fine irregularities. Examples of the microetching solution that can be used in this embodiment include those containing sulfuric acid or hydrochloric acid as a main component, and those containing hydrogen peroxide and sulfuric acid as main components.

[0117] In the step of forming the rough surface, the a in the CIELab color space of the rough surface is * Values ​​range from 12 to 19, b * The roughening is performed so that the arithmetic mean curvature Spc of the peaks of the roughened surface is in the range of 12 to 17. -1 or more. Furthermore, the roughened surface is preferably roughened so that its arithmetic mean height Sa is 0.12 μm or more, and more preferably is roughened so that it is in the range of 0.12 μm to 0.34 μm. By forming the roughened surface to be in such a predetermined range, it is possible to obtain a lead frame 100 that can be used to manufacture a semiconductor device that can prevent moisture in the air from penetrating to the electrodes of the semiconductor element.

[0118] Thereafter, the support layer 360 and the covering layer 350 are sequentially peeled off and removed, and a metal plating layer 112 is provided on the inner end (on the die pad portion 120 side) of the upper surface 111A of the inner lead portion, thereby obtaining the lead frame 100 shown in FIG. 1 and FIG. 2 (see FIG. 6H). The metal plating layer 112 can be formed, for example, by forming a plating resist layer having a predetermined pattern by a photolithography method, and forming the metal plating layer 112 by an electrolytic plating method on the portion not covered by the plating resist layer. The lead frame 100 produced by the above manufacturing method may be subjected to an alkali treatment. Specifically, the lead frame 100 is immersed in an alkaline aqueous solution. By performing the alkali treatment, the acid contained in the surface treatment agent used in the rough surface forming step is neutralized, and corrosion of the lead frame 100 can be suppressed. The alkali used in the alkali treatment is not particularly limited, and examples thereof include sodium hydroxide, potassium hydroxide, etc., and one of these may be used alone, or two or more of them may be used in combination.

[0119] [Method of manufacturing semiconductor device] The method for manufacturing the semiconductor device 200 shown in Figures 3 and 4 will be described as an example. Figures 7A to 7D are process diagrams for explaining the method for manufacturing the semiconductor device according to this embodiment.

[0120] First, a lead frame 100 manufactured by the manufacturing method shown in FIGS. 6A to 6H is prepared (see FIG. 7A). Next, a semiconductor element 210 is mounted on the die pad portion 120 of the lead frame 100. In this case, the semiconductor element 210 is placed and fixed on the die pad portion 120 using an adhesive 240 such as a die attach paste (see FIG. 7B). The adhesive 240 may be an epoxy resin-based adhesive containing components such as silver paste and epoxy resin. At this time, the semiconductor element 210 is placed on the rough upper surface of the die pad portion 120 via the adhesive 240.

[0121] Next, each electrode 210A of the semiconductor element 210 and the metal plating layer 112 formed on each lead portion 110 are electrically connected to each other by a connecting member 220 (see FIG. 7C).

[0122] Next, a thermosetting resin or a thermoplastic resin is injection molded or transfer molded onto the lead frame 100 to form the sealing portion 230 (see FIG. 7D). This allows the lead portion 110, the die pad portion 120, the semiconductor element 210, and the connection member 220 to be resin-sealed.

[0123] Thereafter, the lead frame 100 is diced for each package area 100A. At this time, since the upper surface of the connecting bar 130 to be diced is a non-roughened surface, it is possible to suppress the generation of foreign matter during dicing. In this manner, the lead frame 100 is diced into individual semiconductor devices 200, and the semiconductor device 200 shown in FIG. 3 and FIG. 4 is obtained.

[0124] Furthermore, when the semiconductor device 200 is used for a long time, moisture in the air may penetrate from the side or bottom side of the semiconductor device 200. For example, moisture in the air may penetrate through the interface between the sealing portion 230 and the lead portion 110 or the die pad portion 120.

[0125] In this embodiment, to solve this problem, rough surfaces are formed on the upper surface of the lead portion 110 where the metal plating layer 112 is not provided, the side wall surface of the lead portion 110, and the upper surface and the side wall surface of the die pad portion 120. * The value is in the range of 12 to 19, and b * The value is in the range of 12 to 17, or the arithmetic mean curvature Spc of the peaks of the rough surface is 700 mm -1The rough surface is roughened so that the arithmetic mean height Sa of the rough surface is 0.12 μm or more. This relatively increases the distance of the infiltration path through which moisture infiltrates from the interface between the sealing portion 230 and the lead portion 110 or the die pad portion 120 to the semiconductor element 210 side. This makes it possible to prevent moisture from infiltrating into the electrodes 210A of the semiconductor element 210. Furthermore, by having a rough surface within the above-mentioned predetermined range, it is possible to increase the adhesion strength between the die pad portion 120 or the lead portion 110 and the sealing portion 230, and it is possible to prevent the die pad portion 120 or the lead portion 110 and the sealing portion 230 from peeling off from each other.

[0126] Moreover, the lead portion 110 in this embodiment includes an inner lead portion 111 that is thinned from the lower surface side of the lead portion 110. Since the lower surface of the inner lead portion 111 is rough, the distance of the moisture infiltration path at the interface between the sealing portion 230 and the lead portion 110 is long on the lower surface side of the semiconductor device 200. This makes it possible to suppress moisture from infiltrating from the interface between the sealing portion 230 and the lead portion 110 to the electrode 210A of the semiconductor element 210. Furthermore, since the lower surface of the inner lead portion 111 has a rough surface within the above-mentioned predetermined range, the adhesion strength between the lead portion 110 and the sealing portion 230 can be increased, and the lead portion 110 and the sealing portion 230 can be suppressed from peeling off from each other.

[0127] The above-described embodiments are described for the purpose of facilitating understanding of the present invention, and are not described for the purpose of limiting the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0128] [Example] The present disclosure will be described in more detail below with reference to examples and comparative examples, but the present disclosure is not limited to the following examples or the like.

[0129] Example 1 1 and 2. A lead frame 100 was prepared. In the lead frame 100, the upper surface and side wall surface of the lead portion 110 and the upper surface and side wall surface of the die pad portion 120 are in the a color space of the CIELab color space. * Value is 17.53, b * The value is 14.80 and the arithmetic mean curvature Spc of the peak is 2431.46 mm -1 , and the rough surface had an arithmetic mean height Sa of 0.14 μm. * value and b * The values ​​were measured using a spectrodensitometer eXact (manufactured by X-rite), and the arithmetic mean curvature Spc and arithmetic mean height Sa of the peaks were measured using a laser microscope VK-X260 (manufactured by Keyence, measurement unit) and a laser microscope VK-X250 (manufactured by Keyence, controller unit).

[0130] Example 2 The upper surface and side wall surface of the lead portion 110 and the upper surface and side wall surface of the die pad portion 120 are within the a range of the CIELab color space. * Value is 16.03, b * The value is 13.84 and the arithmetic mean curvature Spc of the peak is 2952.08 mm -1 A lead frame 100 having the same configuration as in Example 1 was prepared, except that the lead frame 100 had a rough surface having an arithmetic mean height Sa of 0.17 μm.

[0131] Example 3 The upper surface and side wall surface of the lead portion 110 and the upper surface and side wall surface of the die pad portion 120 are within the a range of the CIELab color space. * Value is 15.39, b * The value is 13.16 and the arithmetic mean curvature Spc of the peak is 3523.76 mm -1 A lead frame 100 having the same configuration as in Example 1 was prepared, except that the lead frame 100 had a rough surface having an arithmetic mean height Sa of 0.22 μm.

[0132] Example 4 The upper surface and side wall surface of the lead portion 110 and the upper surface and side wall surface of the die pad portion 120 are within the a range of the CIELab color space.* Value is 14.65, b * The value is 12.86 and the arithmetic mean curvature Spc of the peak is 3378.00 mm -1 A lead frame 100 having the same configuration as in Example 1 was prepared, except that the lead frame 100 had a rough surface having an arithmetic mean height Sa of 0.21 μm.

[0133] Comparative Example 1 The upper surface and side wall surface of the lead portion 110 and the upper surface and side wall surface of the die pad portion 120 are within the a range of the CIELab color space. * Value is 18.59, b * The value is 17.29 and the arithmetic mean curvature Spc of the peak is 629.05 mm -1 A lead frame having the same structure as in Example 1 was prepared, except that the lead frame had a rough surface having an arithmetic mean height Sa of 0.11 μm.

[0134] Comparative Example 2 The upper surface and side wall surface of the lead portion 110 and the upper surface and side wall surface of the die pad portion 120 are within the a range of the CIELab color space. * Value is 10.06, b * The value is 7.18 and the arithmetic mean curvature Spc of the peak is 986.96 mm -1 A lead frame having the same configuration as in Example 1 was prepared, except that the lead frame had a non-roughened surface having an arithmetic mean height Sa of 0.09 μm.

[0135] [Test example] The rough surface condition of each lead frame of Examples 1 to 4 and Comparative Examples 1 to 2 was observed by SEM and laser microscope, and the shear strength of each lead frame of Examples 1 to 4 and Comparative Examples 1 to 2 was measured. The results are shown in Table 1. The shear strength was measured by molding the mold resin on the lead frame and applying a shear direction as a mold resin adhesion strength test (pudding cup test). EME-631 (manufactured by Sumitomo Bakelite Co., Ltd.) was used as the mold resin, and mold resin molding was performed with a molding time of 120 seconds, a molding temperature of 175±5°C, and a molding pressure of 10 MPa, and then a curing treatment was performed at 175°C for 6 hours. The size of the molded mold resin was 4 mm in height, 4 mm in bottom diameter, and 3 mm in top diameter, and the bottom side was molded into the lead frame. The lead frame was then fixed to a bonding strength tester DAGE4000 (manufactured by Nordson Corporation), and a shear load of 1 kg was applied laterally to the molding resin on the lead frame at a speed of 0.1 mm / sec to measure the shear strength.

[0136] [Table 1]

[0137] As shown in Table 1, the rough surface of the lead frame 100 has a CIELab color space of a * The value is in the range of 12 to 19, and b * If the value is in the range of 12 to 17, a * value and b * It was confirmed that the shear strength increased when the value was outside the above range. * value and b * By keeping the value within the above range, it is presumed that the adhesion strength with the molding resin in the semiconductor device manufactured using the lead frame 100 will be increased, thereby preventing moisture in the air from penetrating to the electrodes 210A of the semiconductor element 210.

[0138] In addition, the arithmetic mean curvature Spc of the peaks of the rough surface of the lead frame 100 is 700 mm -1 If it is more than this, the arithmetic mean curvature Spc of the peak is 700 mm -1It was confirmed that the shear strength was increased compared to when the roughness was less than 700 mm. Furthermore, the arithmetic mean height Sa of the rough surface of each of the lead frames 100 in Examples 1 to 4 was 0.12 μm or more. From this result, it was found that the arithmetic mean curvature Spc of the peaks of the rough surface was 700 mm. -1 It is presumed that the arithmetic mean height Sa of the rough surface being 0.12 μm or more increases the adhesive strength with the molding resin in the semiconductor device manufactured using the lead frame 100, and can prevent moisture in the air from penetrating to the electrodes 210A of the semiconductor element 210. Note that the arithmetic mean curvature Spc of the peaks of the non-roughened surface of Comparative Example 2 is 700 mm -1 This is because when the lead frame of Comparative Example 2 was manufactured by rolling the metal substrate, there were sharp rolling marks, and the arithmetic mean curvature Spc of the apex of the rolling marks was 700 mm. -1 It is presumed that the above-mentioned result was obtained. Also, the arithmetic mean curvature Spc of the peaks of the rough surface of the lead frame of Comparative Example 1 is smaller than the arithmetic mean curvature Spc of the peaks of the non-roughened surface of Comparative Example 2. This is presumed to be because the rough surface was formed by roughening to such an extent that the peaks of the peaks with sharp rolling marks were scraped off. The rough surfaces of the lead frames 100 of Examples 1 to 4 are rougher than the rough surface of the lead frame of Comparative Example 1. It is presumed that the etching is deep, resulting in a large value of the arithmetic mean curvature Spc of the peaks.

[0139] Second Embodiment Next, a second embodiment will be described with reference to Figures 8 to 17. In the following figures, the same parts are denoted by the same reference numerals, and some detailed descriptions may be omitted.

[0140] (Lead frame configuration) First, an outline of the lead frame according to this embodiment will be described with reference to Figures 8 to 10. Figures 8 to 10 are diagrams showing the lead frame according to this embodiment.

[0141] The lead frame 10 shown in Figures 8 and 9 is used when manufacturing a semiconductor device 20 (Figures 11 and 12). Such a lead frame 10 has a plurality of package areas 10a. The plurality of package areas 10a are arranged in multiple rows and multiple stages (in a matrix). Note that Figure 8 shows only a portion of the lead frame 10 centered on one package area 10a.

[0142] In this specification, "inner" and "inside" refer to the side facing the center of each package area 10a. "Outer" and "outside" refer to the side away from the center of each package area 10a (the connecting bar 13 side). Additionally, "front surface" refers to the surface on which the semiconductor element 21 is mounted. "Back surface" refers to the surface opposite the "front surface" that is connected to an external mounting board (not shown). "Side surface" refers to the surface located between the "front surface" and the "back surface" that constitutes the thickness of the lead frame 10 (metal substrate).

[0143] In this specification, half-etching refers to etching the material to be etched halfway in the thickness direction. The thickness of the material to be etched after half-etching is, for example, 30% to 70%, preferably 40% to 60%, of the thickness of the material to be etched before half-etching.

[0144] 8 and 9, each package area 10a of the lead frame 10 includes a die pad 11 and a lead portion 12 located around the die pad 11. Of these, the lead portion 12 is partially thinned from the back surface side. Of the back surface of the lead portion 12, the thinned portion is a rough surface. Of the back surface of the lead portion 12, the non-thinned portion is a smooth surface.

[0145] The package region 10a is a region corresponding to a semiconductor device 20 (described later). The package region 10a is a region surrounded by a rectangular imaginary line (two-dot chain line) in FIG. 8. In this embodiment, the lead frame 10 includes a plurality of package regions 10a. However, this is not limited thereto, and only one package region 10a may be formed in one lead frame 10.

[0146] The package areas 10a are connected to each other via connecting bars (support members) 13. The connecting bars 13 support the die pad 11 and the leads 12. The connecting bars 13 extend along the X direction or the Y direction. Here, the X direction and the Y direction are two directions parallel to each side of the package areas 10a within the plane of the lead frame 10. The X direction and the Y direction are perpendicular to each other. The Z direction is perpendicular to both the X direction and the Y direction.

[0147] Each connecting bar 13 is disposed around the package area 10a and outside the package area 10a. Each connecting bar 13 has a long and thin rod shape in a plan view. The width of each connecting bar 13 (the distance in a direction perpendicular to the longitudinal direction of the connecting bar 13) may be 95 μm or more and 250 μm or less. A plurality of lead parts 12 are connected to each connecting bar 13 at intervals along the longitudinal direction of the connecting bar 13. The die pad 11 is supported by the connecting bar 13 via the hanging lead 14. The connecting bar 13 is not thinned, but is not limited to this, and may be thinned from the back side by, for example, half etching. The thickness of the connecting bar 13 may be 80 μm or more and 200 μm or less, depending on the configuration of the semiconductor device 20.

[0148] As shown in FIG. 9, the die pad 11 has a die pad front surface 11a located on the front surface side and a die pad back surface 11b located on the back surface side. A semiconductor element 21 is mounted on the die pad front surface 11a as described later. The die pad back surface 11b is exposed to the outside from a semiconductor device 20 (described later). A first die pad side surface 11c and a second die pad side surface 11d are formed on the side of the die pad 11 facing the lead portion 12. The first die pad side surface 11c is located on the die pad front surface 11a side. The second die pad side surface 11d is located on the die pad back surface 11b side. In this case, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are each rough surfaces. On the other hand, the die pad front surface 11a has a smooth surface (die pad smooth surface region 11e) and a rough surface (die pad rough surface region 11f) as described later. The die pad back surface 11b is a smooth surface.

[0149] In this embodiment, the term "rough surface" refers to a surface having an S-ratio of 1.30 or more. The term "smooth surface" refers to a surface having an S-ratio of less than 1.30. A rough surface is a surface that is rougher than a smooth surface. The S-ratio of a "rough surface" is preferably 1.30 or more and 2.30 or less. The S-ratio of a "smooth surface" is preferably 1.00 or more and 1.20 or less. Here, the "S-ratio" is the surface area obtained by dividing the surface to be measured into a plurality of pixels using an optical interference measuring device and measuring the surface area by the observation area. Specifically, the surface to be measured is divided into a plurality of pixels using a VertScan manufactured by Hitachi High-Tech Science Corporation, and the obtained surface area is divided by the observation area to calculate the S-ratio.

[0150] The rough surface may be formed by roughening the outer surface of metal substrate 31 (described later) with, for example, a microetching solution containing hydrogen peroxide and sulfuric acid as main components. The smooth surface may be an unprocessed surface of metal substrate 31 (described later) that is not subjected to such roughening treatment. In Fig. 9, the roughened portion is indicated by a thick dashed line (the same applies to other cross-sectional views).

[0151] The die pad surface 11a of the die pad 11 is a region (internal terminal) electrically connected to the semiconductor element 21 via bumps 26 as described below. The die pad surface 11a may be a region that has not been thinned by half etching or the like. The die pad surface 11a is formed with a die pad smooth surface region 11e, which is a smooth surface region, and a die pad rough surface region 11f, which is a rough surface region.

[0152] A plurality of die pad smooth surface areas 11e may be formed on the die pad surface 11a. The die pad smooth surface areas 11e are connected to corresponding bumps 26 (see FIG. 12). The number of die pad smooth surface areas 11e on the die pad 11 may be the same as the number of bumps 26 connected to the die pad 11. Alternatively, a plurality of bumps 26 may be disposed on one die pad smooth surface area 11e. In this case, the number of die pad smooth surface areas 11e on the die pad 11 may be less than the number of bumps 26 connected to the die pad 11.

[0153] The die pad rough surface region 11f is rougher than the die pad smooth surface region 11e (S-ratio is larger). As shown in FIG. 10(a), the die pad rough surface region 11f is formed so as to surround the entire circumference of each die pad smooth surface region 11e in a plan view. That is, the die pad smooth surface region 11e does not directly contact the periphery 11g of the die pad 11. The die pad rough surface region 11f is formed along the entire periphery 11g of the die pad 11 in a plan view. Here, the periphery 11g of the die pad 11 refers to the region surrounded by multiple (four) sides of the die pad 11 as shown in FIG. 8. In addition, the entire region of the die pad surface 11a other than the die pad smooth surface region 11e may be the die pad rough surface region 11f. That is, the die pad surface 11a may be composed only of the multiple die pad smooth surface regions 11e and the other die pad rough surface regions 11f.

[0154] As shown in FIG. 10(a), the die pad smooth surface region 11e may be circular in plan view. The die pad smooth surface region 11e is preferably larger than the bump 26 (virtual line) in plan view. The width (diameter) D1 of the die pad smooth surface region 11e may be 0.030 mm or more, or 0.035 mm or more. The width (diameter) D1 may be 0.070 mm or less, or 0.065 mm or less. When the bump 26 is disposed at the center of the die pad smooth surface region 11e, the shortest distance d1 between the periphery of the bump 26 and the periphery of the die pad smooth surface region 11e may be 0.005 mm or more, or 0.010 mm or more. The shortest distance d1 may be 0.020 mm or less, or 0.015 mm or less. The shortest distance L1 between the die pad smooth surface region 11e and the periphery 11g of the die pad 11 may be 0.025 mm or more, or 0.030 mm or more. The shortest distance L1 may be 1.0 mm or less, or 0.50 mm or less. Since the die pad smooth surface region 11e is circular in a plan view, it is easy to position the circular bump 26 with respect to the die pad smooth surface region 11e. In Fig. 10(a)(b), the smooth surface portion is shown in white, and the rough surface portion is shown in shaded (the same applies to Figs. 17(a)-(d)).

[0155] 10(a), when a plurality of die pad smooth surface regions 11e are present on the die pad surface 11a, the shortest distance M1 between adjacent die pad smooth surface regions 11e may be 0.030 mm or more, or 0.040 mm or more. The shortest distance M1 may be 1.0 mm or less, or 0.50 mm or less. The pitch P1 between the centers of adjacent die pad smooth surface regions 11e may be 0.045 mm or more, or 0.057 mm or more. The pitch P1 may be 1.2 mm or less, or 0.60 mm or less. The pitch P1 corresponds to the pitch between the centers of adjacent bumps 26.

[0156] 9, an external terminal may be formed on the die pad back surface 11b of the die pad 11. This external terminal may be electrically connected to a mounting board (not shown). The die pad back surface 11b is not thinned by, for example, half etching, and has a smooth surface similar to that of a metal substrate (metal substrate 31 described later) before processing. The die pad back surface 11b is exposed to the outside from the semiconductor device 20 after the semiconductor device 20 (described later) is manufactured.

[0157] As will be described later, each lead portion 12 is connected to the semiconductor element 21 via a bump 26, and is disposed with a space between it and the die pad 11. The multiple lead portions 12 are disposed at intervals along the longitudinal direction of the connecting bar 13. Each lead portion 12 extends from the connecting bar 13.

[0158] The lead portion 12 is disposed along the periphery of the die pad 11. The lead portion 12 is partially thinned from the back surface side. In this case, the back surface of the lead portion 12, an inner lead 51 described later, is thinned. An external terminal 17 is formed on a portion of the back surface of the lead portion 12 that is not thinned. The external terminal 17 is electrically connected to an external mounting board (not shown). The external terminal 17 is exposed to the outside from the semiconductor device 20 after the semiconductor device 20 (described later) is manufactured.

[0159] As shown in Fig. 9, the lead portion 12 has an inner lead 51 and a terminal portion 53. The inner lead 51 is located on the inside (the die pad 11 side). The terminal portion 53 is located on the outside (the connecting bar 13 side). The inner lead 51 extends from the terminal portion 53 to the die pad 11 side. An internal terminal is formed on the front surface side of the inner lead 51. This internal terminal is an area (lead smooth surface area 12e) that is electrically connected to the semiconductor element 21 via a bump 26 as described below.

[0160] The inner lead 51 is thinned from the back surface side by, for example, half etching. The inner lead 51 has an inner lead front surface 51a and an inner lead back surface 51b. The inner lead front surface 51a is located on the front surface side. An inner lead tip surface 51c is formed on the surface of the inner lead 51 facing the die pad 11. The inner lead back surface 51b is located on the back surface side.

[0161] The terminal portion 53 is located on the connecting bar 13 side. The base end of the terminal portion 53 is connected to the connecting bar 13. The terminal portion 53 has a terminal portion surface 53a. The above-mentioned external terminal 17 is formed on the back surface of the terminal portion 53. The terminal portion 53 is not half-etched and has the same thickness as the die pad 11. Note that the back surface of the portion of the lead portion 12 located closer to the connecting bar 13 than the terminal portion 53 may be thinned to form a connection portion with the connecting bar 13.

[0162] In this embodiment, the thinned portion of the back surface of the lead portion 12 is a rough surface. Specifically, the inner lead 51 of the lead portion 12 is thinned from the back surface side. The inner lead back surface 51b located on the back surface side of the inner lead 51 is a rough surface over its entire area. On the other hand, the non-thinned portion of the back surface of the lead portion 12 is a smooth surface. Specifically, the terminal portion 53 of the lead portion 12 is not thinned from the back surface side. The external terminal 17 located on the back surface side of the terminal portion 53 is a smooth surface over its entire area.

[0163] Furthermore, the entire inner lead tip surface 51c of the lead portion 12 is roughened. Although not shown, both side surfaces along the longitudinal direction of the lead portion 12 may also be roughened. On the other hand, the inner lead 51 of the lead portion 12 is not thinned from the surface side. Furthermore, the terminal portion 53 of the lead portion 12 is not thinned from the surface side.

[0164] The lead surface 12a is composed of an inner lead surface 51a of the inner lead 51 and a terminal portion surface 53a of the terminal portion 53. The lead surface 12a is a region that is not thinned from the front side by half etching or the like. The lead surface 12a is formed with a lead smooth surface region 12e, which is a smooth surface region, and a lead rough surface region 12f, which is a rough surface region.

[0165] One lead smooth surface area 12e is formed on the lead surface 12a of each lead 12. A plurality of lead smooth surface areas 12e may be formed on the lead surface 12a of each lead 12. The lead smooth surface areas 12e are connected to corresponding bumps 26 (see FIG. 12). A plurality of bumps 26 may be disposed on one lead smooth surface area 12e. In this case, the number of lead smooth surface areas 12e on each lead 12 may be less than the number of bumps 26 connected to the lead 12.

[0166] The lead rough surface region 12f is present around the lead smooth surface region 12e. The lead rough surface region 12f is rougher than the lead smooth surface region 12e (has a larger S-ratio). As shown in FIG. 10(b), the lead rough surface region 12f is formed so as to surround the entire periphery of each lead smooth surface region 12e in a plan view. That is, the lead smooth surface region 12e does not directly contact the periphery 12g of the lead portion 12. The lead rough surface region 12f is formed along the entire periphery 12g of the lead portion 12 in a plan view. Here, the periphery 12g of the lead portion 12 refers to the region surrounded by multiple (three) sides of the lead portion 12 and the connecting bar 13, as shown in FIG. 8. The entire region of the lead surface 12a other than the lead smooth surface region 12e may be the lead rough surface region 12f. That is, the lead surface 12a may be composed only of the lead smooth surface region 12e and the remaining lead rough surface region 12f.

[0167] As shown in FIG. 10(b), the lead smooth surface region 12e may be circular in plan view. The shape of the lead smooth surface region 12e may be the same as or different from that of the die pad smooth surface region 11e described above. The lead smooth surface region 12e is preferably larger than the bump 26 (virtual line) in plan view. The width (diameter) D2 of the lead smooth surface region 12e may be 0.030 mm or more, or 0.035 mm or more. The width (diameter) D2 may be 0.070 mm or less, or 0.065 mm or less. When the bump 26 is disposed at the center of the lead smooth surface region 12e, the shortest distance d2 between the periphery of the bump 26 and the periphery of the lead smooth surface region 12e may be 0.005 mm or more, or 0.010 mm or more. The shortest distance d2 may be 0.020 mm or less, or 0.015 mm or less. The shortest distance L2 between the lead smooth surface region 12e and the periphery 12g of the lead portion 12 may be 0.025 mm or more, or 0.030 mm or more. The shortest distance L2 may be 1.0 mm or less, or 0.50 mm or less. The lead smooth surface region 12e is circular in plan view, which makes it easier to position the circular bump 26 with respect to the die pad smooth surface region 11e.

[0168] The lead frame 10 described above is generally made of metal such as copper, copper alloy, 42 alloy (Ni42% Fe alloy), etc. The thickness of the non-thinned portion of the lead frame 10 may be 80 μm or more and 300 μm or less, depending on the configuration of the semiconductor device 20 to be manufactured.

[0169] In this embodiment, the lead portions 12 are arranged along all four sides of the package area 10a, but this is not limited thereto, and the lead portions 12 may be arranged, for example, along only two opposing sides of the package area 10a.

[0170] (Configuration of Semiconductor Device) Next, the semiconductor device according to the present embodiment will be described with reference to Figures 11 to 13. Figures 11 to 13 are diagrams showing the semiconductor device (flip chip type) according to the present embodiment.

[0171] As shown in FIGS. 11 and 12, a semiconductor device (semiconductor package) 20 includes a die pad 11, a semiconductor element 21, a plurality of leads 12, a plurality of bumps 26, and a sealing resin 23.

[0172] Of these, the semiconductor element 21 is mounted on the die pad 11 and the lead portion 12. A plurality of bumps 26 electrically connect the semiconductor element 21 to the die pad 11 or the lead portion 12, respectively. In this case, the bumps 26 form the connection portion. The bumps 26 may also be pillars. The sealing resin 23 resin-seals the die pad 11, the lead portion 12, the semiconductor element 21, and the bumps 26.

[0173] The die pad 11 and the lead portion 12 are made from the lead frame 10 described above. In this case, the inner lead 51 of the lead portion 12 is thinned from the back surface side. The inner lead back surface 51b of the inner lead 51 is rough. The sealing resin 23 is adhered to the inner lead back surface 51b. The terminal portion 53 of the lead portion 12 is not thinned from the back surface side. The external terminal 17 located on the back surface of the terminal portion 53 has a smooth surface. The external terminal 17 is exposed to the outside from the sealing resin 23.

[0174] Bumps 26 are provided on the die pad 11 and the lead portions 12. The bumps 26 on the die pad 11 are provided in the die pad smooth surface region 11e. The bumps 26 are provided at a minimum distance d1 away from the die pad rough surface region 11f. The bumps 26 on the lead portions 12 are provided in the lead smooth surface region 12e. The bumps 26 are provided at a minimum distance d2 away from the lead rough surface region 12f. The semiconductor element 21 is electrically connected to the die pad 11 and the lead portions 12 via the bumps 26.

[0175] As the semiconductor element 21, various types of semiconductor elements that are generally used in the past can be used, and are not particularly limited, but examples that can be used include integrated circuits, large scale integrated circuits, transistors, thyristors, diodes, etc. This semiconductor element 21 has a plurality of electrodes 21a to which bumps 26 are each attached.

[0176] The sealing resin 23 may be a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin such as a PPS resin. The thickness of the entire sealing resin 23 may be about 300 μm or more and 1500 μm or less. Moreover, one side of the sealing resin 23 (one side of the semiconductor device 20) may be, for example, 0.2 mm or more and 20 mm or less, or 0.2 mm or more and 16 mm or less. In FIG. 11, the portion of the sealing resin 23 located on the surface side of the lead portion 12 and the semiconductor element 21 is not shown.

[0177] The bumps (connecting parts) 26 are made of a metal material with good conductivity such as copper, and may have a solid, generally cylindrical or generally spherical shape. The upper ends of the bumps 26 are connected to the electrodes 21a of the semiconductor element 21, and the lower ends are connected to the die pad smooth surface region 11e or the lead smooth surface region 12e, respectively. The width (diameter) of the bumps 26 may be 0.01 mm or more and 0.070 mm or less. The bumps 26 do not necessarily have to be provided on the die pad 11. In this case, the die pad 11 and the semiconductor element 21 may be fixed to each other by an adhesive such as die bonding paste.

[0178] 13(a) and (b) are enlarged cross-sectional views showing the periphery of the bump 26. As shown in FIG. 13(a), the bump 26 may be composed of a single layer. In this case, the bump 26 may include a metal layer such as copper. The bump 26 may be composed of the same metal as the main metal (e.g., copper) contained in the die pad 11 and the lead portion 12. The height of the bump 26 may be 30 μm or more and 110 μm or less.

[0179] 13(b), the bump 26 may include multiple layers. For example, the bump 26 includes a first layer 26a located on the die pad 11 side or the lead portion 12 side, and a second layer 26b located on the semiconductor element 21 side. The first layer 26a may include a metal such as tin. The height of the first layer 26a may be 1 μm or more and 10 μm or less. The second layer 26b may include a metal such as copper. The height of the second layer 26b may be 30 μm or more and 100 μm or less.

[0180] Besides this, the configurations of the die pad 11 and the lead portion 12 are the same as those shown in the above-mentioned FIGS. 8 to 10, except for the areas not included in the semiconductor device 20, and therefore a detailed description thereof will be omitted here.

[0181] (Lead frame manufacturing method) Next, a method for manufacturing the lead frame 10 shown in Figures 8 and 9 will be described with reference to Figures 14(a)-(i). Figures 14(a)-(i) are cross-sectional views (figures corresponding to Figure 9) showing the method for manufacturing the lead frame 10.

[0182] 14(a), a flat metal substrate 31 is prepared. A substrate made of a metal such as copper, a copper alloy, or a 42 alloy (a 42% Ni Fe alloy) can be used as this metal substrate 31. It is preferable to use a metal substrate 31 that has been degreased and cleaned on both sides.

[0183] Next, photosensitive resists 32a, 33a are applied to the entire front and back surfaces of the metal substrate 31, respectively, and then dried (FIG. 14(b)). As the photosensitive resists 32a, 33a, conventionally known ones can be used.

[0184] Subsequently, the metal substrate 31 is exposed through a photomask and developed to form etching resist layers 32, 33 having desired openings 32b, 33b (FIG. 14(c)).

[0185] Next, the metal substrate 31 is etched with an etchant using the etching resist layers 32, 33 as a corrosion-resistant film (FIG. 14(d)). The etchant can be appropriately selected depending on the material of the metal substrate 31 to be used. For example, when copper is used as the metal substrate 31, typically an aqueous solution of ferric chloride is used as the etchant, and spray etching may be performed from both sides of the metal substrate 31. This forms the outer shapes of the die pad 11, the lead portion 12, and the connecting bar 13. At this time, the lead portion 12 is partially thinned from the back surface side by half etching. Specifically, the back surface of the inner lead 51 of the lead portion 12 is thinned.

[0186] Next, the etching resist layers 32, 33 are peeled off and removed (FIG. 14(e)). In this manner, the metal substrate 31 having the die pad 11 and the lead portions 12 positioned around the die pad 11 is obtained.

[0187] Next, a plating layer 36 is formed on a part of the metal substrate 31 (FIG. 14(f)). At this time, an elastic member 46 such as a rubber packing having a predetermined pattern of openings is first placed on the surface of the metal substrate 31. The openings of the elastic member 46 have shapes corresponding to the die pad smooth surface area 11e and the lead smooth surface area 12e. Next, the surface of the metal substrate 31 is pressed by a jig 47 via the elastic member 46. The jig 47 has openings of the same pattern as the elastic member 46. Next, the plating layer 36 is formed on the part of the surface of the metal substrate 31 that is not covered by the elastic member 46 and the jig 47. As a result, the plating layer 36 is formed on the part corresponding to the die pad smooth surface area 11e of the die pad 11 and the part corresponding to the lead smooth surface area 12e of the lead portion 12. The thickness of the plating layer 36 may be more than 0 μm and 2 μm or less. For example, silver may be used as the metal constituting the plating layer 36. When the plating layer 36 is made of silver plating, a silver plating solution containing silver cyanide and potassium cyanide as main components can be used as the plating solution for electrolytic plating.

[0188] Then, the elastic member 46 and the jig 47 are removed. A support layer 37 for supporting the metal substrate 31 is provided on the rear surface side of the metal substrate 31 (FIG. 14(g)). The support layer 37 may be, for example, a resist layer.

[0189] Next, as shown in FIG. 14(h), the portion of the metal substrate 31 that is not covered by the plating layer 36 and the support layer 37 is roughened to form a rough surface in that portion. Specifically, the die pad rough surface region 11f and the lead rough surface region 12f are formed on the metal substrate 31. Furthermore, the first die pad side surface 11c, the second die pad side surface 11d, the inner lead tip surface 51c, and the inner lead back surface 51b are roughened. During this process, a microetching solution is supplied to the metal substrate 31 to form a rough surface on the entire metal substrate 31 except for the portion covered by the plating layer 36 and the support layer 37. Here, the microetching solution is a surface treatment agent that slightly dissolves the metal surface to form a rough surface with fine projections and recesses. For example, when roughening the metal substrate 31 made of copper or a copper alloy, a microetching solution containing hydrogen peroxide and sulfuric acid as main components may be used.

[0190] Next, as shown in FIG. 14(i), the support layer 37 and the plating layer 36 are successively peeled off and removed, thereby obtaining the lead frame 10 shown in FIGS.

[0191] (Method of manufacturing a semiconductor device) Next, a method for manufacturing the semiconductor device 20 shown in Figures 11 and 12 will be described with reference to Figures 15(a)-(d). Figures 15(a)-(d) are cross-sectional views (figures corresponding to Figure 12) showing the method for manufacturing the semiconductor device 20.

[0192] First, the lead frame 10 is produced (FIG. 15(a)) by, for example, the method shown in FIGS. 14(a)-(i).

[0193] Next, the semiconductor element 21 is mounted on the die pad 11 and the lead portion 12 of the lead frame 10. In this case, bumps 26 are formed in advance on the electrodes 21a of the semiconductor element 21, respectively. Next, the bumps 26 are connected and fixed to the die pad 11 and the lead portion 12, respectively (FIG. 15(b)). At this time, the electrodes 21a of the semiconductor element 21 are electrically connected to the die pad 11 and the lead portion 12, respectively, via the bumps 26. The bumps 26 on the die pad 11 are connected to the die pad smooth surface region 11e. At this time, the bumps 26 are provided spaced apart from the die pad rough surface region 11f. Furthermore, the bumps 26 on the lead portion 12 are connected to the lead smooth surface region 12e. At this time, the bumps 26 are provided spaced apart from the lead rough surface region 12f.

[0194] Next, a thermosetting resin or a thermoplastic resin is injection molded or transfer molded onto the lead frame 10 to form a sealing resin 23 (FIG. 15(c)). As a result, the die pad 11, the leads 12, the semiconductor element 21, and the bumps 26 are resin-sealed.

[0195] Thereafter, the lead frame 10 and the sealing resin 23 are cut for each package region 10a. As a result, the lead frame 10 is separated into each semiconductor device 20, and the semiconductor device 20 shown in FIGS. 11 and 12 is obtained (FIG. 15(d)).

[0196] However, during long-term use of the semiconductor device 20 manufactured in this manner, it is possible that moisture in the air and the like may penetrate from the side or back side of the semiconductor device 20 through the interface between the sealing resin 23 and the die pad 11 or the lead portion 12.

[0197] In contrast, according to this embodiment, the die pad rough surface region 11f exists so as to surround the entire periphery of the die pad smooth surface region 11e. Similarly, the lead rough surface region 12f exists so as to surround the entire periphery of the lead smooth surface region 12e. Therefore, outside the bumps 26, the distance of the moisture intrusion path at the interface between the die pad surface 11a or the lead surface 12a and the sealing resin 23 is longer. This makes it possible to prevent moisture from infiltrating into the semiconductor element 21 from the interface between the die pad surface 11a or the lead surface 12a and the sealing resin 23 (arrow F in FIG. 16). A As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

[0198] Furthermore, according to this embodiment, the die pad smooth surface region 11e of the die pad surface 11a adjacent to the outer side of the bump 26 is a smooth surface. Also, the lead smooth surface region 12e of the lead surface 12a adjacent to the outer side of the bump 26 is a smooth surface.

[0199] As a result, when the bumps 26 are made of a single metal layer such as copper (see FIG. 13(a)), the following effect can be obtained. That is, when the semiconductor element 21 is mounted on the die pad 11 and the lead portions 12, the adhesion between the bumps 26 and the die pad 11 and the lead portions 12 can be improved. On the other hand, if the surfaces of the die pad 11 and the lead portions 12 to which the bumps 26 are connected are rough, the contact area between the bumps 26 and the rough surfaces is narrowed due to the effect of an oxide film (e.g., copper oxide) formed on the rough surfaces. In this case, there is a risk that the bonding strength between the bumps 26 and the die pad 11 and the lead portions 12 will be weakened.

[0200] Furthermore, when the bumps 26 contain a metal such as tin (see FIG. 13(b)), the following effect can be obtained. That is, when the semiconductor element 21 is mounted on the die pad 11 and the lead portion 12, the tin or the like contained in the bumps 26 can be prevented from flowing out along the rough surface. On the other hand, if the portion adjacent to the outside of the bumps 26 is rough, there is a risk that the tin or the like contained in the bumps 26 will flow out along the rough surface due to surface tension.

[0201] Furthermore, according to this embodiment, the die pad rough surface region 11f is formed along the entire peripheral edge 11g of the die pad 11 in a plan view. Moreover, the lead rough surface region 12f is formed along the entire peripheral edge 12g of the lead portion 12 in a plan view. This makes it possible to more effectively prevent moisture from penetrating into the semiconductor element 21 from the interface between the die pad surface 11a or the lead surface 12a and the sealing resin 23.

[0202] Furthermore, according to this embodiment, the inner lead back surface 51b and the inner lead tip surface 51c of the lead portion 12 are roughened. In addition, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are each roughened. This increases the distance of the moisture intrusion path at the interface between the sealing resin 23 and the die pad 11 or the lead portion 12. This makes it possible to prevent moisture from infiltrating into the semiconductor element 21 from the interface between the sealing resin 23 and the die pad 11 or the lead portion 12 (arrow F in Figure 16). B As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

[0203] In particular, in a flip-chip type semiconductor device 20, the electrodes 21a of the semiconductor element 21 face the back surface side. Therefore, in a flip-chip type semiconductor device 20, the distance from the back surface of the semiconductor device 20 to the electrodes 21a of the semiconductor element 21 tends to be short. In contrast, according to this embodiment, the thinned portion of the back surface of the lead portion 12 is roughened. This makes it possible to more effectively prevent moisture from penetrating from the interface between the sealing resin 23 and the lead portion 12 to the semiconductor element 21 side.

[0204] Furthermore, according to this embodiment, the inner lead back surface 51b and the inner lead tip surface 51c of the lead portion 12 are roughened. Also, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are roughened. This increases the adhesive strength between the die pad 11 and the lead portion 12 and the sealing resin 23, and can prevent the die pad 11 and the lead portion 12 from peeling off from the sealing resin 23.

[0205] (Modification) Next, modified examples of the die pad smooth surface region 11e and the lead smooth surface region 12e will be described with reference to Fig. 17(a)-(d). Fig. 17(a)-(d) are enlarged plan views showing the die pad smooth surface region 11e and the lead smooth surface region 12e (hereinafter also simply referred to as the smooth surface region 11e and 12e), and the die pad rough surface region 11f and the lead rough surface region 12f (hereinafter also simply referred to as the rough surface region 11f and 12f), respectively.

[0206] As shown in Fig. 17(a), the smooth surface regions 11e and 12e may be square or rectangular in plan view. The width (length of each side) D3 of the smooth surface regions 11e and 12e may be 0.030 mm or more, or 0.035 mm or more. The width D3 may be 0.070 mm or less, or 0.065 mm or less. When the bump 26 is disposed at the center of the smooth surface regions 11e and 12e, the shortest distance d3 between the periphery of the bump 26 and the periphery of the smooth surface regions 11e and 12e may be 0.005 mm or more, or 0.010 mm or more. The shortest distance d3 may be 0.020 mm or less, or 0.015 mm or less. Furthermore, the minimum distance L3 between the smooth surface regions 11e, 12e and the periphery 11g of the die pad 11 or the periphery 12g of the lead portion 12 may be 0.025 mm or more, or 0.030 mm or more. The minimum distance L3 may be 1.0 mm or less, or 0.50 mm or less. Since the smooth surface regions 11e, 12e are square or rectangular in plan view, the minimum distance (spacing) d3 between the periphery of the bump 26 and the periphery of the smooth surface regions 11e, 12e can be sufficiently secured.

[0207] As shown in FIG. 17(b), the smooth surface regions 11e, 12e are square or rectangular in plan view, and multiple bumps 26 may be arranged in one smooth surface region 11e, 12e. The length D4a of the long side of the smooth surface regions 11e, 12e may be 0.045 mm or more, or 0.065 mm or more. The length D4a may be 0.12 mm or less, or 0.10 mm or less. The length D4b of the short side of the smooth surface regions 11e, 12e may be 0.030 mm or more, or 0.035 mm or more. The length D4b may be 0.070 mm or less, or 0.065 mm or less. When each bump 26 is disposed at the center of the short side of the smooth surface regions 11e and 12e, the shortest distance d4 between the periphery of the bump 26 and the periphery of the smooth surface regions 11e and 12e in the short side direction may be 0.005 mm or more, or 0.010 mm or more. The shortest distance d4 may be 0.020 mm or less, or 0.015 mm or less. The shortest distance L4 between the smooth surface regions 11e and 12e and the periphery 11g of the die pad 11 or the periphery 12g of the lead portion 12 may be 0.025 mm or more, or 0.030 mm or more. The shortest distance L4 may be 1.0 mm or less, or 0.50 mm or less. Since the smooth surface regions 11e and 12e are square or rectangular in plan view, the shortest distance (spacing) d4 between the periphery of the bump 26 and the periphery of the smooth surface regions 11e and 12e can be sufficiently secured. Also, two or more adjacent bumps 26 can be provided on each smooth surface region 11e, 12e.

[0208] As shown in Fig. 17(c), the smooth surface regions 11e, 12e are elliptical or oval in plan view, and a plurality of bumps 26 may be arranged on one smooth surface region 11e, 12e. The length D5a in the longitudinal direction of the smooth surface regions 11e, 12e may be 0.045 mm or more, or 0.065 mm or more. The length D5a may be 0.12 mm or less, or 0.10 mm or less. The length D5b in the lateral direction of the smooth surface regions 11e, 12e may be 0.030 mm or more, or 0.035 mm or more. The length D5b may be 0.070 mm or less, or 0.065 mm or less. When each bump 26 is disposed at the center of the short side of the smooth surface regions 11e and 12e, the shortest distance d5 between the periphery of the bump 26 and the periphery of the smooth surface regions 11e and 12e may be 0.005 mm or more, or 0.010 mm or more. The shortest distance d5 may be 0.020 mm or less, or 0.015 mm or less. The shortest distance L5 between the smooth surface regions 11e and 12e and the periphery 11g of the die pad 11 or the periphery 12g of the lead portion 12 may be 0.025 mm or more, or 0.030 mm or more. The shortest distance L5 may be 1.0 mm or less, or 0.50 mm or less. Since the smooth surface regions 11e and 12e are elliptical or oval in plan view, two or more bumps 26 adjacent to each other can be disposed on each smooth surface region 11e and 12e.

[0209] As shown in FIG. 17(d), the periphery of the smooth surface region 11e, 12e may be a closed figure including a curve Cv and a line segment Ls in a plan view. The smooth surface region 11e, 12e may be a figure obtained by removing a part of a circle or an ellipse, for example, a semicircle or a semiellipse. The line segment Ls constituting the periphery of the smooth surface region 11e, 12e may be parallel to the periphery 11g of the die pad 11 or the periphery 12g of the lead portion 12. The length D6a of the smooth surface region 11e, 12e in a direction perpendicular to the line segment Ls may be 0.030 mm or more, or may be 0.050 mm or more. The length D6a may be 0.12 mm or less, or may be 0.10 mm or less. The length D6b of the smooth surface region 11e, 12e in a direction parallel to the line segment Ls may be 0.030 mm or more, or may be 0.035 mm or more. The length D6b may be 0.070 mm or less, or 0.065 mm or less. When each bump 26 is disposed at the center of the smooth surface regions 11e, 12e in the direction parallel to and perpendicular to the line segment Ls, the shortest distance d6 between the periphery of the bump 26 and the periphery of the smooth surface regions 11e, 12e may be 0.005 mm or more, or 0.010 mm or more. The shortest distance d6 may be 0.020 mm or less, or 0.015 mm or less. The shortest distance L6 between the smooth surface regions 11e, 12e and the periphery 11g of the die pad 11 or the periphery 12g of the lead portion 12 may be 0.025 mm or more, or 0.030 mm or more. The shortest distance L6 may be 1.0 mm or less, or 0.50 mm or less. Since the smooth surface regions 11e, 12e are closed figures including the curve Cv and the line segment Ls in a planar view, the shortest distance L6 between the smooth surface regions 11e, 12e and the periphery 11g of the die pad 11 or the periphery 12g of the lead portion 12 can be ensured to be at least a certain distance.

[0210] (Third embodiment) Next, a third embodiment will be described with reference to Figures 18 to 25. Figures 18 to 25 are diagrams showing the third embodiment. In Figures 18 to 25, the same parts as those shown in Figures 8 to 17 are given the same reference numerals and detailed descriptions thereof will be omitted.

[0211] (Lead frame configuration) First, an outline of the lead frame according to this embodiment will be described with reference to Figures 18 and 19. Figures 18 and 19 are diagrams showing the lead frame according to this embodiment.

[0212] In this specification, the term "outer periphery" refers to the part of the lead frame 10 (metal substrate) that is exposed to the outside, and includes the "front surface," "side surface," and "rear surface."

[0213] 18 and 19, each package area 10a of the lead frame 10 includes a die pad 11 and lead portions 12 located around the die pad 11. Of these, the lead portions 12 are partially thinned from the back surface side. Of the back surface of the lead portions 12, the thinned portion is a rough surface. Of the back surface of the lead portions 12, the non-thinned portion is a smooth surface.

[0214] 19, the die pad 11 has a die pad front surface 11a located on the front surface side and a die pad back surface 11b located on the back surface side. In this case, the die pad front surface 11a, the first die pad side surface 11c, and the second die pad side surface 11d of the die pad 11 are each rough surfaces. On the other hand, the die pad back surface 11b of the die pad 11 is a smooth surface.

[0215] As shown in Fig. 19, the lead portion 12 has an inner lead 51 and a terminal portion 53. The inner lead 51 is located on the inside (the die pad 11 side). The terminal portion 53 is located on the outside (the connecting bar 13 side). The inner lead 51 extends from the terminal portion 53 to the die pad 11 side. An internal terminal is formed at the tip portion on the front surface side of the inner lead 51. This internal terminal is an area that is electrically connected to the semiconductor element 21 via a bump 26 as described below.

[0216] The inner lead 51 is thinned from the back surface side by, for example, half etching. The inner lead 51 has an inner lead front surface 51a and an inner lead back surface 51b. The inner lead front surface 51a is located on the front surface side. An internal terminal is formed on a part of the inner lead front surface 51a. An inner lead tip surface 51c is formed on the surface of the inner lead 51 facing the die pad 11. The inner lead back surface 51b is located on the back surface side.

[0217] The inner lead tip surface 51c of the lead portion 12 is roughened over its entirety. Although not shown, both side surfaces along the longitudinal direction of the lead portion 12 may also be roughened. On the other hand, the inner lead 51 of the lead portion 12 is not thinned from the front side. The inner lead surface 51a located on the front side of the inner lead 51 is roughened over its entirety. Furthermore, the terminal portion 53 of the lead portion 12 is not thinned from the front side. The terminal portion surface 53a located on the front side of the terminal portion 53 is roughened over its entirety.

[0218] In addition, the configuration of the lead frame 10 according to this embodiment may be the same as the configuration of the lead frame 10 according to the second embodiment.

[0219] In this embodiment, the definitions and measurement methods of the "rough surface" and "smooth surface" are the same as in the second embodiment.

[0220] (Configuration of the Semiconductor Device) Next, the semiconductor device according to the present embodiment will be described with reference to Figures 20 to 22. Figures 20 to 22 are diagrams showing the semiconductor device (flip chip type) according to the present embodiment.

[0221] As shown in FIGS. 20 and 21, a semiconductor device (semiconductor package) 20 includes a die pad 11, a semiconductor element 21, a plurality of leads 12, a plurality of bumps 26, and a sealing resin 23.

[0222] Of these, the semiconductor element 21 is mounted on the die pad 11. Furthermore, the multiple lead portions 12 are arranged around the die pad 11. The multiple bumps 26 electrically connect the semiconductor element 21 to the die pad 11 or the lead portions 12, respectively. In this case, the bumps 26 form the connection portions. Furthermore, the bumps 26 may be pillars. The sealing resin 23 resin-seals the die pad 11, the lead portions 12, the semiconductor element 21, and the bumps 26.

[0223] Bumps 26 are provided on the die pad 11 and the lead portions 12. Through the bumps 26, the semiconductor element 21, the die pad 11, and the lead portions 12 are electrically connected to one another.

[0224] The bumps (connecting portions) 26 are made of a metal material with good conductivity, such as copper, and may have a solid, generally cylindrical or generally spherical shape. The upper ends of the bumps 26 are connected to the electrodes 21a of the semiconductor element 21, and the lower ends are connected to the die pad 11 and the lead portions 12, respectively. Note that the bumps 26 do not necessarily have to be provided on the die pad 11. In this case, the die pad 11 and the semiconductor element 21 may be fixed to each other by an adhesive, such as die bonding paste.

[0225] FIG. 22 is an enlarged cross-sectional view showing the periphery of the bump 26. As shown in FIG. 22, the bump 26 may include multiple layers. For example, the bump 26 includes a first layer 26a located on the die pad 11 or lead portion 12 side, and a second layer 26b located on the semiconductor element 21 side. The first layer 26a may include a metal such as tin. The height of the first layer 26a may be 1 μm or more and 10 μm or less. The second layer 26b may include a metal such as copper. The height of the second layer 26b may be 30 μm or more and 100 μm or less.

[0226] The semiconductor device 20 is not limited to a flip chip type. For example, a bonding wire may be used as the connection portion instead of the bump 26. In this case, the bonding wire may electrically connect the semiconductor element 21 and the lead portion 12 to each other.

[0227] In addition, the configuration of the semiconductor device 20 according to the present embodiment may be the same as the configuration of the semiconductor device 20 according to the second embodiment.

[0228] (Lead frame manufacturing method) Next, a method for manufacturing the lead frame 10 shown in Figures 18 and 19 will be described with reference to Figures 23(a)-(i). Figures 23(a)-(i) are cross-sectional views (figures corresponding to Figure 19) showing the method for manufacturing the lead frame 10.

[0229] First, in the same manner as in the second embodiment (FIGS. 14(a)-(e)), a metal substrate 31 having a die pad 11 and lead portions 12 positioned around the die pad 11 is fabricated (FIGS. 23(a)-(e)).

[0230] Next, a plating layer 36 is formed on a part of the outer periphery of the metal substrate 31 (FIG. 23(f)). At this time, the plating layer 36 is formed on the outer periphery of the metal substrate 31 except for the entire surface. That is, the plating layer 36 is not formed on the entire surface of the metal substrate 31, but is formed on the entire back surface and side surface of the metal substrate 31. More specifically, the plating layer 36 is not formed on the die pad surface 11a of the die pad 11, the inner lead surface 51a of the lead portion 12, and the terminal portion surface 53a. On the other hand, the plating layer 36 is formed on the die pad back surface 11b, the first die pad side surface 11c, and the second die pad side surface 11d of the die pad 11. The plating layer 36 is also formed on the external terminal 17, the inner lead back surface 51b, and the inner lead tip surface 51c of the lead portion 12. The plating layer 36 does not have to be formed on the surface of the connecting bar 13. The plating layer 36 may be formed on the back surface of the connecting bar 13.

[0231] At this time, as shown in FIG. 23(f), the entire surface of the metal substrate 31 is covered with a first jig 45 via an elastic member 44 such as a rubber packing. In this state, electrolytic plating is performed on the metal substrate 31, so that a plating layer 36 is formed on the metal substrate 31 except for the entire surface. The thickness of the plating layer 36 may be more than 0 μm and 2 μm or less. For example, silver may be used as a metal constituting the plating layer 36. When the plating layer 36 is made of silver plating, a silver plating solution containing silver cyanide and potassium cyanide as main components can be used as a plating solution for electrolytic plating. In this way, the plating layer 36 is not formed on the entire surface of the metal substrate 31, so that the amount of metal such as silver constituting the plating layer 36 can be reduced. This reduces the manufacturing cost of the lead frame 10.

[0232] Next, a portion of the plating layer 36 present in the region forming the rough surface is removed. Specifically, the plating layer 36 present on at least the back surface of the metal substrate 31 is left, and the other plating layer 36 is removed (FIG. 23(g)). Specifically, of the plating layer 36, the portion present on the side surface of the metal substrate 31 is removed. This removes the plating layer 36 on the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11. Also, the plating layer 36 on the inner lead tip surface 51c and the inner lead back surface 51b of the lead portion 12 is removed.

[0233] 23(g), an elastic member 46 such as a rubber packing is first placed on the back surface of the metal substrate 31, and a second jig 47A is placed on the back surface side of the metal substrate 31 via the elastic member 46. Next, the plating layer 36 in the portion not covered by the elastic member 46 is peeled off and removed. This exposes the first die pad side surface 11c, the second die pad side surface 11d, the inner lead tip surface 51c, and the inner lead back surface 51b. Meanwhile, the plating layer 36 on the die pad back surface 11b and the external terminals 17 covered with the elastic member 46 remains.

[0234] Next, as shown in FIG. 23(h), a support layer 37 for supporting the metal substrate 31 is provided on the back side of the metal substrate 31. The support layer 37 may be, for example, a resist layer. Next, as shown in FIG. 23(h), the portion of the metal substrate 31 that is not covered by the plating layer 36 is roughened to form a rough surface on the portion that is not covered by the plating layer 36. Specifically, the die pad surface 11a, the first die pad side surface 11c, the second die pad side surface 11d, the inner lead surface 51a, the terminal portion surface 53a, the inner lead tip surface 51c, and the inner lead back surface 51b are each roughened. During this process, a microetching solution is supplied to the metal substrate 31 to form a rough surface on the entire metal substrate 31 except for the portion that is covered by the plating layer 36. Here, the microetching solution is a surface treatment agent that slightly dissolves the metal surface to form a rough surface with fine irregularities. For example, when roughening the metal substrate 31 made of copper or a copper alloy, a microetching solution containing hydrogen peroxide and sulfuric acid as main components may be used.

[0235] Next, as shown in FIG. 23(i), the support layer 37 and the plating layer 36 are successively peeled off and removed, thereby obtaining the lead frame 10 shown in FIGS.

[0236] 24(a)-(d), the method for manufacturing the semiconductor device 20 according to this embodiment can be performed in substantially the same manner as the method for manufacturing the semiconductor device 20 according to the second embodiment. In this case, each electrode 21a of the semiconductor element 21 is electrically connected to the die pad 11 and the lead portion 12 via the bump 26.

[0237] Thus, according to this embodiment, a plating layer 36 is formed on the metal substrate 31 in an area excluding the front surface (FIG. 24(f)). Next, the plating layer 36 present on the rear surface of the metal substrate 31 is left, and the remaining plating layer 36 is removed (FIG. 24(g)). Thereafter, a rough surface is formed on the portion of the metal substrate 31 that is not covered by the plating layer 36 (FIG. 24(h)). In this manner, the plating layer 36 for forming the rough surface is not provided on the entire surface of the metal substrate 31, but is provided on the area of ​​the metal substrate 31 excluding the front surface. This makes it possible to reduce the amount of metal, such as silver, used in the plating layer 36. As a result, the manufacturing cost of the lead frame 10 can be reduced.

[0238] During long-term use of the semiconductor device 20 thus manufactured, moisture in the air may infiltrate from the back surface side of the semiconductor device 20 through the interface between the sealing resin 23 and the die pad 11 or the lead portion 12. In contrast, according to this embodiment, the inner lead back surface 51b and the inner lead tip surface 51c of the lead portion 12 are roughened. In addition, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are each roughened. This increases the distance of the moisture infiltration path at the interface between the sealing resin 23 and the die pad 11 or the lead portion 12. This makes it possible to prevent moisture from infiltrating into the semiconductor element 21 side from the interface between the sealing resin 23 and the die pad 11 or the lead portion 12 (arrow F in Figure 25). A As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

[0239] (Fourth embodiment) Next, a fourth embodiment will be described with reference to Figures 26 to 29. Figures 26 to 29 are diagrams showing the fourth embodiment. The fourth embodiment shown in Figures 26 to 29 is different from the third embodiment in that a metal layer 25 is provided on the surfaces of the die pad 11 and the lead portion 12, and other configurations are substantially the same as those of the third embodiment described above. In Figures 26 to 29, the same parts as those in the second embodiment shown in Figures 8 to 17 and the third embodiment shown in Figures 18 to 25 are denoted by the same reference numerals and detailed description thereof will be omitted.

[0240] (Structure of lead frame and semiconductor device) FIG. 26 is a cross-sectional view showing a lead frame 10A according to the present embodiment, and FIG. 27 is a cross-sectional view showing a semiconductor device 20A according to the present embodiment.

[0241] In the lead frame 10A shown in Fig. 26 and the semiconductor device 20A shown in Fig. 27, a metal layer 25 is located on a part of the die pad 11 and a part of the lead portion 12. Specifically, a plurality of metal layers 25 for improving adhesion with the bumps 26 are provided on the die pad surface 11a of the die pad 11. In addition, a metal layer 25 for improving adhesion with the bumps 26 is provided on an internal terminal formed on an inner lead 51 of the lead portion 12.

[0242] The metal layer 25 is intended to improve the connection between the bump 26 and the die pad 11 and the lead portion 12. The metal layer 25 may be a plating layer formed by, for example, an electrolytic plating method. The thickness of the metal layer 25 may be 1 μm or more and 10 μm or less. Metals constituting such a plating layer may include silver, silver alloys, gold, gold alloys, platinum group metals, copper, copper alloys, palladium, and the like. When underplating is required due to the metal constituting the metal layer 25, known metals such as nickel and copper may be used.

[0243] As shown in Figures 26 and 27, the surface of the lead portion 12 has a first surface portion 56a which is a smooth surface and a second surface portion 56b which is a rough surface. The first surface portion 56a is located at the inner end (on the die pad 11 side) of the lead portion 12. A metal layer 25 is formed on the first surface portion 56a. The entire first surface portion 56a is a smooth surface. The first surface portion 56a is located on a part of the inner lead surface 51a.

[0244] The second surface portion 56b is adjacent to the first surface portion 56a and the outside of the metal layer 25 (the side opposite to the die pad 11). The second surface portion 56b is in direct contact with the first surface portion 56a and the metal layer 25. The second surface portion 56b has a rough surface in its entirety. In the lead frame 10A, the second surface portion 56b preferably extends continuously to the connection portion between the lead portion 12 and the connecting bar 13. The surface of the connecting bar 13 may also have a rough surface. The second surface portion 56b is located on a part of the inner lead surface 51a and a part of the terminal portion surface 53a.

[0245] 27, in the semiconductor device 20A, the bumps 26 are provided on a metal layer 25. The upper ends of the bumps 26 are connected to the electrodes 21a of the semiconductor element 21, and the lower ends are connected to the die pad 11 and the lead portions 12 via the metal layer 25. Note that the metal layer 25 and the bumps 26 do not necessarily have to be provided on the die pad 11.

[0246] In this embodiment, the definitions and measurement methods of the "rough surface" and "smooth surface" are the same as in the second embodiment.

[0247] (Lead frame manufacturing method) Next, a method for manufacturing the lead frame 10A shown in Fig. 26 will be described with reference to Fig. 28(a)-(j). In Fig. 28(a)-(j), the same parts as those shown in Fig. 23(a)-(i) are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0248] First, in the same manner as in the second embodiment (FIGS. 14(a)-(e)), a metal substrate 31 having a die pad 11 and lead portions 12 positioned around the die pad 11 is fabricated (FIGS. 28(a)-(e)).

[0249] Next, the plating layer 36 is formed on the metal substrate 31 except for a part of the surface (FIG. 28(f)). At this time, the plating layer 36 is formed on a part of the surface, the entire back surface, and the entire side surface of the metal substrate 31. The plating layer 36 is also formed on a part of the surface of the die pad 11 and a part of the surface of the lead portion 12. More specifically, the plating layer 36 is formed on the area of ​​the die pad surface 11a of the die pad 11 where the metal layer 25 is to be formed, and is not formed in any area other than the area where the metal layer 25 is to be formed. The plating layer 36 is also formed on the die pad back surface 11b, the first die pad side surface 11c, and the second die pad side surface 11d of the die pad 11. The plating layer 36 is also formed on the first surface portion 56a, the external terminal 17, the inner lead back surface 51b, and the inner lead tip surface 51c of the lead portion 12. On the other hand, the plating layer 36 is not formed on the second surface portion 56b of the lead portion 12. The plating layer 36 does not have to be formed on the front surface of the connecting bar 13, and may be formed on the back surface of the connecting bar 13.

[0250] At this time, as shown in FIG. 28(f), a part of the surface of the metal substrate 31 is covered with a first jig 45A via an elastic member 44A such as a rubber packing. In this state, electrolytic plating is performed on the metal substrate 31, so that a plating layer 36 is formed on the metal substrate 31 except for a part of the surface. By not forming the plating layer 36 on a part of the surface of the metal substrate 31 in this way, the amount of metal such as silver used to form the plating layer 36 can be reduced. This reduces the manufacturing cost of the lead frame 10A. The material and thickness of the plating layer 36 can be the same as those in the third embodiment.

[0251] Next, a portion of the plating layer 36 present in the region that will form the rough surface is removed (FIG. 28(g)). At this time, the plating layer 36 present on a portion of the front surface and rear surface of the metal substrate 31 is left, and the other plating layer 36 is removed. Specifically, of the plating layer 36, the portions corresponding to the first die pad side surface 11c, the second die pad side surface 11d, the inner lead tip surface 51c, and the inner lead rear surface 51b of the metal substrate 31 are removed.

[0252] During this process, as shown in FIG. 28(g), elastic members 46 are placed on the front and back surfaces of the metal substrate 31, and the metal substrate 31 is sandwiched by a second jig 47B via the elastic members 46, such as rubber packing. The elastic member 46 on the front surface side of the metal substrate 31 covers the entire front surface side of the metal substrate 31. Next, the plating layer 36 in the portion not covered by the elastic member 46 is peeled off and removed. This exposes the first die pad side surface 11c, the second die pad side surface 11d, the inner lead tip surface 51c, and the inner lead back surface 51b. Meanwhile, the die pad front surface 11a, the die pad back surface 11b, the first surface portion 56a, and the plating layer 36 on the external terminals 17, which are covered with the elastic member 46, remain.

[0253] 23(h), a support layer 37 is provided on the back surface side of the metal substrate 31. Next, the portion of the metal substrate 31 that is not covered with the plating layer 36 is roughened to form a rough surface in the portion that is not covered with the plating layer 36 (FIG. 28(h)). As a result, the first die pad side surface 11c, the second die pad side surface 11d, the second surface portion 56b, the inner lead tip surface 51c, and the inner lead back surface 51b are roughened.

[0254] Next, in substantially the same manner as the step shown in FIG. 23(i), the support layer 37 and the plating layer 36 are peeled off and removed in this order (FIG. 28(i)).

[0255] Thereafter, as shown in Fig. 28(j), a metal layer 25 is formed on a part of the surface of the metal substrate 31. Specifically, the metal layer 25 is formed on a part of the die pad 11 and a part of the lead portion 12. In this case, a plating resist layer having a predetermined pattern (not shown) is first formed on the die pad 11 and the lead portion 12 by, for example, a photolithography method. Next, the metal layer 25 made of a plating layer is formed by, for example, an electrolytic plating method in the places not covered by this plating resist layer. Thereafter, the plating resist layer is removed to obtain the lead frame 10A shown in Fig. 26.

[0256] (Method of Manufacturing Semiconductor Device) The method of manufacturing the semiconductor device 20A according to this embodiment can be performed in substantially the same manner as the method of manufacturing the semiconductor device 20 shown in Figures 24(a)-(d). In this case, each electrode 21a of the semiconductor element 21 is electrically connected to the die pad 11 and the lead portion 12 via the bump 26 and the metal layer 25, respectively.

[0257] Thus, according to this embodiment, the plating layer 36 is formed on the metal substrate 31 in an area excluding a portion of the surface (FIG. 28(f)). Next, the plating layer 36 present on a portion of the surface and the back surface of the metal substrate 31 is left, and the remaining plating layer 36 is removed (FIG. 28(g)). Thereafter, a rough surface is formed on the portion of the metal substrate 31 that is not covered by the plating layer 36 (FIG. 28(h)). In this way, the plating layer 36 for forming the rough surface is not provided on the entire surface of the metal substrate 31, but is provided on the metal substrate 31 in an area excluding a portion of the surface. This makes it possible to reduce the amount of metal, such as silver, used to form the plating layer 36. As a result, the manufacturing cost of the lead frame 10 can be reduced.

[0258] Furthermore, according to this embodiment, the second surface portion 56b adjacent to the outside of the metal layer 25 is roughened. This increases the distance of the path through which moisture can penetrate at the interface between the surface of the lead portion 12 and the sealing resin 23. This makes it possible to prevent moisture from penetrating into the semiconductor element 21 from the interface between the surface of the lead portion 12 and the sealing resin 23 (arrow F in FIG. 29). B As a result, the reliability of the semiconductor device 20A after long-term use can be improved.

[0259] Furthermore, according to this embodiment, the second surface portion 56b of the lead portion 12 is roughened. This increases the adhesive strength between the second surface portion 56b and the sealing resin 23, and prevents the surface of the lead portion 12 and the sealing resin 23 from peeling off from each other.

[0260] Furthermore, according to this embodiment, on the back surface side of the semiconductor device 20A, the length of the path through which moisture penetrates is increased at the interface between the sealing resin 23 and the die pad 11 or the lead portion 12. This makes it possible to prevent moisture from penetrating into the semiconductor element 21 from the interface between the sealing resin 23 and the die pad 11 or the lead portion 12 (arrow F in FIG. 29). A As a result, the reliability of the semiconductor device 20A after long-term use can be improved.

[0261] Fifth embodiment The fifth embodiment will be described with reference to Figures 30 to 37. Figures 30 to 37 are diagrams showing the fifth embodiment. In Figures 30 to 37, the same parts as those in the embodiment shown in Figures 8 to 29 are given the same reference numerals and detailed descriptions thereof will be omitted.

[0262] (Lead frame configuration) First, an outline of the lead frame according to this embodiment will be described with reference to Figures 30 and 31. Figures 30 and 31 are diagrams showing the lead frame according to this embodiment.

[0263] In this specification, the term "outer periphery" refers to the part of the lead frame 10 (metal substrate) that is exposed to the outside, and includes the "front surface," "side surface," and "rear surface."

[0264] As shown in Figures 30 and 31, each package area 10a of the lead frame 10 includes a die pad 11 and lead portions 12 located around the die pad 11. Of these, the lead portions 12 are partially thinned from the back surface side. Of the back surface of the lead portions 12, the thinned portion is a rough surface. Of the back surface of the lead portions 12, the non-thinned portion is a smooth surface.

[0265] As shown in FIG. 31, the die pad 11 has a die pad front surface 11a located on the front surface side and a die pad back surface 11b located on the back surface side. A semiconductor element 21 is mounted on the die pad front surface 11a as described later. The die pad back surface 11b is exposed to the outside from a semiconductor device 20 (described later). In addition, a first die pad side surface 11c and a second die pad side surface 11d are formed on the side of the die pad 11 facing the lead portion 12. The first die pad side surface 11c is located on the die pad front surface 11a side. The second die pad side surface 11d is located on the die pad back surface 11b side. In this case, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are each rough surfaces. On the other hand, the die pad front surface 11a and the die pad back surface 11b of the die pad 11 are each smooth surfaces.

[0266] In this embodiment, the definitions and measurement methods of the "rough surface" and "smooth surface" are the same as in the second embodiment.

[0267] The rough surface may be formed by roughening the outer surface of metal substrate 31 (described later) with, for example, a microetching solution containing hydrogen peroxide and sulfuric acid as main components. The smooth surface may be an unprocessed surface of metal substrate 31 (described later) that is not subjected to such roughening treatment. In Fig. 31, the roughened portion is indicated by a thick dashed line (the same applies to other cross-sectional views).

[0268] As shown in FIG. 31, the lead portion 12 has an inner lead 51 and a terminal portion 53. The inner lead 51 is located on the inside (the die pad 11 side). The terminal portion 53 is located on the outside (the connecting bar 13 side). The inner lead 51 extends from the terminal portion 53 to the die pad 11 side. An internal terminal is formed at the tip portion on the front surface side of the inner lead 51. This internal terminal is an area that is electrically connected to the semiconductor element 21 via the bump 26 as described below. A metal layer 25 is provided on the internal terminal to improve adhesion to the bump 26.

[0269] The inner lead 51 is thinned from the back surface side by, for example, half etching. The inner lead 51 has an inner lead front surface 51a and an inner lead back surface 51b. The inner lead front surface 51a is located on the front surface side. An internal terminal is formed on a part of the inner lead front surface 51a. An inner lead tip surface 51c is formed on the surface of the inner lead 51 facing the die pad 11. The inner lead back surface 51b is located on the back surface side.

[0270] Furthermore, the entire inner lead tip surface 51c of the lead portion 12 is roughened. Although not shown, both side surfaces along the longitudinal direction of the lead portion 12 may also be roughened. On the other hand, the inner lead 51 of the lead portion 12 is not thinned from the front side. The inner lead surface 51a located on the front side of the inner lead 51 is a smooth surface over its entire area. Furthermore, the terminal portion 53 of the lead portion 12 is not thinned from the front side. The terminal portion surface 53a located on the front side of the terminal portion 53 is a smooth surface over its entire area.

[0271] As shown in FIG. 31, a metal layer 25 is located on the die pad 11 and the lead portion 12. The metal layer 25 is formed on a part of the die pad 11 and a part of the lead portion 12. The metal layer 25 is intended to improve the connection between the bump 26 and the die pad 11 and the lead portion 12. The metal layer 25 may be a plating layer formed by, for example, an electrolytic plating method. The thickness of the metal layer 25 may be 1 μm or more and 10 μm or less. Metals constituting such a plating layer may include silver, silver alloys, gold, gold alloys, platinum group metals, copper, copper alloys, palladium, and the like. When underplating is required due to the metal constituting the metal layer 25, known metals such as nickel and copper may be used.

[0272] In addition, the configuration of the lead frame 10 according to this embodiment may be the same as the configuration of the lead frame 10 according to the second embodiment.

[0273] (Configuration of Semiconductor Device) Next, the semiconductor device according to the present embodiment will be described with reference to Figures 32 to 34. Figures 32 to 34 are diagrams showing the semiconductor device (flip chip type) according to the present embodiment.

[0274] As shown in FIGS. 32 and 33, a semiconductor device (semiconductor package) 20 includes a die pad 11, a semiconductor element 21, a plurality of leads 12, a plurality of bumps 26, and a sealing resin 23.

[0275] Of these, the semiconductor element 21 is mounted on a die pad 11. Furthermore, a plurality of lead portions 12 are arranged around the die pad 11. Furthermore, a metal layer 25 is formed on each of the die pad 11 and the lead portions 12. A bump 26 is provided on the metal layer 25. Through this bump 26, the semiconductor element 21, the die pad 11, and the lead portions 12 are electrically connected to one another.

[0276] One side of the sealing resin 23 (one side of the semiconductor device 20) may be, for example, not less than 0.2 mm and not more than 16 mm.

[0277] The bumps (connecting portions) 26 are made of a metal material with good conductivity such as copper, and may have a solid, generally cylindrical or generally spherical shape. The upper ends of the bumps 26 are connected to the electrodes 21a of the semiconductor element 21, and the lower ends are connected to the die pad 11 and the lead portions 12 via the metal layer 25. The die pad 11 does not necessarily have to be provided with the metal layer 25 and the bumps 26. In this case, the die pad 11 and the semiconductor element 21 may be fixed to each other by an adhesive such as die bonding paste.

[0278] Fig. 34 is an enlarged cross-sectional view showing the periphery of the bump 26. As shown in Fig. 34, the bump 26 may include multiple layers. For example, the bump 26 includes a first layer 26a located on the metal layer 25 side and a second layer 26b located on the semiconductor element 21 side. The first layer 26a may include a metal such as tin. The height of the first layer 26a may be 1 µm or more and 10 µm or less. The second layer 26b may include a metal such as copper. The height of the second layer 26b may be 30 µm or more and 100 µm or less.

[0279] Besides this, the configurations of the die pad 11 and the lead portions 12 are similar to those shown in the above-mentioned FIGS. 30 and 31, except for the areas not included in the semiconductor device 20, and therefore a detailed description thereof will be omitted here.

[0280] The semiconductor device 20 is not limited to a flip chip type. For example, a bonding wire may be used as the connection portion instead of the bump 26. In this case, the bonding wire may electrically connect the semiconductor element 21 and the lead portion 12 to each other.

[0281] In addition, the configuration of the semiconductor device 20 according to the present embodiment may be the same as the configuration of the semiconductor device 20 according to the second embodiment.

[0282] (Lead frame manufacturing method) Next, a method for manufacturing the lead frame 10 shown in Figures 30 and 31 will be described with reference to Figures 35(a)-(j). Figures 35(a)-(j) are cross-sectional views (figures corresponding to Figure 31) showing the method for manufacturing the lead frame 10.

[0283] First, in the same manner as in the second embodiment (FIGS. 14(a)-(e)), a metal substrate 31 having a die pad 11 and lead portions 12 positioned around the die pad 11 is fabricated (FIGS. 35(a)-(e)).

[0284] Next, a plating layer 36 is formed around the metal substrate 31 (FIG. 35(f)). At this time, the plating layer 36 is formed around the entire circumference of the die pad 11, the lead portion 12, and the connecting bar 13. The thickness of the plating layer 36 may be more than 0 μm and not more than 2 μm. The metal constituting the plating layer 36 may be, for example, silver. When the plating layer 36 is made of silver plating, a silver plating solution containing silver cyanide and potassium cyanide as main components can be used as the plating solution for electrolytic plating.

[0285] Next, a part of the plating layer 36 present in the region forming the rough surface is removed. Specifically, the part of the plating layer 36 located other than the front and back surfaces of the metal substrate 31 is removed (FIG. 35(g)). As a result, the plating layer 36 on the first die pad side surface 11c of the die pad 11, the second die pad side surface 11d of the die pad 11, the inner lead tip surface 51c of the lead portion 12, and the inner lead back surface 51b of the lead portion 12 is removed.

[0286] During this process, as shown in Fig. 35(g), elastic members 46 such as rubber packings are placed on the front and back surfaces of the metal substrate 31, and the metal substrate 31 is sandwiched between the elastic members 46 and a jig 47C. Next, the plating layer 36 in the portion not covered by the elastic members 46 is peeled off and removed. This exposes the first die pad side surface 11c, the second die pad side surface 11d, the inner lead tip surface 51c, and the inner lead back surface 51b. Meanwhile, the plating layer 36 on the die pad front surface 11a, the terminal portion front surface 53a, the die pad back surface 11b, the inner lead front surface 51a, and the external terminals 17, which are covered with the elastic members 46, remain.

[0287] Next, as shown in FIG. 35(h), a support layer 37 for supporting the metal substrate 31 is provided on the back side of the metal substrate 31. The support layer 37 may be, for example, a resist layer. Next, as shown in FIG. 35(h), the portion of the metal substrate 31 that is not covered by the plating layer 36 is roughened to form a rough surface on the portion that is not covered by the plating layer 36. Specifically, the first die pad side surface 11c, the second die pad side surface 11d, the inner lead tip surface 51c, and the inner lead back surface 51b are roughened. During this process, a microetching solution is supplied to the metal substrate 31 to form a rough surface on the entire metal substrate 31 except for the portion that is covered by the plating layer 36. Here, the microetching solution is a surface treatment agent that slightly dissolves the metal surface to form a rough surface with fine projections and recesses. For example, when roughening the metal substrate 31 made of copper or a copper alloy, a microetching solution containing hydrogen peroxide and sulfuric acid as main components may be used.

[0288] Next, as shown in FIG. 35(i), the support layer 37 and the plating layer 36 are peeled off and removed in that order.

[0289] Thereafter, as shown in Fig. 35(j), a metal layer 25 is formed on the die pad 11 and the lead portion 12. In this case, a plating resist layer having a predetermined pattern (not shown) is first formed on the die pad 11 and the lead portion 12 by, for example, photolithography. Next, a metal layer 25 made of a plating layer is formed by, for example, electrolytic plating in the areas not covered by this plating resist layer. Thereafter, the plating resist layer is removed to obtain the lead frame 10 shown in Figs. 30 and 31.

[0290] 36(a)-(d), the method for manufacturing the semiconductor device 20 according to this embodiment can be performed in substantially the same manner as the method for manufacturing the semiconductor device 20 according to the second embodiment. In this case, the electrodes 21a of the semiconductor element 21 are electrically connected to the die pad 11 and the leads 12 via the bumps 26 and the metal layer 25, respectively.

[0291] During long-term use of the semiconductor device 20 thus manufactured, moisture in the air may infiltrate from the back surface side of the semiconductor device 20 through the interface between the sealing resin 23 and the die pad 11 or the lead portion 12. In contrast, according to this embodiment, the inner lead back surface 51b and the inner lead tip surface 51c of the lead portion 12 are roughened. In addition, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are each roughened. This increases the distance of the moisture infiltration path at the interface between the sealing resin 23 and the die pad 11 or the lead portion 12. This makes it possible to prevent moisture from infiltrating into the semiconductor element 21 side from the interface between the sealing resin 23 and the die pad 11 or the lead portion 12 (arrow F in Figure 37). A As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

[0292] In particular, in a flip-chip type semiconductor device 20, the electrodes 21a of the semiconductor element 21 face the back surface side. Therefore, in a flip-chip type semiconductor device 20, the distance from the back surface of the semiconductor device 20 to the electrodes 21a of the semiconductor element 21 tends to be short. In contrast, according to this embodiment, the thinned portion of the back surface of the lead portion 12 is roughened. This makes it possible to more effectively prevent moisture from penetrating from the interface between the sealing resin 23 and the lead portion 12 to the semiconductor element 21 side.

[0293] Furthermore, according to this embodiment, the inner lead back surface 51b and the inner lead tip surface 51c of the lead portion 12 are roughened. Also, the first die pad side surface 11c and the second die pad side surface 11d of the die pad 11 are roughened. This increases the adhesive strength between the die pad 11 and the lead portion 12 and the sealing resin 23, and can prevent the die pad 11 and the lead portion 12 from peeling off from the sealing resin 23.

[0294] Sixth embodiment Next, a sixth embodiment will be described with reference to Figures 38 to 41. Figures 38 to 41 are diagrams showing the sixth embodiment. The sixth embodiment shown in Figures 38 to 41 differs mainly in that a rough surface is formed on the surface of the lead portion 12, and other configurations are substantially the same as the fifth embodiment described above. In Figures 38 to 41, the same parts as those in the embodiment shown in Figures 8 to 37 are given the same reference numerals and detailed description will be omitted.

[0295] (Structure of lead frame and semiconductor device) FIG. 38 is a cross-sectional view showing a lead frame 10A according to the present embodiment, and FIG. 39 is a cross-sectional view showing a semiconductor device 20A according to the present embodiment.

[0296] In the lead frame 10A shown in FIG. 38 and the semiconductor device 20A shown in FIG. 39, the surface of the lead portion 12 has a first surface portion 54a which is a smooth surface and a second surface portion 54b which is a rough surface.

[0297] The first surface portion 54a is adjacent to the outer side of the metal layer 25 (the side opposite to the die pad 11). The first surface portion 54a is in direct contact with the metal layer 25. The entire first surface portion 54a is a smooth surface. The length L of the first surface portion 54a along the longitudinal direction of the lead portion 12 (length in the X direction) A The thickness may be 25 μm or more and 200 μm or less, and preferably 50 μm or more and 100 μm or less. The first surface portion 54a is located on a part of the inner lead surface 51a, but is not limited to this. The first surface portion 54a may be located on, for example, a part of the inner lead surface 51a and a part of the terminal portion surface 53a.

[0298] The second surface portion 54b is adjacent to the outside of the first surface portion 54a. That is, the second surface portion 54b is in direct contact with the first surface portion 54a. The second surface portion 54b has a rough surface in its entirety. In the lead frame 10A, the second surface portion 54b preferably extends continuously to the connection portion between the lead portion 12 and the connecting bar 13. The surface of the connecting bar 13 may also have a rough surface. The second surface portion 54b is located on a part of the inner lead surface 51a and a part of the terminal portion surface 53a, but is not limited to this. The second surface portion 54b may be located on a part of the terminal portion surface 53a.

[0299] In this embodiment, the definitions and measurement methods of the "rough surface" and "smooth surface" are the same as in the second embodiment.

[0300] (Lead frame manufacturing method) Next, a method for manufacturing the lead frame 10A shown in Fig. 38 will be described with reference to Fig. 40(a)-(j). In Fig. 40(a)-(j), the same parts as those shown in Fig. 35(a)-(j) are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0301] First, in the same manner as in the second embodiment (FIGS. 14(a)-(e)), a metal substrate 31 having a die pad 11 and lead portions 12 positioned around the die pad 11 is fabricated (FIGS. 40(a)-(e)).

[0302] Next, in substantially the same manner as the step shown in FIG. 35(f) described above, a plating layer 36 is formed all over the periphery of the metal substrate 31 (FIG. 40(f)).

[0303] Next, the portions of the plating layer 36 corresponding to the first die pad side surface 11c, the second die pad side surface 11d, the second surface portion 54b, the inner lead tip surface 51c, and the inner lead back surface 51b of the metal substrate 31 are removed (Figure 40(g)).

[0304] During this process, as shown in FIG. 40(g), elastic members 46 such as rubber packings are placed on the front and back surfaces of the metal substrate 31, and the metal substrate 31 is sandwiched between the jig 47D via the elastic members 46. The elastic member 46 on the front surface side of the metal substrate 31 covers the die pad front surface 11a, the area corresponding to the first surface portion 54a, and the area where the metal layer 25 of the lead portion 12 is provided. Next, the plating layer 36 in the portion not covered by the elastic member 46 is peeled off and removed. This exposes the first die pad side surface 11c, the second die pad side surface 11d, the second surface portion 54b, the inner lead tip surface 51c, and the inner lead back surface 51b. Meanwhile, the plating layer 36 on the die pad front surface 11a, the die pad back surface 11b, the first surface portion 54a, and the external terminals 17 covered with the elastic member 46 remains.

[0305] 35(h), a support layer 37 is provided on the back surface side of the metal substrate 31. Next, the portion of the metal substrate 31 that is not covered with the plating layer 36 is roughened to form a rough surface in the portion that is not covered with the plating layer 36 (FIG. 40(h)). As a result, the first die pad side surface 11c, the second die pad side surface 11d, the second surface portion 54b, the inner lead tip surface 51c, and the inner lead back surface 51b are roughened.

[0306] Next, in substantially the same manner as the step shown in FIG. 35(i), the support layer 37 and the plating layer 36 are peeled off and removed in this order (FIG. 40(i)).

[0307] Thereafter, in substantially the same manner as in the step shown in Fig. 35(j) described above, a metal layer 25 is formed on the die pad 11 and the leads 12. In this manner, the lead frame 10A shown in Fig. 38 is obtained (Fig. 40(j)).

[0308] (Method of manufacturing a semiconductor device) The semiconductor device 20A according to the present embodiment can be manufactured in a manner substantially similar to the method for manufacturing the semiconductor device 20 shown in FIGS.

[0309] According to this embodiment, the first surface portion 54a of the surface of the lead portion 12 adjacent to the outer side of the metal layer 25 is a smooth surface. This makes it possible to prevent tin and the like contained in the bumps 26 from flowing out along the first surface portion 54a when the semiconductor element 21 is mounted on the die pad 11 (arrow F in FIG. 41). C On the other hand, if the first surface portion 54a is rough, there is a risk that the tin and the like contained in the bump 26 will flow out along the first surface portion 54a due to surface tension.

[0310] Furthermore, according to this embodiment, the second surface portion 54b adjacent to the outside of the first surface portion 54a is roughened. This increases the distance of the path through which moisture can penetrate at the interface between the surface of the lead portion 12 and the sealing resin 23. This makes it possible to prevent moisture from penetrating into the semiconductor element 21 from the interface between the surface of the lead portion 12 and the sealing resin 23 (arrow F in FIG. 41). B As a result, the reliability of the semiconductor device 20A after long-term use can be improved.

[0311] Furthermore, according to this embodiment, the second surface portion 54b of the lead portion 12 is roughened. This increases the adhesive strength between the second surface portion 54b and the sealing resin 23, and prevents the surface of the lead portion 12 and the sealing resin 23 from peeling off from each other.

[0312] Furthermore, according to this embodiment, on the back surface side of the semiconductor device 20A, the length of the path through which moisture penetrates is increased at the interface between the sealing resin 23 and the die pad 11 or the lead portion 12. This makes it possible to prevent moisture from penetrating into the semiconductor element 21 from the interface between the sealing resin 23 and the die pad 11 or the lead portion 12 (arrow F in FIG. 41). A As a result, the reliability of the semiconductor device 20A after long-term use can be improved.

[0313] Seventh embodiment Next, the seventh embodiment will be described with reference to Figures 42 to 45. Figures 42 to 45 are diagrams showing the seventh embodiment. The seventh embodiment shown in Figures 42 to 45 differs mainly in that a recess 18 is formed on the surface of the lead portion 12, and other configurations are substantially the same as the fifth embodiment described above. In Figures 42 to 45, the same parts as those in the embodiment shown in Figures 8 to 41 are given the same reference numerals and detailed description will be omitted.

[0314] (Structure of lead frame and semiconductor device) FIG. 42 is a cross-sectional view showing a lead frame 10B according to the present embodiment, and FIG. 43 is a cross-sectional view showing a semiconductor device 20B according to the present embodiment.

[0315] In the lead frame 10B shown in Fig. 42 and the semiconductor device 20B shown in Fig. 43, a recess 18 is formed on the surface of the lead portion 12 outside the metal layer 25 (the side opposite the die pad 11). A portion adjacent to the outside of the recess 18 (third surface portion 54c) is a rough surface. The inner surface of the recess 18 is a smooth surface. A portion located between the recess 18 and the metal layer 25 (fourth surface portion 54d) is a smooth surface.

[0316] The fourth surface portion 54d is adjacent to the outer side of the metal layer 25 (the side opposite to the die pad 11). The fourth surface portion 54d is in direct contact with the metal layer 25. The fourth surface portion 54d has a smooth surface in its entirety. The length L of the fourth surface portion 54d along the longitudinal direction of the lead portion 12 (length in the X direction) B It may be 25 μm or more and 200 μm or less, and preferably 50 μm or more and 100 μm or less.

[0317] The recess 18 is adjacent to the outside of the fourth surface portion 54d (the opposite side to the die pad 11). The recess 18 is in direct contact with the fourth surface portion 54d. The inner surface of the recess 18 is entirely smooth. The length L of the recess 18 along the longitudinal direction of the lead portion 12 (length in the X direction) cThe width of the recess 18 may be 50 μm or more and 150 μm or less, and preferably 75 μm or more and 100 μm or less. The depth of the recess 18 may be 25 μm or more and 125 μm or less, and preferably 50 μm or more and 100 μm or less. The planar shape of the recess 18 may be, for example, a circle or a polygon such as a square. The recess 18 is provided in a part of the lead portion 12 in the width direction. However, the recess 18 is not limited to this, and may be provided over the entire width direction of the lead portion 12.

[0318] The third surface portion 54c is adjacent to the outside of the recess 18 (the side opposite to the die pad 11). The third surface portion 54c is in direct contact with the recess 18. The third surface portion 54c has a rough surface in its entirety. In the lead frame 10B, the third surface portion 54c preferably extends continuously to the connection portion between the lead portion 12 and the connecting bar 13. The surface of the connecting bar 13 may also be rough.

[0319] In this embodiment, the definitions and measurement methods of the "rough surface" and "smooth surface" are the same as in the second embodiment.

[0320] (Lead frame manufacturing method) Next, a method for manufacturing the lead frame 10B shown in Fig. 42 will be described with reference to Fig. 44(a)-(j). In Fig. 44(a)-(j), the same parts as those shown in Fig. 35(a)-(j) are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0321] First, a metal substrate 31 is prepared (FIG. 44(a)) in a manner similar to the process shown in FIGS. 35(a) and (b) described above, and photosensitive resists 32a and 33a are formed on the front and back surfaces of the metal substrate 31, respectively (FIG. 44(b)).

[0322] Next, etching resist layers 32, 33 having openings 32b, 33b are formed (FIG. 44(c)) in substantially the same manner as the process shown in FIG. 35(c) described above. At this time, openings 32b are also formed in the regions corresponding to the recesses 18.

[0323] Next, in substantially the same manner as the process shown in Fig. 35(d) described above, the metal substrate 31 is etched to form the outlines of the die pad 11, the lead portion 12, and the connecting bar 13 (Fig. 44(d)). At this time, a recess 18 is also formed in the surface of the lead portion 12. Next, in substantially the same manner as the process shown in Fig. 35(e) described above, the etching resist layers 32, 33 are peeled off and removed (Fig. 44(e)).

[0324] Next, in substantially the same manner as the step shown in Fig. 35(f) described above, a plating layer 36 is formed all over the periphery of the metal substrate 31 (Fig. 44(f)). At this time, the plating layer 36 is also formed inside the recesses 18.

[0325] Next, portions of the plating layer 36 corresponding to the first die pad side surface 11c, the second die pad side surface 11d, the third surface portion 54c, the inner lead tip surface 51c, and the inner lead back surface 51b of the metal substrate 31 are removed (Figure 44(g)).

[0326] During this process, as shown in FIG. 44(g), elastic members 46 such as rubber packings are placed on the front and back surfaces of the metal substrate 31, and the metal substrate 31 is sandwiched between the jig 47E via the elastic members 46. The elastic member 46 on the front surface side of the metal substrate 31 covers the die pad front surface 11a, the recess 18, the area corresponding to the fourth surface portion 54d, and the area where the metal layer 25 of the lead portion 12 is provided. Next, the plating layer 36 in the portion not covered by the elastic member 46 is peeled off and removed. This exposes the first die pad side surface 11c, the second die pad side surface 11d, the third surface portion 54c, the inner lead tip surface 51c, and the inner lead back surface 51b. Meanwhile, the die pad front surface 11a, the die pad back surface 11b, the inner surface of the recess 18, the fourth surface portion 54d, and the plating layer 36 on the external terminal 17 that are covered by the elastic member 46 remain.

[0327] 35(h), a support layer 37 is provided on the back surface side of the metal substrate 31. Next, the portion of the metal substrate 31 that is not covered with the plating layer 36 is roughened to form a rough surface in the portion that is not covered with the plating layer 36 (FIG. 44(h)). As a result, the first die pad side surface 11c, the second die pad side surface 11d, the third surface portion 54c, the inner lead tip surface 51c, and the inner lead back surface 51b are roughened.

[0328] Next, in substantially the same manner as the step shown in FIG. 35(i), the support layer 37 and the plating layer 36 are peeled off and removed in this order (FIG. 44(i)).

[0329] Thereafter, in substantially the same manner as in the step shown in Fig. 35(j) described above, a metal layer 25 is formed on the die pad 11 and the lead portions 12. In this manner, the lead frame 10B shown in Fig. 42 is obtained (Fig. 44(j)).

[0330] (Method of manufacturing a semiconductor device) The semiconductor device 20B according to the present embodiment can be manufactured in a manner substantially similar to the method for manufacturing the semiconductor device 20 shown in FIGS.

[0331] According to this embodiment, the fourth surface portion 54d of the surface of the lead portion 12 adjacent to the outer side of the metal layer 25 is a smooth surface. This makes it possible to prevent tin and the like contained in the bumps 26 from flowing out along the fourth surface portion 54d when the semiconductor element 21 is mounted on the die pad 11 (arrow F in FIG. 45). C On the other hand, if the fourth surface portion 54d were a rough surface, there is a risk that the tin or the like contained in the bump 26 would flow out along the fourth surface portion 54d due to surface tension.

[0332] Furthermore, according to this embodiment, the recess 18 is formed on the surface of the lead portion 12 outside the metal layer 25. As a result, even if tin or the like contained in the bump 26 flows out along the fourth surface portion 54d, the flowed-out tin or the like can be received by the recess 18. As a result, the flowed-out tin or the like can be prevented from reaching the third surface portion 54c side.

[0333] Furthermore, according to this embodiment, the third surface portion 54c adjacent to the outside of the recess 18 is roughened. This increases the distance of the path along which moisture can penetrate at the interface between the surface of the lead portion 12 and the sealing resin 23. This makes it possible to prevent moisture from penetrating into the semiconductor element 21 from the interface between the surface of the lead portion 12 and the sealing resin 23 (arrow F in FIG. 45). B As a result, the reliability of the semiconductor device 20B after long-term use can be improved.

[0334] Furthermore, according to this embodiment, the third surface portion 54c of the lead portion 12 is roughened. This increases the adhesive strength between the third surface portion 54c and the sealing resin 23, and prevents the surface of the lead portion 12 and the sealing resin 23 from peeling off from each other.

[0335] Furthermore, according to this embodiment, on the back surface side of the semiconductor device 20B, the length of the path through which moisture penetrates is increased at the interface between the sealing resin 23 and the die pad 11 or the lead portion 12. This makes it possible to prevent moisture from penetrating into the semiconductor element 21 from the interface between the sealing resin 23 and the die pad 11 or the lead portion 12 (arrow F in FIG. 45). A As a result, the reliability of the semiconductor device 20B after long-term use can be improved.

[0336] Eighth embodiment Next, an eighth embodiment will be described with reference to Figures 46 to 49. Figures 46 to 49 are diagrams showing the eighth embodiment. The eighth embodiment shown in Figures 46 to 49 is different from the seventh embodiment in that the inner surface of the recess 18 is rough, and other configurations are substantially the same as those of the seventh embodiment described above. In Figures 46 to 49, the same parts as those in the embodiment shown in Figures 8 to 45 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0337] (Structure of lead frame and semiconductor device) FIG. 46 is a cross-sectional view showing a lead frame 10C according to the present embodiment, and FIG. 47 is a cross-sectional view showing a semiconductor device 20C according to the present embodiment.

[0338] In the lead frame 10C shown in Fig. 46 and the semiconductor device 20C shown in Fig. 47, a recess 18 is formed on the surface of the lead portion 12 outside the metal layer 25 (opposite the die pad 11). In addition, a portion adjacent to the outside of the recess 18 (third surface portion 54c) is rough. The entire inner surface of the recess 18 is rough. A portion (fourth surface portion 54d) located between the recess 18 and the metal layer 25 is smooth.

[0339] In this embodiment, the definitions and measurement methods of the "rough surface" and "smooth surface" are the same as in the second embodiment.

[0340] (Lead frame manufacturing method) Next, a method for manufacturing the lead frame 10C shown in Fig. 46 will be described with reference to Fig. 48(a)-(j). In Fig. 48(a)-(j), the same parts as those shown in Fig. 35(a)-(j) are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0341] First, a metal substrate 31 is prepared (Figure 48(a)) in a manner similar to the process shown in Figures 35(a) and (b) described above, and photosensitive resists 32a and 33a are formed on the front and back surfaces of the metal substrate 31, respectively (Figure 48(b)).

[0342] Next, etching resist layers 32, 33 having openings 32b, 33b are formed (FIG. 48(c)) in substantially the same manner as the process shown in FIG. 35(c) described above. At this time, openings 32b are also formed in the regions corresponding to the recesses 18.

[0343] Next, in substantially the same manner as the process shown in Fig. 35(d) described above, the metal substrate 31 is etched to form the outlines of the die pad 11, the lead portion 12, and the connecting bar 13 (Fig. 48(d)). At this time, a recess 18 is also formed in the surface of the lead portion 12. Next, in substantially the same manner as the process shown in Fig. 35(e) described above, the etching resist layers 32, 33 are peeled off and removed (Fig. 48(e)).

[0344] Next, in substantially the same manner as the step shown in Fig. 35(f) described above, a plating layer 36 is formed all over the periphery of the metal substrate 31 (Fig. 48(f)). At this time, the plating layer 36 is also formed inside the recesses 18.

[0345] Next, portions of the plating layer 36 corresponding to the first die pad side surface 11c, the second die pad side surface 11d, the third surface portion 54c, the recess 18, the inner lead tip surface 51c, and the inner lead back surface 51b of the metal substrate 31 are removed (Figure 48(g)).

[0346] During this process, as shown in FIG. 48(g), elastic members 46 such as rubber packings are placed on the front and back surfaces of the metal substrate 31, and the metal substrate 31 is sandwiched between the jig 47F via the elastic members 46. The elastic member 46 on the front surface side of the metal substrate 31 covers the die pad front surface 11a, the area corresponding to the fourth surface portion 54d, and the area where the metal layer 25 of the lead portion 12 is provided. Next, the plating layer 36 in the portion not covered by the elastic member 46 is peeled off and removed. This exposes the first die pad side surface 11c, the second die pad side surface 11d, the third surface portion 54c, the recess 18, the inner lead tip surface 51c, and the inner lead back surface 51b. Meanwhile, the plating layer 36 on the die pad front surface 11a, the die pad back surface 11b, the fourth surface portion 54d, and the external terminals 17 covered with the elastic member 46 remains.

[0347] 35(h), a support layer 37 is provided on the back surface side of the metal substrate 31. Next, the portion of the metal substrate 31 that is not covered with the plating layer 36 is roughened to form a rough surface in the portion that is not covered with the plating layer 36 (FIG. 48(h)). As a result, the first die pad side surface 11c, the second die pad side surface 11d, the third surface portion 54c, the inner surface of the recess 18, the inner lead tip surface 51c, and the inner lead back surface 51b are roughened.

[0348] Next, in substantially the same manner as the step shown in FIG. 35(i), the support layer 37 and the plating layer 36 are peeled off and removed in this order (FIG. 48(i)).

[0349] Thereafter, in substantially the same manner as in the step shown in Fig. 35(j) described above, a metal layer 25 is formed on the die pad 11 and the leads 12. In this manner, the lead frame 10C shown in Fig. 46 is obtained (Fig. 48(j)).

[0350] (Method of manufacturing a semiconductor device) The semiconductor device 20C according to the present embodiment can be manufactured in a manner substantially similar to the method for manufacturing the semiconductor device 20 shown in FIGS.

[0351] According to this embodiment, the fourth surface portion 54d of the surface of the lead portion 12 adjacent to the outer side of the metal layer 25 is a smooth surface. This makes it possible to prevent tin and the like contained in the bumps 26 from flowing out along the fourth surface portion 54d when the semiconductor element 21 is mounted on the die pad 11 (arrow F in FIG. 49). C On the other hand, if the fourth surface portion 54d were a rough surface, there is a risk that the tin or the like contained in the bump 26 would flow out along the fourth surface portion 54d due to surface tension.

[0352] Furthermore, according to this embodiment, the recess 18 is formed on the surface of the lead portion 12 outside the metal layer 25. As a result, even if tin or the like contained in the bump 26 flows out along the fourth surface portion 54d, the flowed-out tin or the like can be received by the recess 18. As a result, the flowed-out tin or the like can be prevented from reaching the third surface portion 54c side.

[0353] Furthermore, according to this embodiment, the inner surface of the recess 18 and the third surface portion 54c are roughened. This increases the distance of the path through which moisture can penetrate at the interface between the surface of the lead 12 and the sealing resin 23. This makes it possible to prevent moisture from penetrating into the semiconductor element 21 from the interface between the surface of the lead 12 and the sealing resin 23 (arrow F in FIG. 49). B As a result, the reliability of the semiconductor device 20C after long-term use can be improved.

[0354] According to the present embodiment, the inner surface of the recess 18 and the third surface portion 54c are roughened. This increases the adhesive strength between the recess 18 and the third surface portion 54c and the sealing resin 23, and prevents the surface of the lead portion 12 and the sealing resin 23 from peeling off from each other.

[0355] Furthermore, according to this embodiment, on the back surface side of the semiconductor device 20C, the length of the path through which moisture penetrates is increased at the interface between the sealing resin 23 and the die pad 11 or the lead portion 12. This makes it possible to prevent moisture from penetrating into the semiconductor element 21 from the interface between the sealing resin 23 and the die pad 11 or the lead portion 12 (arrow F in FIG. 49). A As a result, the reliability of the semiconductor device 20C after long-term use can be improved.

[0356] Ninth embodiment The ninth embodiment will be described with reference to Figures 50 to 57. Figures 50 to 57 are diagrams showing the ninth embodiment. In Figures 50 to 57, the same parts as those in the embodiment shown in Figures 8 to 49 are given the same reference numerals and detailed descriptions thereof will be omitted.

[0357] (Lead frame configuration) First, an outline of the lead frame according to this embodiment will be described with reference to Figures 50 and 51. Figures 50 and 51 are views showing the lead frame according to this embodiment.

[0358] As shown in Figures 50 and 51, each package area 10a of the lead frame 10 includes a die pad 11 and lead portions 12 located around the die pad 11. Of these, the lead portions 12 are partially thinned from the back surface side. Of the back surface of the lead portions 12, the thinned portion is a rough surface. Of the back surface of the lead portions 12, the non-thinned portion is a smooth surface.

[0359] As shown in FIG. 51, the die pad 11 has a die pad front surface 11a located on the front surface side and a die pad back surface 11b located on the back surface side. A semiconductor element 21 is mounted on the die pad front surface 11a as described later. The die pad back surface 11b is exposed to the outside from a semiconductor device 20 (described later). A die pad side surface 11h is formed on the side of the die pad 11 facing the lead portion 12. The die pad side surface 11h extends in the thickness direction (Z direction) from the die pad front surface 11a side to the die pad back surface 11b side. In this case, the die pad side surface 11h is a rough surface. That is, a third rough surface R3 is formed on the die pad side surface 11h. On the other hand, the die pad back surface 11b is a smooth surface.

[0360] In this embodiment, the term "rough surface" refers to a surface with an S-ratio of 1.10 or more. The term "smooth surface" refers to a surface with an S-ratio of less than 1.10. A rough surface is a surface that is rougher than a smooth surface. The S-ratio of a "rough surface" is preferably 1.10 or more and 2.30 or less. The S-ratio of a "smooth surface" is preferably 1.00 or more and less than 1.10. Here, "S-ratio" refers to the surface area ratio obtained by dividing the surface to be measured into multiple pixels using an optical interference measuring device. Specifically, the surface to be measured is divided into multiple pixels using a VertScan manufactured by Hitachi High-Tech Science Corporation, and the obtained surface area is divided by the observation area to calculate.

[0361] The rough surface may be formed by roughening the outer surface of the metal substrate 31, which will be described later, with, for example, a microetching solution. Examples of such microetching solutions include those containing sulfuric acid or hydrochloric acid as the main component (for example, a first microetching solution, which will be described later). Alternatively, a microetching solution containing hydrogen peroxide and sulfuric acid as the main components (for example, a second microetching solution, which will be described later) may be used. The smooth surface may be an unprocessed surface of the metal substrate 31, which will be described later, that is not subjected to such a roughening treatment. In FIG. 51, a rough surface with a relatively smooth surface (for example, a first rough surface R1, which will be described later) is indicated by a thin dashed line. In FIG. 51, a rough surface with a relatively rough surface (for example, a second rough surface R2, a third rough surface R3, a fourth rough surface R4, and a fifth rough surface R5, which will be described later) is indicated by a thick dashed line (the same applies to other cross-sectional views).

[0362] The die pad surface 11a of the die pad 11 is a region (internal terminal) that is bonded to the semiconductor element 21 via an adhesive 24 such as a die attach paste, as described later. The die pad surface 11a may be a region that is not thinned by half etching or the like. A first rough surface R1 is formed on the die pad surface 11a. The roughness of the first rough surface R1 is smoother (less rough) than the roughness of a second rough surface R2 of the lead portion 12, which will be described later. Specifically, the S-ratio of the first rough surface R1 may be 1.10 or more and less than 1.30.

[0363] In this embodiment, the first rough surface R1 is formed over the entire area of ​​the die pad surface 11a. However, the present invention is not limited to this, and the first rough surface R1 may be formed on a part of the die pad surface 11a. In particular, the first rough surface R1 is preferably formed on the outer periphery of the mounting area of ​​the semiconductor element 21 on the die pad surface 11a. This makes it possible to suppress the phenomenon (bleed-out) in which components such as epoxy resin in the adhesive 24 ooze out of the die pad surface 11a due to capillary action, as described later. The first rough surface R1 may also be formed along the entire periphery of the die pad 11. When the first rough surface R1 is formed on a part of the die pad surface 11a, the part other than the first rough surface R1 may be a smooth surface. Alternatively, the part of the die pad surface 11a other than the first rough surface R1 may be a rough surface that is rougher than the roughness of the first rough surface R1. For example, the S-ratio of the portion of the die pad surface 11a other than the first rough surface R1 may be 1.30 or more and 2.30 or less.

[0364] 51, the die pad rear surface 11b is not thinned by, for example, half etching, and has a smooth surface similar to that of the metal substrate (metal substrate 31 described later) before processing. The die pad rear surface 11b is exposed to the outside from the semiconductor device 20 after the semiconductor device 20 (described later) is manufactured.

[0365] As will be described later, each lead portion 12 is connected to a semiconductor element 21 via a bonding wire 22, and is disposed with a space between it and the die pad 11. The multiple lead portions 12 are disposed at intervals along the longitudinal direction of the connecting bar 13. Each lead portion 12 extends from the connecting bar 13.

[0366] As shown in FIG. 51, the lead portion 12 has an inner lead 51 and a terminal portion 53. The inner lead 51 is located on the inside (the die pad 11 side). The terminal portion 53 is located on the outside (the connecting bar 13 side). The inner lead 51 extends from the terminal portion 53 to the die pad 11 side. An internal terminal is formed on the front surface side of the inner lead 51. This internal terminal is an area that is electrically connected to the semiconductor element 21 via a bonding wire 22 as described below. A metal layer 25 is provided on the internal terminal to improve adhesion with the bonding wire 22.

[0367] In this embodiment, the thinned portion of the back surface of the lead portion 12 is a rough surface. Specifically, the inner lead 51 of the lead portion 12 is thinned from the back surface side. The inner lead back surface 51b located on the back surface side of the inner lead 51 is a rough surface over its entire area. That is, a fourth rough surface R4 is formed on the inner lead back surface 51b. On the other hand, the non-thinned portion of the back surface of the lead portion 12 is a smooth surface. Specifically, the terminal portion 53 of the lead portion 12 is not thinned from the back surface side. The external terminal 17 located on the back surface side of the terminal portion 53 is a smooth surface over its entire area.

[0368] Furthermore, the entire inner lead tip surface 51c of the lead portion 12 is roughened. That is, a fifth rough surface R5 is formed on the inner lead tip surface 51c. Although not shown, both side surfaces along the longitudinal direction of the lead portion 12 may also be roughened. On the other hand, the inner lead 51 of the lead portion 12 is not thinned from the front surface side. Moreover, the terminal portion 53 of the lead portion 12 is not thinned from the front surface side.

[0369] The lead surface 12a is composed of an inner lead surface 51a of the inner lead 51 and a terminal surface 53a of the terminal 53. The lead surface 12a is a region that has not been thinned from the front side by half etching or the like. The lead surface 12a is formed with a smooth surface region S, which is a smooth surface region, and a second rough surface R2, which is a rough surface region.

[0370] The smooth surface region S is located at the inner end (die pad 11 side) of the lead portion 12. A metal layer 25 is formed on the smooth surface region S. In this case, the metal layer 25 covers the entire smooth surface region S in a plan view. The metal layer 25 may be a plating layer formed by, for example, an electrolytic plating method. The thickness of the metal layer 25 may be 1 μm or more and 10 μm or less. Metals constituting such a plating layer may include silver, silver alloys, gold, gold alloys, platinum group metals, copper, copper alloys, palladium, and the like. When underplating is required due to the metal constituting the metal layer 25, known metals such as nickel and copper may be applied.

[0371] In this case, one smooth surface region S is formed on the lead surface 12a of each lead portion 12. However, this is not limited to the above, and multiple smooth surface regions S may be formed on the lead surface 12a of each lead portion 12. Also, the lead surface 12a of each lead portion 12 does not have to have a smooth surface region S. In other words, the entire lead surface 12a of each lead portion 12 may be the second rough surface R2.

[0372] The second rough surface R2 is located outside (the connecting bar 13 side) of the smooth surface region S and the metal layer 25. In this case, the second rough surface R2 is provided only outside (the connecting bar 13 side) the smooth surface region S. However, this is not limited thereto, and the second rough surface R2 may be provided so as to surround the smooth surface region S in a plan view. The lead surface 12a may be composed of only the smooth surface region S and the second rough surface R2.

[0373] In this embodiment, the roughness of the second rough surface R2 is rougher than the roughness of the first rough surface R1 of the die pad 11. Specifically, the S-ratio of the second rough surface R2 may be 1.30 or more and 2.30 or less. On the other hand, as described above, the S-ratio of the first rough surface R1 may be 1.10 or more and less than 1.30.

[0374] The roughness of the third rough surface R3 of the die pad 11 described above may be rougher than the roughness of the first rough surface R1. The S-ratio of the third rough surface R3 may be 1.30 or more and 2.30 or less. The roughness of the fourth rough surface R4 of the lead portion 12 may be rougher than the roughness of the first rough surface R1 described above. The S-ratio of the fourth rough surface R4 may be 1.30 or more and 2.30 or less. The roughness of the fifth rough surface R5 of the lead portion 12 may be rougher than the roughness of the first rough surface R1 described above. The S-ratio of the fifth rough surface R5 may be 1.30 or more and 2.30 or less.

[0375] The second rough surface R2, the third rough surface R3, the fourth rough surface R4, and the fifth rough surface R5 may have different roughnesses or may have the same roughness.

[0376] In addition, the configuration of the lead frame 10 according to this embodiment may be the same as the configuration of the lead frame 10 according to the second embodiment.

[0377] (Configuration of Semiconductor Device) Next, the semiconductor device according to the present embodiment will be described with reference to Figures 52 and 53. Figures 52 and 53 are diagrams showing the semiconductor device (QFN type) according to the present embodiment.

[0378] As shown in FIGS. 52 and 53, a semiconductor device (semiconductor package) 20 includes a die pad 11, a semiconductor element 21, a plurality of leads 12, a plurality of bonding wires 22, and a sealing resin .

[0379] Of these, the semiconductor element 21 is mounted on the die pad 11. The multiple bonding wires 22 electrically connect the semiconductor element 21 to the metal layer 25 of the lead portion 12. In this case, the bonding wires 22 form a connecting member. The sealing resin 23 resin-seals the die pad 11, the lead portion 12, the semiconductor element 21, and the bonding wires 22.

[0380] The die pad 11 and the lead portion 12 are produced from the above-mentioned lead frame 10. In this case, a first rough surface R1 is formed on a die pad surface 11a of the die pad 11. A second rough surface R2 is formed on a lead surface 12a of the lead portion 12 at a position outside (farther from) the metal layer 25. The roughness of the second rough surface R2 of the lead portion 12 is rougher than the roughness of the first rough surface R1 of the die pad 11.

[0381] Also, a third rough surface R3 is formed on the die pad side surface 11h of the die pad 11. The roughness of the third rough surface R3 is coarser than that of the first rough surface R1. The sealing resin 23 is adhered to the die pad side surface 11h. The inner lead 51 of the lead portion 12 is thinned from the back surface side. The inner lead back surface 51b of the inner lead 51 is a fourth rough surface R4. The roughness of the fourth rough surface R4 is coarser than that of the first rough surface R1. The sealing resin 23 is adhered to the inner lead back surface 51b. Also, a fifth rough surface R5 is formed on the inner lead tip surface 51c of the inner lead 51. The roughness of the fifth rough surface R5 is coarser than that of the first rough surface R1. The sealing resin 23 is adhered to the inner lead tip surface 51c. The terminal portion 53 of the lead portion 12 is not thinned from the back surface side. The external terminals 17 located on the back surface of the terminal portion 53 have a smooth surface. The external terminals 17 are exposed to the outside from the sealing resin 23.

[0382] As the semiconductor element 21, various types of semiconductor elements that are generally used in the past can be used, and are not particularly limited, and examples that can be used include integrated circuits, large-scale integrated circuits, transistors, thyristors, diodes, etc. This semiconductor element 21 has a plurality of electrodes 21a to which bonding wires 22 are respectively attached. Furthermore, the semiconductor element 21 is fixed to the surface of the die pad 11 by an adhesive 24 such as a die attach paste. The adhesive 24 may be an epoxy resin-based adhesive containing components such as silver paste and epoxy resin.

[0383] Each bonding wire 22 is made of a material with good conductivity, such as gold or copper. One end of each bonding wire 22 is connected to an electrode 21a of the semiconductor element 21, and the other end is connected to a metal layer 25 located on each lead portion 12. A conductor such as a bump may be used as the connecting member instead of the bonding wire 22. In this case, the semiconductor element 21 can be connected to the lead portion 12 by flip chip bonding.

[0384] The sealing resin 23 may be a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin such as a PPS resin. The overall thickness of the sealing resin 23 may be about 300 μm or more and 1500 μm or less. Also, one side of the sealing resin 23 (one side of the semiconductor device 20) may be, for example, 0.2 mm or more and 20 mm or less. In FIG. 52, the portion of the sealing resin 23 located on the front side of the lead portion 12 and the semiconductor element 21 is not shown.

[0385] Besides this, the configurations of the die pad 11 and the lead portions 12 are similar to those shown in the above-mentioned FIGS. 50 and 51, except for the areas not included in the semiconductor device 20, and therefore a detailed description thereof will be omitted here.

[0386] (Lead frame manufacturing method) Next, a method for manufacturing the lead frame 10 shown in Figures 50 and 51 will be described with reference to Figures 54(a)-(e) and Figures 55(a)-(h). Figures 54(a)-(e) and Figures 55(a)-(h) are cross-sectional views (figures corresponding to Figure 51) showing the method for manufacturing the lead frame 10.

[0387] First, in the same manner as in the second embodiment (FIGS. 14(a)-(e)), a metal substrate 31 having a die pad 11 and lead portions 12 positioned around the die pad 11 is fabricated (FIGS. 54(a)-(e)).

[0388] Next, a plating layer (coating layer) 36 is formed around the metal substrate 31 (FIG. 55(a)). At this time, the plating layer 36 may be formed on the entire outwardly exposed portions of the die pad 11, the lead portion 12, and the connecting bar 13. The thickness of the plating layer 36 may be more than 0 μm and not more than 2 μm. The metal constituting the plating layer 36 may be, for example, silver. When the plating layer 36 is made of silver plating, a silver plating solution containing silver cyanide and potassium cyanide as main components can be used as the plating solution for electrolytic plating.

[0389] Next, the plating layer 36 present in the region of the metal substrate 31 that forms the first rough surface R1 is removed. Specifically, the plating layer 36 located over the entire die pad surface 11a of the die pad 11 is removed (FIG. 55(b)). In this case, for example, the front surface and back surface of the metal substrate 31 other than the die pad surface 11a are clamped by a jig via elastic members. Next, the plating layer 36 in the portion not covered by the elastic member and the jig may be peeled off and removed. This removes the plating layer 36 on the die pad surface 11a.

[0390] Next, the portion of the metal substrate 31 that is not covered with the plating layer 36 is roughened to form a first rough surface R1 on that portion (FIG. 55(c)). Specifically, a first micro-etching liquid is supplied to the metal substrate 31 to form a first rough surface R1 on the entire die pad surface 11a that is not covered with the plating layer 36. Here, the first micro-etching liquid is a surface treatment agent that slightly dissolves the metal surface to form the first rough surface R1 with fine irregularities. For example, when roughening the metal substrate 31 made of copper or a copper alloy, a micro-etching liquid mainly containing sulfuric acid or hydrochloric acid may be used as the first micro-etching liquid.

[0391] Next, the plating layer 36 present in the metal substrate 31 other than the smooth surface region S (region where the metal layer 25 is formed) of the lead surface 12a is removed. In this case, for example, the front surface and back surface of the metal substrate 31 other than the smooth surface region S are clamped by a jig via an elastic member. Next, the plating layer 36 in the portion not covered by the elastic member and the jig may be peeled off and removed. This removes the plating layer 36 located on the die pad back surface 11b and die pad side surface 11h of the die pad 11. Also, in the lead portion 12, the plating layer 36 located in the portion other than the smooth surface region S of the lead surface 12a, the inner lead back surface 51b, the inner lead tip surface 51c, and the external terminal 17 is removed.

[0392] Next, protective layers 37A are provided on the front and back surfaces of the metal substrate 31, respectively (FIG. 55(e)). The protective layer 37A may be, for example, a resist layer. The protective layer 37A on the front side covers the die pad front surface 11a of the die pad 11 and the plating layer 36 on the smooth surface region S of the lead portion 12. At this time, the protective layer 37A on the front side covers the entire first rough surface R1 of the die pad 11. The protective layer 37A on the front side may also cover a part or the entire plating layer 36 on the smooth surface region S. The protective layer 37A on the back side covers the die pad back surface 11b of the die pad 11 and the external terminals 17 of the lead portion 12.

[0393] Next, the portion of the metal substrate 31 that is not covered by the plating layer 36 and the protective layer 37A is roughened to form a rough surface in the portion that is not covered by the plating layer 36 and the protective layer 37A (FIG. 55(f)). Specifically, a second rough surface R2 is formed on a part of the lead surface 12a of the lead portion 12. A third rough surface R3 is formed on the die pad side surface 11h of the die pad 11. A fourth rough surface R4 is formed on the inner lead back surface 51b of the lead portion 12. A fifth rough surface R5 is formed on the inner lead tip surface 51c of the lead portion 12.

[0394] During this time, the second microetching solution is supplied to the metal substrate 31. This forms a rough surface on the entire metal substrate 31 except for the portion covered with the plating layer 36 and the protective layer 37A. Here, the second microetching solution is a surface treatment agent that slightly dissolves the metal surface and forms a rough surface with fine irregularities. For example, when roughening the metal substrate 31 made of copper or a copper alloy, the second microetching solution may be a microetching solution containing hydrogen peroxide and sulfuric acid as main components. The second microetching solution may contain components different from the first microetching solution described above. The second microetching solution roughens the metal more than the first microetching solution. Therefore, the second rough surface R2, the third rough surface R3, the fourth rough surface R4, and the fifth rough surface R5 are each rougher than the first rough surface R1.

[0395] Next, the protective layer 37A and the plating layer 36 on the front surface side of the metal substrate 31 are peeled off and removed (FIG. 55(g)). At this time, the plating layer 36 covering the lead front surface 12a is removed, and the smooth surface region S is exposed. Note that the protective layer 37A on the back surface side remains on the metal substrate 31.

[0396] Thereafter, a metal layer 25 is formed on the smooth surface region S of the lead portion 12 (FIG. 55(h)). In this case, a plating resist layer having a predetermined pattern (not shown) is first formed on the die pad 11 and the lead portion 12 excluding the smooth surface region S, for example, by photolithography. Next, a metal layer 25 made of a plating layer is formed on the smooth surface region S not covered by the plating resist layer, for example, by electrolytic plating. Thereafter, the plating resist layer is removed to obtain the lead frame 10 shown in FIGS. 50 and 51.

[0397] (Method of manufacturing a semiconductor device) Next, a method for manufacturing the semiconductor device 20 shown in Figures 52 and 53 will be described with reference to Figures 56(a)-(e). Figures 56(a)-(e) are cross-sectional views (figures corresponding to Figure 53) showing the method for manufacturing the semiconductor device 20.

[0398] First, the lead frame 10 is produced (FIG. 56(a)) by, for example, the method shown in FIGS. 54(a)-(e) and 55(a)-(h).

[0399] Next, the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10. In this case, the semiconductor element 21 is placed and fixed on the die pad 11 using an adhesive 24 such as a die attach paste (FIG. 56(b)). The adhesive 24 may be an epoxy resin-based adhesive containing components such as silver paste and epoxy resin. At this time, the semiconductor element 21 is placed on the first rough surface R1 of the die pad surface 11a via the adhesive 24. In addition, the first rough surface R1 is located along the outer periphery of the semiconductor element 21 and the adhesive 24.

[0400] Subsequently, each electrode 21a of the semiconductor element 21 and the metal layer 25 formed on each lead portion 12 are electrically connected to each other by a bonding wire (connecting member) 22 (FIG. 56(c)).

[0401] Next, a thermosetting resin or a thermoplastic resin is injection molded or transfer molded onto the lead frame 10 to form the sealing resin 23 (FIG. 56(d)). As a result, the die pad 11, the lead portion 12, the semiconductor element 21, and the bonding wires 22 are resin-sealed.

[0402] Thereafter, the lead frame 10 and the sealing resin 23 are cut for each package region 10a. As a result, the lead frame 10 is separated into each semiconductor device 20, and the semiconductor device 20 shown in Figures 52 and 53 is obtained (Figure 56(e)).

[0403] Meanwhile, during the fabrication of the semiconductor device 20 in this manner, a step of heating and curing the adhesive 24 is carried out (FIG. 56(b)). Specifically, the adhesive 24, such as a die attach paste, is applied to the die pad 11, the semiconductor element 21 is mounted on the die pad 11, and then the adhesive 24 is heated and cured. At this time, components such as epoxy resin in the applied adhesive 24 may seep out due to capillary action on the die pad surface 11a. This phenomenon is also called bleed-out or epoxy bleed-out.

[0404] In contrast, according to this embodiment, a first rough surface R1 is formed on the die pad surface 11a of the die pad 11. The roughness of the first rough surface R1 is suppressed below that of the second rough surface R2. This can suppress the phenomenon (bleed-out) of the epoxy resin or the like in the adhesive 24 due to the capillary phenomenon caused by the unevenness of the die pad surface 11a (see arrow E in FIG. 57). On the other hand, it is also possible to make the die pad surface 11a around the adhesive 24 a smooth surface. However, if the viscosity of the epoxy resin in the adhesive 24 is low, the epoxy resin will rather flow easily along the die pad surface 11a, which is a smooth surface. For this reason, in this embodiment, the roughness of the die pad surface 11a is made moderately rough to the extent that the capillary phenomenon does not occur (first rough surface R1). This can suppress the epoxy resin from flowing along the die pad surface 11a regardless of the viscosity of the epoxy resin in the adhesive 24.

[0405] Furthermore, when such a semiconductor device 20 is used for a long period of time, moisture in the air may enter from the side or back side of the semiconductor device 20. For example, moisture may enter through the interface between the sealing resin 23 and the die pad 11 or the lead portion 12.

[0406] In contrast, according to this embodiment, a second rough surface R2 is formed on the lead surface 12a of the lead portion 12. This increases the length of the path through which moisture can penetrate at the interface between the lead surface 12a and the sealing resin 23. This makes it possible to prevent moisture from penetrating into the semiconductor element 21 from the interface between the lead surface 12a and the sealing resin 23 (arrow F in FIG. 57).A As a result, the reliability of the semiconductor device 20 after long-term use can be improved.

[0407] Furthermore, according to this embodiment, the die pad side surface 11h of the die pad 11 is the third rough surface R3. The roughness of the third rough surface R3 is greater than the roughness of the first rough surface R1. As a result, the length of the path along which moisture can penetrate at the interface between the sealing resin 23 and the die pad 11 on the back surface side of the semiconductor device 20 is longer. This makes it possible to prevent moisture from penetrating into the semiconductor element 21 side from the interface between the sealing resin 23 and the die pad 11 (arrow F in Figure 57). B As a result, it is possible to improve the reliability of the semiconductor device 20 even after a long period of use. Furthermore, it is possible to increase the adhesive strength between the die pad 11 and the sealing resin 23, and to prevent the die pad 11 and the sealing resin 23 from peeling off from each other.

[0408] Furthermore, according to this embodiment, the inner lead back surface 51b of the lead portion 12 is the fourth rough surface R4. Furthermore, the inner lead tip surface 51c of the lead portion 12 is the fifth rough surface R5. The roughness of the fourth rough surface R4 and the roughness of the fifth rough surface R5 are each greater than the roughness of the first rough surface R1. As a result, the length of the moisture intrusion path at the interface between the sealing resin 23 and the lead portion 12 on the back surface side of the semiconductor device 20 is longer. This makes it possible to prevent moisture from infiltrating into the semiconductor element 21 side from the interface between the sealing resin 23 and the lead portion 12 (arrow F in Figure 57). c As a result, it is possible to improve the reliability of the semiconductor device 20 even after long-term use. Furthermore, it is possible to increase the adhesive strength between the lead portion 12 and the sealing resin 23, and to prevent the lead portion 12 and the sealing resin 23 from peeling off from each other.

[0409] (Modification) Next, a modified example of the lead frame 10 according to the present embodiment will be described with reference to Fig. 58. Fig. 58 is a cross-sectional view showing the modified lead frame 10. In Fig. 58, the same parts as those shown in Figs. 50 to 57 are given the same reference numerals and detailed description will be omitted.

[0410] 58, a smooth surface region S and a second rough surface R2 are formed on the lead surface 12a of the lead portion 12. In this case, the metal layer 25 is not provided on the smooth surface region S. Therefore, the smooth surface region S is exposed to the outside of the lead frame 10.

[0411] When producing the lead frame 10 shown in Fig. 58, after performing the steps shown in Fig. 54(a)-(e) and Fig. 55(a)-(g) described above, the step of forming the metal layer 25 (Fig. 55(h)) is not performed. As a result, the lead frame 10 shown in Fig. 58 is obtained.

[0412] In this way, by not providing the metal layer 25 on the smooth surface region S, the manufacturing process of the lead frame 10 can be reduced. Also, by not providing the metal layer 25 made of a plating layer of silver, silver alloy, gold, gold alloy, platinum group metals, copper, copper alloy, palladium, or the like, the manufacturing cost of the lead frame 10 can be reduced. Also, this is more effective when the semiconductor element 21 is connected to the lead portion 12 by flip chip bonding, rather than by wire bonding.

[0413] It is also possible to combine the multiple components disclosed in the above embodiments and modifications as necessary. Alternatively, some components may be deleted from all the components shown in the above embodiments and modifications.

Claims

1. A die pad on which a semiconductor element is mounted, and lead portions located around the die pad, comprising: at least a part of the surface of the die pad has a first rough surface formed thereon, a third rough surface is formed on the side surface of the die pad, The roughness value based on the S-ratio of the third rough surface of the die pad is rougher than the roughness value based on the S-ratio of the first rough surface of the die pad. A lead frame.

2. A die pad on which a semiconductor element is mounted, and lead portions located around the die pad, comprising: at least a part of the surface of the die pad has a first rough surface formed thereon, The lead portion has an inner lead that is thinned from the back side, An inner lead back surface is formed on the back side of the inner lead, A fourth rough surface is formed on the inner lead back surface, The roughness value based on the S-ratio of the fourth rough surface of the lead portion is rougher than the roughness value based on the S-ratio of the first rough surface of the die pad. A lead frame.

3. A die pad on which a semiconductor element is mounted, and lead portions located around the die pad, comprising: at least a part of the surface of the die pad has a first rough surface formed thereon, The lead portion has an inner lead that is thinned from the back side, An inner lead tip surface is formed on the surface of the inner lead facing the die pad, A fifth rough surface is formed on the inner lead tip surface, The roughness value based on the S-ratio of the fifth rough surface of the lead portion is rougher than the roughness value based on the S-ratio of the first rough surface of the die pad. A lead frame.

4. The S-ratio of the first rough surface is 1.10 or more and less than 1.

30. The lead frame according to any one of Claims 1 to 3.

5. The S-ratio of the third rough surface is 1.30 or more and 2.30 or less. The lead frame according to Claim 1.

6. The S-ratio of the fourth rough surface is 1.30 or more and 2.30 or less. The lead frame according to Claim 2.

7. The S-ratio of the fifth rough surface is 1.30 or more and 2.30 or less. The lead frame according to Claim 3.

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