Logic circuit design device and logic circuit design method

Abstract

To provide a logic circuit design device and logic circuit design method that can reduce the burden on a designer who designs a logic circuit.SOLUTION: A logic circuit design device 10 for designing a logic circuit by using a standard cell composed of multiple elements includes: a library 21 in which multiple standard cells are registered; and input reception means which receives input information from a user. The multiple standard cells include MV (Multi-Vth) standard cells which has: a first element that has a first polarity; and a second element that has a second polarity opposite to the first polarity, and has a threshold voltage different from that of the first element.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a logic circuit design device and a logic circuit design method. [Background technology]

[0002] Conventionally, a design method has been known in which a plurality of standard cells each combining pre-designed and standardized logic elements is registered in a library in advance, and the standard cells registered in the library are arranged and wired to design a semiconductor integrated circuit such as an LSI (Large Scale Integration). For example, in Patent Document 1, a PMOS transistor and an NMOS transistor are connected to a V DD Lines and V SS It is disclosed that in standard cells that are connected in series between lines and share a gate, the standard cell length (cell height) of a PMOS transistor is made larger than the standard cell length of an NMOS transistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2019-145823 A Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been a demand for miniaturization of semiconductor circuits, and accordingly, there is also a demand for miniaturization of logic circuits that are configured by combining multiple standard cells. At the same time, designers must consider the design values ​​of logic circuits more precisely in order to maintain the noise resistance of logic circuits. In other words, designers must design logic circuits that guarantee their operation based on process rules and layout rules that require stricter accuracy. In this way, in logic circuit design, the required requirements and the design conditions corresponding to those requirements become stricter as the logic circuits become smaller, reducing the degree of freedom in design and increasing the burden on designers.

[0005] The present disclosure has been made in consideration of the above circumstances, and has an object to provide a logic circuit design device and a logic circuit design method that can reduce the burden on designers who design logic circuits. [Means for solving the problem]

[0006] A logic circuit design device according to some embodiments of the present disclosure is a logic circuit design device for designing a logic circuit using standard cells composed of a plurality of elements, the device including a library in which a plurality of standard cells are registered, and an input receiving means for receiving input information from a user, the plurality of standard cells including a first element of a first polarity and a second element of a second polarity that is opposite to the first polarity and has a threshold voltage different from that of the first element, the plurality of standard cells being MV (Multi-V th ) standard cells are included.

[0007] A logic circuit design method according to some embodiments of the present disclosure is a logic circuit design method for designing a logic circuit using a standard cell composed of a plurality of elements, the method including: designing a logic circuit using a multi-voltage (MV) transistor having a first element of a first polarity and a second element of a second polarity opposite to the first polarity and having a threshold voltage different from that of the first element; th The present invention uses a library in which a plurality of standard cells including the .DELTA..sub.1 standard cell are registered, and an input receiving means for receiving information input by a user. Effect of the Invention

[0008] According to the present disclosure, it is possible to expand the degree of freedom in designing a logic circuit using standard cells, and to reduce the burden on a designer in terms of designing under strict design conditions. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is a layout diagram of a standard cell including a PMOSFET and an NMOSFET according to the present disclosure. [Diagram 2] FIG. 1 is a layout diagram illustrating a standard cell in which a PMOSFET is enlarged. [Diagram 3] FIG. 1 is a diagram illustrating an example of a hardware configuration of a logic circuit design apparatus according to the present disclosure. [Figure 4] 1 is a functional block diagram showing an example of functions of a logic circuit design device according to the present disclosure. FIG. [Diagram 5] FIG. 1 is a diagram showing an example of a standard cell registered in a library of a logic circuit device according to the present disclosure. [Figure 6] 1 is a graph showing a change in the logic threshold voltage of a standard cell due to a change in the threshold voltage of a PMOSFET. [Figure 7] FIG. 13 is a diagram showing an example of the application of the MV standard cell according to the present disclosure to a clock buffer cell. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of a logic circuit design device and a logic circuit design method according to the present disclosure will be described with reference to the drawings.

[0011] In the following, for the sake of convenience, the positional relationship of each component described using the expressions "upper" and "lower" with respect to the paper surface indicates the vertically upper and lower sides, respectively. The positional relationship of each component described using the expressions "left" and "right" with respect to the paper surface indicates the horizontally left and right sides, respectively. Furthermore, in this embodiment, for components that can obtain similar effects in the up-down and horizontal directions, the up-down direction on the paper surface is not necessarily limited to the vertical up-down direction, but may correspond to, for example, a horizontal direction perpendicular to the vertical direction. The same applies to the horizontal direction.

[0012] 1 is a layout diagram of a standard cell including a PMOSFET and an NMOSFET according to the present disclosure. The standard cell 1 is registered in a library described below as a cell in which a basic arithmetic circuit composed of transistors is pre-built. Logic circuit design is performed by placing the standard cells registered in the library and other pre-designed functional blocks on a chip and wiring them together.

[0013] In this embodiment, as shown in Fig. 1, the standard cell 1 is a pre-designed and standardized cell, and includes a PMOSFET 2 (first element) and an NMOSFET 3 (second element). The PMOSFET 2 and the NMOSFET 3 are arranged in parallel in the vertical direction (cell height direction) of the paper surface of Fig. 1, and the boundary position between the PMOSFET 2 and the NMOSFET 3 is the center position C of the standard cell 1 in the cell height direction. Note that the standard cell 1 configured in this way may be used as, for example, an inverter.

[0014] The PMOSFET 2 has an active region 4 in which a transistor is formed, and similarly, the NMOSFET 3 has an active region 5 in which a transistor is formed. The active regions 4, 5 are surrounded by a field oxide film. Each of the active regions 4, 5 is divided by a finger 6 formed over each of the active regions 4, 5.

[0015] The standard cell 1 is generally designed so that the boundary between the PMOSFET 2 and the NMOSFET 3 is at the center of the cell height. That is, the heights of the PMOSFET 2 and the NMOSFET 3 are formed at a 1:1 ratio, and the number of fingers of the PMOSFET 2 and the number of fingers of the NMOSFET 3 are the same.

[0016] In such a configuration, the operating speed of the PMOSFET 2 and the operating speed of the NMOSFET 3 are different. For example, the operating speed of the NMOSFET 3 is two to three times that of the PMOSFET 2. In addition, when the gate width Wg per finger of the PMOSFET 2 and the NMOSFET 3 is the same, the logic threshold voltage V th is the power supply voltage V connected to the drain side of the MOSFET dd It will be lower than half the value of.

[0017] The logic threshold voltage V th When V is low, the power supply voltage V connected to the source side of the MOSFET ss Therefore, the logic threshold voltage V th is the power supply voltage V dd It is desirable that the value be approximately half that of the above.

[0018] Logic threshold voltage V of standard cell 1 th supply voltage V dd In order to reduce this to about half, for example, it is possible to increase the number of fingers in the PMOSFET (see Fig. 2(a)) or to increase the gate width of the PMOSFET (see Fig. 2(b)).

[0019] Figure 2(a) shows the logic threshold voltage V th supply voltage V dd In order to reduce the number of fingers to about half, a standard cell is illustrated in which the number of fingers of the PMOSFET is three for one finger of the NMOSFET 3.

[0020] However, when the number of fingers of the PMOSFET is increased to three, the gate length of the PMOSFET must be increased to two to three times that of the NMOSFET. Therefore, in this method, the cell area of ​​the PMOSFET increases, resulting in an increase in the layout area and manufacturing cost. In addition, the cell size of the standard cell 1 also increases.

[0021] In addition, in Fig. 2(b), the logic threshold voltage V th supply voltage V dd In order to make the gate width W of the PMOSFET about half, g is the gate width W of the NMOSFET g Illustrated is a standard cell that is larger than the

[0022] 2(a), this method also increases the cell area of ​​the PMOSFET2, which in turn increases the layout area and manufacturing cost, and also increases the cell size of the standard cell 1.

[0023] Furthermore, the number of fingers and the gate width W g In the standard cell 1 having a different PMOSFET2 and NMOSFET3, the boundary position between the PMOSFET2 and NMOSFET3 may deviate from the center position of the cell height of the standard cell 1. In addition, if the boundary position between the PMOSFET2 and NMOSFET3 deviates from the specified position due to manufacturing variations, etc., the logic threshold voltage V th is the power supply voltage V dd If the value deviates from half of the original value, noise resistance may be reduced.

[0024] In the technical field of integrated circuits that integrate semiconductor elements, efforts are being made to increase the integration density of semiconductor elements such as transistors to improve performance. For this reason, there is a demand for a miniaturized structure for standard cells 1 that include semiconductor elements, but it is difficult to achieve miniaturization using the above-mentioned techniques. Therefore, in this embodiment, a multi-V th Standard cells are provided.

[0025] (Multi-V th About logic circuit design using standard cells Given the above background, Multi-V thA logic circuit design using standard cells (hereinafter referred to as "MV standard cells") will be described below. Fig. 3 is a diagram showing an example of a hardware configuration of a logic circuit design device according to the present disclosure. As shown in Fig. 3, a logic circuit design device 10 includes, for example, a CPU (Central Processing Unit: processor) 11, a main memory 12, a secondary storage 13, a communication interface 14, an input unit 15 including a keyboard, a mouse, etc., and a display unit 16 including a liquid crystal display device or the like for displaying data. These units are connected to each other directly or indirectly via a bus 18, and cooperate with each other to execute various processes.

[0026] The CPU 11 controls the logic circuit design device 10 using, for example, an OS (Operating System) stored in a secondary storage device 13 connected via a bus, and executes various processes by executing various programs stored in the secondary storage device 13. One or more CPUs 11 may be provided, and they may cooperate with each other to realize processes.

[0027] The main memory device 12 is composed of writable memory such as a cache memory or a RAM (Random Access Memory), and is used as a working area for reading out the execution program of the CPU 11, writing processing data by the execution program, and the like.

[0028] The secondary storage device 13 is a non-transitory computer readable storage medium. The secondary storage device 13 is, for example, a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM, a semiconductor memory, or the like. Examples of the secondary storage device 13 include a ROM (Read Only Memory), a HDD (Hard Disk Drive), an SSD (Solid State Drive), and a flash memory. The secondary storage device 13 stores, for example, an OS for controlling the entire heat source system such as Windows (registered trademark), iOS (registered trademark), Android (registered trademark), a BIOS (Basic Input / Output System), various device drivers for operating peripheral devices in hardware, various application software, and various data and files. In addition, the secondary storage device 13 stores programs for realizing various processes, for example, a program describing arithmetic processing required to realize logic circuit design, and various data required to realize various processes. A plurality of secondary storage devices 13 may be provided, and the above-mentioned programs and data may be divided and stored in each secondary storage device 13. Furthermore, the secondary storage device 13 may be provided on a cloud, and some of the programs and data stored in the secondary storage device 13 may be provided on the cloud. A library 21 described below may be stored in the secondary storage device 13 .

[0029] The communication interface 14 communicates with other devices via a communication line and functions as an interface for transmitting and receiving information. For example, the communication interface 14 communicates with other devices by wire or wirelessly. Examples of wireless communication include communication through lines such as Bluetooth (registered trademark), Wi-Fi, mobile communication systems (3G, 4G, 5G, 6G, LTE, etc.), and wireless LAN. An example of wired communication includes communication through lines such as a wired LAN (Local Area Network).

[0030] 4 is a functional block diagram showing an example of functions of the logic circuit design device according to the present disclosure. As shown in FIG. 4, the logic circuit design device 10 includes a library 21 and an input receiving unit 22.

[0031] A plurality of standard cells are registered in the library 21. The plurality of standard cells also includes MV standard cells in which the threshold voltages of PMOSFET and NMOSFET are different.

[0032] As described above, each of the multiple MV standard cells registered in the library 21 has a different threshold voltage of the PMOSFET and a different threshold voltage of the NMOSFET. For example, the threshold voltage of the PMOSFET may be lower than the threshold voltage of the NMOSFET. Furthermore, the library 21 may register multiple types of MV standard cells each having a different combination of the threshold voltage of the first element and the threshold voltage of the NMOSFET.

[0033] For example, the threshold voltages of the PMOSFET and the NMOSFET are either a standard threshold voltage, a low threshold voltage that is a threshold lower than the standard threshold voltage, or a high threshold voltage that is a threshold higher than the standard threshold voltage. Depending on whether the threshold voltage of the first element included in the standard cell and the threshold voltage of the NMOSFET are the standard threshold voltage, the low threshold voltage, or the high threshold voltage, a number of combinations are realized.

[0034] Also, standard cells having different cell dimensions for PMOSFET and NMOSFET may be registered in the library 21. Furthermore, the library 21 may include multiple types of libraries depending on the purpose and required specifications of the standard cells used in logic circuit design.

[0035] The input receiving unit 22 receives input operations input by a designer who designs a standard cell using the library 21. Then, the logic circuit design device 10 realizes the design of a logic circuit by executing a predetermined process based on the received input operations. Note that the process of constructing a logic circuit based on the input operations can be carried out by appropriately adopting publicly known techniques (e.g., Patent Document 1, etc.), and detailed explanations thereof will be omitted here.

[0036] (MV standard cell logic threshold voltage V th About Fig. 5 is a diagram showing an example of a standard cell registered in a library of a logic circuit device according to the present disclosure. Fig. 5(a) is a diagram showing an example of a standard cell in which the threshold voltages of a PMOSFET and an NMOSFET are standard threshold voltages. Fig. 5(b) is a diagram showing an example of an MV standard cell in which the threshold voltage of a PMOSFET is a low threshold voltage and the threshold voltage of an NMOSFET is a standard threshold voltage.

[0037] The standard cell 1 in FIG. 5(a) and the MV standard cell 101 in FIG. 5(b) have different threshold voltages for the PMOSFETs 2 and 102. Here, FIG. 5(a) is the same as FIG. 1, so a description thereof will be omitted. In the MV standard cell 101 in FIG. 5(b), the cell heights of the PMOSFET 102 and NMOSFET 103 are the same, and the threshold voltage V thp is the threshold voltage V of the NMOSFET 103. thn Lower than.

[0038] Here, the logic threshold voltage V of the MV standard cell 101 th As mentioned above, ideally, the power supply voltage V dd However, it can be changed by the threshold voltages of the PMOSFET 102 and the NMOSFET 103. Therefore, the logical threshold voltage V th The change is made by the threshold voltages of the PMOSFET 102 and the NMOSFET 103, not by the number of fingers or the gate width of the PMOSFET 102 and the NMOSFET 103.

[0039] The logic threshold voltage V of the MV standard cell 101 is shown below. th An example of a calculation method is shown below. First, when the PMOSFET 102 and the NMOSFET 103 each operate in the saturation region, the current I p and the current I of NMOSFET103 n is expressed by the following formula (1). p ,β n is a constant, and V GS is the gate-source voltage, V thp ,V thn is the threshold voltage of each of the MOSFETs 102 and 103.

number

[0040] Next, in equation (1), the gate-source voltage V GS is the power supply voltage V dd If so, the current I n is transformed into the following equation (2).

number

[0041] On the other hand, for the PMOSFET 102, V thp <0, it can be expressed by the following equation (3).

number

[0042] When the above formula (2) and formula (3) are equal, the logic threshold voltage V th is expressed by the following equation (4).

number

[0043] Here, the constant β p ,β n are values ​​that change depending on the aspect ratio of the gate length and gate width of the corresponding MOSFET. In the example shown in Figure 2, when the threshold voltages of the PMOSFET and NMOSFET are the same, the constant β p By changing the logic threshold voltage V th supply voltage V dd It was approaching half the value.

[0044] On the other hand, according to equation (4), the logic threshold voltage V th is the threshold voltage V thp That is, in the MV standard cell 101 shown in FIG. 5(b), the threshold voltage V thp is the threshold voltage V of the NMOSFET 103. thn Since the cell heights of the PMOSFET 102 and the NMOSFET 103 are the same, the logic threshold voltage V th supply voltage V dd It can be about half of that.

[0045] In addition, since the cell heights of the PMOSFET 102 and the NMOSFET 103 of the MV standard cell 101 can be made the same, the cell height of the PMOSFET 102 and the cell height of the NMOSFET 103 can be made 1:1. In other words, the boundary position between the PMOSFET 102 and the NMOSFET 103 can be set at the center position of the standard cell 1 in the cell height direction.

[0046] Fig. 6 is a graph showing the change in the logic threshold voltage of the standard cell due to the change in the threshold voltage of the PMOSFET. In Fig. 6, the solid line corresponds to the standard cell 1 in Fig. 5(a), and the dashed line corresponds to the MV standard cell 101 in Fig. 5(b). As shown in Fig. 6, the standard cell and the MV standard cell have the same configuration, except that the threshold voltage of the PMOSFET is the same or lower than the threshold voltage of the NMOSFET. In Fig. 6, the intersection of the solid line and the dashed line indicates the threshold voltage of the standard cell. Similarly, the intersection of the dashed line and the dashed line indicates the threshold voltage of the MV standard cell.

[0047] The threshold voltage of the MV standard cell indicated by the intersection of the dashed line and the dashed line ("●" in Fig. 6) is higher than the threshold voltage of the standard cell indicated by the intersection of the solid line and the dashed line ("■" in Fig. 6) because the threshold voltage of the PMOSFET is lower than the threshold voltage of the NMOSFET. As a result of the improvement in the logic threshold voltage, the power supply voltage V ss This improves the resistance to noise generated by the

[0048] As described above, the MV standard cell 101 is configured to detect the threshold voltage V thp is the threshold voltage V of the NMOSFET 103. thn Since the cell heights of the PMOSFET 102 and the NMOSFET 103 are the same, the logic threshold voltage V th supply voltage V dd In addition, the improvement in the logic threshold voltage reduces the power supply voltage V ss This improves the resistance to noise generated by the

[0049] Since the MV standard cells 101 are registered in the library of a logic circuit design device, a designer of a logic circuit using standard cells can design the logic circuit using the MV standard cells 101 registered in the library. This allows for greater freedom in designing logic circuits using standard cells that require miniaturization, without being subject to restrictions such as process rules and layout rules. Furthermore, since restrictions on design are relaxed, the burden on designers who design logic circuits can be reduced.

[0050] Furthermore, there are a plurality of types of MV standard cells 101, each of which has a different combination of the threshold voltage of the PMOSFET 102 and the threshold voltage of the NMOSFET 103. The plurality of MV standard cells 101 may be registered in a library of a logic circuit device. The plurality of MV standard cells 101 may be, for example, one in which the PMOSFET 102 has a low threshold voltage and the NMOSFET 103 has a standard threshold voltage, one in which the PMOSFET 102 has a low threshold voltage and the NMOSFET 103 has a high threshold voltage, one in which the PMOSFET 102 has a standard threshold voltage and the NMOSFET 103 has a high threshold voltage, etc.

[0051] In this way, by registering multiple types of MV standard cells in the library, designers can select MV standard cells according to the design specifications of various logic circuits, which relaxes the restrictions on standard cells in logic circuit design and further expands the degree of freedom in design.

[0052] (Application to clock buffer cells) The MV standard cell 101 may be used as a clock buffer cell that is inserted to eliminate delay differences between clock signals when the clock signals are transmitted to a plurality of logic circuits. 7A and 7B are diagrams showing an example of a case where the MV standard cell according to the present disclosure is used as a clock buffer cell. Fig. 7(a) is a diagram showing an example of a clock buffer cell using a conventional standard cell. Fig. 7(b) is a diagram showing an example of a clock buffer cell using an MV standard cell.

[0053] In the clock buffer cell 201 illustrated in FIG. 7(a), the threshold voltages of the PMOSFET 202 and the NMOSFET 203 are the same as in the conventional standard cell, and the logical threshold voltage is the power supply voltage V ddIn order to make the driving capability ratio of the PMOSFET 202 and the NMOSFET 203 about half of the conventional clock buffer cell, the driving capability ratio of the PMOSFET 202 and the NMOSFET 203 has been adjusted. Specifically, for example, the number of fingers or the gate width of the PMOSFET 202 has been increased to adjust the driving capability ratio of the PMOSFET 202 and the NMOSFET 203. In this case, the area of ​​the clock buffer cell increases.

[0054] On the other hand, the clock buffer cell 205 using the MV standard cell illustrated in FIG. 7B has a logic threshold voltage of 100 V. dd The threshold voltage of the PMOSFET 206 is adjusted to be lower than the threshold voltage of the NMOSFET 207 to be about half of that of the NMOSFET 207. This makes it possible to reduce the increase in the number of fingers and gate width of the PMOSFET 206 when the number of fingers and gate width of the PMOSFET 206 are increased more than the number of fingers and gate width of the NMOSFET 207. That is, it is possible to prevent the area of ​​the clock buffer cell from becoming larger than that of a clock buffer cell using a conventional standard cell. This contributes to the miniaturization of a logic circuit including the clock buffer cell.

[0055] As described above, the logic circuit design device according to this embodiment provides the following advantageous effects. For example, according to the logic circuit design device of this embodiment, an MV standard cell 101 including a PMOSFET 102 and an NMOSFET 103 having different polarities and threshold voltages is registered in the library 21. A logic circuit designer can design a logic circuit using the MV standard cell 101 registered in the library 21. This can improve the degree of freedom in designing a logic circuit using standard cells that require miniaturization, against restrictions such as process rules and layout rules. In addition, since restrictions on design are relaxed, the burden on the designer who designs the logic circuit can be reduced.

[0056] In addition, multiple types of MV standard cells may be registered in the library. This allows designers to select MV standard cells according to the design specifications of various logic circuits. This relaxes restrictions on standard cells in logic circuit design, further expanding the degree of freedom in design.

[0057] Although the present disclosure has been described above using the embodiments, the technical scope of the present disclosure is not limited to the scope described in the above embodiments. Various modifications or improvements can be made to the above embodiments without departing from the gist of the present disclosure, and the forms in which such modifications or improvements are made are also included in the technical scope of the present disclosure. In addition, the above embodiments may be appropriately combined. [Explanation of symbols]

[0058] 1 Standard Cell 2 PMOSFET 3 NMOSFET 4,5 Active Area 6 Finger 10 Logic circuit design equipment 11 CPU 12 Main storage 13 Secondary storage device 14 Communication Interface 15 Input section 16 Display section 18 Bus 21 Library 22 Input reception section 101 Multi-V th Standard Cell (MV Standard Cell) 102 PMOSFET 103 NMOSFET 201 Clock Buffer Cell 202 PMOSFET 203 NMOSFET 205 Clock Buffer Cell 206 PMOSFET 207 NMOSFET

Claims

1. A logic circuit design device for designing a logic circuit using standard cells composed of a plurality of elements, A library in which multiple standard cells are registered; An input receiving means for receiving information input by a user; Equipped with The plurality of standard cells include a multi-voltage (MV) transistor having a first element of a first polarity and a second element of a second polarity opposite to the first polarity and having a threshold voltage different from that of the first element. ｔｈ ) A logic circuit design device that includes standard cells.

2. 2. The logic circuit design device according to claim 1, wherein the first element and the second element included in the MV standard cell have the same cell height, and the threshold voltage of the first element is lower than the threshold voltage of the second element.

3. 2 . The logic circuit design device according to claim 1 , wherein the first element and the second element included in the MV standard cell have a threshold voltage of the first element lower than a threshold voltage of the second element.

4. A plurality of the MV standard cells are registered in the library, 2. The logic circuit design device according to claim 1, wherein the plurality of MV standard cells each have a different combination of the threshold voltage of the first element and the threshold voltage of the second element.

5. A logic circuit design method for designing a logic circuit using standard cells composed of a plurality of elements, comprising the steps of: A multi-voltage transistor (MV) having a first element of a first polarity and a second element of a second polarity opposite to the first polarity and having a threshold voltage different from that of the first element. ｔｈ A library in which multiple standard cells including the standard cell are registered, An input receiving means for receiving information input by a user; A logic circuit design method using

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