Low distortion amplifier

Abstract

To provide a low distortion amplifier capable of reducing adjustment time for compensation of distortion characteristics and performing compensation of distortion characteristics according to individual differences in performances of power amplifiers.SOLUTION: A low distortion amplifier 100 includes: an A / D converter 1a that converts an input signal to a first digital signal; an output signal detection unit 2 that extracts a part of an output signal as a feedback signal; an A / D converter 1b that converts the feedback signal to a second digital signal; a distortion compensation coefficient calculation unit 12 that compares phases and amplitudes by analyzing the first digital signal and the second digital signal, and calculates a distortion compensation coefficient based on the results of comparison; a generation unit 14 that generates a digital baseband signal with distortion characteristics compensated based on the first digital signal and the result of calculation of the distortion compensation coefficient; a D / A converter 3 that converts the digital baseband signal to an analog signal; and a power amplifier 20 that amplifies the analog signal and outputs the output signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a low distortion amplifier that is installed in, for example, a transmitter or a communication device. [Background technology]

[0002] In a transmitter used for communication purposes, a power amplifier mounted inside the transmitter may cause distortion characteristics in an output signal, so techniques for compensating for the distortion characteristics have been developed.

[0003] For example, Japanese Patent Laid-Open Publication No. 2016-032127 (Patent Document 1) discloses a communication device that employs predistortion to compensate for the distortion characteristics of an output signal. The communication device disclosed in Patent Document 1 generates a predistortion signal by multiplying a transmission baseband signal by a distortion compensation coefficient corresponding to the power value of the transmission baseband signal.

[0004] Japanese Patent Application Laid-Open No. 2010-233055 discloses a distortion compensation circuit capable of adjusting the distortion compensation characteristics. Specifically, the distortion compensation characteristics are adjusted by the values ​​of inductors and the like that constitute the distortion compensation circuit. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2016-032127 A [Patent Document 2] JP 2010-233055 A Summary of the Invention [Problem to be solved by the invention]

[0006] The technique disclosed in Patent Document 1 uses a distortion compensation coefficient according to the power value of a transmission baseband signal, and therefore cannot adequately compensate for distortion characteristics according to individual differences in the performance of power amplifiers.

[0007] Generally, multiple power amplifiers may be arranged in parallel to obtain a high output signal. When the technology of Patent Document 1 is applied to a transmitter in which multiple power amplifiers are arranged in parallel, compensation for distortion characteristics is performed collectively on a signal obtained by combining output signals of the multiple power amplifiers. When compensation for distortion characteristics is performed collectively on multiple power amplifiers, compensation for distortion characteristics is not optimized for each individual power amplifier. Therefore, when the distortion characteristics of a specific individual power amplifier are poor, the overall performance of the multiple power amplifiers is affected by the distortion characteristics of the specific individual. As a result, the maximum performance inherent to the transmitter is not fully utilized.

[0008] On the other hand, the technique disclosed in Patent Document 2 makes it possible to adjust the distortion compensation characteristics in accordance with individual differences in the performance of the power amplifier, but it takes time for testing and adjustment to find the optimum values ​​for the inductors and the like.

[0009] The present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a low-distortion amplifier in which distortion characteristics are compensated for in accordance with individual differences in performance of power amplifiers, and the adjustment time for compensating for the distortion characteristics can be reduced. [Means for solving the problem]

[0010] A low distortion amplifier according to an aspect of the present disclosure receives an input signal and outputs an output signal. The low distortion amplifier includes a first A / D converter, an output signal detection unit, a second A / D converter, a distortion compensation coefficient calculation unit, a generation unit, a D / A converter, and a power amplifier. The first A / D converter converts the input signal into a first digital signal. The output signal detection unit extracts a part of the output signal as a feedback signal. The second A / D converter converts the feedback signal into a second digital signal. The distortion compensation coefficient calculation unit compares the phase and amplitude of the first digital signal and the second digital signal by analyzing the first digital signal and the second digital signal, and calculates a distortion compensation coefficient based on the comparison result. The generation unit generates a digital baseband signal with compensated distortion characteristics based on a calculation result of the first digital signal and the distortion compensation coefficient. The D / A converter converts the digital baseband signal into an analog signal. The power amplifier amplifies the analog signal and outputs an output signal. Effect of the Invention

[0011] The low distortion amplifier according to the present disclosure compensates for distortion characteristics in accordance with individual differences in performance of power amplifiers, and can reduce the adjustment time required for compensating for distortion characteristics. [Brief description of the drawings]

[0012] [Figure 1] 1 is a diagram showing a configuration of a low distortion amplifier according to a first embodiment. [Diagram 2] 4 is a diagram showing a flow of distortion compensation processing of the low distortion amplifier according to the first embodiment. [Diagram 3] FIG. 11 is a diagram showing a configuration of a low distortion amplifier according to a second embodiment. [Figure 4] FIG. 11 is a block diagram showing configurations of a power amplifier and an output signal detection unit included in a low distortion amplifier according to a third embodiment. [Diagram 5] 13 is a diagram showing a flow of distortion compensation processing of the low distortion amplifier according to the third embodiment. [Figure 6] FIG. 11 is a block diagram showing configurations of a power amplifier and an output signal detection unit included in a low distortion amplifier according to a fourth embodiment. [Figure 7]FIG. 11 is a diagram showing a flow of distortion compensation processing in the low distortion amplifier according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In addition, the same or corresponding parts in the drawings are given the same reference numerals and the description thereof will not be repeated. The embodiments and modifications described below may be appropriately and selectively combined.

[0014] Embodiment 1 Fig. 1 is a diagram showing the configuration of a low-distortion amplifier according to a first embodiment. The low-distortion amplifier 100 according to the first embodiment is built into a transmitter or a communication device, receives an analog input signal of a carrier frequency (RF (Radio Frequency)), and outputs an analog output signal whose power has been amplified. As shown in Fig. 1, the low-distortion amplifier 100 includes A / D (analog / digital) converters 1a and 1b, an output signal detection unit 2, a D / A (digital / analog) converter 3, a digital predistorter 10, and a power amplifier 20.

[0015] The A / D converter 1a corresponds to a first A / D converter, and converts an analog input signal into a digital signal (hereinafter referred to as a "first digital signal").

[0016] The output signal detector 2 extracts a part of the output signal from the power amplifier 20 as a feedback signal (analog).

[0017] The A / D converter 1b corresponds to a second A / D converter, and converts the feedback signal extracted by the output signal detection unit 2 into a digital signal (hereinafter referred to as a "second digital signal").

[0018] The digital predistorter 10 generates a digital baseband signal by causing the signal generator 13 to generate a digital signal having the inverse distortion characteristic of the distortion characteristic generated in the power amplifier 20. The digital predistorter 10 may be realized by a processor that executes a computer program, or may be realized by a logic circuit including a plurality of electronic components.

[0019] The D / A converter 3 converts the digital baseband signal generated by the digital predistorter 10 into an analog signal.

[0020] The power amplifier 20 generates an output signal by amplifying the analog signal output from the D / A converter 3 to a specified power level, and outputs the generated output signal. The analog signal output from the D / A converter 3 is obtained by analog converting a digital baseband signal having distortion characteristics opposite to those generated in the power amplifier 20. Therefore, in the output signal output from the power amplifier 20, the distortion characteristics caused by the power amplifier 20 are compensated for.

[0021] The digital predistorter 10 includes a distortion compensation coefficient calculation unit 12 and a generation unit 14 . The distortion compensation coefficient calculation section 12 analyzes the first digital signal and the second digital signal to compare the phase and amplitude of the first digital signal with that of the second digital signal, and calculates a distortion compensation coefficient based on the comparison result.

[0022] Specifically, the distortion compensation coefficient calculation unit 12 analyzes the first digital signal and the second digital signal, compares the waveforms of the first digital signal and the second digital signal, and identifies the distortion characteristics occurring in the power amplifier 20. That is, the distortion compensation coefficient calculation unit 12 calculates the phase difference between the first digital signal and the second digital signal. Furthermore, the distortion compensation coefficient calculation unit 12 calculates the amplitude ratio between the first digital signal and the second digital signal whose phase has been adjusted by the phase difference.

[0023] Based on the calculated phase difference and amplitude ratio, the distortion compensation coefficient calculation unit 12 calculates a distortion compensation coefficient for generating a distortion characteristic that is the inverse of the distortion characteristic generated in the power amplifier 20 so that the feedback signal has a distortion-free waveform (sine waveform).

[0024] The generation unit 14 generates a digital baseband signal in which the distortion characteristics generated in the power amplifier 20 are compensated for, based on a result of an operation using the first digital signal and the distortion compensation coefficient. The generation unit 14 includes a distortion compensation operation unit 11 and a signal generation unit 13.

[0025] The distortion compensation calculation unit 11 calculates (typically multiplies) the first digital signal by a distortion compensation coefficient to generate transmission data for generating a digital baseband signal with compensated distortion characteristics. The transmission data includes amplitude data indicating the amplitude and phase data indicating the phase.

[0026] The signal generating unit 13 generates a digital baseband signal with compensated distortion characteristics, based on the transmission data generated by the distortion compensation calculating unit 11. The digital baseband signal is a signal in which the inverse distortion characteristics to those generated in the power amplifier 20 are imparted to the first digital signal.

[0027] 2 is a diagram showing a flow of distortion compensation processing of the low distortion amplifier according to embodiment 1. As shown in Fig. 2, the distortion compensation processing includes an initial setting phase and an operation phase. After performing processing of the initial setting phase, the low distortion amplifier 100 starts processing of the operation phase.

[0028] In the initial setting phase, steps S1 to S4 are executed. In step S1, the distortion compensation coefficient calculation unit 12 analyzes a first digital signal obtained by the A / D converter 1a performing AD conversion on the input signal. The distortion compensation coefficient calculation unit 12 analyzes the first digital signal to obtain information on the input signal (for example, information indicating a modulation method or an amplitude level). The distortion compensation coefficient calculation unit 12 may obtain the information on the input signal from a signal source (not shown).

[0029] In the next step S2, the distortion compensation coefficient calculation unit 12 sends information on the input signal to the distortion compensation calculation unit 11. The distortion compensation calculation unit 11 generates transmission data based on the information on the input signal. The signal generation unit 13 generates a reference digital baseband signal (hereinafter referred to as a "reference signal") based on the transmission data.

[0030] In step S2, since the distortion compensation coefficient is not set, a digital baseband signal with compensated distortion characteristics is not generated. Therefore, the distortion compensation calculation unit 11 generates transmission data including, for example, amplitude data indicating the amplitude of the first digital signal and phase data indicating the same phase as the first digital signal. As a result, the signal generation unit 13 outputs the first digital signal as a reference signal.

[0031] The reference signal output from the signal generating unit 13 is converted into an analog signal by the D / A converter 3. The analog signal is amplified to a specified power level by the power amplifier 20. The output signal detecting unit 2 extracts a part of the output signal from the power amplifier 20 as a feedback signal. The feedback signal is converted into a second digital signal by the A / D converter 1b and fed back to the digital predistorter 10.

[0032] In the next step S3, the distortion compensation coefficient calculation unit 12 of the digital predistorter 10 analyzes the second digital signal to obtain information on the feedback signal (for example, information indicating the modulation method or the amplitude level).

[0033] In the next step S4, the distortion compensation coefficient calculation unit 12 compares the phase and amplitude of the first digital signal and the second digital signal based on the information of the input signal acquired in step S1 and the information of the feedback signal acquired in step S3. The comparison result includes the phase difference between the first digital signal and the second digital signal, and the amplitude ratio between the first digital signal and the second digital signal whose phase has been adjusted by the phase difference. The distortion compensation coefficient calculation unit 12 identifies distortion characteristics occurring in the power amplifier 20 based on the comparison result, and sets a distortion compensation coefficient corresponding to the inverse distortion characteristics of the identified distortion characteristics (step S4). In this way, the distortion compensation coefficient is set in the initial setting phase.

[0034] In the operation phase, steps S5 to S8 are executed. In step S5, the distortion compensation coefficient calculation unit 12 analyzes a first digital signal obtained by the A / D converter 1a performing AD conversion on the input signal. The distortion compensation coefficient calculation unit 12 analyzes the first digital signal to obtain information on the input signal (for example, information indicating a modulation method or an amplitude level). The distortion compensation coefficient calculation unit 12 may obtain the information on the input signal from a signal source (not shown).

[0035] In the next step S6, the distortion compensation coefficient calculation unit 12 outputs the set distortion compensation coefficient to the generation unit 14. In the first step S6 after the end of the initial setting phase, the distortion compensation coefficient set in the initial setting phase is output to the generation unit 14. In step S6 after the distortion compensation coefficient is updated in step S8 described later, the updated distortion compensation coefficient is output to the generation unit 14. The generation unit 14 performs a calculation between the first digital signal and the distortion compensation coefficient, and generates a digital baseband signal (hereinafter may be referred to as a "distortion compensation signal") whose distortion characteristics have been compensated for, based on the calculation result.

[0036] The distortion compensation signal output from the generator 14 is converted into an analog signal by the D / A converter 3. The analog signal is amplified to a specified power level by the power amplifier 20. The output signal detector 2 extracts a part of the output signal from the power amplifier 20 as a feedback signal. The feedback signal is converted into a second digital signal by the A / D converter 1b and fed back to the digital predistorter 10.

[0037] In the next step S7, the distortion compensation coefficient calculation unit 12 of the digital predistorter 10 analyzes the second digital signal to obtain information on the feedback signal (for example, information indicating a modulation method or an amplitude level). The distortion compensation coefficient calculation unit 12 compares the phase and amplitude of the first digital signal with the second digital signal based on the information on the input signal obtained in step S5 and the information on the feedback signal obtained in step S7. The comparison result includes the phase difference between the first digital signal and the second digital signal, and the amplitude ratio between the first digital signal and the second digital signal whose phase has been adjusted by the phase difference. The distortion compensation coefficient calculation unit 12 determines whether the calculation process of the distortion compensation coefficient has converged based on the comparison result. For example, the distortion compensation coefficient calculation unit 12 determines that the calculation process of the distortion compensation coefficient has converged when the phase difference and the amplitude ratio are within a reference range. When the distortion compensation coefficient calculation unit 12 determines that the calculation process of the distortion compensation coefficient has not converged, the distortion compensation coefficient calculation unit 12 performs the process of step S8. On the other hand, if the distortion compensation coefficient calculation unit 12 determines that the calculation process of the distortion compensation coefficient has converged, it omits the process of step S8 and does not update the distortion compensation coefficient.

[0038] In step S8, the distortion compensation coefficient calculation unit 12 updates the distortion compensation coefficient so as to cancel the phase difference and add a compensation amount such that the amplitude ratio corresponds to a specified amplification factor. After step S8, steps S6 to S8 are repeated again.

[0039] In this way, the power amplifier 20 performs distortion compensation of the output signal by the digital predistorter 10 corresponding to the power amplifier 20. Therefore, it is possible to compensate for the distortion characteristics corresponding to the individual differences in the performance of the power amplifier 20, and it is possible to reduce the adjustment time for compensating for the distortion characteristics regardless of the individual differences in the performance of the power amplifier 20.

[0040] Embodiment 2 Fig. 3 is a diagram showing the configuration of a low distortion amplifier according to embodiment 2. As shown in Fig. 3, low distortion amplifier 100A according to embodiment 2 differs from low distortion amplifier 100 according to embodiment 1 in that it includes frequency converters 15a to 15c.

[0041] Frequency converter 15a corresponds to a first frequency converter, converts the frequency of an input signal, and outputs the frequency-converted (down-converted) input signal to A / D converter 1a.

[0042] Frequency converter 15b corresponds to a second frequency converter, and performs frequency conversion (down-conversion) of the feedback signal, and outputs the frequency-converted feedback signal to A / D converter 1b.

[0043] The frequency converter 15c corresponds to a third frequency converter, and converts (up-converts) the frequency of the analog signal output from the D / A converter 3, and outputs the frequency-converted analog signal to the power amplifier 20.

[0044] According to the low distortion amplifier 100A of the second embodiment, even if the input signal contains frequency components that cannot be A / D converted (handled) by the A / D converters 1a, 1b (frequency components outside the operable range of the A / D converters 1a, 1b) or frequency components that cannot be D / A converted (handled) by the D / A converter 3 (frequency components outside the operable range of the D / A converter 3), the frequency converters 15a to 15c convert the frequency components into frequencies that can be handled by the A / D converters 1a, 1b and the D / A converter 3 (frequencies within the operable ranges of the A / D converters 1a, 1b and the D / A converter 3).

[0045] The types of frequency converters 15a to 15c are appropriately determined according to the high-frequency components contained in the input signal. Alternatively, each of frequency converters 15a to 15c may be replaced by a plurality of frequency converters connected in series (cascade) in multiple stages that sequentially convert the frequencies of the high-frequency components contained in the input signal according to the high-frequency components contained in the input signal.

[0046] The frequency of the signal converted and output by frequency converter 15a, the frequency of the signal converted and output by frequency converter 15b, and the frequency of the signal input to frequency converter 15c and then frequency converted are the same. Similarly, the frequency of the signal input to frequency converter 15a, the frequency of the signal input to frequency converter 15b, and the frequency of the signal output from frequency converter 15c are the same.

[0047] Thus, in addition to the effects of embodiment 1, embodiment 2 can compensate for distortion characteristics even at frequencies that cannot be directly handled by the A / D converter and D / A converter (frequencies outside the operable ranges of the A / D converter and D / A converter).

[0048] Embodiment 3 The low distortion amplifier according to the third embodiment has a configuration similar to that of the low distortion amplifier 100 according to the first embodiment or the low distortion amplifier 100A according to the second embodiment. However, in the low distortion amplifier according to the third embodiment, the power amplifier 20 is controlled to further improve the effect of compensating for the distortion characteristics in the first and second embodiments.

[0049] 1 or 3, the distortion compensation calculation unit 11 of the digital predistorter 10 outputs a distortion compensation control signal to the power amplifier 20. The power amplifier 20 controls the power supply voltage (i.e., the drain-source voltage (hereinafter referred to as the "drain voltage")) of at least one power amplification transistor among one or more built-in power amplification transistors in accordance with the distortion compensation control signal.

[0050] The distortion compensation calculation unit 11 outputs a distortion compensation control signal when the calculation process of the distortion compensation coefficient does not converge even after performing steps S6 to S8 shown in FIG. 2 a specified number of times.

[0051] The distortion compensation control signal may include a signal indicating a control amount of a drain voltage of a power amplifying transistor included in the power amplifier 20. Furthermore, the distortion compensation control signal may include a signal indicating a phase difference between the first digital signal and the second digital signal.

[0052] The distortion compensation calculation unit 11 may set the control amount of the drain voltage based on the result of comparing the phases of the first digital signal and the second digital signal. For example, the distortion compensation calculation unit 11 sets the control amount of the drain voltage according to the phase difference between the first digital signal and the second digital signal. Typically, the distortion compensation calculation unit 11 sets the control amount of the drain voltage by referring to a lookup table that associates the phase difference with the control amount of the drain voltage. The lookup table is created in advance so that the distortion is compensated for.

[0053] FIG. 4 is a block diagram showing configurations of a power amplifier and an output signal detection unit included in the low distortion amplifier according to the third embodiment.

[0054] As shown in Fig. 4, the power amplifier 20 includes power amplification transistors 21a to 21d, a variable attenuator 22, a phase shifter 23, and a power amplifier control unit 26. The power amplification transistor 21a, the variable attenuator 22, the phase shifter 23, and the power amplification transistors 21b, 21c, and 21d are connected in series in this order. The output signal detection unit 2 includes an output signal detection circuit 24. Furthermore, a circulator 25 is provided in the subsequent stage of the output signal detection circuit 24.

[0055] Each of the power amplification transistors 21a to 21d amplifies an input analog signal (corresponding to the analog-converted digital baseband signal in the first embodiment). The signal amplified by the power amplification transistor 21d arranged at the last stage passes through the output signal detection circuit 24 and the circulator 25, and is output as an output signal of the low distortion amplifier. The output signal detection circuit 24 extracts a part of the output signal of the low distortion amplifier as a feedback signal. As described in the first embodiment, the feedback signal is output to the A / D converter 1b.

[0056] The variable attenuator 22 attenuates the amplitude of the input analog signal. The amount of attenuation by the variable attenuator 22 is set by the power amplifier control unit 26. When the variable attenuator 22 is a voltage variable attenuator, the amount of attenuation by the variable attenuator 22 varies depending on the voltage applied to the variable attenuator 22. When the variable attenuator 22 is a digital step attenuator, the amount of attenuation by the variable attenuator 22 varies depending on the digital signal to the variable attenuator 22.

[0057] The phase shifter 23 adjusts (delays) the phase of the input analog signal. The amount of phase delay by the phase shifter 23 is set by the power amplifier control unit 26.

[0058] The power amplifier control unit 26 controls whether the voltage applied from the external power supply to the power amplifier transistors 21a to 21d is set to an ON potential or an OFF potential in response to the main control signal. When the low distortion amplifier 100 is for a pulse radar, the main control signal may include a signal for controlling pulse timing. The main control signal is input to the power amplifier control unit 26 from a main controller (not shown).

[0059] In response to receiving a distortion compensation control signal from the distortion compensation calculation unit 11, the power amplifier control unit 26 controls the power supply voltage (drain voltage) of the power amplification transistors 21a to 21d, the amount of attenuation by the variable attenuator 22, and the amount of phase delay by the phase shifter 23. The power amplifier control unit 26 includes a power supply control unit 261 and a phase / amplitude control unit 262.

[0060] The power supply control unit 261 controls the drain voltage of at least one of the power amplification transistors 21a to 21d as a control target in response to receiving a distortion compensation control signal from the distortion compensation calculation unit 11. The power supply control unit 261 may determine all of the power amplification transistors 21a to 21d as control targets, or may determine some of the power amplification transistors 21a to 21d as control targets. In the example shown in Fig. 4, the power supply control unit 261 determines the power amplification transistors 21c and 21d as control targets, and sets the drain voltages of the power amplification transistors 21a and 21b to a fixed voltage.

[0061] As an example, the power supply control unit 261 boosts the drain voltage of the power amplification transistor to be controlled within a range that does not cause a breakdown. By boosting the drain voltage, the saturation power of the power amplification transistor increases. In general, when the operating point of the power amplification transistor approaches a saturation region, the phase characteristic that affects the distortion characteristic of the power amplification transistor reaches an inflection point. Therefore, when the drain voltage is boosted and the saturation power increases, the phase fluctuation at the operating point of the power amplification transistor is equivalently suppressed. As a result, deterioration of the distortion characteristic is suppressed.

[0062] The power supply control unit 261 sets a predetermined amount as the boost amount of the drain voltage of the power amplification transistor to be controlled. Alternatively, when the distortion compensation control signal includes a signal indicating the control amount of the drain voltage, the power supply control unit 261 may set the boost amount of the drain voltage of the power amplification transistor to be controlled based on the signal.

[0063] The phase / amplitude control section 262 controls the amount of attenuation by the variable attenuator 22 and the amount of phase delay by the phase shifter 23 .

[0064] When the drain voltage of the power amplification transistor to be controlled is controlled by the power supply control unit 261, the power of the output signal fluctuates. Therefore, after the drain voltage is controlled by the power supply control unit 261, the phase / amplitude control unit 262 controls the attenuation amount by the variable attenuator 22 in order to adjust the power of the output signal fluctuated by the drain voltage of the power amplification transistor to a specified power level. After the drain voltage is controlled by the power supply control unit 261, the phase / amplitude control unit 262 may set the attenuation amount by the variable attenuator 22 based on the detection voltage (amplitude) of the feedback signal. The phase / amplitude control unit 262 may obtain the detection voltage of the feedback signal from the output signal detection circuit 24 or may obtain the detection voltage of the feedback signal from the digital predistorter 10.

[0065] When the variable attenuator 22 is a variable voltage attenuator, the phase / amplitude control section 262 determines the amount of attenuation to obtain a specified power level according to the feedback detection voltage (amplitude). The phase / amplitude control section 262 has an analog circuit that outputs a voltage according to the determined amount of attenuation, and applies the output voltage of this analog circuit to the variable attenuator 22. Alternatively, the phase / amplitude control section 262 may perform A / D conversion on the detection voltage (amplitude) of the feedback signal, and then generate a control signal for adjusting the power of the output signal to a specified power level, and apply a voltage obtained by D / A converting the generated control signal to the variable attenuator 22.

[0066] When the variable attenuator 22 is a digital step attenuator, the phase / amplitude control unit 262 performs A / D conversion on the detection voltage (amplitude) of the feedback signal, then generates a control signal for adjusting the power of the output signal to a specified power level, and outputs the generated control signal to the variable attenuator 22.

[0067] Even when the drain voltage is controlled by the power supply control section 261, there may be cases where the phase difference between the first digital signal and the second digital signal does not fall within the reference range. Therefore, the phase / amplitude control section 262 may control the amount of phase delay by the phase shifter 23 based on a signal (a signal indicating the phase difference between the first digital signal and the second digital signal) received from the distortion compensation calculation section 11 after the drain voltage is controlled by the power supply control section 261. Specifically, the phase / amplitude control section 262 sets the amount of phase delay by the phase shifter 23 so as to cancel out the phase difference between the first digital signal and the second digital signal, and outputs a digital signal or analog voltage indicating the set value to the phase shifter 23.

[0068] FIG. 5 is a diagram showing a flow of the distortion compensation process of the low distortion amplifier according to the third embodiment. As shown in FIG. 5, the distortion compensation process according to the third embodiment is different from the distortion compensation process shown in FIG. 3 in that it includes steps S11 to S14. Steps S11 to S14 are executed when it is determined in step S7 of the operation phase that the calculation process of the distortion compensation coefficient has not converged. Alternatively, steps S11 to S14 may be executed when it is determined N or more times consecutively that the calculation process of the distortion compensation coefficient has not converged in step S7. In other words, when it is determined in step S7 that the calculation process of the distortion compensation coefficient has not converged less than N times, steps S11 to S14 may be omitted.

[0069] In step S11, the distortion compensation calculation unit 11 determines whether or not the phase difference between the first digital signal and the second digital signal exceeds a threshold value Th1. The threshold value Th1 is determined in advance according to a phase fluctuation that occurs when the operating point of the power amplification transistor belongs to a saturation region.

[0070] If it is determined in step S11 that the phase difference exceeds the threshold value Th1, the process proceeds to step S12. In step S12, the power amplifier control unit 26 boosts the drain voltage of at least one of the power amplifier transistors 21a to 21d that is the control target, in accordance with the distortion compensation control signal from the distortion compensation calculation unit 11. After step S12, the process returns to step S7.

[0071] By executing step S12 once or a plurality of times, the saturation power of the power amplifier transistor to be controlled is improved, and the operating point of the power amplifier transistor to be controlled is moved in a direction away from the saturation region. As a result, the phase fluctuation at the operating point of the power amplifier transistor to be controlled is suppressed. As a result, the deterioration of the distortion characteristic is suppressed.

[0072] In step S11, if the phase difference does not exceed threshold value Th1, the process proceeds to step S13. In step S13, the power amplifier control unit 26 determines whether the power difference between the power of the feedback signal, which is a part of the output signal, and a specified power level exceeds threshold value Th2.

[0073] If the power difference exceeds the threshold value Th2 in step S13, the process proceeds to step S14. In step S14, the power amplifier control unit 26 adjusts the attenuation amount of the variable attenuator 22 in accordance with the control signal from the distortion compensation calculation unit 11 so that the power difference approaches 0. After step S14, the process returns to step S7.

[0074] In step S14, the amount of attenuation of the variable attenuator 22 is controlled, so that the power of the output signal that has fluctuated in response to control of the drain voltage of the power amplifying transistor is adjusted to a specified power level.

[0075] If the power difference does not exceed the threshold Th2 in step S13, the process proceeds to step S8. In step S8, the distortion compensation coefficient is updated to a value according to the state of the power amplifier 20 controlled in steps S12 and S14.

[0076] In the third embodiment, in addition to the effects of the first embodiment, by controlling the power supply voltage (drain voltage) of at least one of the multiple power amplifiers constituting power amplifier 20 and the phase / amplitude of the analog signal input to power amplifier 20, it is possible to perform more accurate distortion compensation.

[0077] Embodiment 4 In the low distortion amplifier according to the third embodiment, the digital predistorter 10 determines whether or not to control the drain voltages of the power amplification transistors 21a to 21d of the power amplifier 20. This increases the computation load on the digital predistorter 10. Therefore, in the low distortion amplifier according to the fourth embodiment, the power amplifier autonomously controls the drain voltages of the power amplification transistors 21a to 21d based on the correlation between the gate current and the fluctuation in phase characteristics with respect to the input power of the power amplification transistors 21a to 21d.

[0078] It is generally known that in the AM-PM characteristic (amplitude modulation-phase modulation characteristic) which indicates the relationship between the power of an input signal (input power) and a phase change, the phase changes as the input power increases. Also, the gate potential is determined according to the input power. The gate current depends on the gate potential. Therefore, the low distortion amplifier according to the fourth embodiment identifies a power amplification transistor which generates a phase change based on the gate current, and suppresses the phase change by controlling the drain voltage of the identified power amplification transistor.

[0079] FIG. 6 is a block diagram showing configurations of a power amplifier and an output signal detection unit included in the low distortion amplifier according to the fourth embodiment. In FIG.

[0080] As shown in FIG. 6, power amplifier 20A according to the fourth embodiment differs from power amplifier 20 shown in FIG. 4 in that it includes a power amplifier control unit 26A instead of power amplifier control unit 26, and also includes series resistors 27a, 27b and operational amplifiers 28a, 28b.

[0081] The series resistor 27a and the operational amplifier 28a correspond to a gate current detection unit that detects the gate current of the power amplifier transistor 21c. The "gate current" is a current that flows through the gate terminal. The series resistor 27a is connected in series between the gate terminal of the power amplifier transistor 21c and an external power supply. Therefore, the voltage across the series resistor 27a is equivalent to representing the gate current of the power amplifier transistor 21c. The operational amplifier 28a amplifies the voltage across the series resistor 27a. The voltage amplified by the operational amplifier 28a is output to the power amplifier control unit 26A.

[0082] The series resistor 27b and the operational amplifier 28b correspond to a gate current detection unit that detects the gate current of the power amplifier transistor 21d. The series resistor 27b is connected in series between the gate terminal of the power amplifier transistor 21d and an external power supply. Therefore, the voltage across the series resistor 27b is equivalent to representing the gate current of the power amplifier transistor 21d. The operational amplifier 28b amplifies the voltage across the series resistor 27b. The voltage amplified by the operational amplifier 28b is output to the power amplifier control unit 26A.

[0083] 4 in that it includes a power supply control unit 261A instead of the power supply control unit 261. The power supply control unit 261A differs from the power supply control unit 261 in that it controls the drain voltages of the power amplification transistors 21c, 21d in response to the voltages output from the operational amplifiers 28a, 28b, rather than the distortion compensation control signal from the distortion compensation calculation unit 11.

[0084] Specifically, the power supply control unit 261A compares the voltage output from the operational amplifier 28a with a threshold value Th3. When the voltage output from the operational amplifier 28a exceeds the threshold value Th3, the power supply control unit 261A changes the drain voltage of the power amplification transistor 21c. The threshold value Th3 is set according to the magnitude of the drain voltage of the power amplification transistor 21c, and is obtained from the value of the gate current at which a phase fluctuation appears in the power amplification transistor 21c. Therefore, the power supply control unit 261A changes the drain voltage of the power amplification transistor 21c in response to the gate current of the power amplification transistor 21c exceeding the control start threshold value corresponding to the threshold value Th3. For example, the power supply control unit 261A boosts the drain voltage of the power amplification transistor 21c by a predetermined amount within a range that does not cause a breakdown. The control start threshold value is the minimum value of the gate current at which a phase fluctuation appears in the power amplification transistor 21c, or a value close to the minimum value.

[0085] Similarly, the power supply control unit 261A compares the voltage output from the operational amplifier 28b with a threshold value Th4. When the voltage output from the operational amplifier 28b exceeds the threshold value Th4, the power supply control unit 261A changes the drain voltage of the power amplification transistor 21d. The threshold value Th4 is set according to the magnitude of the drain voltage of the power amplification transistor 21d, and is obtained from the value of the gate current at which a phase fluctuation appears in the power amplification transistor 21d. Therefore, the power supply control unit 261A changes the drain voltage of the power amplification transistor 21d in response to the gate current of the power amplification transistor 21d exceeding the control start threshold value corresponding to the threshold value Th4. For example, the power supply control unit 261A boosts the drain voltage of the power amplification transistor 21d by a predetermined amount within a range that does not cause a breakdown. The control start threshold value is the minimum value of the gate current at which a phase fluctuation appears in the power amplification transistor 21d, or a value close to the minimum value.

[0086] Fig. 7 is a diagram showing a flow of distortion compensation processing of the low distortion amplifier according to embodiment 4. As shown in Fig. 7, the distortion compensation processing according to embodiment 4 differs from the distortion compensation processing shown in Fig. 5 in that it includes step S21 instead of step S11.

[0087] In step S21, the power supply control unit 261A determines whether the gate currents of the power amplification transistors 21c and 21d exceed the control start threshold. Specifically, when the voltage output from the operational amplifier 28a exceeds a threshold Th3, the power supply control unit 261A determines that the gate current of the power amplification transistor 21c exceeds the control start threshold. Similarly, when the voltage output from the operational amplifier 28b exceeds a threshold Th4, the power supply control unit 261A determines that the gate current of the power amplification transistor 21d exceeds the control start threshold.

[0088] When the gate current of at least one of the power amplification transistors 21c, 21d exceeds the control start threshold, the power supply control unit 261A determines the power amplification transistor whose gate current exceeds the control start threshold as the power amplification transistor to be controlled, and proceeds to step S12.

[0089] If the gate current of neither of the power amplifying transistors 21c, 21d exceeds the control start threshold, the process proceeds to step S13.

[0090] According to the low distortion amplifier of the fourth embodiment, in addition to the effect of the first embodiment, the power amplifier 20A autonomously controls the drain voltage of the power amplifying transistor whose gate current exceeds the control start threshold, thereby suppressing phase fluctuations of the output signal.

[0091] Variations. In the above third and fourth embodiments, the drain voltage of the power amplifying transistor to be controlled is boosted as an example of the method of controlling the drain voltage of the power amplifying transistor to be controlled. However, the method of controlling the drain voltage of the power amplifying transistor to be controlled is not limited to this.

[0092] For example, when the power amplification transistor 21d has a phase variation characteristic opposite to that of the power amplification transistor 21c, the power supply control units 261 and 261A may perform the following process. Note that the power amplification transistor 21c corresponds to the first power amplification transistor, and the power amplification transistor 21d corresponds to the second power amplification transistor.

[0093] The power supply control unit 261, 261A determines, among the power amplifier transistors 21c, 21d, a power amplifier transistor having a phase variation characteristic opposite to that of the second digital signal relative to the first digital signal as a power amplifier transistor to be controlled. The power supply control unit 261, 261A receives a signal indicating the phase variation characteristic of the second digital signal relative to the first digital signal from the distortion compensation calculation unit 11, and determines the power amplifier transistor to be controlled based on the signal. The power supply control unit 261, 261A lowers the drain voltage of the power amplifier transistor to be controlled. By lowering the drain voltage of the power amplifier transistor to be controlled, the operating point of the power amplifier transistor to be controlled approaches the saturation region, and the phase variation of the power amplifier transistor to be controlled increases. However, the phase variation characteristic of the power amplifier transistor to be controlled is opposite to that of the second digital signal relative to the first digital signal. Therefore, the phase variation of the output signal relative to the input signal is suppressed.

[0094] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the description of the embodiments described above, and is intended to include all modifications within the meaning and scope of the claims.

[0095] Various aspects of the present disclosure are summarized below as appendices.

[0096] (Appendix 1) A low distortion amplifier that receives an input signal and outputs an output signal, a first A / D converter for converting the input signal into a first digital signal; an output signal detection unit that extracts a part of the output signal as a feedback signal; a second A / D converter for converting the feedback signal into a second digital signal; a distortion compensation coefficient calculation unit that analyzes the first digital signal and the second digital signal to compare a phase and an amplitude of the first digital signal with that of the second digital signal, and calculates a distortion compensation coefficient based on a comparison result; a generation unit that generates a digital baseband signal having a compensated distortion characteristic based on a calculation result of the first digital signal and the distortion compensation coefficient; a D / A converter for converting the digital baseband signal into an analog signal; a power amplifier that amplifies the analog signal and outputs the output signal. (Appendix 2) a first frequency converter that converts a frequency of the input signal and outputs the frequency-converted input signal to the first A / D converter; a second frequency converter that frequency-converts the feedback signal and outputs the frequency-converted feedback signal to the second A / D converter; and a third frequency converter that frequency-converts the analog signal and outputs the frequency-converted analog signal to the power amplifier. (Appendix 3) The power amplifier includes: one or more power amplifier transistors; and a control unit that controls a power supply voltage of at least one power amplification transistor among the one or more power amplification transistors based on a result of the comparison of the phases of the first digital signal and the second digital signal. (Appendix 4) The power amplifier includes: one or more power amplifier transistors; a gate current detection unit that detects a gate current of the one or more power amplification transistors; and a control unit that controls a power supply voltage of at least one power amplifying transistor, among the one or more power amplifying transistors, the gate current of which exceeds a threshold value. (Appendix 5) 5. The low distortion amplifier according to claim 3, wherein the control unit increases a power supply voltage of the at least one power amplifying transistor. (Appendix 6) the at least one power amplifying transistor includes a first power amplifying transistor and a second power amplifying transistor having a phase variation characteristic inverse to that of the first power amplifying transistor; The control unit reduces a power supply voltage of one of the first power amplifying transistor and the second power amplifying transistor, the power amplifying transistor having a phase fluctuation characteristic inverse to a phase fluctuation characteristic of the second digital signal with respect to the first digital signal. [Explanation of symbols]

[0097] 1a, 1b A / D converter, 2 output signal detection unit, 3 D / A converter, 10 digital predistorter, 11 distortion compensation calculation unit, 12 distortion compensation coefficient calculation unit, 13 signal generation unit, 14 generation unit, 15a, 15b, 15c frequency converter, 20, 20A power amplifier, 21a, 21b, 21c, 21d power amplification transistor, 22 variable attenuator, 23 phase shifter, 24 output signal detection circuit, 25 circulator, 26, 26A power amplifier control unit, 27a, 27b series resistor, 28a, 28b operational amplifier, 100, 100A low distortion amplifier, 261, 261A power supply control unit, 262 phase / amplitude control unit.

Claims

1. A low distortion amplifier that receives an input signal and outputs an output signal, a first A / D converter for converting the input signal into a first digital signal; an output signal detection unit that extracts a part of the output signal as a feedback signal; a second A / D converter for converting the feedback signal into a second digital signal; a distortion compensation coefficient calculation unit that analyzes the first digital signal and the second digital signal to compare a phase and an amplitude of the first digital signal with that of the second digital signal, and calculates a distortion compensation coefficient based on a comparison result; a generation unit that generates a digital baseband signal having a compensated distortion characteristic based on a calculation result of the first digital signal and the distortion compensation coefficient; a D / A converter for converting the digital baseband signal into an analog signal; a power amplifier that amplifies the analog signal and outputs the output signal.

2. a first frequency converter that converts a frequency of the input signal and outputs the frequency-converted input signal to the first A / D converter; a second frequency converter that converts a frequency of the feedback signal and outputs the frequency-converted feedback signal to the second A / D converter; 2. The low distortion amplifier according to claim 1, further comprising: a third frequency converter that frequency-converts the analog signal and outputs the frequency-converted analog signal to the power amplifier.

3. The power amplifier includes: one or more power amplifier transistors; a control unit that controls a power supply voltage of at least one power amplifying transistor of the one or more power amplifying transistors based on a result of the comparison of the phases of the first digital signal and the second digital signal.

4. The power amplifier includes: one or more power amplifier transistors; a gate current detection unit for detecting a gate current of the one or more power amplifying transistors; 2. The low distortion amplifier according to claim 1, further comprising: a control unit that controls a power supply voltage of at least one power amplifying transistor of which the gate current exceeds a threshold value, among said one or more power amplifying transistors.

5. 5. The low distortion amplifier according to claim 3, wherein the control section increases a power supply voltage of the at least one power amplifying transistor.

6. the at least one power amplifying transistor includes a first power amplifying transistor and a second power amplifying transistor having a phase variation characteristic inverse to a phase variation characteristic of the first power amplifying transistor; 5. The low distortion amplifier according to claim 3, wherein the control unit lowers a power supply voltage of one of the first power amplifying transistor and the second power amplifying transistor, the power amplifying transistor having a phase variation characteristic inverse to a phase variation characteristic of the second digital signal with respect to the first digital signal.

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