Semiconductor integrated circuit device, analog front-end, and sensor

Abstract

To provide a semiconductor integrated circuit device capable of reducing an output offset.SOLUTION: A semiconductor integrated circuit device (12) includes: a terminal (REF) configured to receive an external reference voltage; a first amplifier (A1) configured to receive an input signal and amplify the input signal in reference to a reference voltage; and a second amplifier (A2) configured to receive the output signal of the first amplifier and amplify the output signal of the first amplifier in reference to the external reference voltage. The reference voltage is a voltage based on the external reference voltage.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a semiconductor integrated circuit device, an analog front end, and a sensor. [Background technology]

[0002] 2. Description of the Related Art A current detection amplifier is known in the art, which generates an output voltage (sense voltage) corresponding to a voltage across a shunt resistor that detects a current (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-198217 A (paragraph 0069)

[0004] [overview] If the output offset of the current detection amplifier is large, the output accuracy of the current detection amplifier decreases. Note that even if the detection target is something other than current, if the output offset of the amplifier is large, the output accuracy of the amplifier decreases.

[0005] A semiconductor integrated circuit device disclosed in this specification includes a terminal configured to receive an external reference voltage, a first amplifier configured to receive an input signal and amplify the input signal with reference to the reference voltage, and a second amplifier configured to receive an output signal of the first amplifier and amplify the output signal of the first amplifier with reference to the external reference voltage, wherein the reference voltage is a voltage based on the external reference voltage.

[0006] The analog front end disclosed in this specification includes the semiconductor integrated circuit device having the above-described configuration, and an AD converter configured to perform AD conversion of the output of the second amplifier.

[0007] The sensor disclosed herein comprises a sensor element and an analog front end as described above configured to process an output of the sensor element. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a configuration of a current sensor according to a comparative example. [Diagram 2] FIG. 2 is a diagram showing the relationship between the external reference voltage and the output offset in the comparative example. [Diagram 3] FIG. 3 is a diagram showing a configuration of the current sensor according to the first embodiment. [Figure 4] FIG. 4 is a diagram showing the relationship between the external reference voltage and the output offset in the first embodiment. [Diagram 5] FIG. 5 is a diagram showing a configuration of a current sensor according to the second embodiment. [Figure 6] FIG. 6 is a diagram showing the relationship between the external reference voltage and the output offset in the second embodiment. [Figure 7] FIG. 7 is a diagram showing a configuration of a current sensor according to the third embodiment. [Figure 8] FIG. 8 is a diagram showing the relationship between the external reference voltage and the output offset in the third embodiment. [Figure 9] FIG. 9 is a diagram showing a modified example of the current sensor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [Detailed Description] <Current sensor (comparison example)> Fig. 1 is a diagram showing the configuration of a current sensor according to a comparative example (= a general configuration to be compared with the embodiments described later). A current sensor 100 shown in Fig. 1 is a sensor that outputs a voltage corresponding to a current flowing through a load LD.

[0010] The current sensor 100 includes a shunt resistor RS and an analog front end that processes an output of the shunt resistor RS. The analog front end of the current sensor 100 includes a semiconductor integrated circuit device 10, external resistors RO1 and RO2, an external capacitor CO, and an AD converter 20.

[0011] The shunt resistor RS is an example of a sensor element. A first end of the shunt resistor RS is externally connected to the terminal INP of the semiconductor integrated circuit device 10. A constant voltage Vcc is applied to the first end of the shunt resistor RS and the terminal INP of the semiconductor integrated circuit device 10. A second end of the shunt resistor RS and a first end of the load LD are externally connected to the terminal INM of the semiconductor integrated circuit device 10. A ground voltage is applied to the second end of the load LD. The voltage across the shunt resistor RS is proportional to the current flowing through the load LD.

[0012] The semiconductor integrated circuit device 10 generates an output voltage corresponding to the voltage across the shunt resistor RS, and outputs the output voltage from a terminal OUT to the outside of the semiconductor integrated circuit device 10. The semiconductor integrated circuit device 10 is a current detection amplifier having a circuit configuration that performs two-stage amplification. In other words, the semiconductor integrated circuit device 10 is a current detection amplifier having a circuit configuration that includes a front-stage amplifier and a rear-stage amplifier.

[0013] The semiconductor integrated circuit device 10 includes an amplifier A1 which is a front-stage amplifier, an amplifier A2 which is a rear-stage amplifier, a common mode feedback circuit CF0, capacitors C1 to C4, and resistors R3 to R6. The semiconductor integrated circuit device 10 also includes a terminal INP, a terminal INM, a terminal GND, a terminal OUT, a terminal REF, and a terminal VDD. The common mode feedback circuit CF0 includes resistors R1, R2, R7, and R8, and an error amplifier A3. The amplifier A1 is a differential input and differential output type amplifier. The amplifier A2 is a differential input and non-differential output type amplifier.

[0014] A first end of the capacitor C1 is connected to the terminal INP. A first end of the capacitor C2 is connected to the terminal INM. A second end of the capacitor C1 and a first end of the capacitor C3 are connected to the non-inverting input end of the amplifier A1. A second end of the capacitor C2 and a first end of the capacitor C4 are connected to the inverting input end of the amplifier A1.

[0015] The second terminal of the capacitor C3, the first terminal of the resistor R1, and the first terminal of the resistor R3 are connected to the inverting output terminal of the amplifier A1. The second terminal of the capacitor C4, the first terminal of the resistor R2, and the first terminal of the resistor R4 are connected to the non-inverting output terminal of the amplifier A1.

[0016] The second end of resistor R1 and the second end of resistor R2 are connected to each other. A common mode voltage VCM generated at a connection node between resistors R1 and R2 is supplied to an inverting input terminal of an error amplifier A3. Resistors R7 and R8 divide a power supply voltage Vdd to generate a reference voltage VREF. A reference voltage VREF generated at a connection node between resistors R7 and R8 is supplied to a non-inverting input terminal of an error amplifier A3. An output of the error amplifier A3 is supplied to an amplifier A1. A common mode feedback circuit CF0 applies feedback to the amplifier A1 so that the reference voltage VREF and the common mode voltage VCM become the same.

[0017] The second end of resistor R3 and the first end of resistor R5 are connected to the inverting input end of amplifier A2. The second end of resistor R4 and the first end of resistor R6 are connected to the non-inverting input end of amplifier A2. The second end of resistor R5 is connected to the output end of amplifier A2 and terminal OUT. The second end of resistor R6 is connected to terminal REF.

[0018] A power supply voltage Vdd is applied to the terminal VDD. A first end of the external capacitor CO and a first end of the external resistor RO1 are externally connected to the terminal VDD. A ground voltage is applied to the terminal GND. A second end of the external capacitor CO and a first end of the external resistor RO2 are externally connected to the terminal GND.

[0019] The second end of the external resistor RO1 and the second end of the external resistor RO2 are connected to each other. An external reference voltage VREFO generated at a connection node between the external resistor RO1 and the external resistor RO2 is applied to the terminal REF. The external resistors RO1 and RO2 divide the power supply voltage Vdd to generate the external reference voltage VREFO.

[0020] The input terminal of the AD converter 20 is externally connected to a terminal OUT. The output of the AD converter 20, which is the output of the current sensor 100, is supplied to the microcomputer 30.

[0021] In the semiconductor integrated circuit device 10, the reference for the output of the amplifier A1 is the reference voltage VREF, and the reference for the output of the amplifier A2 is the external reference voltage VREFO. The output offset OFT of the amplifier A2, which becomes the output offset of the semiconductor integrated circuit device 10, is expressed by the following formula. The matching error ΔR is the matching error between the resistance values ​​of the resistors R3 and R4 and between the resistance values ​​of the resistors R5 and R6. The voltage difference ΔV is the difference between the reference voltage VREF and the external reference voltage VREFO. The gain G is the ratio of the resistance value of the resistor R5 to the resistance value of the resistor R3. OFT=ΔR*ΔV*G

[0022] Therefore, when the resistance value of each of the resistors R3 to R6 is fixed and the reference voltage VREF is also fixed, the external reference voltage VREFO and the output offset OFT have a relationship as shown in Fig. 2. In other words, as the difference between the reference voltage VREFO and the external reference voltage VREFO increases, the output offset OFT increases.

[0023] The matching error ΔR leads to an increase in the circuit area of ​​the semiconductor integrated circuit device 10. For this reason, it is desirable to improve the output offset OFT by improving the voltage difference ΔV.

[0024] In view of the above considerations, a novel embodiment capable of reducing the output offset of a semiconductor integrated circuit device will be proposed below.

[0025] <Current Sensor (First Embodiment)> Fig. 3 is a diagram showing the configuration of a current sensor according to the first embodiment. A current sensor 101 shown in Fig. 3 is a sensor that outputs a voltage according to a current flowing through a load LD.

[0026] The current sensor 101 includes a shunt resistor RS and an analog front end that processes an output of the shunt resistor RS. The analog front end of the current sensor 101 includes a semiconductor integrated circuit device 11, external resistors RO1 and RO2, an external capacitor CO, and an AD converter 20.

[0027] The semiconductor integrated circuit device 11 differs from the above-described semiconductor integrated circuit device 10 in the configuration of the common mode feedback circuit, but is otherwise identical to the above-described semiconductor integrated circuit device 10.

[0028] The semiconductor integrated circuit device 11 includes a common mode feedback circuit CF1. The common mode feedback circuit CF1 includes resistors R1 and R2, and an error amplifier A3.

[0029] A first terminal of the resistor R1 is connected to the second terminal of the capacitor C3, the inverting output terminal of the amplifier A1, and a first terminal of the resistor R3. A first terminal of the resistor R2 is connected to the second terminal of the capacitor C4, the non-inverting output terminal of the amplifier A1, and a first terminal of the resistor R4.

[0030] The second end of resistor R1 and the second end of resistor R2 are connected to each other. A common mode voltage VCM generated at the connection node between resistor R1 and resistor R2 is supplied to the inverting input end of error amplifier A3. The non-inverting input end of error amplifier A3 is connected to the second end of resistor R6 and terminal REF. A reference voltage VREF supplied to the non-inverting input end of error amplifier A3 is equal to an external reference voltage VREFO. That is, the reference voltage VREF is the external reference voltage VREFO. The output of error amplifier A3 is supplied to amplifier A1. A common mode feedback circuit CF1 applies feedback to amplifier A1 so that the reference voltage VREF and the common mode voltage VCM become equal to each other.

[0031] In the semiconductor integrated circuit device 11, the reference voltage VREF is the external reference voltage VREFO, so the reference for the output of the amplifier A1 and the reference for the output of the amplifier A2 are both the external reference voltage VREFO. Therefore, in the semiconductor integrated circuit device 11, the voltage difference ΔV is zero, that is, the minimum.

[0032] Therefore, in the semiconductor integrated circuit device 11, when the resistance values ​​of the resistors R3 to R6 are fixed, the external reference voltage VREFO and the output offset OFT have a relationship as shown by the solid line in Fig. 4. In Fig. 4, the relationship between the external reference voltage VREFO and the output offset OFT in the semiconductor integrated circuit device 10 is shown by a thick dotted line.

[0033] As is clear from FIG. 4, the semiconductor integrated circuit device 11 can reduce the output offset OFT as compared to the semiconductor integrated circuit device 10.

[0034] <Current Sensor (Second Embodiment)> Fig. 5 is a diagram showing the configuration of a current sensor according to the second embodiment. A current sensor 102 shown in Fig. 5 is a sensor that outputs a voltage according to a current flowing through a load LD.

[0035] The current sensor 102 includes a shunt resistor RS and an analog front end that processes an output of the shunt resistor RS. The analog front end of the current sensor 102 includes a semiconductor integrated circuit device 12, external resistors RO1 and RO2, an external capacitor CO, and an AD converter 20.

[0036] The semiconductor integrated circuit device 12 differs from the above-described semiconductor integrated circuit device 10 in the configuration of the common mode feedback circuit, but is otherwise identical to the above-described semiconductor integrated circuit device 10.

[0037] The semiconductor integrated circuit device 12 includes a common mode feedback circuit CF2. The common mode feedback circuit CF2 includes resistors R1 and R2, an error amplifier A3, and resistors R7 to R9.

[0038] A first terminal of the resistor R1 is connected to the second terminal of the capacitor C3, the inverting output terminal of the amplifier A1, and a first terminal of the resistor R3. A first terminal of the resistor R2 is connected to the second terminal of the capacitor C4, the non-inverting output terminal of the amplifier A1, and a first terminal of the resistor R4.

[0039] The second end of the resistor R1 and the second end of the resistor R2 are connected to each other. A common mode voltage VCM generated at a connection node between the resistor R1 and the resistor R2 is supplied to the inverting input terminal of the error amplifier A3.

[0040] A power supply voltage Vdd is applied to a first terminal of the resistor R7. A second terminal of the resistor R7 is connected to a first terminal of the resistor R8, a first terminal of the resistor R9, and the non-inverting input terminal of the error amplifier A3. A ground voltage is applied to a second terminal of the resistor R8. A second terminal of the resistor R9 is connected to a second terminal of the resistor R6 and the terminal REF. The resistors R7 and R8 divide the power supply voltage Vdd. The resistors R8 and R9 divide the external reference voltage VREFO.

[0041] The reference voltage VREF supplied to the non-inverting input terminal of the error amplifier A3 is a voltage based on the power supply voltage Vdd and the external reference voltage VREFO. More specifically, the reference voltage VREF supplied to the non-inverting input terminal of the error amplifier A3 is a voltage based on the divided voltage of the power supply voltage Vdd and the divided voltage of the external reference voltage VREFO.

[0042] The output of the error amplifier A3 is supplied to the amplifier A1. The common mode feedback circuit CF2 applies feedback to the amplifier A1 so that the reference voltage VREF and the common mode voltage VCM become equal to each other.

[0043] In the semiconductor integrated circuit device 12, the reference voltage VREF is a voltage based on the power supply voltage Vdd and the external reference voltage VREFO. In other words, the reference voltage VREF is a voltage that follows the external reference voltage VREFO. Therefore, in the semiconductor integrated circuit device 12, the voltage difference ΔV is smaller than in the semiconductor integrated circuit device 10.

[0044] In the semiconductor integrated circuit device 12, when the resistance values ​​of the resistors R3 to R6 are fixed, the external reference voltage VREFO and the output offset OFT have a relationship as shown by the solid line in Fig. 6. In Fig. 6, the relationship between the external reference voltage VREFO and the output offset OFT in the semiconductor integrated circuit device 10 is shown by a thick dotted line.

[0045] As is clear from FIG. 6, the semiconductor integrated circuit device 12 can reduce the output offset as compared to the semiconductor integrated circuit device 10.

[0046] The error amplifier A3 needs to operate over the entire range of use of the external reference voltage VREFO. In the semiconductor integrated circuit device 11, the external reference voltage VREFO itself is supplied to the non-inverting input terminal of the error amplifier A3, whereas in the semiconductor integrated circuit device 12, a voltage based on the power supply voltage Vdd and the external reference voltage VREFO is supplied to the non-inverting input terminal of the error amplifier A3. In the semiconductor integrated circuit device 12, the voltage based on the power supply voltage Vdd and the external reference voltage VREFO can be adjusted by the resistance values ​​of the resistors R7 to R9, so that the restrictions on the range of use of the external reference voltage VREFO are less stringent than in the semiconductor integrated circuit device 11.

[0047] <Current Sensor (Third Embodiment)> Fig. 7 is a diagram showing the configuration of a current sensor according to the third embodiment. A current sensor 103 shown in Fig. 7 is a sensor that outputs a voltage according to a current flowing through a load LD.

[0048] The current sensor 103 includes a shunt resistor RS and an analog front end that processes an output of the shunt resistor RS. The analog front end of the current sensor 103 includes a semiconductor integrated circuit device 13, external resistors RO1 and RO2, an external capacitor CO, and an AD converter 20.

[0049] The semiconductor integrated circuit device 13 differs from the above-described semiconductor integrated circuit device 12 in the configuration of the common mode feedback circuit, but is otherwise identical to the above-described semiconductor integrated circuit device 12.

[0050] The semiconductor integrated circuit device 13 includes a common mode feedback circuit CF3. The common mode feedback circuit CF3 has a configuration in which a clamp circuit is added to the common mode feedback circuit CF2 provided in the semiconductor integrated circuit device 12.

[0051] The clamp circuit of the common mode feedback circuit CF3 clamps the reference voltage VREF. As the clamp circuit of the common mode feedback circuit CF3, for example, a Zener diode ZD1 as shown in FIG.

[0052] In the semiconductor integrated circuit device 13, when the resistance values ​​of the resistors R3 to R6 are fixed, the external reference voltage VREFO and the output offset OFT have a relationship as shown by the solid line in Fig. 8. In Fig. 8, the relationship between the external reference voltage VREFO and the output offset OFT in the semiconductor integrated circuit device 10 is shown by a thick dotted line.

[0053] When the external reference voltage VREF0 becomes equal to or higher than the voltage V1, the Zener diode ZD1 clamps the reference voltage VREF. In the semiconductor integrated circuit device 13, since it is possible to prevent the reference voltage VREF from becoming too large, restrictions on the range of use of the external reference voltage VREF0 are looser than in the semiconductor integrated circuit device 12.

[0054] As described above, the common mode feedback circuit CF3 of this embodiment has a configuration in which a clamp circuit that clamps the reference voltage VREF is added to the common mode feedback circuit CF2 of the second embodiment. Similarly, a clamp circuit that clamps the reference voltage VREF may be added to the common mode feedback circuit CF1 of the first embodiment.

[0055] <Other> In addition to the above-described embodiment, various modifications can be made to the configuration of the invention without departing from the spirit of the invention. The above-described embodiment should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention is indicated by the claims, not the description of the above-described embodiment, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0056] For example, the front-stage amplifier is not limited to a differential input and differential output type amplifier, and may be a differential input and non-differential output type amplifier. Fig. 9 shows a modified example of the current sensor in which the front-stage amplifier is a differential input and non-differential output type amplifier.

[0057] A current sensor 104 shown in FIG. 9 is a sensor that outputs a voltage according to a current flowing through a load LD.

[0058] The current sensor 104 includes a shunt resistor RS and an analog front end that processes an output of the shunt resistor RS. The analog front end of the current sensor 104 includes a semiconductor integrated circuit device 14, external resistors RO1 and RO2, an external capacitor CO, and an AD converter 20.

[0059] The semiconductor integrated circuit device 14 has a configuration in which the differential input and differential output type amplifier A1 in the semiconductor integrated circuit device 12 is replaced with a differential input and non-differential output type amplifier A11, the capacitors C1 to C4 are replaced with resistors R11 to R14, an amplifier A4 that receives a reference voltage VREF is added, and the resistors R1 and R2 and the error amplifier A3 are removed. The amplifier A4 is a differential input and non-differential output type amplifier. Since the inverting input terminal and the output terminal of the amplifier A4 are connected, the amplifier A4 operates as a buffer amplifier that receives the reference voltage VREF and outputs the reference voltage VREF.

[0060] <Additional Notes> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0061] A semiconductor integrated circuit device (11 to 14) of the present disclosure includes a terminal (REF) configured to receive an external reference voltage, a first amplifier (A1, A11) configured to receive an input signal and amplify the input signal based on the reference voltage, and a second amplifier (A2) configured to receive an output signal of the first amplifier and amplify the output signal of the first amplifier based on the external reference voltage, and has a configuration (first configuration) in which the reference voltage is a voltage based on the external reference voltage.

[0062] According to the semiconductor integrated circuit device of the first configuration, the output offset can be reduced.

[0063] In the semiconductor integrated circuit device of the first configuration described above, a configuration (second configuration) may be provided in which the semiconductor integrated circuit device includes common mode feedback circuits (CF1 to CF3), the first amplifier is a differential input and differential output type amplifier (A1), and the common mode feedback circuit is configured to apply feedback to the first amplifier so that the reference voltage and the common mode voltage of the first amplifier become the same.

[0064] In the semiconductor integrated circuit device of the first or second configuration, the reference voltage may be a voltage based on a predetermined voltage and the external reference voltage (third configuration).

[0065] In the semiconductor integrated circuit device of the first or second configuration, the reference voltage may be the external reference voltage (fourth configuration).

[0066] The semiconductor integrated circuit device of any one of the first to fourth configurations may have a configuration (fifth configuration) including a clamp circuit (ZD1) configured to clamp the reference voltage.

[0067] The analog front-end of the present disclosure has a configuration (sixth configuration) including the semiconductor integrated circuit device configured as described above, and an AD converter (20) configured to perform AD conversion of the output of the second amplifier.

[0068] The sensors (101 to 104) of the present disclosure have a configuration (seventh configuration) including a sensor element (RS) and the analog front end of the above configuration configured to process the output of the sensor element. [Explanation of symbols]

[0069] 10~14 Semiconductor integrated circuit device 20 AD converter 30 Microcomputer 100~104 Current sensor A1, A2, A4, A11 Amplifiers A3 Error amplifier C1~C4 capacitors CF0~CF3 Common mode feedback circuit CO External Capacitor INM, INP, GND, OUT, REF, VDD terminal LD load R1~R9 Resistors RO1, RO2 external resistors RS Shunt resistor ZD1 Zener diode

Claims

1. a terminal configured to receive an external reference voltage; a first amplifier configured to receive an input signal and amplify the input signal relative to a reference voltage; a second amplifier configured to receive the output signal of the first amplifier and amplify the output signal of the first amplifier with respect to the external reference voltage; Equipped with The reference voltage is a voltage based on the external reference voltage.

2. Equipped with a common mode feedback circuit, The first amplifier is a differential input and differential output type amplifier, 2. The semiconductor integrated circuit device according to claim 1, wherein the common mode feedback circuit is configured to apply feedback to the first amplifier so that the reference voltage and a common mode voltage of the first amplifier become equal to each other.

3. 2. The semiconductor integrated circuit device according to claim 1, wherein said reference voltage is a voltage based on a predetermined voltage and said external reference voltage.

4. 2. The semiconductor integrated circuit device according to claim 1, wherein said reference voltage is an external reference voltage.

5. 2. The semiconductor integrated circuit device according to claim 1, further comprising a clamp circuit configured to clamp the reference voltage.

6. A semiconductor integrated circuit device according to any one of claims 1 to 5, an AD converter configured to AD convert an output of the second amplifier; An analog front end comprising:

7. A sensor element; 7. An analog front end according to claim 6 configured to process an output of the sensor element; A sensor comprising:

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