Nonvolatile memory system and nonvolatile memory rewriting control method

Abstract

To provide a nonvolatile memory system capable of suppressing excessive stress on a normal cell and also ensuring a data retention margin of the normal cell.SOLUTION: In a nonvolatile memory system according to one embodiment, for an address which is determined to fail in erasing verification processing, it is determined whether or not an error is correctable, the number of addresses determined to be error correctable is counted, and when the number of addresses described above is equal to or less than a predetermined number, it is determined that the erasing processing is normal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a nonvolatile memory system and a method for controlling rewriting of a nonvolatile memory. [Background technology]

[0002] In the rewrite process of a non-volatile memory, i.e., the erase process and the write process, a verify process is performed to determine whether the rewrite has been performed correctly. In a normal verify process, if all bits to be rewritten are rewritten correctly, it is determined to be a pass, and if there is a rewrite error in even one bit, it is determined to be a fail. Then, the rewrite process and the verify process are repeated until it is determined to be a pass, and if it is still determined to be a fail after being repeated a predetermined number of times, it is finally determined to be a fail.

[0003] On the other hand, a non-volatile memory is known that includes, in addition to data cells, cells for an error correction code (ECC) for detecting and correcting error bits. Patent Document 1 discloses a technique that, even if a verify process judges it to be a fail, if the number of error bits is equal to or less than the number of error correctable bits n (n is a natural number), it is finally judged to be a pass and allowed. With this configuration, the failure rate of nonvolatile memories can be reduced. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2006-048783 A Summary of the Invention [Problem to be solved by the invention]

[0005] The inventors have found the following problems with the technique disclosed in Patent Document 1. For example, in the method disclosed in FIG. 6 of Patent Document 1, the rewrite process and the verify process are repeated the maximum number of times, and then it is determined whether the number of bits n is equal to or smaller than the number of bits that can be corrected for errors. In the erase process, for example, if there is an abnormal cell with a small on-current that is out of the distribution of normal cells, the erase process is repeated due to the abnormal cell. As a result, there is a problem that excessive stress is applied to the normal cells. The mechanism by which this problem occurs will be described in detail later in the specification as a comparative example.

[0006] On the other hand, for example, in the method disclosed in FIG. 7 of Patent Document 1, it is determined whether the number of bits n is equal to or less than the number of bits that can be corrected for errors each time a rewrite process and a verify process are performed. In the erase process, for example, if there are no abnormal cells, there is a risk that even normal cells whose on-current does not reach the erase verify threshold level will be tolerated by error correction. In that case, there is a problem that the data retention margin is insufficient, and the data retention time, i.e., the lifespan, is shortened. The mechanism by which this problem occurs will be described in detail later in the specification as a comparative example. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] In one embodiment of a non-volatile memory system, a controller determines whether or not errors can be corrected for addresses that have been determined to have failed in an erase verify process, counts the number of addresses that have been determined to have errors that can be corrected, and if the number of such addresses is less than a predetermined number, determines that the erase process is normal.

[0008] In one embodiment of a method for controlling rewriting of non-volatile memory, for addresses determined to have failed in an erase verify process, it is determined whether or not errors can be corrected, the number of addresses determined to have errors that can be corrected is counted, and if the number of such addresses is less than a predetermined number, it is determined that the erase process is normal. Effect of the Invention

[0009] According to the embodiment, it is possible to provide a non-volatile memory system capable of suppressing excessive stress on normal cells and also ensuring a data retention margin for normal cells. [Brief description of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a configuration of a nonvolatile memory system according to a first embodiment. [Diagram 2] 4 is a flowchart showing a rewrite control method for the nonvolatile memory according to the first embodiment. [Diagram 3] 5 is a flowchart showing a rewrite control method for a nonvolatile memory according to a first comparative example. [Figure 4] 11 is a graph for explaining a problem in a method for controlling rewrite of a nonvolatile memory according to a first comparative example. [Diagram 5] 10 is a flowchart showing a rewrite control method for a nonvolatile memory according to a second comparative example. [Figure 6] 10 is a graph for explaining a problem in a method for controlling rewrite of a nonvolatile memory according to a second comparative example. [Figure 7] 4 is a graph for explaining the effect of the rewrite control method for the nonvolatile memory according to the first embodiment. [Figure 8] 10 is a flowchart showing a method for controlling rewriting of a nonvolatile memory according to a second embodiment. [Figure 9] 9A to 9C are diagrams showing a schematic diagram of transition of data written to a data cell by the write process shown in FIG. 8; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, specific embodiments of the present disclosure will be described in detail with reference to the drawings. However, the present disclosure is not limited to the following embodiments. In addition, in order to clarify the description, the following description and drawings are appropriately simplified. Furthermore, in each drawing, the same elements are given the same reference numerals, and repeated description is omitted as necessary.

[0012] (First embodiment) <Non-volatile memory system configuration> First, a nonvolatile memory system according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a block diagram showing the configuration of the nonvolatile memory system according to the first embodiment. 1, the nonvolatile memory system according to the first embodiment includes a nonvolatile memory 10, a controller 20, and a CPU 30. Note that the CPU 30 is not essential to the nonvolatile memory system according to this embodiment.

[0013] The non-volatile memory 10 is, for example, a flash memory, and includes a data cell and an error correction code (ECC) cell for each address. By providing the ECC cell, it becomes possible to correct errors for each address. The number of bits n (n is a natural number) that can be corrected for errors is determined appropriately.

[0014] As an example, to enable 1-bit error correction per address, a 6-bit ECC cell is added to the data cell of one address (32 bits), and to enable 2-bit error correction per address, a 12-bit ECC cell is added to the data cell.

[0015] The controller 20 executes rewrite processing, i.e., erase processing and write processing, on the nonvolatile memory 10. For example, if the nonvolatile memory 10 is a flash memory, the erase processing turns on all data cells and sets the values ​​of all data cells to "1". The write processing is performed after the erase processing. In other words, to perform the write processing, the erase processing is performed first. In the write processing, a specific data cell is switched from on to off based on the write data, and the value of the data cell is switched from "1" to "0".

[0016] Here, in the non-volatile memory 10, the erase process is performed on a block consisting of multiple addresses or on multiple blocks at once. As an example, one block is 256 addresses (32 bits), that is, 1 KB. However, the capacity of one block is determined appropriately.

[0017] Here, the controller 20 shown in Fig. 1 includes an ECC encoder 21 and an ECC decoder 22. Fig. 1 shows input and output of signals in a write process. The ECC encoder 21 adds error correction data to the write data wd1 received from the CPU 30 to generate write data wd2. The controller 20 writes the write data wd2 to which the error correction data has been added, to the non-volatile memory 10. The ECC decoder 22 decodes the read data rd1 read from the non-volatile memory 10, and performs error correction on the read data rd1. Then, the ECC decoder 22 outputs the error-corrected read data rd2 to the CPU 30.

[0018] Although not shown, in the case of an erase process, the controller 20 turns on all data cells in a block to be erased in the nonvolatile memory 10, and sets the values ​​of all data cells to "1." Then, the ECC decoder 22 decodes data read from the erased nonvolatile memory 10 and performs error correction on the data.

[0019] The controller 20 executes an erase verify process to determine whether the erase process is a pass or a fail for each address. For example, if the non-volatile memory 10 is a flash memory, the controller 20 reads data from the non-volatile memory 10 on which the erase process has been executed, and determines whether the values ​​of all data cells are "1" for each address.

[0020] If the values ​​of all the data cells are "1", the controller 20 determines that the erase verify process has passed, i.e., the controller 20 determines that the erase process is normal. On the other hand, if not all of the data cells have a value of "1" and some of the data cells have a value of "0", the controller 20 determines that the erase verify process has failed.

[0021] In addition, the controller 20 judges whether or not the error can be corrected for the address judged as failing in the erase verify process. For example, the controller 20 executes the erase verify process for the data that has been error corrected by the ECC decoder 22, and judges that the error can be corrected if it passes, and that the error cannot be corrected if it fails.

[0022] Alternatively, the number of error bits included in the data read from the erased non-volatile memory 10 may be counted, and if the number is equal to or less than the number n of error-correctable bits, it may be determined that the errors are correctable. On the other hand, if the number of error bits exceeds the number n of error-correctable bits, it may be determined that the errors are not correctable. In other words, the controller 20 does not necessarily have to include an ECC decoder 22 inside, and the ECC decoder 22 may be provided outside the controller 20.

[0023] The controller 20 then counts the number of addresses that are determined to be error correctable, and determines that the erase process is normal if the number of addresses is equal to or less than a predetermined number m (m is a natural number). Here, the number m is appropriately determined based on, for example, the occurrence rate of abnormal cells with small on-current that are outside the distribution of normal cells. On the other hand, if the number of addresses exceeds the predetermined number m, the controller 20 determines that the erase process is abnormal, and executes the erase process and the erase verify process again. The number of retries for the erase process is determined in advance.

[0024] In addition, the controller 20 can be configured, in terms of hardware, by a computer including a processor, memory, and other circuits, and in terms of software, is realized by a program loaded into memory, etc.

[0025] As described above, in the nonvolatile memory system according to this embodiment, the controller 20 judges whether or not an error can be corrected for an address that has been judged to be a fail in the erase verify process. That is, since it is judged whether or not an error can be corrected without repeating the erase process, it is possible to shorten the erase time and suppress excessive stress on normal cells due to repeated erase processes.

[0026] In addition, in the non-volatile memory system according to the present embodiment, the controller 20 counts the number of addresses that are determined to be error correctable, and if the number of addresses is equal to or less than a predetermined number, it determines that the erase process is normal. That is, the number of addresses that are error correctable is limited so that only when the cause of the fail determination in the erase verify process is due to an abnormal cell, the error correction is permitted. Therefore, the error correction for normal cells whose on-current is less than the threshold level of the erase verify is suppressed, and the data retention margin can be secured.

[0027] <Non-volatile memory rewrite control method> Next, a method for controlling rewriting of a nonvolatile memory according to the first embodiment will be described with reference to Fig. 2. Fig. 2 is a flowchart showing a method for controlling rewriting of a nonvolatile memory according to the first embodiment. Fig. 2 shows a method for controlling an erase process and an erase verify process. In describing Fig. 2, Fig. 1 will be referred to as appropriate.

[0028] 2, the controller 20 executes an erase process on the nonvolatile memory 10 (step ST1). The erase process (step ST1) is performed on a block consisting of multiple addresses or on multiple blocks at once. For example, if the nonvolatile memory 10 is a flash memory, the erase process (step ST1) turns on all data cells at the addresses to be erased in the nonvolatile memory 10, and sets the values ​​of all data cells to "1".

[0029] 2, the controller 20 executes an erase verify process (step ST2) to determine whether the erase process (step ST1) is a pass or a fail for each address. For example, the controller 20 reads data from the nonvolatile memory 10 after the erase process, and determines whether the values ​​of all data cells are "1" for each address.

[0030] If the values ​​of all the data cells are "1", the controller 20 judges the erase verify process as pass (pass in step ST2). In this case, as shown in Fig. 2, if the target address is not the final address, the controller 20 moves to the next address and returns to step ST2, and executes the erase verify process for the next address. If the target address is the final address, the erase process for all addresses is normal, so the controller 20 judges that the erase process is ultimately normal and ends the erase process (pass end).

[0031] On the other hand, if the values ​​of all the data cells are not "1" and some of the data cells have a value of "0", the controller 20 determines that the erase verify process has failed (Fail in step ST2). In this case, as shown in FIG. 2, it is determined whether the error can be corrected (step ST3).

[0032] 2, if it is determined that the error cannot be corrected (NO in step ST3), and the number of retries for the erasure process is not the maximum value, the process returns to step ST1 and the erasure process is executed again. If the number of retries for the erasure process is the maximum value, the controller 20 ultimately determines that the erasure process is abnormal and ends the erasure process (fail end). A fail end means that a failure has occurred in the nonvolatile memory 10.

[0033] 2, if it is determined that the error can be corrected (YES in step ST3), the number of addresses is counted up (step ST4). That is, the number of addresses determined to be error correctable in step ST3 is counted.

[0034] Next, as shown in FIG. 2, it is determined whether the number of addresses counted in step ST4 is equal to or smaller than a predetermined number m (step ST5). If the number of addresses is equal to or less than the predetermined number m (YES in step ST5), and the target address is not the final address, the process proceeds to the next address and returns to step ST2, and erase verify processing is performed on the next address. If the target address is the final address, the controller 20 determines that the erase processing is ultimately normal, and ends the erase processing (pass end).

[0035] On the other hand, if the number of addresses exceeds the predetermined number m (NO in step ST5), and the number of retries for the erasure process is not the maximum value, the process returns to step ST1 and the erasure process is executed again. If the number of retries for the erasure process is the maximum value, the controller 20 ultimately determines that the erasure process is abnormal and ends the erasure process (fail end).

[0036] <Method of controlling rewrite of non-volatile memory according to a first comparative example> Here, a method for controlling rewriting of a nonvolatile memory according to a first comparative example will be described with reference to Fig. 3. Fig. 3 is a flowchart showing a method for controlling rewriting of a nonvolatile memory according to a first comparative example. The erase process (step ST1) and the erase verify process (step ST2) are the same as those in Fig. 2, and therefore will not be described.

[0037] 3, when the erase verify process is judged as pass (pass in step ST2), if the target address is not the final address, the process proceeds to the next address and returns to step ST2, and the erase verify process is executed for the next address. If the target address is the final address, the erase process for all addresses is normal, so the controller 20 judges that the erase process is ultimately normal and ends the erase process (pass end).

[0038] 3, if the erase verify process is judged as fail (Fail in step ST2), and the number of retries for the erase process is not the maximum value, the process returns to step ST1 and executes the erase process again. On the other hand, if the number of retries for the erase process is the maximum value, it is judged whether the error can be corrected (step ST3).

[0039] 3, if it is determined that the error can be corrected (YES in step ST3), and if the target address is not the final address, the process proceeds to the next address and returns to step ST2, where the erase verify process is executed for the next address. If the target address is the final address, the erase process for all addresses is normal, so the controller 20 determines that the erase process is ultimately normal, and ends the erase process (pass end).

[0040] On the other hand, as shown in FIG. 3, when it is determined that the error cannot be corrected (NO in step ST3), the controller 20 ultimately determines that the erasure process is abnormal, and ends the erasure process (fail end).

[0041] <Problems with the method for controlling rewriting of a non-volatile memory according to the first comparative example> Next, a problem in the method for controlling rewriting of a nonvolatile memory according to the first comparative example will be described with reference to Fig. 4. Fig. 4 is a graph for explaining the problem in the method for controlling rewriting of a nonvolatile memory according to the first comparative example. The horizontal axis of Fig. 4 indicates the number of cells, and the vertical axis indicates the on-current Ion of the cell.

[0042] Fig. 4 shows a case where an abnormal cell with a small on-current Ion that is out of the distribution of normal cells is present. In the example shown in Fig. 4, since the abnormal cell does not exceed the threshold level of the erase verify, the erase verify process shown in Fig. 3 is judged as failing (fail in step ST2), and the erase process (step ST1) is repeated up to the maximum number of retries.

[0043] Therefore, in the method for controlling rewrite of a nonvolatile memory according to the first comparative example, the erase time increases until a pass determination is made by error correction. 4, the normal cell distribution is excessively shifted toward the side where the on-current Ion increases until the pass determination is made by the error correction. Therefore, the rewrite control method for the non-volatile memory according to the first comparative example has a problem that excessive stress is applied to the normal cells.

[0044] <Method of controlling rewrite of non-volatile memory according to second comparative example> Next, a method for controlling rewriting of a nonvolatile memory according to a second comparative example will be described with reference to Fig. 5. Fig. 5 is a flowchart showing a method for controlling rewriting of a nonvolatile memory according to a second comparative example. The erase process (step ST1) and the erase verify process (step ST2) are the same as those in Fig. 2, and therefore will not be described.

[0045] 5, when the erase verify process is judged as pass (pass in step ST2), if the target address is not the final address, the process proceeds to the next address and returns to step ST2, and the erase verify process is executed for the next address. If the target address is the final address, the erase process for all addresses is normal, so the controller 20 judges that the erase process is ultimately normal and ends the erase process (pass end).

[0046] On the other hand, as shown in FIG. 5, if the erase verify process is judged as fail (Fail in step ST2), it is immediately judged whether or not the error can be corrected (step ST3). 5, if it is determined that the error can be corrected (YES in step ST3), and if the target address is not the final address, the process proceeds to the next address and returns to step ST2, where the erase verify process is executed for the next address. If the target address is the final address, the erase process for all addresses is normal, so the controller 20 determines that the erase process is ultimately normal, and ends the erase process (pass end).

[0047] On the other hand, as shown in Fig. 5, if it is determined that the error cannot be corrected (NO in step ST3), and the number of retries for the erasure process is not the maximum value, the process returns to step ST1 and the erasure process is executed again. If the number of retries for the erasure process is the maximum value, the controller 20 ultimately determines that the erasure process is abnormal and ends the erasure process (fail end).

[0048] <Problems with the method for controlling rewriting of non-volatile memory according to the second comparative example> Next, a problem in the method for controlling rewriting of a nonvolatile memory according to the second comparative example will be described with reference to Fig. 6. Fig. 6 is a graph for explaining the problem in the method for controlling rewriting of a nonvolatile memory according to the second comparative example. The horizontal axis of Fig. 6 indicates the number of cells, and the vertical axis indicates the on-current Ion of the cell.

[0049] Fig. 6 shows a case where there are no abnormal cells and the on-current Ion of the normal cell distribution is low. In the example shown in Fig. 6, the erase verify process shown in Fig. 5 is judged as failing (fail in step ST2) due to normal cells whose on-current Ion does not meet the erase verify threshold level, but it can be immediately judged as error correctable in the subsequent step ST3.

[0050] That is, in the non-volatile memory rewrite control method according to the second comparative example, as shown in Fig. 6, not only abnormal cells but also normal cells whose on-current Ion does not reach the erase verify threshold level may be tolerated by error correction. In that case, there is a problem that the data retention margin is insufficient, and the data retention time, i.e., the lifespan, is shortened.

[0051] <Effects of non-volatile memory rewrite control method> Next, the effect of the method for controlling rewriting of a nonvolatile memory according to the first embodiment will be described with reference to Fig. 7. Fig. 7 is a graph for explaining the effect of the method for controlling rewriting of a nonvolatile memory according to the first embodiment. The horizontal axis of Fig. 7 indicates the number of cells, and the vertical axis indicates the on-current Ion of the cell.

[0052] Fig. 7 shows a case where there is an abnormal cell with a small on-current Ion that is out of the distribution of normal cells, similar to Fig. 4. In the example shown in Fig. 7, since the abnormal cell does not exceed the erase verify threshold level, the erase verify process shown in Fig. 2 is judged as failing (fail in step ST2), but it is immediately judged in the subsequent step ST3 that the error can be corrected.

[0053] Therefore, in the method for controlling rewriting of a nonvolatile memory according to the first embodiment, whether an error can be corrected is determined without repeating the erase process, and therefore the erase time can be shortened. Also, as can be seen from a comparison between Fig. 4 and Fig. 7, excessive stress on normal cells due to repeated erase processes can be suppressed.

[0054] On the other hand, as shown in Fig. 2, the number of addresses capable of error correction is counted (step ST4), and the number of addresses is limited to m or less (step ST5). That is, the number of addresses capable of error correction is limited so that only when the cause of the fail judgment in the erase verify process is due to an abnormal cell, the error correction is permitted. Therefore, as can be seen from a comparison between Fig. 6 and Fig. 7, the tolerance of error correction for normal cells whose on-current is less than the threshold level of the erase verify is suppressed, and the data retention margin can be secured.

[0055] Second embodiment <Non-volatile memory rewrite control method> Next, a method for controlling rewriting of a nonvolatile memory according to a second embodiment will be described with reference to Fig. 8. Fig. 8 is a flowchart showing a method for controlling rewriting of a nonvolatile memory according to the second embodiment. Fig. 8 shows a method for controlling a write process and a write verify process.

[0056] The write process and the write verify process shown in FIG. 8 are executed after the pass end of the erase process and the erase verify process shown in FIG. The configuration of the nonvolatile memory system according to the second embodiment is shown in Fig. 1, similarly to the first embodiment, so Fig. 1 will be referred to as appropriate in describing Fig. 8.

[0057] First, as shown in Fig. 8, the controller 20 executes a write process for the non-volatile memory 10 (step ST11). For example, if the non-volatile memory 10 is a flash memory, in the above-mentioned erase process executed before the write process, all data cells are turned on and the values ​​of all data cells are set to "1". Then, in the write process (step ST11) shown in Fig. 8, a specific data cell is switched from on to off based on the write data, and the value of the data cell is switched from "1" to "0".

[0058] 8, the controller 20 executes a write verify process (step ST12) to determine whether the write process (step ST11) is a pass or a fail. For example, the controller 20 reads data from the nonvolatile memory 10 on which the write process has been executed, and determines whether the values ​​of all the data cells match the values ​​of the write data.

[0059] If the values ​​of all the data cells match the value of the write data, the controller 20 determines that the write verify process is passed (pass in step ST12). In this case, as shown in FIG. 8, the controller 20 ultimately determines that the writing process is normal, and ends the writing process (pass end).

[0060] On the other hand, if the value of the data cell includes a value that does not match the value of the write data, the controller 20 determines that the write verify process has failed (Fail in step ST12). In this case, as shown in FIG. 8, it is determined whether or not all the values ​​of the cells to be rewritten from "1" to "0" (called "rewrite bits") match the value "0" of the write data (step ST13).

[0061] 8, if the rewrite bit value includes a value that does not match the value of the write data (NO in step ST13), and the number of retries for the write process is not the maximum value, the process returns to step ST11 and executes the write process again. If the number of retries for the write process is the maximum value, the controller 20 ultimately determines that the write process is abnormal and ends the write process (fail end).

[0062] On the other hand, as shown in FIG. 8, if the values ​​of all the rewrite bits match the values ​​of the write data and are correct (YES in step ST13), it is determined whether the errors can be corrected (step ST14).

[0063] If it is determined that the error is correctable (YES in step ST14), the controller 20 determines that the write process is ultimately normal, and ends the write process (pass end). On the other hand, as shown in FIG. 8, when it is determined that the error cannot be corrected (NO in step ST14), the controller 20 ultimately determines that the write process is abnormal, and ends the write process (fail end).

[0064] FIG. 9 is a diagram showing a schematic diagram of the transition of data written in a data cell by the write process shown in FIG. The value of each data cell of the write data is shown in the top row of Fig. 9, and the value of each data cell in the initial state (erased state) is shown in the second row. Furthermore, the value of each data cell after the first write process is shown in the third row of Fig. 9, the value of each data cell after the second write process is shown in the fourth row, and the value of each data cell after the third write process is shown in the bottom row.

[0065] As shown in the initial state (erased state) in the second row of Figure 9, the value of the third data cell from the left in the drawing is "0", which is an erase error, but is tolerated by the error correction in the erase verify process according to the first embodiment.

[0066] The value "10011101" after the first write process shown in the third row of Fig. 9 does not match the value "00101000" of the write data shown in the top row of Fig. 9, so it is judged as fail in the write verify process shown in Fig. 8 (Fail in step ST12). Furthermore, since the value of the rewrite bit that should be "0" does not match the value "0" of the rewrite bit in the write data (NO in step ST13), the process returns to step ST11 and executes the write process again.

[0067] The value "00001101" after the second write process shown in the fourth row of Fig. 9 does not match the value "00101000" of the write data shown in the top row of Fig. 9, so the write verify process shown in Fig. 8 is judged as fail (Fail in step ST12). Furthermore, since the value of the rewrite bit that should be "0" does not match the value "0" of the rewrite bit in the write data (NO in step ST13), the process returns to step ST11 and the write process is executed again.

[0068] The value "00001000" after the third write process shown in the bottom row of Fig. 9 does not match the value "00101000" of the write data shown in the top row of Fig. 9, so the write verify process shown in Fig. 8 is judged as fail (Fail in step ST12). On the other hand, since the value of the rewrite bit that should be "0" matches the value "0" of the rewrite bit in the write data (YES in step ST13), it is judged whether the error can be corrected (step ST14). Here, since the error bit is only one bit due to an erase error, the error can be corrected (YES in step ST14), and therefore the write process is ultimately determined to be normal.

[0069] Here, erase errors are allowed in the erase process and erase verify process according to the first embodiment shown in Fig. 2. Therefore, in the write process and write verify process according to the present embodiment shown in Fig. 8, only erase errors in the initial state (erased state) are allowed, and errors in rewritten bits in the write process are not allowed. The other configuration is similar to that of the first embodiment, and therefore the description will be omitted.

[0070] In the above example, the program includes a set of instructions (or software code) that, when loaded into a computer, causes the computer to perform one or more functions described in the embodiment. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or tangible storage medium includes a random-access memory (RAM), a read-only memory (ROM), a flash memory, a solid-state drive (SSD) or other memory technology, a CD-ROM, a digital versatile disc (DVD), a Blu-ray® disk or other optical disk storage, a magnetic cassette, a magnetic tape, a magnetic disk storage or other magnetic storage device. The program may be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, the transitory computer-readable medium or the communication medium includes an electrical, optical, acoustic, or other form of propagating signal.

[0071] The invention made by the present inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the embodiment already described, and various modifications are possible without departing from the gist of the invention. [Explanation of symbols]

[0072] 10 Non-volatile memory 20 Controller 21 ECC Encoder 22 ECC Decoder 30 CPU

Claims

1. a non-volatile memory including a data cell and an error correction code cell for each address; a controller that executes an erase process for a plurality of addresses of the nonvolatile memory at once and an erase verify process for determining whether the erase process is a pass or a fail for each address; The controller: determining whether an error can be corrected for an address determined to be a fail in the erase verify process; counting the number of addresses determined to be error correctable, and determining that the erasure process is normal if the number of addresses is equal to or less than a predetermined number; Non-volatile memory system.

2. If the number of the addresses exceeds the predetermined number, the erasure process is determined to be abnormal, and the erasure process is executed again.

10. The non-volatile memory system of claim 1.

3. The number of retries for the erasure process when it is determined that the erasure process is abnormal is determined in advance.

3. The non-volatile memory system of claim 2.

4. The controller: further executing a write process on the non-volatile memory after the erase process, and a write verify process for determining whether the write process is a pass or a fail. If the write verify process is judged to be a fail, it is judged whether or not all values ​​of the rewrite bits to be rewritten from the erased state are correct; If all the rewrite bits have the correct values, it is determined whether the error can be corrected; If it is determined that the error can be corrected, it is determined that the writing process is normal.

10. The non-volatile memory system of claim 1.

5. The controller: If the value of the rewrite bit is incorrect, it is determined that the write process is abnormal; repeating the write process and the write verify process; 5. The non-volatile memory system of claim 4.

6. The controller: If it is determined that the error cannot be corrected, it is determined that the writing process is ultimately abnormal.

5. The non-volatile memory system of claim 4.

7. performing a collective erase process on a plurality of addresses of a non-volatile memory including data cells and error correction code cells for each address; A method for controlling rewrite of a non-volatile memory, comprising: executing an erase verify process for determining whether the erase process is a pass or a fail for each address, the method comprising: determining whether an error can be corrected for an address determined to be a fail in the erase verify process; counting the number of addresses determined to be error correctable, and determining that the erasure process is normal if the number of addresses is equal to or less than a predetermined number; A method for controlling rewriting of a non-volatile memory.

8. If the number of the addresses exceeds the predetermined number, the erasure process is determined to be abnormal, and the erasure process is executed again.

8. A method for controlling rewriting of a non-volatile memory according to claim 7.

9. The number of retries for the erasure process when it is determined that the erasure process is abnormal is determined in advance. The method for controlling rewriting of a non-volatile memory according to claim 8.

10. a write process for the non-volatile memory after the erase process; and further executing a write verify process for determining whether the write process is a pass or a fail. If the write verify process is judged to be a fail, it is judged whether or not all values ​​of the rewrite bits to be rewritten from the erased state are correct; If all the rewrite bits have the correct values, it is determined whether the error can be corrected; If it is determined that the error can be corrected, it is determined that the writing process is normal.

8. A method for controlling rewriting of a non-volatile memory according to claim 7.

11. If the value of the rewrite bit is incorrect, it is determined that the write process is abnormal; performing the write process and the write verify process again; The method for controlling rewriting of a non-volatile memory according to claim 10.

12. If it is determined that the error cannot be corrected, it is determined that the writing process is ultimately abnormal. The method for controlling rewriting of a non-volatile memory according to claim 10.

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