Transistor structure

Abstract

To provide a transistor structure that can prevent a fin structure from collapsing.SOLUTION: A transistor structure includes a substrate, an insulating wall, and a gate region. The substrate has a fin structure. The insulating wall clamps side walls of the fin structure. The gate region is above the fin structure and the insulating wall, and the insulating wall is configured to prevent the fin structure from collapsing.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to a transistor structure, in particular to a transistor structure that provides a solid wall (additional beam-like structures may be provided to strengthen the solid wall) that clamps the active area or narrow fin structure, in particular the sidewall of the fin structure, allows control of the relative position or distance between the edge of the source / drain and the edge of the gate, improves the source / drain resistance, and allows the majority of the source / drain regions to be isolated by insulating material. [Background technology]

[0002] An example of a state-of-the-art field effect transistor (e.g., NMOS (N-type metal oxide semiconductor) transistor) with a FIN structure (FinFET or Tri-gate) is shown in Figure 1. On a three-dimensional (3D) silicon surface with sidewalls insulated from other transistor sidewalls with an insulating material (e.g., oxide, or oxide / nitride, or some high-k dielectric, etc.), the gate structure 10 of the NMOS transistor is formed with some conductive material (such as metal, polysilicon, polycide, etc.) on top of the insulator. The source 11 and drain 12 of the NMOS transistor are formed by implanting a high concentration of n-type (n+) dopants into a p-type substrate (or p-well) using ion implantation plus thermal annealing techniques, thus resulting in two isolated n+ / p junction regions.

[0003] Also, to reduce impact ionization and hot carrier injection, it is common to form lightly doped drains (n-type LDDs) 13 in front of the source 11 and drain 12 by ion implantation plus thermal annealing techniques prior to the heavily doped n+ / p junctions, which often results in the LDDs 13 encroaching into the portion of the 3D active area underneath the gate structure 10 (as shown in FIG. 1 ). Thus, the effective channel length 14 between the LDDs 13 is inevitably shortened.

[0004] Meanwhile, advances in manufacturing process technology continue to advance rapidly by scaling down NMOS transistor geometries in both horizontal and vertical dimensions (e.g., reducing the minimum feature size, called lambda (λ), from 28 nm to 5 nm or 3 nm). However, this scaling of FinFET or Tri-Gate geometries introduces or exacerbates a number of problems: (1) As both horizontal and vertical dimensions are scaled down, it is difficult to perfectly align the LDD junction edge (or source / drain edge) to the edge of the gate structure 10 using only the conventional self-alignment method using gate, spacer, and ion implantation formation. Also, the thermal annealing technique to remove the ion implantation damage must rely on high temperature processing techniques, such as rapid thermal annealing, by using various energy sources and other thermal processes. Thus, one problem caused is the gate-induced drain leakage (GIDL) current, which is difficult to control, despite the fact that the resulting GIDL current should be minimized to reduce the leakage current, and another problem caused is that the length of the effective channel 14 is difficult to control, and therefore the short channel effect (SCE) is hardly minimized. Moreover, it is also difficult to adjust the relative position between the source / drain edge and the edge of the gate structure 10 to control the GIDL; (2) Also, since the ion implantation for forming the LDD 13 (or the n+ / p junction in NMOS, or the p+ / n junction in PMOS (p-type metal oxide semiconductor)) acts like a bombardment to insert ions from above the silicon surface straight down into the substrate, the dopant concentration is unevenly distributed vertically from the top surface, which has a higher doping concentration, to the junction region, which has a lower doping concentration, making it difficult to create a uniform material interface with few defects from the source 11 and drain 12 to the effective channel 14 and substrate body region; (3) Furthermore, when the lateral dimensions are scaled down to 7 nm, 5 nm, or 3 nm, the height (vertical dimension) of the NMOS transistor fin structure (e.g., 60-300 nm, etc.) becomes much larger than the width (horizontal dimension) of the NMOS transistor fin structure (e.g., 3-7 nm, etc.), which results in the fin structure becoming weak or even collapsing during subsequent processes (e.g., source / drain formation, gate formation, etc.).

[0005] Therefore, the present invention provides a transistor structure for solving the above problems 1)-3). Summary of the Invention

[0006] One embodiment of the present invention provides a transistor structure, the transistor structure including a substrate, an insulating wall, and a gate region, the substrate having a fin structure, the insulating wall clamping a sidewall of the fin structure, the gate region overlying the fin structure and the insulating wall, the insulating wall configured to prevent the fin structure from collapsing.

[0007] According to one aspect of the invention, the insulating walls clamp the four side walls of the fin structure.

[0008] According to one aspect of the invention, the transistor structure further includes an STI layer surrounding the insulating wall.

[0009] According to one aspect of the invention, the transistor structure further includes a sheet channel layer disposed between a sidewall of the fin structure and the insulating wall, the sheet channel layer being formed by selective epitaxial growth.

[0010] According to one aspect of the invention, the gate region includes a gate dielectric layer over the fin structure, a gate conductive layer over the gate dielectric layer, and a cap layer over the gate conductive layer.

[0011] According to one aspect of the invention, the insulating wall is configured to prevent the fin structure from collapsing during formation of the gate dielectric layer, the gate conductive layer, and the cap layer.

[0012] According to one aspect of the invention, the transistor structure further includes a spacer layer on a sidewall of the gate region.

[0013] According to one aspect of the invention, a first conductive region is formed in a first recess below an initial surface of a substrate.

[0014] Another embodiment of the present invention provides a transistor structure, the transistor structure including a substrate, a composite structure, and a gate region, the substrate having a fin structure, the composite structure clamping a sidewall of the fin structure, the gate region overlying the fin structure and the composite structure, the composite structure configured to prevent the fin structure from collapsing.

[0015] According to one aspect of the invention, a composite structure includes a support wall that clamps a side wall of a fin structure and a support beam that supports the support wall.

[0016] According to one aspect of the invention, the support wall extends in a first direction from a bottom of the fin structure and the support beam extends in a second direction different from the first direction of the support wall.

[0017] According to one aspect of the invention, the support walls and support beams are made of nitride.

[0018] According to one aspect of the invention, the support beam abuts the support wall.

[0019] According to one aspect of the invention, a composite structure includes a support wall that clamps a sidewall of a fin structure and a plurality of support beams that support the support wall.

[0020] Another embodiment of the invention includes a transistor structure including a substrate having an initial surface, a channel region, a gate region over the channel region, a shallow trench isolation region, a first conductive region between the gate region and the shallow trench isolation region, the first conductive region in electrical contact with the channel region, and a metal region between the gate region and the shallow trench isolation region, at least two sides of the first conductive region in contact with the metal region.

[0021] According to one aspect of the invention, the shallow trench isolation region initially extends above the surface and the first conductive region does not overlie the shallow trench isolation region.

[0022] According to one aspect of the invention, the metal region contacts the top surface and sidewalls of the first conductive region.

[0023] According to one aspect of the invention, the transistor structure further includes an L-shaped isolator below a bottom of the first conductive region.

[0024] Another embodiment of the invention includes a transistor structure including a substrate having an initial surface, a channel region, a gate region over the channel region, a shallow trench isolation region surrounding the channel region, and a first conductive region in electrical contact with the channel region, where a bottom surface of the gate region is below a bottom surface of the first conductive region.

[0025] According to one aspect of the invention, a bottom surface of the gate region overlies a portion of the shallow trench isolation region.

[0026] These and other objects of the present invention will no doubt become obvious to those skilled in the art after reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings. [Brief description of the drawings]

[0027] [Figure 1]FIG. 1 illustrates a FinFET according to the prior art. [Figure 2A] 1 is a flow chart illustrating a method for manufacturing a Fin Field Effect Transistor (FinFET) according to a first embodiment of the present invention. [Figure 2B] 2B, 2C, and 2D are diagrams for explaining FIG. 2A. [Figure 2C] 2B, 2C, and 2D are diagrams for explaining FIG. 2A. [Figure 2D] 2B, 2C, and 2D are diagrams for explaining FIG. 2A. [Diagram 3] FIG. 2 shows a pad oxide layer being grown, a pad nitride layer being deposited, a trench and a semiconductor layer being formed, oxide spacers being deposited on the semiconductor layer, and nitride spacers being deposited on the oxide spacers. [Figure 4] FIG. 1 shows that shallow trench isolation (STI) is formed to define a gate area spanning the active area and the isolation area. [Diagram 5] FIG. 1 shows the gate material is formed, the composite cap layer is deposited, the STI is etched, and the pad nitride layer is removed. [Figure 6] FIG. 13 shows that the pad oxide layer is etched away, portions of the STI are etched back, oxide 2 spacers and nitride 2 spacers are formed, and some exposed silicon areas are etched away to create shallow trenches for the source and drain. [Figure 7] FIG. 1 shows that an oxide 3 layer is thermally grown. [Figure 8] FIG. 13 shows that the oxide 3 layer is etched away and the source and drain are formed by SEG technique. [Figure 9] FIG. 2 is a diagram showing a cross section of an SCBFET and Y-direction doping concentrations and X-direction doping concentrations corresponding to the cross section of the SCBFET. [Figure 10] FIG. 1 shows a cross section of a trapezoidal shaped SCBFET. [Figure 11]FIG. 1 shows a cross section of an SCBFET without a thin sheet channel layer. [Figure 12A] 12A and 12B are a flowchart showing a method for manufacturing a FinFET according to the second embodiment of the present invention. [Figure 12B] 12A and 12B are a flowchart showing a method for manufacturing a FinFET according to the second embodiment of the present invention. [Figure 13] FIG. 1 illustrates depositing an oxide layer, removing the excess oxide layer using CMP techniques to form STI, and depositing a nitride film on the STI. [Figure 14] FIG. 13 illustrates forming an STI on a nitride film, defining a gate area spanning an active region and an isolation region, etching away a pad oxide layer and a pad nitride layer corresponding to the gate area, etching back the STI corresponding to the gate area, forming a gate dielectric material, depositing a gate material in a recess, then etching back the gate material, forming a composite cap layer, and polishing the composite cap layer. [Figure 15] FIG. 13 illustrates etching a portion of the STI, removing the pad nitride layer, etching away the pad oxide layer, etching back the STI, and forming oxide 2 spacers and nitride 2 spacers on edges of the gate material and composite cap layer. [Figure 16] FIG. 13 shows the etching away of exposed silicon and thermal growth of an oxide 3 layer. [Figure 17] FIG. 13 shows the etching away of part of the oxide 3 layer, followed by the formation of an n-type lightly doped drain (LDD), followed by the formation of an n+ doped source and an n+ doped drain. [Figure 18] FIG. 2 shows that the nitride film is deposited several times. [Figure 19] FIG. 1 shows the formation of a fused semiconductor junction-metal conductor (MSMC) structure. [Figure 20A] FIG. 2 illustrates a fused semiconductor junction-metal conductor (MSMC) structure formed in accordance with another embodiment of the present invention. [Figure 20B] FIG. 2 illustrates a fused semiconductor junction-metal conductor (MSMC) structure formed in accordance with another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] First embodiment Please refer to Figures 2A, 2B, 2C, 2D, 3, 4, 5, 6, 7, 8, 9, 10, and 11. Figure 2A is a flow chart showing a method for manufacturing a fin field effect transistor (FinFET) according to a first embodiment of the present invention, which can reduce the gate-induced drain leakage (GIDL) current and short channel effect (SCE) of the FinFET, and can form a solid wall clamping the active area or narrow fin structure of the FinFET. The detailed steps are as follows:

[0029] Step 10: Start.

[0030] Step 20: Define the active area based on the p-type well 202 and form the fin structure.

[0031] Step 30: A gate of a FinFET is formed on the original horizontal surface (OHS) of the p-type well 202.

[0032] Step 40: Form the source and drain of the FinFET.

[0033] Step 50: Finished.

[0034] See Figures 2B and 3. Step 20 may include:

[0035] Step 102: Grow a pad oxide layer 204 and deposit a pad nitride layer 206.

[0036] Step 104: Define the active area and remove portions of the silicon material outside the active area to create trenches 210 and form fin structures.

[0037] Step 106 : Form oxide spacers 304 , etch back the oxide spacers 304 , and form nitride spacers 306 .

[0038] 2C, 4 and 5. Step 30 may include:

[0039] Step 108: Deposit an oxide layer and remove the excess oxide layer using a chemical mechanical polishing (CMP) technique to form the STI 402.

[0040] Step 110: Define a gate area spanning the active area and the isolation area, etch away the pad oxide layer 204 and the pad nitride layer 206 corresponding to the gate area, and etch back the STI 402 corresponding to the gate area.

[0041] Step 112: Form a gate dielectric material 502, deposit a gate material 504 in the recess 404, and then etch back the gate material 504.

[0042] Step 114: Form a composite cap layer 506, and polish the composite cap layer 506 by a CMP technique.

[0043] See Figure 2D, Figure 6, Figure 7 and Figure 8. Step 40 may include:

[0044] Step 116: Etch back the STI 402, nitride spacers 306, and remove the pad nitride layer 206.

[0045] Step 118: Etch away pad oxide layer 204 and etch back STI 402.

[0046] Step 120 : Form oxide 2 spacers 802 and nitride 2 spacers 804 on the edges of the gate material 504 and the composite cap layer 506 .

[0047] Step 122: Etch away the exposed silicon.

[0048] Step 124: Thermally grow oxide 3 layer 1002.

[0049] Step 126: Etch away the oxide 3 layer 1002 portions, then form n-type lightly doped drains (LDDs) 1102, 1104, then form an n+ doped source 1106 and an n+ doped drain 1108.

[0050] A detailed description of the above-mentioned fabrication method is as follows: Starting with a well-designed doped p-type well 202, the p-type well 202 is provided in a p-type substrate 200 (although in other embodiments of the invention one may start with the p-type substrate 200 rather than starting with the p-type well 202), in one example the p-type well 202 is counted down from its top surface by about 500 nm from OHS, and is a substrate doped to a lower concentration (even including punch-through implant dopant profiles) of 5×10 higher (for example) than is used in state-of-the-art FinFETs. 18 Dopant / cm 3 For example, the p-type substrate 200 has a concentration close to 1×10 16 Dopant / cm 3 The actual dopant concentration will be determined by final volume manufacturing optimization. As a result, a p-type substrate voltage (usually grounded, i.e., 0V) can be provided across most of the body of the FinFET, rather than resulting in a largely depleted fin substrate (which behaves like a voltage floating body with little control or stabilization, making it less desirable than a semiconductor transistor with a voltage stabilized body).

[0051] In step 102, a pad oxide layer 204 of a well-designed thickness is grown over the OHS, and a pad nitride layer 206 of a well-designed thickness is deposited on top of the pad oxide layer 204, as shown in FIG. 3(a).

[0052] In step 104, as shown in Fig. 3(a), photolithography masking technology is used to define the active area of ​​FinFET by anisotropic etching technology, which removes the part of silicon material corresponding to OHS outside the active area to create trench 210 (e.g., about 300 nm deep) for later STI (shallow trench isolation) needs, and thus also creates the fin structure of FinFET. Also, Fig. 3(b) is a top view corresponding to Fig. 3(a), and Fig. 3(a) is a cross-sectional view along the X-direction cutting line shown in Fig. 3(b).

[0053] In step 106, as shown in FIG. 3(a), a semiconductor layer 302 is grown using a selective growth method, such as a selective epitaxial growth (SEG) technique, over the exposed silicon surfaces (the two sidewalls of the fin structure and the top surface of the bottom region of the trench 210), hereafter named a sheet channel layer (SCL), which can be a monolithic p-type doped silicon with a thickness of about 1-2 nm, which should be fully adjusted to the detailed device design. In another example, the sheet channel layer (SCL) is optional. An oxide spacer 304 is deposited on the semiconductor layer 302, and then an anisotropic etching technique is used to etch back the oxide spacer 304 so that the top surface of the oxide spacer 304 is at a height that matches the OHS. Then, a nitride spacer 306 is deposited on the oxide spacer 304 so that the top surface of the nitride spacer is at a height that matches the top surface of the pad nitride layer 206. In addition, the oxide spacer 304 and the nitride spacer 306 are outside the active area of ​​the FinFET. Therefore, the key point here is that the oxide spacer 304 and the nitride spacer 306 form a solid wall that clamps the active area or the narrow fin structure, especially the sidewall of the fin structure. This solid clamping wall can be a single layer or other composite capping layer to protect the narrow fin structure from collapsing during the formation of the source / drain or gate of the FinFET.

[0054] Another important point here is that the semiconductor layer 302 is used for the channel region of the FinFET, which will be turned into a depletion region until it is fully inverted into a channel conduction region depending on how the gate voltage is applied. Therefore, the doping concentration of the semiconductor layer 302 affects the threshold voltage of the FinFET and forms the main conductive layer with electron carriers under inversion to connect both the n-type source and the n-type drain. Since the SEG layer 302 is formed separately from the bulk body of the FinFET, the most desirable design is to use a doping concentration preferably lower than that of the fin body (e.g., 1×10 2 × 10 3 × 10 4 × 10 5 × 10 6 × 10 7 × 10 8 × 10 9 × 10 10 × 10 15 × 10 25 × 10 35 × 10 45 × 10 5 × 10 65 × 10 15 × 10 25 × 10 35 × 10 45 × 10 ... 16 From 3×10 18 ). Additionally, as feature sizes (i.e., line dimensions) continue to scale down horizontally, the semiconductor layer 302 also enhances the mechanical stability of the fins as they are proportionately made thinner and taller. Taller fins allow for increased device widths (to compensate for reduced carrier mobility due to undesirable channel collisions as the fins become narrower), but may result in physical collapse of some narrow fins.

[0055] In step 108, as shown in FIG. 4(a), a thick oxide layer is deposited to completely fill the trench 210, and the excess oxide layer is removed using CMP techniques to form the STI 402. The top surface of the STI 402 is at a height that coincides with the top surface of the pad nitride layer 206. Again, the STI 402 further surrounds or clamps the active area or narrow fin structure, particularly the sidewalls of the fin structure, to protect the narrow fin structure from collapsing when forming the source / drain or gate of the FinFET. Also, FIG. 4(b) is a top view corresponding to FIG. 4(a), and FIG. 4(a) is a cross-sectional view along the X-direction cut line shown in FIG. 4(b).

[0056] Then, in step 110, as shown in FIG. 4(a), a photolithographic masking technique is used to define a gate area spanning the active area and the STI isolation area, so that the pad oxide layer 204 and the pad nitride layer 206 corresponding to the gate area are removed to create a recess 404. Furthermore, the STI 402 corresponding to the gate area is also etched down by a certain amount (e.g., 40-80 nm deep) to form a step structure between the etched STI area corresponding to the gate area and the fin surface. The oxide spacer 304 and the nitride spacer 306 corresponding to the gate area may also be removed. Thus, the top of the semiconductor layer 302 is exposed, providing a smooth line edge roughness for the gate of the FinFET.

[0057] In step 112, as shown in FIG. 5(a), a gate dielectric material 502 (composite material or oxide) is formed in the recess 404 (also the step structure between the etched STI 402 corresponding to the gate area and the fin surface), and a gate material 504 (e.g., a metal such as tungsten 5044 covering TiN 5042) is deposited on the gate dielectric material 502. Then, the gate material 504 is polished by a CMP technique to make the top surface of the gate material 504 coincident with the top surface of the remaining pad nitride layer 206, and the gate material 504 is etched back to make the top surface of the gate material 504 lower than the top surface of the remaining pad nitride layer 206. Thus, a tri-gate structure may exist.

[0058] Then, in step 114, a composite cap layer 506 consisting of a nitride 1 layer 5062 and a hard mask oxide layer 5064 is deposited on the top surface of the gate material 504 in the recess 404 as shown in FIG. 5(a). The composite cap layer 506 is used to protect the gate material 504. The composite cap layer 506 is then polished by a CMP technique to make the top surface of the composite cap layer 506 coincident with the top surface of the pad nitride 206. Also, FIG. 5(b) is a top view corresponding to FIG. 5(a), and FIG. 5(a) is a cross-sectional view taken along the X-direction cut line shown in FIG. 5(b).

[0059] In step 116, the STI 402 and nitride spacers 206 are etched to remove the pad nitride layer 206 and bring the top surface of the STI 402 to a height that coincides with the top surface of the pad oxide layer 204, as shown in FIG. 6(a).

[0060] Similarly, up to step 116, two semiconductor layers 302 (sheet channel layers, SCLs) are formed on the two sidewalls of the fin (these two semiconductor layers 302 are named Qleft and Qright respectively), but the top surface of the fin structure does not have SCLs, and therefore the threshold voltage of the upper MOSFET (Qtop) which has a higher doping concentration can be higher than that of the two sidewalls of the FinFET).

[0061] In step 118, the pad oxide layer 204 is etched away and portions of the STI 402 are etched back, as shown in FIG. 6(a).

[0062] Then, in step 120, as shown in Figure 6(a), an oxide 2 layer is deposited to form oxide 2 spacers 802 and a nitride 2 layer is deposited to form nitride 2 spacers 804 on the edges of the gate material 504 and composite cap layer 506. Also, Figure 6(b) is a top view corresponding to Figure 6(a), and Figure 6(a) is a cross-sectional view taken along the X-direction cut line shown in Figure 6(b).

[0063] In another example, the STI 402 can be retained and the pad nitride layer 206 removed so that the STI 402 still surrounds the fin structure. The pad oxide layer 204 is then etched away and portions of the STI 402 are etched away so that the remaining STI 402 still has a top surface higher than the OHS, as shown in FIG. 6(c). Thus, the fin structure is surrounded by the remaining STI 402 with a top surface higher than the OHS.

[0064] Then, in step 122, some exposed silicon areas are etched away to create shallow trenches 902 (eg, about 50 nm deep) for the source and drain of the FinFETs, as shown in FIG. 7(a).

[0065] In step 124, as shown in FIG. 7(a), a thermal oxidation process called the Oxide 3 process is used to grow an Oxide 3 layer 1002 (including both an Oxide 3V layer 10022 that penetrates the vertical sidewalls of the bulk body of the FinFET (assumed to have a sharp (110) crystal orientation) and an Oxide 3B layer 10024 on the top surface of the bottom of the shallow trench 902). Since two sidewalls of the shallow trench 902 have a vertical composite of Oxide 2 spacer 802 and Nitride 2 spacer 804 and the other sidewall of the shallow trench 902 is in contact with Oxide spacer 304 and Nitride spacer 306, the width of the source / drain of the FinFET is not affected at all by such a thermal oxidation process. Also, the thicknesses of the Oxide 3V layer 10022 and Oxide 3B layer 10024 depicted in FIG. 7 and subsequent figures are shown for illustrative purposes only and their geometries are not proportional to the dimensions of the STI 402 depicted in those figures. For example, the thickness of oxide 3V layer 10022 and oxide 3B layer 10024 may be approximately 20-30 nm, while the vertical height of STI 402 may be approximately 200-250 nm.

[0066] However, it is very important to design the oxidation 3 process so that the thickness of the oxide 3V layer 10022 can be very precisely controlled, both under precisely controlled thermal oxidation temperature, timing and growth rate. Thermal oxidation on a well-defined silicon surface should result in 40% of the oxide 3V layer 10022 thickness being taken away from the thickness of the exposed (110) silicon surface of the FinFET body vertical wall, and the remaining 60% of the oxide 3V layer 10022 thickness being considered as an addition to the outside of the FinFET body vertical wall (such 40% and 60% distribution of the oxide 3V layer 10022 to the oxide 2 spacer 802 / nitride 2 spacer 804 is depicted in FIG. 7 by dashed lines for special clarity, because its importance will be clearly stated in the following text). Also, FIG. 7(b) is a top view corresponding to FIG. 7(a), and FIG. 7(a) is a cross-sectional view along the X-direction cut line shown in FIG. 7(b). FIG. 7(c) shows another example of the oxidation 3 process based on the structure of FIG. 6(c).

[0067] In step 126, as shown in FIG. 8(a), first, the oxide 3 layer 1002 is etched away. Then, using a selective growth method such as a SEG technique, n-type LDDs 1102 and 1104 are formed, and then an n+ doped source 1106 and an n+ doped drain 1108 are formed. Thus, the main part of the FinFET is completed. Also, FIG. 8(b) is a top view corresponding to FIG. 8(a), and FIG. 8(a) is a cross-sectional view along the cutting line in the X direction shown in FIG. 8(b). Also, FIG. 8(c) shows another example of a selective growth process based on the structure of FIG. 7(c). As shown in FIG. 8(c), since the fin structure is surrounded by the remaining STI 402 having a top surface higher than the OHS, in the selective growth of the source / drain region, the selectively grown source / drain region is not on the remaining STI 402 but is confined by the remaining STI 402.

[0068] It is also noted that in one example, the bottom surface of the gate structure (not shown) over the STI regions may be approximately 10-20 nm lower than the bottom surface of the drain / source regions.

[0069] Please refer to FIG. 9. FIG. 9(a) is a cross-sectional view along the Y-direction cutting line shown in FIG. 8(b). As shown in FIG. 9(a), both Qleft and Qright, which are SEG-grown p-type doped silicon channel regions, are clearly visible on the cross-sectional view. As shown in FIG. 9(b), there are Y-direction concentration profiles LYN and LYP of the prior art, and the Y-direction concentration profile LYN corresponds to the dashed line L1 shown in FIG. 9(a). Similarly, as shown in FIG. 9(c), there are X-direction concentration profiles LXN and LXP of the prior art, and the X-direction concentration profile LXN corresponds to the dashed line L2 shown in FIG. 9(a). The doping concentrations of Qleft and Qright (e.g., 1×10 16 From 3×10 18 ) is smaller than that of the FinFET fin body (e.g., 5×10 18 ) is evident. Also, in another embodiment, the fin structure can be etched as a trapezoidal shape for better short channel effect control, as shown in FIG. 10. Furthermore, in another embodiment, the fin body can be undoped.

[0070] The main inventive points are described below. Both drain and source of FinFET are formed by SEG technology except that they are doped with n-type dopant with higher concentration than Qleft and Qright, so that seamless contact area is clearly created between drain and channel and between source and channel, respectively. All of channel, drain and source are completed without ion implantation, and high temperature thermal annealing is not required to remove damage caused by hard bombardment of drain and source formation. Also, a solid wall (e.g. oxide spacer 304 and nitride spacer 306 shown in FIG. 3) clamps the active area or narrow fin structure, especially the sidewall of the fin structure. This solid clamp wall can be a single layer or other composite cap layer to protect the narrow fin structure from collapsing during the formation of source / drain or gate of FinFET. Moreover, STI 402 (shown in FIG. 4) further surrounds or clamps the active area or narrow fin structure, especially the sidewall of the fin structure, to protect the narrow fin structure from collapsing during the formation of source / drain or gate of FinFET. Therefore, even if the height of the fin structure (e.g., 60-300 nm, etc.) is much larger than the width of the fin structure of a FinFET (e.g., 3-7 nm, etc.), the fin structure protected by the solid wall of the present invention is less likely to be vulnerable during subsequent processes (e.g., source / drain formation, gate formation, etc.).

[0071] As shown in FIG. 6, another advantage of the present invention is that the thickness of the oxide 2 spacer 802 and nitride 2 spacer 804 formed on the edge of the gate region (i.e., gate material 504 and composite cap layer 506) can be controlled, and the thickness of the oxide 3V layer 10022 and oxide 3B layer 10024 formed by the thermal oxidation process (shown in FIG. 7) can also be controlled, so that the edge of the source / drain can be aligned or substantially aligned with the edge of the gate region (as shown in FIG. 8), especially the source / drain formed by the SEG technique. Thus, according to the present invention, the relative position or distance between the edge of the source / drain and the edge of the gate region can be controlled, and may depend on the thickness of the spacer formed on the edge of the gate region and / or the thickness of the oxide layer (such as the oxide 3V layer 10022 shown in FIG. 7, but the oxide 3V layer 10022 is removed in FIG. 8). Thus, the effective channel length Leff (shown in FIG. 8) can be controlled so that the gate-induced drain leakage (GIDL) current problem can be improved.

[0072] In another embodiment, the selective epitaxial growth (SEG) technique of growing the monolithic p-type doped silicon thin sheet channel layer (semiconductor layer 302) shown in FIG. 3 is not required, but solid walls (such as oxide spacer 304 and nitride spacer 306 shown in FIG. 3) are still formed to clamp the active area or narrow fin structure, especially the sidewalls of the fin structure. Then, similar processes as in FIG. 4 to FIG. 8 can be performed to form another fin structure (as shown in FIG. 11) without the thin sheet channel layer (semiconductor layer 302). Of course, in another embodiment, the fin structure can be etched as a trapezoidal shape for better short channel effect control. Again, as shown in FIG. 11, the fin structure of this embodiment protected by the solid walls is less vulnerable during subsequent processes (such as source / drain formation, gate formation, etc.) even if the height of the fin structure (such as 60-300 nm) is much larger than the width of the fin structure (such as 3-7 nm). The relative position or distance between the edge of the source / drain and the edge of the gate region can be controlled and may depend on the thickness of the spacer formed on the edge of the gate region and / or the thickness of the oxide layer (such as the oxide 3V layer 10022 shown in FIG. 11 ). Thus, the effective channel length Leff can be controlled so that the GIDL current problem can be improved.

[0073] Second embodiment Please refer to Figures 12A, 12B, 13, 14, 15, 16, and 17. Figures 12A and 12B are flow charts showing a method for manufacturing a FinFET according to a second embodiment of the present invention, and the method for manufacturing a FinFET in Figures 12A and 12B can also reduce the gate-induced drain leakage (GIDL) current and short channel effect (SCE) of the FinFET, and can form a solid wall to clamp the active region or narrow fin structure of the FinFET. The detailed steps are as follows:

[0074] Process 1200: Start.

[0075] Step 1202: Grow a pad oxide layer 204 based on the p-type well 202 and deposit a pad nitride layer 206 (shown in FIG. 3).

[0076] Step 1204: The active area of ​​the FinFET is defined and portions of the silicon material corresponding to the OHS outside the active area are removed to create trenches 210 and fin structures (shown in FIG. 3).

[0077] Step 1206: Form oxide spacers 304, etch back the oxide spacers 304, and form nitride spacers 306 (shown in FIG. 3).

[0078] Step 1208: Deposit an oxide layer and remove the excess oxide layer using a chemical mechanical polishing (CMP) technique to form STI 402 (shown in FIG. 13).

[0079] Step 1210: Deposit a nitride film 1302 on the STI 402 (shown in FIG. 13).

[0080] Step 1212: Form STI 402 again on the nitride film 1302, define a gate area spanning the active area and the isolation area, etch away the pad oxide layer 204 and the pad nitride layer 206 corresponding to the gate area, and etch back the STI 402 corresponding to the gate area (shown in FIG. 14).

[0081] Step 1214: Form a gate dielectric material 502, deposit a gate material 504 in the recess 404, and then etch back the gate material 504 (as shown in FIG. 14).

[0082] Step 1216: Form a composite cap layer 506, and polish the composite cap layer 506 by a CMP technique (shown in FIG. 14).

[0083] Step 1218: Etch a portion of the STI 402 and remove the pad nitride layer 206 (shown in FIG. 15).

[0084] Step 1220: Etch away the pad oxide layer 204 and etch back the STI 402 (shown in FIG. 15).

[0085] Step 1222: Form oxide 2 spacers 802 and nitride 2 spacers 804 on the edges of the gate material 504 and the composite cap layer 506 (shown in FIG. 15).

[0086] Step 1224: Etch away the exposed silicon (as shown in FIG. 16).

[0087] Step 1226: Thermally grow oxide 3 layer 1002 (shown in FIG. 16).

[0088] Step 1228: Etch away portions of the oxide 3 layer 1002, then form n-type lightly doped drains (LDDs) 1102, 1104, then form n+ doped source 1106 and n+ doped drain 1108 (shown in FIG. 17).

[0089] Step 1230: Finished.

[0090] The differences between the second embodiment and the first embodiment are: 1) in step 1208, as shown in FIG. 13, deposit a thick oxide layer to completely fill the trench 210, remove the excess oxide layer using CMP technology, and etch back the oxide layer to form STI 402, where the top surface of STI 402 is at a certain height lower than OHS; 2) Then, in step 1210, a nitride film 1302 with an appropriate thickness is deposited on the STI 402, as shown in Fig. 13. It is noted that the extending direction of the nitride film 1302 (e.g., horizontal direction) is different from the extending direction of the nitride spacer 306 (e.g., vertical direction) that clamps the fin structure, and the nitride film 1302 can be a support beam for supporting the nitride spacer 306.

[0091] Accordingly, the second embodiment of the present invention provides a composite structure for clamping a fin structure. The composite structure includes a support wall (i.e., semiconductor layer 302, oxide spacer 304, and nitride spacer 306) for clamping the fin structure, the support wall extending in a first direction (i.e., vertical direction) from a bottom of the fin structure. The composite structure further includes a support beam (i.e., nitride membrane 1302) extending in a second direction (i.e., horizontal direction) different from the first direction of the support wall. The support beam can abut against and support the support wall, thereby further strengthening the fin structure and preventing it from collapsing.

[0092] Additionally, the active area or narrow fin structure, particularly the sidewalls of the fin structure, may be further surrounded or clamped by STI 402 (shown in FIG. 13) to prevent the narrow fin structure from collapsing during formation of the source / drains or gates of the FinFET.

[0093] Also, an object of the second embodiment is to ensure additional fin protection against bending and dropping effects.

[0094] Further, in another embodiment, the nitride film 1802 can be deposited several times in step 1210 (as shown in FIG. 18). The multiple deposited nitride films 1802 in combination with the nitride spacers can strengthen the fin structure and prevent the fin structure from collapsing. Similarly, in another embodiment, the nitride film 1904 can be deposited several times as shown in FIG. 19 and the resistance of the source / drain region can be improved by forming a metal-semiconductor junction in the source / drain region. Furthermore, most of the source / drain area is isolated by insulating materials including the bottom structure of the oxide 3B layer 2304 and / or nitride 3 layer 2402, which can significantly reduce the junction leakage. Also, in FIG. 19, a merged semiconductor junction and metal conductor (MSMC) structure is utilized to form source and drain, in this case directly connected to the p-type well 202 of the FinFET (disclosed in U.S. patent application Ser. No. 17 / 983,348, filed Nov. 8, 2022, the corresponding content of which is incorporated herein by reference and will not be further described for the sake of brevity).

[0095] As shown in FIG. 19, again, (1) the fin structure of the second embodiment (shown in FIG. 12A, FIG. 12B) is protected by a solid wall, and (2) the relative position or distance between the edge of the source / drain and the edge of the gate region is controllable and may depend on the thickness of the oxide 3V layer 2302 (and / or the thickness of the spacer formed on the edge of the gate region). Also, by forming a fused metal-semiconductor junction at the source / drain as shown in FIG. 19, the resistance of the source / drain may be improved. Moreover, most of the source / drain regions are isolated by insulating materials including the bottom structure by the oxide 3B layer 2304 and / or nitride 3 layer 2402, therefore the junction leakage may be significantly reduced.

[0096] In another embodiment, as shown in FIG. 20A, the top surface of the STI region surrounding the fin structure is higher than the top surface of the fin structure, so that the selectively grown source / drain regions are confined by the STI region instead of over the STI region. Metal contact plugs can be deposited in the holes between the STI region and the gate region without using a separate contact mask to create such holes. Also, the top, bottom, and sidewalls of the source (drain) region can be in direct contact with the metal, dramatically reducing the contact resistance of the source / drain region. Furthermore, it is possible that the bottom surface (not shown) of the gate structure on or over the STI region surrounding the fin structure can be about 10-20 nm lower than the bottom surface of the drain / source region. In FIG. 20A, the metal material surrounds or contacts the top, bottom, and one sidewall of the n+ doped drain 2806.

[0097] Furthermore, in another embodiment (as shown in FIG. 20B), the difference between FIG. 20A and FIG. 20B is that the deposited TiN 2502 and deposited metal (e.g., tungsten 2504) can be omitted, and simply use the top surface of the nitride 3 layer 2402 as a reference to etch down a portion of the oxide 3V layer 2302 to expose the silicon sidewall 2702, and then use selective growth techniques to form the n-type lightly doped drain (NLDD) 2802 and the n+ doped source 2804 and n+ doped drain 2806, followed by depositing a metal such as tungsten (e.g., tungsten 2504 shown in FIG. 20B). In FIG. 20B, a metal plug contacts the top surface and one sidewall of the n+ doped drain.

[0098] In summary, the FinFET provided by the present invention has several advantages which can be described as follows: (1) A solid wall is formed to clamp the active area or the narrow fin structure, especially the sidewall of the fin structure. Therefore, even if the height of the fin structure (e.g., 60-300 nm) is much larger than the width of the fin structure (e.g., 3-7 nm), the fin structure protected by the solid wall of the present invention is less vulnerable. Furthermore, an additional beam-like structure can be provided to strengthen the solid wall; (2) the relative position or distance between the edge of the source / drain and the edge of the gate region can be controlled and may depend on the thickness of the spacer formed on the edge of the gate region and / or the thickness of the oxide layer (such as, for example, the oxide 3V layer of FIG. 7 or FIG. 16 ); (3) The gate structure is formed in the etched area with smooth line edge roughness (Fig. 4), and therefore the gate structure has smoother edges; (4) By forming a metal-semiconductor junction (as shown in FIG. 20A, FIG. 20B, or FIG. 19) at the source / drain, the resistance of the source / drain may be improved; (5) Most of the source / drain areas are isolated by insulating materials including bottom structures with oxide 3B layer and / or nitride 3B layer (as shown in FIG. 20A, FIG. 20B, or FIG. 19), therefore, junction leakage current can be significantly reduced.

[0099] In addition, the technical features shown in Figures 20A, 20B, or 19, the gate formation described herein, and advantages (2)-(5) described above can be applied not only to FinFETs, but also to other types of transistors (e.g., planar transistors).

[0100] Also, when using selective growth techniques to form the source / drain, it is not limited to the LDD and the subsequent heavily doped regions, and the concentration of the selectively grown source / drain can be <110> The gradient may be gradually increased from the surface, from n- to n+, or from n- to n++ to n+, or other gradual or step-like profile.

[0101] While the invention has been illustrated and described with reference to embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. a substrate having an initial semiconductor surface; a gate structure coupled to the initial semiconductor surface, the gate structure including a gate extension region; a first epitaxial conductive region adjacent one side of the gate structure; a second epitaxial conductive region adjacent the other side of the gate structure; a shallow trench isolation region adjacent to the first epitaxial conductive region and the second epitaxial conductive region; a bottom surface of the gate extension region over a portion of the shallow trench isolation region is below a bottom surface of the first epitaxial conductive region or a bottom surface of the second epitaxial conductive region. Transistor structure.

2. 10. The transistor structure of claim 1, further comprising a metal region between the gate structure and the shallow trench isolation region, at least two sides of the first epitaxial conductive region being in contact with the metal region.

3. 3. The transistor structure of claim 2, wherein the metal region contacts a top surface and an outermost sidewall of the first epitaxial conductive region.

4. 4. The transistor structure of claim 3, wherein the metal region further contacts a bottom surface of the first epitaxial conductive region.

5. 2. The transistor structure of claim 1, wherein the shallow trench isolation region extends above the initial semiconductor surface of the substrate, the shallow trench isolation region surrounds the first epitaxial conductive region and the second epitaxial conductive region, and neither the first epitaxial conductive region nor the second epitaxial conductive region overlies the shallow trench isolation region.

6. a first recess below the initial surface of the substrate and containing the first epitaxial conductive region; a metal region surrounded by the shallow trench isolation region and in contact with the first epitaxial conductive region; an L-shaped isolator in the first recess; Further comprising: the bottom surface of the first epitaxial conductive region and the bottom surface of the metal region are insulated from the substrate by the L-shaped isolator. The transistor structure of claim 5.

7. 7. The transistor structure of claim 6, wherein an edge of said L-shaped isolator is aligned with said one side of said gate structure.

8. 2. The transistor structure of claim 1 , wherein the first epitaxial conductive region extends along a first direction and includes a first surface extending along the first direction, the first surface of the first epitaxial conductive region being substantially perpendicular to the original semiconductor surface of the substrate.

9. 9. The transistor structure of claim 8, wherein the first epitaxial conductive region further includes a second surface extending along the first direction, the second surface of the first epitaxial conductive region being substantially perpendicular to the original semiconductor surface of the substrate.

10. 9. The transistor structure of claim 8, wherein the first epitaxial conductive region is rectangular in shape.

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