Compound semiconductor structure and manufacturing method thereof

Abstract

To provide a compound semiconductor structure and a manufacturing method thereof, capable of preventing reduced resistance of a Si substrate.SOLUTION: A compound semiconductor structure CS1 includes a Si substrate 1 and a SiC layer 2 formed on a main surface of the Si substrate 1. The SiC layer 2 includes a region 21 and a region 22 adjacent to the region 21 on a side opposite to a side where the Si substrate 1 exists in the region 21. An average concentration of an impurity atom comprising at least one of a B atom and an Al atom in the region 22 is higher than an average concentration of the impurity atom in the region 21, and a concentration of the impurity atom in the region 21 is lowered in accordance with approach to the Si substrate 1 from an interface between the region 22 and the region 21.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present invention relates to a compound semiconductor structure, and more particularly to a compound semiconductor structure having a Si (silicon) substrate and a SiC (silicon carbide) layer, and a method for manufacturing the compound semiconductor structure. [Background technology]

[0002] The rapid development of mobile phones and other devices has created a need for high-frequency, high-power wireless transceivers (such as satellite communication devices and base stations) as the next-generation wireless infrastructure. Compared to Si, GaN (gallium nitride) has a higher dielectric breakdown field value, higher electron mobility, and a higher saturated electron velocity. For this reason, devices using GaN can withstand higher voltages than conventional electronic devices using Si, making them suitable for high-power applications. In addition, GaN has higher electron mobility and a higher saturated electron velocity than SiC. For this reason, GaN is being increasingly used in high-frequency devices such as power transistors that operate with high-frequency signals and handle large amounts of power.

[0003] In particular, high-frequency devices used in mobile phone base stations are being replaced from conventional Si-based devices to GaN-based devices due to the advantages of being able to be air-cooled and not needing to lower the power supply voltage.

[0004] The substrate that serves as the base for growing the GaN layer used in high frequency devices is required to have high resistance. Increasing the resistance of the substrate has the following advantages:

[0005] In high-frequency devices, unintended parasitic capacitance is formed between the substrate and the surface electrode, and high-frequency signal current flows to the substrate side via this parasitic capacitance, which may cause power loss. By increasing the resistance of the substrate, the high-frequency signal current via the parasitic capacitance can be reduced, thereby suppressing power loss.

[0006] In addition, when multiple high-frequency elements are formed on a semi-insulating substrate, it is necessary to reduce the leakage current between the elements by electrically isolating them from each other. By increasing the resistance of the substrate, the elements are electrically isolated from each other, which reduces the leakage current.

[0007] Conventionally, as substrates serving as bases for growing a GaN layer, SiC bulk substrates, GaN bulk substrates, sapphire substrates, Si substrates, and the like have been used.

[0008] Among these substrates, SiC bulk substrates have the advantage that they can be made highly resistive by doping V (vanadium) atoms into the SiC crystal. This is because V atoms act to compensate for excess carriers in the SiC crystal. However, since it is difficult to fabricate large-diameter SiC substrates, SiC bulk substrates have the disadvantages that it is difficult to make the GaN layer large-diameter and that they are expensive.

[0009] Like SiC bulk substrates, GaN bulk substrates also have the disadvantages that it is difficult to increase the diameter of the GaN layer and that they are expensive.

[0010] The sapphire substrate has the problem of low thermal conductivity and poor heat dissipation.

[0011] On the other hand, a high-resistance Si substrate has the advantage that the GaN layer can be fabricated in a large size and the cost can be reduced. However, when a high-resistance Si substrate is used, Ga (gallium) atoms may diffuse into the Si substrate during the growth of the GaN layer, resulting in a low resistance of the Si substrate. Furthermore, a eutectic reaction may occur between the Ga atoms and the Si substrate, resulting in a killer defect called meltdown etching. In addition, when a high-resistance Si substrate is used, a buffer layer made of an AlN (aluminum nitride)-based material is generally formed between the Si substrate and the GaN layer. The Al (aluminum) atoms in this buffer layer may diffuse into the Si substrate, resulting in a low resistance of the Si substrate. For this reason, when a high-resistance Si substrate is used, unless an appropriate diffusion barrier layer is inserted between the Si substrate and the GaN layer to prevent the diffusion of Ga atoms and Al atoms into the Si substrate, the GaN high-frequency device fabricated will not exhibit sufficient high-frequency characteristics.

[0012] In light of the above-mentioned background, there is a demand for a base substrate that can produce a large-diameter GaN layer at low cost while suppressing the adverse effects of diffusion of Ga atoms, Al atoms, etc. Regarding this demand, the following Patent Document 1 and the like disclose a technique of using a substrate including a Si substrate and a SiC layer formed on the Si substrate as a base substrate when growing a GaN layer. The SiC layer includes a first SiC layer formed on the main surface of the Si substrate and a second SiC layer formed on the side farther from the Si substrate than the first SiC layer. The average concentration of B (boron) atoms in the first SiC layer is higher than the average concentration of V atoms in the first SiC layer. The average concentration of V atoms in the second SiC layer is higher than the average concentration of B atoms in the second SiC layer.

[0013] According to the technology of the following Patent Document 1, by forming a SiC layer on a Si substrate, a SiC layer having the same diameter as the Si substrate can be formed, so that a GaN layer with a large diameter can be fabricated at a low cost compared to the case of using a SiC bulk substrate. In addition, the diffusion of Ga atoms, Al atoms, etc. is suppressed by the SiC layer, so that the adverse effects of the diffusion of Ga atoms, Al atoms, etc. can be suppressed. Furthermore, n-type carriers concentrated in the stacking fault portion in the first SiC layer are bonded with B atoms and disappear, and n-type carriers in the second SiC layer are compensated by V atoms. As a result, the resistance of the SiC layer can be increased. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] JP 2019-117908 A Summary of the Invention [Problem to be solved by the invention]

[0015] According to the technology of Patent Document 1, it is possible to increase the resistance of the SiC layer. However, in the technology of Patent Document 1, B atoms in the first SiC layer diffuse due to heat during film formation and penetrate into the Si substrate, locally converting the portion of the Si substrate near the interface with the SiC layer to p-type. As a result, there is a problem that the resistance of the Si substrate decreases.

[0016] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a compound semiconductor structure capable of preventing a decrease in the resistance of a Si substrate, and a method for manufacturing the compound semiconductor structure. [Means for solving the problem]

[0017] A compound semiconductor structure according to one aspect of the present invention comprises a Si substrate and a SiC layer formed on a main surface of the Si substrate, the SiC layer including a first region and a second region adjacent to the first region on a side of the first region opposite to the side on which the Si substrate is present, the average concentration of impurity atoms consisting of at least one of B atoms and Al atoms in the second region being higher than the average concentration of impurity atoms in the first region, and the concentration of impurity atoms in the first region decreasing from the interface with the second region toward the Si substrate.

[0018] In the above compound semiconductor structure, preferably, the SiC layer further includes a third region located on the opposite side of the second region to the side on which the first region is located, the third region including V atoms, the average concentration of the impurity atoms in the second region being higher than the average concentration of V atoms in the second region, and the average concentration of the V atoms in the third region being higher than the average concentration of the impurity atoms in the third region.

[0019] In the above compound semiconductor structure, the average concentration of impurity atoms in the first region is preferably higher than the average concentration of impurity atoms in the Si substrate.

[0020] In the above compound semiconductor structure, the first region is preferably adjacent to the Si substrate.

[0021] In the above compound semiconductor structure, the SiC layer may further include an enrichment region provided between the first region and the Si substrate, and a concentration of impurity atoms in the enrichment region may increase toward an interface with the Si substrate.

[0022] In the above compound semiconductor structure, preferably, a region of the SiC layer including a boundary with the Si substrate exhibits n-type conductivity.

[0023] In the above compound semiconductor structure, the first region preferably has a thickness of not less than 10 nm and not more than 1 μm.

[0024] The above compound semiconductor structure preferably further comprises an electron transit layer made of GaN formed on the side of the second region opposite to the side on which the first region is present, and an electron barrier layer forming a potential barrier against the two-dimensional electron gas in the electron transit layer.

[0025] The compound semiconductor structure preferably further comprises a control electrode for controlling the two-dimensional electron gas in the electron transit layer.

[0026] A method for manufacturing a compound semiconductor structure according to another aspect of the present invention includes the steps of preparing a Si substrate and forming a SiC layer on a main surface of the Si substrate, the SiC layer including a first region and a second region adjacent to the first region on an opposite side of the first region to the side on which the Si substrate is present, the average concentration of impurity atoms consisting of at least one of B atoms and Al atoms in the second region being higher than the average concentration of impurity atoms in the first region, and the concentration of impurity atoms in the first region decreasing from the interface with the second region toward the Si substrate.

[0027] In the above manufacturing method, preferably, the step of forming the SiC layer includes the steps of: forming a first SiC layer in an atmosphere containing a SiC raw material gas and no raw material gas containing impurity atoms; and forming a second SiC layer adjacent to the first SiC layer in an atmosphere containing a SiC raw material gas and a raw material gas containing impurity atoms while heating the first SiC layer.

[0028] In the above manufacturing method, preferably, in the step of forming the first SiC layer, the first SiC layer is formed in an atmosphere in which no impurities are intentionally doped.

[0029] In the above manufacturing method, preferably, the step of forming the SiC layer includes a step of forming a uid-SiC layer, which is a SiC layer that does not contain intentionally doped impurities, on a main surface of a Si substrate, and a step of changing the uid-SiC layer into a SiC layer by implanting ions of impurity atoms consisting of at least one of B atoms and Al atoms into the uid-SiC layer.

[0030] In the above manufacturing method, preferably, the step of forming the SiC layer further includes the step of diffusing ions of the implanted impurity atoms in the SiC layer toward the Si substrate. Effect of the Invention

[0031] According to the present invention, it is possible to provide a compound semiconductor structure capable of preventing a decrease in the resistance of a Si substrate and a method for manufacturing the compound semiconductor structure. [Brief description of the drawings]

[0032] [Figure 1] 1 is a cross-sectional view showing a configuration of a compound semiconductor structure CS1 according to a first embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view showing a first step of a method for manufacturing the compound semiconductor structure CS1 in the first embodiment of the present invention. FIG. [Diagram 3] 4 is a cross-sectional view showing a second step of the method for manufacturing the compound semiconductor structure CS1 in the first embodiment of the present invention. FIG. [Figure 4] 4 is a cross-sectional view showing a third step of the method for manufacturing the compound semiconductor structure CS1 in the first embodiment of the present invention. FIG. [Diagram 5] 2 is a diagram showing a concentration distribution of impurity atoms in a depth direction inside a SiC layer 2 and a Si substrate 1 in a compound semiconductor structure CS1 according to a first embodiment of the present invention. FIG. [Figure 6] 3 is a diagram showing the distribution of V atom concentration in the depth direction inside SiC layer 2 and Si substrate 1 in the first embodiment of the present invention. FIG. [Figure 7] FIG. 2 is a diagram showing a cross section of a SiC layer formed on the surface of a Si substrate. [Figure 8] 1A to 1C are diagrams illustrating the effect of adding impurity atoms and V atoms in an embodiment of the present invention. [Figure 9] FIG. 11 is a diagram showing the concentration distribution of impurity atoms in a depth direction inside a SiC layer 2 and a Si substrate 1 in a second embodiment of the present invention. [Figure 10]FIG. 13 is a diagram showing the analysis results of the concentration distribution of each of B atoms and N atoms in an actually fabricated compound semiconductor structure CS1, the analysis results being obtained by SIMS (Secondary Ion Mass Spectrometry). [Figure 11] 11 is a cross-sectional view showing a first step of a method for manufacturing a compound semiconductor structure CS1 according to a third embodiment of the present invention. FIG. [Figure 12] 11 is a cross-sectional view showing a second step of the method for manufacturing the compound semiconductor structure CS1 according to the third embodiment of the present invention. FIG. [Figure 13] FIG. 11 is a cross-sectional view showing a configuration of a compound semiconductor structure CS2 according to a fourth embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0034] [First embodiment]

[0035] FIG. 1 is a cross-sectional view showing a configuration of a compound semiconductor structure CS1 according to a first embodiment of the present invention.

[0036] With reference to FIG. 1, a compound semiconductor structure CS1 (an example of a compound semiconductor structure) in the first embodiment is a substrate, and includes a Si substrate 1 (an example of a Si substrate) and a SiC layer 2 (an example of a SiC layer).

[0037] The Si substrate 1 is made of, for example, high resistance crystal of Fz-Si. The (111) plane is exposed on the surface 1a (one example of the main surface of the Si substrate) of the Si substrate 1. The (100) plane or the (110) plane may be exposed on the surface 1a of the Si substrate 1 depending on the orientation of the GaN crystal to be finally formed. The Si substrate 1 has, for example, a diameter of 6 inches and a thickness of 1000 μm.

[0038] The SiC layer 2 is formed on the surface 1a of the Si substrate 1. The SiC layer 2 is made of, for example, 3C-SiC. In particular, when the SiC layer 2 is epitaxially grown on the surface 1a of the Si substrate 1, the SiC layer 2 is generally made of 3C-SiC. At least a portion of the SiC layer 2 contains impurity atoms consisting of at least one of B atoms and Al atoms. Unless otherwise specified, in this specification, the impurity atoms refer to atoms consisting of at least one of B atoms and Al atoms.

[0039] The SiC layer 2 includes a region 21 (an example of a first region), a region 22 (an example of a second region), and a region 23 (an example of a third region). Each of the regions 21, 22, and 23 is stacked in the thickness direction (the vertical direction in FIG. 1).

[0040] Region 21 is formed on the front surface 1a side of Si substrate 1. In the present embodiment, region 21 is adjacent to Si substrate 1. Region 21 has a thickness of, for example, 10 nm or more and 1 μm or less, preferably 10 nm or more and 500 nm or less, and more preferably 50 nm or more and 350 nm or less.

[0041] Region 22 is adjacent to region 21 on the side opposite to the side of region 21 where Si substrate 1 is present (upper side in FIG. 1). Region 22 has a thickness of, for example, 0.1 μm or more and 2.0 μm or less. The stacking fault density in each of region 21 and region 22 is, for example, 1×10 5 Greater than strands / cm.

[0042] Region 23 is formed on the side of region 22 opposite to the side where region 21 exists (upper side in FIG. 1). Region 23 has a thickness of, for example, 0.2 μm or more and 2.7 μm or less. The stacking fault density in region 23 is lower than the stacking fault density in each of regions 21 and 22, and is, for example, 1×10 5 Less than strands / cm.

[0043] The compound semiconductor structure CS1 may further include a GaN layer formed on the surface 2a side of the SiC layer 2, a buffer layer formed between the SiC layer 2 and the GaN layer, and the like.

[0044] 2 to 4 are cross-sectional views showing a method for manufacturing the compound semiconductor structure CS1 according to the first embodiment of the present invention in the order of steps.

[0045] 2, first, the Si substrate 1 is prepared. Next, the surface 1a of the Si substrate 1 is carbonized to form the SiC layer 211. As a result, the Si present on the surface 1a of the Si substrate 1 is converted to SiC, and the surface 1a of the Si substrate 1 regresses toward the Si substrate 1. The surface 1a of the Si substrate 1 is carbonized at atmospheric pressure and at a temperature of 1050° C. or higher and 1250° C. or lower. When the surface 1a of the Si substrate 1 is carbonized, a source gas containing C (carbon) atoms may be used. An example of the source gas containing C atoms is CH 4 (Methane), C 3 H 8 (propane) and other feed gases are used.

[0046] The SiC layer 211 is formed in an atmosphere that does not contain a source gas that contains impurity atoms. The SiC layer 211 is preferably formed in an atmosphere that is not intentionally doped with impurities.

[0047] The carbonization of the surface 1a of the Si substrate 1 may be omitted. In this case, the SiC layer 212 is formed directly on the surface 1a of the Si substrate 1.

[0048] Next, a SiC layer 212 (an example of a first SiC layer) is formed on the surface 211a of the SiC layer 211 (in other words, on the 1a side of the Si substrate 1). The SiC layer 212 is, for example, 1×10 -6 The SiC source gas is introduced to the surface 211a of the SiC layer 211 while the Si substrate 1 and the SiC layer 211 are heated to a temperature of, for example, 850° C. to 1050° C. under a high vacuum of 0.1 Pa or less.

[0049] The SiC layer 212 is formed in an atmosphere that contains a source gas of SiC but does not contain a source gas containing impurity atoms. The SiC layer 212 is preferably formed in an atmosphere that is not intentionally doped with impurities. A SiC layer that is not intentionally doped with impurities, such as the SiC layers 211 and 212, is called a uid (Unintentional-dope)-SiC layer. The uid-SiC layer does not mean a SiC layer that is not doped with impurities at all. The uid-SiC layer contains a small amount of impurity atoms due to the diffusion of atoms from adjacent layers and the natural incorporation of atoms contained in the atmosphere (called autodoping).

[0050] The source gas for SiC when forming the entire SiC layer 2 including the SiC layer 212 is, for example, SiH 4 (Monosilane), SiH 3 Cl(monochlorosilane), SiH 2 Cl 2 (Dichlorosilane), SiHCl 3 (Trichlorosilane), SiCl 4 (Silicon tetrachloride), Si 2 H 6 (Disilane), Si 3 H 8 (Trisilane), SiH 3 (CH 3 ) (monomethylsilane), SiCl 3 (CH 3 ) (methyltrichlorosilane) or the like is used. When forming the SiC layer 2, a source gas of C may be used, or C in the atmosphere may be used without using a source gas of C.

[0051] When the SiC layer 2 is formed, N (nitrogen) atoms present in the atmosphere are incorporated into the SiC layer 2. Therefore, the SiC layer 2 contains N atoms throughout. The N atoms have the property of generating n-type conductive carriers in the SiC layer 2.

[0052] 3, next, a SiC layer 221 (an example of a second SiC layer) containing impurity atoms is formed on surface 212a of SiC layer 212. SiC layer 221 has a concentration of, for example, 1×10 -6 The SiC layer 221 is formed by introducing a source gas of SiC and a source gas containing impurity atoms to the surface 212a of the SiC layer 212 while the Si substrate 1 and the SiC layers 211 and 212 are heated to a temperature of, for example, 850° C. to 1050° C. under a high vacuum of 1000 Pa or less. The SiC layer 221 is formed in an atmosphere containing the source gas of SiC and the source gas containing impurity atoms. The source gas containing impurity atoms is H 2 It is preferable to dilute it with (hydrogen) gas to a concentration of about 100 ppm.

[0053] When the impurity atoms include B atoms, the source gas containing B atoms is, for example, B(C 2 H 5 ) 3 (triethylboron), B(CH 3 ) 3 (trimethylboron), or B 2 H 6 When the impurity atoms include Al atoms, the source gas containing Al is, for example, AlCl 3 (Aluminum chloride), Al(CH 3 ) 3 (trimethylaluminum) or Al(C 2 H 5 ) 3 (Triethylaluminum), etc. are used.

[0054] Some of the impurity atoms in SiC layer 221 are diffused by heat during the formation of SiC layer 221 and SiC layer 231 (described later), and penetrate into SiC layers 212 and 211. As a result, SiC layers 211 and 212 are no longer uid-SiC layers. The concentration of impurity atoms in SiC layer 221 is controlled by adjusting the flow rate of a source gas containing impurity atoms during the growth of SiC layer 221.

[0055] 4, next, a SiC layer 231 containing V atoms is formed on a surface 221a of the SiC layer 221. The SiC layer 231 has a concentration of, for example, 1×10 -6 The SiC layer 231 is formed by introducing a source gas of SiC and a source gas containing V atoms to the surface 221a of the SiC layer 221 while the Si substrate 1 and the SiC layers 211, 212, and 221 are heated to a temperature of, for example, 850° C. to 1050° C. under a high vacuum of 0.1 Pa or less. The SiC layer 231 is formed in an atmosphere containing the source gas of SiC and the source gas containing V atoms. Some of the impurity atoms in the SiC layer 221 may be diffused by the heat generated when the SiC layer 231 is formed and may enter the SiC layer 231.

[0056] The source gas containing V atoms is, for example, VCl 4 (vanadium tetrachloride) and V[N(CH 3 ) 2 ] 4 (tetrakisdimethylaminovanadium) and other source gases are used. The source gas for V atoms is H 2 The concentration of V atoms in the SiC layer 231 may be controlled by adjusting the flow rate of a source gas containing V atoms during the growth of the SiC layer 231.

[0057] It is preferable to adjust the concentration of the impurity doped into SiC layer 221 and the thickness of SiC layers 211 and 212 so that the impurity atoms diffusing inside SiC layers 211 and 212 are stopped before reaching Si substrate 1.

[0058] As a result of the diffusion of the impurity atoms, SiC layers 211 and 212 become region 21 of SiC layer 2. SiC layer 221 becomes region 22 of SiC layer 2. SiC layer 231 becomes region 23 of SiC layer 2. After forming SiC layer 231, surface 2a of SiC layer 2 may be planarized using CMP (Chemical Mechanical Polishing) or the like. In this case, the arithmetic mean roughness Ra of surface 2a of SiC layer 2 after planarization may be less than 0.5 nm (Ra<0.5 nm).

[0059] Through the above steps, the compound semiconductor structure CS1 shown in FIG. 1 is obtained.

[0060] 5 is a diagram showing the concentration distribution of impurity atoms in the depth direction inside the SiC layer 2 and the Si substrate 1 in the compound semiconductor structure CS1 according to the first embodiment of the present invention. When the SiC layer 2 does not contain Al atoms, the distribution in FIG. 5 relates to the concentration distribution of B atoms. When the SiC layer 2 does not contain B atoms, the distribution in FIG. 5 relates to the concentration distribution of Al atoms. When at least a part of the SiC layer 2 contains both B atoms and Al atoms, the distribution in FIG. 5 relates to the distribution of the total concentration of B atoms and Al atoms.

[0061] 4 and 5, impurity atoms are added to SiC layer 221 when SiC layer 221 is formed. The concentration distribution of the impurity atoms in the depth direction is preferably a substantially constant value in region 22. The average concentration N22B (atoms / cm 3 ) is 1 × 10 17 (atoms / cm 3 ) or more 1×10 20 (atoms / cm 3 ) or less.

[0062] Furthermore, impurity atoms are not actively added to SiC layers 211 and 212 when they are formed. Some of the impurity atoms in SiC layer 221 penetrate into SiC layers 212 and 211 due to diffusion caused by heat when forming SiC layers 221 and 231. For this reason, the concentration of impurity atoms in region 21 decreases from the interface between region 22 and region 21 toward Si substrate 1. As a result, the average concentration N22B (atoms / cm) of impurity atoms in region 22 is 3 ) is the average concentration of impurity atoms in region 21, N21B (atoms / cm 3 ) (N22B>N21B). The concentration of impurity atoms in region 21 is 1×10 16 (atoms / cm 3 ) or more 1×10 20(atoms / cm 3 ) or less.

[0063] Similarly, some of the impurity atoms in the SiC layer 221 are diffused by the heat generated when the SiC layer 231 is formed and penetrate into the SiC layer 231. Therefore, the concentration of the impurity atoms in the region 23 decreases with increasing distance from the interface between the region 22 and the region 23 to the region 22. As a result, the average concentration N22B (atoms / cm) of the impurity atoms in the region 22 3 ) is the average concentration of impurity atoms in region 23, N23B (atoms / cm 3 ) (N22B>N23B).

[0064] In addition, SiC layers 211 and 212 are present between the SiC layer 221 and the Si substrate 1. The SiC layers 211 and 212 act as barriers to impurity atoms diffusing from within the SiC layer 221, and suppress the intrusion of the impurity atoms into the Si substrate 1. As a result, the average concentration N21B (atoms / cm) of impurity atoms in the region 21 is 3 ) is the average concentration of impurity atoms in the Si substrate 1, N1B (atoms / cm 3 ) (N21B>N1B).

[0065] FIG. 6 is a diagram showing the distribution of V atom concentration in the depth direction inside SiC layer 2 and Si substrate 1 in the first embodiment of the present invention.

[0066] 4 and 6, V atoms are added to SiC layer 231 when forming SiC layer 231. It is preferable that the concentration distribution of V atoms in the depth direction in region 23 is approximately constant.

[0067] Moreover, V atoms are not added to each of the SiC layers 211, 212, and 221 when each of the SiC layers 211, 212, and 221 is formed. On the other hand, some of the V atoms in the SiC layer 231 are diffused by the heat generated when the SiC layer 231 is formed, and penetrate into the inside of the SiC layer 221. For this reason, the concentration of V atoms in the region 22 decreases from the interface between the region 22 and the region 23 toward the Si substrate 1. As a result, the average concentration of V atoms in the region 23, N23V (atoms / cm 3 ) is the average concentration of impurity atoms in region 22, N22V (atoms / cm 3 ) is higher (N23V>N22V).

[0068] It is noted that the SiC layer 231 does not necessarily have to be formed, and the SiC layer 2 does not necessarily have to include the region 23.

[0069] Next, effects of the embodiment will be described.

[0070] Figure 7 shows a cross section of a SiC layer formed on the surface of a Si substrate. Figure 7(a) is an image taken with a TEM (Transmission Electron Microscope). Figure 7(b) is an illustration of the image in Figure 7(a) with necessary explanations added.

[0071] Referring to Figure 7, stacking faults occur in the SiC layer formed on the surface of the Si substrate. Stacking faults that occur in the SiC layer appear in the cross section of the SiC layer as straight lines extending in a direction inclined (diagonally upward) relative to the normal to the surface of the Si substrate (the growth direction of SiC). Stacking faults in the SiC layer have the property of propagating away from the Si substrate and disappearing when they collide with other stacking faults. For this reason, stacking faults in the SiC layer are concentrated near the interface with the Si substrate and gradually decrease with increasing distance from the Si substrate.

[0072] Fig. 8 is a diagram for explaining the effect of adding impurity atoms and V atoms in one embodiment of the present invention. In Fig. 8, only B atoms are shown as impurity atoms, but the impurity atoms may be Al atoms or both B and Al atoms. In Fig. 8(b), the state in which an n-type carrier is bonded to a V atom or a B atom means the state in which the n-type carrier is bonded to a p-type carrier of a V atom or a B atom and disappears.

[0073] 8, generally, dopants tend to concentrate in stacking fault portions, and the portions tend to be locally made n-type or p-type at a higher concentration than the surroundings. As described with reference to FIG. 7, regions 21 and 22 close to the Si substrate 1 in the SiC layer 2 have a higher stacking fault density than region 23. In regions 21 and 22, N atoms unintentionally doped in the SiC layer 2 when forming the SiC layer 2 concentrate in the stacking fault portions, generating carriers having n-type conductivity (n-type carriers).

[0074] Therefore, in the first embodiment, of the regions 21 and 22 having a high stacking fault density in the SiC layer 2, the region 22 is doped with impurity atoms, and the region 23 having a low stacking fault density in the SiC layer 2 is doped with V atoms.

[0075] The reason for doping region 22 with impurity atoms is as follows. B atoms and Al atoms are impurities that generate carriers having p-type conductivity (p-type carriers) in the SiC layer. Like N atoms, B atoms and Al atoms have the property of easily concentrating in stacking fault areas. For this reason, the p-type carriers generated by doping with B atoms or Al atoms effectively combine with the n-type carriers concentrated in the stacking fault areas, eliminating the n-type carriers. As a result, the number of carriers in region 22 decreases, making it possible to increase the resistance of region 22.

[0076] On the other hand, B atoms and Al atoms form a relatively deep acceptor level in the band gap of SiC. Therefore, when B atoms and Al atoms are doped into the SiC layer, their contribution to making the SiC layer p-type is small. Therefore, by using B atoms or Al atoms as a dopant for region 22, it is possible to prevent region 22 from becoming excessively p-type and having low resistance.

[0077] In addition, some of the impurity atoms in SiC layer 221 are diffused by heat when SiC layer 221 and SiC layer 231 are formed, and penetrate into SiC layers 212 and 211 .

[0078] The p-type carriers generated by the B atoms or Al atoms penetrating into the SiC layers 212 and 211 effectively combine with some of the n-type carriers concentrated in the stacking faults inside the SiC layers 212 and 211, and annihilate the n-type carriers. As a result, the number of carriers in the region 21 decreases, and the resistance of the region 21 can be increased.

[0079] Furthermore, when forming the SiC layers 211 and 212 that become the region 21, impurity atoms are not directly added to the SiC layers 211 and 212. Therefore, the SiC layers 211 and 212 act as a barrier to the impurity atoms diffusing from within the SiC layer 221, and suppress the impurity atoms from penetrating into the Si substrate 1. As a result, the portion of the Si substrate 1 near the interface with the SiC layer 2 can be prevented from becoming locally p-type, and the resistance of the Si substrate 1 can be prevented from decreasing.

[0080] Furthermore, V atoms have the property of forming a deep level exactly at the center of the band gap of SiC, and are impurities that have the property of compensating carriers. By doping V atoms into region 23, which has a low stacking fault density in the SiC layer, the n-type carriers present in small amounts in region 23 are compensated by the V atoms, and region 23 can be made highly resistive. As a result, the carrier concentration can be reduced throughout the entire SiC layer 2, and the SiC layer 2 can be made highly resistive.

[0081] According to this embodiment, it is possible to obtain a highly insulating compound semiconductor substrate (compound semiconductor structure CS1) suitable for fabricating high-frequency elements, since it is possible to increase the resistance over a wide range of the SiC layer 2 and the Si substrate 1. Furthermore, by forming high-frequency elements in the compound semiconductor structure CS1, it is possible to fabricate next-generation high-frequency devices for beyond-5G and 6G.

[0082] In addition, since the concentration of impurity atoms in region 21 is low near the interface with Si substrate 1, n-type carriers may remain in the region in region 21 near the interface with Si substrate 1 without being annihilated by impurity atoms. In this case, the region in SiC layer 2 (region 21) including the interface with Si substrate 1 becomes n-type region 25, which is a region exhibiting n-type conductivity. N-type region 25 has a higher n-type carrier concentration than the n-type carrier concentration in the region other than n-type region 25 in SiC layer 2, and has a lower resistivity than the resistivity of the region other than n-type region 25 in SiC layer 2. From the viewpoint of increasing the resistance of SiC layer 2 and Si substrate 1, it is preferable to adjust the concentration of impurities doped into SiC layer 221 and the thicknesses of SiC layers 211 and 212 so that n-type region 25 is as small as possible.

[0083] [Second embodiment]

[0084] In each of the second to fourth embodiments, the concentration distribution of impurity atoms in the depth direction, the modified manufacturing method, or the configuration of the compound semiconductor structure in the first embodiment will be described. Note that the concentration distribution of impurity atoms in the depth direction, the modified manufacturing method, the configuration of the compound semiconductor structure, and the like other than those described in the second to fourth embodiments are similar to those in the first embodiment, and therefore the description thereof will not be repeated.

[0085] In the second embodiment, a modification of the concentration distribution of impurity atoms in the depth direction inside SiC layer 2 and Si substrate 1 will be described.

[0086] FIG. 9 is a diagram showing the concentration distribution of impurity atoms in the depth direction within SiC layer 2 and Si substrate 1 in the second embodiment of the present invention.

[0087] 9, in this modification, a peak of impurity atoms exists near the interface between Si substrate 1 and SiC layer 2. Due to the presence of this peak, SiC layer 2 further includes region 24 (an example of an increased region) provided between region 21 and Si substrate 1. Region 21 is not adjacent to Si substrate 1. Region 21 and Si substrate 1 are separated from each other by region 24 and are not adjacent to each other. The concentration of impurity atoms in region 24 increases from the interface between region 21 and region 24 to the interface between Si substrate 1 and region 24. Region 24 is a part of SiC layer 211, or a part of SiC layers 211 and 212.

[0088] When HEPA filters are used as a means of removing impurities in the cleaning room, it is known that the borosilicate glass in the HEPA filters is corroded by the hydrofluoric acid contained in the cleaning solution used to clean the cleaning room, releasing B atoms into the cleaning room. For example, for this reason, there is a possibility that impurity atoms are present in the cleaning room.

[0089] When the Si substrate 1 before the formation of the SiC layer 2 is exposed to a cleaning room, a small amount of impurity atoms and N atoms present in the cleaning room are taken into the Si substrate 1. The impurity atoms and N atoms taken into the Si substrate 1 penetrate into the SiC layer 211 or the SiC layer 2 due to heat generated when forming the SiC layers 211 and 212, etc. The peak of impurity atoms in this modification is caused by the impurity atoms that penetrate from the Si substrate 1 into the SiC layer 2 in this manner.

[0090] The occurrence of impurity atom peaks as in this modified example can be prevented by not exposing the Si substrate 1 before the formation of the SiC layer 2 to the cleaning room and by using a filter that does not contain B (such as a chemical filter) as a means for removing impurities in the cleaning room.

[0091] For the above reasons, the amount of impurity atoms taken into the Si substrate 1 is small. Therefore, even if the compound semiconductor structure CS1 has the concentration distribution of impurity atoms in the depth direction of the second embodiment, it has the same effect as the first embodiment. According to this embodiment, the Si substrate 1 can be exposed to an atmosphere in a cleaning room where impurity atoms are present, so that the compound semiconductor structure CS1 can be easily manufactured.

[0092] The inventors of the present application fabricated the compound semiconductor structure CS1 shown in Fig. 1 (wherein the region 23 is omitted), and actually measured the concentration distribution of impurity atoms (here, B atoms) and N atoms in the compound semiconductor structure CS1 in the depth direction. The thickness of the Si substrate 1 was set to 3 µm, and the thickness of the SiC layer 2 was set to 1.5 µm.

[0093] The concentration distribution was measured as follows: The SiC layer 2 and the Si substrate 1 were each removed in the depth direction by sputtering with Cs (cesium) ions from the front side of the SiC layer 2 (upper side in Fig. 1) and the back side of the Si substrate 1 (lower side in Fig. 1), while the concentrations of B atoms and N atoms were each measured using SIMS.

[0094] When measuring the concentration from the Si substrate 1 side, the Si substrate was thinned to a thickness of about 2 μm before sputtering in order to reduce the thickness of the Si substrate 1 to be removed by sputtering. Also, the B atoms and N atoms are pushed deep inside by the Cs ions used in sputtering. For these reasons, there is an error in the depth direction in the concentration distribution obtained.

[0095] Fig. 10 shows the analysis results of the concentration distributions of B atoms and N atoms in an actually fabricated compound semiconductor structure CS1, which are analysis results obtained by SIMS (Secondary Ion Mass Spectrometry). In Fig. 10, curve B1 shows the concentration distribution of B atoms measured from the back surface side of the Si substrate 1. Curve B2 shows the concentration distribution of B atoms measured from the front surface 2a side of the SiC layer 2. Curve N1 shows the concentration distribution of N atoms measured from the back surface side of the Si substrate 1. Curve N2 shows the concentration distribution of N atoms measured from the front surface 2a side of the SiC layer 2.

[0096] 10, according to the concentration distribution of B atoms measured from the front surface 2a side of the SiC layer 2 (curve B2 in FIG. 10), the concentration of B atoms is almost constant in the region 22. The concentration of B atoms gradually decreases in the region 21. The concentration of B atoms increases in the region 24, and a peak of the concentration of B atoms appears at the boundary between the region 24 and the Si substrate 1. According to the concentration distribution of B atoms measured from the rear surface side of the Si substrate 1 (curve B1), the concentration of B atoms is low and almost constant in the Si substrate 1. According to the concentration distribution of N atoms measured from the front surface 2a side of the SiC layer 2 and the concentration distribution of N atoms measured from the rear surface side of the Si substrate 1 (curves N2 and N1), a peak of the concentration of N atoms appears at the boundary between the region 24 and the Si substrate 1. In the regions inside the SiC layer 2 and the Si substrate 1 other than the above-mentioned boundaries, the N concentration is almost constant. This shows that the concentration distribution of B atoms in the actually fabricated compound semiconductor structure CS1 is similar to the modified concentration distribution of impurity atoms in the depth direction shown in FIG.

[0097] [Third embodiment]

[0098] In the third embodiment, a modified example of the manufacturing method for the compound semiconductor structure shown in Fig. 1 will be described. The compound semiconductor structure CS1 can also be manufactured by the manufacturing method of the third embodiment.

[0099] 11 and 12 are cross-sectional views showing a method for manufacturing a compound semiconductor structure CS1 according to the third embodiment of the present invention in the order of steps.

[0100] 11, first, a Si substrate 1 is prepared. Next, a SiC layer 251 is formed on a surface 1a of the Si substrate 1. The SiC layer 251 has a thickness of, for example, 1×10 -6 The SiC is formed by introducing a source gas of SiC onto the surface 1a of the Si substrate 1 while the Si substrate 1 is heated to a temperature of, for example, 850° C. to 1050° C. under a high vacuum of 100 Pa or less.

[0101] The SiC layer 251 is formed in an atmosphere that contains a source gas of SiC and does not contain a source gas containing impurity atoms. The SiC layer 251 is preferably formed in an atmosphere that is not intentionally doped with impurities. In this case, the SiC layer 251 does not contain intentionally doped impurities.

[0102] 12, next, using an ion implantation device, ions of impurity atoms are implanted into the SiC layer 2 from the surface 2a of the SiC layer 2. The depth of the implanted ions of the impurity atoms is adjusted by the acceleration voltage. The concentration of the impurity atoms is adjusted by the current and voltage of the ion beam.

[0103] The ions of the impurity atoms are implanted so that the concentration of the impurity atoms becomes maximum in a region 252 including the center in the depth direction in the SiC layer 251. As a result, the concentration distribution of the impurity atoms in the depth direction in the SiC layer 251 and the Si substrate 1 in the compound semiconductor structure CS1 becomes the same as the concentration distribution shown in FIG. 5. As a result, the SiC layer 251 becomes the SiC layer 2 containing the impurity atoms that are intentionally doped. Note that after the impurity atoms are implanted in the SiC layer 251, the implanted impurity atoms may be diffused in the SiC layer 251 toward the Si substrate 1 by a method such as heating the SiC layer 251.

[0104] [Fourth embodiment]

[0105] In the fourth embodiment, a modified example of the compound semiconductor structure will be described.

[0106] FIG. 13 is a cross-sectional view showing a configuration of a compound semiconductor structure CS2 according to the fourth embodiment of the present invention.

[0107] 13, a compound semiconductor structure CS2 (an example of a compound semiconductor structure) in the fourth embodiment is a device including a HEMT (High Electron Mobility Transistor). The compound semiconductor structure CS2 includes a GaN layer 7 (an example of an electron transit layer), an Al nitride semiconductor layer 10 (an example of an electron barrier layer), a source electrode 11, a gate electrode 13 (an example of a control electrode), and a drain electrode 15 in addition to the configuration of the compound semiconductor structure CS1 shown in FIG.

[0108] The GaN layer 7 is formed on the surface 2a of the SiC layer 2. The GaN layer 7 is formed on the side of the region 22 opposite to the side where the region 21 exists (the upper side in FIG. 11). No impurities are introduced into the GaN layer 7, and the GaN layer 7 serves as an electron transit layer for the HEMT. The GaN layer 7 has a thickness of, for example, 100 nm or more and 10,000 nm or less.

[0109] The GaN layer 7 is formed by using, for example, a metal organic chemical vapor deposition (MOCVD) method. At this time, the raw material gas containing Ga is, for example, Ga(CH 3 ) 3 (trimethylgallium) and Ga(C 2 H 5 ) 3 (triethylgallium), etc. are used. The N source gas is, for example, NH 3 (Ammonia), etc. are used.

[0110] The Al nitride semiconductor layer 10 is in contact with the GaN layer 7 and is formed on the GaN layer 7. The Al nitride semiconductor layer 10 is made of a nitride semiconductor containing Al, for example, Al x Ga 1-xIt is made of a material represented by N(0 < x ≤ 1). Further, the Al nitride semiconductor layer 10 contains Al x In y Ga 1-x-y It may be made of a material represented by N(0 < x ≤ 1, 0 ≤ y < 1). The Al nitride semiconductor layer 10 serves as an electron barrier layer that forms a potential barrier for the two-dimensional electron gas 71 in the GaN layer 7. The Al nitride semiconductor layer 10 has a thickness of, for example, 10 nm or more and 50 nm or less.

[0111] The Al nitride semiconductor layer 10 is formed, for example, using the MOCVD method. At this time, as the raw material gas containing Al, for example, AlCl 3 (aluminum chloride), Al(CH 3 ) 3 (trimethylaluminum) or Al(C 2 H 5 ) 3 (triethylaluminum) etc. are used. As the raw material gas containing Ga, for example, Ga(CH 3 ) 3 (trimethylgallium) or Ga(C 2 H 5 ) 3 (triethylgallium) etc. are used. As the raw material gas containing N, for example, NH 3 (ammonia) etc. are used.

[0112] Each of the source electrode 11, the gate electrode 13, and the drain electrode 15 is formed on the Al nitride semiconductor layer 10 with a space therebetween. The gate electrode 13 makes a Schottky contact with the Al nitride semiconductor layer 10. The gate electrode 13 serves as a control electrode for controlling the two-dimensional electron gas 71 in the GaN layer 7. The gate electrode 13 has a structure in which, for example, an Ni (nickel) layer and an Au (gold) layer are laminated in this order from the side of the Al nitride semiconductor layer 10.

[0113] Each of the source electrode 11 and the drain electrode 15 is in ohmic contact with the Al nitride semiconductor layer 10. Each of the source electrode 11 and the drain electrode 15 has a structure in which, for example, a Ti (titanium) layer and an Al layer are laminated in this order from the Al nitride semiconductor layer 10 side. Each of the source electrode 11, the gate electrode 13, and the drain electrode 15 is formed by, for example, a vapor deposition method or a sputtering method.

[0114] A buffer layer made of AlN or the like may be formed between the SiC layer 2 and the GaN layer 7. The device fabricated using the compound semiconductor structure CS1 may be a high-frequency device such as a transistor, in addition to a HEMT as in this modification.

[0115] According to the fourth embodiment, it is possible to obtain the same effects as those of the first embodiment. In addition, since the high-frequency device is formed on the high-resistance compound semiconductor structure CS1, it is possible to suppress the power loss and the leakage current during the operation of the high-frequency device.

[0116] The inventors of the present application measured the transmission loss in the millimeter wave band (30 GHz) of a conventional compound semiconductor structure and the compound semiconductor structure CS2 of the present embodiment. As a result, the conventional compound semiconductor structure had a transmission loss of more than 1 dB / mm. On the other hand, the compound semiconductor structure CS2 had a transmission loss of less than 1 dB / mm. These results show that the compound semiconductor structure CS2 has low transmission loss and is suitable for use as a millimeter wave device.

[0117] As described above, the present invention provides a compound semiconductor structure and a method for manufacturing the compound semiconductor structure that can prevent the resistance of the Si substrate from decreasing. The present invention can improve the power energy conversion efficiency of the semiconductor element to obtain an energy saving effect, thereby contributing to the achievement of the sustainable development goals.

[0118] [others]

[0119] The above-described embodiments and modifications can be combined as appropriate.

[0120] The above-described embodiments and modifications should be considered as illustrative and not restrictive in all respects. The scope of the present invention is defined by the claims, not the above description, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0121] 1. Si (silicon) substrate (an example of a Si substrate) 1a Surface of the Si substrate 2,211,212,221,231,251 SiC (silicon carbide) layer (an example of a SiC layer, and a first and second SiC layer) 2a, 211a, 212a, 221a Surface of SiC layer 7 GaN (gallium nitride) layer (an example of an electron transport layer) 10. Al (aluminum) nitride semiconductor layer (an example of an electron barrier layer) 11 Source electrode 13 Gate electrode (an example of a control electrode) 15 Drain electrode 21-24,252 SiC layer region (an example of the first to third regions and the increased region) 25 n-type region of SiC layer 71 Two-dimensional electron gas CS1, CS2 Compound semiconductor structure (example of compound semiconductor structure)

Claims

1. A Si substrate; a SiC layer formed on a main surface of the Si substrate; The SiC layer is A first region; and a second region adjacent to the first region on an opposite side to a side of the first region where the Si substrate is present; an average concentration of impurity atoms consisting of at least one of B atoms and Al atoms in the second region is higher than an average concentration of the impurity atoms in the first region; A compound semiconductor structure, wherein a concentration of the impurity atoms in the first region decreases from an interface with the second region toward the Si substrate.

2. 2. The compound semiconductor structure of claim 1, wherein an average concentration of the impurity atoms in the first region is higher than an average concentration of the impurity atoms in the Si substrate.

3. The compound semiconductor structure of claim 1 , wherein the first region is adjacent to the Si substrate.

4. The compound semiconductor structure according to claim 1 , wherein a region of said SiC layer including a boundary with said Si substrate exhibits n-type conductivity.

5. 2. The compound semiconductor structure of claim 1, wherein the first region has a thickness of at least 10 nm and at most 1 μm.

6. an electron transit layer made of GaN formed on a side of the second region opposite to a side on which the first region is present; 2. The compound semiconductor structure according to claim 1, further comprising an electron barrier layer forming a potential barrier against a two-dimensional electron gas in the electron transit layer.

7. The compound semiconductor structure according to claim 6 , further comprising a control electrode for controlling a two-dimensional electron gas in the electron transit layer.

8. providing a Si substrate; forming a SiC layer on a main surface of the Si substrate; The SiC layer is A first region; and a second region adjacent to the first region on an opposite side to a side of the first region where the Si substrate is present; an average concentration of impurity atoms consisting of at least one of B atoms and Al atoms in the second region is higher than an average concentration of the impurity atoms in the first region; A method for manufacturing a compound semiconductor structure, wherein a concentration of the impurity atoms in the first region decreases from an interface with the second region toward the Si substrate.

9. The step of forming the SiC layer includes: forming a first SiC layer in an atmosphere containing a source gas of SiC and not containing a source gas containing the impurity atoms; 9. The method for manufacturing a compound semiconductor structure according to claim 8, further comprising the step of: forming a second SiC layer adjacent to the first SiC layer in an atmosphere containing a SiC source gas and a source gas containing the impurity atoms while the first SiC layer is heated.

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