Memory reading circuit
By setting capacitors that can be charged and discharged by the storage cell current on the read node and dynamically adjusting the reference voltage and bias current of the comparator, the problem of insufficient reading edge differences during fast reading is solved, and a more robust reading process is achieved.
Patent Information
- Application Number
- JP2024117116
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-07-28
- Filing Date
- 2024-07-22
- Publication Date
- 2025-02-07
AI Technical Summary
While existing semiconductor memory devices quickly read data, it is difficult to ensure that the time position difference of the reading edge is large enough to distinguish between 0 and 1, resulting in the reading process being insolent.
By setting a capacitor that can be charged and discharged by the storage cell current on the read node, combined with the variable comparator reference voltage and bias current, the switching threshold and speed of the comparator are dynamically adjusted to meet the reading requirements of different storage cell currents.
It realizes that while fast reading, the reading window is expanded, and the robustness and noise resistance of the reading process are improved.
Smart Images
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Abstract
Description
[Technical field]
[0001] Exemplary embodiments relate generally to memory read circuits. [Background technology]
[0002] In semiconductor memories, the decision as to whether a memory cell stores a 0 or a 1 is typically made on the basis of a read current provided by the memory cell. For this purpose, the read current is compared to a reference, for example by discharging a precharged capacitance with the read current and the voltage at the capacitance being compared to a reference voltage. In this way, the read current is converted into a digital signal, whose edges have a time position depending on the intensity of the read current. Here, there is a trade-off in that, on the one hand, the time position of the edges when the memory cell stores a 0 must be sufficiently different from the time position of the edges when the memory cell stores a 1 in order to allow a robust read, but, on the other hand, the memory must be able to be read as quickly as possible. A memory read circuit that can meet these two requirements is desirable. Summary of the Invention [Means for solving the problem]
[0003] One embodiment provides a memory reading circuit comprising: a read node having a capacitance that is discharged by a memory cell to read the memory cell by a cell current; a level detector configured to provide a digital output signal and to switch the output signal when the potential of the read node (due to the discharge of the read node) crosses a switching threshold (depending on the selection of the level and downward or upward polarity, i.e., whether the switching threshold is overshot or undershot); and a control circuit configured to set the switching threshold and / or switching speed of the level detector depending on the cell current.
[0004] The figures are not to scale, but rather are intended to illustrate the principles of various exemplary embodiments. Various exemplary embodiments are described in detail below with reference to the following figures: [Brief description of the drawings]
[0005] [Figure 1] It shows memory. [Diagram 2] 2 shows a memory read circuit. [Diagram 3] 4 shows a related time graph for the read process. [Figure 4] 1 shows a schematic diagram of a configuration of a memory read circuit. [Diagram 5] 13 illustrates a time graph for active read window extension according to one embodiment. [Figure 6] 1 illustrates a memory read circuit according to one embodiment. [Figure 7] 2 shows a memory read circuit. [Figure 8] 4 shows a related time graph for the read process. [Figure 9] 1 shows a comparison of a read process with and without active read window extension. [Figure 10] 4 illustrates a memory read circuit according to another embodiment. [Figure 11] 1 illustrates a memory read circuit according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0006] The following detailed description refers to the accompanying drawings which show details and exemplary embodiments. These exemplary embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments are possible, and the exemplary embodiments can be modified in structural, logical and electrical terms without departing from the subject matter of the invention. The various exemplary embodiments are not necessarily mutually exclusive, but rather various embodiments can be combined with each other to produce new embodiments. Within this specification, the terms "coupled," "connected," and "coupled" are used to describe both direct and indirect couplings, direct or indirect connections, and direct or indirect couplings.
[0007] FIG. 1 shows a memory 100 .
[0008] The memory 100 includes a memory array having a plurality of memory cells 102 , each memory cell 102 connected to a respective word line 101 and a respective bit line 103 .
[0009] Data can be stored in and read out from memory cells 102. This kind of memory cells 102 can be realized based on semiconductors of different technologies, for example Flash, RRAM (Resistive Random Access Memory) or MRAM (Magnetic RAM) technologies. All these memory technologies have the common feature that when reading a memory cell 102, a read current (or read current) is typically generated or measured (depending on the fact that a certain voltage is applied to the memory cell 102) through the bit line 103 to which the memory cell 102 to be read is connected. Word lines 101 are used to address the memory cell 102 to be read (in the example of FIG. 1, a row of memory cells 102), i.e. each provides a read current on a respective bit line.
[0010] In this case, there may be at least two states for this read current, e.g., a lower current representing a logic "0" and a higher current representing a logic "1." The purpose of the memory read circuitry (traditionally called a "read amplifier") in this case is to measure the read current and determine whether a logic "0" state or a logic "1" state is present, i.e., whether a 0 or a 1 was last stored in memory cell 102.
[0011] One way to do this is to first convert the read current into time information by converting the current I or flowing charge I x Δt into a voltage ΔU by a capacitance C. According to the capacitor equation, C=ΔQ / ΔU=I×ΔT / ΔU or ΔU=I×Δt / C The voltage value ΔU increases with time Δt. An example of this procedure is shown in FIG.
[0012] FIG. 2 shows a (integration-based) memory read circuit 200 and FIG. 3 shows an associated time graph 300 for the read process.
[0013] A read node 201 of the memory read circuit 200, which is connected to a first input of a comparator 202, is supplied with a voltage level V pre The second transistor 204 (voltage V hold A multiplexer 205, which switches on a holding transistor, in this case an n-channel field effect transistor, for example an n-MOS transistor, controlled by and the desired bit line (i.e. the bit line to which the memory cell to be read is connected), is used to connect the read node 201 to a terminal of the memory cell to be read 206, represented in this case by a resistor. A third (n-channel field effect) transistor 207 is used to connect the other terminal of the memory cell to be read to ground (i.e. the low supply potential).
[0014] Therefore, at time t pre At , a connection between the read node 201 and ground is established via the memory cell 206, i.e., the read phase is started (thus the control signal of the first transistor 203 is set from 0 to 1, and the precharge is terminated). In this way, the read current I cell begins to flow, and the integral capacitance C int 208 is discharged, and the voltage of the read node V sense V pre (The integration capacitance 208 can be thought of as the capacitance of the readout node.) When the readout node 201 reaches the voltage level V ref As soon as the reference voltage source 209 connected to the second input of the comparator 202 is reached, the comparator 202 switches and the digital output DO of the comparator changes from logic 0 to logic 1. We assume that the memory cell is configured such that when it stores a 0 the read current is high (low resistance of the memory cell) and when it stores a 1 the read current is low (high resistance of the memory cell). This results in a fast or slow discharge curve 301 or 302 for these two cases, respectively. Thus, when the memory cell stores a 0 the input of the comparator 202 is early (time t0) and the comparator 202 switches as if the memory cell stored a 1 (time t1).
[0015] Minimum Read Access Time T access Also shown in graph 300 is the discharge current I cell,0 The time t0 is given by T access = Precharge time +I cell,0 Read time at = t pre +C int ×(V pre -V ref ) / I cell,0 +t delay (1)
[0016] Time t delay In this case, the delay of the comparator (i.e., the voltage at the read node 201 is V ref 2. The delay is the delay between the time when the comparator bias current I bias It depends heavily on.
[0017] Furthermore, the read window T window is shown in the graph 300. The read window of the (integral based) read process is defined by t1-t0, and therefore the cell current I cell,0 and the cell current I cell,1 corresponds to the difference between T window =(V pre -V ref )×C int (I cell,0 -I cell,1 ) / (I cell,0 ×I cell,1 )(2)
[0018] The read process, on the one hand, The minimum read access time must be as short as possible so that it can be read as quickly as possible, On the other hand, · The read window must be as large as possible to be robust against read errors and noise.
[0019] Regarding the read access time (see equation (1)), T pre is given by the memory area (bit line capacitance) and technology parameters, I cell,0 is determined by the respective memory technology.
[0020] Therefore, the remaining design parameters for fast read access time are the voltage difference V pre -V ref and Cint (which must be reduced for this) as well as the delay t delay Only.
[0021] With respect to the read window (see equation (2)), I cell,0 and I cell,1 is determined by the respective memory technology.
[0022] Therefore, the remaining design parameters for extending the read window are the voltage difference V pre -V ref and C int (which must be reduced for this).
[0023] This results in a trade-off between readout time and readout window; for a fixed comparator delay, the readout time cannot be shortened without shortening the readout window.
[0024] FIG. 4 shows a schematic diagram of a memory read circuit configuration 400.
[0025] According to the memory read circuit 200, the memory read circuit includes a precharge circuit 401, a bit line preparation and holding circuit 402, a multiplexer 403, (or connected to) a memory cell 404, an integrating capacitance 405, and a comparator 406, which are connected to each other in the manner described in FIG. 2.
[0026] According to various embodiments, in order to extend the read window and keep the read time short, the cell current is used to actively change the comparator reference voltage 407 and the comparator bias current 408. Specifically, in one exemplary embodiment, at large cell currents (i.e., storing a zero), the reference voltage 407 and the bias current 408 are increased, so that the comparator switches faster when a zero is stored. When a one is stored (cell current is small), the reference voltage 407 and the bias current 408 are not increased (but may be decreased). This shortens the read time and extends the read window. This is also referred to below as active read window extension.
[0027] FIG. 5 illustrates a time graph 500 for active read window extension according to one embodiment.
[0028] In contrast to the time graph 300, here the reference voltages for reading 0 and 1 are not the same, but the reference voltage V ref,0 The reference voltage for reading 1 is V ref,1 In addition, the bias current for reading a 0 is larger than the bias current for reading a 1, and therefore the comparator delay for reading a 0, t delay,0 is the comparator delay t delay,1 This reduces the (minimum) readout time and extends the readout window.
[0029] Thus, the formula takes the place of forms (1) and (2). T access =t pre +C int ×(V pre -V ref,0 ) / I cell,0 +t delay,0 (3) or T window =(V pre -V ref,1 )×C int / Icell,1 -(V pre -V ref,0 )×C int / I cell,0 +t delay,1 -t delay,0 (4)
[0030] In the following text, V ref and I bias We now describe a memory read circuit in which V is variable and depends on the cell current as described above, i.e., V varies depending on the cell current. ref and I bias According to various embodiments, a control circuit is provided that sets V ref and I bias is the charge (or discharge) current I cap =I cell (See Figure 2) cap is tapped (or measured) by the corresponding circuit and V ref and I bias is set or changed.
[0031] FIG. 6 illustrates a memory read circuit 600 according to one embodiment.
[0032] Memory read circuit 600 is an example of a circuit in which the cell current is measured in an integrating capacitance (based on the discharge current of the integrating capacitance during the read phase) and the comparator bias current and / or reference voltage (in the case of circuit 600, both) are variably set based on this.
[0033] Similar to the memory read circuit 200 of FIG. 2, the memory read circuit 600 includes a first transistor 603 (precharge transistor) and a second transistor 604 (hold transistor) connected via a read node 601, a comparator 602, and an integrating capacitor 608 connected by its first terminal to the read node 601 and by its second terminal to ground via a third (n-channel field effect) transistor 605, which is connected to a constant bias current source I b This second terminal of the integrating capacitance is further connected to the drain of a fourth (p-channel field effect) transistor 606.
[0034] The fourth transistor 606, together with the fifth (p-channel field effect) transistor 607, supplies a reference current I ref and together with a sixth (p-channel field effect) transistor 609 forms a first current mirror providing a bias current I bias to the comparator 602. The fourth transistor 606 is thus used as a current measuring element and measures the current I bias and I ref Control.
[0035] Reference voltage V ref is the reference current I ref is given by the voltage dropped across resistor 610 which causes a
[0036] After the precharge phase, the cell current I cell When current I flows, the integral capacitance cell This is because the cell current and V ref (That is, the reference current I ref and the value of resistor 610) is measured and I biasis set via two current mirrors depending on this cell current. Thus, the switching threshold and switching speed of the comparator 602 (used as a level detector) depend on the cell current.
[0037] Therefore, as described with reference to FIGS. 4 and 5, in the memory read circuit 600, V ref and I bias depends on the cell current.
[0038] The control circuitry that implements this dependency includes, among other things, two current mirrors and a resistor 610 .
[0039] FIG. 7 shows a memory read circuit 700 according to a further embodiment, and FIG. 8 shows an associated time graph 800 for the read process.
[0040] Similar to the memory read circuit 200 of FIG. 2, the memory read circuit 700 includes a first transistor 703 (precharge transistor) and a second transistor 704 (hold transistor) connected via a read node 701, a comparator (in this case in the form of a seventh (n-channel field effect) transistor 712, see below), and an integrating capacitor 708 connected by a first terminal to the read node 701 (the multiplexer and memory cell are omitted here for simplicity).
[0041] Furthermore, the second terminal of the integration capacitance is connected to the drain of a fourth (p-channel field effect) transistor 706 .
[0042] The fourth transistor 706, together with the fifth (p-channel field effect) transistor 707, provides a bias current I bias to the input node 709 of the inverter 702. The fourth transistor 706 is thus used as a current measuring element and measures the current I bias Control.
[0043] The second terminal of the integrating capacitor 708 is further connected to the drain of a sixth (n-channel field effect) transistor 710, the source of which is connected to ground (ie, the low supply potential).
[0044] The sixth transistor 710 has a bias voltage v bias as the input voltage, which results in a precharge phase, i.e., I cell When is equal to 0, the current mirror still operates at a specific bias current I b This reflects the bias current I bias I b is equal to.
[0045] During the precharge phase, i.e. when PRE is active (corresponding to a low level of PRE in this example), the precharge voltage V pre is connected to the read node 701 via a first transistor 703, and the second terminal of the integrating capacitor 708 is connected to ground via a second transistor 704, thereby charging the integrating capacitor 708 as in the above example.
[0046] In addition, PRE is active (so
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[0047] The read phase (now PRE is high, i.e.
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[0048] The voltage at the read node (cell current I cell When the seventh transistor 712 is turned off (after a time that depends on the level of I), the voltage at the input node DOa of the inverter 702 rises, the inverter 702 switches, and the output signal DO of the inverter 702 goes high. biasbecomes larger, on the one hand, the node DOa is charged faster, and on the other hand, the switching threshold is changed to VthN1+Vov, from which the node DOa starts to increase.
[0049] The circuit 700 achieves a situation in which possible variations in the threshold voltage VthN1 of the seventh transistor 712 are compensated for.
[0050] In addition, similar to the circuit 600 of Fig. 6, the switching threshold and switching speed of the level detector (which in this case has as its central component the seventh transistor 712) depends on the cell current. A control circuit that realizes this dependence includes, inter alia, a current mirror.
[0051] Since the integral capacitor 708 is connected to VDD when discharging, this adversely affects the reading of noise in the power supply voltage. To avoid this, a precharge voltage V (instead of VDD) is applied to the sources of the fourth and fifth transistors. pre (which may be stabilized, for example, by a preconditioning process).
[0052] 9 shows a comparison between a read process with active read window extension (top graph 901) as in the circuits of FIGS. 6 and 7 and a read process without active read window extension (bottom graph 902) as in the circuit of FIG. 2. With active read window extension, the read window T window can be extended by about 25%, and the time required to read zero can be significantly reduced. As a result, higher robustness against process variations can be achieved using active read window extension.
[0053] In the above example of a circuit with active read window extension, the cell current is determined by measuring the discharge current of the read capacitance. It is also possible to split the read capacitance and measure the discharge current only at one of the two partial capacitances. An example of this is shown in Figure 10.
[0054] FIG. 10 shows a memory read circuit 1000 according to another embodiment.
[0055] In this example, there are two integrating capacitors 1001, 1002, and the discharge current of the second integrating capacitor 1002 is measured and based on this the bias current and reference voltage of the comparator 1003 are set. Otherwise the functionality is the same as the circuit of FIG.
[0056] In summary, according to various embodiments, a memory read circuit is provided as shown in FIG.
[0057] FIG. 11 illustrates a memory read circuit 1100 according to one embodiment.
[0058] The memory read circuit 1100 includes a read node 1101 having a capacitance that is discharged by a memory cell 1104 to read the memory cell 1104 by a cell current.
[0059] Furthermore, the memory read circuit 1100 includes a level detector 1102 configured to provide a digital output signal and to switch the output signal when the potential of the read node (due to discharging of the read node) crosses the switching threshold (depending on the selection of the level and downward or upward polarity, i.e., whether the switching threshold is overshot or undershot), and a control circuit configured to set the switching threshold and / or switching speed of the level detector depending on the cell current.
[0060] According to various embodiments, for example, the reference voltage (and therefore the switching threshold) and bias current (and therefore the switching speed) of the comparator are actively modified to widen the read window and shorten the access time, for example by measuring the current flowing through the integration capacitance during the read phase and setting the reference voltage and bias current of the comparator (or, in general, the switching threshold and switching speed of the level detector) accordingly.
[0061] According to one embodiment, a memory is provided comprising a plurality of memory cells and at least one memory read circuit according to one of the embodiments specified in this specification, wherein the memory cell to be read is one of the plurality of memory cells.
[0062] Various exemplary embodiments are described below.
[0063] Exemplary embodiment 1 is the memory read circuit described with reference to FIG.
[0064] Exemplary embodiment 2 is a memory read circuit according to exemplary embodiment 1, in which the control circuit is configured to set a higher switching speed as the cell current is larger.
[0065] Exemplary embodiment 3 is a memory read circuit according to exemplary embodiment 1 or 2, in which the crossing is an undershoot, and the control circuit is configured to set a higher switching speed for a larger cell current.
[0066] Exemplary embodiment 4 is a memory read circuit according to exemplary embodiment 1 or 2, wherein the crossing is an overshoot, and the control circuit is configured to set the switching speed lower for larger cell currents.
[0067] Exemplary embodiment 5 is a memory reading circuit according to any one of exemplary embodiments 1 to 4, wherein the control circuit is configured to set the switching speed of the level detector by setting a bias current of the level detector.
[0068] Exemplary embodiment 6 is a memory read circuit according to any one of exemplary embodiments 1 to 5, in which the level detector is a comparator.
[0069] Exemplary embodiment 7 is a memory read circuit according to exemplary embodiment 6, in which the control circuit is configured to set a switching threshold by setting a reference voltage that the comparator compares with the potential of the read node.
[0070] Exemplary embodiment 8 is a memory read circuit according to any one of exemplary embodiments 1 to 6, in which the level detector has an inverter, and an input node potential of the inverter is switched according to the potential of the read node.
[0071] Exemplary embodiment 9 is a memory reading circuit according to any one of exemplary embodiments 1 to 8, wherein the control circuit is configured to measure a discharge current of the capacitance discharge and set a switching threshold and / or a switching speed according to the measured discharge current.
[0072] Exemplary embodiment 10 is a memory read circuit according to any one of exemplary embodiments 1 to 9, wherein the control circuit has at least one current mirror configured to mirror a discharge current of the capacitance discharge, and the control circuit is configured to provide the mirrored current to the level detector as a bias current and / or provide a voltage drop of the mirrored current in a resistor to the level detector as a switching threshold.
[0073] An eleventh exemplary embodiment is a memory comprising a plurality of memory cells and at least one memory read circuit according to any one of the first to tenth exemplary embodiments.
[0074] Although the present invention has been illustrated and described primarily with reference to specific embodiments, it should be understood by those skilled in the art that many modifications may be made in its configuration and details without departing from the spirit and scope of the invention as defined by the following claims. The scope of the present invention is therefore determined by the appended claims, and it is the intention to embrace all modifications that come within the literal meaning or equivalent range of the claims. [Explanation of symbols]
[0075] 100 Memory 101 Word Line 102 memory cells 103 bit lines 200 Memory read circuit 201 Read Node 202 Comparator 203,204 Transistors 205 Multiplexer 206 Memory Cells 207 Transistor 208 Integral capacity 209 Reference Voltage Source 210 Bias Current Source 300 Time graph of the read process 301,302 discharge curve 401 Precharge Circuit 402 Bit Line Preparation and Retention Circuit 403 Multiplexer 404 memory cells 405 Integral capacity 406 Comparator 407 Reference Voltage 408 Bias Current 500 Time graph of the read process with active read window extension 600 Memory Readout Circuit 601 Read Node 602 Comparator 603-607 Transistor 608 Integral capacity 609 Transistor 610 Resistance 700 Memory Readout Circuit 701 Read Node 702 Inverter 703-707 Transistor 708 Integral capacity 709 Inverter Input Node 710 Transistor 711 Compensation capacity 712 Transistor 800 Read process time graph 901 Time graph of the read process with active read window extension 902 Time graph of the read process without active read window extension 1000 Memory Readout Circuit 1001,1002 integral capacity 1003 Comparator 1100 Memory read circuit 1101 Read Node 1102 Level detector 1103 Control circuit 1104 Memory Cell
Claims
1. a read node having a capacitance that is discharged by the memory cell to read the memory cell with a cell current; a level detector providing a digital output signal and configured to switch said output signal when the potential of said read node crosses a switching threshold; a control circuit configured to set the switching threshold and / or switching speed of the level detector in response to the cell current; A memory read circuit comprising:
2. The control circuit is configured to set the switching speed higher as the cell current increases.
2. The memory read circuit of claim 1.
3. the crossing is an undershoot, and the control circuit is configured to set the switching speed higher the larger the cell current is.
3. The memory read circuit according to claim 1 or 2.
4. the crossing is an overshoot, and the control circuit is configured to set the switching speed lower the greater the cell current.
3. The memory read circuit according to claim 1 or 2.
5. the control circuit is configured to set the switching speed of the level detector by setting a bias current of the level detector.
5. A memory read circuit as claimed in claim 1.
6. The level detector is a comparator.
6. A memory read circuit as claimed in claim 1.
7. the control circuit is configured to set the switching threshold by setting a reference voltage which the comparator compares with the potential of the read node; 7. The memory read circuit according to claim 6.
8. the level detector has an inverter, and an input node potential of the inverter is switched in response to the potential of the read node; 7. A memory read circuit as claimed in claim 1.
9. the control circuit is configured to measure a discharge current of the discharge of the capacitance and to set the switching threshold and / or the switching speed in response to the measured discharge current. A memory read circuit as claimed in any one of claims 1 to 8.
10. the control circuit has at least one current mirror configured to mirror a discharge current of the discharge of the capacitance, the control circuit being configured to provide the mirrored current to the level detector as a bias current and / or to provide a voltage drop of the mirrored current across a resistor to the level detector as the switching threshold. A memory read circuit as claimed in any one of claims 1 to 9.
11. A memory comprising a plurality of memory cells and at least one memory read circuit according to any one of claims 1 to 10.