Filter design method and IIR-type all-pass filter

Abstract

To provide a filter design method and an IIR-type all-pass filter, capable of reducing the number of components.SOLUTION: There is provided a filter design method in which a computer designs an IIR-type all-pass filter 100, and, with respect to an order N defined by the number N of signal processors 110-N, a group delay count M of the filter has a relation M=N-3. In the method, the computer is configured to: receive input of the order N and a bandwidth B of the filter; using the bandwidth B, perform setting so that a lower limit frequency fl and an upper limit frequency fh are symmetrical; and perform calculation so that a π / 2 phase shift characteristic is realized by filter coefficients ai (i=0 to N) including N filter coefficients aN to be multiplied by outputs of the N signal processors and a filter coefficient to be multiplied by an output of a delay device of the N-th signal processor from an input terminal.SELECTED DRAWING: Figure 7

Description

[Technical field]

[0001] The present disclosure relates to a filter design method and an IIR type all-pass filter. [Background technology]

[0002] Conventionally, there has been a medium on which a program has been recorded for designing an IIR digital filter, which is configured by connecting a delay device and a phase equalizer in parallel, on a computer in accordance with the Remez algorithm using a given filter order, passband edge frequency, stopband edge frequency, and weighting function, the design program being characterized in that, when an empirical function is given that represents the relationship between a ratio x of a phase slope that approximates a predetermined phase difference for the delay device to a phase slope in the transient band of the filter, and a stopband attenuation y of the filter, the design program inputs a passband amplitude error, a stopband attenuation, the passband edge frequency, and the stopband edge frequency as parameters that represent the transfer characteristics of the filter, calculates the weighting function and the filter order based on each of the parameters and the empirical function, and performs filter design using the weighting function and the filter order (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-187662 Summary of the Invention [Problem to be solved by the invention]

[0004] However, conventional IIR digital filter design programs do not allow for a reduction in the number of components.

[0005] It is therefore an object of the present invention to provide a filter design method that allows for a reduction in the number of components, and an IIR type all-pass filter. [Means for solving the problem]

[0006] A filter design method according to an embodiment of the present disclosure is a filter design method in which a computer designs an IIR type all-pass filter including N (N is an integer equal to or greater than 4) signal processing units connected between an input terminal and an output terminal, in which an order N defined by the number N of the signal processing units has a group delay number M of the IIR type all-pass filter having a relationship of M=N-3, and the computer receives an input of the order N and a bandwidth B of the IIR type all-pass filter, sets a lower limit frequency fl and an upper limit frequency fh to be symmetrical using the bandwidth B, and determines N filter coefficients a1 to aN by which outputs of the N signal processing units are multiplied, and a delay unit of the Nth signal processing unit from the input terminal is multiplied. and calculating filter coefficients ai (i=0 to N) including a filter coefficient a0 so as to realize a π / 2 phase-shift characteristic, the process including: calculating the filter coefficients ai by a Remez algorithm until a change in frequency at which the amplitude value of a complex amplitude error shows an extreme value converges to a predetermined value or less; extracting a maximum value of the filter coefficients ai and an index i (referred to as imax) of the filter coefficient ai that gives the maximum value; and setting the filter coefficients ai whose index i is an even number to zero when the order N is an odd number and the index imax is 1, and setting the filter coefficients ai whose index i is an odd number to zero when the order N is an even number and the index imax is 0. Effect of the Invention

[0007] It is possible to provide a filter design method that allows for a reduction in the number of components, and an IIR type all-pass filter. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 illustrates a receiving device according to an embodiment. [Figure 2A] FIG. 2 is a diagram illustrating an example of the configuration of an IIR type all-pass filter according to an embodiment. [Figure 2B]FIG. 13 is a diagram illustrating an example of another configuration of the IIR type all-pass filter according to the embodiment. [Diagram 3] FIG. 1 is a diagram illustrating an example of a frequency characteristic of the accumulated phase of an IIR type all-pass filter. [Figure 4] 11 is a diagram illustrating an example of frequency characteristics of the phase difference between an I signal and a Q signal and the amplitude of a Q signal. FIG. [Diagram 5] FIG. 13 is a diagram illustrating an example of a frequency characteristic of a phase error of a Q signal. [Figure 6] 1 is a diagram illustrating an example of a relationship between a combination of an order N and a group delay number M and a lower limit frequency fl, an upper limit frequency fh, a design bandwidth B, a phase error, and a filter coefficient. [Figure 7] FIG. 1 is a diagram showing an IIR type all-pass filter with a reduced circuit configuration. [Figure 8] FIG. 1 is a diagram showing an IIR type all-pass filter with a reduced circuit configuration. [Figure 9] FIG. 1 is a diagram showing an IIR type all-pass filter with a reduced circuit configuration. [Figure 10] FIG. 1 is a diagram illustrating an example of frequency characteristics of an IIR type all-pass filter in which the order N is 9 and M=N−2. [Figure 11] FIG. 1 is a diagram illustrating an example of the frequency characteristics of an IIR type all-pass filter in which the order N is 9 and M=N−1. [Figure 12] FIG. 2 is a diagram illustrating an example of the configuration of an IIR type all-pass filter (N=10) according to an embodiment. [Figure 13] 1 is a diagram illustrating an example of a relationship between a combination of an order N and a group delay number M and a lower limit frequency fl, an upper limit frequency fh, a design bandwidth B, a phase error, and a filter coefficient. [Figure 14] FIG. 1 is a diagram illustrating an example of the frequency characteristics of an IIR type all-pass filter in which the order N is 10 and M=N−3. [Figure 15] FIG. 1 is a diagram illustrating an example of the frequency characteristics of an IIR type all-pass filter in which the order N is 10 and M=N−2. [Figure 16] FIG. 1 is a diagram illustrating an example of the frequency characteristics of an IIR type all-pass filter in which the order N is 10 and M=N−1. [Figure 17]FIG. 1 illustrates a computer system. [Figure 18] 2 is a block diagram illustrating a configuration of a main part in a main body of a computer system. [Figure 19] FIG. 2 is a diagram illustrating functional blocks of a filter design apparatus. [Figure 20] 1 is a flowchart showing a process executed by a filter design device. [Figure 21] 1 is a flowchart showing a process executed by a filter design device. [Figure 22] 1 is a flowchart showing a process executed by a filter design device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, a filter design method according to the present disclosure and an embodiment to which an IIR type all-pass filter is applied will be described.

[0010] <Embodiment> 1 is a diagram showing a receiving device 50 according to an embodiment. The receiving device 50 includes a digital orthogonal signal detection circuit 1, an orthogonal frequency division multiplexing detection circuit (OFDM detection circuit) 2, a detection signal output terminal 3, an analog / digital converter (A / D) 4, a receiving circuit 5, and a receiving antenna 6.

[0011] The digital orthogonal signal detection circuit 1 has an IIR type all-pass filter 100, which is an infinite impulse response digital filter (IIR), and a digital signal delay circuit (DL) 8. The orthogonal frequency division multiplexing detection circuit 2 has a fast Fourier transform (FFT) circuit 9 and an orthogonal frequency division multiplexing demodulation circuit (DEM) 10. The IIR type all-pass filter 100 shifts the phase of an input digital signal by 90°, and the digital signal delay circuit 8 gives the input digital signal a signal delay equal to the signal group delay amount of the IIR type all-pass filter 100. The phase shift refers to shifting the phase of a signal.

[0012] The receiving circuit 5 has an input terminal connected to the receiving antenna 6, and an output terminal connected to the input terminal of the analog / digital converter 4. In the digital orthogonal signal detection circuit 1, the IIR type all-pass filter 100 has an input terminal directly connected to the output terminal of the analog / digital converter 4, and an output terminal connected to a first input terminal of the fast Fourier transform circuit 9. The digital signal delay circuit (DL) 8 has an input terminal directly connected to the output terminal of the analog / digital converter 4, and an output terminal connected to a second input terminal of the fast Fourier transform circuit 9. In the orthogonal frequency division multiplexing detection circuit 2, the orthogonal frequency division multiplexing demodulation circuit 10 has an input terminal connected to the output terminal of the fast Fourier transform circuit 9, and an output terminal connected to the detection signal output terminal 3.

[0013] When a digital signal is received at the receiving antenna 6, the digital signal is supplied to the receiving circuit 5 as a received signal. The receiving circuit 5 amplifies the received signal, then frequency-mixes the amplified received signal with a local oscillation signal to form a frequency-mixed signal, extracts an intermediate frequency (IF) signal from the frequency-mixed signal, and outputs the obtained intermediate frequency signal to the analog / digital converter 4. The analog / digital converter 4 analog / digital converts the input intermediate frequency signal, and outputs digital signals (sampling frequency fs) from the output terminals, which are supplied to the digital quadrature signal detection circuit 1.

[0014] In the digital orthogonal signal detection circuit 1, the IIR all-pass filter 100 shifts the phase of the supplied digital signal by 90° to generate a Q signal, and outputs the Q signal to the orthogonal frequency division multiplexing detection circuit 2. The digital signal delay circuit 8 generates an I signal by delaying the input digital signal by an amount of signal delay equal to the amount of signal group delay given to the digital signal that is phase-shifted by 90° on the IIR all-pass filter 100 side, and outputs the I signal to the orthogonal frequency division multiplexing detection circuit 2.

[0015] In the quadrature frequency division multiplexing detection circuit 2, the fast Fourier transform circuit 9 performs fast Fourier transform processing using the I signal and the Q signal, and supplies the Fourier transform processing signal to the quadrature frequency division multiplexing demodulation circuit 10. The quadrature frequency division multiplexing demodulation circuit 10 performs demodulation processing for digital modulation such as quadrature phase shift keying (QPSK) on the supplied Fourier transform processing signal, and supplies the obtained demodulation signal to the detection signal output terminal 3.

[0016] <Configuration of IIR type all-pass filter 100> FIG. 2A is a diagram showing an example of the configuration of the IIR type all-pass filter 100 according to the embodiment. The IIR type all-pass filter 100 includes an input terminal 101, an output terminal 102, N signal processing units 110, an amplifier 120, N adders 130, and an amplifier 140. N is an integer of 4 or more, and FIG. 2A shows nine signal processing units 110-1 to 110-9 and nine adders 130-0 to 130-8 in the case of N = 9 as an example. Hereinafter, the N signal processing units 110 may be referred to as signal processing units 110-1 to 110-N.

[0017] The integer N represents the number of signal processing units 110 and represents the order N of the IIR type all-pass filter 100. The order N is defined by the number of signal processing units 110. When the signal processing units 110-1 to 110-N are not particularly distinguished, they are simply referred to as signal processing units 110. In FIG. 2A, the configuration of the IIR type all-pass filter 100 with N = 9 will be described.

[0018] The signal processing units 110-1 to 110-9 are provided between the input terminal 101 and the output terminal 102. Since the configurations of the signal processing units 110-1 to 110-9 are the same, in FIG. 2A, the delay elements 111, 112, adder 113, and amplifier 114 included in the signal processing unit 110-1 are labeled, and the same applies to the signal processing units 110-2 to 110-9.

[0019] An input terminal of delay unit 111 of signal processing unit 110-9 and one input terminal of adder 113 are connected to input terminal 101. Input terminals of delay unit 111 of signal processing units 110-1 to 110-8 are connected to one input terminal of adder 113 of each signal processing unit 110 and to an output terminal of delay unit 111 of the adjacent (left) signal processing unit 110 whose order is one step higher. An output terminal of delay unit 111 of signal processing unit 110-1 is connected to an input terminal of amplifier 120.

[0020] The input terminal of the delay unit 112 of the signal processing unit 110-1 is connected to the output terminal 102 and the output terminal of the amplifier 140. The input terminal of the delay unit 112 of the signal processing units 110-2 to 110-9 is connected to the output terminal of the delay unit 112 of the adjacent (right adjacent) signal processing unit 110 having a smaller order by one. The output terminal of the delay unit 112 of the signal processing units 110-1 to 110-8 is connected to the other input terminal of the adder 113 of each signal processing unit 110 and the input terminal of the delay unit 112 of the adjacent (left adjacent) signal processing unit 110 having a larger order by one. The output terminal of the delay unit 112 of the signal processing unit 110-9 is connected to the other input terminal of the adder 113 of the signal processing unit 110-9. In each signal processing unit 110, the output terminal of the adder 113 is connected to the input terminal of the amplifier 114. Adder 113 subtracts a signal input to one upper input terminal (lower input terminal) from a signal input to the other upper input terminal (upper input terminal), and outputs the difference.

[0021] The output terminal of the amplifier 114 of the signal processing unit 110-1 and the output terminal of the adder 130-2 are respectively connected to the two input terminals of the adder 130-1. The connection relationship is similar to the connection relationship in which the output terminals of the amplifiers 114 of the signal processing units 110-2 to 110-7 and the output terminals of the adders 130-3 to 130-8 are respectively connected to the two input terminals of the adder 130-2 to 130-7. The output terminal of the amplifier 114 of the signal processing unit 110-8 and the output terminal of the amplifier 114 of the signal processing unit 110-9 are respectively connected to the two input terminals of the adder 130-8. In addition, the output terminal of the amplifier 120 and the output terminal of the adder 130-1 are respectively connected to the two input terminals of the adder 130-0. The output terminal of the adder 130-0 is connected to the input terminal of the amplifier 140. Adders 130-0 to 130-8 each add up signals input to two input terminals and output the sum.

[0022] The amplifier 140 is provided to correct the filter output when a filter coefficient a0 described later is neither 0 (zero) nor 1. The amplification factor of the amplifier 140 is 1 / a0. The output terminal of the amplifier 140 is connected to the output terminal 102.

[0023] 2A, the amplification factors of amplifier 120 and 10 amplifiers 114 of signal processing units 110-1 to 110-9 are designated as filter coefficients a0 to a9. In the following, the filter coefficient in N-th order IIR type all-pass filter 100 is designated as ai. The index i of filter coefficient ai ranges from 0 to N (i=0 to N).

[0024] FIG. 2B is a diagram showing an example of another configuration of the IIR type all-pass filter 100 according to the embodiment. The IIR type all-pass filter 100 shown in FIG. 2B has a configuration in which the signal processing unit 110-1 and the adder 130-1 of the IIR type all-pass filter 100 shown in FIG. 2A are deleted, the amplification factor of the amplifier 120 is changed to a1, and further the amplification factor of the amplifier 140 is changed to 1 / a1. The IIR type all-pass filter 100 shown in FIG. 2B deletes the signal processing unit 110-1 and the adder 130-1 related to the filter coefficient a0 from the IIR type all-pass filter 100 shown in FIG. 2A, changes the amplification factor of the amplifier 120 to a1, and further changes the amplification factor of the amplifier 140 to 1 / a1 in order to avoid the amplification factor (1 / a0) of the amplifier 140 diverging to infinity when the filter coefficient a0 in the IIR type all-pass filter 100 shown in FIG. 2A is zero.

[0025] Here, if any one of the filter coefficients a1 to a9 in FIG. 2A can be set to zero, the amplifiers 114 and the adders 113 of the signal processing units 110-1 to 110-9 can be reduced, and miniaturization and power consumption reduction of the IIR type all-pass filter 100 can be realized. Similarly, if any one of the filter coefficients a2 to a9 in FIG. 2B can be set to zero, the amplifiers 114 and the adders 113 of the signal processing units 110-2 to 110-9 can be reduced, and miniaturization and power consumption reduction of the IIR type all-pass filter 100 can be realized.

[0026] <Frequency characteristics of the IIR type all-pass filter 100 (M = N - 3)> FIG. 3 is a diagram showing an example of the frequency characteristics of the cumulative phase of the IIR type all-pass filter 100. In FIG. 3, the horizontal axis represents frequency, and the vertical axis represents cumulative phase. The frequency on the horizontal axis is the frequency normalized by the Nyquist frequency which is 1 / 2 of the sampling frequency, and has no unit. The cumulative phase on the vertical axis represents the number of 1 / π radians (rad). The fact that the value on the vertical axis is -6 means that the phase is shifted by -6π in the direction of lagging with respect to 0. In FIG. 3, the I signal is shown by a broken line, and the Q signal is shown by a solid line.

[0027] The I signal output from the digital signal delay circuit 8 (see Fig. 1) has a characteristic of -6π phase shift while the frequency changes from 0 to 1. The Q signal has a phase that is 90 degrees delayed from the I signal in the frequency band of 0.1 to 0.9, and has a characteristic (π / 2 phase shift characteristic) that changes linearly with the increase in frequency. Hereinafter, the number of group delays (group delay number) M is defined by the slope of the frequency characteristic of the cumulative phase shown in Fig. 3, and is given by the value obtained by dividing the change amount of the cumulative phase by the frequency width and inverting the sign. In the I signal, since the cumulative phase changes linearly by -6 while the frequency changes from 0 to 1, the group delay number is 6. Also, in the Q signal, since the cumulative phase changes linearly by -4.8 (-1.2 to -6) while the frequency changes from 0.1 to 0.9, the group delay number becomes 6 simultaneously with the I signal. The IIR type all-pass filter 100 having the frequency characteristic shown in Fig. 3 has a degree N of 9 and a group delay number M of 6 (M = 6). That is, the IIR type all-pass filter 100 having the frequency characteristic shown in Fig. 3 is an IIR type all-pass filter with M = N - 3. Also, when designing the IIR type all-pass filter 100, the width of the frequency band in which the Q signal changes linearly with respect to the change in frequency is referred to as the design bandwidth, the lower limit of the design band is referred to as the lower frequency, and the upper limit of the design band is referred to as the upper frequency.

[0028] <Frequency Characteristics of Phase Difference between I Signal and Q Signal and Amplitude of Q Signal> Fig. 4 is a diagram showing an example of the frequency characteristics of the phase difference between the I signal and the Q signal and the amplitude of the Q signal. In Fig. 4, the horizontal axis represents the normalized frequency, the left vertical axis represents the phase difference between the I signal and the Q signal in terms of the number of 1 / π radians (rad), and the right vertical axis represents the amplitude of the Q signal. In Fig. 4, the phase difference between the I signal and the Q signal is shown by a solid line, and the amplitude of the Q signal is shown by a dashed line.

[0029] As shown in Fig. 4, in the frequency band of 0.1 to 0.9, the phase difference between the I signal and the Q signal is approximately 0.5 (π / 2 = 90 degrees), and the amplitude of the Q signal is 1.

[0030] Fig. 5 is a diagram showing an example of the frequency characteristic of the phase error of the Q signal. In Fig. 5, the horizontal axis represents the normalized frequency, and the vertical axis represents the phase error of the Q signal in degrees. The phase error of the Q signal is the error relative to -90 degrees. As shown in Fig. 5, the phase error of the Q signal with respect to the change in frequency is ±0.64 degrees, and it was confirmed that an equiripple characteristic with equal upper and lower swings was obtained. As an example, a guide for whether the phase error is a good value is an absolute value of less than 1 degree.

[0031] <Combination of order N and group delay number M> 6 is a table showing an example of the relationship between the combination of the order N and the group delay number M and the lower limit frequency fl, the upper limit frequency fh, the design bandwidth B, the phase error, and the filter coefficients a0 to a9. Here, normalization is performed using the Nyquist frequency which is 1 / 2 the sampling frequency, and the lower limit frequency fl and the upper limit frequency fh are set to be symmetrical with respect to 1 / 2 the Nyquist frequency, so that the lower limit frequency fl and the upper limit frequency fh have a relationship of fl+fh=1.

[0032] The table in FIG. 6 shows the calculation results of the phase error and filter coefficients a0 to a9 obtained when the lower limit frequency fl is set to 0.1, the upper limit frequency fh is set to 0.9, and the design bandwidth B is set to 0.8 for four combinations of order N and group delay number M, namely, M=N-3=6, M=N-2=7, M=N-1=8, and M=N=9, where N=9. Here, all the filter coefficients a0 to a9 are shown normalized so that the maximum value among the filter coefficients a0 to a9 is 1. The filter coefficients ai may take negative values. Here, the maximum value of the filter coefficients a0 to a9 is set to 1. The phase error is shown as an absolute value.

[0033] When M=N-3=6, the phase error was a good value of 0.64 degrees, and among the filter coefficients a0 to a9, the filter coefficients ai with index i being even numbers were zero. Specifically, the filter coefficients a0, a2, a4, a6, and a8 were zero. Here, the filter coefficients ai shown in FIG. 6 have significant figures up to three decimal places, and are values ​​rounded off to the fourth decimal place. These values ​​are values ​​obtained by processing described later with reference to FIG. 20.

[0034] Furthermore, when M=N-2=7, the phase error is a good value of 0.64 degrees, and among the filter coefficients a0 to a9, the filter coefficients ai with index i starting from 0, two each, are the same value. Specifically, the filter coefficients a0 and a1 are both 1, the filter coefficients a2 and a3 are both -0.486, the filter coefficients a4 and a5 are both -0.104, the filter coefficients a6 and a7 are both -0.039, and the filter coefficients a8 and a9 are both -0.019. The reason why the filter coefficients ai with index i starting from 0, two each, are the same value is because the filter coefficients ai with index i starting from 0, two each, are set to the average value of two filter coefficients ai. These values ​​are values ​​obtained by processing described later with reference to FIG. 21.

[0035] Furthermore, when M=N-1=8, the phase error was a good value of 0.64 degrees, and among the filter coefficients a0 to a9, the filter coefficients ai with odd indexes i were zero. Specifically, the filter coefficients a1, a3, a5, a7, and a9 were zero. Here, the filter coefficients ai shown in FIG. 6 have significant figures up to three decimal places, and are values ​​rounded off to the fourth decimal place. These values ​​are values ​​obtained by processing described later with reference to FIG. 22.

[0036] Furthermore, when M=N=9, the phase error was 8.40 degrees, which is not a good value. Therefore, when N=9, the combinations of order N and group delay number M of M=N-3, M=N-2, and M=N-1 have good phase errors and can be used as an IIR type all-pass filter 100, but the combination of order N and group delay number M of M=N cannot be used. How to obtain the filter coefficients when M=N=9 will be described at the end of the explanation of FIG. 21.

[0037] Furthermore, for a combination of order N and group delay number M where M=N-3, the filter coefficients ai with index i of even numbers among filter coefficients a0 to a9 become zero. Therefore, it was found that it is possible to reduce approximately half (four) of the total of nine amplifiers, including amplifiers 114 and 120 in signal processing units 110-2 to 110-9 shown in FIG. 2B, as well as their surrounding components.

[0038] Similarly, for a combination of order N and group delay number M where M=N-1, the filter coefficients ai with odd index i among filter coefficients a0 to a9 become zero, so it was found that it is possible to reduce half (five) of the total of ten amplifiers, including amplifiers 114 and 120 in signal processing units 110-1 to 110-9 shown in FIG. 2A, and their surrounding components.

[0039] In addition, for a combination of order N and group delay number M of M=N-2, it was found that by combining two amplifiers corresponding to filter coefficients ai with index i of 0 to 2 into one (one common amplifier), it is possible to reduce half (five) of the total of ten amplifiers including amplifiers 114 and 120 of signal processing units 110-1 to 110-9 shown in Fig. 2A and their peripheral components. More specifically, it was found that the number of amplifiers can be reduced by combining amplifier 120 and amplifier 114 of signal processing unit 110-1 into one common amplifier, amplifiers 114 of signal processing units 110-2 and 110-3 into one common amplifier, amplifiers 114 of signal processing units 110-4 and 110-5 into one common amplifier, amplifiers 114 of signal processing units 110-6 and 110-7 into one common amplifier, and amplifiers 114 of signal processing units 110-8 and 110-9 into one common amplifier. Moreover, by reducing the number of amplifiers, the number of components before and after the amplifiers can also be reduced, as shown in Figs.

[0040] <IIR type all-pass filter 100 (M=N-3) with reduced circuit configuration> FIG. 7 is a diagram showing an IIR type all-pass filter 100 with a reduced circuit configuration. FIG. 7 shows the configuration of the IIR type all-pass filter 100 with M=N-3. In the case of N=9 and M=N-3=6, the filter coefficient a0 becomes zero, so that the filter coefficients a2, a4, a6, and a8 become zero by using the IIR type all-pass filter 100 shown in FIG. 2B. Therefore, the amplifiers 114 (a2, a4, a6, and a8) of the signal processing units 110-2, 110-4, 110-6, and 110-8 can be eliminated along with their paths. In addition, by eliminating the amplifiers 114 (a2, a4, a6, and a8) of the signal processing units 110-2, 110-4, 110-6, and 110-8 along with their paths, the adders 113 of the signal processing units 110-2, 110-4, 110-6, and 110-8 can be eliminated along with their paths.

[0041] Moreover, by deleting the amplifiers 114 (a2, a4, a6, a8) of the signal processing units 110-2, 110-4, 110-6, and 110-8, it is possible to delete the adders 130-2, 130-4, 130-6, and 130-8. Moreover, since the filter coefficient a1 of the amplifier 120 is 1 (a1=1), it is sufficient to delete the amplifier 120 and connect the output terminal of the delay unit 111 of the signal processing unit 110-2 to one input terminal of the adder 130-0. Furthermore, it is sufficient to delete the amplifier 140 (1 / a1) and connect the output terminal of the adder 130-0 to the input terminal and output terminal 102 of the delay unit 112 of the signal processing unit 110-2.

[0042] As a result, it is possible to design an IIR type all-pass filter 100 having a circuit configuration shown in Fig. 7. The IIR type all-pass filter 100 with N=9 and M=N-3=6 shown in Fig. 7 has a significantly reduced circuit configuration compared to the IIR type all-pass filter 100 shown in Fig. 2B, and can achieve smaller size, lower cost, and lower power consumption. The IIR type all-pass filter 100 with N=9 and M=N-3=6 shown in Fig. 7 has fewer components than the IIR type all-pass filter 100 with N=9 and M=N-1=8 described later with Fig. 9.

[0043] <IIR type all-pass filter 100 (M=N-2) with reduced circuit configuration> Fig. 8 is a diagram showing an IIR type all-pass filter 100 with a reduced circuit configuration. Fig. 8 shows the configuration of the IIR type all-pass filter 100 for M=N-2. When N=9 and M=N-2=7, the filter coefficients a0 and a1 are both 1, so that the amplifier 120 and the amplifier 114 of the signal processing unit 110-1 can be deleted, and the output terminal of the delay unit 111 and the output terminal of the adder 113 of the signal processing unit 110-1 can be connected to one input terminal of the adder 130-0 via the newly added adder 150-0.

[0044] Also, the filter coefficients a2 and a3, the filter coefficients a4 and a5, the filter coefficients a6 and a7, and the filter coefficients a8 and a9 have the same values. Therefore, the amplifiers 114 (a3, a5, a7, a9) of the signal processing units 110-3, 110-5, 110-7, and 110-9 may be deleted, and the output terminals of the adders 113 of the signal processing units 110-3, 110-5, 110-7, and 110-9 may be connected to the input terminals of the amplifiers 114 (a, a4, a6, a8) of the signal processing units 110-2, 110-4, 110-6, and 110-8 via the newly added adders 150-2, 150-4, 150-6, and 150-8.

[0045] Furthermore, by deleting the amplifiers 114 (a1, a3, a5, a7, a9) of the signal processing units 110-1, 110-3, 110-5, 110-7, and 110-9, it is possible to delete the adders 130-1, 130-3, 130-5, 130-7, and 130-8. Furthermore, since the filter coefficient a0=1, it is only necessary to delete the amplifier 140 with an amplification factor of 1 / a0 and connect the output terminal of the adder 130-0 to the output terminal 102.

[0046] As a result, it is possible to design an IIR type all-pass filter 100 having a circuit configuration shown in Fig. 8. The IIR type all-pass filter 100 with N=9 and M=N-2=7 shown in Fig. 8 has a slightly larger circuit configuration than the IIR type all-pass filter 100 shown in Fig. 7, but the circuit configuration can be sufficiently reduced compared to the IIR type all-pass filter 100 shown in Fig. 2A, and it is possible to achieve miniaturization, cost reduction, and reduced power consumption.

[0047] <IIR type all-pass filter 100 (M=N-1) with reduced circuit configuration> Fig. 9 is a diagram showing an IIR type all-pass filter 100 with a reduced circuit configuration. Fig. 9 shows the configuration of an IIR type all-pass filter 100 with M=N-1. In the case of N=9 and M=N-1=8, the filter coefficients a1, a3, a5, a7, and a9 become zero, so that the amplifiers 114 (a1, a3, a5, a7, and a9) of the signal processing units 110-1, 110-3, 110-5, 110-7, and 110-9 can be deleted along with the path. In addition, by deleting the amplifiers 114 (a1, a3, a5, a7, and a9) of the signal processing units 110-1, 110-3, 110-5, 110-7, and 110-9 along with the path, the adders 113 of the signal processing units 110-1, 110-3, 110-5, 110-7, and 110-9 can be deleted along with the path. Furthermore, by eliminating adder 113 from signal processing section 110-9, delay section 112 from signal processing section 110-9 can also be eliminated.

[0048] Moreover, by deleting the amplifiers 114 (a1, a3, a5, a7) of the signal processing units 110-1, 110-3, 110-5, and 110-7, it is possible to delete the adders 130-1, 130-3, 130-5, and 130-7. Moreover, by deleting the amplifier 114 (a9) of the signal processing unit 110-9, it is possible to delete the adder 130-8. Moreover, since the filter coefficient a0=1, it is only necessary to delete the amplifier 120 and the amplifier 140 having an amplification factor of 1 / a0, and to connect the output terminal of the delay unit 111 of the signal processing unit 110-1 to one input terminal of the adder 130-0 and to connect the output terminal of the adder 130-0 to the output terminal 102.

[0049] As a result, it is possible to design an IIR type all-pass filter 100 having a circuit configuration shown in Fig. 9. The IIR type all-pass filter 100 with N=9 and M=N-1=8 shown in Fig. 9 has a significantly reduced circuit configuration compared to the IIR type all-pass filter 100 shown in Fig. 2A, and it is possible to achieve miniaturization, low cost, and reduced power consumption.

[0050] Next, the frequency characteristics of the IIR-type all-pass filter 100 with M = N - 2 and M = N - 1 will be described. Note that the frequency characteristics of the IIR-type all-pass filter 100 with M = N - 3 are as shown in FIGS. 3 to 5.

[0051] <Frequency characteristics of the IIR-type all-pass filter 100 (M = N - 2)> FIG. 10 is a diagram showing an example of the frequency characteristics of the IIR-type all-pass filter 100 with order N = 9 and M = N - 2. In FIG. 10(A), the horizontal axis represents frequency, and the vertical axis represents cumulative phase. Since the frequency on the horizontal axis is a normalized frequency, it has no unit. The cumulative phase on the vertical axis represents the number of 1 / π radians (rad). In FIG. 10, the I signal is indicated by a dashed line, and the Q signal is indicated by a solid line.

[0052] The I signal output from the digital signal delay circuit 8 (see FIG. 1) has a characteristic of shifting by -7π in phase while the frequency changes from 0 to 1. The Q signal has a phase that is 90 degrees later than the I signal in the frequency band of 0.1 to 0.9 in frequency, and has a characteristic of changing linearly with respect to the increase in frequency (π / 2 phase shift characteristic). The IIR-type all-pass filter 100 having the frequency characteristics shown in FIG. 10(A) has an order N = 9 and M = N - 2, so the group delay number M is 7 (M = 7). Actually, while the frequency changes from 0.1 to 0.9, the cumulative phase changes linearly by -5.6 (-1.2 to -6.8), so the group delay number becomes 7 simultaneously with the I signal.

[0053] Also, FIG. 10(B) is a diagram showing an example of the frequency characteristics of the phase difference between the I signal and the Q signal. In FIG. 10(B), the horizontal axis represents the normalized frequency, the left vertical axis represents the phase difference between the I signal and the Q signal in terms of the number of 1 / π radians (rad), and the right vertical axis represents the amplitude of the Q signal. In FIG. 10(B), the phase difference between the I signal and the Q signal is indicated by a solid line, and the amplitude of the Q signal is indicated by a dashed line.

[0054] As shown in FIG. 10(B), in the frequency band of 0.1 to 0.9 in frequency, the phase difference between the I signal and the Q signal is approximately 0.5 (π / 2 = 90 degrees), and the amplitude of the Q signal is 1.

[0055] FIG. 10(C) is a diagram showing an example of the frequency characteristics of the phase error of the Q signal. In FIG. 10(C), the horizontal axis represents the normalized frequency, and the vertical axis represents the phase error of the Q signal in degrees. The phase error of the Q signal is the error with respect to -90 degrees. As shown in FIG. 10(C), it was confirmed that the phase error of the Q signal with respect to the change in frequency is ±0.64 degrees, and a good equiripple characteristic with equal upper and lower swing widths was obtained.

[0056] <Frequency Characteristics of IIR All-Pass Filter 100 (M = N - 1)> FIG. 11 is a diagram showing an example of the frequency characteristics of the IIR all-pass filter 100 with degree N = 9 and M = N - 1. In FIG. 11(A), the horizontal axis represents the frequency, and the vertical axis represents the cumulative phase. Since the frequency on the horizontal axis is the normalized frequency, it has no unit. The cumulative phase on the vertical axis represents the number of 1 / π radians (rad). In FIG. 11, the I signal is shown by a dashed line, and the Q signal is shown by a solid line.

[0057] The I signal output from the digital signal delay circuit 8 (see FIG. 1) has a characteristic of shifting -8π in phase while the frequency changes from 0 to 1. The Q signal has a characteristic that its phase lags 90 degrees behind the I signal in the frequency band of 0.1 to 0.9 in frequency, and has a characteristic of changing linearly with respect to the increase in frequency (π / 2 phase shift characteristic). The IIR all-pass filter 100 having the frequency characteristics shown in FIG. 11(A) has degree N = 9 and M = N - 1, so the group delay number M is 8 (M = 8). Actually, while the frequency changes from 0.1 to 0.9, the cumulative phase linearly changes by -6.4 (-1.3 to -7.7), so the group delay number becomes 8 simultaneously with the I signal.

[0058] Also, FIG. 11(B) is a diagram showing an example of the frequency characteristics of the phase difference between the I signal and the Q signal. In FIG. 11(B), the horizontal axis represents the normalized frequency, the left vertical axis represents the phase difference between the I signal and the Q signal in the number of 1 / π radians (rad), and the right vertical axis represents the amplitude of the Q signal. In FIG. 11(B), the phase difference between the I signal and the Q signal is shown by a solid line, and the amplitude of the Q signal is shown by a dashed line.

[0059] As shown in FIG. 11(B), in the frequency band where the frequency is 0.1 to 0.9, the phase difference between the I signal and the Q signal is approximately 0.5 (π / 2 = 90 degrees), and the amplitude of the Q signal is 1.

[0060] FIG. 11(C) is a diagram showing an example of the frequency characteristics of the phase error of the Q signal. In FIG. 11(C), the horizontal axis represents the normalized frequency, and the vertical axis represents the phase error of the Q signal in degrees. The phase error of the Q signal is the error with respect to -90 degrees. As shown in FIG. 11(C), it was confirmed that the phase error of the Q signal is ±0.64 degrees with respect to the change in frequency, and a good equiripple characteristic with equal upper and lower swing widths is obtained.

[0061] <Configuration of IIR type all-pass filter 100 (N = 10)> FIG. 12 is a diagram showing an example of the configuration of the IIR type all-pass filter 100 (N = 10) according to the embodiment. The IIR type all-pass filter 100 shown in FIG. 12 is a filter with an order N of 10.

[0062] The IIR type all-pass filter 100 with an order N of 10 has a configuration in which a signal processing unit 110-10 and an adder 130-9 are added to the IIR type all-pass filter 100 with an order N of 9 shown in FIG. 2A. That is, the IIR type all-pass filter 100 with an order N of 10 includes ten signal processing units 110-1 to 110-10, an amplifier 120, ten adders 130-0 to 130-9, and an amplifier 140, which are provided between the input terminal 101 and the output terminal 102. The filter coefficients of the amplifiers 114 of the signal processing units 110-1 to 110-10 are a0 to a10.

[0063] FIG. 13 is a diagram showing a table of an example of the relationship between the combination of the order N and the group delay number M, the lower frequency fl, the upper frequency fh, the design bandwidth B, the phase error, and the filter coefficients a0 to a9.

[0064] The table in FIG. 13 shows the calculation results of the phase error and filter coefficients a0 to a10 obtained when the lower limit frequency fl is set to 0.1, the upper limit frequency fh is set to 0.9, and the design bandwidth B is set to 0.8 for four combinations of order N and group delay number M, namely, M=N-3=7, M=N-2=8, M=N-1=9, and M=N=10, where N=10. Here, all the filter coefficients a0 to a10 are shown normalized so that the maximum value among the filter coefficients a0 to a10 is 1. The filter coefficients ai may take negative values. Here, the maximum value of the filter coefficients a0 to a10 is set to 1. The phase error is shown as an absolute value.

[0065] When M=N-3=7, the phase error was a good value of 0.64 degrees, and among the filter coefficients a0 to a10, the filter coefficients ai with odd indexes i were zero. Specifically, the filter coefficients a1, a3, a5, a7, and a9 were zero. Here, the filter coefficients ai shown in FIG. 13 have significant figures up to three decimal places, and are values ​​rounded off to the fourth decimal place. These values ​​are values ​​obtained by processing described later with reference to FIG. 20.

[0066] Moreover, when M=N-2=8, the phase error is a little high at 2.86 degrees, and among the filter coefficients a0 to a10, the filter coefficients ai with index i starting from 0 and two each are the same value. Specifically, the filter coefficients a0 and a1 are both 1, the filter coefficients a2 and a3 are both -0.487, the filter coefficients a4 and a5 are both -0.105, the filter coefficients a6 and a7 are both -0.034, and the filter coefficients a8 and a9 are both -0.004. The reason why the filter coefficients ai with index i starting from 0 and two each are the same value is because the filter coefficients ai with index i starting from 0 and two each are set to the average value of two filter coefficients ai. The filter coefficient a10 is also -0.004, but the value at the fourth decimal point is different from the filter coefficients a8 and a9. These values ​​are values ​​obtained by processing described later with reference to FIG. 21.

[0067] Furthermore, when M=N-1=9, the phase error was a good value of 0.89 degrees, and among the filter coefficients a0 to a10, the filter coefficients ai with odd indexes i were zero. Specifically, the filter coefficients a1, a3, a5, a7, and a9 were zero. Here, the filter coefficients ai shown in FIG. 13 have significant figures up to three decimal places, and are values ​​rounded off to the fourth decimal place. These values ​​are values ​​obtained by processing described later with reference to FIG. 22.

[0068] Furthermore, when M=N=10, the phase error was 22.23 degrees, which is not a good value. Therefore, when N=10, the combinations of order N and group delay number M of M=N-3, M=N-2, and M=N-1 have good phase errors and can be used as an IIR type all-pass filter 100, but the combination of order N and group delay number M of M=N cannot be used. How to obtain the filter coefficients when M=N=10 will be described at the end of the explanation of FIG. 21.

[0069] Furthermore, for a combination of order N and group delay number M where M=N-3, the filter coefficients ai with odd index i among the filter coefficients a0 to a10 become zero. Therefore, it was found that it is possible to reduce approximately half (five) of the total of eleven amplifiers, including amplifiers 114 and 120 in signal processing units 110-1 to 110-10 shown in FIG. 12, as well as their surrounding components.

[0070] Similarly, for a combination of order N and group delay number M where M=N-1, the filter coefficients ai with odd index i among the filter coefficients a0 to a10 become zero, so it was found that it is possible to reduce approximately half (five) of the total of 11 amplifiers, including amplifiers 114 and 120 in signal processing units 110-1 to 110-10 shown in FIG. 12, as well as their surrounding components.

[0071] Also, for the combination of the order N of M = N - 2 and the group delay number M, for the signal processing units 110-1 to 110-9 among the signal processing units 110-1 to 110-10, by combining two amplifiers corresponding to filter coefficients ai with an index i incrementing by two from 0 into one (using one common amplifier), it was found that approximately half (5) of the total 11 amplifiers, namely the amplifiers 114 and 120 in the signal processing units 110-1 to 110-10 shown in FIG. 12, can be reduced. More specifically, the amplifier 120 and the amplifier 114 of the signal processing unit 110-1 are made into one common amplifier, the amplifiers 114 of the signal processing units 110-2 and 110-3 are made into one common amplifier, the amplifiers 114 of the signal processing units 110-4 and 110-5 are made into one common amplifier, the amplifiers 114 of the signal processing units 110-6 and 110-7 are made into one common amplifier, and the amplifiers 114 of the signal processing units 110-8 and 110-9 are made into one common amplifier, and it was found that the number of amplifiers can be halved. Also, by reducing the amplifiers, specifically, the components before and after can also be reduced. Note that for the specific circuit configuration of the IIR type all-pass filter 100 with the circuit configuration reduced in the cases of N = 10 and M = N - 3, M = N - 2, M = N - 1, since it is based on the same method as the IIR type all-pass filter 100 (FIGS. 7 to 9) with N = 9 and M = N - 3, M = N - 2, M = N - 1, it is omitted here.

[0072] <Frequency characteristics of the IIR type all-pass filter 100 (M = N - 3)> FIG. 14 is a diagram showing an example of the frequency characteristics of the IIR type all-pass filter 100 with an order N of 10 and M = N - 3. In FIG. 14(A), the horizontal axis represents frequency, and the vertical axis represents cumulative phase. Since the frequency on the horizontal axis is a normalized frequency, it has no unit. The cumulative phase on the vertical axis represents the number of 1 / π radians (rad). In FIG. 14, the I signal is shown by a dashed line, and the Q signal is shown by a solid line.

[0073] The I signal output from the digital signal delay circuit 8 (see FIG. 1) has a characteristic of shifting by -7π during the change in frequency from 0 to 1. The Q signal has a phase that is 90 degrees later than the I signal in the frequency band of 0.1 to 0.9, and has a characteristic (π / 2 phase shift characteristic) that linearly changes with the increase in frequency. The IIR type all-pass filter 100 having the frequency characteristics shown in FIG. 14(A) has a degree N of 10 and M = N - 3, so the group delay number M is 7 (M = 7). Actually, since the cumulative phase linearly changes from -1.2 to -6.8 by -5.6 while the frequency changes from 0.1 to 0.9, the group delay number becomes 7 simultaneously with the I signal.

[0074] Also, FIG. 14(B) is a diagram showing an example of the frequency characteristics of the phase difference between the I signal and the Q signal. In FIG. 14(B), the horizontal axis represents the normalized frequency, the left vertical axis represents the phase difference between the I signal and the Q signal in terms of the number of 1 / π radians (rad), and the right vertical axis represents the amplitude of the Q signal. In FIG. 14(B), the phase difference between the I signal and the Q signal is shown by a solid line, and the amplitude of the Q signal is shown by a dashed line.

[0075] As shown in FIG. 14(B), in the frequency band of 0.1 to 0.9, the phase difference between the I signal and the Q signal is approximately 0.5 (π / 2 = 90 degrees), and the amplitude of the Q signal is 1.

[0076] FIG. 14(C) is a diagram showing an example of the frequency characteristics of the phase error of the Q signal. In FIG. 14(C), the horizontal axis represents the normalized frequency, and the vertical axis represents the phase error of the Q signal in degrees. The phase error of the Q signal is the error with respect to -90 degrees. As shown in FIG. 14(C), it was confirmed that the phase error of the Q signal is ±0.64 degrees with respect to the change in frequency, and a good equiripple characteristic with equal upper and lower amplitudes was obtained. Note that the ripples occurring above and below at the position where the frequency is 0.5 are caused by the convenience of calculation in the simulation, and the actual phase error characteristic continuously changes with the change in frequency.

[0077] <Frequency characteristics of the IIR type all-pass filter 100 (M = N - 2)> Fig. 15 is a diagram showing an example of the frequency characteristics of an IIR type all-pass filter 100 where the order N is 10 and M=N-2. In Fig. 15(A), the horizontal axis represents frequency and the vertical axis represents cumulative phase. The frequency on the horizontal axis is a normalized frequency and has no unit. The cumulative phase on the vertical axis represents the number of 1 / π radians (rad). In Fig. 15, the I signal is shown by a dashed line and the Q signal is shown by a solid line.

[0078] The I signal output from the digital signal delay circuit 8 (see FIG. 1) has a characteristic of being shifted by -8π phase while the frequency changes from 0 to 1. The Q signal has a phase delay of 90 degrees from the I signal in the frequency band of 0.1 to 0.9, and has a characteristic of changing linearly with increasing frequency (π / 2 phase shift characteristic). The IIR all-pass filter 100 having the frequency characteristic shown in FIG. 15(A) has an order N of 10 and M=N-2, so that the group delay number M is 8 (M=8). In fact, the cumulative phase changes linearly by -6.4 (from -1.3 to -7.7) while the frequency changes from 0.1 to 0.9, so the group delay number becomes 8 at the same time as the I signal.

[0079] Moreover, Fig. 15(B) is a diagram showing an example of the frequency characteristic of the phase difference between the I signal and the Q signal. In Fig. 15(B), the horizontal axis represents normalized frequency, and the left vertical axis represents the phase difference between the I signal and the Q signal in the number of 1 / π radians (rad). The right vertical axis represents the amplitude of the Q signal. In Fig. 15(B), the phase difference between the I signal and the Q signal is shown by a solid line, and the amplitude of the Q signal is shown by a dashed line.

[0080] As shown in FIG. 15(B), in the frequency band of 0.1 to 0.9, the phase difference between the I signal and the Q signal was approximately 0.5 (π / 2=90 degrees), and the amplitude of the Q signal was 1.

[0081] FIG. 15(C) is a diagram showing an example of the frequency characteristics of the phase error of the Q signal. In FIG. 15(C), the horizontal axis represents the normalized frequency, and the vertical axis represents the phase error of the Q signal in degrees. The phase error of the Q signal is the error with respect to -90 degrees. As shown in FIG. 15(C), with respect to the change in frequency, the phase error of the Q signal is larger on the positive side at +2.86 degrees, and an equiripple characteristic could not be obtained. Although the phase error is large, it is an IIR type all-pass filter 100 that can be used depending on the application.

[0082] <Frequency Characteristics of IIR Type All-Pass Filter 100 (M = N - 1)> FIG. 16 is a diagram showing an example of the frequency characteristics of an IIR type all-pass filter 100 with order N = 10 and M = N - 1. In FIG. 16(A), the horizontal axis represents the frequency, and the vertical axis represents the cumulative phase. Since the frequency on the horizontal axis is the normalized frequency, it has no unit. The cumulative phase on the vertical axis represents the number of 1 / π radians (rad). In FIG. 16, the I signal is shown by a dashed line, and the Q signal is shown by a solid line.

[0083] The I signal output from the digital signal delay circuit 8 (see FIG. 1) has a characteristic of shifting -9π in phase while the frequency changes from 0 to 1. The Q signal has a characteristic that its phase lags 90 degrees behind the I signal in the frequency band of 0.1 to 0.9, and has a characteristic of changing linearly with respect to the increase in frequency (π / 2 phase shift characteristic). The IIR type all-pass filter 100 having the frequency characteristics shown in FIG. 16(A) has an order N = 10 and M = N - 1, so the group delay number M is 9 (M = 9). Actually, while the frequency changes from 0.1 to 0.9, the cumulative phase changes linearly by -7.2 (-1.4 to -8.6), so the group delay number becomes 9 simultaneously with the I signal.

[0084] Moreover, Fig. 16(B) is a diagram showing an example of the frequency characteristic of the phase difference between the I signal and the Q signal. In Fig. 16(B), the horizontal axis represents normalized frequency, and the left vertical axis represents the phase difference between the I signal and the Q signal in the number of 1 / π radians (rad). The right vertical axis represents the amplitude of the Q signal. In Fig. 16(B), the phase difference between the I signal and the Q signal is shown by a solid line, and the amplitude of the Q signal is shown by a dashed line.

[0085] As shown in FIG. 16(B), in the frequency band of 0.1 to 0.9, the phase difference between the I signal and the Q signal was approximately 0.5 (π / 2=90 degrees), and the amplitude of the Q signal was 1.

[0086] Fig. 16(C) is a diagram showing an example of the frequency characteristic of the phase error of the Q signal. In Fig. 16(C), the horizontal axis represents the normalized frequency, and the vertical axis represents the phase error of the Q signal in degrees. The phase error of the Q signal is the error relative to -90 degrees. As shown in Fig. 16(C), the phase error of the Q signal with respect to the change in frequency is ±0.89 degrees, and although it is not an equiripple characteristic, it was confirmed that a practically usable error characteristic was obtained.

[0087] <Computer system 20 for implementing the filter design method> 17 is a diagram showing a computer system 20. The computer system 20 includes a main body 21, a display 22, a keyboard 23, a mouse 24, and a modem 25, and is used as a server on which the filter design program of the embodiment is installed. The filter design method of the embodiment is realized by executing the filter design program of the embodiment. The computer system 20 functions as a filter design device 200. For this reason, the reference numeral 200 is written in parentheses around the reference numeral 20.

[0088] The main body 21 incorporates a CPU (Central Processing Unit), an HDD (Hard Disk Drive), a disk drive, etc. The display 22 displays processing results, etc. on a screen 22A in response to instructions from the main body 21. The display 22 may be, for example, a liquid crystal monitor. The keyboard 23 is an input unit for inputting various information to the computer system 20. The mouse 24 is an input unit for specifying an arbitrary position on the screen 22A of the display 22. The modem 25 accesses an external database, etc., to download programs, etc. stored in another computer system.

[0089] The filter design program of the embodiment is stored in a portable recording medium such as disk 27, or downloaded from a recording medium 26 of another computer system using a communication device such as modem 25, and input to computer system 20 to be compiled. The portable recording medium may be an IC card memory, a magnetic disk such as a floppy (registered trademark) disk, a magneto-optical disk, a CD-ROM, a USB (Universal Serial Bus) memory, or the like. Instead of a portable recording medium, a computer-readable recording medium accessible by a computer system connected via a communication device such as modem 25 or a LAN may be used.

[0090] Fig. 18 is a block diagram explaining the configuration of the main parts in the main body 21 of the computer system 20. The main body 21 includes a CPU 31, a memory section 32 including RAM or ROM, etc., a disk drive 33 for the disk 27, and a hard disk drive (HDD) 34, all connected by a bus 30. Note that the computer system 20 is not limited to the configuration shown in Figs. 17 and 18, and various well-known elements may be added or used instead.

[0091] <Function block> 19 is a diagram showing functional blocks of the filter design device 200. The computer system 20 functions as the filter design device 200 by executing a filter design program.

[0092] The filter design device 200 has a main control unit 201, an input processing unit 202, a parameter setting unit 203, a filter coefficient calculation unit 204, an index extraction unit 205, a reduction processing unit 206, and a memory 207. The main control unit 201, the input processing unit 202, the parameter setting unit 203, the filter coefficient calculation unit 204, the index extraction unit 205, and the reduction processing unit 206 are functional blocks showing the functions of a filter design program executed by the computer system 20. The memory 207 is a functional representation of the memory of the computer system 20.

[0093] The main control unit 201 is a processing unit that controls the processing of the filter design device 200 , and executes processes other than those executed by the input processing unit 202 , the parameter setting unit 203 , the filter coefficient calculation unit 204 , the index extraction unit 205 , and the reduction processing unit 206 .

[0094] The input processing unit 202 performs processing for receiving input of the order N and the design bandwidth B of the IIR type all-pass filter. The order N and the design bandwidth B are input by the user using the keyboard 23 and / or the mouse 24.

[0095] The parameter setting unit 203 uses the design bandwidth B to perform a process of setting a lower limit frequency fl and an upper limit frequency fh.

[0096] The filter coefficient calculation unit 204 calculates filter coefficients ai (i=0 to N) including N filter coefficients a1 to aN by which the outputs of N signal processing units 110-1 to 110-N are multiplied, and a filter coefficient a0 by which the output of delay unit 111 of the Nth signal processing unit 110-1 from the input terminal 101 is multiplied, so as to realize a π / 2 phase shift characteristic, and performs processing to calculate the filter coefficients ai using the Remez algorithm until the change in frequency at which the amplitude value of the complex amplitude error shows an extreme value converges to a predetermined value or less.

[0097] Furthermore, when the index extraction section 205 extracts the maximum value of the filter coefficients ai and the index i (assumed to be imax) of the filter coefficients ai that give the maximum value, the filter coefficient calculation section 204 performs the following process.

[0098] When the group delay number M is order N-3, if the order N is odd and the index imax is 1, the filter coefficient calculation unit 204 sets the filter coefficient ai with an even index i to zero, and if the order N is even and the index imax is 0, the filter coefficient ai with an odd index i to zero.

[0099] When the group delay number M is the order N-1, if the index imax is 0, the filter coefficient calculation unit 204 performs a process of setting the filter coefficient ai having an odd index i to zero.

[0100] When the group delay number M is order N-2, and the index imax is 0 or 1, the filter coefficient calculation unit 204 performs processing to set every two filter coefficients ai, starting from index i 0, to the same value (the average value of the two filter coefficients).

[0101] The index extraction unit 205 performs processing to extract the maximum value of the filter coefficients ai and the index i (assumed to be imax) of the filter coefficient ai that gives the maximum value.

[0102] The reduction processing unit 206 performs a process of reducing the components of a signal processing unit corresponding to an index i in which the filter coefficient ai of the signal processing units 110-1 to 110-N is set to zero, or a process of reducing the components of one of two signal processing units corresponding to an index i in which the filter coefficient ai of the signal processing units 110-1 to 110-N is set to the same value.

[0103] The memory 207 stores a filter design program. The memory 207 also stores the calculated filter coefficients ai, data necessary for the main control unit 201, the input processing unit 202, the parameter setting unit 203, the filter coefficient calculation unit 204, the index extraction unit 205, and the reduction processing unit 206 to perform processing, data generated by the processing, and the like.

[0104] <Calculations in filter design method> Next, a description will be given of a calculation method for designing the IIR all-pass filter 100. This calculation is performed by the filter coefficient calculation unit 204.

[0105] First, Ad is calculated according to the following formula (1). Ad is the frequency characteristic of a π / 2 phase-shift all-pass filter with a constant group delay characteristic, and is the desired characteristic targeted in filter design. Here, f is the normalized frequency, which corresponds to the frequency on the horizontal axis in Figures 3 to 5, 10, 11, and 14 to 16. The frequency f is in the range of 0≦f≦1, and f=1 is the Nyquist frequency. Also, j is the imaginary unit (√-1).

[0106]

number

[0107] Here, θd in equation (1) represents a desired accumulated phase of the Q signal, and is expressed by the following equation (2): The phase of the Q signal lags behind the phase (−πMf) of the I signal by π / 2.

[0108]

number

[0109] The frequency characteristic of the IIR all-pass filter 100 is calculated by the following equation (3).

[0110]

number

[0111] The evaluation function for evaluating the amplitude error as a complex amplitude error is defined as the difference between equations (1) and (3), and is expressed by the following equation (4).

[0112]

number

[0113] The filter coefficients ai are optimally approximated using the following equation (5) so that the amplitude value E*(f) of the error function is equal to or smaller than a predetermined value.

[0114]

number

[0115] |D(f)| in equation (5) is calculated using the following equation (6).

[0116]

number

[0117] In order to make the amplitude value E*(f) of the error function equal to or less than a predetermined value, specifically, the filter coefficients are optimized using the following equation (7) so that the amplitude value E*(f) of the error function becomes equiripple at frequency points fk (k is 0 to N).

[0118]

number

[0119] When equation (7) is expanded using the filter coefficients ai, the following equation (8) is obtained: Index i ranges from 0 to N, and δ is a predetermined value.

[0120]

number

[0121] When equation (8) is formulated for N+1 frequency points fk and rearranged with respect to the filter coefficients ai, it is expressed as a matrix as in equation (9) below, from which the filter coefficients ai can be obtained.

[0122]

number

[0123] Ski in equation (9) is expressed by the following equation (10): Index i ranges from 0 to N, and index k also ranges from 0 to N.

[0124]

number

[0125] By performing the above calculations, for example, the filter coefficients ai shown in FIG. 6 and FIG. 13 can be obtained.

[0126] <Flowchart (M=N-3)> 20 is a flowchart showing a process executed by filter design device 200. Here, a case will be described where group delay number M is M=N-3.

[0127] When the process starts, the input processing unit 202 performs a process of receiving inputs of the order N and the design bandwidth B of the IIR type all-pass filter 100 as design conditions (step S10). The order N is 4 or more, and the design bandwidth B is greater than 0 and less than 1 (0 <B<1)である。

[0128] The parameter setting unit 203 performs a process of setting design parameters (step S11). The design parameters are the lower limit frequency fl, the upper limit frequency fh, and the group delay number M. Here, the group delay number M is M=N-3. The lower limit frequency fl and the upper limit frequency fh are calculated by the following equation (11). Here, the lower limit frequency fl and the upper limit frequency fh are set so that they have equal bandwidths centered around a frequency of 0.5, which is half the Nyquist frequency. This is the same as setting the lower limit frequency fl and the upper limit frequency fh so that the sum of the lower limit frequency fl and the upper limit frequency fh is the Nyquist frequency 1.

[0129]

number

[0130] The filter coefficient calculation unit 204 sets a design initial value (step S12). Specifically, the filter coefficient calculation unit 204 sets frequency points fk at equal intervals between fl and fh, where k=0 to N. The filter coefficient calculation unit 204 also initializes |D(fk)| to 1.0.

[0131] The filter coefficient calculation unit 204 calculates filter coefficients ai having a π / 2 phase shift characteristic in an IIR type all-pass filter by using equations (9) and (10) (step S13), where i=0 to N.

[0132] The index extraction unit 205 extracts the maximum value amax and the index imax of the filter coefficient ai that gives the maximum value from among the filter coefficients a0 to aN calculated in step S13 (step S14).

[0133] The filter coefficient calculation unit 204 determines whether the order N is an odd number (step S15).

[0134] If the filter coefficient calculation unit 204 determines that the order N is an odd number (S15: YES), it determines whether the index imax is 1 (step S16).

[0135] When the filter coefficient calculation unit 204 determines that the index imax is 1 (S16: YES), it sets the values ​​of the filter coefficients ai whose index i is an even number to zero (step S17). For example, as in the calculation result of M=N-3 in Fig. 6, the filter coefficients a0, a2, a4, a6, and a8 are set to zero. After completing the process of step S17, the filter coefficient calculation unit 204 advances the flow to step S20, but before that, steps S18 and S19 will be described.

[0136] Furthermore, if it is determined in step S15 that the order N is not an odd number (S15: NO), the filter coefficient calculation unit 204 determines whether the index imax is 0 (step S18).

[0137] If the filter coefficient calculation unit 204 determines that the index imax is 0 (S18: YES), it sets the values ​​of the filter coefficients ai whose index i is an odd number to zero (step S19). For example, as in the calculation result of M=N-3 in FIG. 13, the filter coefficients a1, a3, a5, a7, and a9 are set to zero. After completing the process of step S19, the filter coefficient calculation unit 204 advances the flow to step S20. Also, if the filter coefficient calculation unit 204 determines in step S18 that the index imax is not 0 (S18: NO), it also advances the flow to step S20.

[0138] The filter coefficient calculation unit 204 normalizes the value of the filter coefficient ai by the maximum value amax (step S20). This is performed for all i=0 to N.

[0139] The filter coefficient calculation unit 204 calculates the amplitude value E*(f) of the error function using equations (5) and (6). Here, multiple frequency points that satisfy the relationship of fl≦f≦fh are substituted for f in equations (5) and (6) to perform the calculation. The multiple calculated amplitude values ​​E*(f) are referenced, and frequencies showing the maximum and minimum values ​​are searched for and stored in fpk (step S21). k=0 to N. Here, it is preferable that the multiple frequency points are set with a granularity that allows the maximum and minimum values ​​of the amplitude value E*(f) to be distinguished.

[0140] The filter coefficient calculation unit 204 calculates the difference Δfk between the frequency point fk and the frequency fpk, and searches for the maximum value Δfkmax of the difference Δfk (k=0 to N) (step S22). That is, Δfk=|fk−fpk|, where k=0 to N.

[0141] The filter coefficient calculation unit 204 determines whether the maximum value Δfkmax is equal to or smaller than a predetermined value (step S23).

[0142] When the filter coefficient calculation unit 204 determines that the maximum value Δfkmax is equal to or smaller than the predetermined value (S23: YES), it stores the filter coefficients ai (i=0 to N) in the memory 207 (step S24).

[0143] After completing the process of step S24, the filter coefficient calculation unit 204 ends the series of processes (END).

[0144] Furthermore, if the filter coefficient calculation unit 204 determines in step S23 that the maximum value Δfkmax is not equal to or less than the predetermined value (S23: NO), it updates the frequency points fk (k=0 to N) with frequencies fpk (k=0 to N) (step S25). That is, it updates the frequency points f0 to fN to frequencies fp0 to fpN, respectively.

[0145] The filter coefficient calculation unit 204 calculates |D(fi)| (i = 0 to N) by substituting the frequency point fk into f using Equation (6) (step S26). When the process of step S26 is completed, the filter coefficient calculation unit 204 returns the flow to step S13. The processes of steps S13, S14, S20 to S26 are performed according to the Remez algorithm.

[0146] Through the above processing, the filter coefficients ai that are set to zero when the order N is odd or even and M = N - 3 are specified.

[0147] The reduction processing unit 206 reduces the components of the signal processing unit 110 - i corresponding to the index i of the filter coefficient ai set to zero in the process of FIG. 20. For example, when N = 9, the circuit configuration shown in FIG. 2B is reduced to the circuit configuration shown in FIG. 7 by the reduction processing unit 206.

[0148] <Flowchart (M = N - 2)> FIG. 21 is a flowchart showing the processing executed by the filter design apparatus 200. Here, the case where the group delay number M is M = N - 2 will be described.

[0149] When the process starts, the input processing unit 202 performs a process of receiving an input of the order N and the design bandwidth B of the IIR type all - pass filter 100 as design conditions (step S110). The order N is 4 or more, and the design bandwidth B is greater than 0 and less than 1 (0 < B < 1). The process of step S110 is the same as the process of step S10 in FIG. 20.

[0150] The parameter setting unit 203 performs a process of setting design parameters (step S111). The design parameters are the lower - limit frequency fl, the upper - limit frequency fh, and the group delay number M. Here, the group delay number M is M = N - 2. Also, the lower - limit frequency fl and the upper - limit frequency fh are obtained by the following Equation (12). The process of step S111 is the same as the process of step S11 in FIG. 20 except for the setting of the group delay number M.

[0151]

number

[0152] The filter coefficient calculation unit 204 sets a design initial value (step S112). Specifically, the filter coefficient calculation unit 204 sets frequency points fk between fl and fh at equal intervals, where k=0 to N. The filter coefficient calculation unit 204 also initializes |D(fk)| to 1.0. The process of step S112 is the same as the process of step S12 in FIG. 20.

[0153] The filter coefficient calculation unit 204 calculates filter coefficients ai having a π / 2 phase shift characteristic in an IIR type all-pass filter by using equations (9) and (10) (step S113), where i = 0 to N. The process of step S113 is the same as the process of step S13 in FIG.

[0154] The index extraction unit 205 extracts the maximum value amax and the index imax of the filter coefficient ai that gives the maximum value from among the filter coefficients a0 to aN calculated in step S113 (step S114). The process of step S114 is the same as the process of step S14 in FIG.

[0155] The filter coefficient calculation unit 204 determines whether the index imax is 1 (step S115).

[0156] Furthermore, if the filter coefficient calculation unit 204 determines that the index imax is not 1 (S115: NO), it determines whether the index imax is 0 (step S116).

[0157] If the filter coefficient calculation unit 204 determines that the index imax is 0 (S116: YES), the flow proceeds to step S117.

[0158] When the filter coefficient calculation unit 204 determines in step S115 that the index imax is 1 (S115: YES), it sets (updates) each of the two filter coefficients ai, each of which has an index i starting from 0, to the average value of the two filter coefficients ai (step S117). For example, for the filter coefficients a0 and a1, it calculates V01=(a0+a1) / 2, and sets the new filter coefficient a0 to V01. Similarly, for the filter coefficients a2 and a3, it calculates V23=(a2+a3) / 2, and sets the new filter coefficient a1 to V23. The same applies below.

[0159] The filter coefficient calculation unit 204 updates the maximum value amax of the filter coefficients ai (i=0 to N) to the average value V01 (step S118). That is, amax=V01=(a0+a1) / 2.

[0160] The filter coefficient calculation unit 204 normalizes the value of the filter coefficient ai by the maximum value amax (step S120). This is performed for all i = 0 to N. The process of step S120 is the same as the process of step S20 in FIG.

[0161] The filter coefficient calculation unit 204 calculates the amplitude value E*(f) of the error function using equations (5) and (6). Here, multiple frequency points that satisfy the relationship of fl≦f≦fh are substituted for f in equations (5) and (6) to perform the calculation. The calculated multiple amplitude values ​​E*(f) are referenced, and frequencies showing the maximum and minimum values ​​are searched for and stored in fpk (step S121). k=0 to N. Here, it is preferable that the multiple frequency points are set with a granularity that allows the maximum and minimum values ​​of the amplitude value E*(f) to be distinguished. The process of step S121 is the same as the process of step S21 in FIG. 20.

[0162] The filter coefficient calculation unit 204 calculates the difference Δfk between the frequency point fk and the frequency fpk, and searches for the maximum value Δfkmax of the difference Δfk (k=0 to N) (step S122). That is, Δfk=|fk-fpk|, k=0 to N. The process of step S122 is the same as the process of step S22 in FIG. 20.

[0163] The filter coefficient calculation unit 204 determines whether the maximum value Δfkmax is equal to or smaller than a predetermined value (step S123). The process of step S123 is the same as the process of step S23 in FIG.

[0164] When the filter coefficient calculation unit 204 determines that the maximum value Δfkmax is equal to or smaller than the predetermined value (S123: YES), it stores the filter coefficients ai (i=0 to N) in the memory 207 (step S124). The process of step S124 is the same as the process of step S24 in FIG.

[0165] After completing the process of step S124, the filter coefficient calculation unit 204 ends the series of processes (END).

[0166] Furthermore, if the filter coefficient calculation unit 204 determines in step S123 that the maximum value Δfkmax is not equal to or less than the predetermined value (S123: NO), it updates the frequency points fk (k=0 to N) with frequencies fpk (k=0 to N) (step S125). That is, it updates the frequency points f0 to fN with frequencies fp0 to fpN, respectively. The process of step S125 is the same as the process of step S25 in FIG. 20.

[0167] The filter coefficient calculation unit 204 calculates |D(fk)| (k=0 to N) by substituting the frequency point fk for f using equation (6) (step S126). After completing the process of step S126, the filter coefficient calculation unit 204 returns the flow to step S113. The processes of steps S113, S114, and S120 to S126 are performed according to the Remez algorithm.

[0168] Through the above process, filter coefficients ai are specified that are set to the same value two by two when the order N is an odd or even number and M=N-2.

[0169] The reduction processing unit 206 reduces one of the components of two signal processing units 110-i corresponding to the index i for which the filter coefficient ai is set to the same value in the process of FIG. 21. For example, when N = 9, the circuit configuration shown in FIG. 2A is reduced to the circuit configuration shown in FIG. 8 by the reduction processing unit 206.

[0170] Note that the values in the case of M = N = 9 shown in FIG. 6 and the values in the case of M = N = 10 shown in FIG. 13 are calculated by setting M = N in step S111 and proceeding to step S120 without going through steps S115, S117, and S118 after performing the process of step S114 in the flow shown in FIG. 21.

[0171] <Flowchart (M = N - 1)> FIG. 22 is a flowchart showing the process executed by the filter design apparatus 200. Here, the case where the group delay number M is M = N - 1 will be described.

[0172] When the process starts, the input processing unit 202 performs a process of receiving an input of the order N and the design bandwidth B of the IIR type all-pass filter 100 as design conditions (step S210). The order N is 4 or more, and the design bandwidth B is greater than 0 and less than 1 (0 < B < 1). The process of step S210 is the same as the process of step S10 in FIG. 20.

[0173] The parameter setting unit 203 performs a process of setting design parameters (step S211). The design parameters are the lower limit frequency fl, the upper limit frequency fh, and the group delay number M. Here, the group delay number M is M = N - 1. Also, the lower limit frequency fl and the upper limit frequency fh are obtained by the following equation (13). The process of step S211 is the same as the process of step S11 in FIG. 20 except for the setting of the group delay number M.

[0174]

Equation

[0175] The filter coefficient calculation unit 204 sets a design initial value (step S212). Specifically, the filter coefficient calculation unit 204 sets frequency points fk between fl and fh at equal intervals, where k=0 to N. The filter coefficient calculation unit 204 also initializes |D(fk)| to 1.0. The process of step S212 is the same as the process of step S12 in FIG. 20.

[0176] The filter coefficient calculation unit 204 calculates filter coefficients ai having a π / 2 phase shift characteristic in an IIR type all-pass filter by using equations (9) and (10) (step S213), where i = 0 to N. The process of step S213 is the same as the process of step S13 in FIG.

[0177] The index extraction unit 205 extracts the maximum value amax and the index imax of the filter coefficient ai that gives the maximum value from among the filter coefficients a0 to aN calculated in step S213 (step S214). The process of step S214 is the same as the process of step S14 in FIG.

[0178] The filter coefficient calculation unit 204 determines whether the index imax is 0 (step S218).

[0179] Furthermore, when the filter coefficient calculation unit 204 determines that the index imax is 0 (S218: YES), it sets the values ​​of the filter coefficients ai whose index i is an odd number to zero (step S219). For example, as in the calculation result of M=N-1 in Fig. 6, the filter coefficients a1, a3, a5, a7, and a9 are set to zero. When the filter coefficient calculation unit 204 finishes the process of step S219, it advances the flow to step S220. However, even when it is determined in step S218 that the index imax is not 0 (S218: NO), it also advances the flow to step S220.

[0180] The filter coefficient calculation unit 204 normalizes the value of the filter coefficient ai by the maximum value amax (step S220). This is performed for all i = 0 to N. The process of step S220 is the same as the process of step S20 in FIG.

[0181] The filter coefficient calculation unit 204 calculates the amplitude value E*(f) of the error function using equations (5) and (6). Here, multiple frequency points that satisfy the relationship of fl≦f≦fh are substituted for f in equations (5) and (6) to perform the calculation. The calculated multiple amplitude values ​​E*(f) are referenced, and frequencies showing the maximum and minimum values ​​are searched for and stored in fpk (step S221). k=0 to N. Here, it is preferable that the multiple frequency points are set with a granularity that allows the maximum and minimum values ​​of the amplitude value E*(f) to be distinguished. The process of step S221 is the same as the process of step S21 in FIG. 20.

[0182] The filter coefficient calculation unit 204 calculates the difference Δfk between the frequency point fk and the frequency fpk, and searches for the maximum value Δfkmax of the difference Δfk (k=0 to N) (step S222). That is, Δfk=|fk-fpk|, k=0 to N. The process of step S222 is the same as the process of step S22 in FIG. 20.

[0183] The filter coefficient calculation unit 204 determines whether the maximum value Δfkmax is equal to or smaller than a predetermined value (step S223). The process of step S223 is the same as the process of step S23 in FIG.

[0184] When the filter coefficient calculation unit 204 determines that the maximum value Δfkmax is equal to or smaller than the predetermined value (S223: YES), it stores the filter coefficients ai (i=0 to N) in the memory 207 (step S224). The process of step S224 is the same as the process of step S24 in FIG.

[0185] After completing the process of step S224, the filter coefficient calculation unit 204 ends the series of processes (END).

[0186] Furthermore, if the filter coefficient calculation unit 204 determines in step S223 that the maximum value Δfkmax is not equal to or less than the predetermined value (S223: NO), it updates the frequency points fk (k=0 to N) with frequencies fpk (k=0 to N) (step S225). That is, it updates the frequency points f0 to fN with frequencies fp0 to fpN, respectively. The process of step S225 is the same as the process of step S25 in FIG. 20.

[0187] The filter coefficient calculation unit 204 calculates |D(fk)| (k=0 to N) by substituting the frequency point fk for f using equation (6) (step S226). After completing the process of step S226, the filter coefficient calculation unit 204 returns the flow to step S213. The processes of steps S213, S214, and S220 to S226 are performed according to the Remez algorithm.

[0188] Through the above process, the filter coefficients ai that are set to zero when the order N is odd or even and M=N-1 are specified.

[0189] The reduction processing unit 206 reduces components of the signal processing unit 110-i corresponding to the index i of the filter coefficient ai that has been set to zero in the process of Fig. 22. For example, when N=9, the circuit configuration shown in Fig. 2A is reduced to the circuit configuration shown in Fig. 9 by the reduction processing unit 206.

[0190] As described above, when the order N is 9 or 10 and the group delay number M is M=N-3 or M=N-1, some filter coefficients ai can be set to zero, and the components of the signal processing unit 110-i corresponding to the index i of the filter coefficient ai set to zero can be reduced. Also, when the order N is 9 or 10 and the group delay number M is M=N-2, two filter coefficients ai can be set to the same value, and the components of one of the two signal processing units 110-i corresponding to the index i with the filter coefficients ai set to the same value can be reduced.

[0191] Therefore, it is possible to provide a filter design method and an IIR all-pass filter 100 that can reduce the number of components.

[0192] Although the above describes cases where the order N is 9 or 10, it has been confirmed that if the order N is 4 or more, it is possible to reduce the number of components up to about 80. Since the range of order N can be covered up to about 80, it is possible to design IIR type all-pass filters 100 of almost all orders N that are actually usable in order to reduce the number of components.

[0193] The filter design method and the IIR type all-pass filter according to the exemplary embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims. [Explanation of symbols]

[0194] 100 IIR type all-pass filter 101 Input terminal 102 Output terminal 110, 110-1 to 110-10, 110-N Signal processing unit 111, 112 Delay 113 Adder 114 Amplifier 115 Adder 120 Amps 130 Adder 140 Amps 200 Filter Design Device 201 Main control unit 202 Input processing section 203 Parameter setting section 204 Filter coefficient calculation section 205 Index Extraction Unit 206 Reduction Processing Unit 207 Memory

Claims

1. A filter design method for designing an IIR type all-pass filter including N (N is an integer of 4 or more) signal processing sections connected between an input terminal and an output terminal, the method comprising the steps of: With respect to an order N defined by the number N of the signal processing units, a group delay number M of the IIR type all-pass filter has a relationship of M=N-3, The computer, accepting input of the order N and a bandwidth B of the IIR type all-pass filter; Using the bandwidth B, a lower limit frequency f1 and an upper limit frequency fh are set symmetrically; Calculating filter coefficients ai (i=0 to N) including N filter coefficients a1 to aN by which the outputs of the N signal processing units are multiplied and a filter coefficient a0 by which the output of the delay unit of the Nth signal processing unit from the input terminal is multiplied so as to realize a π / 2 phase shift characteristic, and calculating the filter coefficients ai by the Remez algorithm until a change in frequency at which the amplitude value of the complex amplitude error shows an extreme value converges to a predetermined value or less; extracting a maximum value of the filter coefficient ai and an index i (denoted as imax) of the filter coefficient ai that gives the maximum value; When the order N is an odd number and the index imax is 1, the filter coefficient ai having the even index i is set to zero, and when the order N is an even number and the index imax is 0, the filter coefficient ai having the odd index i is set to zero. The filter design method includes the steps of:

2. A filter design method for designing an IIR type all-pass filter including N (N is an integer of 4 or more) signal processing sections connected between an input terminal and an output terminal, the method comprising the steps of: With respect to an order N defined by the number N of the signal processing units, a group delay number M of the IIR type all-pass filter has a relationship of M=N-1, The computer, accepting input of the order N and a bandwidth B of the IIR type all-pass filter; Using the bandwidth B, a lower limit frequency f1 and an upper limit frequency fh are set symmetrically; Calculating filter coefficients ai (i=0 to N) including N filter coefficients a1 to aN by which the outputs of the N signal processing units are multiplied and a filter coefficient a0 by which the output of the delay unit of the Nth signal processing unit from the input terminal is multiplied so as to realize a π / 2 phase shift characteristic, and calculating the filter coefficients ai by the Remez algorithm until a change in frequency at which the amplitude value of the complex amplitude error shows an extreme value converges to a predetermined value or less; extracting the maximum value of the filter coefficient ai and the index i (defined as imax) of the filter coefficient ai that gives the maximum value; When the index imax is 0, the filter coefficient ai having the index i of an odd number is set to zero. The filter design method includes the steps of:

3. 3. The filter design method according to claim 1, wherein the processing further comprises reducing components of a signal processing unit corresponding to an index i of the N signal processing units whose filter coefficients ai are set to zero.

4. A filter design method for designing an IIR type all-pass filter including N (N is an integer of 4 or more) signal processing sections connected between an input terminal and an output terminal, the method comprising the steps of: With respect to an order N defined by the number N of the signal processing units, a group delay number M of the IIR type all-pass filter has a relationship of M=N-2, The computer, accepting input of the order N and a bandwidth B of the IIR type all-pass filter; Using the bandwidth B, a lower limit frequency f1 and an upper limit frequency fh are set symmetrically; Calculating filter coefficients ai (i=0 to N) including N filter coefficients a1 to aN by which the outputs of the N signal processing units are multiplied and a filter coefficient a0 by which the output of the delay unit of the Nth signal processing unit from the input terminal is multiplied so as to realize a π / 2 phase shift characteristic, and calculating the filter coefficients ai by the Remez algorithm until a change in frequency at which the amplitude value of the complex amplitude error shows an extreme value converges to a predetermined value or less; extracting the maximum value of the filter coefficient ai and the index i (defined as imax) of the filter coefficient ai that gives the maximum value; When the index imax is 0 or 1, the filter coefficients ai starting from the index i of 0 are set to the same value. The filter design method includes the steps of:

5. 5. The filter design method according to claim 4, wherein the processing further includes reducing components of one of two signal processing units corresponding to index i in which the filter coefficients ai among the N signal processing units are set to the same value.

6. 6. An IIR type all-pass filter designed by the filter design method according to claim 1.

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