Power semiconductor device and cell data generation system

Abstract

To improve a performance of a power semiconductor device.SOLUTION: The present invention relates to a power semiconductor device having: unit cells UR and UL arranged periodically in an X direction and a Y direction that are orthogonal each other; and a plurality of termination end cells. Here, in the X direction, each of the unit cells UR and UL is alternately arranged, and the plurality of termination end cells contains an X-termination end cell XL, Y-termination end cells YR and YL, an XY-termination end cell XY1 L, and an XY-termination end cell XY2 L for an optional region. The number of periodic arrangements in each of the unit cells UR and UL in the Y direction is changed depending on a repetition periodic coordinate of the X direction, and each of the unit cells UR and UL that are periodically arranged is adjacent to any one of the plurality of termination end cells in the outermost part of the periodic arrangement of each of the X direction and the Y direction. In a region where each of the plurality of termination end cells exists, an electric characteristic that is different from that of the unit cells UR and UL is provided.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] The present invention relates to a power semiconductor device and a cell data generation system. [Background technology]

[0002] Power metal insulator semiconductor field effect transistors (MISFETs), which are one type of power semiconductor device, have traditionally been dominated by power MISFETs using silicon (Si) substrates (hereafter referred to as Si power MISFETs). In contrast, power MISFETs using silicon carbide (SiC) substrates (hereafter referred to as SiC substrates) (hereafter referred to as SiC power MISFETs) can achieve higher breakdown voltages and lower losses compared to Si power MISFETs. For this reason, SiC power MISFETs (SiC power devices) are attracting particular attention in the field of power-saving or environmentally friendly inverter technology.

[0003] Compared to Si power MISFETs, SiC power MISFETs can achieve a lower on-resistance at the same breakdown voltage. This is because silicon carbide (SiC) has a dielectric breakdown field strength approximately seven times greater than that of silicon (Si), allowing the epitaxial layer that serves as the drift layer to be made thinner.

[0004] A power semiconductor device chip has a structure in which a plurality of MISFET unit cells are arranged in a matrix in a plan view. Patent Document 1 (JP Patent Publication No. 2020-512682) describes a configuration in which a plurality of power MOSFET cells having gate trenches are arranged in an active region. Here, a termination trench is arranged in a termination region surrounding the active region. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Special Publication No. 2020-512682 Summary of the Invention [Problem to be solved by the invention]

[0006] In SiC power devices, the depth of ion implantation tends to be deep in order to alleviate the electric field in the insulating film. Deep ion implantation requires a thick resist mask, which means that the sides of the resist pattern tend to be inclined near the end of the area exposed using the resist mask. As a result, the shape of the impurity region (semiconductor region) in the SiC substrate becomes distorted, causing problems with reduced chip performance.

[0007] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0008] A brief outline of a representative embodiment of the present invention will be described below.

[0009] A power semiconductor device according to one embodiment includes first and second unit cells and a plurality of termination cells that are periodically arranged in a first direction and a second direction that are orthogonal to each other. Here, the first and second unit cells are alternately arranged in the first direction, and the plurality of termination cells include a first termination cell, a second termination cell, a third termination cell, a fourth termination cell, and a fifth termination cell. The number of periodic arrangements of the first and second unit cells in the second direction varies depending on the repeating period coordinates of the first and second unit cells in the first direction, and each of the periodically arranged first and second unit cells is adjacent to one of the plurality of termination cells at the extreme ends of the periodic arrangement in the first and second directions, and a region in which each of the plurality of termination cells exists has electrical characteristics different from those of the first and second unit cells.

[0010] A cell data generation system according to one embodiment generates placement data for periodically placing first and second unit cells in a first direction and a second direction perpendicular to each other, and generates placement data for a plurality of termination cells. Here, the first and second unit cells are alternately placed in the first direction, and the plurality of termination cells include a first termination cell, a second termination cell, a third termination cell, a fourth termination cell, and a fifth termination cell, and the number of periodic arrangements of the first and second unit cells in the second direction varies depending on the repeating period coordinates of the first and second unit cells in the first direction. Each of the periodically placed first and second unit cells is adjacent to one of the plurality of termination cells at the extreme end of the periodic arrangement in the first and second directions, and the region in which each of the plurality of termination cells exists has electrical characteristics different from those of the first and second unit cells. Effect of the Invention

[0011] The effects obtained by the representative inventions among those disclosed in this application will be briefly described as follows.

[0012] According to the present invention, the performance of a power semiconductor device can be improved. [Brief description of the drawings]

[0013] [Figure 1] 4 is a flow chart showing the operation of the cell data generation system according to the first embodiment. [Diagram 2] 1 is a plan view showing a power semiconductor device according to a first embodiment. [Diagram 3] FIG. 3 is a cross-sectional view taken along line AA in FIG. [Figure 4] 3 is a cross-sectional view for explaining the operation of the cell data generation system according to the first embodiment. FIG. [Diagram 5] FIG. 5 is a cross-sectional view illustrating the operation of the cell data generating system subsequent to FIG. 4. [Figure 6] FIG. 6 is a cross-sectional view illustrating the operation of the cell data generating system subsequent to FIG. 5. [Figure 7] 1 is a plan view showing a power semiconductor device according to a first embodiment. [Figure 8] FIG. 8 is a cross-sectional view taken along line BB in FIG. [Figure 9] 8 is a cross-sectional view taken along line CC in FIG. 7. [Figure 10] 1 is a plan view showing a power semiconductor device according to a first embodiment. [Figure 11] FIG. 11 is a cross-sectional view taken along line DD in FIG. [Figure 12] FIG. 11 is a cross-sectional view taken along line EE in FIG. [Figure 13] FIG. 11 is a plan view showing a power semiconductor device according to Comparative Example 4. [Figure 14] 1 is a plan view showing a power semiconductor device according to a first embodiment. [Figure 15] 15 is a cross-sectional view taken along the line FF in FIG. 14. [Figure 16] 15 is a cross-sectional view taken along line GG in FIG. 14. [Figure 17] FIG. 11 is a plan view showing a power semiconductor device according to a second embodiment. [Figure 18] 13 is a flow chart showing the operation of the cell data generation system according to the second embodiment. [Figure 19] FIG. 11 is a plan view showing a power semiconductor device according to a third embodiment. [Figure 20] 20 is a cross-sectional view taken along line HH in FIG. 19. [Figure 21] FIG. 13 is a cross-sectional view explaining the operation of the cell data generation system according to the first modification of the third embodiment. [Figure 22] FIG. 22 is a cross-sectional view illustrating the operation of the cell data generating system subsequent to FIG. 21. [Figure 23] FIG. 23 is a cross-sectional view illustrating the operation of the cell data generating system subsequent to FIG. 22. [Figure 24] FIG. 13 is a cross-sectional view explaining the operation of the cell data generation system according to the second modification of the third embodiment. [Diagram 25] FIG. 25 is a cross-sectional view illustrating the operation of the cell data generating system subsequent to FIG. 24. [Figure 26] FIG. 26 is a cross-sectional view illustrating the operation of the cell data generating system subsequent to FIG. 25. [Figure 27] FIG. 2 is a cross-sectional view of a power semiconductor device according to Comparative Example 1. [Figure 28] FIG. 11 is a cross-sectional view of a power semiconductor device according to Comparative Example 2. [Figure 29] 11 is a partial plan view showing a power semiconductor device according to Comparative Example 3. [Diagram 30] 11 is a partial plan view showing a power semiconductor device according to Comparative Example 4. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, the embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, the same reference numerals are used for the members having the same functions, and the repeated explanations are omitted. In addition, in the following embodiments, the explanations of the same or similar parts are not repeated in principle, except when particularly necessary. In addition, in the drawings for explaining the embodiments, hatching may be used even in plan views or perspective views, etc., in order to make the configuration easier to understand. Furthermore, in the drawings for explaining the embodiments, hatching may be omitted in cross-sectional views in order to make the configuration easier to understand.

[0015] Also," - " and " + " is a code that indicates the relative impurity concentration of the conductivity type, n-type or p-type. For example, "n - ", "n", "n + The concentration of n-type impurities increases in this order.

[0016] In this application, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), which is a type of MISFET, will be described.

[0017] <Details of areas for improvement> Room for technical improvement of power semiconductor devices will be described below with reference to Figs. 27 to 30. Fig. 27 is a cross-sectional view of a power semiconductor device of Comparative Example 1, and Fig. 28 is a cross-sectional view of a power semiconductor device of Comparative Example 2. Fig. 29 shows a part of a plan view of a power semiconductor device of Comparative Example 3. Fig. 30 shows a part of a plan view of a power semiconductor device of Comparative Example 4.

[0018] A semiconductor region (impurity region, impurity-injected region) constituting a power semiconductor device is formed, for example, by injecting impurity ions into the main surface of a wafer, which is a semiconductor substrate, or into the back surface opposite to the main surface. The impurity ions are injected into the semiconductor substrate via a resist pattern made of a photoresist film, thereby implanting the impurity ions into desired positions in the semiconductor substrate. In the resist pattern formation process, a resist liquid that will become a photoresist film is applied onto the main surface of the semiconductor substrate, the photoresist film is exposed to light through a mask, and then the photoresist film is developed (ashed) to form a resist pattern having a desired pattern.

[0019] However, the optical periodicity is easily lost at the end of the range where the above-mentioned exposure is performed. One of the reasons for this is that the resist pattern is not large enough compared to the wavelength of the light used for exposure. In addition, spin coating is used when applying the resist solution, and if the developer stagnates, this can cause variations in the reactivity of the photoresist film with the developer. Due to these factors, the side of the resist pattern is likely to be inclined at the end of the exposure area.

[0020] Fig. 27 shows a cross-sectional view of Comparative Example 1 in which a guard region 4 is formed by injecting p-type impurities into the interior of a semiconductor substrate 1 via a photoresist film PR, which is a resist pattern. In Fig. 27, the outline of a trench 7 formed in the main surface of the semiconductor substrate 1 and positioned in the depth direction of the figure is shown by a dot-dash line. In the unit cell formation region, which is the central side of the exposure range, the photoresist film PR has side surfaces that are approximately perpendicular to the main surface of the semiconductor substrate 1. In contrast, at the edge of the exposure range (the left side of Fig. 27), the side surfaces of the photoresist film PR are inclined due to the above-mentioned reasons.

[0021] Guard region 4, which is a p-type semiconductor region, is formed directly below the opening of photoresist film PR. However, under the inclined photoresist film PR, ions are only partially decelerated during ion implantation, and as a result, guard region 4 is formed at a shallow position. This causes the shape of guard region 4 to be distorted. For the same reason, the shapes of the semiconductor region including body region 5, which is the channel formation region of the MOSFET, and trench 7 at the termination portion are also distorted.

[0022] In the semiconductor substrate 1 between the adjacent guard regions 4, a JFET (Junction Field Effect Transistor) region 6, which is an n-type impurity region, is formed. In the cross-sectional views of the present application including FIG. 27, the lower end of the JFET region 6 is indicated by a broken line. When ion implantation is performed using a photoresist film PR having an inclination as a mask, the width A of the JFET region 6 in the direction along the main surface of the semiconductor substrate 1 at the end portion may be widened, and the channel width B of the MOSFET may be shortened. In this case, a problem occurs in that the threshold value of the MOSFET constituting the power semiconductor device decreases. In SiC power devices, the depth of ion implantation tends to be deep in order to relax the electric field of the insulating film. A thick resist mask is required to perform deep ion implantation. For this reason, in the end portion of the region exposed using the resist mask, the side of the resist pattern is particularly likely to be inclined.

[0023] A power semiconductor device is a semiconductor chip with multiple MOSFET cells arranged in a matrix, and multiple such semiconductor chips are prepared and used in a parallel-connected state. The overall performance of a parallel-connected power semiconductor device is determined by the part of the multiple chips with the lowest performance. For this reason, it is necessary to improve the overall performance of the power semiconductor device by taking measures to prevent abnormalities in the above-mentioned termination parts.

[0024] As a method for this, there is a method of deactivating in advance the portions of the termination section where it is predicted that the shape of the semiconductor region is likely to be deformed. In other words, the pattern of the termination section is configured with a dummy pattern having characteristics different from those of the unit cells. Here, as shown in FIG. 28 as Comparative Example 2, in the termination section, n + The p-type semiconductor region extends to a position deeper than the source region 2. + The p-type semiconductor region 12 is formed. + The type semiconductor region 12 has a higher impurity concentration than the source region 2. As a result, the source region 2 does not exist at the end portion, and the threshold voltage increases significantly. As a result, the cells at the end portion do not operate as MOSFETs and are inactivated. In other words, even if the shapes of the guard region 4 and the trench 7 are deformed, adverse effects on the chip operation can be prevented. + The p-type semiconductor region 12 can be formed by introducing a p-type impurity (for example, Al (aluminum)) into the semiconductor substrate 1 by ion implantation.

[0025] Fig. 29 shows a planar layout of the power semiconductor device of Comparative Example 3, assuming that the exposure region is rectangular. In this case, unit cells (periodic cells) U1 constituting the power semiconductor device are periodically arranged in the X and Y directions. The X and Y directions in this application are directions along the main surface of the semiconductor substrate, and the Y direction is perpendicular to the X direction in a plan view. The Z direction is the thickness direction of the semiconductor substrate, and is a direction (vertical direction, depth direction) perpendicular to each of the X and Y directions. In Figs. 29 and 30, each of the terminal cells Xa and Ya is hatched to make it easier to understand the overlap between the terminal cells.

[0026] As shown in Fig. 29, when the overall planar shape of unit cells U1 arranged in a matrix is ​​rectangular, it is easy to manually create cell data for terminal cells Xa, Ya, and XY to be inactive. In this application, cell data refers to design information for cell placement (layout). Here, terminal cell Xa is placed adjacent to the terminal end of unit cell U1 arranged in the X direction, and terminal cell Ya is placed adjacent to the terminal end of unit cell U1 arranged in the Y direction. In addition, terminal cell XY is placed adjacent to the terminal end in the X direction of terminal cell Ya arranged in the X direction.

[0027] FIG. 30 shows a planar layout of a power semiconductor device of Comparative Example 4 in which the end of the exposure region is curved in plan view. The region shown in FIG. 30 is the periphery (e.g., corner) of the semiconductor chip, and the contour of the periphery of the exposure region is shown by a curve. Here, the cost of the wafer of the SiC substrate is high, so there is a reason to want to make the most of the area. For this reason, it is desirable to arrange unit cells U1 as much as possible in the non-rectangular region of the chip periphery. Therefore, the overall shape of the unit cells U1 arranged in a matrix in the X and Y directions is not rectangular, and at least the corners have a shape with curvature. In other words, the number of unit cells U1 is non-uniform depending on the column and is also non-uniform depending on the row. In this case, the end cells Xa, Ya, and XY interfere with each other, so manual generation of cell data requires a very complicated operation.

[0028] That is, when multiple unit cells U1 are arranged in a rectangular region as shown in Fig. 29, it is sufficient to prepare up to eight types of terminal cells Xa, Ya, and XY and arrange these terminal cells Xa, Ya, and XY repeatedly, and the generation of cell data is simple and easy. On the other hand, when the outline of the arrangement region of unit cell U1 is approximately curved as shown in Fig. 30, in any region near this curved portion, the number of unit cells U1 adjacent to terminal cells Xa, Ya, and XY is not constant, so a large number of terminal patterns must be assumed.

[0029] Manually creating cell data for terminal cells in non-rectangular areas requires a huge amount of work, is prone to errors, and is costly. For this reason, a method is needed to mechanically place terminal cells independent of the chip shape and device structure. In other words, there is room for improvement in realizing a cell data generation system that can automatically generate cell data with a minimum number of cell types that can operate properly even when multiple terminal cells overlap or interfere with each other, and to use this to form power semiconductor devices.

[0030] Therefore, in the following embodiment, some measures are taken to solve the above-mentioned room for improvement. The technical idea of ​​the present embodiment 1 in which these measures are taken will be described below.

[0031] (Embodiment 1) Fig. 1 is a flow diagram showing the operation of the cell data generation system of the present embodiment. In the following, the operation of the cell data generation system of the present embodiment and the structure of the power semiconductor device will be described with reference to Fig. 1 and with reference to Figs. 2 to 12 and 14.

[0032] First, the cell data generation system generates cell data for unit cells arranged in a matrix in the X and Y directions (step S1 in FIG. 1). Next, the cell data generation system generates cell data for an X-terminal cell located at the terminal end of the unit cell in the X direction (step S2 in FIG. 1). Note that in the plan views of the present application, including FIG. 2, illustration of structures on the semiconductor substrate including inside the trench, that is, gate electrodes, gate wiring, interlayer insulating film, and source wiring, is omitted. Also, in these plan views, the body region, source region, and n-type semiconductor region (current diffusion region) formed in the semiconductor substrate are not illustrated, and only guard regions 4, p + 1, only the type semiconductor region 12, the JFET region 6, the trench 7, and the gate insulating film 8a in the trench are shown. In each plan view, the guard region 4 is formed in the entire region that does not overlap with the JFET region 6.

[0033] In Figure 2, p +The area where the p-type semiconductor region 12 is formed is hatched. + In order to make it easier to understand where the p-type semiconductor region 12 is formed, the hatching overlaps the inside of the trench 7 and the gate insulating film 8a in the trench 7 in FIG. + Since the depth of the type semiconductor region 12 is shallower than that of the trench 7, + The type semiconductor region 12 is formed only outside the trench 7. In FIG. 2, the contours of the unit cells UR and UL are shown by solid lines, and the contours of the X-terminal cells XL and XR are shown by dashed lines. The contours of the Y-terminal cells YR and YL described later are shown by dashed lines, and the contour of the XY-terminal cell XY1L is shown by dashed lines. A cell external region OC exists in a region adjacent to the Y-terminal cells YR and YL and the XY-terminal cell XY1L, and on the opposite side to the unit cells UR and UL. A guard region 4 is formed in the semiconductor substrate 1 of the cell external region OC. Note that the lines showing the contours of each cell actually overlap each other, but in each plan view, some of the contours are separated from each other to make the drawings easier to understand.

[0034] The configuration of the unit cells will be described below. Here, active regions operable as switching elements are arranged as unit cells. As shown in FIG. 2, the unit cells UR and the unit cells UL are arranged alternately in the X direction. The unit cells UR and the unit cells UL are adjacent to each other and have a line-symmetric structure with respect to the boundary between them. However, the structures of the unit cells UR and the unit cells UL do not have to be line-symmetric. The power semiconductor device of this embodiment has a semiconductor substrate 1 as shown in FIG. 3. The semiconductor substrate 1 has an n-type semiconductor region (drift layer).

[0035] A plurality of trenches 7 are formed in the main surface of the semiconductor substrate 1, the trenches 7 reaching a depth of the semiconductor substrate 1. The trenches 7 extend in the X direction, and a plurality of trenches 7 are arranged in the Y direction and the X direction. +In the MOSFET of the present embodiment, a source region 2 which is a fin-type semiconductor region is formed. The source region 2 extends in the Y direction and is formed at a depth shallower than that of the trench 7. The source region 2 is located between the trenches 7 adjacent to each other in the X direction and is separated from the trenches 7. The semiconductor region which is the semiconductor substrate 1 between the trenches 7 adjacent to each other in the Y direction constitutes a fin which extends in the X direction and has a small thickness in the Y direction. The MOSFET of the present embodiment is also called a FIN-type MOSFET because a channel is formed in the fin.

[0036] An n-type semiconductor region (current diffusion layer) 3 is formed at a predetermined depth on the main surface of the semiconductor substrate 1, extending between the source regions 2 adjacent to each other in the X direction. That is, the n-type semiconductor region 3 is in contact with the source region 2. The depth of the n-type semiconductor region 3 is shallower than the depth of the source region 2. A p-type guard region 4 is formed in the semiconductor substrate 1, extending between the trenches 7 adjacent to each other in the X direction. The guard region 4 is in continuous contact with the lower and side surfaces of the source region 2 and the lower surface of the n-type semiconductor region 3, and covers the lower end of the source region 2. The depth of the guard region 4 is deeper than the depth of the trench 7, and the lower end of the guard region 4 is located midway through the semiconductor substrate 1. The end of the guard region 4 in the X direction is adjacent to a part of the trench 7 in the Y direction.

[0037] Between the trenches 7 adjacent to each other in the Y direction, two guard regions 4 are formed at a distance from each other, and a body region 5 in which a channel of a MOSFET is formed is formed in the semiconductor substrate 1 between the guard regions 4. The upper end of the body region 5 is in contact with the lower end of the n-type semiconductor region 3, and the depth of the body region 5 is shallower than that of the trench 7. The region between the lower end of the body region 5 and the lower end of the trench 7, which is sandwiched between the guard regions 4 adjacent to each other in the X direction, constitutes a JFET region 6. The JFET region 6 is an n-type semiconductor region sandwiched between p-type semiconductor regions, and has a lower n-type impurity concentration than any of the n-type semiconductor region 3, the source region 2, and the drain region 13 described later. The n-type impurity concentration of the JFET region may be higher than the n-type impurity concentration of the semiconductor substrate (drift layer) 1, or may be the same as the n-type impurity concentration of the semiconductor substrate (drift layer) 1.

[0038] In a fin, which is the semiconductor substrate 1 adjacent to the side surface of the trench 7 in the Y direction, an n-type semiconductor region 3, a body region 5, and a JFET region 6 are arranged in this order from the main surface side to the back surface side of the semiconductor substrate 1.

[0039] The back surface of the semiconductor substrate 1 opposite to the main surface is provided with a predetermined depth of n + A drain region 13, which is a type semiconductor region, is formed. The upper end of the drain region 13 and the lower end of the guard region 4 are spaced apart from each other. A drain electrode 14, which includes, for example, Au (gold), is formed so as to cover the back surface of the semiconductor substrate 1. A gate electrode 9 is embedded in the trench 7 via a gate insulating film 8a (see FIG. 2). An interlayer insulating film 8, which is mainly made of, for example, a silicon oxide film, is formed on the semiconductor substrate 1. A gate electrode 9 formed directly above the trench 7 and a gate wiring 10 formed on the gate electrode 9 and integrated with the gate electrode 9 are formed in the interlayer insulating film 8. The gate wiring 10 extends in the Y direction so as to overlap with a plurality of trenches 7, and is connected to a plurality of gate electrodes 9. In the cross-sectional views other than FIG. 3, the drain region 13 and the drain electrode 14 are omitted from illustration.

[0040] A source wiring (source contact plug, conductive connection part) 11 made mainly of, for example, aluminum (Al) is formed in a through hole penetrating the interlayer insulating film 8 in the Z direction. The source wiring 11 extends in the Y direction and is connected to the source region 2 at its bottom. A silicide layer may be interposed between the source wiring 11 and the source region 2. The source region 2, the drain region 13, the gate electrode 9, and the body region 5 configure a MOSFET (trench MOSFET). Although not shown, a source pad connected to each source wiring 11 is formed on the interlayer insulating film 8. When the MOSFET is conductive, electrons supplied from the source wiring 11 flow to the drain region 13 and drain electrode 14 side through the source region 2, the n-type semiconductor region 3, the body region 5, and the JFET region 6 in this order.

[0041] The body region 5 adjacent to the trench 7 in the Y direction configures a trench MOSFET structure. The drain of the trench MOSFET structure is connected to the source of the JFET region 6. In other words, the end (lower end) of the body region 5 on the drain side is connected to the end (upper end) of the JFET region 6 on the source side.

[0042] As shown in Fig. 2, the JFET region 6, which is the active region of the unit cells UR and UL, extends in the Y direction so as to overlap with multiple trenches 7 aligned in the Y direction. Although not shown in Fig. 2, multiple unit cells UR and UL are aligned in the X direction and alternately formed at the same period in the Y direction. Each of the unit cells UR aligned in the Y direction shares the source region 2, n-type semiconductor region 3, guard region 4, and JFET region 6 extending in the Y direction.

[0043] Next, the X-terminal cell XL located at the end of the unit cells UR and UL arranged in the X-direction will be described. Each terminal cell has a part of the structure in common with the unit cells UR and UL, so in explaining the structure of the terminal cell, differences from the structure of the unit cells UR and UL will be explained. As described above with reference to FIG. 29, in order to suppress the effect of pattern collapse at the end of the cell arrangement, a JFET region 6 and a trench 7 similar to the JFET region 6 formed by the unit cells UR and UL are created at the terminal, and P + The X-terminal cell XL is deactivated by overlaying the n-type semiconductor region 12 on the JFET region 6 or the MOSFET structure, which may be, for example, the n-type semiconductor region 3 and the body region 5.

[0044] 2 and 3, the X-terminal cell XL has guard regions 4, body regions 5, JFET regions 6, trenches 7, gate insulating films 8a, gate electrodes 9, gate wiring 10, and source wiring 11, which are formed in the same period as the unit cells UR and UL. + A P type semiconductor region 12 is formed. + The depth of the type semiconductor region 12 is, for example, the same as or greater than the depth of the source region 2 , and is shallower than the depth of the body region 5 here, but may be deeper than the depth of the body region 5 .

[0045] In plan view, P + The P type semiconductor region 12 is formed in the entire X-terminal cell XL except for the end portion that contacts the unit cell UR in the X direction. That is, the X-terminal cell XL is separated from the body region 5, JFET region 6, and trench 7 shared with the unit cell UR that contacts it in the X direction, and is located at a position that overlaps with other body regions 5 and JFET regions 6 in a plan view. + In this way, the width of the JFET region 6 formed at the end of the unit cell UR (hereinafter, sometimes referred to as the JFET width) is prevented from becoming small. The source wiring 11 formed in the X-terminal cell XL is + Located directly above the P-type semiconductor region 12 +The semiconductor region 12 is electrically connected to the insulating layer 11 .

[0046] In the X-terminated cell XL, P + By disposing the type semiconductor region 12 on the JFET region 6, the current path disappears, and the channel threshold is significantly increased so that the MOSFET does not turn on. Also, the absence of the source region 2 of the MOSFET inhibits current conduction in the cell.

[0047] Although only one period of the inactive JFET region 6 and the X-termination cell XL having a MOSFET structure is shown in FIG. 3, they may be arranged in two or more periods in the X direction. In that case, an X-termination cell XR having a structure that is linearly symmetrical to the X-termination cell XL is arranged next to the X-termination cell XL. The number of periods of the JFET region 6 and the MOSFET structure may be different from each other. However, the more X-termination cells there are, the smaller the area of ​​the active cells will be, and the chip performance of the power semiconductor device will decrease. The range in which the pattern collapse occurs is not constant because it depends on the process conditions, but it is not uncommon for the pattern collapse to occur in two or more periods. Therefore, it is necessary to select the optimal number of periodic arrangements by considering the required active area and the effect of the pattern collapse.

[0048] Next, a specific procedure for generating cell data for a unit cell in step S1 of Fig. 1 and a specific procedure for generating cell data for an X-terminal cell in step S2 will be described with reference to Fig. 4 to Fig. 6. Fig. 4 to Fig. 6 show the process for generating cell data (layout information) and do not show the process for manufacturing an actual power semiconductor device.

[0049] First, as shown in FIG. 4, unit cells UR and UL are arranged alternately (step S1 in FIG. 1). At this time, the number of periods of the inactive cells and the number of cells terminating the JFET region 6 are arranged. In other words, the same cell data as the unit cells UR and UL are repeatedly arranged in the region that will become the X-terminal cell. In other words, in the X-terminal cell, regions corresponding to the unit cells UL, UR, and UL are arranged in the X direction. Hereinafter, the parts corresponding to the unit cells arranged in the X direction in the terminal cell will be referred to as the first cell X1, the second cell X2, and the third cell X3, in that order, from the unit cells UR and UL side. Here, "in order from the unit cells UR and UL side" means "in order in the X direction from the center of the power semiconductor device (the center of the exposure region)."

[0050] Next, as shown in FIG. 5, in the first cell X1, the second cell X2, and the third cell X3, a p + In this case, the n-type semiconductor region having a higher concentration than the n-type semiconductor region 12 is removed. That is, the source region 2 is excluded from the cell data of the first cell X1, the second cell X2, and the third cell X3. That is, the plan to form the source region 2 in the first cell X1, the second cell X2, and the third cell X3 is canceled.

[0051] Next, as shown in Figure 6, + The p-type semiconductor region 12 is disposed so as to cover at least the entire JFET region 6 formed in the terminal cell. In other words, the p-type semiconductor region 12 is disposed so as to overlap the body region 5 or the JFET region 6, which is a MOSFET structure, in a plan view. + In the case where the source wiring 11 of the first cell X1, the second cell X2, or the third cell X3 is defined to straddle the unit cells, the guard region 4, the P + The type semiconductor region 12 and the contact mask are extended, whereby cell data for the X-terminal cell XL (XR) composed of the first cell X1, the second cell X2, and the third cell X3 can be generated.

[0052] Here, in FIG. 5, + The n-type semiconductor region having a higher concentration than the n-type semiconductor region 12 is removed. For example, the source region 2 is + If the source region 2 has a lower concentration than the type semiconductor region 12, it is possible to leave it without removing it. In that case, + By forming the p-type semiconductor region 12 so as to overlap the source region 2, the source region 2 becomes a p-type semiconductor region.

[0053] Next, the cell data generation system generates cell data for the Y terminal cell located at the terminal end of the unit cell in the Y direction (step S3 in FIG. 1). Since pattern collapse also occurs in the Y direction, the structure constituting the channel (trench 7, etc.) is arranged in the Y terminal cell for one or more periods, and p + The Y-terminal cell YR is disposed adjacent to the end of the unit cell UR aligned in the Y direction, and the Y-terminal cell YL is disposed adjacent to the end of the unit cell UL aligned in the Y direction. The planar layout shown in FIG. 7 is the same as the planar layout shown in FIG. 2.

[0054] Here, in a structure in which each of the unit cells UR and UL is expanded or contracted in the Y direction, objects other than the gate wiring 10 and the guard region 4 are cut off midway in the Y terminal direction YE. Next, the guard region 4 is placed up to a certain width from the Y terminal direction YE. Finally, p + By disposing the type semiconductor region 12 on the entire surface of the Y terminal cells YR, YL, it is possible to achieve isolation from the cell external region OC and inactivation of the terminal cells.

[0055] The above-mentioned constant width may be the entire surface of the Y termination cells YR and YL. This is because the collapse of the pattern of the JFET region 6 in the Y direction is generally on the safe operation side and is not important. On the other hand, the collapse of the trench 7 in the Y direction is on the dangerous operation side, such as a decrease in the threshold value, so it is necessary to ensure that it is inactivated.

[0056] As with the X-terminal cells XR and XL, the MOSFET structure (trench 7) in the Y-terminal cells YR and YL is shown in Fig. 7 as one period in the Y direction, but may be arranged in two or more periods. The number of periods can be determined independently of the extension width of the JFET region 6 to the Y-terminal cells YR and YL.

[0057] As shown in FIG. 7 to FIG. 9, in a plan view, the Y terminal cells YR and YL are entirely covered with p + A p-type semiconductor region 12 is formed in the Y terminal cells YR and YL. The Y terminal cells YR and YL each include a JFET region 6 extending from the adjacent unit cells UR and UL. In plan view, the Y terminal cells YR and YL each include a guard region 4 in the entire region other than the region in which the JFET region 6 is formed. In the Y terminal cells YR and YL, the trench 7 extends to the bottom end thereof and is covered with a p-type semiconductor region (p + The cell is inactivated by being covered by the type semiconductor region 12 and the guard region 4).

[0058] That is, the trench 7 is a dummy trench in which no channel is formed in the vicinity of the side surface thereof. Even if a channel is formed in the vicinity of the side surface of the trench 7, the channel will not be conductive.

[0059] That is, the Y terminal cells YR and YL have a structure in which the unit cells UR and UL are expanded and contracted in the Y direction, and elements other than the gate wiring 10 and the guard region 4 are terminated midway in the Y direction, and the JFET region 6 is blocked midway in the Y direction. + The semiconductor region 12 is disposed over the entire surfaces of the Y terminal cells YR and YL.

[0060] As one of the features of this embodiment, as described below, when generating placement data for a Y terminal cell, the cell data generation system places the Y terminal cell adjacent to the end of a unit cell that is periodically arranged in the Y direction only if the Y terminal cell does not overlap with an X terminal cell.

[0061] Next, the cell data generation system generates cell data for the XY terminal cell located at the terminal end of the X terminal cell in the Y direction (step S4 in FIG. 1). As shown in FIG. 10 to FIG. 12, the XY terminal cell XY1L can be generated by performing the same process on the X terminal cell XL as when creating the Y terminal cell YL. Although not shown, the XY terminal cell XY1R can be generated by performing the same process on the X terminal cell XR as when creating the Y terminal cell YR. Specifically, a MOSFET structure (trench 7, etc.) is placed, and p + It is sufficient to inactivate the entire XY termination cell in the type semiconductor region 12. The planar layout shown in Fig. 10 is the same as the planar layouts shown in Figs.

[0062] Here, the XY terminal cell XY1L will be described as an example, but the structure of the XY terminal cell XY1R is similar. The structure of the XY terminal cell XY1L has the same characteristics as the Y terminal cell YL. That is, in a plan view, the entire XY terminal cell XY1L is filled with p + A p-type semiconductor region 12 is formed in the XY termination cell XY1L. The XY termination cell XY1L also includes a JFET region 6 extending from the adjacent X termination cell XL side. In plan view, the XY termination cell XY1L includes a guard region 4 in the entire region other than the region in which the JFET region 6 is formed. In the XY termination cell XY1L, the trench 7 is formed to the bottom end of a p-type semiconductor region (p + The cell is inactivated by being covered by the type semiconductor region 12 and the guard region 4).

[0063] That is, the XY terminal cell XY1L has a structure in which the X terminal cell is expanded or contracted in the Y direction, but the elements other than the gate wiring 10 and the guard region 4 are terminated halfway in the Y direction, and the JFET region 6 is blocked halfway in the Y direction. + In the region where each of the XY terminal cells exists, p + By forming the type semiconductor region 12, the MOSFET structure has a higher threshold voltage than the unit cells UR and UL.

[0064] The operation of the cell data generation system described above can generate cell data without any problem when the unit cells are arranged in a rectangular area, as in Comparative Example 3 described with reference to FIG. 29. Even if cell data is generated without the above-mentioned condition as one of the features of this embodiment, that is, the condition that the Y-terminal cell is arranged adjacent to the terminal end of the unit cell only when it does not overlap with the X-terminal cell, there is no problem as long as the unit cells are arranged in a rectangular area. However, in that case, as in Comparative Example 4 described with reference to FIG. 30, in a power semiconductor device in which the terminal end of the exposure area is curved in a plan view, the following problem occurs. For this reason, it is necessary to add further conditions to the cell data generation method, including the above-mentioned condition as one of the features of this embodiment.

[0065] 13 shows a plan view of a power semiconductor device of Comparative Example 4. This power semiconductor device is formed according to a cell data generation system in which an X-terminal cell is arranged at an X-direction terminal portion of a unit cell, a Y-terminal cell is arranged at a Y-direction terminal portion of the unit cell, and an XY-terminal cell is arranged at a Y-direction terminal portion of the X-terminal cell. The area in which the unit cells UR and UL are arranged here has terminal portions that follow a curve in a plan view and is not a simple rectangle. For this reason, a part of the X-terminal cell XL arranged according to the cell data generation system overlaps with the Y-terminal cells YR and YL, and a part of the XY-terminal cell XY1L overlaps with a part of the X-terminal cell XL.

[0066] This overlapping part is p +Although the type semiconductor region 12 is inactive, various components overlap, so defects may occur. One example is the shape abnormality of the guard region 4 as shown in FIG. 13. In FIG. 13, the guard region 4 of the XY terminal cell XY1L and the Y terminal cell YR protrudes so as to divide the JFET region 6, which results in an isolated pattern 6a in the JFET region 6. There is no problem in operation even if the isolated pattern 6a is formed. However, when forming such a minute isolated pattern 6a, it is necessary to form a minute resist pattern on the semiconductor substrate 1. The resist pattern, which is a minute protrusion, is easily turned into particles by falling during the manufacturing process of the power semiconductor device, which causes a decrease in the yield in the manufacturing process.

[0067] Therefore, the inventors have noticed that the areas where cells may overlap are between the X terminal cell XL and the Y terminal cells YR and YL, and between the part corresponding to the unit cell UL that is placed first when creating the terminal cell and the part added for contact.The inventors have studied cell placement in an arbitrary area (arbitrary shape area) and have made it possible to solve the above problem by manufacturing a power semiconductor device using a cell data generation system described below.

[0068] Fig. 14 shows a plan view of the power semiconductor device of the present embodiment, Fig. 15 is a cross-sectional view taken along line FF in Fig. 14, and Fig. 16 is a cross-sectional view taken along line GG in Fig. 14.

[0069] If the X-terminal cell XL includes a first cell X1, a second cell X2, and a third cell X3 (see FIG. 6) in the same period as the unit cells UR and UL, in the order from the unit cell UR side adjacent in the X direction, the first cell X1 and the second cell X2 of the X-terminal cell XL are equivalent to the Y-terminal cells YR and YL in the cell data generation algorithm. Therefore, the Y-terminal cell does not need to be placed in the column where the X-terminal cell exists. That is, when generating cell data for the Y-terminal cell (step S3 in FIG. 1), the Y-terminal cell is placed adjacent to the terminal of the unit cell only if it does not overlap with the X-terminal cell, which is the condition described above as one of the features of this embodiment. By adopting such a placement, the overlap between the Y-terminal cell and the X-terminal cell can be eliminated.

[0070] In addition, in terms of the generation algorithm, the first cell X1 of the XY termination cell XY1L differs from the unit cell UL only in that the JFET region 6 is blocked, that is, the JFET region 6 terminates in the Y direction. Therefore, when placing an XY termination cell at a position adjacent to the Y-direction termination portion of a specific X termination cell, if there is another X termination cell in the same row of the column adjacent to that position, an XY termination cell for any region XY2L created by removing the guard region 4 in the first cell X1 at the end on the unit cell UR side is placed as an XY termination cell having a different structure from the XY termination cell XY1L (step S5 in FIG. 1).

[0071] In other words, the XY termination cell XY1L is placed adjacent to the terminal end in the Y direction of the X termination cell XL only when the X termination cell XL is not placed in an adjacent position in the X direction. The XY termination cell XY2L for the arbitrary region is placed adjacent to the terminal end in the Y direction of the X termination cell XL when the X termination cell XL is placed in an adjacent position in the X direction. This prevents the isolated pattern 6a from being generated in the JFET region 6 as shown in FIG.

[0072] The XY termination cell XY2L for an arbitrary region has a structure in which the elements other than the gate wiring 10 and the guard region 4 are terminated halfway in the Y direction, and the JFET region 6 is blocked halfway in the Y direction, in contrast to the structure of a cell in which the X termination cell is expanded or contracted in the Y direction. + A type semiconductor region 12 is disposed over the entire surface of the XY terminal cell XY2L for an arbitrary region, and the guard region 4 is removed in the first cell X1 at the end on the unit cell UR side.

[0073] 14 to 16, the trenches formed in the termination cells, such as the Y termination cells YR and YL, the XY termination cell XY1L, and the XY termination cell XY2L for an arbitrary region, are spaced apart from the JFET region 6. That is, in any of the termination cells, there is a trench that is not connected to the JFET region 6. This prevents the trench MOSFET structure adjacent to the deformed trench from operating and the threshold voltage of the MOSFET from decreasing.

[0074] <Effects of the embodiment> As described above, the cell data generation system of this embodiment generates placement data for periodically placing unit cells UR and UL in the X and Y directions (step S1 in FIG. 1), and generates placement data for a plurality of terminal cells (steps S2 to S5 in FIG. 1). In the X direction, the unit cells UR and UL are alternately placed, and the plurality of terminal cells include at least an X terminal cell XL (first terminal cell), a Y terminal cell YR (second terminal cell), a Y terminal cell YL (third terminal cell), an XL terminal cell XL1L (fourth terminal cell), and an XL terminal cell XL2L (fifth terminal cell) for an arbitrary region.

[0075] The number of periodic arrangements of the unit cells UR, UL in the Y direction varies depending on the repeating period coordinates of the unit cells UR, UL in the X direction, and each of the periodically arranged unit cells UR, UL is adjacent to one of a plurality of terminal cells at the extreme end of the periodic arrangement in the X direction and the Y direction, respectively. In the region where each of the plurality of terminal cells exists, the terminal cells have electrical characteristics different from those of the first unit cell and the second unit cell.

[0076] The cell data generation system operates as follows, according to the flow shown in Fig. 1. That is, in step S1, the cell data generation system periodically places unit cells UR and UL.

[0077] In step S2, the cell data generation system places an X-terminal cell XL or XR connected to the terminal end of the unit cells UR and UL in the X direction.

[0078] In step S3, the cell data generation system places the Y terminal cell YR at a position adjacent to the end of the unit cell UR periodically arranged in the Y direction only if the Y terminal cell YR does not overlap with the X terminal cells XL, XR. Similarly, the cell data generation system places the Y terminal cell YL at a position adjacent to the end of the unit cell UL periodically arranged in the Y direction only if the Y terminal cell YR does not overlap with the X terminal cells XL, XR.

[0079] In step S4, the cell data generation system places an XY terminal cell XY1L or XY1R at a position adjacent to the terminal end in the Y direction of the X terminal cell XL or XR only if an X terminal cell XL is not placed at an adjacent position in the X direction.

[0080] In step S5, when the X-terminal cell XL is placed at an adjacent position in the X-direction, the cell data generation system places the XY-terminal cell XY2L or XY2R at a position adjacent to the terminal end in the Y direction of the X-terminal cell XL or XR.

[0081] The power semiconductor device of this embodiment is equivalent to the structure generated by the above-mentioned cell data generation system.

[0082] By using the X-terminator cell, Y-terminator cell, XY-terminator cell, and XY-terminator cell for any region created and placed as described above, automatic cell placement including the terminator structure can be performed for any chip shape. In other words, the terminator cell can be mechanically placed regardless of the chip shape and device structure. A cell data generation system can be realized that can automatically generate cell data with a minimum number of cell types that can operate appropriately even when multiple terminator cells overlap or interfere with each other, and this can be used to form a power semiconductor device, eliminating the room for improvement mentioned above.

[0083] That is, by preventing abnormalities at the termination of the power semiconductor device, the overall performance of the power semiconductor device can be improved. Also, a decrease in yield caused by the presence of isolated resist patterns as described with reference to FIG. 13 can be prevented. Also, since the cell data can be generated automatically, an increase in manufacturing costs due to manual generation of cell data can be prevented, and the occurrence of manufacturing errors can be prevented.

[0084] (Embodiment 2) In the first embodiment, it has been described that cell termination can be realized by the X termination cell, the Y termination cell, the XY termination cell, and the XY termination cell for any region. In the present embodiment, a further simplified algorithm that does not require the Y termination cells YL and YR and the XY termination cell XY1L will be described.

[0085] In the first embodiment, the Y terminal cell is arranged in a column where there is no XY terminal cell for any area, but all of these Y terminal cells can be replaced with XY terminal cells for any area. In this case, as shown in FIG. 17, the first cell and the third cell overlap each other as XY terminal cells for any area adjacent in the X direction. The difference between these two cells is that the guard area 4 is removed in the first cell. When the first cell overlaps with the third cell, this overlapping part has the same value as the Y terminal cell YL. On the other hand, the second cell has the same value as the Y terminal cell YR, so the same structure as when the Y terminal cells YR and YL are arranged side by side is generated. Therefore, the Y terminal cell is not necessary.

[0086] Furthermore, in embodiment 1, when an XY termination cell for an arbitrary area is used in an XY termination cell adjacent to a Y termination cell, there was a problem that the JFET width in the first cell becomes narrower. However, this is also solved by overlapping with the third cell, so the XY termination cell is also unnecessary.

[0087] In addition, the XY terminal cell XY2L for an arbitrary area can overlap with the XY terminal cell XY2L for an arbitrary area, and by overlapping and placing the Y terminal cell in the entire area where it should have been placed, it is possible to completely place the arbitrary area from one end to the other end in the X direction.

[0088] As described above, in this embodiment, the Y terminal cell and the XY terminal cell have a structure equivalent to the XY terminal cell for an arbitrary region. Therefore, as shown in Fig. 18, in the cell data generation system of this embodiment, similar to steps S1 and S2 in Fig. 1, after placing the unit cell and the X terminal cell in steps S11 and S12, the XY terminal cell for an arbitrary region is placed (step S13), thereby almost completing the generation of cell data. In step S13, the XY terminal cell for an arbitrary region is placed at a position adjacent to the end in the Y direction of each of the unit cell and the X terminal cell.

[0089] (Embodiment 3) In the first and second embodiments, the JFET width is constant in the termination cells arranged in the X and Y directions. +In the conventional method, the JFET region is used to make the cells completely inactive. However, even if the cells have a perfect JFET width without pattern collapse, the cells at the end of the active region do not share the current path of the epitaxial layer with other cells, so a larger current flows through them. Therefore, it is also effective to gradually narrow the JFET width toward the end of the power semiconductor device without making the JFET region of the end cell completely inactive.

[0090] Figures 19 and 20 show plan and cross-sectional views, respectively, of a case where one narrow JFET region is arranged in a terminal cell. Figure 20 shows a cross-sectional view taken along line HH in Figure 19. As shown in Figure 19, the width of the JFET region 6 gradually narrows not only in the X direction but also in the Y direction as it approaches the terminal portion.

[0091] Two or more JFET regions 6 may be arranged in each termination cell in the X direction, and different JFET widths may be adopted for each. In addition, when the MOSFET structure has a lateral current flow, it is also effective to use a MOSFET structure in which the channel length gradually increases toward the termination of the power semiconductor device. That is, the X termination cell XL of this embodiment has a different JFET width or a different channel length from the unit cells UR and UL. Specifically, the X termination cell XL has a narrower JFET width or a longer channel length in the X direction as it approaches the termination of the power semiconductor device in comparison with the unit cells UR and UL.

[0092] In this embodiment, the JFET width becomes narrower as it approaches the terminal end, and therefore the current is dispersed, so that, for example, among a plurality of unit cells arranged in a row, it is possible to prevent heat from concentrating on the unit cells on the terminal end side.

[0093] In this embodiment, as in the second embodiment, the description has been given using a diagram in which only the X terminal cell and the XY terminal cell for an arbitrary area are arranged as terminal cells. However, as in the first embodiment, the X terminal cell, the Y terminal cell, the XY terminal cell, and the XY terminal cell for an arbitrary area may be arranged.

[0094] <Variation 1> The above first to third embodiments can also be applied to a case where the semiconductor element is a DMOSFET (Double-Diffused MOSFET). In the case of a DMOSFET, the method of the first to third embodiments can be used to automatically create a structure having an inactive cell at the end.

[0095] As shown in Fig. 21, the DMOSFET includes a p-type semiconductor region 4a formed partway down from the main surface of an n-type semiconductor substrate 1, and a source region 2 formed in the p-type semiconductor region 4a partway down from the main surface of the n-type semiconductor substrate 1 to the depth of the p-type semiconductor region 4a. Although not shown, a drain region 13 and a drain electrode 14 are formed on the back surface of the semiconductor substrate, similar to the MOSFET shown in Fig. 3. Here, no trench is formed, and a gate electrode 9 is formed on the flat main surface of the semiconductor substrate 1 via a gate insulating film (interlayer insulating film 8).

[0096] 21, electrons supplied from source wiring 11 pass through source region 2, p-type semiconductor region 4a, and semiconductor substrate 1 in this order, and flow toward drain region 13 and drain electrode 14. p-type semiconductor region 4a is a semiconductor region corresponding to guard region 4 and body region 5 described in the first embodiment. A channel is formed in p-type semiconductor region 4a sandwiched between source region 2 and semiconductor substrate 1 near the main surface of semiconductor substrate 1.

[0097] The procedure for arranging the unit cells UR, UL and the X-terminal cell XL (generating cell data) in steps S1 and S2 in Fig. 1 is similar to the steps described with reference to Fig. 4 to Fig. 6. That is, first, the unit cells UR and UL are arranged alternately as shown in Fig. 21 (step S1 in Fig. 1).

[0098] Next, as shown in FIG. 22, in the first cell X1, the second cell X2, and the third cell X3, a p-type semiconductor region 4a is electrically located closer to the source side than the channel (p-type semiconductor region 4a) and is to be formed in a process described later. + In this case, the n-type semiconductor region having a higher concentration than the n-type semiconductor region 12 is removed. That is, the source region 2 is excluded from the cell data of the first cell X1, the second cell X2, and the third cell X3. That is, the plan to form the source region 2 in the first cell X1, the second cell X2, and the third cell X3 is canceled.

[0099] Next, as shown in Figure 23, + The p-type semiconductor region 12 is disposed so as to cover at least the entire surface of the semiconductor substrate 1 sandwiched between adjacent p-type semiconductor regions 4a in the terminal cell. This makes it possible to generate cell data for the X terminal cell XL (XR) composed of the first cell X1, the second cell X2, and the third cell X3.

[0100] <Variation 2> The above-mentioned first to third embodiments can also be applied to a special trench MOSFET in which the source region is formed in a deep region relative to the channel and the drain region is present on the main surface side of the semiconductor substrate relative to the channel, because the operation of electrically excluding the source side region from the MOSFET structure can reliably inactivate the operation of the MOSFET.

[0101] As shown in Fig. 24, the trench MOSFET of this modification includes a p-type semiconductor region 4a formed from the main surface of an n-type semiconductor substrate 1 to an intermediate depth, and a source region 2 formed in the p-type semiconductor region 4a from the main surface of the n-type semiconductor substrate 1 to an intermediate depth of the p-type semiconductor region 4a. A plurality of trenches 7 deeper than the source region 2 and shallower than the p-type semiconductor region 4a are formed side by side in the X and Y directions in the main surface of the semiconductor substrate 1. Although not shown, a drain region 13 and a drain electrode 14 are formed on the back surface of the semiconductor substrate, similar to the MOSFET shown in Fig. 3. A gate electrode 9 is embedded in the trench 7 via a gate insulating film (not shown).

[0102] A part of the lower end of the source region 2 protrudes in the X direction and is adjacent to the trench 7 in the Y direction. An n-type semiconductor region 3 is formed from the main surface of the semiconductor substrate 1 to a predetermined depth. The n-type semiconductor region 3 is adjacent to the trench 7 in the Y direction and is formed directly above the p-type semiconductor region 4a in the X direction. The n-type semiconductor region 3 is formed directly above the lower end of the source region 2 protruding in the X direction, with the p-type semiconductor region 4a interposed therebetween. In the X direction, the n-type semiconductor region 3 and the source region 2 are separated from each other via the p-type semiconductor region 4a. The n-type semiconductor region 3 is formed directly above the semiconductor substrate 1 between the p-type semiconductor regions 4a adjacent to each other in the X direction.

[0103] When the trench MOSFET of this modification is conductive, electrons supplied from the source wiring 11 flow through the source region 2, the p-type semiconductor region 4a, the n-type semiconductor region 3, and the semiconductor substrate 1 in this order toward the drain region 13 and the drain electrode 14, as shown by the arrows in Fig. 24. A channel is formed in the p-type semiconductor region 4a between the lower end of the source region 2 protruding in the X direction and the n-type semiconductor region 3 directly above it. The n-type semiconductor region 3 is electrically connected to the drain region 13 and the drain electrode 14 via the semiconductor substrate 1. In this way, the drain (n-type semiconductor region 3) is located on the main surface side of the semiconductor substrate 1 with respect to the channel.

[0104] The procedure for arranging the unit cells UR, UL and the X-terminal cell XL (generating cell data) in steps S1 and S2 in Fig. 1 is similar to the steps described with reference to Fig. 4 to Fig. 6. That is, first, the unit cells UR and UL are arranged alternately as shown in Fig. 24 (step S1 in Fig. 1).

[0105] Next, as shown in FIG. 25, in the first cell X1, the second cell X2, and the third cell X3 as a whole, a p-type semiconductor region 4a is formed on the source side electrically from the channel (p-type semiconductor region 4a) in a process to be described later. +In this case, the n-type semiconductor region having a higher concentration than the n-type semiconductor region 12 is removed. That is, the source region 2 is excluded from the cell data of the first cell X1, the second cell X2, and the third cell X3. That is, the plan to form the source region 2 in the first cell X1, the second cell X2, and the third cell X3 is canceled.

[0106] Next, as shown in Figure 26, + The p-type semiconductor region 12 is disposed so as to cover at least the entire surface of the semiconductor substrate 1 sandwiched between adjacent p-type semiconductor regions 4a in the terminal cell. This makes it possible to generate cell data for the X terminal cell XL (XR) composed of the first cell X1, the second cell X2, and the third cell X3.

[0107] The invention made by the present inventors has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention.

[0108] For example, the material, conductivity type, and manufacturing conditions of each part are not limited to those described in the above-mentioned embodiments, and it goes without saying that many modifications are possible. Here, for convenience of explanation, the conductivity types of the semiconductor substrate and the semiconductor film are fixed, but they are not limited to the conductivity types described in the above-mentioned embodiments. That is, in each embodiment and each modification, an n-type MOSFET is described, but a p-type MOSFET in which the conductivity type of each semiconductor region is inverted can also achieve the same effects as the above-mentioned embodiments and each modification. [Explanation of symbols]

[0109] 1. Semiconductor substrate 2 Source Area 3 n-type semiconductor region 4 Guard Area 4a p-type semiconductor region 5. Body Region 6 JFET area 6a Isolated Pattern 7. Trench 8 Interlayer insulating film 8a Gate insulating film 9 Gate electrode 10 Gate wiring 11 Source wiring 12 pages + Semiconductor area 13 Drain Region 14 Drain electrode U1, UL, UR unit cells X1 1st cell X2 Second cell X3 3rd cell XL, XR X-Terminated Cell XL1L, XL2L XL termination cells XY1L, XY1R XY termination cell XY2L, XY2R XY termination cells YL, YR Y-Terminated Cell

Claims

1. a first unit cell and a second unit cell that are periodically arranged in a first direction and a second direction that are perpendicular to each other; A plurality of termination cells; having the first unit cells and the second unit cells are arranged alternately in the first direction; the plurality of termination cells includes a first termination cell, a second termination cell, a third termination cell, a fourth termination cell, and a fifth termination cell; the number of periods of the first unit cell and the second unit cell in the second direction varies depending on a repeating period coordinate of the first unit cell and the second unit cell in the first direction; each of the first unit cell and the second unit cell that are periodically arranged is adjacent to any one of the plurality of terminal cells at an end of the periodic arrangement in each of the first direction and the second direction; A power semiconductor device, wherein a region in which each of the plurality of termination cells exists has electrical characteristics different from the first unit cell and the second unit cell.

2. 2. The power semiconductor device according to claim 1, each of the first unit cell and the second unit cell has a MOSFET structure and a JFET region; a drain of the MOSFET structure is connected to a source of the JFET region; a MOSFET structure having a higher threshold voltage than the first unit cell and the second unit cell in a region where each of the plurality of termination cells exists;

3. 2. The power semiconductor device according to claim 1, each of the first unit cell and the second unit cell has a trench MOSFET structure and a JFET region; a drain of the trench MOSFET structure is connected to a source of the JFET region; A power semiconductor device, wherein in any of the plurality of termination cells, there is a trench that is not connected to the JFET region.

4. 2. The power semiconductor device according to claim 1, the first terminal cell is adjacent to terminal ends of the first unit cells and the second unit cells that are periodically arranged in the first direction; the second terminal cell is adjacent to a terminal end of the first unit cell that is periodically arranged in the second direction only if the second terminal cell does not overlap with the first terminal cell; the third terminal cell is adjacent to a terminal end of the second unit cell periodically arranged in the second direction only if the third terminal cell does not overlap with the first terminal cell; the fourth end cell is adjacent to end portions of the second end cell and the third end cell that are periodically arranged in the first direction; The fifth terminal cell is adjacent to a terminal end of the first terminal cell in the second direction.

5. 2. The power semiconductor device according to claim 1, each of the first unit cell, the second unit cell and the first termination cell has a MOSFET structure and a JFET region; The first termination cell has a different JFET width than the first unit cell and the second unit cell, or a different channel length than the first unit cell and the second unit cell.

6. 6. The power semiconductor device according to claim 5, a JFET width of the first termination cell becomes narrower as it approaches a termination portion of the power semiconductor device in the first direction, or a channel length of the first termination cell becomes longer as it approaches a termination portion of the power semiconductor device in the first direction, compared to each of the first unit cell and the second unit cell.

7. 2. The power semiconductor device according to claim 1, The second termination cell, the third termination cell and the fourth termination cell are equivalent in structure to the fifth termination cell.

8. a semiconductor substrate having a main surface and a back surface opposite to the main surface; unit cells periodically arranged in a first direction along the main surface of the semiconductor substrate and in a second direction perpendicular to the first direction in a plan view; a terminal cell adjacent to a terminal end of a plurality of the unit cells arranged in the first direction or the second direction; having The unit cell comprises: a guard region of a first conductivity type formed in the semiconductor substrate; a body region of the first conductivity type formed in the semiconductor substrate; a first semiconductor region of a second conductivity type different from the first conductivity type formed in the semiconductor substrate; the second conductivity type JFET region formed between the guard regions adjacent to each other in the first direction in the semiconductor substrate; a source region of the second conductivity type formed in the semiconductor substrate including the main surface of the semiconductor substrate and connected to the first semiconductor region; a conductive connection portion formed on the main surface of the semiconductor substrate and connected to the source region; a plurality of trenches formed in the main surface of the semiconductor substrate, the trenches having ends in the first direction within the guard region and repeatedly arranged in the second direction; a fin made of the semiconductor substrate and sandwiched between the trenches adjacent to each other in the second direction; a gate electrode embedded in each of the plurality of trenches; having the first semiconductor region, the body region, and the JFET region are arranged in this order from the main surface side to the back surface side of the semiconductor substrate in the semiconductor substrate adjacent to a side surface of the trench of the unit cell, The termination cell includes: The guard area; The body region; a second semiconductor region of the first conductivity type formed in the semiconductor substrate including the main surface of the semiconductor substrate; the conductive connection portion connected to the second semiconductor region; the plurality of trenches; The fin; The gate electrode; A power semiconductor device comprising:

9. generating placement data for periodically placing the first unit cells and the second unit cells in a first direction and a second direction perpendicular to each other; generating placement data for a plurality of termination cells; Run the first unit cells and the second unit cells are arranged alternately in the first direction; the plurality of termination cells includes a first termination cell, a second termination cell, a third termination cell, a fourth termination cell, and a fifth termination cell; the number of periods of the first unit cell and the second unit cell in the second direction varies depending on a repeating period coordinate of the first unit cell and the second unit cell in the first direction; each of the first unit cell and the second unit cell that are periodically arranged is adjacent to any one of the plurality of terminal cells at an end of the periodic arrangement in each of the first direction and the second direction; A cell data generation system, wherein a region in which each of the plurality of termination cells exists has electrical characteristics different from the first unit cell and the second unit cell.

10. 10. The cell data generation system according to claim 9, Each of the first unit cell and the second unit cell has a first conductivity type guard region formed in a semiconductor substrate having a main surface and a back surface opposite to the main surface; a body region of the first conductivity type formed in the semiconductor substrate; a first semiconductor region of a second conductivity type different from the first conductivity type formed in the semiconductor substrate; the second conductivity type JFET region formed between the guard regions adjacent to each other in the first direction in the semiconductor substrate; a source region of the second conductivity type formed in the semiconductor substrate including the main surface of the semiconductor substrate and connected to the first semiconductor region; a conductive connection portion formed on the main surface of the semiconductor substrate and connected to the source region; a plurality of trenches formed in the main surface of the semiconductor substrate, the trenches having ends in the first direction within the guard region and repeatedly arranged in the second direction; a fin made of the semiconductor substrate and sandwiched between the trenches adjacent to each other in the second direction; a gate electrode embedded in each of the plurality of trenches; having the first semiconductor region, the body region, and the JFET region are arranged in this order from the main surface side to the back surface side of the semiconductor substrate in the semiconductor substrate adjacent to side surfaces of the trenches of the first unit cell and the second unit cell, The termination cell includes: The guard area; The body region; a second semiconductor region of the first conductivity type formed in the semiconductor substrate including the main surface of the semiconductor substrate; the conductive connection portion connected to the second semiconductor region; the plurality of trenches; The fin; The gate electrode; A cell data generation system comprising:

11. The cell data generation system according to claim 10, the source region has a first impurity concentration; When generating the cell data of the first terminal cell, disposing a first termination cell having a MOSFET structure and the JFET region connected to a termination portion of the first unit cell and the second unit cell aligned in the first direction; removing the second conductivity type semiconductor region, which is electrically located on a source electrode side of the MOSFET structure and has an impurity concentration higher than a first impurity concentration, in the first termination cell; a second semiconductor region having an impurity concentration higher than the first impurity concentration so as to overlap the MOSFET structure or the JFET region in a plan view;

12. The cell data generation system according to claim 10, each of the first unit cell and the second unit cell includes a gate wiring that is formed on the main surface of the semiconductor substrate, is connected to the gate electrode inside each of the plurality of trenches aligned in the second direction, and extends in the second direction; When generating cell data of the second terminal cell and the third terminal cell, the second terminal cell is disposed at a position adjacent to a terminal end of the first unit cells periodically disposed in the second direction only when the second terminal cell does not overlap with the first terminal cell; the third terminal cell is disposed at a position adjacent to a terminal end of the second unit cell periodically disposed in the second direction only when the third terminal cell does not overlap with the first terminal cell; a cell data generation system for generating a cell data of each of the second and third termination cells, the cell data being obtained by expanding or contracting the first unit cell or the second unit cell in the second direction, the elements other than the gate wiring and the guard region being terminated midway in the second direction, the JFET region being blocked midway in the second direction, and the second semiconductor region being disposed over the entire surface.

13. The cell data generation system according to claim 12, When generating the cell data of the fourth terminal cell, The fourth terminal cell is disposed at a position adjacent to a terminal end portion of the first terminal cell in the second direction, the fourth terminal cell being disposed at a position adjacent to the first terminal cell in the first direction, A cell data generation system in which, for a cell obtained by expanding or contracting the first terminal cell in the second direction, elements other than the gate wiring and the guard region are terminated midway in the second direction, the JFET region is blocked midway in the second direction, and the second semiconductor region is placed over the entire surface.

14. The cell data generation system according to claim 12, When generating the cell data of the fifth terminal cell, The fifth terminal cell is disposed at a position adjacent to a terminal end portion of the first terminal cell in the second direction, the fifth terminal cell being disposed adjacent to the first terminal cell in the first direction; a cell data generation system for generating cell data by expanding or contracting the first terminal cell in the second direction, terminating elements other than the gate wiring and the guard region midway in the second direction, blocking the JFET region midway in the second direction, disposing the second semiconductor region over the entire surface, and removing a certain length of the guard region from the side connected to the first unit cell.

15. A power semiconductor device equivalent to a structure generated by the cell data generation system according to any one of claims 9 to 14.

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