Memory system and control method

Abstract

To provide a memory system and a control method capable of suitably executing GC operation.SOLUTION: A controller calculates a light amplification when executing garbage collection operation. The controller calculates a first threshold that increases as the number of first blocks for storing at least effective data increases. The controller adjusts the first threshold such that the first threshold becomes a large value when a light amplification is smaller than a target value of the light amplification, and adjusts the first threshold such that the first threshold becomes a small value when a light amplification is larger than a target value. The controller selects each of blocks in which an effective data rate is smaller than the first threshold from among the first blocks. The controller copies effective data stored in each of selected blocks to a copy destination block.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a memory system including a nonvolatile memory and a control method for controlling the nonvolatile memory. [Background technology]

[0002] In recent years, memory systems equipped with nonvolatile memories have become widespread. One such memory system is a solid-state drive (SSD) equipped with a NAND flash memory.

[0003] NAND flash memory contains multiple blocks, which are the smallest unit of data erasure. The memory system controller performs garbage collection (GC) operations to restore the number of free blocks available for writing data.

[0004] If GC operations are performed too frequently (or if too many free blocks are created in one GC operation), the lifespan of the memory system may be shortened due to poor write amplification.On the other hand, if GC operations are performed too infrequently (or if too few free blocks are created in one GC operation), a lack of free blocks may prevent the memory system from immediately starting to process write commands received from the host, which may cause a decrease in performance of the memory system. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-33002 [Patent Document 2] Japanese Patent Application Publication No. 2019-212099 [Patent Document 3] Japanese Patent Application Laid-Open No. 2017-111476 Summary of the Invention [Problem to be solved by the invention]

[0006] The problem to be solved by the embodiments of the present invention is to provide a memory system and a control method that can perform GC operations favorably. [Means for solving the problem]

[0007] According to an embodiment, a memory system connectable to a host includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks, each of which is a unit of a data erase operation. The controller is configured to control the nonvolatile memory and perform a garbage collection operation on the nonvolatile memory. When performing the garbage collection operation, the controller calculates a write amplification indicating a ratio of a total amount of data written to the nonvolatile memory to a total amount of data written to the nonvolatile memory based on a request from the host. The controller calculates a first threshold value based on at least the number of first blocks storing valid data, the first threshold value increasing as the number of the first blocks increases. If the calculated write amplification is smaller than a target value of the write amplification, the controller adjusts the first threshold value to a larger value. If the calculated write amplification is greater than the target value, the controller adjusts the first threshold value to a smaller value. The controller determines a valid data ratio for each of the first blocks, indicating a ratio of a total amount of valid data to a total amount of data that can be stored in one block. The controller selects each of the first blocks having the valid data ratio smaller than the first threshold, and copies the valid data stored in each of the selected blocks to a destination block, thereby making each of the selected blocks a free block. [Brief explanation of the drawings]

[0008] [Figure 1]FIG. 1 is a block diagram showing an example of the configuration of an information processing system including a memory system according to an embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a NAND flash memory included in the memory system according to the embodiment. [Figure 3] FIG. 2 is a block diagram showing an example of the configuration of a DRAM included in the memory system according to the embodiment. [Figure 4] FIG. 2 is a block diagram showing an example of the functional configuration of a CPU included in a controller of the memory system according to the embodiment. [Figure 5] 1A and 1B are diagrams showing examples of write operations and garbage collection operations executed in a memory system according to an embodiment. [Figure 6] FIG. 10 is a diagram showing the relationship between the first threshold and the number of active blocks in the memory system according to the embodiment. [Figure 7] 10 is a diagram showing the relationship between the first threshold and the number of active blocks in a memory system according to an embodiment when write amplification (WAF) is equal to a WAF target value. [Figure 8] 10 is a diagram showing the relationship between the first threshold and the number of active blocks in a memory system according to an embodiment when the WAF is smaller than the WAF target value. [Figure 9] 10 is a diagram showing the relationship between the first threshold and the number of active blocks in a memory system according to an embodiment when the WAF is greater than the WAF target value. [Figure 10] 10 is a flowchart showing the procedure of an idle state transition operation executed in the memory system according to the embodiment. [Figure 11] 1 is a flowchart showing the procedure of a garbage collection operation executed in a memory system according to an embodiment. [Figure 12] 10 is a flowchart showing the procedure of a WAF calculation operation executed in a memory system according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment will be described with reference to the drawings. 1 is a block diagram showing an example of the configuration of an information processing system 1 including a memory system 3 according to an embodiment. The memory system 3 according to the embodiment is a storage device including a nonvolatile memory.

[0010] The information processing system 1 includes a host (host device) 2 and a memory system 3. The host 2 and the memory system 3 can be connected via a bus 7.

[0011] The host 2 is an information processing device. The host 2 is, for example, a personal computer, a server computer, or a mobile terminal. The host 2 accesses the memory system 3. Specifically, the host 2 sends a write command to the memory system 3, which is a command requesting that data be written to the nonvolatile memory. The host 2 sends a read command to the memory system 3, which is a command requesting that data be read from the nonvolatile memory. The host 2 also sends an invalidation command to the memory system 3, which is a command requesting that data be invalidated. Examples of invalidation commands are an unmap command and a trim command.

[0012] The memory system 3 is a semiconductor storage device connectable to the host 2. The memory system 3 is realized by, for example, an embedded multimedia card (eMMC), a solid state device (SSD), or the like. The memory system 3 includes, for example, a NAND flash memory 5, which is an example of a nonvolatile memory. The memory system 3 writes data to the nonvolatile memory. Then, the memory system 3 reads data from the nonvolatile memory.

[0013] Communication between the memory system 3 and the host 2 is carried out via a bus 7. The bus 7 is primarily used for transmitting data and input / output commands (I / O commands) from the host 2 to the memory system 3, and for transmitting data and responses from the memory system 3 to the host 2. An I / O command is a command for writing or reading data to or from the nonvolatile memory. Examples of I / O commands include a write command for requesting writing data to the nonvolatile memory and a read command for requesting reading data from the nonvolatile memory.

[0014] Next, we will explain the internal configuration of the memory system 3. The memory system 3 includes a controller 4 and a NAND flash memory 5. The memory system 3 may further include a dynamic random access memory (DRAM) 6.

[0015] The controller 4 is a memory controller. The controller 4 is, for example, a control circuit such as a System-on-a-Chip (SoC). The controller 4 is electrically connected to each of the NAND flash memory 5 and the DRAM 6. The controller 4 processes various commands received from the host 2. The controller 4 writes data to the NAND flash memory 5 by processing a write command. The controller 4 reads data from the NAND flash memory 5 by processing a read command. When a certain period of time has passed without an access from the host 2, the controller 4 transitions the memory system 3 to an idle state. Alternatively, the controller 4 transitions the memory system 3 to an idle state based on a request from the host 2. The memory system 3 in the idle state is waiting for a request from the host 2. For example, the memory system 3 reduces its power consumption during the idle state. Alternatively, the memory system 3 may perform, for example, a garbage collection operation during the idle state.

[0016] The controller 4 is also communicatively connected to the DRAM 6. The controller 4 writes data to the DRAM 6 and reads data from the DRAM 6.

[0017] The NAND flash memory 5 is a non-volatile memory. The NAND flash memory 5 is, for example, a flash memory with a three-dimensional structure. The NAND flash memory 5 includes a memory cell array 50. The memory cell array 50 includes a plurality of memory cells arranged in a matrix. The memory cell array 50 in the NAND flash memory 5 includes a plurality of blocks BLK0 to BLKx-1. Each of the blocks BLK0 to BLKx-1 is a unit of a data erase operation for erasing data. The data erase operation is also referred to as an erase operation or simply as an erase operation. Each of the blocks BLK0 to BLKx-1 is also referred to as a physical block, a flash block, or a memory block.

[0018] Each of the blocks BLK0 to BLKx-1 includes multiple pages (pages P0 to Py-1 in this example). Each page includes multiple memory cells connected to the same word line. Each of the pages P0 to Py-1 is a unit for data write and read operations.

[0019] Some of the blocks BLK0 to BLKx-1 can be used as triple-level cell blocks (TLC blocks), for example. In the operation of writing data to each TLC block, three bits of data are written to each memory cell, so that three pages of data are written to multiple memory cells connected to the same word line.

[0020] Each of the other blocks among the blocks BLK0 to BLKx-1 can be used as, for example, a single-level cell block (SLC block). In an operation of writing data to each SLC block, one bit of data is written to each memory cell, and one page of data is written to multiple memory cells connected to the same word line.

[0021] The storage density per memory cell of an SLC block is 1 bit (i.e., 1 page per word line), while the storage density per memory cell of a TLC block is 3 bits (i.e., 3 pages per word line). Therefore, even if the number of SLC blocks and TLC blocks is the same, the amount of data that can be stored by using TLC blocks is three times the total amount of data that can be stored by using SLC blocks. In other words, by storing data preferentially in TLC blocks rather than in SLC blocks, the resources of memory system 3 can be used more effectively.

[0022] On the other hand, the data write and read speeds for the NAND flash memory 5 are slower as the storage density increases and faster as the storage density decreases. Therefore, the time required to read and write data from and to a TLC block is longer than the time required to read and write data from and to an SLC block.

[0023] Therefore, in the memory system 3, by writing data associated with a write command received from the host 2 to an SLC block, the write command can be processed faster than if the data were written to a TLC block. Then, by copying the data stored in the SLC block to a TLC block, the resources of the memory system 3 can be used more effectively.

[0024] However, this copy operation causes a data write operation to the NAND flash memory 5 in addition to the data write operation requested by the host 2. Therefore, this copy operation deteriorates the write amplification (WAF) in the memory system 3, and as a result, shortens the lifespan of the NAND flash memory 5. Write amplification is also called a write efficiency value. Write amplification indicates the ratio of the total amount of data written to the NAND flash memory 5 to the total amount of data written to the NAND flash memory 5 based on a request from the host 2.

[0025] Hereinafter, the mode in which three pages of data are written to multiple memory cells connected to the same word line will be referred to as the first write mode, and the mode in which one page of data is written to multiple memory cells connected to the same word line will be referred to as the second write mode. The first write mode will also be referred to as the TLC mode. The second write mode will also be referred to as the SLC mode. Each of the multiple blocks included in the NAND flash memory 5 is, for example, either a block dedicated to the first write mode or a block dedicated to the second write mode.

[0026] The DRAM 6 is a volatile memory. A part of the storage area of ​​the DRAM 6 is used, for example, to temporarily store information used to manage the memory system 3. Another part of the storage area of ​​the DRAM 6 can be used to temporarily store write data received from the host 2 or read data read from the NAND flash memory 5.

[0027] Next, we will explain an example of the internal configuration of the controller 4. The controller 4 includes a host interface (host I / F) 41, a CPU 42, a direct memory access controller (DMAC) 43, a static RAM (SRAM) 44, a NAND interface (NAND I / F) 45, an ECC encoding / decoding circuit 46, and a DRAM interface (DRAM I / F) 47. Each of these components is connected to an internal bus 40.

[0028] The host interface 41 is an interface circuit that communicates with the host 2. For example, the host interface 41 receives I / O commands and data from the host 2. The host interface 41 also transmits data and responses to the host 2.

[0029] The CPU 42 is a processor. The CPU 42 controls the host interface 41, the DMAC 43, the SRAM 44, the NAND interface 45, the ECC encoding / decoding circuit 46, and the DRAM interface 47. The CPU 42 loads a control program (firmware) stored in the NAND flash memory 5 or a ROM (not shown) into the SRAM 44 or the DRAM 7. The CPU 42 executes this control program (firmware) to perform various processes.

[0030] The CPU 42, for example, functions as a flash translation layer (FTL) to manage data stored in the NAND flash memory 5 and blocks included in the NAND flash memory 5. The management of data stored in the NAND flash memory 5 involves, for example, the management of mapping information, which is information indicating the correspondence between each logical address and each physical address. A logical address is an address used by the host 2 to access the memory system 3. A logical address is, for example, an LBA (Logical Block Address). A physical address is an address indicating a physical storage location in the NAND flash memory 5. In the NAND flash memory 5, data can be written to one page of a block only once per program / erase cycle for the block. Therefore, the controller 4 writes updated data corresponding to a certain logical address to a different storage location, rather than to the storage location where the previous data corresponding to this logical address is stored. Therefore, the CPU 42 manages the mapping between logical addresses and physical addresses using a logical-to-physical address translation table (L2P table) 61. Of the data stored in the NAND flash memory 5, data stored in a storage location indicated by a physical address mapped to a logical address is valid data. On the other hand, data stored in a storage location indicated by a physical address not mapped to any logical address is invalid data. The CPU 42 manages blocks that store at least valid data as active blocks. The CPU 42 also manages blocks that do not store valid data as free blocks.

[0031] Furthermore, in managing the blocks included in the NAND flash memory 5, for example, a garbage collection operation is performed. In the garbage collection operation, the CPU 42 selects a specific active block as a block to be garbage collected. The block to be garbage collected is called a copy source block. The CPU 42 extracts only valid data stored in the block stored in the selected block and copies it to a copy destination block. As a result, all data stored in the selected block to be garbage collected becomes invalid data. Therefore, the selected block becomes a free block. The CPU 42 then performs a data erase operation on the block that has become a free block. In other words, the CPU 42 can restore the number of free blocks in the memory system 3 by performing the garbage collection operation.

[0032] The DMAC 43 is a circuit that executes direct memory access (DMA) and transfers data between a memory (not shown) of the host 2 and the SRAM 44 or the DRAM 6.

[0033] The SRAM 44 is a volatile memory. A portion of the storage area of ​​the SRAM 44 can be used, for example, as a write buffer that temporarily stores write data received from the host 2. A portion of the storage area of ​​the SRAM 44 can also be used, for example, as a read buffer that temporarily stores data read from the NAND flash memory 5. The SRAM 44 has a faster data write and read speed than, for example, the DRAM 6. Therefore, frequently used information from among the information stored in the DRAM 6 may be temporarily stored in a portion of the storage area of ​​the SRAM 44.

[0034] The NAND interface 45 is an interface circuit that executes access to the NAND flash memory 5 .

[0035] The NAND interface 45 is a circuit that controls the NAND flash memory 5. When the NAND flash memory 5 is configured from multiple NAND flash dies, the NAND interface 45 may be connected to each of the multiple NAND flash memory dies via multiple channels.

[0036] The ECC encoding / decoding circuit 46 is a circuit that performs data encoding and decoding. The ECC encoding / decoding circuit 46 performs encoding when writing data to the NAND flash memory 5. In the encoding process, the ECC encoding / decoding circuit 46 adds an error correction code (ECC) as a redundant code to the data to be written. In the decoding process, the ECC encoding / decoding circuit 46 performs decoding when data is read from the NAND flash memory 5. In the decoding process, the ECC encoding / decoding circuit 46 performs error correction on the data read from the NAND flash memory 5 using the ECC added to the data.

[0037] The DRAM interface 47 is a circuit that controls the DRAM 6. The DRAM interface 47 stores data in the DRAM 6 and reads data stored in the DRAM 6.

[0038] Next, a configuration example of the NAND flash memory 5 will be described. Fig. 2 is a block diagram showing a configuration example of the NAND flash memory 5 included in the memory system 3 according to the embodiment. A part of the storage area of ​​the NAND flash memory 5 is used to store user data 51 and system data 52.

[0039] The user data 51 is data written to the NAND flash memory 5 based on a write command received from the host 2. The user data stored in the NAND flash memory 5 is broadly divided into valid data and invalid data. The valid data is data stored in a storage location in the NAND flash memory 5 indicated by a physical address associated with a logical address. The valid data is data that may be read by the host 2 later. The invalid data is data stored in a storage location in the NAND flash memory 5 indicated by a physical address not associated with a logical address. The invalid data is data that may no longer be read by the host 2.

[0040] The system data 52 is data used for managing the memory system 3. The system data 52 is also referred to as management information. The system data 52 includes health data. The health data is referred to as smart health information, for example. The health data includes information indicating the total amount of data written to the NAND flash memory 5.

[0041] Next, we will explain a configuration example of the DRAM 6. Fig. 3 is a block diagram showing a configuration example of the DRAM 6 included in the memory system 3 according to the embodiment. Part of the storage area of ​​the DRAM 6 is used to store an L2P table 61, an active block list 62, and a free block list 63.

[0042] The L2P table 61 manages mapping between each logical address and each physical address for each predetermined size such as a cluster.

[0043] The active block list 62 is a list that manages active blocks, which are blocks that store at least valid data. The active block list 62 may also manage, for each active block, a valid data ratio that indicates the ratio of the total amount of valid data to the total amount of data that can be stored in one block. The active block list 62 may hold the valid data ratio of each active block. The valid data ratio of each active block may be held in the SRAM 44 instead of being held in the active block list 62 of the DRAM 6. When the valid data ratio of each active block is managed, the controller 4 updates the valid data ratio of each active block whose data has been rewritten each time data is rewritten. Alternatively, the valid data ratio of each active block may be calculated by the controller 4 each time a garbage collection operation is performed.

[0044] The free block list 63 is a list for managing free blocks, which are blocks that do not store valid data.

[0045] Next, an example of the functional configuration of the CPU 42 will be described. Fig. 4 is a block diagram showing an example of the functional configuration of the CPU 42 included in the controller 4 of the memory system 3 according to the embodiment. The CPU 42 includes a write control unit 421, a write amplification (WAF) calculation unit 422, and a garbage collection (GC) control unit 423. The processes by the write control unit 421, the WAF calculation unit 422, and the GC control unit 423 may be performed by the CPU 42 executing firmware, or may be performed by dedicated hardware.

[0046] The write control unit 421 controls the operation of writing data to the NAND flash memory 5. The write control unit 421 generates a program command, which is an instruction to write data to the NAND flash memory 5, and issues the generated program command to the NAND interface 45. The write control unit 421 generates a program command in response to the fact that it is possible to write data to the NAND flash memory 5.

[0047] The write control unit 421 receives a write command via the host interface 41. The write command specifies at least a logical address corresponding to the write data to be written to the NAND flash memory 5 and the size of the write data. The write control unit 421 receives the write data associated with the received write command from the host 2 and stores the received write data in the write buffer 441. Then, in response to the total amount of valid data stored in the write buffer 441 reaching the minimum write size, the write control unit 421 determines a write destination memory location in the write destination block to which the write data is to be written and generates a program command for writing the write data to the write destination memory location. The program command specifies a physical address indicating the write destination memory location and an address indicating the memory location in the write buffer 441 where the user data to be written is stored. The write control unit 421 issues the generated program command to the NAND flash memory 5 via a command queue (not shown) and the NAND interface 45. In this way, the write control unit 421 writes the write data associated with the write command to the write destination memory location in the write destination block.

[0048] Furthermore, the write control unit 421 selects a write mode to be used in the data write operation based on the status of the memory system 3. For example, if the number of free blocks in the memory system 3 is greater than a threshold, the write control unit 421 selects the second write mode. In this case, the write control unit 421 generates a program command when one page of user data is prepared in the write buffer 441. For example, if the number of free blocks in the memory system 3 is equal to or less than a threshold, the write control unit 421 selects the first write mode. In this case, the write control unit 421 generates a program command when three pages of user data are prepared in the write buffer 441. The program command for writing three pages of user data to the NAND flash memory 5 may be transmitted all at once or may be transmitted in multiple batches.

[0049] Furthermore, a data read operation for reading data written to the NAND flash memory 5 is controlled by a read control unit (not shown). The read control unit executes the data read operation based on a read command received from the host 2. At this time, the read control unit generates a read command to be sent to the NAND flash memory 5 via the NAND interface 45.

[0050] The WAF calculation unit 422 calculates the write amplification. In response to the start of the garbage collection operation, the WAF calculation unit 422 starts the write amplification calculation operation.

[0051] The WAF calculation unit 422 first reads health data from the NAND flash memory 5. The WAF calculation unit 422 obtains the total amount of data written to the NAND flash memory 5 from the read health data. Furthermore, the WAF calculation unit 422 obtains, for example, the total amount of data written to the NAND flash memory 5 based on the write command received from the host 2 from the read health data. The WAF calculation unit 422 may use the total amount of data written to the NAND flash memory 5 obtained from the read health data to calculate the total amount of data written to the NAND flash memory 5 based on the write command received from the host 2.

[0052] The GC control unit 423 controls garbage collection operations. The GC control unit 423 executes two types of garbage collection operations (first garbage collection operation or second garbage collection operation) depending on the number of active blocks (or the number of free blocks) in the memory system 3.

[0053] When the memory system 3 transitions to the idle state, the GC control unit 423 determines whether the number of active blocks in the memory system 3 is within a first range. The first range is, for example, n min At least n max The range is less than n min and n max are all natural numbers, and n min is n maxThe GC control unit 423 performs a first garbage collection operation when the number of active blocks is within a first range. When the first garbage collection operation starts, the GC control unit 423 causes the WAF calculation unit 422 to calculate the WAF. The GC control unit 423 then calculates a first threshold value that increases as the number of active blocks in the memory system 3 increases. The first threshold value is also referred to as Vcth. Specifically, Vcth is a percentage based on the value obtained by multiplying the WAF by a value obtained by dividing the number of active blocks to a power of 1 or greater by the number of blocks to a power of 1 or greater. The GC control unit 423 compares the calculated threshold value with the valid data ratio of each active block in the memory system 3. The GC control unit 423 selects each of the active blocks whose valid data ratio is smaller than Vcth. The GC control unit 423 then copies the valid data stored in each selected block to a destination block, thereby making each of the selected blocks a free block.

[0054] Furthermore, when the number of free blocks in the memory system 3 falls below a threshold, the GC control unit 423 executes a second garbage collection operation, which is different from the first garbage collection. For example, the GC control unit 423 sets the number of free blocks to be recovered. For example, the GC control unit 423 selects active blocks in order of lowest valid data rate. The GC control unit 423 copies valid data stored in each selected block to a destination block, thereby making each selected block a free block. However, the GC control unit 423 continues the second garbage collection operation until the set number of free blocks is recovered.

[0055] Hereinafter, the first garbage collection operation will be simply referred to as the garbage collection operation, and the second garbage collection operation will be referred to as the other garbage collection.

[0056] Next, the flow of data in a data write operation and a garbage collection operation will be described. Figure 5 is a diagram showing an example of a write operation and a garbage collection operation executed in the memory system according to the embodiment.

[0057] First, the data write operation will be described. The write control unit 421 receives user data associated with a write command received from the host 2 and temporarily stores the received user data in the write buffer 441. The write control unit 421 then writes the stored user data to the write destination block. When the write is complete, the controller 4 sends a completion response corresponding to the write command for which processing has been completed to the host 2.

[0058] When user data is written to a write destination block and the block becomes full, making it impossible to write new user data, the controller 4 releases the block from the write destination block allocation and registers it in the active block list 62. Alternatively, the block may be registered in the active block list 62 when it is allocated to the write destination block.

[0059] If a new data write operation occurs and no block has been assigned to the write destination block, the write control unit 421 selects an arbitrary block from the free block list 63 and assigns it to the write destination block. At this time, the write control unit 421 may refer to the program / erase cycle of each free block. For example, the write control unit 421 selects a block with a relatively long lifespan that is a block where the program / erase cycle progresses slowly, and assigns it as the write destination block.

[0060] Next, the garbage collection operation will be described.

[0061] The GC control unit 423 selects, as blocks to be garbage collected, all of the active blocks registered in the active block list 62 that satisfy the condition that the valid data ratio is smaller than Vcth. For example, in a garbage collection operation, the GC control unit 423 identifies the valid data ratio of each active block by calculating the valid data ratio of each active block. Alternatively, the GC control unit 423 identifies the valid data ratio by referring to the valid data ratio of each active block managed in the memory system 3.

[0062] If there is no block that satisfies the condition, the GC control unit 423 ends the garbage collection operation.

[0063] If one or more blocks satisfying the condition exist, the GC control unit 423 selects each of the one or more blocks satisfying the condition as one or more blocks to be garbage collected. The selected blocks are allocated as copy source blocks. If no blocks are allocated as copy destination blocks, the GC control unit 423 selects one or more free blocks from the free block list 63 and allocates them as copy destination blocks.

[0064] The GC control unit 423 then copies the valid data stored in the garbage collection target block to the copy destination block. As a result, the valid data stored in the garbage collection target block becomes invalid data. After a data erasure operation is performed on the garbage collection target block, in which all data stored therein has become invalid data, the block is returned to the free block list 63. The data erasure operation on the block may also be performed immediately before a block registered in the free block list 63 is assigned as a write destination block or a copy destination block.

[0065] When a destination block becomes full as a result of data being copied, the block is deallocated from the destination block and registered in the active block list 62. Alternatively, the block may have been registered in the active block list 62 when it was allocated as a destination block.

[0066] When copying valid data to a destination block, for example, the controller 4 writes the data to the destination block using the TLC mode. In this case, a block corresponding to the TLC mode is selected as the block to be allocated to the destination block. At this time, if the valid data stored in the source block was data that was written using the SLC mode, the controller 4 can reduce the number of blocks used to store this data by copying the data to the destination block in the TLC mode.

[0067] However, copying data to a destination block based on a garbage collection operation is writing data to the NAND flash memory 5 other than writing data to the NAND flash memory 5 based on a request from the host 2. Therefore, the WAF of the memory system 3 increases when data is copied based on a garbage collection operation.

[0068] Next, Vcth, which is a threshold value used in the garbage collection operation, will be described. Figure 6 is a diagram showing the relationship between the first threshold value and the number of active blocks in the memory system according to the embodiment.

[0069] 6, the vertical axis indicates a threshold value (referred to as Vcth) used in the garbage collection operation, and the horizontal axis indicates n, which is the number of active blocks in the memory system 3. Vcth is calculated by the following equation 1. Vcth = 100 × z × WAF × (nn min ) x / (Nn min) x …Formula 1 WAF in Equation 1 is the current write amplification of the memory system 3 .

[0070] N indicates the total number of blocks managed in the memory system 3. The total number of blocks, N, is the sum of the number of active blocks and the number of free blocks. In other words, the number obtained by subtracting the number of active blocks, n, from the total number of blocks, N, represents the number of free blocks.

[0071] n min is the garbage collection start threshold and indicates the lower end value of the first range.

[0072] n max is the garbage collection termination threshold, and indicates the upper end value of the first range.

[0073] The release size indicates the number of blocks corresponding to the first range. The release size is N-(n min + offset + GC threshold). The offset is the number of active blocks that is n max The offset does not have to be set (for example, it may be 0). The GC threshold is a threshold used to determine whether or not another garbage collection operation is started. The GC control unit 423 executes another garbage collection operation in response to the number of free blocks in the memory system 3 becoming equal to or less than the GC threshold.

[0074] z is a normalization value. It is a value that is set in advance so that Vcth falls within a percentage value. z is, for example, a fixed value during operation of the memory system 3.

[0075] x is a number equal to or greater than 1. For example, x is set to a value such as 2 or 3.

[0076] β is a free block supply control variable. β is a value used to adjust Vcth according to the value of WAF. β is, for example, 20%. In addition, the free block supply control variable used to adjust Vcth to a larger value and the free block supply control variable used to adjust Vcth to a smaller value may be set to different values.

[0077] The number of active blocks, n, is 0 to n max + offset, the write control unit 421 of the controller 4 uses the SLC mode to write data to the NAND flash memory 5. While performing a write operation using the SLC mode, the memory system 3 can process a write command received from the host 2 with relatively low latency.

[0078] The number of active blocks, n, is max If the offset is equal to or greater than the +offset, the write control unit 421 of the controller 4 uses the TLC mode to write data to the NAND flash memory 5. While performing a write operation using the TLC mode, the memory system 3 processes a write command received from the host 2 with a relatively higher latency than when performing a write operation using the SLC mode.

[0079] Also, when the number of free blocks is below the GC threshold, the GC control unit 423 executes another garbage collection operation. maxWhen the value is equal to or greater than the +offset, the number of free blocks is equal to or less than the GC threshold, so the controller 4 performs another garbage collection operation when using the TLC mode to write data to the NAND flash memory 5. The GC control unit 423 performs another garbage collection operation in the background while the number of free blocks is below the GC threshold but is equal to or greater than the threshold. In other words, the GC control unit 423 performs another garbage collection operation when data writing based on a write command received from the host 2 is not being performed. This threshold is a value smaller than the GC threshold.

[0080] Also, the number of active blocks, n, is n max +offset or more and while the number of free blocks is less than the threshold, the GC control unit 423 of the controller 4 executes other garbage collection operations in the foreground. During this time, the memory system 3 executes other garbage collection operations in parallel with the write operation based on the write command received from the host 2. Therefore, the memory system 3 processes the write command received from the host 2 with even higher latency than while simply executing a write operation in TLC mode.

[0081] While n, which is the number of active blocks, is within the first range corresponding to the release size, the GC control unit 423 of the controller 4 executes a garbage collection operation every time the memory system 3 transitions to the idle state.

[0082] At this time, the WAF calculation unit 422 of the controller 4 calculates the WAF in the memory system 3. Then, the controller 4 uses the calculated WAF and the number n of active blocks in the memory system 3 to calculate Vcth.

[0083] In the garbage collection operation, the GC control unit 423 selects each block whose valid data rate is equal to or less than Vcth as a block to be garbage collected. Therefore, the larger the calculated Vcth value, the more active blocks will be selected as blocks to be garbage collected.

[0084] The curve in the graph of Figure 6 shows the relationship between Vcth = 100 × z × WAF × (nn min ) x / (Nn min ) x where n is a value within the first range. That is, n is a curve represented by min is greater than or equal to n max Furthermore, since x is a number equal to or greater than 1, the value of Vcth increases as n, which is the number of active blocks, increases.

[0085] For this reason, while the number of active blocks in the memory system 3 is small, blocks with a low valid data rate are selected as copy source blocks. As the number of active blocks increases, blocks with a high valid data rate are selected as copy source blocks. In other words, in a garbage collection operation, blocks with a low rate of valid data to be copied are selected as copy source blocks and become free blocks.

[0086] The GC control unit 423 calculates Vcth=50% in FIG.

[0087] Then, the GC control unit 423 compares the WAF value with the WAF target value and adjusts the calculated Vcth. If the WAF is equal to the WAF target value, the GC control unit 423 performs subsequent garbage collection operations with Vcth=50%.

[0088] If the WAF value is smaller than the WAF target value, the GC control unit 423 adds β to the calculated Vcth. For example, Vcth becomes 70% (= 50% + 20%). This may increase the number of blocks selected as source blocks compared to when a Vcth without β is used. In this case, because the WAF of the memory system 3 is smaller than the WAF target value, an increase in the total amount of data to be copied is permitted.

[0089] Furthermore, if the WAF value is greater than the WAF target value, the GC control unit 423 subtracts β from the calculated Vcth. For example, Vcth becomes 30% (=50%-20%). This can reduce the number of blocks selected as copy source blocks. This reduces the total amount of data to be copied, so the WAF of the memory system 3 is prevented from increasing and tends to approach the WAF target value.

[0090] As a result, when the WAF of the memory system 3 is smaller than the WAF target value, Vcth is adjusted so that the WAF is more likely to increase. When the WAF is larger than the WAF target value, Vcth is adjusted so that the increase in WAF is suppressed. Thus, by adjusting Vcth, the controller 4 can control the WAF so that it does not deviate from the WAF target value.

[0091] Although the method of adjusting Vcth has been described above as adding β to Vcth or subtracting β from Vcth, Vcth may be adjusted by other methods. For example, Vcth may be increased by multiplying Vcth by a number greater than 1, or may be decreased by multiplying Vcth by a number greater than 0 and less than 1.

[0092] Next, Vcth will be described for each case of the result of comparing the WAF with the WAF target value. Figure 7 is a diagram showing the relationship between the first threshold and the number of active blocks in a memory system according to an embodiment when the WAF is equal to the target value. Here, the number of active blocks in the memory system 3 is n1.

[0093] Since the WAF is equal to the WAF target value, the same curve as in Figure 6 is plotted in Figure 7. Here, when the number of active blocks is n1, Vcth indicating 50% is calculated.

[0094] At this time, because the WAF is equal to the WAF target value, the GC control unit 423 uses the calculated Vcth to select blocks to be garbage collected. That is, each block with a valid data rate less than 50% is selected as a block to be garbage collected. Then, the GC control unit 423 copies the valid data stored in each of the selected blocks to the destination block.

[0095] In this way, when the WAF is equal to the WAF target value, the controller 4 does not need to increase the total amount of data copied by the garbage collection operation, nor does it need to suppress the increase. Therefore, the controller 4 does not adjust Vcth, but uses the calculated Vcth as is to select blocks to be garbage collected.

[0096] Next, a case where the WAF is smaller than the WAF target value will be described. Figure 8 is a diagram showing the relationship between the first threshold and the number of active blocks in a memory system according to an embodiment when the WAF is smaller than the target value. Here, the number of active blocks in the memory system 3 is n2.

[0097] In Figure 8, the dotted line indicates the Vcth when the WAF is equal to the WAF target value. The solid line indicates the Vcth when the WAF is smaller than the WAF target value. Vcth is proportional to the WAF. Therefore, for the same number of active blocks, the smaller the WAF, the smaller the calculated Vcth value.

[0098] Here, when the number of active blocks is n2, Vcth indicating 10% is calculated.

[0099] At this time, because the WAF is smaller than the WAF target value, the GC control unit 423 adjusts Vcth to a larger value. Specifically, the GC control unit 423 adds 20% to the calculated Vcth. The adjusted Vcth is 30% (=10%+20%).

[0100] Then, the GC control unit 423 uses the adjusted Vcth to select blocks to be collected. That is, the GC control unit 423 selects, from among the active blocks, blocks with a valid data rate of less than 30% as blocks to be collected.

[0101] In this way, when the WAF is smaller than the WAF target value, the controller 4 adjusts Vcth to a larger value. As a result, the controller 4 selects more blocks as blocks to be garbage collected than if the Vcth before adjustment was used. This is because the total amount of data to be copied can be allowed to increase because the WAF is smaller than the WAF target value.

[0102] Next, a case where the WAF is greater than the WAF target value will be described. Figure 9 is a diagram showing the relationship between the first threshold and the number of active blocks in a memory system according to an embodiment when the WAF is greater than the target value. Here, the number of active blocks in the memory system 3 is n3.

[0103] In Figure 9, the dotted line shows the Vcth curve when the WAF is equal to the WAF target value, and the solid line shows the Vcth curve when the WAF is greater than the WAF target value. Vcth is proportional to the WAF. Therefore, for the same number of active blocks, the larger the WAF, the larger the Vcth value.

[0104] Here, when the number of active blocks is n3, Vcth indicating 70% is calculated.

[0105] At this time, because the WAF is larger than the WAF target value, the GC control unit 423 adjusts Vcth to a smaller value. Specifically, the GC control unit 423 subtracts 20% from the calculated Vcth. The adjusted Vcth is 50% (=70%-20%).

[0106] Then, the GC control unit 423 uses the adjusted Vcth to select blocks to be collected. That is, the GC control unit 423 selects, from among the active blocks, blocks with a valid data rate of less than 50% as blocks to be collected.

[0107] In this way, when the WAF is larger than the WAF target value, the controller 4 adjusts Vcth to a smaller value. As a result, the controller 4 reduces the number of blocks selected as garbage collection target blocks compared to when the Vcth before adjustment is used. By reducing the number of blocks selected as copy source blocks, it is possible to suppress an increase in the WAF.

[0108] Next, the idle state transition operation will be described. Fig. 10 is a flowchart showing the procedure of the idle state transition operation executed in the memory system according to the embodiment. For example, the controller 4 starts the idle state transition operation for transitioning the memory system 3 to the idle state in response to not receiving an I / O command from the host 2 for a certain period of time.

[0109] The controller 4 transitions the memory system 3 to an idle state (step S101).

[0110] The controller 4 determines whether the number of active blocks in the memory system 3 is within a first range (step S102).

[0111] If the number of active blocks is not within the first range (No in S102), the controller 4 ends the idle state transition operation.

[0112] If the number of active blocks is within the first range (Yes in S102), the controller 4 executes a garbage collection operation (step S103).

[0113] In this way, the controller 4 determines whether or not to perform a garbage collection operation every time the memory system 3 transitions to the idle state.

[0114] Next, the garbage collection operation in S103 of Fig. 10 will be described in detail. Fig. 11 is a flowchart showing the procedure of the garbage collection operation executed in the memory system according to the embodiment. When the memory system 3 transitions to the idle state, if the number of active blocks is within the first range (Yes in S102 of Fig. 10), the controller 4 starts the garbage collection operation.

[0115] The controller 4 calculates the write amplification (WAF) in the memory system 3 (step S201).

[0116] The controller 4 calculates Vcth using the WAF calculated in S201 and the number of active blocks in the memory system 3 (step S202).

[0117] The controller 4 compares the WAF calculated in S201 with the WAF target value (step S203). The WAF target value is a preset value.

[0118] When the calculated WAF is smaller than the WAF target value (WAF < WAF target value in S203), the controller 4 adjusts to increase the Vcth calculated in S202 (step S204). For example, the controller 4 adds β to Vcth.

[0119] When the calculated WAF is larger than the WAF target value (WAF > WAF target value in S203), the controller 4 adjusts to decrease the Vcth calculated in S202 (step S205). For example, the controller 4 subtracts β from Vcth.

[0120] Also, when the calculated WAF is equal to the WAF target value, the controller 4 uses the Vcth calculated in S202 as it is.

[0121] The controller 4 acquires the valid data rate of each active block (step S206). For example, the controller 4 refers to the active block list 62 to identify the valid data rate of each active block. Alternatively, the controller 4 calculates the valid data rate by referring to each of the active blocks.

[0122] The controller 4 determines whether there is an active block whose valid data rate is below Vcth based on the valid data rate acquired in S206 (step S207).

[0123] When there is no active block whose valid data rate is below Vcth (No in S207), the controller 4 ends the garbage collection operation.

[0124] If there are active blocks whose valid data rate is below Vcth (Yes in S207), the controller 4 selects each of the active blocks whose valid data rate is below Vcth as a block to be garbage collected (step S208).

[0125] The controller 4 copies the valid data stored in each of the blocks selected in S208 to the copy destination block (step S209). As a result, each of the blocks selected in S208 becomes a free block that does not store valid data.

[0126] As a result, the controller 4 calculates Vcth based on the WAF of the memory system 3 and the number of active blocks. Then, the controller 4 adjusts the value of Vcth based on the comparison result between the WAF and the WAF target value. The controller 4 uses this Vcth to select blocks to be garbage collected. This allows the controller 4 to control the amount of data copied by a garbage collection operation according to the WAF of the memory system 3 and the number of active blocks.

[0127] Next, the details of the operation of calculating the WAF in S201 of Fig. 11 will be described. Fig. 12 is a flowchart showing the procedure of the WAF calculation operation executed in the memory system according to the embodiment. The controller 4 starts the WAF calculation operation when starting the garbage collection operation.

[0128] The controller 4 reads the health data from the NAND flash memory 5 (step S301).

[0129] The controller 4 calculates the WAF based on the total amount of data written to the NAND flash memory 5, which is included in the health data read in S301 (step S302). Specifically, the controller 4 calculates the WAF by dividing the total amount of data written to the NAND flash memory 5 based on a request from the host 2 by the total amount of data written to the NAND flash memory 5. The total amount of data written to the NAND flash memory 5 based on a request from the host 2 may be included in the health data read in S301, for example.

[0130] As a result, the controller 4 calculates the WAF of the memory system 3 when performing a garbage collection operation.

[0131] As described above, according to the embodiment, when the memory system 3 transitions to an idle state, the controller 4 starts a garbage collection operation if the number of active blocks is within a first range. When starting a garbage collection operation, the controller 4 calculates a WAF and a Vcth. Then, the controller 4 adjusts the calculated Vcth based on a comparison result between the calculated WAF and a WAF target value. The controller 4 selects each of the active blocks whose valid data rate is smaller than the Vcth and copies the valid data stored in each of the selected blocks to make the selected blocks free blocks. This allows the controller 4 to optimally perform a garbage collection operation based on the WAF and the number of active blocks of the memory system 3. For example, if the Vcth is 30%, the controller 4 selects only blocks whose valid data rate is smaller than 30% and copies the valid data stored in the selected blocks to make the selected blocks free blocks. This reduces the amount of data copied, thereby suppressing an increase in the WAF.

[0132] Specifically, since Vcth is an exponential function of the number of active blocks in the first range, the controller 4 selects more blocks as blocks to be garbage collected as the number of active blocks increases. Therefore, the controller 4 can control the garbage collection operation so that the number of free blocks recovers more as the number of active blocks increases.

[0133] Furthermore, when the WAF of the memory system 3 is smaller than the WAF target value, the controller 4 adjusts Vcth to a larger value. This allows the controller 4 to increase the number of free blocks supplied by the garbage collection operation. Furthermore, the controller 4 increases the WAF because more data is copied, and can bring the WAF closer to the WAF target value.

[0134] Furthermore, when the WAF is larger than the WAF target value, the controller 4 adjusts Vcth to a smaller value. This allows the controller 4 to suppress the number of free blocks supplied by garbage collection operations. Furthermore, the controller 4 can reduce the amount of data to be copied, allowing the WAF to approach the WAF target value.

[0135] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0136] 1...information processing system, 2...host, 3...memory system, 4...controller, 5...NAND flash memory, 6...DRAM, 7...bus, 40...internal bus, 41...host interface, 42...CPU, 43...DMAC, 44...SRAM, 45...NAND interface, 46...ECC encoding / decoding circuit, 47...DRAM interface, 50...memory cell array, 51...user data, 52...system data, 61...L2P table, 62...active block list, 63...free block list, 421...write control unit, 422...WAF calculation unit, 423...GC control unit, 441...write buffer

Claims

1. 1. A memory system connectable to a host, comprising: a non-volatile memory including a plurality of blocks each of which is a unit of a data erase operation; a controller configured to control the non-volatile memory and to perform garbage collection operations on the non-volatile memory; The controller: When performing the garbage collection operation, Calculating a write amplification indicating a ratio of a total amount of data written to the non-volatile memory to a total amount of data written to the non-volatile memory based on a request from the host; calculating a first threshold value based on at least the number of first blocks storing valid data, the first threshold value increasing as the number of the first blocks increases; adjusting the first threshold to a larger value if the calculated write amplification is smaller than a target value of the write amplification, and adjusting the first threshold to a smaller value if the calculated write amplification is larger than the target value; identifying a valid data ratio indicating a ratio of a total amount of valid data to a total amount of data that can be stored in one block for each of the first blocks; selecting each of the first blocks having a valid data ratio smaller than the first threshold; is configured to make each of the selected blocks a free block by copying valid data stored in each of the selected blocks to a destination block; Memory system.

2. The controller: In the garbage collection operation, performing a data erase operation on each of the selected blocks for which the copying has been completed; It is configured as follows:

2. The memory system of claim 1.

3. The controller: When the memory system is transitioned to an idle state, configured to perform the garbage collection operation.

2. The memory system of claim 1.

4. The controller: When the memory system is transitioned to the idle state, performing the garbage collection operation if the number of the first blocks is within a first range; configured to not perform the garbage collection operation if the first number of blocks is not within the first range.

4. The memory system of claim 3.

5. The controller: initiating a garbage collection operation different from the garbage collection operation in response to a number of free blocks among the plurality of blocks becoming equal to or less than a second threshold; When performing the different garbage collection operations, Selecting a block having a low valid data rate from among the first blocks; configured to copy valid data stored in the selected block to a destination block.

2. The memory system of claim 1.

6. The controller: Reading management information from the non-volatile memory; a write amplification calculation unit configured to calculate the write amplification by using a total amount of data written to the non-volatile memory, the total amount being included in the management information; 2. The memory system of claim 1.

7. The controller: and calculating the first threshold value based on a value calculated by multiplying a number obtained by dividing a power of the number of the first blocks, the power being a number equal to or greater than 1, by a power of the number of the plurality of blocks, the power being a number equal to or greater than 1, by the write amplification.

2. The memory system of claim 1.

8. The controller: If the calculated write amplification is less than the target value, adjusting the first threshold to a smaller value by subtracting a second value from the calculated first threshold; If the calculated write efficiency value is greater than the target value, and adjusting the first threshold value to a larger value by adding a third value to the calculated first threshold value.

2. The memory system of claim 1.

9. The second value and the third value are equal.

9. The memory system of claim 8.

10. 1. A method for controlling a non-volatile memory including a plurality of blocks, each of which is a unit of an erase operation, comprising: performing a garbage collection operation on the non-volatile memory; The garbage collection operation is performed by: Calculating a write amplification indicating a ratio of a total amount of data written to the non-volatile memory to a total amount of data written to the non-volatile memory based on a request from a host; calculating a first threshold value based on at least the number of first blocks storing valid data, the first threshold value increasing as the number of the first blocks increases; adjusting the first threshold to a larger value when the calculated write amplification is smaller than a target value of the write amplification, and adjusting the first threshold to a smaller value when the calculated write amplification is larger than the target value; identifying a valid data ratio indicating a ratio of an amount of valid data to a total amount of data that can be stored in one block for each of the first blocks; selecting each of the first blocks having a valid data ratio smaller than the first threshold; making each of the selected blocks a free block by copying valid data stored in each of the selected blocks to a destination block; Including, Control methods.

Images