Electro-optical device and electronic device

Abstract

To provide an electro-optical device that can reduce power consumed by parasitic capacitance of data lines.SOLUTION: A pixel circuit 110 includes an OLED that emits light with luminance in accordance with current flowing from an anode to a cathode, and a transistor that supplies current to the OLED in accordance with voltage between a gate node and a source node. A control circuit 30 supplies the gate node with a potential corresponding to the gray level through a data line 14 during a write period of a first frame, and performs a reset operation in odd-numbered rows and a non-reset operation in even-numbered rows during an initialization period prior to the write period. The reset operation is to supply a potential Vorst through the data line 14, and the non-reset operation is to electrically disconnect the anode of the OLED from the data line 14.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] In recent years, various electro-optical devices using light-emitting elements such as organic light-emitting diodes (hereinafter referred to as "OLEDs") have been proposed. In electro-optical devices, a pixel circuit including the light-emitting elements and transistors for driving the light-emitting elements is generally provided in correspondence with the pixels of an image to be displayed, at the intersections of scanning lines and data lines.

[0003] In such a configuration, when a data signal with a potential corresponding to the grayscale level of a pixel is supplied to the gate node of the transistor, the transistor supplies a current corresponding to the voltage between the gate node and the source node to the light-emitting element. This causes the light-emitting element to emit light with a luminance corresponding to the grayscale level. A configuration having four transistors, including a transistor that drives the light-emitting element, is known as a pixel circuit (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-179628 Summary of the Invention [Problem to be solved by the invention]

[0005] When an electro-optical device is miniaturized and applied to a portable device, there is a strong demand for low power consumption due to battery etc. However, the above-mentioned configuration has a problem in that the power consumption is not sufficiently low. [Means for solving the problem]

[0006] In order to solve the above problem, an electro-optical device according to one embodiment of the present disclosure includes a first pixel circuit provided corresponding to a data line and a first scanning line, a second pixel circuit provided corresponding to the data line and a second scanning line, and a control circuit that controls the first pixel circuit and the second pixel circuit, the first pixel circuit including a first light-emitting element that emits light with a luminance corresponding to a current flowing between two electrodes, and a first transistor that causes a current corresponding to a voltage between a potential of a gate node and a potential of a source node to flow to the first light-emitting element, the second pixel circuit including a second light-emitting element that emits light with a luminance corresponding to the current flowing between the two electrodes, a second transistor that causes a current corresponding to the voltage between the potential of the gate node and a potential of a source node to flow to the second light-emitting element, and a third transistor that electrically connects the data line and one of two electrodes in the second light-emitting element. the control circuit supplies a potential corresponding to a gradation level to a gate node of the first transistor via the data line during a first write period of a first horizontal scanning period in which the first scanning line is selected in a first frame, and performs a first operation during a first initialization period before the first write period; supplies a potential corresponding to the gradation level to a gate node of the second transistor via the data line during a second write period of a second horizontal scanning period in which the second scanning line is selected, and performs a second operation during a second initialization period before the second write period, the first operation being an operation of supplying a first potential different from the potential corresponding to the gradation level to one of the two electrodes via the data line, and the second operation being an operation of turning off the third transistor and causing the potential of the data line to be a potential between the first potential and the second potential. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a perspective view of an electro-optical device. [Diagram 2] FIG. 2 is a block diagram showing an electrical configuration of the electro-optical device. [Diagram 3] FIG. 2 is a diagram illustrating a pixel circuit of the electro-optical device. [Figure 4]4 is a timing chart showing the operation of the electro-optical device according to the first embodiment. [Diagram 5] 4 is a timing chart showing the operation of the electro-optical device according to the first embodiment. [Figure 6] 5A to 5C are diagrams illustrating the operation of the electro-optical device according to the first embodiment. [Figure 7] 5A to 5C are diagrams illustrating the operation of the electro-optical device according to the first embodiment. [Figure 8] 5A to 5C are diagrams illustrating the operation of the electro-optical device according to the first embodiment. [Figure 9] 5A to 5C are diagrams illustrating the operation of the electro-optical device according to the first embodiment. [Figure 10] 5A to 5C are diagrams illustrating the operation of the electro-optical device according to the first embodiment. [Figure 11] 5A to 5C are diagrams illustrating the operation of the electro-optical device according to the first embodiment. [Figure 12] FIG. 4 is a diagram showing a potential range in a writing period in the first embodiment. [Figure 13] 5A to 5C are diagrams illustrating a comparison of displays by electro-optical devices according to the first embodiment and the like. [Figure 14] 10 is a timing chart showing the operation of the electro-optical device according to the second embodiment. [Figure 15] 10 is a timing chart showing the operation of the electro-optical device according to the second embodiment. [Figure 16] 10A to 10C are diagrams illustrating the operation of the electro-optical device according to the second embodiment. [Figure 17] 10 is a timing chart showing the operation of the electro-optical device according to the third embodiment. [Figure 18] 10 is a timing chart showing the operation of the electro-optical device according to the third embodiment. [Figure 19] FIG. 1 is a perspective view showing a head mounted display using an electro-optical device. [Figure 20] FIG. 2 is a diagram showing an optical configuration of a head mounted display. [Figure 21] 10 is a timing chart showing the operation of an electro-optical device according to a second comparative example. [Figure 22] 10 is a timing chart showing the operation of an electro-optical device according to a second comparative example. [Figure 23] 10A and 10B are diagrams illustrating the operation of an electro-optical device according to a second comparative example. [Figure 24] 10A and 10B are diagrams illustrating the operation of an electro-optical device according to a second comparative example. [Diagram 25] 10A and 10B are diagrams illustrating the operation of an electro-optical device according to a second comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Hereinafter, electro-optical devices according to embodiments will be described with reference to the drawings. In each drawing, the dimensions and scale of each part are appropriately different from the actual ones. In addition, the embodiments described below are preferred specific examples, and therefore various technically preferable limitations are attached, but the scope of the present disclosure is not limited to these forms unless otherwise specified in the following description to the effect that the present disclosure is limited.

[0009] FIG. 1 is a perspective view showing an electro-optical device 10 according to an embodiment. The electro-optical device 10 is a micro display panel that displays an image in, for example, a head mounted display. The electro-optical device 10 includes a pixel circuit including an OLED, a drive circuit for driving the pixel circuit, and the like. The pixel circuit, the drive circuit, and the like are integrated on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but may be another type of semiconductor substrate.

[0010] The electro-optical device 10 is housed in a frame-shaped case 192 that opens in the display region 100. The electro-optical device 10 is connected to one end of an FPC board 194. FPC is an abbreviation for Flexible Printed Circuits. The other end of the FPC board 194 is provided with a plurality of terminals 196 that are connected to a host device (not shown). When the plurality of terminals 196 are connected to the host device, video data, synchronization signals, and the like are supplied to the electro-optical device 10 from the host device via the FPC board 194.

[0011] In the figure, the X direction indicates the extension direction of the scanning lines in the electro-optical device 10, and the Y direction indicates the extension direction of the data lines. The two-dimensional plane defined by the X and Y directions is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X and Y directions and is the emission direction of the light emitted from the OLED.

[0012] 2 is a block diagram showing an electrical configuration of the electro-optical device 10. As shown in the figure, the electro-optical device 10 includes a control circuit 30, a data signal output circuit 50, an auxiliary circuit 60, n capacitive elements 70, an initialization circuit 80, a display area 100, and a scanning line driving circuit 120. In the display area 100, m rows of scanning lines 12 are provided along the X direction in the drawing, and n columns of data lines 14 are provided along the Y direction so as to be electrically insulated from each of the scanning lines 12. Here, m and n are integers of 2 or more.

[0013] In the display region 100, pixel circuits 110 are provided corresponding to the intersections of m rows of scanning lines 12 and n columns of data lines 14. Therefore, the pixel circuits 110 are arranged in a matrix of m rows and n columns. In order to distinguish the rows of the matrix arrangement, they may be referred to as 1, 2, 3, ..., (m-1), mth row from the top in the figure. Similarly, in order to distinguish the columns of the matrix, they may be referred to as 1, 2, 3, ..., (n-1), nth column from the left in the figure. Integers (i-1) and i, which are 1 to m, are used to generally describe the scan lines 12. In particular, (i-1) may be used as an odd number to generally describe odd-numbered (1, 3, 5, ...) rows, and i may be used as an even number to generally describe even-numbered (2, 4, 6, ...) rows. In addition, an integer j, which is 1 to n, is used to generally describe the data lines 14.

[0014] The control circuit 30 controls each unit based on video data Vid and a synchronous signal Sync supplied from a host device. The video data Vid specifies the gradation level of pixels in an image to be displayed, for example, in 8 bits. The synchronization signal Sync includes a vertical synchronization signal that instructs the start of vertical scanning of the video data Vid, a horizontal synchronization signal that instructs the start of horizontal scanning, and a dot clock signal that indicates the timing of one pixel of the video data.

[0015] In this embodiment, the pixels of an image to be displayed and the pixel circuits 110 in the display area 100 correspond one-to-one. The brightness characteristic indicated by the grayscale level in the video data Vid supplied from the host device does not necessarily match the luminance characteristic of the OLED included in the pixel circuit 110. Therefore, in order to make the OLED emit light at a brightness corresponding to the grayscale level specified by the video data Vid, the control circuit 30 up-converts the 8 bits of the video data Vid to, for example, 10 bits in the embodiment and outputs it as the video data Vdata. Therefore, the 10-bit video data Vdata also specifies a grayscale level. In other words, the video data Vdata specifies a grayscale level obtained by converting the grayscale level specified by the video data Vid.

[0016] For up-conversion, a look-up table is used that stores in advance the correspondence between, for example, 8 bits of input video data Vid and 10 bits of output video data Vdata. The control circuit 30 also generates various control signals to control each unit, which will be described in detail later.

[0017] The scanning line driving circuit 120 is a circuit for outputting various signals to drive the pixel circuits 110 arranged in m rows and n columns, row by row, under the control of the control circuit 30. For example, the scanning line driving circuit 120 supplies scanning signals / Gwr(1), / Gwr(2), ..., / Gwr(m-1), / Gwr(m) to the 1st, 2nd, 3rd, ..., (m-1), mth scanning lines 12 in order. In general, the scanning signal supplied to the (i-1)th scanning line 12 is represented as / Gwr(i-1). The scanning line driving circuit 120 outputs various control signals in addition to the scanning signals / Gwr(1) to / Gwr(m), which will be described in detail later.

[0018] The data signal output circuit 50 is a circuit that outputs a signal of a voltage according to luminance to the pixel circuits 110 located in a row selected by the scanning line driving circuit 120. In detail, the data signal output circuit 50 includes a selection circuit group 52, a first latch circuit group 54, a second latch circuit group 56, and n DA conversion circuits 500. The selection circuit group 52 includes selection circuits 520 in one-to-one correspondence with the n columns, the first latch circuit group 54 includes first latch circuits L1 in one-to-one correspondence with the n columns, and the second latch circuit group 56 includes second latch circuits L2 in one-to-one correspondence with the n columns. Also, the n DA conversion circuits 500 are in one-to-one correspondence with the n columns.

[0019] That is, a set of a selection circuit 520, a first latch circuit L1, a second latch circuit L2, and a DA conversion circuit 500 is provided corresponding to each example. Here, the selection circuit 520 of the jth column instructs the first latch circuit L1 of the jth column to select the video data of the jth column from the video data Vdata output from the control circuit 30, and the first latch circuit L1 of the jth column latches the video data Vdata according to the instruction. The second latch circuit L2 of the jth column outputs the video data Vdata latched by the first latch circuit L1 of the jth column to the DA conversion circuit 500 of the jth column in a writing period (C) described later according to the control of the control circuit 30.

[0020] The j-th column DA conversion circuit 500 converts the 10-bit video data Vdata output from the j-th column second latch circuit L2 into an analog signal and outputs it to the j-th column data signal output line 14c. In other words, the data signal output line 14c is provided in one-to-one correspondence with the data line 14, and the output terminal of the j-th column DA conversion circuit 500 is connected to the j-th column data signal output line 14c.

[0021] The auxiliary circuit 60 is a collection of transistors 62 provided in one-to-one correspondence with the data signal output lines 14c. The source node of the transistor 62 corresponding to the jth column is connected to a power supply line of potential Vref, and the drain node of the transistor 62 is connected to the jth data signal output line 14c. A control signal / Gref output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 62 in each column.

[0022] The n capacitive elements 70 are provided in one-to-one correspondence with pairs of data signal output lines 14c and data lines 14. In particular, one end of the capacitive element 70 in the jth column is connected to the data signal output line 14c in the jth column, and the other end of the capacitive element 70 in the jth column is connected to the data line 14 in the jth column. The video data Vdata corresponds to a gradation level specified by the video data Vid, and the DA conversion circuit 500 converts the video data Vdata into an analog signal, which is supplied as a data signal to the data line 14 via the capacitive element 70. Therefore, the potential of the data signal supplied to the data line 14 corresponds to the gradation level specified by the video data Vid and the video data Vdata.

[0023] The initialization circuit 80 is a collection of pairs of transistors 82 , 84 and 86 provided in one-to-one correspondence with the data lines 14 . A source node of the transistor 82 corresponding to the j-th column is connected to a power supply line of potential Vel, and a drain node of the transistor 82 is connected to the data line 14 of the j-th column. A control signal / Drst output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 82 in each column. The potential Vel is used as a high-level potential of the power supply voltage. In this embodiment, the control signal / Drst is always at H level, so the transistors 82 in each column are always off. Therefore, in this embodiment, the transistors 82 have no electrical meaning. However, they are provided for the purpose of comparison with a second comparative example described later.

[0024] A source node of the transistor 84 corresponding to the j-th column is connected to a power supply line of potential Vini, and a drain node of the transistor 84 is connected to the j-th column data line 14. A control signal / Gini output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 84 in each column.

[0025] The source node of the transistor 86 corresponding to the j-th column is connected to a power supply line of the potential Vorst, and the drain node of the transistor 86 is connected to the data line 14 of the j-th column. A control signal / Grst output from the control circuit 30 is commonly supplied to the gate nodes of the transistors 86 in each column. The potential Vorst is, for example, the potential Gnd or a low potential close to the potential Gnd. Specifically, the potential Vorst is a potential at which no current flows through the OLED if power is supplied to the anode of the OLED. The potential Gnd is a ground potential, which is a reference potential of zero voltage.

[0026] A capacitance component parasitic on each data line 14 of each column. In the figure, the capacitance component is represented as a parasitic capacitance 72. That is, the parasitic capacitance 72 is represented electrically as a capacitance element having one end connected to the data line 14 and the other end connected to a power supply line having a constant potential, for example, a potential Gnd. In addition, in the figure, the potentials of the data lines 14 in the 1st, 2nd, ..., (n-1), and nth columns are denoted as Vd(1), Vd(2), ..., Vd(n-1), and Vd(n), respectively. In general, the potential of the data line 14 in the jth column is denoted as Vd(j).

[0027] 3 is a circuit diagram showing a pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are electrically identical to one another. For this reason, the pixel circuits 110 will be described by taking the pixel circuit 110 located in the odd-numbered row (i-1) and column j as a representative.

[0028] As shown in the figure, the pixel circuit 110 includes an OLED 130, p-type transistors 121 to 124, and a capacitance element 140. The transistors 121 to 124 are, for example, MOS type. Note that MOS is an abbreviation for Metal-Oxide-Semiconductor field-effect transistor. In addition, the pixel circuit 110 in the (i-1)th row is supplied with the control signals / Gel(i-1) and / Gcmp(i-1) from the scanning line driving circuit 120 in addition to the scanning signal / Gwr(i-1) corresponding to the (i-1)th row.

[0029] Control signal / Gel(i-1) is a generalized representation of control signals / Gel(1), / Gel(2), ..., / Gel(m-1), / Gel(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows. Similarly, control signal / Gcmp(i-1) is a generalized representation of control signals / Gcmp(1), / Gcmp(2), ..., / Gcmp(m-1), / Gcmp(m) that are supplied in sequence corresponding to the 1st, 2nd, ..., (m-1), mth rows.

[0030] The OLED 130 is a light-emitting element in which a light-emitting functional layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 is optically transparent. In the OLED 130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, thereby emitting white light.

[0031] In the case of color display, the generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective semi-transmissive layer (not shown), and is emitted at a resonant wavelength set corresponding to one of the colors R (red), G (green), and B (blue). A color filter corresponding to the color is provided on the light emission side from the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and the color filter in order, and is visually recognized by the observer. Note that the optical resonator is not shown. In addition, when the electro-optical device 10 simply displays a monochromatic image of light and dark only, the optical resonator and the color filter are omitted.

[0032] In the transistor 121 of the pixel circuit 110 in the (i-1)th row and jth column, the gate node g is connected to the drain node of the transistor 122, the source node s is connected to the power supply line 116 to which the potential Vel is supplied, and the drain node d is connected to the source node of the transistor 123 and the source node of the transistor 124. In the capacitance element 140, one end is connected to the gate node g of the transistor 121, and the other end is connected to the power supply line 116. Therefore, the capacitance element 140 holds the voltage between the gate node g and the source node s of the transistor 121. The other end of the capacitive element 140 may be connected to a power supply line of a different potential other than the power supply line 116 of the potential Vel, as long as the potential is kept substantially constant.

[0033] In the embodiment, a so-called MOS capacitance formed by sandwiching a gate insulating layer of a transistor between a semiconductor layer (lower electrode) and a gate electrode layer (upper electrode) of a transistor is used as the capacitance element 140. Note that a parasitic capacitance of the gate node g of the transistor 121 may be used as the capacitance element 140, or a so-called metal capacitance formed by sandwiching an insulating layer between different conductive layers in a semiconductor substrate may be used.

[0034] In the transistor 122 of the pixel circuit 110 in the (i-1)th row and jth column, a gate node is connected to the (i-1)th row scanning line 12, and a source node is connected to the jth column data line 14. In the transistor 123 of the pixel circuit 110 in the (i-1)th row and jth column, a control signal / Gcmp(i-1) is supplied to a gate node, and a drain node is connected to the jth column data line 14. In the transistor 124 of the pixel circuit 110 in the (i-1)th row and jth column, a control signal / Gel(i-1) is supplied to a gate node, and a drain node is connected to the pixel electrode 131 which is the anode of the OLED 130. A potential Vct is supplied to the common electrode 133 that functions as the cathode of the OLED 130. Note that the potential Vct is, for example, the potential Gnd or a low potential close to the potential Gnd. In such a pixel circuit 110, a series connection of transistors 123 and 124 is provided in the path from the data line 14 to the pixel electrode 131, and a transistor 124 is provided between the drain node d of the transistor 121 and the pixel electrode 131.

[0035] In this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements, and includes, for example, coupling between two or more elements in a semiconductor substrate through different wiring layers and contact holes even if the elements are not directly connected to each other. Although the pixel circuit 110 in the odd-numbered (i-1) row and j column has been described here, the pixel circuit 110 in the even-numbered i row and j column has a similar configuration. However, in the pixel circuit 110 in the even-numbered i row and j column, a control signal / Gwr(i) is supplied to the gate node of transistor 122, a control signal / Gcmp(i) is supplied to the gate node of transistor 123, and a control signal / Gel(i) is supplied to the gate node of transistor 124.

[0036] The control circuit 30 controls driving of the pixel circuit 110 via the data signal output circuit 50, the auxiliary circuit 60, the initialization circuit 80, and the scanning line drive circuit 120. For this reason, the control circuit 30, the data signal output circuit 50, the auxiliary circuit 60, the initialization circuit 80, and the scanning line drive circuit 120 may be collectively referred to as a control circuit in a broad sense that controls the pixel circuit 110.

[0037] Next, the operation of the electro-optical device 10 will be described.

[0038] 4 and 5 are timing charts illustrating the operation of the electro-optical device. Of these, FIG. 4 is a timing chart for an odd-numbered frame (V_odd), and FIG. 5 is a timing chart for an even-numbered frame (V_even).

[0039] In this description, an odd frame (V_odd) refers to the frame that precedes the other of two consecutive frames, and an even frame (V_even) refers to the frame that follows the other of two consecutive frames. One frame refers to the period required to display one frame of an image specified by video data Vid. When the time length of one frame is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the synchronization signal Sync is 60 Hz, it is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal.

[0040] In the electro-optical device 10, in each of the odd-numbered frames (V_odd) and even-numbered frames (V_odd), the m scanning lines 12 are selected one by one in the order of 1st, 2nd, 3rd, ..., mth row and horizontally scanned. The period required for horizontal scanning of one row is the horizontal scanning period (H).

[0041] In the electro-optical device 10, the horizontal scanning period (H) is divided, in order of time, into an initialization period (A), a compensation period (B), and a writing period (C). Of these, the initialization period (A) is further divided into three initialization periods (A1), (A2), and (A3). In addition to the initialization period (A), the compensation period (B), and the writing period (C), the operation of the pixel circuit 110 further includes a light emission period (D). The initialization period (A1) in this embodiment is a period provided intentionally for the purpose of comparison with a second comparative example described later, and may not actually be required.

[0042] The initialization period (A2) is a period in which the anode potential of either the odd-numbered rows or the even-numbered rows in the OLED 130 is reset. Note that, in the initialization period (A2), the anode potential of the OLED 130 is not reset in the other of the odd-numbered rows or the even-numbered rows. The initialization period (A3) is a period for supplying the potential Vini for turning on the transistor 121 to the gate node g. The compensation period (B) is a period for causing the gate node g of the transistor 121 to converge to a potential corresponding to the threshold voltage of the transistor 121. The write period (C) is a period during which a potential corresponding to the gradation level is held (written) at the gate node g of the transistor 121, and more specifically, is a period during which the gate node g of the transistor 121 is changed from a potential corresponding to the threshold voltage by an amount corresponding to a voltage corresponding to the current flowing through the OLED 130. The light emitting period (D) is a period for causing a current corresponding to the potential of the gate node g held in the writing period (C) to flow through the OLED 130 to emit light.

[0043] As described above, in the embodiment, there is a division into odd frames (V_odd) and even frames (V_odd). Moreover, the operation of each row in the horizontal scanning period (H) is common except that it differs between odd-numbered rows and even-numbered rows in the initialization period (A2). The operation of the pixel circuits 110 in columns 1 to n of a row scanned in a certain horizontal scanning period (H) is common. Therefore, in the following, the operation of the odd frame (V_odd) will be described first, and then the operation of the even frame (V_even) will be described. Also, in each frame, the horizontal scanning period (H_odd) of the odd (i-1)th row and the operation of the pixel circuit 110 in the (i-1)th row and jth column will be described first, and then the horizontal scanning period (H_even) of the even ith row and the operation of the pixel circuit 110 in the ith row and jth column will be described.

[0044] In an odd-numbered frame (V_odd), during the initialization period (A2) of each horizontal scanning period (H), the control signal / Gini is at H level and the control signal / Gref is at L level, so that the transistors 84 in each column are turned off and the transistors 62 in each column are turned on. In the initialization period (A2), the control signal / Grst is at level L. As a result, the transistors 86 in each column are turned on.

[0045] In the initialization period (A2) of the horizontal scanning period (H_odd) in the odd-numbered (i-1)th row, the scanning signal / Gwr(i-1) is at H level, the control signal / Gcmp(i-1) is at L level, and the control signal / Gel(i-1) is at L level. Therefore, in the initialization period (A2), in the pixel circuit 110 in the (i-1)th row and jth column, the transistor 122 is in the off state, the transistor 123 is in the on state, and the transistor 124 is in the on state.

[0046] Therefore, in the initialization period (A2), as shown in FIG. 6, the anode of the OLED 130 in the pixel circuit 110 in the (i-1)th row and jth column is reset to the potential Vorst via the transistors 124 and 123, the jth column data line 14, and the transistor 86 in that order, that is, a reset operation is performed.

[0047] In the initialization period (A2), the transistor 86 in each column is in the on state, and the transistor 62 in each column is in the on state, so that the data line 14 in each column is at the potential Vorst, and the data signal output line 14c is at the potential Vref. Therefore, in each column, the voltage across the capacitive element 70 becomes |Vref-Vorst|, and one end of the parasitic capacitance 72 is held at the potential Vorst.

[0048] In an odd frame (V_odd), during the initialization period (A3) of each horizontal scanning period (H), the control signal / Gini changes to L level and the control signal / Gref maintains L level. As a result, the transistors 84 in each column change to the ON state and the transistors 62 in each column maintain the ON state. In addition, in the initialization period (A3), the control signal / Grst changes to H level, causing the transistors 86 in each column to change to the off state.

[0049] In the initialization period (A3) of the horizontal scanning period (H_odd) in the odd-numbered (i-1) row, the scanning signal / Gwr(i-1) changes to the L level, the control signal / Gcmp(i-1) changes to the H level, and the control signal / Gel(i-1) changes to the H level. Therefore, in the initialization period (A3), in the pixel circuit 110 in the (i-1) row and j column, the transistor 122 changes to the ON state, the transistor 123 changes to the OFF state, and the transistor 124 changes to the OFF state.

[0050] Therefore, during the initialization period (A3), as shown in FIG. 8, in the pixel circuit 110 in the (i-1)th row and jth column, the potential Vini is supplied to one end of the capacitance element 140 and to the gate node g of the transistor 121 via the transistor 84, the jth column data line 14, and the transistor 122, in that order.

[0051] In the initialization period (A3) of the horizontal scanning period (H_odd) of the odd-numbered (i-1)th row in the odd-numbered frame (V_odd), the transistor 84 in each column is in the on state, and the transistor 62 in each column maintains the on state. Therefore, in the initialization period (A3) of the horizontal scanning period (H_odd), the data line 14 in each column becomes the potential Vini, and the data signal output line 14c maintains the potential Vref from the initialization period (A2). Therefore, in each column, the voltage across the capacitive element 70 is |Vini-Vref|, and one end of the parasitic capacitance 72 is held at the potential Vini. The potentials Vini and Vorst are expressed as follows: Vini>Vorst This is the relationship. As a result, the capacitive element 70 and the parasitic capacitance 72 become charged.

[0052] In the odd frame (V_odd), in the compensation period (B) of each horizontal scanning period (H), the control signal / Gini changes to H level and the control signal / Gref maintains L level. As a result, the transistors 84 in each column change to the OFF state and the transistors 62 in each column maintain the ON state. During the compensation period (B), the control signal / Grst is maintained at the H level, so that the transistors 86 in each column are maintained in the off state.

[0053] In the compensation period (B) of the horizontal scanning period (H_odd) of the odd-numbered (i-1) row, the scanning signal / Gwr(i-1) maintains the L level, the control signal / Gcmp(i-1) changes to the L level, and the control signal / Gel(i-1) maintains the H level. As a result, in the pixel circuit 110 in the (i-1) row and j column, the transistor 122 maintains the ON state, the transistor 123 changes to the ON state, and the transistor 124 maintains the OFF state.

[0054] At the start of the compensation period (B), in the pixel circuit 110 in the (i-1)th row, the gate node g of the transistor 121 is at the potential Vini. When the transistor 123 is turned on while the gate node g is at the potential Vini, the transistor 121 is in a diode-connected state, that is, the gate node g and the drain node d are connected to each other.

[0055] 9, in the compensation period (B), the voltage between the gate node g and the source node s of the transistor 121 converges to (a voltage close to) the threshold voltage Vth of the transistor 121. That is, the potentials of the gate node g of the transistor 121 and the data line 14 approach the threshold equivalent potential (Vel-Vth).

[0056] During the compensation period (B) of the (i-1)th row, the transistors 62 in each column are maintained in the on state, so that the data signal output lines 14c in each column are maintained at the potential Vref. Furthermore, since the data line 14 converges to the potential equivalent to the threshold voltage (Vel-Vth), the voltage across the capacitive element 70 becomes |Vel-Vth-Vref|, and one end of the parasitic capacitance 72 is held at the potential equivalent to the threshold voltage (Vel-Vth).

[0057] In an odd frame (V_odd), during a writing period (C) of each horizontal scanning period (H), the control signal / Gini maintains the H level, and the control signal / Gref changes to the H level. As a result, the transistors 84 in each column maintain the off state, and the transistors 62 in each column change to the off state. During the write period (C), the control signal / Grst is maintained at the H level, so that the transistors 86 in each column are maintained in the off state.

[0058] In the writing period (C) of the horizontal scanning period (H_odd) of the (i-1)th row, the scanning signal / Gwr(i-1) maintains the L level, the control signal / Gcmp(i-1) changes to the H level, and the control signal / Gel(i-1) maintains the H level. As a result, in the pixel circuit 110 of the (i-1)th row and column j, the transistor 122 maintains the ON state, the transistor 123 changes to the OFF state, and the transistor 124 maintains the OFF state.

[0059] During the writing period (C), the transistors 62 in each column are turned off. The DA conversion circuit 500 in each column is supplied with 10-bit video data Vdata corresponding to the (i-1)th row and column. Therefore, the DA conversion circuit 500 in the jth column outputs a signal of a potential corresponding to the grayscale level of the (i-1)th row and jth column to the data signal output line 14c.

[0060] 10, one end of the capacitive element 70 in the jth column rises from a potential Vref to a potential of a gradation level corresponding to the (i-1)th row and the jth column. This potential rise reaches the gate node g of the transistor 121 via the capacitive element 70, the data line 14, and the transistor 122 in this order.

[0061] The potential change amount of the gate node g in the writing period (C) is a value obtained by multiplying the potential rise amount at the data signal output line 14c, i.e., one end of the capacitance element 70, by the ratio of the capacitance value of the capacitance element 70 to the "composite capacitance value." The "composite capacitance value" here refers to the capacitance value of the composite capacitance of the capacitance element 70, the parasitic capacitance 72, and the capacitance element 140. Note that the capacitance value of the capacitance element 140 can be ignored if it is sufficiently small compared with the other capacitance values.

[0062] The potential changes of the data signal output line 14c and the data line 14 during the writing period (C) will be described with reference to FIG. The potential corresponding to the gradation level output by the DA conversion circuit 500 to the data signal output line 14c ranges from a potential Bk corresponding to the black level of the lowest gradation to a potential Wt corresponding to the white level of the highest gradation. The potential in this range is compressed to a range from a potential Vbk (≈Vel) to a potential Vwt slightly lower than the potential Vbk by the charge distribution by the capacitive element 70 and the parasitic capacitance 72, and reaches the data line 14 and the gate node g.

[0063] When the scanning signal / Gwr(i-1) changes to the H level, the writing period (C) of the (i-1)th row ends, that is, the horizontal scanning period (H_odd) of the (i-1)th row ends. When the scanning signal / Gwr(i-1) becomes the H level, the transistor 122 in the pixel circuit 110 in the (i-1)th row and jth column is turned off, but the voltage difference between the potential of the gate node g and the potential Vel of the source node s is held in the capacitance element 140.

[0064] After the writing period (C) ends, a light emitting period (D) begins. When the light emission period (E) of the (i-1)th row is reached, the control signal / Gel(i-1) is inverted to the L level, so that the transistor 124 is turned on. 11, in the light emission period (D), a current Iel according to the potential of the gate node g held by the capacitance element 140 flows through the OLED 130 in the pixel circuit 110 in the (i-1)th row and jth column through the transistor 121. As a result, the OLED 130 emits light with a luminance according to the current Iel.

[0065] In an odd frame (V_odd), the operation of the horizontal scanning period (H_even) of the even row i next to the odd (i-1) row is the same as the operation of the horizontal scanning period (H_odd) of the odd (i-1) row, except that the control signal / Grst is at H level during the initialization period (A2) and the control signal / Gcmp(i) is at H level, as shown in Figure 4. Therefore, the operation of the horizontal scanning period (H_even) of the even-numbered i-th row will be explained with emphasis on the initialization period (A2).

[0066] In the initialization period (A2) of the horizontal scanning period (H_even) of the even-numbered i-th row, the transistors 84 of each column are in the off state and the transistors 62 of each column maintain the on state, which is common to the initialization period (A2) of the horizontal scanning period (H_odd) of the odd-numbered (i-1)-th row. In the initialization period (A2) of the horizontal scanning period (H_even), for example in the j-th column, the data signal output line 14c and one end of the capacitive element 70 change from the potential in the state immediately before the initialization period (A2) of the horizontal scanning period (H_even) to the potential Vref. Here, the potential in the state immediately before is the potential in the writing period (C) in the horizontal scanning period (H_odd) of the odd-numbered (i-1)th row before the initialization period (A2), that is, the potential according to the grayscale level of the (i-1)th row and the jth column.

[0067] Here, the range of potential on the data line 14 according to the gradation level is approximately the potential Vel in the case of black display, and is a potential slightly lower than the potential Vel in the case of white display, and in either case is a relatively high potential. In the initialization period (A2) of the horizontal scanning period (H_even) of the even-numbered i-th row, unlike the initialization period (A2) of the horizontal scanning period (H_odd) of the odd-numbered (i-1)-th row, as shown in FIG. 7, the transistor 123 in the pixel circuit 110 is in an off state, so that the anode of the OLED 130 is not discharged and the data line 14 maintains a relatively high potential.

[0068] In the writing period (C) of the odd-numbered (i-1)th horizontal scanning period (H_odd), the potential of the data signal output line 14c ranges from potential Bk to potential Wt, as shown in Fig. 12, but drops to potential Vref in the initialization period (A2) of the subsequent even-numbered i-th horizontal scanning period (H_even). In the initialization period (A2), the data line 14 is not electrically connected to any part other than one end of the capacitance element 70 and one end of the parasitic capacitance 72. Therefore, when the data signal output line 14c drops from a potential in the range from potential Bk to potential Wt to ​​potential Vref, the data line 14 also drops from a potential in the range from potential Vbk to potential Vwt via the capacitive element 70. Therefore, in the initialization period (A2) in the horizontal scanning period (H_even) of the even-numbered i-th row, the data line 14 has a potential lower than the potential Vel and higher than the potential Vorst.

[0069] In this manner, in an odd frame (V_odd), during the initialization period (A2) of the horizontal scanning period (H_odd) of the odd (i-1)th row, a reset operation is executed to discharge the anode of the OLED 130, whereas during the initialization period (A2) of the horizontal scanning period (H_even) of the even i-th row, a non-reset operation is executed to not discharge the anode, and no reset operation is executed.

[0070] The main reason why a reset operation for discharging the anode of the OLED 130 is performed is as follows. In the OLED 130, the light-emitting functional layer 132, which is an organic layer, is sandwiched between the pixel electrode 131, which is the anode, and the common electrode 133, which is the cathode, so that the OLED 130 has a parasitic capacitance. As described above, in the compensation period (B), the gate node g and the drain node d (the source node of the transistor 124) of the transistor 121 are at a potential equivalent to the threshold value. Next, in the writing period (C), a potential corresponding to the grayscale level is supplied to the gate node g of the transistor 121.

[0071] If a data signal of potential Vbk corresponding to the black level of the lowest gradation (darkest level) is supplied to the gate node g, the gate node g should ideally be at potential Vel, but in reality, the potential is lower than the potential Vel. Therefore, when the transistor 124 is turned on during the light emission period (D), a leakage current flows from the source node s to the drain node d in the transistor 121. If the charge accumulated in the parasitic capacitance of the OLED 130 is not reset in advance, the leakage current will eventually fully charge the parasitic capacitance, causing a current to start flowing through the OLED 130, resulting in light emission. This phenomenon is called black floating, because even though the black level, i.e., a luminance at which no light is emitted, is specified, a slight light is emitted, and it is visually perceived as if the black is floating.

[0072] Therefore, in the initialization period (A2), the anode of the OLED 130 is set to the potential Vorst to discharge the anode in advance and reset the charge accumulated in the parasitic capacitance of the OLED 130. As a result, even if a leakage current flows through the transistor 121 in the light emission period (D), the leakage current does not fully charge the parasitic capacitance of the OLED 130, and light is not emitted, so that the so-called black floating can be suppressed.

[0073] However, a configuration in which a reset operation is performed can be a factor that hinders low power consumption. When a reset operation is performed, the data line 14, the other end of the capacitive element 70, and one end of the parasitic capacitance 72 are at a potential in the range from potential Vbk to potential Vwt in the write period (C) that is the state immediately before the initialization period (A2), are at potential Vorst in the initialization period (A2), and are at potential Vini in the initialization period (A3).

[0074] As described above, the potentials Vel, Vorst, and Vini are Vel>Vini>Vorst (≒Vct). This is the relationship. Among these, the potential Vel is a high level of the power supply voltage, and the potential Vorst is a low level of the power supply voltage, or a potential close to the potential Gnd. Therefore, when the reset operation is performed, the capacitive element 70 and the parasitic capacitance 72 are discharged from the write period (C) to the initialization period (A2), and are charged from the initialization period (A2) to the initialization period (A3). Since such a discharge->charge in the capacitive element 70 and the parasitic capacitance 72 is performed in each column, the power consumed becomes large.

[0075] The non-reset operation is the same as the reset operation in that the other end of the capacitance element 70 and one end of the parasitic capacitance 72 become a potential close to the potential Vel in the write period (C) which is the state immediately before the initialization period (A2). However, in the non-reset operation, only the parasitic capacitance 72 is electrically connected to the data line 14 in the initialization period (A2), so the discharge of the capacitance element 70 and the parasitic capacitance 72 can be ignored compared to when the reset operation is performed. Furthermore, in the reset operation and the non-reset operation, the other end of the capacitance element 70 and one end of the parasitic capacitance 72 both become the potential Vini in the initialization period (A3), but while in the reset operation, they are charged from the potential Vorst, in the non-reset operation, they are discharged by changing to the potential Vini.

[0076] That is, in the write period (C)→(A2)→(A3), the capacitive element 70 and the parasitic capacitance 72 go from large discharge to large charge in the reset operation, whereas in the non-reset operation they remain almost unchanged→small discharge. Therefore, in the non-reset operation, it is possible to reduce the power consumed by the charging and discharging of the capacitive element 70 and the parasitic capacitance 72 in each column, compared to the reset operation.

[0077] However, it should be noted that the non-reset operation causes the so-called black floating, as described above. That is, in an odd frame (V_odd), the reset operation is performed in the horizontal scanning period (H_odd) of the odd (i-1)th row, whereas the non-reset operation is performed in the horizontal scanning period (H_even) of the even i-th row, causing the black floating.

[0078] Therefore, in the embodiment, in the even frame (V_even) following the odd frame (V_odd), a non-reset operation is performed during the horizontal scanning period (H_odd) of the odd (i-1)th row, and a reset operation is performed during the horizontal scanning period (H_even) of the even i-th row, so that the row performing the reset operation and the row performing the non-reset operation are interchanged. That is, in the embodiment, in an even frame (V_even), in the horizontal scanning period (H_odd) of the odd-numbered (i-1)th row, in the initialization period (A2), a reset operation for discharging the anode of the OLED 130 is not performed, and in the horizontal scanning period (H_even) of the even-numbered i-th row, in the initialization period (A2), a reset operation is performed.

[0079] The advantages of low power consumption and reduction in display quality in this embodiment will be described.

[0080] 13 is a diagram showing a display in which the lowest grayscale black level is specified for all pixels in the first frame, that is, an all-black display is specified, and then an all-black display is specified for the second and subsequent frames in the first and second comparative examples and this embodiment. Note that in the diagram, the four frames are the first, second, third, and fourth frames in chronological order. Of the four frames, the first and third frames are odd-numbered frames (V_odd), and the second and fourth frames are even-numbered frames (V_even).

[0081] The first comparative example has a configuration in which the reset operation is performed in the initialization period (A2) without distinguishing between odd-numbered rows and even-numbered rows.

[0082] In the first comparative example, when an all-black display is specified, a reset operation is performed on all rows (Reset: Yes), so that black floating does not occur. However, power is consumed by the capacitive element 70 and the parasitic capacitance 72 due to the reset operation.

[0083] In contrast, in this embodiment, in the first frame, which is an odd frame (V_odd), a reset operation is performed during the horizontal scanning period (H_odd) of the odd rows, but a non-reset operation is performed during the horizontal scanning period (H_even) of the even rows, resulting in black floating in the even rows. However, since the next second frame is an even frame (V_even), a non-reset operation is performed during the horizontal scanning period (H_odd) of the odd rows, and a reset operation is performed during the horizontal scanning period (H_even) of the even rows.

[0084] In this embodiment, since the previous display state in the odd-numbered rows of the even-numbered frame (V_even) is a black display state after a reset operation, the anode of the OLED 130 is held at the potential of the black display state by the parasitic capacitance. Therefore, in this embodiment, if the all-black display continues, the black display will be achieved without floating black even if a non-reset operation is performed in the horizontal scanning period (H_odd) of the odd-numbered rows in the even-numbered frame (V_even). In this embodiment, since the even-numbered rows of the even-numbered frame (V_even) are displayed in black after undergoing a reset operation, no floating black occurs in the even-numbered rows.

[0085] The third frame, which follows the second frame, is an odd frame (V_odd). In the odd frame (V_odd), a reset operation is performed during the horizontal scanning period (H_odd) of odd rows, but a non-reset operation is performed during the horizontal scanning period (H_even) of even rows. However, the display state immediately before the even rows of the odd frame (V_odd) is a black display that has undergone a reset operation. Therefore, in this embodiment, if all black display continues, even if a non-reset operation is performed during the horizontal scanning period (H_even) of even rows in the odd frame (V_even), black display will be achieved without floating black. From the fourth frame onwards, the reset operation and the non-reset operation are alternately performed in the odd-numbered rows and the even-numbered rows every horizontal scanning period, and in the above case, black display is achieved without causing a floating black image.

[0086] In this embodiment, the black floating occurs only in the first frame where the display switches to all black, and is hardly noticeable to the user. Also, in this embodiment, in comparison with the first comparative example, the non-reset operation is performed in half of all the rows in one frame, so that the power consumed by the capacitive element 70 and the parasitic capacitance 72 can be reduced compared to the first comparative example.

[0087] Next, a second comparative example will be described to illustrate the superiority of the display quality in this embodiment. In the second comparative example, the data line 14 and the gate node g of the transistor 121 are reset to potential Vel during the initialization period (A1), and when a non-reset operation is performed on either the odd or even rows during the initialization period (A2), the transistors 123 and 124 are turned on.

[0088] Fig. 21 and Fig. 22 are timing charts for explaining the operation of an electro-optical device according to Comparative Example 2. Of these, Fig. 21 is a timing chart for an odd-numbered frame (V_odd), and Fig. 22 is a timing chart for an even-numbered frame (V_even). As shown in this figure, in the second comparative example, an initialization period (A1) is provided before an initialization period (A2) in each horizontal scanning period of an odd-numbered frame (V_odd) and an even-numbered frame (V_even).

[0089] In the second comparative example, the initialization period (A1) is a period for setting the transistor 121 to an OFF state. In the odd frame (V_odd), during the initialization period (A1) of each horizontal scanning period (H), the control signal / Drst is at an L level, the control signal / Gini is at an H level, and the control signal / Gref is at an L level. Therefore, during the initialization period (A1), the transistor 82 in each column is turned on, the transistor 84 in each column is turned off, and the transistor 62 in each column is turned on. In addition, in the initialization period (A1) of the horizontal scanning period (H_odd) of the odd-numbered (i-1)th row in the odd-numbered frame (V_odd), the control signal / Grst is at H level, so that the transistors 86 in each column are turned off.

[0090] In the second comparative example, during the initialization period (A1) of the horizontal scanning period (H_odd) in the odd-numbered (i-1) row, the scanning signal / Gwr(i-1) is at the L level, the control signal / Gcmp(i-1) is at the H level, and the control signal / Gel(i-1) is at the H level. Therefore, during the initialization period (A1), in the pixel circuit 110 in the (i-1) row and j column, the transistor 122 is in the ON state, the transistor 123 is in the OFF state, and the transistor 124 is in the OFF state.

[0091] 23, in the pixel circuit 110 in the (i-1)th row and jth column, a potential Vel is supplied to one end of the capacitance element 140 and to the gate node g of the transistor 121 via the transistor 82, the jth column data line 14, and the transistor 122 in that order. When the gate node g reaches the potential Vel, the voltage between the gate node g and the source node s becomes zero, and the transistor 121 is forced to enter an off state.

[0092] In addition, in the initialization period (A1), the transistor 82 in each column is in an on state, and the transistor 62 in each column is in an on state. Therefore, in the initialization period (A1), the data line 14 in each column is at the potential Vel, and the data signal output line 14c is at the potential Vref. Therefore, in each column, the voltage across the capacitive element 70 becomes |Vel-Vref|, and one end of the parasitic capacitance 72 is held at the potential Vel. Since the potential Vel is the higher level of the power supply voltage, in each column, the capacitive element 70 and the parasitic capacitance 72 are charged.

[0093] In the second comparative example, in the initialization period (A2) of each horizontal scanning period (H) of the odd frame (V_odd), the control signal / Drst changes to H level, the control signal / Gini maintains H level, and the control signal / Gref maintains L level. As a result, the transistors 82 in each column change to the OFF state, the transistors 84 in each column maintain the OFF state, and the transistors 62 in each column maintain the ON state. In addition, in the initialization period (A2) of the horizontal scanning period (H_odd) of the odd-numbered (i-1) row, the control signal / Grst changes to the L level, so that the transistors 86 in each column change to the ON state.

[0094] In the initialization period (A2), the scanning signal / Gwr(i-1) changes to H level, the control signal / Gcmp(i-1) changes to L level, and the control signal / Gel(i-1) changes to L level. Therefore, in the initialization period (A2), in the pixel circuit 110 in the (i-1)th row and jth column, the transistor 122 changes to the OFF state, the transistor 123 changes to the ON state, and the transistor 124 changes to the ON state. Therefore, in the initialization period (A2), as shown in FIG. 24, the anode of the OLED 130 in the pixel circuit 110 in the (i-1)th row and jth column is reset to the potential Vorst via the transistors 124 and 123, the jth column data line 14, and the transistor 86 in this order.

[0095] Furthermore, in the initialization period (A2), the transistor 86 in each column is in an on state, and the transistor 62 in each column maintains an on state. Therefore, in the initialization period (A2), the data line 14 in each column becomes the potential Vorst, and the data signal output line 14c continues to maintain the potential Vref from the initialization period (A1). Therefore, in each column, the voltage across the capacitive element 70 becomes |Vorst-Vref|, and one end of the parasitic capacitance 72 is held at the potential Vorst. The potentials Vel and Vorst are expressed as follows: Vel>Vorst Since this relationship holds, the capacitive element 70 and the parasitic capacitance 72 in the j-th column are discharged.

[0096] In the second comparative example, in the odd-numbered frame (V_odd), the operation after the initialization period (A3) in the horizontal scanning period (H_odd) of the odd-numbered (i-1)th row is common to the first embodiment.

[0097] In the second comparative example, the operation of the initialization period (A1) of the horizontal scanning period (H) of the even-numbered i-th row next to the odd-numbered (i-1) row in the odd-numbered frame (V_odd) is the same as the initialization period (A1) of the odd-numbered (i-1) row. That is, in the initialization period (A1) of the horizontal scanning period (H) of the even-numbered i-th row, a potential Vel is set to the data line 14 and the gate node g of the transistor 121 in the pixel circuit 110 of the i-th row.

[0098] In the second comparative example, the operation of the initialization period (A2) of the horizontal scanning period (H) of the even-numbered i-th row of an odd-numbered frame (V_odd) is the same as that of the initialization period (A2) of the odd-numbered (i-1)-th row, except that the control signal / Grst is maintained at the H level. Therefore, in the initialization period (A2) of the even-numbered i-th row, the transistor 86 is turned off.

[0099] In the immediately preceding initialization period (A 1 ), the data line 14 is at the potential Vel, and the potential Vel is held at the other end of the capacitive element 70 and one end of the parasitic capacitance 72 . Furthermore, in the initialization period (A2) of the horizontal scanning period (H_even), in the pixel circuit 110 in the i-th row and j-th column, the transistor 122 changes to the off state, the transistor 123 changes to the on state, and the transistor 124 changes to the on state. For this reason, as shown in FIG. 25 , in the OLED 130 in the pixel circuit 110 in the i-th row and j-th column, charges flow out from the capacitive element 70 and the parasitic capacitance 72, and the flowed-out charges are directed toward the OLED 130 via the data line 14, the transistors 123 and 124 in this order.

[0100] When the parasitic capacitance of the OLED 130 is fully charged due to the charge flowing out from the capacitive element 70 and the parasitic capacitance 72, the charge overflows and flows into (the light-emitting functional layer 132 of) the OLED 130, causing the OLED 130 to emit light. In addition, the charge outflow causes the capacitive element 70 and the parasitic capacitance 72 in the jth column to discharge, and the data line 14 drops from the potential Vel. This discharge is only a small amount, and is only sufficient to distribute the charge to the parasitic capacitance of the OLED 130 via the jth data line 14. For this reason, during the initialization period (A2) of the horizontal scanning period of the even-numbered i-th row, the anode of the j-th data line 14 and the i-th column pixel circuit 110 drops slightly from potential Vel to a potential between potential Vorst and potential Vel, but it is safe to say that it is approximately at potential Vel.

[0101] Thus, in the second comparative example, in an odd frame (V_odd), in the horizontal scanning period (H_odd) of the odd (i-1)th row, a reset operation for discharging the anode of OLED 130 is performed in the initialization period (A2), and in the horizontal scanning period (H_even) of the even i-th row, a reset operation is not performed in the initialization period (A2). In the second comparative example, in an even frame (V_even), during the initialization period (A2) of the horizontal scanning period (H_odd) of the odd (i-1)th row, a reset operation for discharging the anode of the OLED 130 is not performed, and during the initialization period (A2) of the horizontal scanning period (H_even) of the even i-th row, a reset operation is performed.

[0102] The embodiment and the second comparative example are common in that in the initialization period (A2), a reset operation is performed on either the odd-numbered rows or the even-numbered rows, and a reset operation is not performed on the other of the odd-numbered rows or the even-numbered rows. However, in the second comparative example, even if the reset operation is not performed in the initialization period (A2), as shown in FIG. 25, the charges flowing out from the capacitive element 70 and the parasitic capacitance 72 flow into the OLED 130, causing the OLED 130 to emit light. For this reason, as shown in FIG. 13, when an all-black display is specified for multiple consecutive frames, rows for which the reset operation is not performed in the second comparative example emit a small amount of light, which is perceived as black floating, resulting in a decrease in display quality. In contrast, in the embodiment, the black floating occurs only in the first frame where the display switches to all black, and is hardly noticeable to the user. Therefore, the embodiment is superior to the second comparative example in terms of suppressing the deterioration of display quality.

[0103] In addition, in the second comparative example, during the initialization period (A1), charging of the capacitive element 70 and the parasitic capacitance 72 occurs in each column, whereas in this embodiment, such charging does not occur, and therefore, from the viewpoint of achieving low power consumption, this embodiment is superior to the second comparative example.

[0104] Note that Figure 13 also shows a display in which the highest grayscale white level is specified for all pixels in the first frame in the first comparative example, the second comparative example, and this embodiment, i.e., an all-white display is specified, and from the second frame onwards, an all-white display is continuously specified. In the first comparative example, the reset operation is performed on all rows, so that no adverse effects due to black floating occur. In the second comparative example and the embodiment, when all white is displayed, the reset operation is not performed on either the odd-numbered rows or the even-numbered rows. In the rows where the reset operation is not performed, floating black occurs, but even if the rows emit light at a slightly brighter luminance when the rows are already emitting light at a bright luminance, the difference cannot be visually recognized. Therefore, when displaying all white, there is no difference in display between the first comparative example, the second comparative example, and the embodiment. However, in this embodiment, when all white display is performed, the reset operation is not performed on half of all the rows, so that the power consumed by the capacitive element 70 and the parasitic capacitance 72 can be reduced.

[0105] Next, a second embodiment will be described. The configuration of the electro-optical device 10 according to the second embodiment is the same as that of the first embodiment shown in FIGS. 2 and 3, but differs from that of the first embodiment in the non-reset operation. In detail, in the first embodiment, during the horizontal scanning period (H_odd) of the even-numbered i-th row in the odd-numbered frame (V_odd) as shown in Fig. 4, the control signal / Gcmp(i) is set to H level and the transistor 123 is set to the OFF state during the initialization period (A2) of the horizontal scanning period (H_odd) of the odd-numbered (i-1)-th row in the even-numbered frame (V_even) as shown in Fig. 5.

[0106] In contrast, in the second embodiment, as shown in FIG. 14, during the horizontal scanning period (H_odd) of the even-numbered i-th row in an odd-numbered frame (V_odd), during the initialization period (A2), the control signal / Gcmp(i) is set to an L level to turn on transistor 123, and instead the control signal / Gel(i) is set to an H level to turn off transistor 124. Similarly, in the second embodiment, as shown in FIG. 15, during the horizontal scanning period (H_odd) of the odd (i-1) row in an even frame (V_even), during the initialization period (A2), the control signal / Gcmp(i-1) is set to an L level to turn on the transistor 123, and instead the control signal / Gel(i-1) is set to an H level to turn off the transistor 124.

[0107] According to the second embodiment, during the initialization period (A2) of the horizontal scanning period (H_even) of the even-numbered i-th row in an odd-numbered frame (V_odd), as shown in FIG. 16 , in the pixel circuit 110 in the i-th row and j-th column, the anode of the OLED 130 is disconnected from the data line 14 by the off state of the transistor 124, not the transistor 123. Similarly, although not shown, during the initialization period (A2) of the horizontal scanning period (H_odd) of the odd-numbered (i-1) row in an even-numbered frame (V_even), the anode of the OLED 130 in the pixel circuit 110 in the (i-1) row and j column is disconnected from the data line 14 due to the off state of the transistor 124.

[0108] Therefore, according to the second embodiment, as in the first embodiment, the reset operation and the non-reset operation are alternately performed in the odd-numbered rows and the even-numbered rows every horizontal scanning period, so that the power consumption can be reduced compared to the first comparative example, and the power consumed by the capacitive element 70 and the parasitic capacitance 72 can be reduced compared to the first comparative example. Furthermore, according to the second embodiment, when an all black display continues over several frames, the occurrence of black floating is not noticeable except for the frame immediately after switching, so that deterioration of display quality can be suppressed compared to the second comparative example.

[0109] Next, a third embodiment will be described. 2 and 3, the configuration of the electro-optical device 10 according to the third embodiment is the same as that of the first embodiment shown in Fig. 2 and 3, but the non-reset operation is different from either the first or second embodiment. That is, in the first or second embodiment, one of the transistors 123 or 124 of the pixel circuit 110 in which the non-reset operation is executed is turned off, but in the third embodiment, both the transistors 123 and 124 are turned off.

[0110] In detail, in the third embodiment, as shown in FIG. 17, during the horizontal scanning period (H_odd) of the even-numbered i-th row in an odd-numbered frame (V_odd), during the initialization period (A2), the control signals / Gcmp(i) and / Gel(i) are set to H level, and the transistors 123 and 124 are turned off. Similarly, in the third embodiment, as shown in FIG. 18, during the horizontal scanning period (H_odd) of the odd-numbered (i-1) row in an even frame (V_even), during the initialization period (A2), the control signals / Gcmp(i) and / Gel(i) are set to the H level, and the transistors 123 and 124 are turned off.

[0111] Thus, according to the third embodiment, a non-reset operation is performed in the initialization period (A2) of the horizontal scanning period (H_even) of the even-numbered i-th row in an odd frame (V_odd), and in the initialization period (A2) of the odd-numbered (i-1)-th horizontal scanning period (H_odd) in an even frame (V_even). In particular, although not shown, in the non-reset operation, the anode of the OLED 130 in the pixel circuit 110 in the i-th row and j-th column is disconnected from the data line 14 by turning off both the transistors 123 and 124 .

[0112] Therefore, according to the third embodiment, similarly to the first and second embodiments, the reset operation and the non-reset operation are alternately performed every horizontal scanning period in the odd-numbered rows and the even-numbered rows, so that the power consumed by the capacitive element 70 and the parasitic capacitance 72 can be reduced compared to the first comparative example. Furthermore, according to the third embodiment, the resistance value between the data line 14 and the anode of the OLED 130 in the non-reset operation is higher than that of the first or second embodiment in which only one of the transistors 123 and 124 is turned off. Therefore, according to the third embodiment, when an all-black display continues for several frames, the black floating that occurs except for the frame immediately after switching becomes more noticeable than that of the first or second embodiment.

[0113] In the above-described first to third embodiments (hereinafter referred to as "embodiments, etc."), various modifications or applications are possible as follows.

[0114] In the embodiment and the like, the transistor 86 is provided for the purpose of explanation in comparison with the second comparative example, but as described above, it is not necessary in the embodiment and the like, and may be omitted.

[0115] In the embodiment and the like, the reset operation and the non-reset operation are alternately performed for every odd-numbered row and every even-numbered row in every horizontal scanning period, but the present invention is not limited to this configuration. For example, the reset operation and the non-reset operation may be alternately performed for every two or more consecutive rows.

[0116] In the embodiment and the like, the OLED 130 has been described as an example of the light-emitting element, but other light-emitting elements may be used. For example, the light-emitting element may be an LED, or a liquid crystal element combined with an illumination mechanism. In other words, the light-emitting element may be an electro-optical element that changes its optical state according to the voltage of the data line 14. In the embodiment and the like, a 10-bit conversion example is shown as the DA conversion circuit 500, but the present invention is not limited to this.

[0117] The channel types of the transistors 64, 82, 84, (86), 121 to 124, etc. are not limited to those in the embodiment, etc. Furthermore, the channels of these transistors, etc. may be changed as appropriate, or may be replaced with transmission gates as appropriate.

[0118] Next, an electronic device to which the electro-optical device 10 according to the embodiment is applied will be described. The electro-optical device 10 is suitable for applications requiring small-sized pixels and high-definition display. Therefore, a head-mounted display will be taken as an example of the electronic device.

[0119] FIG. 19 is a diagram showing the appearance of a head mounted display, and FIG. 20 is a diagram showing the optical configuration thereof. First, as shown in Fig. 19, the head mounted display 300 has temples 310, a bridge 320, and lenses 301L and 301R in appearance similar to general eyeglasses. Also, as shown in Fig. 20, the head mounted display 300 has an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye provided near the bridge 320 and on the rear side of the lenses 301L and 301R (the lower side in the figure). The image display surface of the electro-optical device 10L is disposed to the left in FIG. 20. As a result, the image displayed by the electro-optical device 10L is output in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is disposed to the right, opposite the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is output in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction, while transmitting light incident from the 12 o'clock direction.

[0120] In this configuration, a person wearing the head mounted display 300 can observe images displayed by the electro-optical devices 10L and 10R in a see-through state in which the images are superimposed on the outside world. Furthermore, in this head mounted display 300, when the electro-optical device 10L displays an image for the left eye and the electro-optical device 10R displays an image for the right eye among the binocular images with parallax, the wearer can perceive the displayed image as if it had depth and a three-dimensional effect.

[0121] In addition, electronic devices including the electro-optical device 10 can be applied to electronic viewfinders in video cameras and interchangeable lens digital cameras, portable information terminals, display units of wristwatches, light bulbs of projection projectors, and the like, in addition to the head mounted display 300.

[0122] From the above-mentioned exemplary embodiments, the following aspects can be understood, for example.

[0123] An electro-optical device according to one aspect (aspect 1) includes a first pixel circuit provided corresponding to a data line and a first scanning line, a second pixel circuit provided corresponding to the data line and a second scanning line, and a control circuit that controls the first pixel circuit and the second pixel circuit, wherein the first pixel circuit includes a first light-emitting element that emits light with a luminance corresponding to a current flowing between two electrodes, and a first transistor that passes a current to the first light-emitting element corresponding to a voltage between a potential of a gate node and a potential of a source node, and the second pixel circuit includes a second light-emitting element that emits light with a luminance corresponding to the current flowing between the two electrodes, a second transistor that passes a current to the second light-emitting element corresponding to a voltage between the potential of the gate node and a potential of a source node, and a third transistor that electrically connects the data line and one of two electrodes in the second light-emitting element, and the control circuit controls a first pixel circuit to be connected to the first pixel circuit and the second pixel circuit when the first scanning line is selected in a first frame. During a first write period of one horizontal scanning period, a potential corresponding to the gradation level is supplied to the gate node of the first transistor via the data line, and during a first initialization period before the first write period, a first operation is performed. During a second horizontal scanning period in which the second scanning line is selected, a potential corresponding to the gradation level is supplied to the gate node of the second transistor via the data line during a second write period, and a second operation is performed during a second initialization period before the second write period, the first operation being an operation of supplying a first potential different from the potential corresponding to the gradation level to one of the two electrodes via the data line, the second operation being an operation of turning off the third transistor and setting the potential of the data line to a potential between the first potential and the second potential, and the second potential being a potential that, when supplied to the gate node, turns off the first transistor and the second transistor.

[0124] According to the first aspect, when the first operation is performed in the first pixel circuit, the second operation is performed in the second pixel circuit. In the first operation, the amount of discharge in the parasitic capacitance of the data line is increased, whereas in the second operation, the amount of discharge in the parasitic capacitance of the data line is reduced.

[0125] Note that the odd-numbered frame (V_odd) is an example of a first frame, the (i-1)th scanning line 12 is an example of a first scanning line, and the i-th scanning line 12 is an example of a second scanning line. The pixel circuit 110 in the (i-1)th row and jth column is an example of a first pixel circuit, and the pixel circuit 110 in the i-th row and jth column is an example of a second pixel circuit. In the pixel circuit 110 in the (i-1)th row and the jth column, the OLED 130 is an example of a first light-emitting element, and the transistor 121 is an example of a first transistor. In the pixel circuit 110 in the i-th row and j-th column, the OLED 130 is an example of a second light-emitting element, the transistor 121 is an example of a second transistor, and the transistor 123 or 124 is an example of a third transistor. Moreover, the horizontal scanning period (H_odd) is an example of a first horizontal scanning period, and in the horizontal scanning period (H_odd), the writing period (C) is an example of a first writing period, and the initialization period (A2) is an example of a first initialization period. The horizontal scanning period (H_even) is an example of a second horizontal scanning period, and in the horizontal scanning period (H_even), the writing period (C) is an example of a second writing period, and the initialization period (A2) is an example of a second initialization period. The potential Vorst is an example of a first potential, and the potential Vel is an example of a second potential. The reset operation is an example of a first operation, and the non-reset operation is an example of a second operation.

[0126] In an electro-optical device according to a specific embodiment 2 of embodiment 1, the third transistor is a threshold compensation transistor or a light emission control transistor provided in a path from the data line to one of the two electrodes of the second light emitting element, the threshold compensation transistor diode-connects the second transistor, and the light emission control transistor electrically connects the second transistor to the one electrode. According to the second aspect, a threshold compensation transistor that compensates for the threshold of the second transistor, or a light emission control transistor that controls whether the second light emitting element emits light, can also be used as the third transistor. In the pixel circuit 110 in the i-th row and j-th column, the transistor 123 is an example of a threshold compensation transistor, and the transistor 124 is an example of a light emission control transistor.

[0127] In an electro-optical device according to a specific embodiment 3 of embodiment 1, the third transistor is a series connection of a threshold compensation transistor and an emission control transistor provided in a path extending from the data line to one of the two electrodes of the second light-emitting element, the threshold compensation transistor diode-connects the second transistor, and the emission control transistor electrically connects the second transistor to the one electrode. According to the third aspect, a series connection of a threshold compensation transistor that compensates for the threshold of the second transistor and a light emission control transistor that controls whether the second light emitting element emits light or not can also be used as the third transistor.

[0128] In the electro-optical device according to a fourth specific example of the third example, the off state of the third transistor is the off state of either the light emission control transistor or the threshold compensation transistor. According to the fourth aspect, the path from the data line to one electrode of the second light-emitting element is cut off by the off state of either the threshold compensation transistor or the light-emission control transistor.

[0129] In the electro-optical device according to a fifth specific example of the third example, the off state of the third transistor corresponds to the off state of both the light emission control transistor and the threshold compensation transistor. According to the fifth aspect, the path from the data line to one electrode of the second light-emitting element is blocked by turning off both the threshold compensation transistor and the light-emission control transistor, and therefore the resistance between the data line and one electrode during the second operation is higher than when only one of the two transistors is turned off.

[0130] In an electro-optical device according to a specific aspect 6 of aspect 1, the first pixel circuit includes a fourth transistor electrically connecting the data line to one of the two electrodes of the first light-emitting element, and the control circuit performs the second operation in the first initialization period and the first operation in the second initialization period in a second frame following the first frame. According to aspect 6, the first operation is performed in the second pixel circuit and the second operation is performed in the first pixel circuit in the second frame, and they are replaced from the first frame, making it possible to make a decrease in display quality less noticeable. The even frame (V_even) is an example of the second frame.

[0131] An electronic device according to a seventh aspect includes the electro-optical device according to any one of the first to sixth aspects. [Explanation of symbols]

[0132] 10...electro-optical device, 12...scanning line, 14...data line, 14c...data signal output line, 30...control circuit, 50...data signal output circuit, 60...auxiliary circuit, 62...transistor, 70...capacitive element, 72...parasitic capacitance, 80...initialization circuit, 82, 84, 86...transistor, 110...pixel circuit, 120...scanning line driving circuit, 121-124...transistor, 130...OLED.

Claims

1. a first pixel circuit provided corresponding to the data line and the first scanning line; a second pixel circuit provided corresponding to the data line and a second scanning line; a control circuit for controlling the first pixel circuit and the second pixel circuit; Including, The first pixel circuit includes: a first light emitting element that emits light with a luminance corresponding to a current flowing between two electrodes; a first transistor that causes a current corresponding to a voltage between a potential of a gate node and a potential of a source node to flow through the first light emitting element; Including, The second pixel circuit includes: a second light emitting element that emits light with a luminance corresponding to a current flowing between the two electrodes; a second transistor for causing a current corresponding to a voltage between a potential of a gate node and a potential of a source node to flow through the second light emitting element; a third transistor electrically connecting the data line and one of the two electrodes of the second light emitting element; Including, The control circuit includes: During a first horizontal scanning period in which the first scanning line is selected in a first frame, In the first write period, supplying a potential corresponding to a gray level to a gate node of the first transistor via the data line; In a first initialization period before the first writing period, Performing a first action; During the second horizontal scanning period in which the second scanning line is selected, In the second write period, supplying a potential corresponding to a gray level to a gate node of the second transistor via the data line; In a second initialization period before the second writing period, Perform a second operation; The first operation includes: an operation of supplying a first potential different from a potential corresponding to the gradation level to one of the two electrodes via the data line; The second operation includes: The third transistor is turned off, an operation of setting the potential of the data line to a potential between the first potential and the second potential, The second potential is a potential that turns off the first transistor and the second transistor when supplied to the gate node. Electro-optical device.

2. The third transistor is a threshold compensation transistor or a light emission control transistor provided on a path from the data line to one of the two electrodes of the second light emitting element, the threshold compensation transistor causes the second transistor to be diode-connected; The light emission control transistor electrically connects the second transistor to the one electrode.

2. The electro-optical device according to claim 1.

3. The third transistor is a series connection of a threshold compensation transistor and a light emission control transistor provided on a path from the data line to one of the two electrodes of the second light emitting element; the threshold compensation transistor causes the second transistor to be diode-connected; The light emission control transistor electrically connects the second transistor to the one electrode.

2. The electro-optical device according to claim 1.

4. The off state of the third transistor is Either the light emission control transistor or the threshold compensation transistor is in an off state.

4. The electro-optical device according to claim 3.

5. The off state of the third transistor is Both the light emission control transistor and the threshold compensation transistor are in an off state.

4. The electro-optical device according to claim 3.

6. The first pixel circuit includes: a fourth transistor electrically connecting the data line and one of the two electrodes of the first light emitting element; The control circuit includes: In a second frame following the first frame, The second operation is performed during the first initialization period; The first operation is performed during the second initialization period.

2. The electro-optical device according to claim 1.

7. 7. An electronic apparatus comprising the electro-optical device according to claim 1.

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