Reference signal generation circuit and imaging apparatus

Abstract

To suppress increase of noise with linearity correction while making possible the linearity correction of AD conversion of a pixel signal.SOLUTION: A reference signal generation circuit comprises: a binary counter circuit which performs a count-up operation in response to a clock signal; and a linearity correction signal generation circuit which corrects output of the binary counter circuit on the basis of a correction signal for controlling an addition amount of the count-up operation. The correction signal may also include: an addition amount adding signal which adds the addition amount of the count-up operation; and an addition suppressing signal which suppresses addition of the count-up operation. The binary counter circuit may also include a selector which changes the addition amount of the count-up operation.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present technology relates to a reference signal generation circuit and an imaging device. More specifically, the present technology relates to a reference signal generation circuit and an imaging device capable of correcting linearity of AD (Analog to Digital) conversion. [Background technology]

[0002] In imaging devices, linearity correction of AD conversion of pixel signals is sometimes performed. For example, a photoelectric conversion device has been proposed that corrects the linearity of a digital value of an AD-converted pixel signal based on a digital value obtained by AD-converting a reference voltage (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-250304 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, the above-mentioned conventional technology may cause an increase in noise due to linearity correction of AD conversion of pixel signals.

[0005] This technology was developed in light of these circumstances, and its purpose is to enable linearity correction of AD conversion of pixel signals while suppressing the increase in noise that accompanies that linearity correction. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a reference signal generation circuit including a binary counter circuit that performs a count-up operation in response to a clock signal, and a linearity correction signal generation circuit that corrects the output of the binary counter circuit based on a correction signal that controls an addition amount of the count-up operation, thereby providing an effect that the slope is changed for each section divided in the digital domain.

[0007] In addition, in the first aspect, the correction signal may include an addition amount addition signal that adds an addition amount to the count-up operation, and an addition suppression signal that suppresses the addition of the count-up operation, thereby providing an effect that the increase or decrease in slope is changed for each section divided in the digital domain.

[0008] In addition, in the first aspect, the linearity correction signal generating circuit may be capable of changing a duty of an addition period during which an addition amount of the count-up operation is added and a suppression period during which the addition of the count-up operation is suppressed, thereby providing an effect that a slope is changed based on the duty of the addition period and the suppression period.

[0009] In addition, in the first aspect, the linearity correction signal generating circuit may superimpose a linearity correction signal on the output of the binary counter circuit based on pulse width modulation and its frequency when the addition period is set to a high level and the suppression period is set to a low level. This provides an effect that the slope of the linearity correction is set regardless of the time constant of a filter that smoothes the linearity-corrected nonlinear signal. For example, when the filter time constant is small, the frequency of the pulse width modulation can be increased, and when the filter time constant is large, the frequency of the pulse width modulation can be decreased.

[0010] In addition, in the first aspect, the addition amount addition signal and the addition suppression signal may be set in units of a cycle of the clock signal, thereby providing an effect that a slope is changed in units of a cycle of the clock signal.

[0011] In the first aspect, the input / output device may further include a shift register that outputs a thermometer code as the most significant bit of the output of the binary counter circuit, thereby making it easier to ensure monotonic increase in the DA converter.

[0012] In the first aspect, the digital-to-analog converter may further be provided for performing digital-to-analog conversion based on an output of the binary counter circuit, thereby providing an effect that a slope of an analog signal is changed based on a digital value.

[0013] In the first aspect, the digital signal processing device may further include a first low-pass filter including an output resistor of the DA converter and a capacitor connected to the output of the DA converter, thereby smoothing the analog signal whose slope has been changed based on the digital value.

[0014] In the first aspect, the digital to analog converter may further include a second low-pass filter including a buffer circuit connected to a downstream of the DA converter and a capacitor connected to an output of the buffer circuit. This provides an effect of smoothing the analog signal whose slope has been changed based on the digital value. The buffer circuit may be a source follower.

[0015] In the first aspect, the digital signal processing device may further include a comparator connected to a stage subsequent to the first low-pass filter or the second low-pass filter, thereby providing an effect that the reference signal having the linearity correction signal superimposed thereon is input to the comparator.

[0016] In addition, in the first aspect, the linearity correction signal generation circuit may correct the output of the binary counter circuit for each correction interval into which at least a part of the full scale of the DA converter is divided, thereby providing an effect that correction of the slope of the linearity correction is subdivided.

[0017] In addition, in the first aspect, the binary counter circuit may include a selector that changes the amount of addition in the count-up operation, thereby providing an effect that the amount of addition in the count-up operation is changed based on a switching operation.

[0018] In the first aspect, the digital signal processing device may further include a first DA converter that performs DA conversion based on an output of the binary counter circuit, a second DA converter that performs DA conversion based on an output of the linearity correction signal generating circuit, and a combiner that combines the output of the first DA converter and the output of the second DA converter, thereby providing an effect that the linearity of a reference signal used in AD conversion is corrected based on the normal counting operation of the binary counter circuit.

[0019] In addition, in the first aspect, the linearity correction signal generating circuit may include a frequency dividing circuit that divides the clock signal to generate a frequency-divided clock, and the binary counter circuit may perform the count-up operation in response to the frequency-divided clock, thereby providing an effect that the count-up timing is changed.

[0020] A second aspect of the present invention is a reference signal generating circuit including a binary counter circuit that performs a countdown operation in response to a clock signal, and a linearity correction signal generating circuit that corrects the output of the binary counter circuit based on a correction signal that controls the subtraction amount of the countdown operation, thereby providing an effect that the slope is changed for each section divided in the digital domain.

[0021] Also, a third aspect is an imaging device including a pixel array unit in which pixels generating pixel signals based on photoelectric conversion are arranged in a matrix in row and column directions, a column AD conversion unit performing AD conversion for each column based on a comparison result between the pixel signals and a reference signal, and a reference signal generation circuit generating the reference signal, the reference signal generation circuit including a binary counter circuit performing a count-up operation in response to a clock signal, and a linearity correction signal generation circuit correcting an output of the binary counter circuit based on a correction signal that controls an addition amount of the count-up operation. This brings about an effect that the pixel signals are AD converted based on the reference signal whose slope is changed for each section divided in the digital domain. [Brief description of the drawings]

[0022] [Figure 1] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment. [Diagram 2] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment. [Diagram 3] 2 is a diagram illustrating an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. [Figure 4] 1 is a block diagram showing an example of the configuration of a reference signal generating circuit according to a first embodiment; [Diagram 5] FIG. 2 is a diagram illustrating a method for generating a nonlinear signal according to the first embodiment. [Figure 6] 1 is a diagram illustrating an example of the configuration of a DA converter according to a first embodiment; [Figure 7] FIG. 2 is a diagram illustrating a first configuration example of a binary counter circuit according to a first embodiment. [Figure 8] FIG. 4 is a diagram illustrating a first output example of the binary counter circuit according to the first embodiment. [Figure 9] FIG. 4 is a diagram illustrating a second configuration example of the binary counter circuit according to the first embodiment. [Figure 10] FIG. 11 is a diagram illustrating a second output example of the binary counter circuit according to the first embodiment. [Figure 11] 3 is a block diagram showing a first example configuration of a thermometer code generating unit that generates a thermometer code according to the first embodiment. FIG. [Figure 12] FIG. 4 is a block diagram showing a second exemplary configuration of the thermometer code generating unit that generates a thermometer code according to the first embodiment. [Figure 13] FIG. 4 is a diagram illustrating a first example of a nonlinear signal according to the first embodiment. [Figure 14] FIG. 11 is a diagram illustrating a second example of a nonlinear signal according to the first embodiment. [Figure 15] FIG. 11 is a diagram illustrating a third example of a nonlinear signal according to the first embodiment. [Figure 16] 5 is a diagram illustrating an example of an error between an ideal waveform and an actual waveform of a nonlinear signal in the first embodiment. FIG. [Figure 17] 4A to 4C are diagrams illustrating a first example of a waveform of a nonlinear signal and an error in the first embodiment. [Figure 18] 6A to 6C are diagrams illustrating a second example of a waveform of a nonlinear signal and an error in the first embodiment. [Figure 19] 13A and 13B are diagrams illustrating a third example of a waveform of a nonlinear signal and an error in the first embodiment. [Figure 20] 13A to 13C are diagrams illustrating a fourth example of a waveform of a nonlinear signal and an error in the first embodiment. [Figure 21] FIG. 11 is a diagram illustrating a fifth example of a waveform of a nonlinear signal and an error in the first embodiment. [Figure 22] FIG. 11 is a diagram illustrating a sixth example of a waveform of a nonlinear signal and an error in the first embodiment. [Figure 23] FIG. 11 is a diagram illustrating a seventh example of a waveform of a nonlinear signal and an error in the first embodiment. [Figure 24] FIG. 13 is a diagram illustrating an eighth example of a waveform of a nonlinear signal and an error in the first embodiment. [Diagram 25] 4 is a timing chart showing a first example of updating a count value according to a clock of the binary counter circuit according to the first embodiment. [Figure 26]10 is a timing chart showing a second example of updating a count value according to a clock of the binary counter circuit according to the first embodiment. [Figure 27] 4 is a timing chart showing an example of a waveform of a nonlinear signal corresponding to a clock of the binary counter circuit according to the first embodiment. [Figure 28] FIG. 13 is a diagram illustrating a configuration example of a binary counter circuit according to a second embodiment. [Figure 29] FIG. 13 is a block diagram showing a configuration example of a selector of a binary counter circuit according to a second embodiment. [Diagram 30] 13 is a diagram illustrating an example of an output from the binary counter circuit according to the second embodiment. FIG. [Diagram 31] FIG. 13 is a block diagram showing an example of the configuration of a reference signal generating circuit according to a third embodiment. [Diagram 32] FIG. 13 is a block diagram showing an example of the configuration of a reference signal generating circuit according to a fourth embodiment. [Diagram 33] FIG. 13 is a diagram illustrating a configuration example of a binary counter circuit according to a fourth embodiment. [Diagram 34] 13 is a diagram illustrating an example of an output of the binary counter circuit according to the fourth embodiment. FIG. [Diagram 35] FIG. 13 is a perspective view showing an example of a stack of layers in a solid-state imaging device according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (an example in which a linearity correction signal is superimposed on the output of a binary counter circuit based on a correction signal that controls the amount of addition in a count-up operation) 2. Second embodiment (example in which the amount of count-up operation can be controlled from outside) 3. Third embodiment (an example in which the DA conversion value of the output of a binary counter circuit on which a linearity correction signal is superimposed and the DA conversion value of a thermometer code are combined) 4. Fourth embodiment (an example in which a DA conversion value of an output of a binary counter circuit with uncorrected linearity is combined with a DA conversion value of a correction signal that controls the amount of addition in a count-up operation) 5. Fifth embodiment (example in which semiconductor chips forming a solid-state imaging device are stacked)

[0024] <1. First embodiment> FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to the first embodiment.

[0025] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to each other via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, or a vehicle or a drone.

[0026] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0027] The solid-state imaging device 102 converts an optical image formed on a light receiving surface into an electric signal for each pixel, digitizes the electric signal, and outputs it. At this time, the solid-state imaging device 102 can digitize the pixel signal based on the timing until the level of the pixel signal read from the pixel matches the level of a reference signal. Here, the solid-state imaging device 102 can use a nonlinear reference signal whose linearity has been corrected as the reference signal. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor. The solid-state imaging device 102 may be a ToF (Time of Flight) sensor, an event-based vision sensor, or the like.

[0028] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on a command from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, and the like of the solid-state imaging device 102.

[0029] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0030] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program for operating the imaging device 100 based on software. The storage unit 105 may include a read only memory (ROM), a random access memory (RAM), and a memory card.

[0031] The display unit 106 displays captured images and various information supporting the image capturing operation, etc. The display unit 106 may be a liquid crystal display or an organic EL (Electro Luminescence) display.

[0032] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit .

[0033] Depending on the configuration of the imaging device 100, some of the above-mentioned functions may not be included, and conversely, the imaging device 100 may further include functions that are not disclosed.

[0034] FIG. 2 is a block diagram illustrating an example of the configuration of the solid-state imaging device according to the first embodiment. As shown in FIG.

[0035] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0036] The pixel array unit 111 includes a plurality of pixels PIX. The pixels PIX are arranged in a matrix along a row direction (also called a horizontal direction) and a column direction (also called a vertical direction). Each pixel PIX may be sensitive to visible light, near infrared light (NIR: Near InfraRed), short wave infrared light (SWIR: Short Wavelength InfraRed), ultraviolet light, X-rays, or the like. When each pixel PIX is sensitive to visible light, the pixels PIX may form a Bayer array or a quad Bayer array.

[0037] Each pixel PIX can form a source follower with the column readout circuit 113 when reading out a signal. Each pixel PIX is connected to a horizontal drive line HSL for each row. Also, each pixel PIX is connected to a vertical signal line VSL for each column. The horizontal drive line HSL drives each pixel PIX for each row when reading out a signal from each pixel PIX. The vertical signal line VSL transmits the pixel signal read out from the pixel PIX to the column signal processing unit 114 for each column.

[0038] The vertical scanning circuit 112 scans the pixels PIX to be read out in the column direction. The vertical scanning circuit 112 may be configured to include a vertical register. Here, the vertical scanning circuit 112 can drive each pixel PIX row by row via the horizontal drive line HSL when reading out a signal from each pixel PIX.

[0039] The column readout circuit 113 can configure a source follower with each pixel PIX when reading out a signal from the pixel PIX. At this time, the column readout circuit 113 can change the potential of the vertical signal line VSL based on the charge held in the pixel PIX.

[0040] The column signal processing unit 114 processes signals transmitted in the column direction from each pixel PIX. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the column direction from each pixel PIX. In addition, the column signal processing unit 114 can perform AD (Analog to Digital) conversion processing based on the signals transmitted in the column direction from each pixel PIX, and output an imaging signal Gout.

[0041] The column signal processing unit 114 includes a column ADC unit 114A and a reference signal generating circuit 114B. The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on a comparison result between a pixel signal read from the pixel PIX and a reference signal REF. The reference signal generating circuit 114B supplies a nonlinear reference signal whose linearity has been corrected to the column ADC unit 114A as the reference signal REF. At this time, the reference signal generating circuit 114B can generate a nonlinear reference signal whose linearity has been corrected based on control of the addition amount of the count-up operation according to the clock signal.

[0042] The horizontal scanning circuit 115 scans the pixels PIX to be read out in the row direction. The horizontal scanning circuit 115 may be configured to include a horizontal register.

[0043] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114.

[0044] FIG. 3 is a block diagram showing an example of a circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment.

[0045] In the figure, the pixel PIX includes a photodiode 121, a transfer transistor 122, a reset transistor 123, an amplification transistor 124, a selection transistor 125, and a floating diffusion FD. The transfer transistor 122, the reset transistor 123, the amplification transistor 124, and the selection transistor 125 can be implemented by MOS (Metal Oxide Semiconductor) transistors.

[0046] The amplification transistor 124 and the selection transistor 125 are connected in series. The cathode of the photodiode 121 is connected to the floating diffusion FD via the transfer transistor 122. The floating diffusion FD is connected to the upper power supply VDD via the reset transistor 123. The upper power supply VDD is connected to the vertical signal line VSL via a series circuit of the amplification transistor 124 and the selection transistor 125. The gate of the amplification transistor 124 is connected to the floating diffusion FD.

[0047] A transfer signal TGL is applied to the gate of the transfer transistor 122. A reset signal RST is applied to the gate of the reset transistor 123. A selection signal SEL is applied to the gate of the selection transistor 125. The transfer signal TGL, the reset signal RST, and the selection signal SEL can be transmitted to each pixel PIX via the horizontal drive line HSL in FIG.

[0048] When the transfer transistor 122 is turned on, the charge accumulated in the photodiode 121 is transferred to the floating diffusion FD. When the selection transistor 125 is turned on, the source potential of the amplification transistor 124 changes according to the potential of the floating diffusion FD. The source potential of the amplification transistor 124 is applied to the vertical signal line VSL via the selection transistor 125 and transmitted via the vertical signal line VSL. When the reset transistor 123 is turned on, the charge accumulated in the floating diffusion FD is discharged.

[0049] FIG. 4 is a block diagram illustrating an example of a configuration of the reference signal generating circuit according to the first embodiment.

[0050] 2, the reference signal generating circuit 114B includes a register 201, a ramp signal control circuit 202, a synthesis unit 203, a DA converter 204, capacitors 205 and 208, a current source 206, and a PMOS transistor 207.

[0051] The register 201 stores the correction setting data DH and outputs it to the linearity correction signal generating circuit 213. The correction setting data DH sets data used to correct the linearity of the reference signal REF, and can make the reference signal REF nonlinear. The correction setting data DH can include, for example, common data used in common to each correction interval and individual data used individually to each correction interval. The correction interval can include a plurality of correction intervals into which the full scale of the DA converter 204 is divided. The correction interval may include a plurality of correction intervals into which a part of the full scale of the DA converter 204 is divided.

[0052] The common data can be used to set whether to enable or disable linearity correction, the amount of change in the count value in one correction interval according to the clock signal CLK, switching between PWM (Pulse Width Modulation) input and step input, the number of times the same duty of the PWM input is repeated, the division number of the clock signal CLK, etc. The individual data can be used to set whether to add, not correct, or thin out the count according to the clock signal CLK (addition enabled and thinning enabled). Here, by switching between the PWM input and step input, the shape of the distortion caused by the filter characteristics in the subsequent stage can be changed.

[0053] The amount of change in the count value can be set by the amount of increment in the count-up operation and by suppressing the increment in the count-up operation. The amount of increment in the count-up operation can be specified as a positive integer. When suppressing the increment in the count-up operation, the amount of increment in the count-up operation can be specified as 0.

[0054] Here, the correction setting data DH can set an addition period during which the addition amount of the count-up operation is added and a suppression period during which the addition of the count-up operation is suppressed. At this time, the correction setting data DH can change the duty of the addition period during which the addition amount of the count-up operation is added and the suppression period during which the addition of the count-up operation is suppressed.

[0055] With PWM input, it is possible to equivalently realize pulse width modulation when the addition period during which the count-up operation is added is set to high level, and the suppression period during which the count-up operation is suppressed is set to low level. Note that in addition to PWM input, PFM (Pulse Frequency Modulation) input or PDM (Pulse Density Modulation) input such as ΔΣ input may also be used.

[0056] The ramp signal control circuit 202 controls the slope of the ramp signal according to the clock signal CLK. At this time, the ramp signal control circuit 202 can control the slope of the ramp signal in units of the period of the clock signal CLK, an integer multiple of the period, or a combination thereof. The ramp signal control circuit 202 includes a thermometer code generating unit 211, a binary counter circuit 212, and a linearity correction signal generating circuit 213.

[0057] The thermometer code generating unit 211 outputs a thermometer code as the most significant bits of the output of the binary counter circuit 212. The thermometer code can easily ensure the monotonic increase of the DA converter 204 based on the output of the binary counter circuit 212. The thermometer code generating unit 211 can be configured using a shift register.

[0058] The binary counter circuit 212 performs a count-up operation or stops counting up in response to the clock signal CLK or the divided clock. At this time, the binary counter circuit 212 can nonlinearly increase the linearly increasing count value based on the correction signal DNL output from the linearity correction signal generation circuit 213. At this time, the binary counter circuit 212 can make the output of the binary counter circuit 212 nonlinear by switching between a normal count-up operation, adding an amount to be added to the count-up operation, and stopping the count-up in response to the clock signal CLK or the divided clock. At this time, the binary counter circuit 212 can include a selector used to make the output of the binary counter circuit 212 nonlinear. This selector can switch between a normal count-up operation, adding an amount to be added to the count-up operation, and stopping the count-up in response to the clock signal CLK or the divided clock.

[0059] The linearity correction signal generation circuit 213 corrects the output of the binary counter circuit 212 based on a correction signal DNL that controls the amount of addition in the count-up operation. The correction signal DNL can include an addition amount addition signal that adds an amount of addition in the count-up operation and a suppression signal that suppresses the addition in the count-up operation. The linearity correction signal generation circuit 213 can set the addition amount addition signal and the suppression signal in units of the period of the clock signal CLK.

[0060] Furthermore, the correction signal DNL may include a divided clock obtained by dividing the clock signal CLK. In this case, the linearity correction signal generating circuit 213 may include a frequency dividing circuit 214. The frequency dividing circuit 214 can divide the clock signal CLK to generate the divided clock and output it to the binary counter circuit 212.

[0061] Here, the ramp signal control circuit 202 superimposes a nonlinear signal based on PDM, thereby enabling output in steps finer than the 1 LSB unit of the DA converter 204. This makes it possible to reduce noise (output error in response to a step input) newly generated in association with linearity correction.

[0062] The combiner 203 combines the digital data with the output of the binary counter circuit 212 as the lower bits and the thermometer code as the upper bits.

[0063] DA converter 204 performs DA conversion on the digital data output from synthesis unit 203. DA converter 204 is connected to the rear stage of synthesis unit 203. Capacitor 205 is connected to the output of DA converter 204. In this case, the output resistance of DA converter 204 and capacitor 205 can configure a low-pass filter LP1 that smoothes the output of DA converter 204.

[0064] A current source 206 is connected to the source of the PMOS transistor 207, and a lower power supply VSS is connected to the drain of the PMOS transistor 207. The lower power supply VSS may be ground. The current source 206 is connected to an upper power supply VDD. The output of the DA converter 204 is connected to the gate of the PMOS transistor 207. At this time, the PMOS transistor 207 can configure a source follower. Also, a capacitor 208 is connected in parallel to the source of the PMOS transistor 207. At this time, the source follower of the PMOS transistor 207 and the capacitor 208 can configure a low-pass filter LP2 that smoothes the output of the DA converter 204. The source follower is an example of a buffer circuit described in the claims.

[0065] The comparator 221 compares the reference signal REF generated by the reference signal generating circuit 114B with the pixel signal transmitted via the vertical signal line VSL. A post-amplifier 222 is connected to the rear of the comparator 221.

[0066] The comparator 221 balances the comparator inputs DV1 and DV2 based on the auto-zero operation, and outputs a voltage according to the difference between the comparator inputs DV1 and DV2. The comparator 221 includes PMOS transistors 231 and 232, NMOS transistors 233 to 235, and switches 236 and 237.

[0067] The PMOS transistor 231 and the NMOS transistor 233 are connected in series to each other. The PMOS transistor 232 and the NMOS transistor 234 are connected in series to each other. The source of each of the PMOS transistors 231 and 232 is connected to the upper power supply VDD, and the gate of each of the PMOS transistors 231 and 232 is connected to the drain of the PMOS transistor 231. At this time, the PMOS transistors 231 and 232 can configure a current mirror.

[0068] A capacitor 225 is connected in parallel to the PMOS transistor 232. At this time, the comparator 221 and the capacitor 225 can configure a low-pass filter LP3 that smoothes the output of the reference signal generating circuit 114B.

[0069] A reference signal REF is input to the gate of the NMOS transistor 233 via a DC blocking capacitor 223. The gate of the NMOS transistor 234 is connected to the vertical signal line VSL via a DC blocking capacitor 224 for each column.

[0070] A switch 236 is connected between the gate and drain of the NMOS transistor 233, and a switch 237 is connected between the gate and drain of the NMOS transistor 234. The sources of the NMOS transistors 233 and 234 are connected to the lower power supply VSS via an NMOS transistor 235.

[0071] Each switch 236, 237 is opened and closed based on the auto-zero signal AZ. Here, during the auto-zero period, each switch 236, 237 is turned on based on the auto-zero signal AZ. At this time, a current flows through each PMOS transistor 231, 232 based on the current mirror operation of the PMOS transistors 231, 232. Then, charge is accumulated in each DC cut capacitor 223, 224 so that the non-inverting input and the inverting input of the comparator 221 are balanced.

[0072] A bias voltage BIAS is applied to the gate of the NMOS transistor 235. The NMOS transistor 235 can operate as a constant current source based on the bias voltage BIAS.

[0073] The post-amplifier 222 amplifies the output of the comparator 221. The post-amplifier 222 includes a PMOS transistor 241 and an NMOS transistor 242.

[0074] The PMOS transistor 241 and the NMOS transistor 242 are connected in series to each other. The source of the PMOS transistor 241 is connected to the upper power supply VDD, and the gate of the PMOS transistor 241 is connected to the drain of the PMOS transistor 232. The capacitor 226 is connected between the gate and drain of the NMOS transistor 242, and the source of the NMOS transistor 242 is connected to the lower power supply VSS.

[0075] FIG. 5 is a diagram illustrating a method for generating a nonlinear signal according to the first embodiment.

[0076] In the figure, in generating a nonlinear signal, the AD conversion period is divided into a plurality of correction intervals, and the nonlinear signal can be changed to an arbitrary shape. For example, the correction intervals can include 16 correction intervals K1 to K16 obtained by dividing at least a part of the full scale of the DA converter 204 into 16. Here, the correction intervals K1 to K16 can be assigned to the D phase, and the correction intervals K1 to K16 of the D phase can be terminated midway for the P phase. At this time, for example, the correction intervals K1 to K8 can be assigned to the P phase. The correction intervals can be started after the delay amount DL has elapsed from the reference timing TK. In each of the correction intervals K1 to K16, when moving to the next correction interval, the correction amount can be set to be either addition of the count, no correction, or thinning. For example, in each of the correction intervals K9 and K12, addition or thinning can be performed by N (N is a positive integer) LSB. At this time, the PWM duty may be changed in a series of 25% → 50% → 75% → 100% when adding, and in a series of 75% → 50% → 25% → 0% when thinning out. The PWM duty repetition number can be set. At this time, if the PWM duty cycle is short, the action of the low-pass filters LP1 and LP2 can be made more effective than if it is long. Also, by setting the step or the number of PWM repetitions, it is possible to set how many LSBs are corrected in one correction interval. The clock used to set the PWM may be divided.

[0077] FIG. 6 is a diagram illustrating an example of the configuration of the DA converter according to the first embodiment.

[0078] In the figure, the DA converter 204 includes an upper DA converter 204A, a lower DA converter 204B, and a load resistor 271. The upper DA converter 204A can accommodate the input of a thermometer code. For example, if the thermometer code is represented by TH[xx:0], the upper DA converter 204A can accommodate TH[xx:0]. The lower DA converter 204B can accommodate the output of the binary counter circuit 212. For example, if the output of the binary counter circuit 212 is represented by BIN[4:0], the lower DA converter 204B can accommodate BIN[4:0].

[0079] The upper DA converter 204A includes PMOS transistors 251 to 254. The source of the PMOS transistor 251 is connected to the upper power supply VDD. The drain of the PMOS transistor 252 is connected to the PMOS transistors 253 and 254 in parallel with each other.

[0080] The lower DA converter 204B includes PMOS transistors 261 to 264. The source of the PMOS transistor 261 is connected to the upper power supply VDD. The drain of the PMOS transistor 262 is connected to PMOS transistors 263 and 264 in parallel with each other.

[0081] The drains of the PMOS transistors 253 and 263 are connected to the lower power supply VSS. The drains of the PMOS transistors 254 and 264 are connected to the lower power supply VSS via the load resistors 271.

[0082] A bias voltage VB1 is applied to the gate of each of the PMOS transistors 251, 261. A bias voltage VB2 is applied to the gate of each of the PMOS transistors 252, 262. A switching signal XSW is applied to the gate of each of the PMOS transistors 253, 263. A switching signal SW is applied to the gate of each of the PMOS transistors 254, 264. The switching signal XSW is an inverted signal of the switching signal SW.

[0083] When a switching signal SW is input according to the i-th (i is a positive integer) bit of the thermometer code, each of the PMOS transistors 254, 264 turns on. Then, a voltage DAO according to the current flowing through the load resistor 271 is output via each of the PMOS transistors 254, 264.

[0084] 7 is a diagram showing a first configuration example of the binary counter circuit according to the first embodiment. Note that, although the diagram shows an example in which a 5-bit count-up operation is performed, the present invention is not necessarily limited to this.

[0085] In the figure, the first configuration example of the binary counter circuit 212 stops the count-up operation corresponding to the clock signal CLK based on the correction signal DNL output from the linearity correction signal generation circuit 213. At this time, a switching signal SC for switching between normal counting and counting stop can be used as the correction signal DNL. Note that the normal counting is a count-up operation in which the addition amount corresponding to the clock signal CLK is 1.

[0086] The first configuration example of the binary counter circuit 212 includes AND circuits 302 to 305, an inverter 310, EXOR circuits 311 to 314, selectors 320 to 324, and flip-flops 330 to 334.

[0087] Each of the flip-flops 330 to 334 operates in synchronization with the clock signal CLK, and outputs a count value Q0 to Q4, respectively.

[0088] Each of the selectors 320 to 324 switches between normal counting and counting stop based on a switching signal SC. The output of each of the selectors 320 to 324 is connected to the D terminal of each of the flip-flops 330 to 334. The input terminal 0 of each of the selectors 320 to 324 is connected to the Q terminal of each of the flip-flops 330 to 334. The input terminal 1 of the selector 320 is connected to the output of the inverter 310. The input terminal 1 of each of the selectors 321 to 324 is connected to the output of each of the EXOR circuits 311 to 314.

[0089] An input of the inverter 310 is connected to a Q terminal of the flip-flop 330. A first input terminal of each of the EXOR circuits 311 to 314 is connected to a Q terminal of each of the flip-flops 331 to 334. A second input terminal of the EXOR circuit 311 is connected to a Q terminal of the flip-flop 330. A second input terminal of each of the EXOR circuits 312 to 314 is connected to an output of each of the AND circuits 302 to 304.

[0090] The AND circuit 302 calculates the product of the count values ​​Q0 and Q1. The AND circuit 303 calculates the product of the count values ​​Q0 to Q2. The AND circuit 304 calculates the product of the count values ​​Q0 to Q3. The AND circuit 304 calculates the product of the count values ​​Q0 to Q3.

[0091] When the count is stopped, the input terminal 0 of each of the selectors 320 to 324 is selected based on the switching signal SC. At this time, the D terminal of each of the flip-flops 330 to 334 is connected to the Q terminal, and the count-up operation is stopped.

[0092] In normal counting, the input terminal 1 of each of the selectors 320 to 324 is selected based on the switching signal SC. At this time, the D terminal of the flip-flop 330 is connected to the output of the inverter 310, and the D terminals of each of the flip-flops 331 to 334 are connected to the outputs of each of the EXOR circuits 311 to 314, respectively, and normal counting is performed.

[0093] FIG. 8 is a diagram illustrating a first output example of the binary counter circuit according to the first embodiment.

[0094] In the figure, in normal counting, the switching signal SC is set to 1. At this time, a count-up operation is performed in response to the clock signal CLK, and D n-1 =Q n-1 It becomes +1.

[0095] When the count is stopped, the switching signal SC is set to 0. At this time, the count-up operation according to the clock signal CLK is stopped, and the D n-1 =Q n-1 When the count is stopped, the clock signal CLK may be stopped, or the input of the clock signal CLK may be blocked.

[0096] FIG. 9 is a diagram illustrating a second configuration example of the binary counter circuit according to the first embodiment.

[0097] In the figure, the second configuration example of the binary counter circuit 212 switches between a count-up operation with an addition amount of 1 (normal count), a count-up operation with an addition amount of 2 (2-up count), and a count stop according to the clock signal CLK, based on the correction signal DNL output from the linearity correction signal generation circuit 213. At this time, a switching signal SC that enables the count stop and a switching signal VC that enables the 2-up count operation can be used as the correction signal DNL.

[0098] In the second configuration example of the binary counter circuit 212 , AND circuits 306 to 308 , an inverter 315 , EXOR circuits 316 to 318 , and selectors 340 to 345 are added to the first configuration example of the binary counter circuit 212 .

[0099] Each of the selectors 340 to 345 switches between normal counting and 2-up counting based on the switching signal VC. An input terminal 1 of the selector 320 is connected to the output of the selector 340. An input terminal 0 of the selector 340 is connected to the output of the inverter 310. An input terminal 1 of the selector 340 is connected to the Q terminal of the flip-flop 330. An output of each of the selectors 340 to 344 is connected to an input terminal 1 of each of the selectors 320 to 324. An input terminal 0 of each of the selectors 341 to 344 is connected to an output of each of the EXOR circuits 311 to 314. An input terminal 1 of the selector 341 is connected to an output of the inverter 315. An input terminal 1 of each of the selectors 342 to 344 is connected to an output of each of the EXOR circuits 316 to 318. An input terminal 0 of the selector 345 is connected to an output of the AND circuit 305. An input terminal 1 of the selector 345 is connected to an output of the AND circuit 308. A carry CA is output from the selector 345.

[0100] An input of the inverter 315 is connected to a Q terminal of a flip-flop 331. A first input terminal of each of the EXOR circuits 316 to 318 is connected to a Q terminal of each of the flip-flops 332 to 334. A second input terminal of the EXOR circuit 316 is connected to a Q terminal of the flip-flop 331. A second input terminal of each of the EXOR circuits 317 and 318 is connected to an output of each of the AND circuits 306 and 307.

[0101] An AND circuit 306 calculates the product of the count values ​​Q1 and Q2. An AND circuit 307 calculates the product of the count values ​​Q1 to Q3. An AND circuit 308 calculates the product of the count values ​​Q1 to Q4.

[0102] When the count is stopped, the input terminal 0 of each of the selectors 320 to 324 is selected based on the switching signal SC. At this time, the D terminal of each of the flip-flops 330 to 334 is connected to the Q terminal, and the count-up operation is stopped.

[0103] In normal counting, the input terminal 0 of each of the selectors 340 to 345 is selected based on the switching signal VC. At this time, the D terminal of the flip-flop 330 is connected to the output of the inverter 310, and the D terminals of each of the flip-flops 331 to 334 are connected to the outputs of each of the EXOR circuits 311 to 314, respectively, and normal counting is performed.

[0104] In the 2-up count, the input terminal 1 of each of the selectors 340 to 345 is selected based on the switching signal VC. At this time, the D terminal of the flip-flop 330 is connected to the Q terminal of the flip-flop 330, the D terminal of the flip-flop 331 is connected to the output of the inverter 315, and the D terminals of each of the flip-flops 332 to 334 are connected to the outputs of each of the EXOR circuits 316 to 318, respectively, and the 2-up count is performed.

[0105] FIG. 10 is a diagram illustrating a second output example of the binary counter circuit according to the first embodiment.

[0106] In the figure, when the count is stopped, the switching signal VC is set to 0. At this time, the count-up operation according to the clock signal CLK is stopped, and D n-1 =Q n-1 It becomes.

[0107] In the normal count, the switching signal VC is set to 1 and the switching signal SC is set to 0. At this time, a count-up operation according to the clock signal CLK is performed, and D n-1 =Q n-1 The result is +1.

[0108] In the 2-up count, the switching signal VC is set to 1 and the switching signal SC is set to 1. At this time, the value of the 0th bit is fixed, and the value of the 1st bit is added, thereby performing a count-up operation according to the clock signal CLK. Therefore, in the 2-up count, D n-1 =Q n-1 It becomes +2.

[0109] FIG. 11 is a block diagram showing a first example configuration of a thermometer code generating unit that generates a thermometer code according to the first embodiment. As shown in FIG.

[0110] In the figure, the first configuration example of the thermometer code generation unit includes flip-flops F1 to Fn (n is an integer equal to or greater than 2). The flip-flops F1 to Fn are cascode-connected to form a shift register. Each of the flip-flops F1 to Fn generates thermometer codes TH1 to TH n and outputs it to the D terminal of the subsequent stage. However, an H level is input to the D terminal of the first stage flip-flop F1. Note that the inverted count value XQ4 is a signal obtained by inverting the count value Q4.

[0111] FIG. 12 is a block diagram showing a second configuration example of the thermometer code generating unit that generates the thermometer code according to the first embodiment.

[0112] In the figure, the second configuration example of the thermometer code generator includes flip-flops F1 to Fn and selectors S1 to Sn. The flip-flops F1 to Fn are cascode-connected via selectors S1 to Sn connected to the front stage of each of the flip-flops F1 to Fn. Each of the flip-flops F1 to Fn generates thermometer codes TH1 to TH n At this time, each thermometer code TH1 to TH n-1 is input to input terminal 1 of the subsequent selectors S2 to Sn. However, an H level is input to input terminal 1 of the first-stage selector S1. Each of the selectors S1 to Sn switches its output according to the carry CA. The input terminal 0 of each of the selectors S1 to Sn is connected to the Q terminal of each of the flip-flops F1 to Fn.

[0113] 13 is a diagram showing a first example of a nonlinear signal according to the first embodiment. In the figure, a shows an example of a step input, and b to f show examples of changing the duty in the PWM input. The duty can be given by A / (A+B), where A is the length of the addition period during which the addition amount of the count-up operation is added, and B is the length of the suppression period during which the addition of the count-up operation is suppressed.

[0114] At a in the figure, a step input STP is given to the DA converter 204. At this time, if the CR time constant of the low-pass filter LP1 is small, the output changes in the first half of the correction interval, causing an output error. For example, the rising slope of the output RPA of the low-pass filter LP1 in the first half becomes large, and the error between the output RPA of the low-pass filter LP1 and the linear reference signal RNE becomes large. At this time, the error between the output RPA of the low-pass filter LP1 and the linear reference signal RNE can be reduced by subdividing the output RPA of the low-pass filter LP1 based on the PWM input.

[0115] At b in the figure, a PWM input PW1 is given to the DA converter 204. The PWM input PW1 is given in a sequence in which the duty in one correction interval is 50%→100%. In this case, the output RA1 of the low-pass filter LP1 can be made to fall in the middle of a rise or rise in the middle of a fall, and the error between the output RA1 of the low-pass filter LP1 and the linear reference signal RNE can be reduced.

[0116] At c in the figure, it is assumed that a PWM input PW2 is provided to the DA converter 204. The PWM input PW2 is provided in a sequence in which the duty in one correction interval is 50%→50%→100%→100%. At this time, the output RA2 of the low-pass filter LP1 can repeatedly fall in the middle of a rise and rise in the middle of a fall, and the error between the output RA2 of the low-pass filter LP1 and the linear reference signal RNE can be further reduced.

[0117] At d in the figure, a PWM input PW3 is provided to the DA converter 204. The PWM input PW3 is provided in a sequence in which the duty in one correction interval is 25%→50%→75%→100%. At this time, the output RA3 of the low-pass filter LP1 can repeat a fall in the middle of a rise and a rise in the middle of a fall more frequently, and the error between the output RA3 of the low-pass filter LP1 and the linear reference signal RNE can be further reduced.

[0118] At e in the figure, the PWM input PW4 is given to the DA converter 204. The PWM input PW4 is given in a sequence of 25%→25%→50%→50%→75%→75%→100%→100% duty in one correction section. At this time, the output RA4 of the low-pass filter LP1 can repeat a fall in the middle of a rise and a rise in the middle of a fall more often, and the error between the output RA4 of the low-pass filter LP1 and the linear reference signal RNE can be further reduced. Also, as shown at b, c, d, and e in the figure, by increasing the frequency of the PWM signal, the effect of reducing the error becomes greater even if the cutoff frequency of the low-pass filter LP1 is constant.

[0119] The count-down operation at f in the figure is the same as the count-up operation at e in the figure. At this time, the polarities of the PWM input PW4', the output RA4' of the low-pass filter LP1, and the linear reference signal RNE' at e in the figure are inverted.

[0120] Fig. 14 is a diagram showing a second example of a nonlinear signal according to the first embodiment. Fig. 14 shows an example in which the same input as in the example of Fig. 13 is used, but the CR time constant of the low-pass filter LP1 is increased.

[0121] 14A, a step input STP is applied to the DA converter 204. In this case, if the CR time constant of the low-pass filter LP1 is increased, the rising slope of the output RPB of the low-pass filter LP1 can be made smaller, and the error between the output RPC of the low-pass filter LP1 and the linear reference signal RNE can be made smaller.

[0122] 14, it is assumed that PWM inputs PW1 to PW4, PW4' are respectively provided to the DA converter 204. In this case, if the CR time constant of the low-pass filter LP1 is increased, the range of up and down fluctuations of the outputs RB1 to RB4, RB4' of the low-pass filter LP1 becomes smaller, and the error with respect to the linear reference signal RNE can be further reduced.

[0123] Fig. 15 is a diagram showing a third example of a nonlinear signal according to the first embodiment. Fig. 15 shows an example in which the CR time constant of the low-pass filter LP1 is further increased in the step input of the example of Fig. 14.

[0124] In the figure, it is assumed that a step input STP is given to the DA converter 204. In this case, if the CR time constant of the low-pass filter LP1 is further increased, the rising slope of the output RPC of the low-pass filter LP1 can be made smaller, and the error between the output RPC of the low-pass filter LP1 and the linear reference signal RNE can be made smaller. For this reason, by selectively using the step input and the PWM input according to the CR time constant of the low-pass filter LP1 and further changing the PWM frequency, it is possible to reduce the error in the linearity correction.

[0125] FIG. 16 is a diagram illustrating an example of an error between an ideal waveform and an actual waveform of a nonlinear signal according to the first embodiment.

[0126] In the figure, the nonlinear ideal signal SNL0 that corrects the linearity of the reference signal REF has a gentle waveform. Here, for example, it is assumed that the output of the DA converter 204 is changed in units of 2 LSB. At this time, a periodic error ERR1 of about 1 LSB occurs in the nonlinear real signal SNL1.

[0127] On the other hand, in b in the figure, for example, it is assumed that the output of the DA converter 204 is changed by PWM input in units of 2 LSB. At this time, a periodic error ERR2 of about 0.2 to 0.4 LSB occurs in the nonlinear real signal SNL2. Therefore, by applying a PWM input, it is possible to reduce the error.

[0128] Fig. 17 is a diagram showing a first example of a waveform of a nonlinear signal and an error according to the first embodiment. In Fig. 17 to Fig. 20 below, a signal change at 4τ is assumed, where τ is the CR time constant of the low-pass filter.

[0129] At a in the figure, it is assumed that a step input IN11 is provided to the DA converter 204. At this time, the rising slope of the output LB11 of the low-pass filter LP2 is closer to the rising slope of the linear reference signal RNE than the rising slope of the output LA11 of the low-pass filter LP1. Therefore, as shown at b in the figure, the error EB11 between the output LB11 of the low-pass filter LP2 and the linear reference signal RNE is smaller than the error EA11 between the output LA11 of the low-pass filter LP1 and the linear reference signal RNE.

[0130] FIG. 18 is a diagram illustrating a second example of the waveform of a nonlinear signal and an error according to the first embodiment.

[0131] At a in the figure, it is assumed that a PWM input IN12 is provided to a DA converter 204. The duty of the PWM input IN12 in one correction interval can be changed. By decreasing the duty of the PWM input IN12, the slope of the output LB12 of the low-pass filter LP2 can be decreased. By increasing the duty of the PWM input IN12, the slope of the output LB12 of the low-pass filter LP2 can be increased. At this time, the duty of the PWM input IN12 can be changed so that the slope of the output LB12 of the low-pass filter LP2 approaches the slope of the linear reference signal RNE.

[0132] For example, in order to reduce the error EB11 between the output LB11 of the low-pass filter LP2 and the linear reference signal RNE in FIG. 17b, the duty of the PWM input IN12 in one correction interval can be gradually increased. At this time, the PWM input IN12 can be given in a series of 0.25→0.25→0.5→0.5→0.75→0.75→1→1 in one correction interval. Here, the output LA12 of the low-pass filter LP1 rises while fluctuating up and down, and the output LB12 of the low-pass filter LP2 is smoothed. At this time, as shown in FIG. 18b, the errors EA12 and EB12 between the outputs LA12 and LB12 of the low-pass filters LP1 and LP2 and the linear reference signal RNE can be reduced, respectively, as shown in FIG. 18b, compared to the case where the step input IN11 in FIG. 17a is applied.

[0133] FIG. 19 is a diagram illustrating a third example of a waveform of a nonlinear signal and an error according to the first embodiment.

[0134] In a in the figure, it is assumed that the PWM input IN13 is given to the DA converter 204. Here, in order to reduce the error EB12 between the output LB12 of the low-pass filter LP2 and the linear reference signal RNE in b in FIG. 18, the first duty of the PWM input IN13 in one correction interval is made larger than the PWM input IN12, and the subsequent duty can be reduced once and then gradually increased. For example, the PWM input IN13 can be given in a sequence in which the duty in one correction interval is 0.5→0.25→0.5→0.5→0.75→0.75→1→1. Here, the output LA13 of the low-pass filter LP1 rises while fluctuating up and down, and the output LB13 of the low-pass filter LP2 is smoothed by the output LA13 of the low-pass filter LP1. At this time, the initial outputs LA13 and LB13 of the low-pass filters LP1 and LP2 are burst. Based on this burst, the distortion at the start of the output change can be reduced. Therefore, as shown in b of Figure 19, the error between the output LA13 of the low-pass filter LP1 and the linear reference signal RNE is EA13, and the error EB13 between the output LB13 of the low-pass filter LP2 and the linear reference signal RNE can be reduced compared to when the PWM input IN12 of a in Figure 18 is applied.

[0135] FIG. 20 is a diagram illustrating a fourth example of the waveform of a nonlinear signal and an error according to the first embodiment.

[0136] In a in the figure, it is assumed that the PWM input IN14 is given to the DA converter 204. Here, in order to reduce the error EB12 between the output LB12 of the low-pass filter LP2 and the linear reference signal RNE in b in FIG. 18, the first duty of the PWM input IN13 in one correction interval can be made larger than the PWM input IN12, and the subsequent duty can be gradually increased. For example, the PWM input IN13 can be given in a sequence in which the duty in one correction interval is 0.5→0.5→0.5→0.5→0.75→0.75→1→1. Here, the output LA14 of the low-pass filter LP1 rises while fluctuating up and down, and the output LB14 of the low-pass filter LP2 is smoothed by the output LA14 of the low-pass filter LP1. At this time, the initial outputs LA14 and LB14 of the low-pass filters LP1 and LP2 are burst. Therefore, as shown in b of Figure 20, the error between the output LA14 of the low-pass filter LP1 and the linear reference signal RNE is EA14, and the error EB14 between the output LB14 of the low-pass filter LP2 and the linear reference signal RNE can be reduced compared to when the PWM input IN12 of a in Figure 18 is applied.

[0137] Fig. 21 is a diagram showing a fifth example of a waveform of a nonlinear signal and an error according to the first embodiment. Note that in the following Figs. 21 to 24, a signal change at 8τ is assumed.

[0138] In the figure, it is assumed that a step input IN21 is provided to the DA converter 204. At this time, as shown in b in the figure, the error EB21 between the output LB21 of the low-pass filter LP2 and the linear reference signal RNE is smaller than the error EA21 between the output LA121 of the low-pass filter LP1 and the linear reference signal RNE.

[0139] FIG. 22 is a diagram illustrating a sixth example of a waveform of a nonlinear signal and an error according to the first embodiment.

[0140] In the figure, the duty of the PWM input IN22 is set to be the same as the duty of the PWM input IN12. Here, the output LA22 of the low-pass filter LP1 rises while fluctuating up and down, and the output LB22 of the low-pass filter LP2 is smoothed from the output LA22 of the low-pass filter LP1. At this time, as shown in b of Figure 22, the errors EA22 and EB22 between the outputs LA22 and LB22 of the low-pass filters LP1 and LP2 and the linear reference signal RNE can be reduced, respectively, compared to the case where the step input IN21 of a in Figure 21 is applied.

[0141] FIG. 23 is a diagram illustrating a seventh example of the waveform of a nonlinear signal and an error according to the first embodiment.

[0142] In the figure, the duty of the PWM input IN23 is set to be the same as the duty of the PWM input IN13. At this time, the initial outputs LA23, LB23 of the low-pass filters LP1, LP2 are bursty compared to the outputs LA22, LB22 when the PWM input IN22 of Fig. 21a is applied. Therefore, as shown in Fig. 23b, the error between the output LA23 of the low-pass filter LP1 and the linear reference signal RNE is EA23, and the error EB23 between the output LB23 of the low-pass filter LP2 and the linear reference signal RNE can be reduced compared to the case when the PWM input IN22 of Fig. 21a is applied.

[0143] FIG. 24 is a diagram illustrating an eighth example of the waveform of a nonlinear signal and an error according to the first embodiment.

[0144] In the figure, the duty of the PWM input IN24 is set to be the same as the duty of the PWM input IN14. At this time, the initial outputs LA24, LB24 of the low-pass filters LP1, LP2 are bursty compared to the outputs LA22, LB22 when the PWM input IN22 of Fig. 23a is applied. Therefore, as shown in Fig. 24b, the error between the output LA24 of the low-pass filter LP1 and the linear reference signal RNE is EA24, and the error EB24 between the output LB24 of the low-pass filter LP2 and the linear reference signal RNE can be reduced compared to the case when the PWM input IN22 of Fig. 23a is applied.

[0145] 25 is a timing chart showing a first example of updating the count value according to the clock of the binary counter circuit according to the first embodiment. In this first example, a +1LSB correction is performed in one correction section in which the duty changes in four stages (0.25→0.5→0.75→1).

[0146] In the figure, in normal counting, the normal count-up amount CNV is set to +1, and the normal count value CNU is incremented by 1 in synchronization with the clock signal CLK.

[0147] In each correction interval, the change in duty DUY can be set based on the phase difference between the switching signal VC that enables 2-up counting and the switching signal SC that enables count-up stop. For example, by setting the phase difference between the switching signals VC and SC to 1, 2, 3, and 4 cycles of the clock signal CLK, respectively, the duty DUY can be set to 0.25, 0.5, 0.75, and 1.

[0148] The PWM count-up amount PWU is set to the normal count value CNU+1 based on the rising edge input of the clock signal CLK when 2 count-up is enabled. Also, the PWM count-up amount PWU is set to the normal count value CNU-1 based on the rising edge input of the clock signal CLK when count-up is stopped. Also, the PWM count-up amount PWU is set to +1 by the time difference from 2 count-up to count-up stop. Also, if there is no count-up stop from 2 count-up, the PWM count-up amount PWU continues to be the normal count value CNU+1.

[0149] At this time, an addition period of the addition amount APW for the normal count is set based on the duty DUY of each correction interval. Then, the input IDA of the DA converter 204 is determined based on the value obtained by adding the addition amount APW to the normal count value CNU. At this time, in the input IDA of the DA converter 204, the normal count-up amount CNV is changed to the PWM count-up amount CUV. Then, the value STC of the input IDA of the DA converter 204 (step STP-normal count value CNU) is incremented by 1 for each correction interval.

[0150] 26 is a timing chart showing a second example of updating the count value according to the clock of the binary counter circuit according to the first embodiment. In this second example, a -1LSB correction is performed in one correction section in which the duty changes in four stages (1→0.75→0.5→0.25).

[0151] In the figure, in normal counting, the normal count-up amount CNV is set to +1, and the normal count value CNU is incremented by 1 in synchronization with the clock signal CLK.

[0152] In each correction section, the change in duty can be set based on the phase difference between the switching signal VC that enables 2-up counting and the switching signal SC that enables count-up stop. For example, the duty DUY can be set to 0.75, 0.5, 0.25, or 0 by setting the phase difference between the switching signals VC and SC to -1, -2, -3, or -4 cycles of the clock signal CLK, respectively.

[0153] The PWM count-up amount PWU is set to the normal count value CNU+1 based on the rising edge input of the clock signal CLK when 2 count-up is enabled. Also, the PWM count-up amount PWU is set to the normal count value CNU-1 based on the rising edge input of the clock signal CLK when count-up is stopped. Also, the PWM count-up amount PWU is set to -1 by the time difference from when count-up stopped to when 2 count-up has not occurred. Also, if there is no 2 count-up since count-up stopped, the PWM count-up amount PWU continues to be the normal count value CNU-1.

[0154] At this time, a subtraction period of the subtraction amount BPW for the normal count is set based on the duty DUY of each correction interval. Then, the input IDA of the DA converter 204 is determined based on the value obtained by subtracting the subtraction amount BPW from the normal count value CNU. At this time, in the input IDA of the DA converter 204, the normal count-up amount CNV is changed to the PWM count-up amount CUV. Then, the value STC of the input IDA of the DA converter 204 (step STP-normal count value CNU) is decremented by 1 for each correction interval.

[0155] 27 is a timing chart showing an example of a waveform of a nonlinear signal corresponding to the clock of the binary counter circuit according to the first embodiment. In this figure, a case where +1LSB correction is performed in one correction interval in which the duty cycle changes in four stages (0.25→0.25→0.5→0.5→0.75→0.75→1→1) with a duty cycle repetition number PD=2 is shown. Also, in this figure, the correction repetition number PK in one correction interval is set to 1.

[0156] In the figure, the PWM signal is set based on the phase difference between the switching signal VC that enables 2-count up and the switching signal SC that enables count up stop. The PWM signal can be controlled based on the correction voltage VM. At this time, in each correction section, when 2-count up is enabled, the PWM count up amount PWU2 is set to the normal count value CNE+1. Also, if there is no count up stop from 2-count up, the PWM count up amount PWU1 continues to be the normal count value CNE+1. Based on the settings of the PWM count up amounts PWU1 and PWU2, a nonlinear reference signal CAU is generated in which the linearity of the linear reference signal CNU is corrected.

[0157] In this way, in the first embodiment described above, the linearity correction signal is superimposed on the output of the binary counter circuit 212 based on the correction signal that controls the amount of addition in the count-up operation. This makes it possible to change the slope of the count-up based on the amount of addition in the count-up operation and the duty of the addition period and suppression period of the amount of addition. Therefore, it is possible to adjust the slope of the count-up regardless of the frequency characteristics of the low-pass filters LP1 and LP2, and correct the linearity of the AD conversion of the pixel signal while suppressing an increase in noise in the correction section.

[0158] <2. Second embodiment> In the above-described first embodiment, a linearity correction signal is superimposed on the output of the binary counter circuit 212 based on a correction signal that controls the amount of addition in the count-up operation. In this second embodiment, the amount of addition in the count-up operation of the binary counter circuit can be controlled externally.

[0159] 28 and 29 are diagrams illustrating a configuration example of a binary counter circuit according to the second embodiment.

[0160] 28 and 29, the binary counter circuit includes an adder 360, selectors 371 and 372, and flip-flops 330 to 334.

[0161] Each of the flip-flops 330 to 334 operates in synchronization with the clock signal CLK, and outputs count values ​​Q0 to Q4, respectively.

[0162] The adder 360 adds the X input X<4:0> and the Y input Y<4:0>, and outputs the sum D<4:0> to each of the flip-flops 330 to 334. The adder 360 includes a half adder 350 and full adders 351 to 354.

[0163] The Y terminals of the half adder 350 and each of the full adders 351 to 354 are connected to the Q terminals of the flip-flops 330 to 334, respectively. Input values ​​Y0 to Y4 are input to the X terminals of the half adder 350 and each of the full adders 351 to 354. The C terminal of the half adder 350 is connected to the C' terminal of the full adder 351, the C terminal of the full adder 351 is connected to the C' terminal of the full adder 352, the C terminal of the full adder 352 is connected to the C' terminal of the full adder 353, and the C terminal of the full adder 353 is connected to the C' terminal of the full adder 354. The S terminals of the half adder 350 and each of the full adders 351 to 354 are connected to the D terminals of the flip-flops 330 to 334, respectively.

[0164] The selector 371 switches between normal counting and 2-up counting based on a switching signal VC. Data DATA2<4:0> is input to an input terminal 0 of the selector 371, and data DATA3<4:0> is input to an input terminal 1 of the selector 371.

[0165] The selector 372 switches between normal counting and count stop based on a switching signal SC. Data DATA1<4:0> is input to an input terminal 0 of the selector 372, and the output of the selector 371 is input to an input terminal 1 of the selector 372.

[0166] FIG. 30 is a diagram illustrating an example of an output from the binary counter circuit according to the second embodiment.

[0167] In the figure, when VC=SC=0, Y<4:0> becomes DATA1<4:0>, and D<4:0>=X<4:0>+DATA1<4:0>. Here, when DATA1<4:0>=0, a +0 count is performed in response to the clock signal CLK.

[0168] When VC=1 and SC=0, Y<4:0> is DATA1<4:0>, and D<4:0>=X<4:0>+DATA1<4:0>. Here, when DATA1<4:0>=0, a +0 count is performed in response to the clock signal CLK.

[0169] When VC=0 and SC=1, Y<4:0> is DATA2<4:0>, and D<4:0>=X<4:0>+DATA2<4:0>. Here, when DATA2<4:0>=1, a +1 count is performed in response to the clock signal CLK.

[0170] When VC=SC=1, Y<4:0> is DATA3<4:0>, and D<4:0>=X<4:0>+DATA3<4:0>. Here, when DATA3<4:0>=2, a +2 count is performed in response to the clock signal CLK.

[0171] In this way, in the second embodiment described above, the increment of the count-up operation of the binary counter circuit can be externally controlled, which allows the increment of the count-up operation of the binary counter circuit to be set arbitrarily, thereby improving the flexibility of the count operation of the binary counter circuit.

[0172] <3. Third embodiment> In the above-described first embodiment, the output of the binary counter circuit 212 is corrected based on a correction signal that controls the amount of addition in the count-up operation. In this third embodiment, the DA-converted value of the output of the binary counter circuit onto which the linearity correction signal is superimposed is combined with the DA-converted value of the thermometer code.

[0173] FIG. 31 is a block diagram illustrating a configuration example of a reference signal generating circuit according to the third embodiment. As shown in FIG.

[0174] In the figure, this reference signal generation circuit includes a DA converter 410 instead of the DA converter 204 of the above-described first embodiment. Other configurations of the reference signal generation circuit of the third embodiment are similar to those of the reference signal generation circuit of the above-described first embodiment.

[0175] The DA converter 410 combines the DA converted value of the output of the binary counter circuit 212 onto which the linearity correction signal is superimposed and the DA converted value of the thermometer code generating unit 211. The DA converter 410 includes DA converters 411 and 412 and a combining unit 413.

[0176] The DA converter 411 performs DA conversion on the thermometer code output from the thermometer code generating unit 211 .

[0177] The DA converter 412 performs DA conversion on the output of the binary counter circuit 212 on which the linearity correction signal is superimposed, based on the correction signal DNL.

[0178] The synthesis unit 413 synthesizes the analog data output from the DA converters 411 and 412. At this time, the monotonically increasing property based on the output of the binary counter circuit 212 can be compensated in the analog domain.

[0179] In this way, in the above-described third embodiment, the DA conversion value of the output of binary counter circuit 212 on which the linearity correction signal is superimposed is combined with the DA conversion value of thermometer code generation unit 211. This allows the DA conversion of the thermometer code and the DA conversion of the output of binary counter circuit 212 to be performed by separate DA converters 411, 412, and the resolution of the DA converters 411, 412 can be reduced compared to the DA converter 204.

[0180] <4. Fourth embodiment> In the first embodiment described above, DA conversion is performed based on the output of the binary counter circuit 212 on which a linearity correction signal is superimposed. In this fourth embodiment, linearity correction is performed on the DA converted value of the output of the binary counter circuit whose linearity has not been corrected.

[0181] FIG. 32 is a block diagram illustrating a configuration example of a reference signal generating circuit according to the fourth embodiment. As shown in FIG.

[0182] In the figure, this reference signal generation circuit includes a ramp signal control circuit 502 instead of the ramp signal control circuit 202 of the above-described third embodiment. Moreover, this reference signal generation circuit is obtained by adding a DA converter 510 and a synthesis unit 511 to the reference signal generation circuit of the above-described third embodiment. Other configurations of the reference signal generation circuit of the fourth embodiment are similar to those of the reference signal generation circuit of the above-described third embodiment.

[0183] The ramp signal control circuit 502 includes a binary counter circuit 512 instead of the binary counter circuit 212 of the above-described third embodiment. Other configurations of the ramp signal control circuit 502 of the fourth embodiment are similar to the configuration of the ramp signal control circuit 202 of the above-described third embodiment.

[0184] The binary counter circuit 512 performs a counting operation in accordance with the clock signal CLK. At this time, the binary counter circuit 512 can increment the count value by 1 in accordance with the clock signal CLK.

[0185] The DA converter 510 performs DA conversion on the correction signal DNL generated by the linearity correction signal generating circuit 213 .

[0186] The synthesis unit 511 synthesizes the analog data output from the DA converters 410 and 510. At this time, based on the output of the DA converter 510, the linearity of the output of the DA converter 410 can be corrected in the analog domain.

[0187] FIG. 33 is a diagram illustrating a configuration example of a binary counter circuit according to the fourth embodiment. As illustrated in FIG.

[0188] 7, the binary counter circuit 512 has the selectors 320 to 324 removed from the binary counter circuit 212 of FIG. 7. At this time, the output of the inverter 310 is connected to the D terminal of the flip-flop 330. The outputs of the EXOR circuits 311 to 314 are connected to the D terminals of the flip-flops 331 to 334, respectively. Other configurations of the binary counter circuit 512 of the fourth embodiment are similar to the configuration of the binary counter circuit 212 of FIG. 7.

[0189] FIG. 34 is a diagram illustrating an example of an output from the binary counter circuit according to the fourth embodiment.

[0190] In the figure, a binary counter circuit 512 performs a normal count. At this time, a count-up operation is performed in response to a clock signal CLK, and D n-1 =Q n-1 It becomes +1.

[0191] In this way, in the above-described fourth embodiment, linearity correction is performed on the DA converted value of the output of the binary counter circuit 512, whose linearity has not been corrected. This allows the binary counter circuit 512 to be configured only with the flip-flops 330 to 334, and makes it possible to correct the linearity of the AD conversion of the pixel signal while suppressing the complexity of the configuration of the binary counter circuit 512.

[0192] <5. Fifth embodiment> In the above-described first embodiment, the output of the binary counter circuit 212 is corrected based on a correction signal that controls the amount of addition in the count-up operation. In this fifth embodiment, semiconductor chips are stacked on one another to form a solid-state imaging device having a pixel array unit in which pixels are arranged in a matrix.

[0193] FIG. 35 is a perspective view illustrating an example of a stack of layers in a solid-state imaging device according to the fifth embodiment. As shown in FIG.

[0194] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0195] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0196] A peripheral circuit 924 is formed in the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a reference signal generating circuit 927, and an oscillation circuit 928 are formed in the peripheral circuit 924. The reference signal generating circuit 927 may have any of the configurations in the first to fourth embodiments described above. In this case, the reference signal generating circuit 927 can correct the linearity of the reference signal after the semiconductor chips 921 and 922 are stacked. The column readout circuit 925 and the column ADC 926 may be formed to correspond to positions on both sides of the pixel array unit 923 in the column direction.

[0197] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding may be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected to each other based on a Cu-Cu connection. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0198] In this manner, in the above-described fifth embodiment, the semiconductor chip 922 in which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 in which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip in which the solid-state imaging device is formed.

[0199] The above-mentioned embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specified in the claims correspond to each other. Similarly, the matters specified in the claims and the matters in the embodiment of the present technology with the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist of the technology. In addition, the effects described in this specification are merely examples and are not limited, and other effects may be present.

[0200] The present technology can also be configured as follows. (1) a binary counter circuit that performs a count-up operation in response to a clock signal; a linearity correction signal generating circuit that corrects an output of the binary counter circuit based on a correction signal that controls an addition amount of the count-up operation; A reference signal generating circuit comprising: (2) The correction signal is an addition amount addition signal for adding an addition amount of the count-up operation; an addition suppression signal that suppresses the addition of the count-up operation; The reference signal generating circuit according to (1) above, (3) The linearity correction signal generating circuit The duty of an addition period during which the amount of addition of the count-up operation is added and a suppression period during which the addition of the count-up operation is suppressed can be changed. The reference signal generating circuit according to (2) above. (4) The linearity correction signal generating circuit comprises: A linearity correction signal is superimposed on the output of the binary counter circuit based on pulse width modulation and its frequency when the addition period is set to a high level and the suppression period is set to a low level. The reference signal generating circuit according to (2) or (3). (5) The addition amount addition signal and the addition suppression signal can be set in units of the cycle of the clock signal. The reference signal generating circuit according to any one of (2) to (4). (6) a shift register that outputs a thermometer code as the most significant bit of the output of the binary counter circuit; The reference signal generating circuit according to any one of (1) to (5), further comprising: (7) A DA converter that performs DA (Digital-to-Analog) conversion based on the output of the binary counter circuit. The reference signal generating circuit according to any one of (1) to (6), further comprising: (8) a first low-pass filter including an output resistor of the DA converter and a capacitor connected to the output of the DA converter; The reference signal generating circuit according to (7) above, further comprising: (9) A second low-pass filter including a buffer circuit connected to a downstream stage of the DA converter and a capacitor connected to an output of the buffer circuit. The reference signal generating circuit according to (8) above, further comprising: (10) a comparator connected to a stage subsequent to the first low-pass filter or the second low-pass filter; The reference signal generating circuit according to (9) above, further comprising: (11) The linearity correction signal generating circuit corrects the output of the binary counter circuit for each correction interval into which at least a part of the full scale of the DA converter is divided. The reference signal generating circuit according to any one of (7) to (10). (12) The binary counter circuit includes a selector for changing the amount of addition of the count-up operation. The reference signal generating circuit according to any one of (1) to (11), comprising: (13) a first DA converter that performs DA conversion based on an output of the binary counter circuit; a second DA converter that performs DA conversion based on an output of the linearity correction signal generating circuit; a synthesis unit that synthesizes an output of the first DA converter and an output of the second DA converter; The reference signal generating circuit according to any one of (1) to (12), further comprising: (14) The linearity correction signal generating circuit includes a frequency dividing circuit that divides the clock signal to generate a frequency-divided clock, The binary counter circuit performs the count-up operation in response to the divided clock. The reference signal generating circuit according to any one of (1) to (13). (15) A binary counter circuit that performs a countdown operation in response to a clock signal; a linearity correction signal generating circuit that corrects an output of the binary counter circuit based on a correction signal that controls an amount of subtraction in the countdown operation; A reference signal generating circuit comprising: (16) A pixel array unit in which pixels for generating pixel signals based on photoelectric conversion are arranged in a matrix in row and column directions; a column AD conversion unit that performs AD conversion for each column based on a comparison result between the pixel signal and a reference signal; a reference signal generating circuit for generating the reference signal; The reference signal generating circuit includes: a binary counter circuit that performs a count-up operation in response to a clock signal; a linearity correction signal generating circuit that corrects an output of the binary counter circuit based on a correction signal that controls an addition amount of the count-up operation; An imaging device comprising: [Explanation of symbols]

[0201] 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing section 105 Storage section 106 Display section 107 Operation section 108 Bus 111 Pixel array section 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing section 114A Column ADC section 114B Reference signal generation circuit 115 Horizontal scanning circuit 116 Control circuit 121 Photodiode 122 Transfer transistor 123 Reset Transistor 124 Amplifying transistor 125 Select Transistor PIX HSL Horizontal drive line VSL vertical signal line 201 Register 202 Lamp signal control circuit 211 Thermometer Code Generator 212 Binary Counter Circuit 213 Linearity correction signal generation circuit 214 Frequency divider circuit 203 Synthesis Section 204 DA Converter 205, 208, 225, 226 Capacitors 206 Current source

Claims

1. a binary counter circuit that performs a count-up operation in response to a clock signal; a linearity correction signal generating circuit that corrects an output of the binary counter circuit based on a correction signal that controls an addition amount of the count-up operation; A reference signal generating circuit comprising:

2. The correction signal is an addition amount addition signal for adding an addition amount of the count-up operation; an addition suppression signal that suppresses the addition of the count-up operation; The reference signal generating circuit according to claim 1 .

3. The linearity correction signal generating circuit includes: The duty of an addition period during which the amount of addition of the count-up operation is added and a suppression period during which the addition of the count-up operation is suppressed can be changed. The reference signal generating circuit according to claim 2 .

4. The linearity correction signal generating circuit includes: A linearity correction signal is superimposed on the output of the binary counter circuit based on pulse width modulation and its frequency when the addition period is set to a high level and the suppression period is set to a low level. The reference signal generating circuit according to claim 2 .

5. The addition amount addition signal and the addition suppression signal can be set in units of the cycle of the clock signal. The reference signal generating circuit according to claim 1 .

6. A shift register that outputs a thermometer code as the most significant bit of the output of the binary counter circuit. The reference signal generating circuit according to claim 1 , further comprising:

7. A DA converter that performs DA (Digital-to-Analogue) conversion based on the output of the binary counter circuit. The reference signal generating circuit according to claim 1 , further comprising:

8. a first low-pass filter configured with an output resistor of the DA converter and a capacitor connected to the output of the DA converter; The reference signal generating circuit according to claim 7 , further comprising:

9. a second low-pass filter including a buffer circuit connected to a stage subsequent to the DA converter and a capacitor connected to an output of the buffer circuit; The reference signal generating circuit according to claim 8 , further comprising:

10. a comparator connected to the rear stage of the first low-pass filter or the second low-pass filter; The reference signal generating circuit according to claim 9 , further comprising:

11. The linearity correction signal generating circuit corrects the output of the binary counter circuit for each correction interval into which at least a part of the full scale of the DA converter is divided. The reference signal generating circuit according to claim 7 .

12. The binary counter circuit includes a selector for changing the amount of addition of the count-up operation. The reference signal generating circuit according to claim 1 .

13. a first DA converter that performs DA conversion based on an output of the binary counter circuit; a second DA converter that performs DA conversion based on an output of the linearity correction signal generating circuit; a synthesis unit that synthesizes an output of the first DA converter and an output of the second DA converter; The reference signal generating circuit according to claim 1 , further comprising:

14. the linearity correction signal generating circuit includes a frequency dividing circuit that divides the clock signal to generate a frequency-divided clock; The binary counter circuit performs the count-up operation in response to the divided clock. The reference signal generating circuit according to claim 1 .

15. a binary counter circuit that performs a countdown operation in response to a clock signal; a linearity correction signal generating circuit that corrects an output of the binary counter circuit based on a correction signal that controls an amount of subtraction in the countdown operation; A reference signal generating circuit comprising:

16. a pixel array section in which pixels for generating pixel signals based on photoelectric conversion are arranged in a matrix in row and column directions; a column AD conversion unit that performs AD conversion for each column based on a comparison result between the pixel signal and a reference signal; a reference signal generating circuit for generating the reference signal; The reference signal generating circuit includes: a binary counter circuit that performs a count-up operation in response to a clock signal; a linearity correction signal generating circuit that corrects an output of the binary counter circuit based on a correction signal that controls an addition amount of the count-up operation; An imaging device comprising:

Images