Semiconductor device

Abstract

To provide a semiconductor device that comprises a diode which can reduce leakage current.SOLUTION: A diode 10 that is included in a semiconductor device 1 comprises: a semiconductor substrate 12; an n-type diffusion region 15 that is selectively formed in a surface layer part of a p-type epitaxial layer 13A; an n-type buried layer 14 that is sandwiched between the semiconductor substrate 12 and the n-type diffusion region 15, and has higher impurity concentration than the n-type diffusion region 15; a p-type anode contact region 20 that is formed in a surface layer part of a first principal surface 3; an n-type first cathode contact region 21 that is formed in the surface layer part of the first principal surface 3 being the surface layer part of the n-type diffusion region 15; and a p-type well region 16 that extends in a depth direction from the first principal surface 3 to arrive at the n-type buried layer 14 outside the first cathode contact region 21 and decouples the n-type diffusion region 15 in a direction along the first principal surface 3.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a diode including a p-type semiconductor substrate, an n-type epitaxial layer formed on a surface of the p-type semiconductor substrate, and an n-type buried layer formed at the boundary between the p-type semiconductor substrate and the n-type epitaxial layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-115365 A

[0004] [overview] An embodiment of the present disclosure provides a semiconductor device including a diode capable of reducing leakage current.

[0005] One embodiment of the present disclosure provides a semiconductor device including a semiconductor substrate of a first conductivity type, a second conductivity type diffusion region selectively formed in a surface layer portion of the semiconductor substrate, a second conductivity type buried layer sandwiched between the semiconductor substrate and the second conductivity type diffusion region and having a higher impurity concentration than the second conductivity type diffusion region, an anode contact region of the first conductivity type formed in a surface layer portion of a main surface, a first cathode contact region of the second conductivity type formed in a surface layer portion of the second conductivity type diffusion region, and a first conductivity type layer extending in a depth direction from the main surface of the semiconductor substrate outside the first cathode contact region to reach the second conductivity type buried layer, and dividing the second conductivity type diffusion region in a direction along the main surface. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment of the present disclosure. [Diagram 2]FIG. 2 is a diagram showing an example of a planar layout of impurity diffusion regions in the diode region. [Diagram 3] FIG. 3 is a diagram showing an example of a planar shape of the field insulating film in the diode region. [Figure 4] FIG. 4 is a diagram showing an example of a planar shape of the gate electrode in the diode region. [Diagram 5] FIG. 5 is a cross-sectional view taken along line VV shown in FIG. [Figure 6] FIG. 6 is an enlarged view of a portion surrounded by a dashed line VI in FIG. [Figure 7A] FIG. 7A is a diagram showing a part of the manufacturing process of the semiconductor device, and corresponds to FIG. [Figure 7B] FIG. 7B is a diagram showing the next step of FIG. 7A. [Figure 7C] FIG. 7C is a diagram showing the next step of FIG. 7B. [Figure 7D] FIG. 7D is a diagram showing the next step of FIG. 7C. [Figure 7E] FIG. 7E is a diagram showing the next step of FIG. 7D. [Figure 7F] FIG. 7F is a diagram showing the next step of FIG. 7E. [Figure 7G] FIG. 7G is a diagram showing the next step of FIG. 7F. [Figure 7H] FIG. 7H is a diagram showing the next step of FIG. 7G. [Figure 7I] FIG. 7I is a diagram showing the next step of FIG. 7H. [Figure 7J] FIG. 7J is a diagram showing the next step of FIG. 7I. [Figure 7K] FIG. 7K is a diagram showing the next step of FIG. 7J. [Figure 7L] FIG. 7L is a diagram showing the next step of FIG. 7K. [Figure 7M] FIG. 7M is a diagram showing the next step of FIG. 7L. [Figure 8] FIG. 8 is an electric circuit diagram showing the configuration of a signal output circuit to which the semiconductor device is applied. [Figure 9]FIG. 9 is a schematic plan view of a semiconductor device according to a second embodiment of the present disclosure, and corresponds to FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] [Detailed Description] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0008] FIG. 1 is a schematic plan view of a semiconductor device 1 according to a first embodiment of the present disclosure.

[0009] The semiconductor device 1 includes a semiconductor chip 2 formed in a rectangular parallelepiped shape. The semiconductor chip 2 forms the outer shape of the semiconductor device 1, and is, for example, a structure in which a single crystal semiconductor material is formed in a chip shape (rectangular parallelepiped shape). The semiconductor chip 2 is formed of a semiconductor material such as Si or SiC. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5 to 8 connecting the first main surface 3 and the second main surface 4. The first to fourth side surfaces 5 to 8 include a first side surface 5, a second side surface 6, a third side surface 7, and a fourth side surface 8. The third side surface 7 and the fourth side surface 8 extend in a first direction X and face a second direction Y perpendicular to the first direction X. The first side surface 5 and the second side surface 6 extend in the second direction Y and face the first direction X.

[0010] The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") seen from the third direction Z (the normal direction of the first main surface 3 and the second main surface 4). The first main surface 3 may be referred to as a device surface on which functional devices are formed. The second main surface 4 may be referred to as a non-device surface on which no functional devices are formed. A plurality of device regions 9 are formed on the first main surface 3. The number and arrangement of the plurality of device regions 9 are arbitrary. The plurality of device regions 9 may include functional devices formed by utilizing a surface layer portion of the first main surface 3. The functional devices may include, for example, at least one of a semiconductor switching device, a semiconductor rectifying device, and a passive device. The functional devices may include, for example, a circuit network in which at least two of a semiconductor switching device, a semiconductor rectifying device, and a passive device are combined.

[0011] The semiconductor switching device may include, for example, at least one of a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET). The semiconductor rectifying device may include, for example, at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include, for example, at least one of a resistor, a capacitor, and an inductor.

[0012] FIG. 2 is a diagram showing an example of a planar layout of an impurity diffusion region in the diode region 11. FIG. 3 is a diagram showing an example of a planar shape of a field insulating film 18 in the diode region 11. FIG. 4 is a diagram showing an example of a planar shape of a gate electrode 19 in the diode region 11. FIG. 5 is a cross-sectional view taken along line VV shown in FIG. 4. FIG. 6 is an enlarged view of a portion surrounded by a dashed dotted line VI in FIG. 5. With reference to FIGS. 1 to 6, the structure of the diode region 11 in which a diode 10 is formed as an example of a functional device among the multiple device regions 9 will be specifically described. The diode 10 has an LDMOS transistor structure. The diode 10 is a pn junction diode.

[0013] 5 and 6, the diode 10 includes a semiconductor substrate 12 and a semiconductor layer 13. The semiconductor substrate 12 is a p-type (first conductivity type) semiconductor substrate. Specifically, the semiconductor substrate 12 is a silicon substrate. The semiconductor substrate 12 forms a surface layer portion of the second main surface 4 of the semiconductor chip 2. The p-type impurity concentration of the semiconductor substrate 12 is 1.0×10 13 cm -3 Above 1.0×10 15 cm -3 The thickness of the semiconductor substrate 12 may be 100 μm or more and 500 μm or less. The semiconductor substrate 12 has a relatively low p-type impurity concentration. - This may also be referred to as the area of ​​the mold.

[0014] 2, 5 and 6, a semiconductor layer 13 is formed on a semiconductor substrate 12. The semiconductor layer 13 is formed on a surface layer portion of a first main surface 3 of the semiconductor chip 2. The semiconductor layer 13 is formed over the entire surface layer portion of the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5 to 8 (see FIG. 1). The thickness of the semiconductor layer 13 is smaller than the thickness of the semiconductor substrate 12, for example. The thickness of the semiconductor layer 13 may be not less than 5 μm and not more than 20 μm.

[0015] 2, 5 and 6, the semiconductor layer 13 includes a p-type epitaxial layer 13A. As shown in FIGS. 5 and 6, the p-type epitaxial layer 13A is selectively formed in a surface layer portion of the first main surface 3 of the semiconductor chip 2. An n-type diffusion region 15 is formed in the p-type epitaxial layer 13A. The n-type diffusion region 15 is formed in a rectangular shape extending long in the first direction X in a plan view. The p-type epitaxial layer 13A is formed in a rectangular ring shape surrounding the sides of the n-type diffusion region 15.

[0016] The p-type impurity concentration of the p-type epitaxial layer 13A is 1.0×10 13 cm -3 Above 1.0×10 15 cm -3 or less. The p-type impurity concentration of p-type epitaxial layer 13A may be the same as the p-type impurity concentration of semiconductor substrate 12. P-type epitaxial layer 13A is formed in a surface layer portion of first main surface 3 except for a region where n-type diffusion region 15 is to be formed, and is exposed from first main surface 3 and first to fourth side surfaces 5 to 8 (see FIG. 1).

[0017] 5 and 6, the semiconductor layer 13 is insulated and separated into a plurality of regions by an element isolation structure (not shown, for example, an element isolation well, DTI (Deep Trench Isolation), STI (Shallow Trench Isolation), etc.). The element isolation structure divides the semiconductor chip 2 into a plurality of device regions 9. FIGS. 2 to 6 show a device region 9 that forms a diode region 11 out of the plurality of separated device regions 9. Referring to FIG. 2, in the diode region 11, an n-type diffusion region 15 is formed in the center of the first main surface 3, and a p-type epitaxial layer 13A is formed in the peripheral portion of the first main surface 3.

[0018] 2, 5 and 6, n-type diffusion region 15 is selectively formed in a surface layer portion of first main surface 3 of semiconductor chip 2. N-type diffusion region 15 extends in a layered manner along first main surface 3. The depth of n-type diffusion region 15 is the same throughout the circumferential direction. The n-type impurity concentration of n-type diffusion region 15 is 1.0×10 12 cm -3 Above 1.0×10 13 cm -3 The thickness of the n-type diffusion region 15 may be 5 μm or more and 20 μm or less. In a plan view, the n-type diffusion region 15 overlaps with the n-type buried layer 14 described next. The bottom of the n-type diffusion region 15 contacts the n-type buried layer 14.

[0019] 2, 5 and 6, the diode 10 further includes an n-type buried layer (second conductivity type buried layer) 14, a p-type well region (first conductivity type well region) 16, a p-type layer (first conductivity type region) 17, a field insulating film 18, a gate electrode 19, an anode contact region 20, a first cathode contact region 21, a second cathode contact region 22, a third cathode contact region 23, an interlayer insulating film 24, an anode wiring 25, an anode contact 26, a cathode wiring 27, a first cathode contact 28, a second cathode contact 29, and a third cathode contact 30. As shown in FIG. 6, the p-type layer 17 includes an upper p-type layer 31 and a lower p-type layer 32.

[0020] 5 and 6, the n-type buried layer 14 is an n-type (second conductivity type) layer (B / L (Buried Layer)) buried between the semiconductor substrate 12 and the semiconductor layer 13. Specifically, the n-type buried layer 14 extends in a layered form along the first main surface 3 so as to straddle the boundary between the semiconductor substrate 12 and the n-type diffusion region 15. That is, the n-type buried layer 14 is formed sandwiched between the semiconductor substrate 12 and the n-type diffusion region 15. Although not shown, the n-type buried layer 14 is quadrangular in plan view. The n-type buried layer 14 is electrically connected to the semiconductor substrate 12 and the p-type epitaxial layer 13A. The thickness of the n-type buried layer 14 may be 0.1 μm or more and 5 μm or less. The n-type impurity concentration of the n-type buried layer 14 is 1.0×10 13 cm -3 Above 1.0×10 14 cm -3 It may be the following.

[0021] The n-type impurity concentration of the n-type buried layer 14 is higher than the n-type impurity concentration of the n-type diffusion region 15. Specifically, as described above, when the n-type impurity concentration of the n-type buried layer 14 is 1.0×10 13 cm -3 Above 1.0×10 14 cm -3 The n-type impurity concentration of the n-type diffusion region 15 is 1.0×10 12 cm -3 Above 1.0×10 13 cm -3 The n-type impurity concentration of the n-type buried layer 14 may be 10 times or more higher than the impurity concentration of the n-type diffusion region 15. The n-type impurity concentration of the n-type buried layer 14 may be one order of magnitude or more higher than the impurity concentration of the n-type diffusion region 15.

[0022] The n-type diffusion region 15 is divided into an inner diffusion region 15A having a rectangular shape in a plan view and an outer diffusion region 15B having a rectangular ring shape in a plan view by the p-type layer 17. The outer periphery of the inner diffusion region 15A and the inner periphery of the outer diffusion region 15B are separated from each other in the first direction X and the second direction Y. The inner diffusion region 15A includes a lower diffusion region 15C sandwiched between the n-type buried layer 14 and the p-type well region 16.

[0023] 2, 5 and 6, the p-type well region 16 is a p-type diffusion region and is formed in a surface layer portion of the n-type diffusion region 15. The p-type well region 16 is in contact with the inner diffusion region 15A (n-type diffusion region 15) in both the first direction X and the second direction Y. The p-type well region 16 is in contact with the lower diffusion region 15C (inner diffusion region 15A) in the third direction Z. The p-type well region 16 is a region in the diode region 11 to which a voltage is applied from the anode wiring 25.

[0024] 2 and 5, the p-type well region 16 is formed in an elliptical shape extending long in the first direction X in a plan view. The p-type well region 16 has a first periphery 61 and a second periphery 62 extending linearly with a gap therebetween along the first direction X. The p-type well region 16 has a third periphery 63 and a fourth periphery 64 connecting the first periphery 61 and the second periphery 62. The third periphery 63 and the fourth periphery 64 face each other in the first direction X. The third periphery 63 and the fourth periphery 64 are formed in an arc shape bulging outward in the first direction X.

[0025] 2 and 5, the p-type layer 17 is a p-type impurity region formed in a surface layer portion of the first main surface 3. The lower end of the p-type layer 17 reaches the n-type buried layer 14. The p-type layer 17 is annular in plan view, and divides the n-type diffusion region 15 in both the first direction X and the second direction Y. The depth of the p-type layer 17 is the same throughout the circumferential direction. With reference to FIG. 2, the p-type layer 17 may be formed in a quadrangular ring shape extending long in the first direction X in plan view.

[0026] The p-type layer 17 is adjacent to the inner diffusion region 15A so as to surround the outer periphery of the inner diffusion region 15A in a plan view. The p-type layer 17 is adjacent to the outer diffusion region 15B so as to be surrounded by the inner periphery of the outer diffusion region 15B in a plan view. The p-type layer 17 surrounds the outer periphery of the p-type well region 16 in a plan view. The p-type layer 17 is formed at a distance from the p-type well region 16 in both the first direction X and the second direction Y in a plan view. Although not shown, the p-type layer 17 may be formed in an elliptical ring shape extending long in the first direction X in a plan view.

[0027] 6, p-type layer 17 includes upper p-type layer 31 and lower p-type layer 32. Upper p-type layer 31 and lower p-type layer 32 are adjacent to each other vertically. Upper p-type layer 31 and lower p-type layer 32 form an annular p-type layer 17.

[0028] The upper p-type layer 31 is a p-type impurity region formed in the surface layer portion of the first main surface 3. The upper p-type layer 31 is formed of a p-type diffusion layer. The p-type impurity concentration of the upper p-type layer 31 is, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3 The p-type impurity concentration of the upper p-type layer 31 may be equal to or lower than the p-type impurity concentration of the p-type well region 16. The p-type impurity concentration of the upper p-type layer 31 may be higher than the p-type impurity concentration of the p-type well region 16. The p-type impurity concentration of the upper p-type layer 31 may be lower than the p-type impurity concentration of the p-type well region 16.

[0029] 2, the upper p-type layer 31 has, for example, a rectangular ring shape. The upper p-type layer 31 surrounds the sides of the p-type well region 16. The upper p-type layer 31 faces the p-type well region 16 in the first direction X and the second direction Y. A first depth D1 of a bottom portion of the upper p-type layer 31 is the same as a second depth D2 of a bottom portion of the p-type well region 16. The first depth D1 may be deeper than the second depth D2. The first depth D1 may be shallower than the second depth D2.

[0030] 5 and 6, the lower p-type layer 32 is formed on the second main surface 4 side of the upper p-type layer 31. The lower p-type layer 32 is in contact with the upper p-type layer 31. Although not shown, the lower p-type layer 32 has a quadrangular ring shape and overlaps the upper p-type layer 31 in a plan view. The lower p-type layer 32 does not face the p-type well region 16 in the lateral direction (first direction X and second direction Y).

[0031] The lower p-type layer 32 is formed of a p-type epitaxial layer. The p-type impurity concentration of the lower p-type layer 32 is 1.0×10 13 cm -3 Above 1.0×10 15 cm -3 or less. The p-type impurity concentration of the lower p-type layer 32 may be the same as the p-type impurity concentration of the p-type epitaxial layer 13A. The p-type impurity concentration of the lower p-type layer 32 may be the same as the p-type impurity concentration of the semiconductor substrate 12. The p-type impurity concentration of the lower p-type layer 32 is lower than the p-type impurity concentration of the upper p-type layer 31. The p-type impurity concentration of the lower p-type layer 32 is lower than the p-type impurity concentration of the p-type well region 16. Since the lower p-type layer 32 has a relatively low p-type impurity concentration, - This may also be referred to as the area of ​​the mold.

[0032] 6, the inner peripheral end of the upper p-type layer 31 is aligned with the inner peripheral end of the lower p-type layer 32 in the first direction X and the second direction Y. The outer peripheral end of the upper p-type layer 31 is aligned with the outer peripheral end of the lower p-type layer 32 in the first direction X and the second direction Y. Although not shown in the figure, the inner peripheral end of the upper p-type layer 31 may be separated outward or inward from the inner peripheral end of the lower p-type layer 32. Also, although not shown in the figure, the outer peripheral end of the upper p-type layer 31 may be separated outward or inward from the outer peripheral end of the lower p-type layer 32.

[0033] 2 and 3, the field insulating film 18 is formed on the first main surface 3 of the semiconductor chip 2. The field insulating film 18 covers the first main surface 3. For clarity, the outer edges of the anode contact region 20, the first cathode contact region 21, the second cathode contact region 22, and the third cathode contact region 23 are all shown by thick solid lines in FIG. 2. For clarity, the field insulating film 18 is shown by hatching in FIG. 3. Regions not hatched in FIG. 3 are regions not covered with the field insulating film 18. The field insulating film 18 may be, for example, a LOCOS oxide film formed by selectively oxidizing the surface (first main surface 3) of the n-type diffusion region 15.

[0034] 3, the field insulating film 18 has a first opening 41, a second opening 42, a third opening 43, and a fourth opening 44. The first opening 41 is formed in a rectangular ring shape extending long in the first direction X in a plan view. The first opening 41 exposes a part of the inner diffusion region 15A of the n-type diffusion region 15 (a first cathode contact region 21 described next). The second opening 42 is formed in a rectangular ring shape extending long in the first direction X in a plan view and surrounding the periphery of the first opening 41 in a plan view. The second opening 42 exposes a part of the upper p-type layer 31 (p-type layer 17) (a second cathode contact region 22 described next). The third opening 43 is formed in a rectangular ring shape extending long in the first direction X in a plan view and surrounding the periphery of the first opening 41 in a plan view. The third opening 43 exposes a portion of the outer diffusion region 15B of the n-type diffusion region 15 (the third cathode contact region 23 described next).

[0035] 3, the fourth opening 44 is formed in an elliptical ring shape extending long in the first direction X in a plan view. The fourth opening 44 exposes the inner diffusion region 15A (n-type diffusion region 15) and the p-type well region 16. The opening width (width in the second direction Y) of the fourth opening 44 is wider than the opening widths (widths in the first direction X and the second direction Y) of the first opening 41, the second opening 42, and the third opening 43. Although not shown, the fourth opening 44 may be formed in a quadrangle shape extending long in the first direction X in a plan view.

[0036] Although not shown in the figures, the first opening 41 may be formed as a pair to sandwich the fourth opening 44 in the second direction Y. Furthermore, although not shown in the figures, the second opening 42 may be formed as a pair to sandwich the first opening 41 and the fourth opening 44 in the second direction Y. Furthermore, although not shown in the figures, the third opening 43 may be formed as a pair to sandwich the first opening 41, the second opening 42, and the fourth opening 44 in the second direction Y.

[0037] 2, 5 and 6, the first cathode contact region 21 is formed in a surface layer portion of the inner diffusion region 15A. The first cathode contact region 21 may have a higher n-type impurity concentration than the inner diffusion region 15A. The n-type impurity concentration of the first cathode contact region 21 is, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3 It may be the following.

[0038] 3, the first cathode contact region 21 is exposed from the field insulating film 18 at the first opening 41. The first cathode contact region 21 is a quadrangular ring shape that matches the first opening 41. The first cathode contact region 21 has a first side portion 21a and a second side portion 21b that extend along the first direction X with a gap therebetween. The first cathode contact region 21 has a third side portion 21c and a fourth side portion 21d that connect the first side portion 21a and the second side portion 21b. The third side portion 21c and the fourth side portion 21d extend along the second direction Y with a gap therebetween. Referring to FIG. 6, the first width W1 of the first cathode contact region 21 is not less than 0.6 μm and not more than 0.8 μm. The first width W1 may be constant over the entire circumferential area of ​​the first cathode contact region 21.

[0039] 2, 5 and 6, the second cathode contact region 22 is formed in a surface layer portion of the upper p-type layer 31 (p-type layer 17). The second cathode contact region 22 may have a higher p-type impurity concentration than the upper p-type layer 31. The p-type impurity concentration of the second cathode contact region 22 is, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3 It may be the following.

[0040] 3, the second cathode contact region 22 is exposed from the field insulating film 18 at the second opening 42. The second cathode contact region 22 is a quadrangular ring shape that matches the second opening 42. The second cathode contact region 22 has a first side portion 22a and a second side portion 22b that extend along the first direction X with a gap therebetween. The second cathode contact region 22 has a third side portion 22c and a fourth side portion 22d that connect the first side portion 22a and the second side portion 22b. The third side portion 22c and the fourth side portion 22d extend along the second direction Y with a gap therebetween. With reference to FIG. 6, the second width W2 of the second cathode contact region 22 is not less than 0.6 μm and not more than 0.8 μm. The second width W2 may be constant over the entire circumferential area of ​​the second cathode contact region 22.

[0041] 2, 5 and 6, the third cathode contact region 23 is formed in a surface layer portion of the outer diffusion region 15B. The third cathode contact region 23 may have a higher n-type impurity concentration than the outer diffusion region 15B. The n-type impurity concentration of the third cathode contact region 23 is, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3 It may be the following.

[0042] 3, the third cathode contact region 23 is exposed from the field insulating film 18 at the third opening 43. The third cathode contact region 23 is a quadrangular ring shape that matches the third opening 43. The third cathode contact region 23 has a first side portion 23a and a second side portion 23b that extend along the first direction X with a gap therebetween. The third cathode contact region 23 has a third side portion 23c and a fourth side portion 23d that connect the first side portion 23a and the second side portion 23b. The third side portion 23c and the fourth side portion 23d extend along the second direction Y with a gap therebetween. With reference to FIG. 6, the third width W3 of the third cathode contact region 23 is not less than 0.6 μm and not more than 0.8 μm. The third width W3 may be constant over the entire circumferential area of ​​the third cathode contact region 23.

[0043] Referring to FIG. 4, a gate electrode 19 is formed on the first main surface 3 of the semiconductor chip 2. For clarity, the gate electrode 19 is shown by hatching in FIG. 4. The gate electrode 19 may include a conductive material such as polysilicon or aluminum. The gate electrode 19 is formed in a ring shape in a plan view. The gate electrode 19 may have a pair of first portions 51 facing each other in the second direction Y and a second portion 52 connecting the pair of first portions 51. In this embodiment, the first portions 51 are formed in linear shapes extending parallel to each other along the first direction X, and the second portions 52 are formed in arc shapes bulging outward in the first direction X. An opening 50 is formed in the center of the gate electrode 19 partitioned by the pair of first portions 51 and the pair of second portions 52. The opening 50 is formed in an elliptical shape extending along the first direction X in a plan view. The opening 50 exposes a part of the p-type well region 16. Specifically, opening 50 exposes anode contact region 20 .

[0044] 4, a channel is formed in a region of p-type well region 16 facing gate electrode 19. The formation of the channel in this region is controlled by gate electrode 19. The thickness of gate electrode 19 may be, for example, not less than 0.1 μm and not more than 0.4 μm.

[0045] 6, a gate insulating film 54 is formed between the gate electrode 19 and the first main surface 3. The gate insulating film 54 may be, for example, a silicon oxide (SiO2) film formed by thermally oxidizing the first main surface 3. The thickness of the gate insulating film 54 may be, for example, not less than 0.2 nm and not more than 100 nm.

[0046] 6, gate electrode 19 may integrally include an annular control portion 55 on the opening 50 side (inner side) and an annular field plate portion 56 outside control portion 55. Control portion 55 of gate electrode 19 covers p-type well region 16 (a region where a channel is formed) and p-type layer 17 via gate insulating film 54 in this order from the inner side to the outer side. Field plate portion 56 of gate electrode 19 is formed on field insulating film 18 on p-type layer 17.

[0047] 6, a sidewall structure 57 is formed on the side of the gate electrode 19. The sidewall structure 57 is formed on both the inner side (the side of the opening 50) and the outer side of the gate electrode 19.

[0048] 6, the anode contact region 20 is formed in a surface layer portion of the p-type well region 16. The anode contact region 20 has a strip shape extending along the first direction X. The anode contact region 20 is a p-type impurity region.

[0049] 2, the anode contact region 20 has a first side portion 20a and a second side portion 20b extending at an interval along the first direction X. The anode contact region 20 has a third side portion 20c and a fourth side portion 20d connecting the first side portion 20a and the second side portion 20b. The third side portion 20c and the fourth side portion 20d are formed in an arc shape that bulges outward in the first direction X. All of the first side portion 20a to the fourth side portion 20d are spaced inward from the periphery (first periphery 61 to fourth periphery 64) of the p-type well region 16 in a plan view. That is, the anode contact region 20 is formed in a surface layer portion of the p-type well region 16 and spaced inward from the periphery (first periphery 61 to fourth periphery 64) of the p-type well region 16.

[0050] 6, the fourth width W4 of the anode contact region 20 in the second direction Y is not less than 1.5 μm and not more than 2.0 μm. The fourth width W4 is wider than any of the first width W1, the second width W2, and the third width W3 (W4>W 1、 W4>W 2、 The fourth width W4 may be constant over the entire area in the first direction X. The anode contact region 20 may be formed in a rectangular shape extending elongatedly in the first direction X in a plan view.

[0051] 3 and 6, the anode contact region 20, the first cathode contact region 21, the second cathode contact region 22 and the third cathode contact region 23 are electrically isolated by a field insulating film 18 in the surface layer portion of the first main surface 3. In the surface layer portion of the first main surface 3, the first cathode contact region 21 surrounds the periphery of the anode contact region 20. Referring to FIG. 6, a first distance W in the second direction Y between the anode contact region 20 and the first cathode contact region 21 is 11 is not less than 1.0 μm and not more than 2.0 μm. The second cathode contact region 22 surrounds the outer periphery of the first cathode contact region 21. With reference to FIG. 6, the second distance W 12is not less than 1.0 μm and not more than 2.0 μm. The third cathode contact region 23 surrounds the outer periphery of the second cathode contact region 22. With reference to FIG. 6, the third distance W 13 is 1.0 μm or more and 2.0 μm or less.

[0052] Referring to FIG. 6, the first interval W 11 is the second interval W 12 It may be larger (W 11 >W 12 ). Third interval W 13 is the second interval W 12 may be the same as (W 13 =W 12 ). Third interval W 13 is the second interval W 12 It may be larger (W 13 >W 12 ), second interval W 12 It may be smaller (W 13 <W 12 ).

[0053] 5 and 6, the interlayer insulating film 24 is formed on the first main surface 3 of the semiconductor chip 2. The interlayer insulating film 24 covers the gate electrode 19. The interlayer insulating film 24 is formed of, for example, silicon oxide (SiO2) or silicon nitride (SiN2). In this embodiment, the interlayer insulating film 24 is formed of a single layer of silicon oxide, but may be formed of a plurality of interlayer insulating films 24.

[0054] 6, the anode wiring 25 is formed on the interlayer insulating film 24. The anode wiring 25 is electrically connected to the anode contact region 20 via an anode contact 26. With reference to Fig. 6, the anode contact 26 is formed to penetrate the interlayer insulating film 24 at a position overlapping the anode contact region 20 in a plan view.

[0055] 6, the cathode wiring 27 is formed on the interlayer insulating film 24. The cathode wiring 27 is electrically connected to the first cathode contact region 21, the second cathode contact region 22, and the third cathode contact region 23 via the first cathode contact 28, the second cathode contact 29, and the third cathode contact 30, respectively. With reference to FIGS. 4 and 7, the first cathode contact 28 is formed penetrating the interlayer insulating film 24 at a position overlapping the first cathode contact region 21 in a plan view. The second cathode contact 29 is formed penetrating the interlayer insulating film 24 at a position overlapping the second cathode contact region 22 in a plan view. The third cathode contact 30 is formed penetrating the interlayer insulating film 24 at a position overlapping the third cathode contact region 23 in a plan view.

[0056] In this embodiment, the anode wiring 25 and the cathode wiring 27 are made of aluminum (Al), but may be made of other conductive materials (for example, copper (Cu) etc.). In this embodiment, the anode contact 26, the first cathode contact 28, the second cathode contact 29 and the third cathode contact 30 are made of tungsten (W), but may be made of other conductive materials (for example, aluminum (Al), copper (Cu) etc.). In this case, it goes without saying that a barrier film such as TiN may be used.

[0057] Although not shown, a gate contact that is mechanically and electrically connected to the gate electrode 19 is embedded in the interlayer insulating film 24. The gate contact is electrically insulated from the anode contact 26, the first cathode contact 28, the second cathode contact 29, and the third cathode contact 30.

[0058] A pn junction diode Di1 (see FIG. 5) is formed by the p-type well region 16 and the inner diffusion region 15A adjacent to the p-type well region 16. When a forward bias is applied between the anode wiring 25 and the cathode wiring 27, a positive voltage is applied to the p-type well region 16 and a negative voltage is applied to the inner diffusion region 15A. In this case, a current flows from the anode contact region 20 through the pn junction diode Di1 to the first cathode contact region 21. As a result, a current path is formed in the surface layer portion of the first main surface 3 from the anode contact region 20 through the p-type well region 16 and the inner diffusion region 15A to the first cathode contact region 21.

[0059] In the diode 10, a vertical parasitic pnp transistor is formed by the p-type well region 16, the p-type semiconductor substrate 12, and the n-type semiconductor (n-type diffusion region 15 and n-type buried layer 14) therebetween. In addition, in the diode 10, a lateral parasitic pnp transistor is formed by the p-type well region 16, the p-type layer 17, and the inner diffusion region 15A therebetween. Generally, there is a risk of leakage current occurring due to these parasitic pnp transistors.

[0060] According to this embodiment, the impurity concentration of the n-type buried layer 14 is relatively high (1.0×10 13 Above 5.0×10 13 As a result, when a forward bias is applied between the anode wiring 25 and the cathode wiring 27, the amount of current flowing from the inner diffusion region 15n to the n-type buried layer 14 can be suppressed or prevented. As a result, the leakage current caused by the vertical parasitic pnp transistor described above can be suppressed or prevented.

[0061] In this embodiment, the n-type diffusion region 15 is divided by the p-type layer 17 outside the first cathode contact region 21. This makes it possible to suppress or prevent the current flowing from the anode contact region 20 to the first cathode contact region 21 from leaking outward from the region outside the anode contact region 20. This makes it possible to suppress or prevent the leakage current caused by the above-mentioned lateral parasitic pnp transistor.

[0062] In addition, since the n-type buried layer 14, which has a higher impurity concentration than the n-type diffusion region 15, is formed below the n-type diffusion region 15, it is possible to suppress or prevent the current flowing from the anode contact region 20 to the first cathode contact region 21 from leaking downward from the bottom of the n-type diffusion region 15.

[0063] Also, a pnp transistor Tr (see FIG. 5) is formed in the diode 10. The pnp transistor Tr is formed by a p-type well region 16, a p-type layer 17, and an inner diffusion region 15A sandwiched therebetween. A second cathode contact region 22 formed in the p-type layer 17 is connected to a cathode wiring 27. Therefore, the current flowing through the pnp transistor Tr is collected in the cathode wiring 27 via the second cathode contact region 22. This makes it possible to more effectively suppress or prevent the leakage current caused by the above-mentioned lateral parasitic pnp transistor.

[0064] Furthermore, a pn junction diode Di2 (see FIG. 5) is formed by the p-type layer 17 and the outer diffusion region 15B adjacent to the p-type layer 17. When a forward bias is applied between the anode wiring 25 and the cathode wiring 27, a negative voltage is applied not only to the inner diffusion region 15A but also to the outer diffusion region 15B.

[0065] When a forward bias is applied between the anode wiring 25 and the cathode wiring 27, as described above, a current path is formed from the anode contact region 20 through the p-type well region 16 and the inner diffusion region 15A to the first cathode contact region 21. In this case, even if a current leaks from the p-type layer 17 to the outside, the leaked current can be collected in the cathode wiring 27 via the pn junction diode Di2 and the first cathode contact region 21.

[0066] As described above, according to this embodiment, the leakage current can be reduced by improving the pn junction isolation without employing a module (such as SOI (Silicon On Insulator)) that physically reduces the leakage current.

[0067] 7A to 7M are diagrams showing, in order of steps, some of the manufacturing steps for the semiconductor device 1. FIGs. 7A to 7M correspond to FIG.

[0068] First, referring to Fig. 7A, a semiconductor wafer 101 is prepared. The semiconductor wafer 101 serves as a base for the semiconductor chip 2 (see Figs. 5 and 6). The semiconductor wafer 101 is a p-type wafer. The semiconductor wafer 101 corresponds to the semiconductor substrate 12 of the semiconductor device 1 (see Figs. 5 and 6).

[0069] 7B, a hard mask (not shown) having an opening corresponding to a region where n-type buried layer 14 (see FIGS. 5 and 6) is to be formed is disposed, and n-type impurities are selectively introduced into the surface portion of semiconductor wafer 101 through the hard mask. As a result, introduced portion 102 is formed in the surface portion of semiconductor wafer 101. Examples of n-type impurities include P (phosphorus) and As (arsenic).

[0070] Next, referring to FIG. 7C, the epitaxial layer 103 is formed by epitaxially growing silicon of the semiconductor wafer 101. The formation of the epitaxial layer 103 forms a semiconductor wafer structure 111 including a p-type epitaxial layer 13A. The epitaxial layer 103 corresponds to the p-type epitaxial layer 13A. The n-type impurity of the introduction portion 102 introduced into the main surface of the semiconductor wafer 101 diffuses into the p-type epitaxial layer 103 to form an n-type buried layer 14. The semiconductor wafer structure 111 has a first wafer main surface 112 on one side and a second wafer main surface 113 on the opposite side. The first wafer main surface 112 and the second wafer main surface 113 correspond to the first main surface 3 and the second main surface 4 of the semiconductor chip 2, respectively (see FIG. 5 and FIG. 6). Next, a sacrificial insulating film 114 is formed on the first wafer main surface 112. The sacrificial insulating film 114 may be, for example, a silicon oxide (SiO 2 ) film formed by thermally oxidizing the surface layer of the first wafer main surface 112 into a film shape.

[0071] Next, referring to Fig. 7D, a hard mask (not shown) having an opening corresponding to a region where n-type diffusion region 15 (see Figs. 5 and 6) is to be formed is disposed, and n-type impurities are selectively introduced into the surface portion of semiconductor wafer 101 through the hard mask. Next, semiconductor wafer structure 111 is heat-treated to diffuse the introduced n-type impurities. As a result, n-type diffusion region 15 is formed. N-type diffusion region 15 includes inner diffusion region 15A and outer diffusion region 15B.

[0072] Next, referring to FIG. 7E, a hard mask (not shown) having openings corresponding to a region for forming the p-type well region 16 (see FIG. 5 and FIG. 6) and a region for forming the upper p-type layer 31 (see FIG. 5 and FIG. 6) is disposed, and p-type impurities are selectively introduced into the surface portion of the semiconductor wafer 101 through the hard mask. Next, the semiconductor wafer structure 111 is heat-treated to diffuse the introduced p-type impurities. As a result, the upper p-type layer 31 and the p-type layer 17 are formed. Moreover, in the first direction X and the second direction Y, a region in the p-type epitaxial layer 13A between the inner diffusion region 15A and the outer diffusion region 15B where the upper p-type layer 31 is not formed becomes the lower p-type layer 32.

[0073] The order of forming the n-type diffusion region 15, the p-type well region 16, and the upper p-type layer 31 can be changed as appropriate. For example, the p-type well region 16 and the upper p-type layer 31 may be formed first, and then the n-type diffusion region 15 may be formed. Also, instead of forming the p-type well region 16 and the upper p-type layer 31 simultaneously, one of the p-type well region 16 and the upper p-type layer 31 may be formed first, and then the other of the p-type well region 16 and the upper p-type layer 31 may be formed.

[0074] 7F, a hard mask (not shown) is formed on the sacrificial insulating film 114, and the sacrificial insulating film 114 is selectively removed by etching through the hard mask to form openings 115. Next, the surface layer portion of the first wafer main surface 112 exposed from the openings 115 of the sacrificial insulating film 114 is thermally oxidized to form the field insulating film 18. Thereafter, the sacrificial insulating film 114 is removed.

[0075] 7G, a gate insulating film 54 is formed on the first wafer main surface 112. The gate insulating film 54 may be, for example, a silicon oxide (SiO2) film formed by thermally oxidizing a surface layer portion of the first wafer main surface 112 exposed from the first opening 41, the second opening 42, the third opening 43, and the fourth opening 44 of the field insulating film 18 into a film shape.

[0076] Next, referring to Fig. 7H, a base electrode 116 which serves as a base for the gate electrode 19 (see Figs. 5 and 6) is formed on the first wafer main surface 112 so as to cover the gate insulating film 54 and the field insulating film 18. In this embodiment, the base electrode 116 is made of conductive polysilicon. The base electrode 116 may be formed by, for example, a CVD method.

[0077] 7I, unnecessary portions of the base electrode 116 are removed by etching through a hard mask (not shown) having a predetermined pattern. As a result, the gate electrode 19 is formed. The etching may be, for example, dry etching (e.g., RIE method) or wet etching. Thereafter, the gate insulating film 54 exposed from the gate electrode 19 is removed, thereby exposing the p-type well region 16 from the opening 50, and the inner diffusion region 15A (n-type diffusion region 15) from the first opening 41 of the field insulating film 18.

[0078] Next, referring to Fig. 7J, a base insulating film 117 serving as a base of the sidewall structure 57 (see Fig. 6) is sequentially formed on the first wafer main surface 112. The base insulating film 117 may be formed by, for example, a CVD method. Next, unnecessary portions of the base insulating film 117 are removed by etch-back. As a result, the sidewall structure 57 is formed by the base insulating film 117 remaining on the inner side portion and the outer side portion of the gate electrode 19.

[0079] Next, referring to FIG. 7K, the anode contact region 20 and the second cathode contact region 22 are formed in the surface layer portion of the p-type well region 16 and the surface layer portion of the upper p-type layer 31 (i.e., the surface layer portion of the p-type layer 17), respectively. Also, the first cathode contact region 21 and the third cathode contact region 23 are formed in the surface layer portion of the inner diffusion region 15A (n-type diffusion region 15) and the surface layer portion of the outer diffusion region 15B (n-type diffusion region 15), respectively. In this embodiment, the anode contact region 20 is formed by injecting p-type impurities into the surface layer portion of the p-type well region 16 by ion implantation using the sidewall structure 57 as a hard mask. That is, the anode contact region 20 is formed in a self-aligned manner with respect to the periphery of the sidewall structure 57 of the gate electrode 19. The first cathode contact region 21 and the third cathode contact region 23 are formed by injecting n-type impurities into the surface layer of the inner diffusion region 15A and the outer diffusion region 15B, respectively, by ion implantation using the field insulating film 18 as a hard mask. That is, the first cathode contact region 21 and the third cathode contact region 23 are formed in a self-aligned manner with respect to the periphery of the first opening 41 and the third opening 43 of the field insulating film 18, respectively. The second cathode contact region 22 is formed by injecting p-type impurities into the surface layer of the upper p-type layer 31 by ion implantation using the field insulating film 18 as a hard mask. That is, the second cathode contact region 22 is formed in a self-aligned manner with respect to the periphery of the second opening 42 of the field insulating film 18.

[0080] 7L, the interlayer insulating film 24 is formed on the first wafer main surface 112. The interlayer insulating film 24 may be formed by, for example, a CVD method.

[0081] Next, referring to FIG. 7M, an anode contact 26, a first cathode contact 28, a second cathode contact 29 and a third cathode contact 30 are formed in the interlayer insulating film 24 by etching through a hard mask (not shown) having a predetermined pattern, forming a metal film by a CVD method, and etching away unnecessary metal film. Next, a base wiring film that serves as a base for a plurality of wirings is formed on the interlayer insulating film 24 and patterned to form an anode wiring 25 and a cathode wiring 27. Thereafter, the semiconductor wafer structure 111 is cut and a plurality of semiconductor chips 2 are cut out. Through the steps including those described above, the semiconductor device 1 is manufactured.

[0082] 8 is an electric circuit diagram showing the configuration of a signal output circuit 301 to which the diode 10 of the semiconductor device 1 is applied. The signal output circuit 301 is a circuit used, for example, in a controller area network (CAN), which is a type of in-vehicle network. The signal output circuit 301 includes a high-side output unit 302, a low-side output unit 303, a resistive divider circuit 304, a high-side output terminal 305, and a low-side output terminal 306.

[0083] The high-side output unit 302 includes a driving transistor 307, a first diode 308, and a protection transistor 309. The first diode 308 is connected in series to the driving transistor 307. The protection transistor 309 is connected in series to the first diode 308. In this embodiment, the driving transistor 307 and the protection transistor 309 include p-type MOS transistors (PMOS). The first diode 308 functions as a reverse current prevention circuit. The diode 10 of the semiconductor device 1 is used as the first diode 308. The source of the driving transistor 307 is connected to the first power supply VCC1. The drain of the driving transistor 307 is connected to the anode of the first diode 308. The cathode of the first diode 308 is connected to the source of the protection transistor 309. The drain of the protection transistor 309 is connected to the high-side output terminal 305. The gate of the protection transistor 309 is grounded.

[0084] The low-side output section 303 includes a second diode 310, a protection transistor 311, and a driving transistor 312. The second diode 310 is connected in series to the protection transistor 311. The protection transistor 311 is connected in series to the second diode 310. The driving transistor 312 is connected in series to the protection transistor 311. In this embodiment, the protection transistor 311 and the driving transistor 312 include n-type MOS transistors (NMOS). The anode of the second diode 310 is connected to the low-side output terminal 306. The cathode of the second diode 310 is connected to the drain of the protection transistor 311. The gate of the protection transistor 311 is connected to the first power supply VCC1. The source of the protection transistor 311 is connected to the drain of the driving transistor 312. The source of the driving transistor 312 is grounded.

[0085] The resistive divider circuit 304 includes a first resistor 313 and a second resistor 314. One end of the first resistor 313 is connected to the high-side output terminal 305. One end of the second resistor 314 is connected to the other end of the first resistor 313. The other end of the second resistor 314 is grounded. A second power supply VCC2 is connected to the connection point between the first resistor 313 and the second resistor 314.

[0086] The high-side output terminal 305 is connected to a first bus line. The low-side output terminal 306 is connected to a second bus line. A load resistor is connected between the first bus line and the second bus line. The load resistors are a high-side load resistor 315A and a low-side load resistor 315B, which are connected in series at a connection node N. The load resistors 315A and 315B have the same resistance value.

[0087] For example, the first power supply VCC1 is set to 5V. At this time, the connection node N is set to 2.5V, which is a midpoint voltage. Since the current flowing through the first resistor 313 and the second resistor 314 is common, the voltage drops occurring in the first resistor 313 and the second resistor 314 are the same, so that the high-side signal CANH occurring at the high-side output terminal 305 is a voltage higher than the voltage of the connection node N (=midpoint voltage) by the voltage drop, and the low-side signal CANL occurring at the low-side output terminal 306 is a voltage lower than the voltage of the connection node N (=midpoint voltage) by the voltage drop. The midpoint voltage may be referred to as a common voltage.

[0088] A control signal is applied to the gate of the driving transistor 307. An inverted signal of the control signal is applied to the gate of the driving transistor 312. When the control signal is at an L level, both driving transistors 307 and 312 are turned on. As a result, a high-side signal CANH of 3.5 V (standard value) is output to the high-side output terminal 305, and a low-side signal CANL of 1.5 V (standard value) is output to the low-side output terminal 306 (dominant state). On the other hand, when the control signal is at an H level, both driving transistors 307 and 312 are turned off. As a result, a high-side signal CANH of 2.5 V (standard value) is output to the high-side output terminal 305, and a low-side signal CANL of 2.5 V (standard value) is output to the low-side output terminal 306 (recessive state).

[0089] In this embodiment, the diode 10 of the semiconductor device 1 is used as the first diode 308 of the high side output section 302 and the second diode 310 of the low side output section 303 .

[0090] If, instead of the diode 10 of the semiconductor device 1, other diodes (diodes with insufficient reduction in leakage current) were used as the first diode 308 and the second diode 310, the following problem would occur. That is, because leakage current exists in the first diode 308 and the second diode 310, the current I a The value of the current ICANH becomes lower than the value of (I CANL CANH In this case, the voltage (=midpoint voltage) of the connection node N may drop. If this voltage (=midpoint voltage) drops, the voltages of the high-side signal CANH and the low-side signal CANL may drop from their intended voltages. In order to achieve good CAN communication, it is necessary to sufficiently reduce the leakage current of the first diode 308 and the second diode 310. Then, the current I CANL The value of current I CANH As close as possible to the value of I CANL =I CANH ) is preferred.

[0091] In this embodiment, the diode 10 of the semiconductor device 1 is used as the first diode 308 and the second diode 310. Therefore, the leakage current of the first diode 308 and the second diode 310 can be sufficiently reduced, and the current I CANL The value of current I CANH can be as close as possible to the value of

[0092] FIG. 9 is a diagram for explaining the effect of the semiconductor device 1. As shown in FIG.

[0093] [Table 1]

[0094] In Table 1, the leakage current ratio (leakage current value (I CANH -I CANL ) / current value (I CANH )) are compared between the semiconductor device 1 and the semiconductor device of the reference example. The semiconductor device of the reference example differs from the semiconductor device 1 in that the bottom of the p-type layer 17 does not reach the n-type buried layer 14 (i.e., the lower p-type layer 32 is not provided). The semiconductor device of the reference example is common to the semiconductor device 1 in the remaining points.

[0095] ​It is apparent from Table 1 that the semiconductor device 1 can achieve a reduction in leakage current compared to the semiconductor device according to the reference example.

[0096] Fig. 9 is a schematic cross-sectional view of a semiconductor device 201 according to a second embodiment of the present disclosure, and corresponds to Fig. 7. In Fig. 10, the same components as those described above are denoted by the same reference symbols, and the description thereof will be omitted.

[0097] The semiconductor device 201 differs from the semiconductor device 1 according to the first embodiment in that a p-type layer 217 is provided instead of the p-type layer 17. The p-type layer 217 differs from the p-type layer 17 according to the first embodiment in that the p-type layer 217 is formed only from a p-type diffusion layer 217a. The bottom of the p-type diffusion layer 217a extends in the depth direction and reaches the n-type buried layer 14.

[0098] The semiconductor device 201 according to the second embodiment of the present disclosure provides the same advantageous effects as those described in relation to the first embodiment.

[0099] In addition, in the semiconductor device 1 and the semiconductor device 201, the first cathode contact region 21, the second cathode contact region 22, and the third cathode contact region 23 have been described as being rectangular ring-shaped, but the cathode contact regions 21-23 may be strip-shaped and long in the first direction X. In this case, the cathode contact regions 21-23 are formed in pairs, sandwiching the anode contact region 20 in the second direction Y.

[0100] In each of the above-described embodiments, the first conductivity type is p-type and the second conductivity type is n-type, but the first conductivity type may be n-type and the second conductivity type may be p-type. A specific configuration in this case can be obtained by replacing the p-type region with an n-type region and the n-type region with a p-type region in the above description and the accompanying drawings.

[0101] In the above-described embodiments, the signal output circuit 301 has been described as a circuit used in a CAN, which is a type of in-vehicle network, but the diodes 308, 310 (i.e., the diode 10 of the semiconductor device 1) used in the signal output circuit 301 can be applied not only to signal output circuits used in a CAN, but also to signal output circuits used in other in-vehicle networks such as a LIN (Local Interconnect Network) and FlexRay. Of course, the diode 10 of the semiconductor device 1 can also be applied to a diode for an in-vehicle switch IC, a diode for a DC / DC converter, etc.

[0102] The embodiments of the present disclosure are illustrative in all respects and should not be construed as limiting, and are intended to include modifications in all respects.

[0103] The following characteristics can be extracted from the description of this specification and the drawings. Below, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiment, but are not intended to limit the scope of each clause to the embodiment.

[0104] [Appendix 1-1] A semiconductor substrate (12) of a first conductivity type; a second conductive type diffusion region (15) selectively formed in a surface layer portion of the semiconductor substrate (12); a second conductive type buried layer (14) formed between the semiconductor substrate (12) and the second conductive type diffusion region (15) and having a higher impurity concentration than the second conductive type diffusion region (15); a first conductivity type anode contact region (20) formed on a surface layer portion of the main surface (3); a first cathode contact region (21) of a second conductivity type formed in a surface layer portion of the second conductivity type diffusion region (15) and in a surface layer portion of the main surface (3); a first conductivity type layer (17, 217) extending in a depth direction from the main surface (3) of the semiconductor substrate (12) outside the first cathode contact region (21) to reach the second conductivity type buried layer (14) and dividing the second conductivity type diffusion region (15) in a direction along the main surface.

[0105] According to this configuration, a current path is formed in the second conductivity type diffusion region (15) from the anode contact region (20) to the first cathode contact region (21). The second conductivity type diffusion region (15) is divided by the first conductivity type layer (17, 217) on the outer side of the first cathode contact region (21). This makes it possible to suppress or prevent a current flowing from the anode contact region (20) to the first cathode contact region (21) from flowing outward from a region outside the first cathode contact region (21).

[0106] In addition, since the second conductivity type buried layer (14) having a higher impurity concentration than the second conductivity type diffusion region (15) is formed below the second conductivity type diffusion region (15), it is possible to suppress or prevent the current flowing from the anode contact region (20) to the first cathode contact region (21) from flowing downward from the bottom of the second conductivity type diffusion region (15).

[0107] As a result, a semiconductor device (1, 201) having a diode capable of reducing leakage current can be provided.

[0108] [Appendix 1-2] The semiconductor device (1, 201) described in Appendix 1-1, wherein the first conductivity type layer (17, 217) is annular in a planar view and divides the second conductivity type diffusion region (15) in both a first direction (X) along the main surface (3) and a second direction (Y) along the main surface (3) and intersecting the first direction (X).

[0109] [Appendix 1-3] The second cathode contact region (22) of the first conductivity type is formed outside the first cathode contact region (21) in a surface layer portion of the main surface (3), The semiconductor device (1, 201) according to Appendix 1-1 or Appendix 1-2, wherein the first conductive type layer (17, 217) is electrically connected to the second cathode contact region (22).

[0110] [Appendix 1-4] The semiconductor device (1, 201) according to appendix 1-3, wherein the second cathode contact region (22) is formed in a surface layer portion of the first conductivity type layer (17, 217).

[0111] [Appendix 1-5] a third cathode contact region (23) of a second conductivity type formed outside the second cathode contact region (22) in a surface layer portion of the main surface (3); the second conductive type diffusion region (15) includes an outer diffusion region (15B) formed outside the first conductive type layer (17, 217); The semiconductor device (1, 201) according to any one of claims 1-3 to 1-4, wherein the outer diffusion region (15B) is electrically connected to the third cathode contact region (23).

[0112] [Appendix 1-6] The semiconductor device (1, 201) according to claim 1-5, wherein the third cathode contact region (23) is formed in a surface layer portion of the outer diffusion region (15B).

[0113] [Appendix 1-7] The semiconductor device (1) according to any one of Appendices 1-1 to 1-6, wherein the first conductivity type layer (17) includes an upper first conductivity type layer (31) and a lower first conductivity type layer (32) formed adjacent to and below the upper first conductivity type layer (31) and having an impurity concentration different from that of the upper first conductivity type layer (31).

[0114] [Appendix 1-8] The semiconductor device (1) according to appendix 1-7, wherein the upper first conductivity type layer (31) has a higher impurity concentration than the lower first conductivity type layer (32).

[0115] [Appendix 1-9] The upper first conductive type layer (31) includes a first conductive type diffusion layer made of a diffusion layer, The semiconductor device (1) according to claim 1-8, wherein the lower first conductivity type layer (32) includes a first conductivity type epitaxial layer made of an epitaxial layer.

[0116] [Appendix 1-10] a first-conductivity-type well region (16) formed adjacent to the second-conductivity-type diffusion region (15) in a surface layer portion of the main surface (3), the first-conductivity-type well region (16) having the anode contact region (20) formed in a surface layer portion thereof; The semiconductor device (1) according to any one of Appendices 1-7 to 1-9, wherein a first depth (D1) of a bottom of the upper first conductivity type layer (31) is the same as a second depth (D2) of a bottom of the first conductivity type well region (16).

[0117] [Appendix 1-11] the first conductive type layer (217) includes a first conductive type diffusion layer (217a) made of a diffusion layer, The semiconductor device (201) according to any one of Appendix 1-1 to Appendix 1-10, wherein a bottom of the first conductive type diffusion layer (217a) extends in a depth direction from the main surface to reach the second conductive type buried layer (14).

[0118] [Appendix 1-12] the anode contact region (20) and the first cathode contact region (21) are strip-shaped extending in a first direction (X) along the main surface (3); The semiconductor device (1,201) according to any one of Appendices 1-1 to 1-11, wherein a width (W4) of the anode contact region (20) in a second direction (Y) along the main surface (3) and intersecting the first direction (X) is wider than a width (W1) of the first cathode contact region (21) in the second direction (Y).

[0119] [Appendix 1-13] a first-conductivity-type well region (16) formed adjacent to the second-conductivity-type diffusion region (15) in a surface layer portion of the main surface (3); The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-12, wherein the second conductivity type diffusion region (15) includes a lower diffusion region (15C) sandwiched vertically between the second conductivity type buried layer (14) and the first conductivity type well region (16).

[0120] [Appendix 1-14] The semiconductor device (1, 201) according to any one of Appendix 1-1 to Appendix 1-13, wherein an impurity concentration of the second conductive type buried layer is ten times or more higher than an impurity concentration of the second conductive type diffusion region.

[0121] [Appendix 1-15] The semiconductor device (1, 201) according to any one of Supplementary Notes 1-1 to 1-14, wherein the first conductivity type is p-type and the second conductivity type is n-type. 1: Semiconductor device 2: Semiconductor chips 3: First main surface (main surface) 4: Second main surface 5 :1st side 6:Second side 7:Third side 8: 4th side 9: Device area 10: Diode 11: Diode region 12: Semiconductor substrate 13: Semiconductor layer 14: n-type buried layer (second conductive type buried layer) 15: n-type diffusion region (second conductivity type diffusion region) 15A: Inner diffusion area 15B:Outer diffusion area 15C: Outer diffusion area 16: p-type well region (first conductivity type well region) 17:p-type layer (first conductivity type layer) 18: Field insulating film 19: Gate electrode 20: Anode contact area 20a: First side 20b: second side 20c: Third side 20d: 4th side 21: First cathode contact region 21a: First side 21b: second side 21c: Third side 21d: 4th side 22: Second cathode contact region 22a: First side 22b: Second side 22c: Third side 22d: 4th side 23: Third cathode contact region 23a: First side 23b: Second side 23c: Third side 23d: 4th side 24: Interlayer insulating film 25: Anode wiring 26: Anode contact 27: Cathode wiring 28: First cathode contact 29: Second cathode contact 30: 3rd cathode contact 31: Upper p-type layer (upper first conductivity type layer) 32: Lower p-type layer (lower first conductivity type layer) 41: First opening 42: Second opening 43: 3rd opening 44: 4th opening 50: Opening 51 :1st part 52:Second part 53: Channel region 54: Gate insulating film 55: Control section 56: Field plate section 57: Sidewall structure 61: First periphery 62: Second periphery 63: Third periphery 64: 4th periphery 101: Semiconductor wafer 102: Introduction 103: Epitaxial layer 108: First diode 111: Semiconductor wafer structure 112: First wafer main surface 113: Second wafer main surface 114: Sacrificial insulating film 115 :Aperture 116: Base electrode 117: Base insulating film 201: Semiconductor device 217:p-type layer (first conductivity type layer) 217a: n-type diffusion layer (first conductive type diffusion layer) 301: Signal output circuit 302: High side output section 303: Low side output section 304: Resistor divider circuit 305: High side output terminal 306: Low side output terminal 307: Drive transistor 308: First diode 309: Protective transistor 310: Second diode 311: Protective transistor 312: Drive transistor 313: 1st resistor 314: 2nd resistor 315A: Load resistance 315B: Load resistance CANH: High side signal CANL: Low side signal D1: First depth D2: Second depth I CANH :Current I CANL :Current VCC1: 1st power supply VCC2: 2nd power supply W1: First width (width of the first cathode contact region in the second direction) W2: Second width W3: 3rd width W4: Fourth width (width of the anode contact region in the second direction) W 11 :First interval W 12 :Second interval W 13 :Third interval X: 1st direction Y: Second direction Z: 3rd direction

Claims

1. a semiconductor substrate of a first conductivity type; A second conductivity type diffusion region selectively formed in a surface layer portion of the semiconductor substrate; a second conductive type buried layer formed between the semiconductor substrate and the second conductive type diffusion region and having an impurity concentration higher than that of the second conductive type diffusion region; an anode contact region of a first conductivity type formed on a surface layer portion of the main surface; a first cathode contact region of a second conductivity type formed in a surface layer portion of the second conductivity type diffusion region; a first conductivity type layer extending in a depth direction from the main surface of the semiconductor substrate outside the first cathode contact region to reach the second conductivity type buried layer, and dividing the second conductivity type diffusion region in a direction along the main surface.

2. 2. The semiconductor device according to claim 1, wherein the first conductivity type layer is annular in a planar view and divides the second conductivity type diffusion region in both a first direction along the main surface and a second direction along the main surface and intersecting the first direction.

3. a second cathode contact region of the first conductivity type formed outside the first cathode contact region in a surface layer portion of the main surface, The semiconductor device according to claim 1 , wherein the first conductive type layer is electrically connected to the second cathode contact region.

4. The semiconductor device according to claim 3 , wherein the second cathode contact region is formed in a surface portion of the first conductive type layer.

5. a third cathode contact region of a second conductivity type formed outside the second cathode contact region in a surface layer portion of the main surface, the second conductive type diffusion region includes an outer diffusion region formed outside the first conductive type layer; The semiconductor device of claim 3 , wherein the outer diffusion region is electrically connected to the third cathode contact region.

6. 6. The semiconductor device according to claim 5, wherein said third cathode contact region is formed in a surface layer portion of said outer diffusion region.

7. 7. The semiconductor device according to claim 1, wherein the first conductivity type layer includes an upper first conductivity type layer and a lower first conductivity type layer formed adjacent to and below the upper first conductivity type layer and having an impurity concentration different from that of the upper first conductivity type layer.

8. 8. The semiconductor device according to claim 7, wherein the upper layer of the first conductivity type has an impurity concentration higher than an impurity concentration of the lower layer of the first conductivity type.

9. the upper first conductive type layer includes a first conductive type diffusion layer made of a diffusion layer, 9. The semiconductor device according to claim 8, wherein the lower first conductivity type layer includes a first conductivity type epitaxial layer made of an epitaxial layer.

10. a first conductivity type well region formed adjacent to the second conductivity type diffusion region in a surface layer portion of the main surface, the first conductivity type well region having the anode contact region formed in a surface layer portion thereof; 10. The semiconductor device according to claim 9, wherein a first depth of a bottom of said upper first conductivity type layer is the same as a second depth of a bottom of said first conductivity type well region.

11. the first conductive type layer includes a first conductive type diffusion layer made of a diffusion layer, 7. The semiconductor device according to claim 1, wherein a bottom of said first conductive type diffusion layer extends in a depth direction from said main surface to reach said second conductive type buried layer.

12. the anode contact region and the first cathode contact region are strip-shaped extending in a first direction along the main surface, The semiconductor device according to any one of claims 1 to 6, wherein the width of the anode contact region in a second direction along the main surface and intersecting the first direction is wider than the width of the first cathode contact region in the second direction.

13. a first conductivity type well region formed adjacent to the second conductivity type diffusion region in a surface layer portion of the main surface, 7. The semiconductor device according to claim 1, wherein the second conductivity type diffusion region includes a lower diffusion region sandwiched vertically between the second conductivity type buried layer and the first conductivity type well region.

14. 7. The semiconductor device according to claim 1, wherein an impurity concentration of said second conductive type buried layer is ten times or more higher than an impurity concentration of said second conductive type diffusion region.

15. 7. The semiconductor device according to claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.

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