Power amplification device

Abstract

To downsize a power amplification device.SOLUTION: A power amplification device comprises: a substrate having a surface; an integrated circuit, provided on the surface, which has a carrier amplifier and a peak amplifier; a carrier balun to be connected to the carrier amplifier; a peak balun to be connected to the peak amplifier; and a surface-mounted component provided on the surface. Each of the carrier amplifier and the peak amplifier is a pair of differential amplifiers. The substrate has a plurality of insulating layers disposed in a lamination direction. The surface is provided with an electrode to which the surface-mounted component is soldered. Viewing from the lamination direction, there are disposed, on one side in a first plane direction of the integrated circuit, the carrier balun, the electrode, and the peak balun arranged in this order in a second plane direction. One of the carrier balun and the peak balun is provided on the insulating layers disposed in a first lamination direction with respect to the insulating layers constituting the surface, and it is at least partially overlaps the electrode when viewed from the lamination direction.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001] The present disclosure relates to a power amplifier device. [Background technology]

[0002] One type of power amplifier device is a differential amplifier device having a differential Doherty circuit. In the differential Doherty circuit, a carrier amplifier and a peak amplifier are connected in parallel. The carrier amplifier operates regardless of the power level of the input signal. The peak amplifier is turned off when the power level of the input signal is low, and turned on when the power level is high. The differential Doherty circuit also has a carrier balun connected to the carrier amplifier, a peak balun connected to the peak amplifier, and an adjustment circuit (components for the adjustment circuit). Regarding the layout on the board, the carrier balun and the peak balun are arranged adjacent to one side of the integrated circuit having the carrier amplifier and the peace amplifier. In other words, the carrier balun and the peak balun are arranged next to each other. In addition, surface mount components such as components for the adjustment circuit are attached to the surface of the board. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-170224 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, if the distance between the carrier balun and the peak balun is small, the carrier balun and the peak balun will electromagnetically interfere with each other. This may result in deterioration of characteristics. For this reason, the carrier balun and the peak balun are spaced apart by a certain distance or more. The space between the carrier balun and the peak balun is dead space, which leads to an increase in the size of the power amplifier. Therefore, there is a demand for a power amplifier that utilizes this dead space to be miniaturized.

[0005] The present disclosure has been made in consideration of the above, and has an object to provide a miniaturized power amplifier device. [Means for solving the problem]

[0006] A power amplifier according to one aspect of the present disclosure includes a substrate having a surface, an integrated circuit having a carrier amplifier and a peak amplifier and provided on the surface, a carrier balun connected to the carrier amplifier, a peak balun connected to the peak amplifier, and a surface-mounted component provided on the surface. The carrier amplifier and the peak amplifier are each a pair of differential amplifiers. A direction in which the integrated circuit and the substrate are arranged is defined as a stacking direction. A direction in which the substrate is arranged as viewed from the integrated circuit in the stacking direction is defined as a first stacking direction. A direction parallel to the surface is defined as a first planar direction. A direction parallel to the surface and intersecting the first planar direction is defined as a second planar direction. The substrate has a plurality of insulating layers arranged in the stacking direction. An electrode to which the surface-mounted component is soldered is provided on the surface. When viewed from the stacking direction, the carrier balun, the electrode, and the peak balun are arranged in order in the second planar direction on one side of the first planar direction of the integrated circuit. One of the carrier balun and the peak balun is provided on the insulating layer arranged in the first stacking direction further than the insulating layer constituting the surface, and at least a portion of it overlaps with the electrode when viewed from the stacking direction.

[0007] A power amplifier according to one aspect of the present disclosure includes a substrate having a surface, an integrated circuit having a carrier amplifier and a peak amplifier and provided on the surface, a carrier balun connected to the carrier amplifier, a peak balun connected to the peak amplifier, and an inductor that is a surface-mounted component provided on the surface. The carrier amplifier and the peak amplifier are each a pair of differential amplifiers. A direction in which the integrated circuit and the substrate are arranged is defined as a stacking direction. A direction in which the substrate is arranged as viewed from the integrated circuit in the stacking direction is defined as a first stacking direction. A direction parallel to the surface is defined as a first planar direction. A direction parallel to the surface and intersecting the first planar direction is defined as a second planar direction. The substrate has a plurality of insulating layers arranged in the stacking direction. The carrier balun includes a primary carrier balun and a secondary carrier balun, each of which has a center line of a winding extending in the stacking direction. One of the primary carrier balun and the secondary carrier balun is provided on the surface, and the other is provided on the insulating layer arranged in the first stacking direction further than the insulating layer constituting the surface. The peak balun has a primary peak balun and a secondary peak balun, each of which has a center line of a winding extending in the lamination direction. One of the primary peak balun and the secondary peak balun is provided on the surface, and the other is provided on the insulating layer that is disposed in the first lamination direction further than the insulating layer that constitutes the surface. When viewed from the lamination direction, the carrier balun, the inductor, and the peak balun are arranged in order in the second planar direction on one side of the first planar direction of the integrated circuit. The center line of the winding of the inductor extends in the second planar direction.

[0008] A power amplifier according to one aspect of the present disclosure includes a substrate having a surface, an integrated circuit having a carrier amplifier and a peak amplifier and provided on the surface, a carrier balun connected to the carrier amplifier, a peak balun connected to the peak amplifier, and an inductor that is a surface-mounted component provided on the surface. The carrier amplifier and the peak amplifier are each a pair of differential amplifiers. A direction in which the integrated circuit and the substrate are arranged is defined as a stacking direction. A direction in which the substrate is arranged as viewed from the integrated circuit in the stacking direction is defined as a first stacking direction. A direction parallel to the surface is defined as a first planar direction. A direction parallel to the surface and intersecting the first planar direction is defined as a second planar direction. The substrate has a plurality of insulating layers arranged in the stacking direction. As viewed from the stacking direction, the carrier balun, the inductor, and the peak balun are arranged in order in the second planar direction on one side of the first planar direction of the integrated circuit. The carrier balun has a primary side carrier balun and a secondary side carrier balun, each of which has a center line of a winding extending in the stacking direction and is provided on the insulating layers different from each other. The peak balun has a primary peak balun and a secondary peak balun, each of which has a center line of a winding extending in the lamination direction and is provided on a different insulating layer. One of the carrier balun and the peak balun is provided on an insulating layer that is disposed in the first lamination direction further than the insulating layer that constitutes the surface. The center line of the inductor winding extends in the second plane direction. Effect of the Invention

[0009] According to the present disclosure, the power amplifier device is miniaturized. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an overall circuit configuration of a power amplifying device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic diagram showing an example of the relationship between the power of a high-frequency signal in the power amplifier circuit of the first embodiment and the signal output by the detection circuit. [Diagram 3]FIG. 3 is a diagram showing a specific example of a detection circuit and a drive level detection circuit of the power amplifier circuit of the first embodiment. [Figure 4] FIG. 4 is a diagram showing an equivalent circuit of a specific example of the detection circuit and the drive level detection circuit of the power amplifier circuit according to the fifth embodiment. In FIG. [Diagram 5] FIG. 5 is a diagram showing an example of the relationship between the power of a high-frequency signal in the power amplifier circuit of the first embodiment and the bias voltage applied to the peak amplifier. [Figure 6] FIG. 6 is a diagram showing a circuit configuration of a Doherty circuit in the power amplifying device of the first embodiment. [Figure 7] FIG. 7 is a plan view of the surface of the substrate in the power amplifier device of the first embodiment. [Figure 8] FIG. 8 is a diagram for explaining the layout of the second insulating layer in the power amplifier device of the first embodiment. [Figure 9] FIG. 9 is a diagram for explaining the layout of the third insulating layer in the power amplifier device of the first embodiment. [Figure 10] FIG. 10 is an enlarged view of a part of FIG. [Figure 11] FIG. 11 is a plan view showing the front surface of the substrate of the power amplifying device of the first modified example. [Figure 12] FIG. 12 is a diagram showing a circuit configuration of a Doherty circuit in a power amplifying device according to a second modified example. [Figure 13] FIG. 13 is a plan view of the surface of a substrate in a power amplifying device according to the second modified example. [Figure 14] FIG. 14 is a diagram for explaining the layout of the second insulating layer in the power amplifier device of the second modified example. [Figure 15] FIG. 15 is a diagram for explaining the layout of the third insulating layer in the power amplifier device of the second modified example. [Figure 16] FIG. 16 is a schematic cross-sectional view taken along line XVI-XVI in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments of the power amplifier device of the present disclosure will be described in detail with reference to the drawings. Note that the present disclosure is not limited to these embodiments. Each embodiment is an example, and it goes without saying that partial replacement or combination of the configurations shown in different embodiments is possible. From the third modification onwards, a description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0012] First, the overall configuration of the power amplifier device 100 will be described, and then the differential Doherty circuit will be described in detail. In the power amplifier device 100 of the present disclosure, the carrier amplifier and the peak amplifier are each composed of a pair of differential amplifiers 13a, 13b, 17a, 17b (see FIG. 6), but in order to simplify the description of the overall configuration of the power amplifier device 100, an example will be described in which a single-ended carrier amplifier 13 and a peak amplifier 17 are used instead of a pair of differential amplifiers.

[0013] (First embodiment) 1 is a diagram showing an overall circuit configuration of a power amplifier device according to a first embodiment. The power amplifier device 100 includes a power amplifier circuit 1. The power amplifier circuit 1 includes an amplifier 2, a bias circuit 3, and a Doherty amplifier circuit 10. The Doherty amplifier circuit 10 includes a splitter 11, a carrier amplifier 12 in a first stage (driver stage), a carrier amplifier 13 in a final stage (power stage), a bias circuit 14, a bias circuit 15, a peak amplifier 16 in the first stage (driver stage), a peak amplifier 17 in the final stage (power stage), a bias circuit 18, a bias circuit 19, a coupler 40, a control circuit 21, and an adjustment circuit 60.

[0014] The control circuit 21 includes a detection circuit 22 and a drive level detection circuit 26. The number of stages in the Doherty amplifier circuit 10 is two, but the present disclosure is not limited to this. The number of stages in the Doherty amplifier circuit 10 may be one, or three or more.

[0015] The bias circuit 3 applies a bias to the amplifier 2. A radio frequency signal RF (Radio Frequency) is input to the amplifier 2. The frequency of the radio frequency signal RFin is, for example, about several GHz. The amplifier 2 amplifies the input radio frequency signal RFin. The amplifier 2 then outputs the amplified radio frequency signal RF1 to the splitter 11. Note that hereinafter, the radio frequency signal RF may be simply referred to as a signal RF.

[0016] The splitter 11 is a 90° hybrid circuit. The 90° hybrid circuit splits the high frequency signal RF1 into high frequency signals RF2 and RF5, which differ in phase by approximately 90°, outputs the high frequency signal RF2 to the carrier amplifier 12, and outputs the high frequency signal RF5 to the peak amplifier 16. Note that "approximately 90°" does not only include a phase of 90°, but also includes a phase of 45° to 135°. The phase of the high frequency signal RF2 lags behind that of the high frequency signal RF5 by 90°. The power of the high frequency signal RF2 and the power of the high frequency signal RF5 are the same.

[0017] The bias circuit 14 applies a bias to the carrier amplifier 12. The bias circuit 15 applies a bias to the carrier amplifier 13. The carrier amplifier 12 outputs a high-frequency signal RF3 obtained by amplifying the high-frequency signal RF2 to the carrier amplifier 13. The carrier amplifier 13 outputs a high-frequency signal RF4 obtained by amplifying the high-frequency signal RF3 to the coupler 40.

[0018] The bias circuit 18 applies a bias to the peak amplifier 16. The bias circuit 19 applies a bias to the peak amplifier 17. The peak amplifier 16 outputs a high frequency signal RF6 obtained by amplifying the high frequency signal RF5 to the peak amplifier 17. The peak amplifier 17 outputs a high frequency signal RF7 obtained by amplifying the high frequency signal RF6 to the coupler 40.

[0019] The coupler 40 couples the high frequency signal RF4 and the high frequency signal RF7. The coupler 40 delays the phase of the high frequency signal RF7 by 90° and couples it with the high frequency signal RF4. The adjustment circuit 60 is a circuit that matches the impedance between the output ends of the carrier amplifier 13 and the peak amplifier 17 and the output terminal of the power amplifier circuit 1. The coupler 40 and the adjustment circuit 60 will be described in detail later.

[0020] The drive level detection circuit 26 outputs a signal S1 representing the drive level (operation level) of the carrier amplifier 13 to the detection circuit 22 based on the high frequency signal RF4 output by the carrier amplifier 13.

[0021] A high frequency signal RFin and a signal S1 are input to the detection circuit 22. In the present disclosure, a high frequency signal RF1 or a high frequency signal RF2 may be input to the detection circuit 22 instead of the high frequency signal RFin.

[0022] The detection circuit 22 outputs a signal S2 that controls the bias circuits 18 and 19 to the bias circuits 18 and 19 based on the high frequency signal RFin and the signal S1. Then, the bias circuit 18 provides a bias to the peak amplifier 16 based on the signal S2. The bias circuit 19 provides a bias to the peak amplifier 17 based on the signal S2. In other words, the detection circuit 22 controls the bias of the peak amplifiers 16 and 17 based on the high frequency signal RFin and the signal S1.

[0023] 2 is a schematic diagram showing an example of the relationship between the power of the high frequency signal of the power amplifier circuit of the first embodiment and the signal output by the detection circuit 22. In FIG. 2, the horizontal axis represents the power of the high frequency signal RFin, and the vertical axis represents the signal S2 output by the detection circuit 22.

[0024] The detection circuit 22 varies the rising point of the signal S2 according to the signal S1. Note that the rising point of this signal S2 may be referred to as a threshold value. The waveform 31 shows the relationship between the power of the high-frequency signal RFin and the signal S2 when the drive level of the carrier amplifier 13 is relatively low. The waveform 32 shows the relationship between the power of the high-frequency signal RFin and the signal S2 when the drive level of the carrier amplifier 13 is relatively intermediate. The waveform 33 shows the relationship between the power of the high-frequency signal RFin and the signal S2 when the drive level of the carrier amplifier 13 is relatively high.

[0025] When the drive level of the carrier amplifier 13 is relatively low, as shown in the waveform 31, the detection circuit 22 starts the signal S2 when the power of the high-frequency signal RFin reaches the value A. In the range where the power of the high-frequency signal RFin is equal to or greater than the value A, the detection circuit 22 increases the signal S2 as the power of the high-frequency signal RFin increases.

[0026] When the drive level of the carrier amplifier 13 is relatively intermediate, as shown in the waveform 32, the detection circuit 22 starts the signal S2 when the power of the high-frequency signal RFin reaches the value B (B < A). In the range where the power of the high-frequency signal RFin is equal to or greater than the value B, the detection circuit 22 increases the signal S2 as the power of the high-frequency signal RFin increases.

[0027] When the drive level of the carrier amplifier 13 is relatively high, as shown in the waveform 33, the detection circuit 22 starts the signal S2 when the power of the high-frequency signal RFin reaches the value C (C < B). In the range where the power of the high-frequency signal RFin is equal to or greater than the value C, the detection circuit 22 increases the signal S2 as the high-frequency signal RFin increases.

[0028] When a high-frequency signal RFin with a large power, which is the main cause for the carrier amplifiers 12 and 13 to saturate, is input, the detection circuit 22 outputs the signal S2 to the bias circuits 18 and 19, thereby activating the peak amplifiers 16 and 17 in the bias circuits 18 and 19. As a result, the carrier amplifiers 12 and 13 basically do not saturate.

[0029] What is important here is the response speed of the detection circuit 22. The detection circuit 22 detects the high frequency signal RFin, and therefore can respond much faster than the conventional technology for detecting saturation of the carrier amplifier. Therefore, even if the power of the high frequency signal RFin rises in a short period of time, the detection circuit 22 responds immediately and causes the bias circuits 18 and 19 to start up the peak amplifiers 16 and 17, and the carrier amplifiers 12 and 13 are not saturated even momentarily.

[0030] On the other hand, when the temperature or other surrounding environment changes (for example, when the gain of the carrier amplifiers 12 and 13 increases at extremely low temperatures), the carrier amplifiers 12 and 13 may become saturated even if the power of the high frequency signal RFin is small. In order to deal with such cases, the detection circuit 22 detects the signal S1 indicating the drive level of the carrier amplifiers 12 and 13, and when the carrier amplifiers 12 and 13 are close to saturation, immediately starts the peak amplifiers 16 and 17 even if the power of the high frequency signal RFin is small.

[0031] Since the detection circuit 22 detects the high frequency signal RFin, even if it takes time to detect the drive levels of the carrier amplifiers 12 and 13, it is possible to cause the bias circuits 18 and 19 to activate the peak amplifiers 16 and 17 without saturating the carrier amplifiers 12 and 13. This allows the Doherty amplifier circuit 10 to suppress deterioration in the quality of the high frequency signal RFout.

[0032] It can also be considered that the detection circuit 22 operates in a feedforward manner in response to the high frequency signal RFin and operates in a feedback manner in response to the signal S1. Note that in this embodiment, the signal S2 for controlling the bias circuit 18 and the bias circuit 19 is output to each of the bias circuit 18 and the bias circuit 19, but in the present disclosure, the signal S2 may be output to only one of the bias circuit 18 and the bias circuit 19.

[0033] (One Example of a Detection Circuit and a Drive Level Detection Circuit) Fig. 3 is a diagram showing a specific example of the detection circuit and the drive level detection circuit of the power amplifier circuit of the first embodiment. Fig. 3 also shows circuit elements for applying a bias to the detection circuit 22. The low-pass filter 25A and the bias circuits 18 and 19 shown in Fig. 3 may be omitted. The low-pass filter 25A can be omitted when a good differential signal can be obtained. The bias circuits 18 and 19 can be omitted when the transistor to which the bias is supplied (the amplification transistor) is small.

[0034] The detector circuit 22 includes a transistor Q DE1 and Q DE2 and resistor R DEE1 and R DEE2 Including,

[0035] In the present disclosure, each transistor is a bipolar transistor, but the present disclosure is not limited thereto. An example of a bipolar transistor is a heterojunction bipolar transistor (HBT), but the present disclosure is not limited thereto. The transistor may be, for example, a field effect transistor (FET). The transistor may be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. A unit transistor refers to the minimum configuration that constitutes a transistor.

[0036] Transistor Q DE1 The collector of the transistor Q is electrically connected to the power supply potential Vcc. DE1 The emitter of is connected to resistor R DEE1 That is, the transistor Q DE1 and resistor R DEE1 Transistor Q is connected as an emitter follower. DE1 and resistor R DEE1 constitutes a first emitter follower circuit 22a.

[0037] The detection circuit 22 may include a source follower circuit instead of the first emitter follower circuit 22a.

[0038] Transistor Q DE2 The collector of the transistor Q is electrically connected to the power supply potential Vcc. DE2 The emitter of is connected to resistor R DEE2 That is, the transistor Q DE2 and resistor R DEE2 Transistor Q is connected as an emitter follower. DE2 and resistor R DEE2 constitutes the second emitter follower circuit 22b.

[0039] The detection circuit 22 may include a source follower circuit instead of the second emitter follower circuit 22b.

[0040] Resistance R DEE1 and the other end of resistor R DEE2 The other end of the first emitter follower circuit 22a is electrically connected to the other end of the second emitter follower circuit 22b. The sum of the output current of the first emitter follower circuit 22a and the output current of the second emitter follower circuit 22b is the output current I1 of the detection circuit 22.

[0041] Resistance R DEBB , R DEB1 and R DEB2 , and transistor Q DE5 , Q DE6 and Q DE7 is the transistor Q DE1 and Q DE2 A bias voltage is applied to the base of the transistor.

[0042] Resistance R DEBB One end of resistor R DEB1 One end of resistor R DEB2 The one end of the first electrode is electrically connected to the other end of the second electrode.

[0043] Resistance R DEBB The other end of the transistor Q DE7 That is, the collector and base of the transistor Q DE7is diode connected. Transistor Q DE7 The emitter of the transistor Q DE6 That is, the collector and base of the transistor Q DE6 is diode connected. Transistor Q DE6 The emitter of the transistor Q DE5 That is, the collector and base of the transistor Q DE5 is diode connected. Transistor Q DE5 The emitter of each of the first and second transistors is electrically connected to a reference potential GND. The reference potential GND is exemplified by a ground potential, but the present disclosure is not limited thereto.

[0044] Resistance R DEBB One end of resistor R DEB1 One end of resistor R DEB2 One end of the bias current BIAS 1 is input. Resistor R DEBB , transistor Q DE7 , transistor Q DE6 and transistor Q DE5 This voltage is generated by resistor R DEB1 Through the transistor Q DE1 and resistor R DEB2 Through the transistor Q DE2 is entered into the base.

[0045] Transistor Q DE3 and Q DE4 Each of the transistors Q DE5 Transistor Q is connected in a current mirror. DE3 The collector of the transistor Q DE1 This electrically connects the transistor Q DE3 is the transistor Q DE1 The base current of the transistor Q can be adjusted. DE4 The collector of the transistor Q DE2 This electrically connects the transistor Q DE4 is the transistor QDE2 The base current of the transistor is adjustable.

[0046] Transistor Q DE1 The base of transistor Q DE2 The base of the RF signal is the RF signal IN, which is converted into a differential signal from the RF signal RFin. 1 and IN 2 are input. High frequency signal IN 1 and IN 2 can be obtained, for example, by inputting a high-frequency signal RFin to a balun.

[0047] Resistance R DEE1 The other end of resistor R DEE2 The other end of the constant current circuit 24 is electrically connected to the constant current circuit 24. DE11 The constant current circuit 24 is a current bias circuit for the detection circuit 22.

[0048] The drive level detection circuit 26 includes a resistor R MO1 , R MO2 , R MO3 , R MO4 and R MO5 and transistor Q MO1 , Q MO2 , Q MO4 , Q MO5 , Q MO6 and Q MO7 and capacitor C MO1 Including,

[0049] In this description, the carrier amplifier 13 (see FIG. 1) is assumed to be a pair of differential amplifiers, and to output high frequency signals RF71 and RF72 that constitute a pair of differential signals.

[0050] Transistor Q MO1 A high frequency signal RF71 is input to the emitter of the transistor Q MO1 The emitter of the transistor 11 is electrically connected to the output terminal (collector or drain of the output transistor) of one of the amplifiers in the carrier amplifier 13, for example.

[0051] Transistor Q MO2 A high frequency signal RF72 is input to the emitter of the transistor Q MO2 The emitter of the second amplifier is electrically connected to the output terminal (collector or drain of the output transistor) of the other amplifier in the carrier amplifier 13, for example.

[0052] Transistor Q MO1 The base of transistor Q MO2 The base of the transistor Q is electrically connected to the node N3. MO1 The collector of the transistor Q MO2 The collector of is electrically connected to a node N4.

[0053] Resistance R MO1 , R MO2 and R MO3 , and transistor Q MO4 applies a voltage to node N3. That is, resistor R MO1 , R MO2 and R MO3 , and transistor Q MO4 is the transistor Q MO1 The base of transistor Q MO2 Provides a bias to the base.

[0054] Resistance R MO3 One end of the resistor R is electrically connected to the power supply potential Vcc. MO3 The other end of the transistor Q MO4 Collector and resistor R MO1 One end of the resistor R MO1 The other end of the transistor Q MO4 Base and resistor R MO2 One end of the transistor Q is electrically connected to the other end of the transistor Q. MO4 The emitter and resistor R MO2 The other end of the resistor R is electrically connected to the reference potential GND. MO1 and R MO2、 And transistor Q MO4 produces a constant voltage. This voltage becomes the voltage at node N3.

[0055] Resistance R MO4 and R MO5 , and transistor Q MO6 and Q MO7 applies a voltage to node N4. That is, resistor R MO4 and R MO5 , and transistor Q MO6 and Q MO7 is the transistor Q MO1 The collector of the transistor Q MO2 A bias is applied to the collector of the

[0056] Resistance R MO5 One end of the resistor R is electrically connected to the power supply potential Vcc. MO5 The other end of the transistor Q MO6 That is, the collector and base of the transistor Q MO6 is diode connected. Transistor Q MO6 The emitter of the transistor Q MO7 That is, the collector and base of the transistor Q MO7 is diode connected. Transistor Q MO7 The emitter of the resistor R is electrically connected to the reference potential GND. MO4 One end of the resistor R MO5 The other end of the transistor Q MO6 The collector and base of the transistor are electrically connected to the resistor R MO4 The other end of the transistor Q is electrically connected to the node N4. MO6 and Q MO7 This voltage is generated by resistor R MO4 This voltage becomes the voltage of node N4 via

[0057] Transistor Q MO5 The collector and base of the transistor Q are electrically connected to the node N4. MO5 is diode connected. Transistor Q MO5 The emitter of is connected to the capacitor C MO1The capacitor C is electrically connected to one end of the MO1 The other end is electrically connected to the reference potential GND.

[0058] Transistor Q MO5 In other words, in this embodiment, the transistor Q MO5 The emitter voltage of the capacitor C corresponds to the signal S1. MO1 shunts and smoothes high frequency components of signal S1.

[0059] Resistance R MO1 , R MO2 and R MO3 , and transistor Q MO4 It is sufficient to output a roughly constant voltage, and can be thought of as a constant voltage source. MO5 , and transistor Q MO6 and Q MO7 The transistor Q can be thought of as a constant voltage source since it only needs to output a roughly constant voltage. MO5 It is sufficient for the voltage drop to be approximately constant, and it can be thought of as being replaced by a constant voltage source.

[0060] The low-pass filter 25B is connected to a resistor R LPF and capacitor C LPF Including,

[0061] Resistance R LPF One end of the transistor Q MO5 It is electrically connected to the emitter of resistor R LPF The other end of the capacitor C LPF It is electrically connected to one end of the capacitor C. LPF The other end is electrically connected to the reference potential GND.

[0062] Resistance R LPF The other end of and capacitor C LPF One end of the transistor Q DE11 The low-pass filter 25B is electrically connected to the base of the transistor QDE11 Output to the base of.

[0063] The low-pass filter 25A is connected to the capacitor C env Includes capacitor C env One end of the resistor R DEE1 The other end of resistor R DEE2 and the other end of transistor Q DE11 It is electrically connected to the collector of the capacitor C env The other end is electrically connected to the reference potential GND.

[0064] Capacitor C env is the output current I1 of the detector circuit 22 and the DE11 The difference between the collector current I2 of the capacitor C and the collector current I3 of the capacitor C is used to charge or discharge the capacitor. env The voltage of the capacitor C is the signal S2. env The capacitor C env This allows the bias circuits 18 and 19 in the subsequent stages and the transistors to which the bias is supplied (amplification transistors) to be appropriately biased.

[0065] The bias circuit 18 is connected to the transistor Q DE8 , Q DE9 and Q DE10 Incidentally, the circuit configuration of the bias circuit 19 (see FIG. 1) is similar to that of the bias circuit 18, and therefore a description thereof will be omitted.

[0066] Transistor Q DE9 is diode connected. Transistor Q DE9 The collector and base of the capacitor C env One end of the transistor Q is electrically connected to the other end of the transistor Q. DE9 The emitter of the transistor Q DE8 The collector and base of the transistor Q are electrically connected to each other. DE8 is diode connected. Transistor Q DE8The emitter of the transistor Q is electrically connected to the reference potential GND. DE9 and Q DE8 The capacitor C env A current flows according to the voltage.

[0067] Transistor Q DE10 The collector of the transistor Q is electrically connected to the power supply potential Vcc. DE10 The base of the transistor Q DE9 The collector and base of the transistor Q are electrically connected to each other. DE10 The emitter voltage of 16 (BIAS 17 ) and is output to the peak amplifier 16 (17).

[0068] 4 is a diagram showing an equivalent circuit of a specific example of the detection circuit and the drive level detection circuit of the power amplifier circuit according to the fifth embodiment. MO1 is the resistance R in Figure 3. MO1 , R MO2 and R MO3 , and transistor Q MO4 This corresponds to the constant voltage source V in Figure 4. MO2 is the resistance R in Figure 3. MO5 , and transistor Q MO6 and Q MO7 This corresponds to the constant voltage source V in Figure 4. MO3 is the transistor Q in Figure 3. MO5 is equivalent to.

[0069] (Drive level detection circuit operation) The operation of the drive level detection circuit 26 will be described with reference to the equivalent circuit of FIG.

[0070] In general, the output terminal voltage of the final-stage carrier amplifier 13 oscillates with the voltage amplitude of the high-frequency signal centered on the bias voltage. When the final-stage carrier amplifier 13 saturates, a situation occurs in which the voltage amplitude of the high-frequency signal increases and becomes almost equal to the bias voltage. In this situation, there occurs a moment in the oscillation period of the high-frequency signal when the output terminal voltage approaches 0V. This moment is a moment when no amplification effect is obtained, which leads to a phenomenon called amplifier saturation.

[0071] The circuit of this embodiment detects the drive level of the carrier amplifier 13 by utilizing this principle of saturation.

[0072] Specifically, within the period of the high frequency signals RF71 and RF72, the voltages of the high frequency signals RF71 and RF72 are MO1 From the voltage of transistor Q MO1 and Q MO2 The voltage of transistor Q MO1 and Q MO2 is turned on.

[0073] When the carrier amplifier 13 is operating with a sufficient margin against saturation, the transistor Q MO1 and Q MO2 Since there is no period when the transistor is in the on state, no collector current flows. MO4 Since no current flows, no voltage drop occurs. Therefore, the signal S1 is MO2 from the voltage of the constant voltage source V MO3 The voltage is the voltage obtained by subtracting the voltage of

[0074] On the other hand, when the amplitude of the high frequency signals RF71 and RF72 increases, the transistor Q MO1 and Q MO2 Since there is a period when the transistor is in the on state, collector current flows. MO4 Since current flows, a voltage drop occurs.

[0075] When the amplitude of the high frequency signals RF71 and RF72 becomes larger, the transistor Q MO1 and Q MO2 Since the on-state period is longer, more collector current flows. Therefore, the resistor R MO4 will have a larger voltage drop because more current will flow.

[0076] Therefore, as the drive level of the carrier amplifier 13 becomes higher, the signal S1 changes from the voltage when the high frequency signals RF71 and RF72 are small signals to the voltage when the high frequency signals RF71 and RF72 are small signals. MO4 The voltage drops by the amount of the voltage drop at

[0077] Next, the operation of the detection circuit 22 will be described.

[0078] Transistor Q DE1 is the high frequency signal IN 1 is transistor Q DE1 When the threshold voltage of transistor Q is equal to or higher than the threshold voltage of transistor Q, the transistor Q turns on and outputs an emitter current. DE2 is the high frequency signal IN 2 is transistor Q DE2 When the threshold voltage is equal to or higher than the threshold voltage, the transistor is turned on and outputs an emitter current.

[0079] In other words, the high-frequency signal IN 1 and IN 2 The larger the amplitude of the high frequency signal IN (the greater the power of the high frequency signal RFin), the larger the output current of the detection circuit 22. 1 and IN 2 The smaller the amplitude of the high frequency signal RFin (the smaller the power of the high frequency signal RFin), the smaller the output current of the detection circuit 22 becomes.

[0080] On the other hand, as described above, when the drive level of the carrier amplifier 13 is relatively high (close to saturation), the signal S1 becomes a relatively low voltage, and when the drive level of the carrier amplifier 13 is relatively low (when the amplification factor is reduced), the signal S1 becomes a relatively high voltage.

[0081] In other words, the higher the drive level of the carrier amplifier 13 is (the closer to saturation), the DE11 The collector current I2 of the transistor Q becomes smaller. Also, the lower the drive level of the carrier amplifier 13 is (the lower the amplification factor is), the smaller the collector current I2 of the transistor Q DE11 The collector current I2 becomes larger.

[0082] To summarize the above, capacitor C env The voltage of the capacitor C tends to become higher as the drive level of the carrier amplifier 13 becomes relatively higher (closer to saturation). env The voltage of the capacitor C is less likely to become high as the drive level of the carrier amplifier 13 becomes relatively low (the amplification factor is reduced). env The voltage of the capacitor C env The lower the power of the high frequency signal RFin, the less likely the voltage of becomes high.

[0083] 5 is a diagram showing an example of the relationship between the power of the high frequency signal in the power amplifier circuit of the first embodiment and the bias voltage applied to the peak amplifier. In FIG. 5, the horizontal axis represents the power of the high frequency signal RFin, and the vertical axis represents the bias voltage BIAS applied from the bias circuit 18 (19) to the peak amplifier 16 (17). 16 (BIAS 17 )

[0084] Waveform 34 shows the bias voltage BIAS when the drive level of the carrier amplifier 13 is relatively low. 16 (BIAS 17 ) when the drive level of the carrier amplifier 13 is relatively intermediate. 16 (BIAS 17 A waveform 36 shows the change in the bias voltage BIAS when the drive level of the carrier amplifier 13 is relatively high. 16 (BIAS 17 ) changes.

[0085] As shown in waveform 36, when the drive level of the carrier amplifier 13 is relatively high, the detection circuit 22 can start up the peak amplifiers 16 and 17 even if the power of the high frequency signal RFin is low. Conversely, as shown in waveform 34, when the drive level of the carrier amplifier 13 is relatively low, the detection circuit 22 can delay the start-up of the peak amplifiers 16 and 17 until the power of the high frequency signal RFin becomes high.

[0086] Therefore, when the drive level of the carrier amplifier 13 is relatively high (close to saturation), the current of the constant current circuit 24 should be reduced so that the peak amplifiers 16 and 17 can be started up even if the power of the high frequency signal RFin is low. Conversely, when the drive level of the carrier amplifier 13 is relatively low, it is not necessary to start up the peak amplifiers 16 and 17 until the power of the high frequency signal RFin becomes large, so the current of the constant current circuit 24 should be increased. In other words, the voltage BIAS input to the constant current circuit 24 2 is set to a voltage that changes complementarily to the drive level of the carrier amplifier 13, the intended operation can be achieved for the entire circuit.

[0087] The response of the detector circuit 22 is faster for the following reasons.

[0088] First, the first emitter follower circuit 22a and the second emitter follower circuit 22b operate differentially. Therefore, the capacitance C env This allows the capacitance of the capacitor C env Since the delay in the detection circuit 22 can be reduced, the change in the signal S2 becomes faster, that is, the response of the detection circuit 22 becomes faster.

[0089] Secondly, the emitter follower circuit is a circuit that can output a large current. Therefore, each of the first emitter follower circuit 22a and the second emitter follower circuit 22b can output a large current. In other words, the detection circuit 22 can output a large output current I1. As a result, the detection circuit 22 can output a large current I2 by using the capacitor C envThat is, the rising response of the detection circuit 22 becomes faster.

[0090] Third, the transistor Q DE11 is a constant current (collector current I2) that flows through the capacitor C env Therefore, the transistor Q DE11 is the capacitor C env That is, the falling edge response of the detection circuit 22 becomes faster.

[0091] Fig. 6 is a diagram showing a circuit configuration of a Doherty circuit in a power amplifier device according to the first embodiment. Next, the Doherty amplifier circuit 10 in the first embodiment will be described in detail. As shown in Fig. 6, the Doherty amplifier circuit 10 of the power amplifier device 100 includes two splitters 30A and 30B, a pair of differential amplifiers 13a and 13b, a pair of differential amplifiers 17a and 17b, a coupler 40 (a carrier balun 41 and a peak balun 51), an adjustment circuit 60, and a load (antenna) 70.

[0092] The splitter 30A splits the high frequency signal RF3 (see FIG. 1) output from the carrier amplifier 12 (see FIG. 1) and outputs the split signals to a pair of differential amplifiers 13a and 13b. The splitter 30B splits the high frequency signal R6 (see FIG. 1) output from the peak amplifier 16 (see FIG. 1) and outputs the split signals to a pair of differential amplifiers 17a and 17b.

[0093] The pair of differential amplifiers 13a, 13b constitute a carrier amplifier 13 (see FIG. 1). The pair of differential amplifiers 17a, 17b constitute a peak amplifier 17 (see FIG. 1). In the present disclosure, the type of the differential amplifier is not particularly limited, but may be, for example, a bipolar transistor such as a heterojunction bipolar transistor (HBT) or a field effect transistor such as a metal-oxide-semiconductor field effect transistor (MOSFET).

[0094] The coupler 40 has a carrier balun 41 and a peak balun 51. The carrier balun 41 has a primary carrier balun 42 and a secondary carrier balun 43 that is magnetically coupled to the primary carrier balun 42. Both ends of the primary carrier balun 42 are connected to a pair of differential amplifiers 13a and 13b. A power supply potential Vcc is supplied to a midpoint 42a of the primary carrier balun 42.

[0095] The peak balun 51 has a primary peak balun 52 and a secondary peak balun 53 that is magnetically coupled to the primary peak balun 52. Both ends of the primary peak balun 52 are connected to a pair of differential amplifiers 17a and 17b. A power supply potential Vcc is supplied to a midpoint 52a of the primary peak balun 52.

[0096] One end of the secondary peak balun 53 is connected to the reference potential GND. The other end of the secondary peak balun 53 is connected to one end of the secondary carrier balun 43. This connects the secondary carrier balun 43 and the secondary peak balun 53 in series.

[0097] The adjustment circuit 60 of the first embodiment has a capacitor 62. The capacitor 62 is an adjustment circuit component of the present embodiment, and corresponds to a surface mount component. The other end of the secondary carrier balun 43 is connected to a load (antenna) 70. The capacitor 62 has one end connected to one end of the secondary carrier balun 43 and the other end connected to the reference potential GND, and is connected in parallel with the secondary peak balun 53.

[0098] According to this embodiment, the phase of the high frequency signal RF7 (see FIG. 1) input from the primary side peak balun 52 to the secondary side peak balun 53 is delayed by 90° by the capacitor 62. Then, the high frequency signal RF7 is combined with the high frequency signal RF4 (see FIG. 1) input to the secondary side carrier balun 43. In addition, the combined high frequency signal RFout (see FIG. 1) is output as an electromagnetic wave from the load (antenna) 70. Next, the layout of the power amplifying device 100 of the first embodiment will be described.

[0099] Fig. 7 is a plan view of the surface of the substrate in the power amplifier device of the first embodiment. Fig. 8 is a diagram for explaining the layout of the second insulating layer in the power amplifier device of the first embodiment. Fig. 9 is a diagram for explaining the layout of the third insulating layer in the power amplifier device of the first embodiment.

[0100] 7, the power amplifier device 100 has a substrate 101. When viewed from above, the substrate 101 has a rectangular shape. In other words, a surface 102 of the substrate 101 has a rectangular shape. The surface 102 has a pair of short sides 102a and a pair of long sides 102b.

[0101] Hereinafter, in the planar direction parallel to the surface 102, a direction parallel to the short side 102a is referred to as a first planar direction X. A direction parallel to the first planar direction X and parallel to the long side 102b (a direction intersecting with the first planar direction X) is referred to as a second planar direction Y. Note that in the present disclosure, the first planar direction X and the second planar direction Y are not limited to being perpendicular to each other, and may intersect with each other.

[0102] An integrated circuit 90 is attached to a surface 102 of the substrate 101. The integrated circuit 90 is an HBT (Heterojunction Bipolar Transistor). The integrated circuit 90 also has the functions of the splitters 30A and 30B and the pair of differential amplifiers 13a, 13b, 17a, and 17b (see FIG. 6).

[0103] Hereinafter, the direction in which the integrated circuit 90 and the substrate 101 are arranged is referred to as the stacking direction. In addition, the direction in which the substrate 101 is arranged as viewed from the integrated circuit 90 is referred to as the first stacking direction, and the opposite direction to the first stacking direction is referred to as the second stacking direction.

[0104] 7 to 9, the substrate 101 is a multi-layer substrate and has a plurality of insulating layers arranged in a stacking direction. Hereinafter, three insulating layers arranged in order from the second stacking direction among the plurality of insulating layers will be referred to as a first insulating layer 110 (see FIG. 7), a second insulating layer 120 (see FIG. 8), and a third insulating layer 130 (see FIG. 9). In addition, the surface of the first insulating layer 110 in the second stacking direction constitutes a surface 102.

[0105] A conductive layer formed by patterning is provided on each insulating layer of the substrate 101. The electrodes, wiring, and baluns (carrier balun 41, peak balun 51) described below are composed of the conductive layers. In the drawings, the conductive layers are hatched to make it easier to understand the range of the conductive layers.

[0106] As shown in Fig. 7, a primary-side peak balun 52 is provided on the surface 102 (first insulating layer 110). As shown in Fig. 8, a primary-side carrier balun 42 and a secondary-side peak balun 53 are provided on the second insulating layer 120. As shown in Fig. 9, a secondary-side carrier balun 43 is provided on the third insulating layer 130. Each balun is formed in a C-shape when viewed from the stacking direction.

[0107] As shown in FIG. 7, electrodes 111, 112, 113, and 114 are provided on the surface 102 (first insulating layer 110) as a conductive layer. The electrodes 111, 112, 113, and 114 are arranged at intervals in the second planar direction Y. The electrodes 111, 112, 113, and 114 are arranged in a range overlapping with the integrated circuit 90 and are connected to an output terminal (not shown) of the integrated circuit 90. As a result, a signal output from the differential amplifier 13a (see FIG. 6) is input to the electrode 111. A signal output from the differential amplifier 13b (see FIG. 6) is input to the electrode 112. A signal output from the differential amplifier 17a (see FIG. 6) is input to the electrode 113. A signal output from the differential amplifier 17b (see FIG. 6) is input to the electrode 114.

[0108] The electrodes 113, 114 are connected to both ends of the primary-side peak balun 52. The electrodes 111, 112 are connected to one ends of wirings 117, 118 extending in the first planar direction X. Interlayer connection conductors 111a, 112a are provided at the other ends of the wirings 117, 118. As shown in FIG. 8, the interlayer connection conductors 111a, 112a extend to the second insulating layer 120 and are connected to both ends of the primary-side carrier balun 42. In each drawing, the interlayer connection conductors are shown as blanks (without hatching) to make them easier to see.

[0109] Moreover, a wiring 115 is provided on the surface 102 (first insulating layer 110). A power supply potential Vcc (not shown in FIG. 7, see FIG. 6) is applied to the wiring 115. The power supply potential Vcc applied to the wiring 115 may be an external voltage generated outside the substrate 101, and the present disclosure is not particularly limited thereto. The primary-side peak balun 52 is connected to the wiring 115 via a junction (midpoint 52a). The primary-side carrier balun 42 is connected to the wiring 115 via the junction (midpoint 42a) and the interlayer connection conductor 116a. As a result, the power supply potential Vcc is supplied to the primary-side peak balun 52 and the primary-side carrier balun 42.

[0110] As shown in FIG. 8, an interlayer connection conductor 127 is provided at one end 53a of the secondary peak balun 53. The interlayer connection conductor 127 extends to the fourth or lower insulating layer (not shown) and is connected to the reference potential GND. An interlayer connection conductor 131 is provided at the other end 53b of the secondary peak balun 53. As shown in FIG. 9, the interlayer connection conductor 131 extends to the third insulating layer 130 and is connected to one end 43a of the secondary carrier balun 43. From the above, the secondary peak balun 53 and the secondary carrier balun 43 are connected in series. The other end 43b of the secondary carrier balun 43 is connected to the load (antenna) 70, although not shown.

[0111] As shown in FIG. 7, electrodes 160, 161 are provided on the surface 102 (first insulating layer 110) at an interval in the first planar direction X. A capacitor 62 (see FIG. 6), which is a component for an adjustment circuit, is placed on the electrodes 160, 161 and soldered. Interlayer connection conductors 160a, 161a are provided on the electrodes 160, 161. As shown in FIG. 9, the interlayer connection conductor 160a extends to the second insulating layer 120 and is connected to the reference potential GND. The interlayer connection conductor 161a extends to the second insulating layer 120 and is connected to the other end 53b of the secondary peak balun 53. As a result, the capacitor 62 and the secondary peak balun 53 are connected in parallel.

[0112] 7 to 9, according to the first embodiment, when viewed from the stacking direction, each balun (carrier balun 41, peak balun 51) is disposed on one side in the first planar direction X1 with respect to the integrated circuit 90. Also, each balun (carrier balun 41, peak balun 51) is disposed spaced apart from each other in the second planar direction Y to prevent electromagnetic interference.

[0113] Fig. 10 is an enlarged view of a part of Fig. 7. As shown in Fig. 10, when viewed from the stacking direction, capacitor 62, which is one of the components for the adjustment circuit, is disposed between carrier balun 41 and peak balun 51. That is, in this embodiment, an area that was previously a dead space is utilized as a space for disposing capacitor 62. Therefore, it is no longer necessary to provide a separate space for disposing capacitor 62 on surface 102 of substrate 101, and power amplifier 100 is made smaller.

[0114] Additionally, the primary-side peak balun 52 and the electrodes 160 and 161 are spaced apart by a distance L1. This is to prevent the solder that joins the capacitor 62 to the electrodes 160 and 161 from connecting to the primary-side peak balun 52.

[0115] If the primary-side carrier balun 42 were to be placed on the surface 102 of the substrate 101, for the same reason, it would need to be placed in a direction away from the electrodes 160, 161 than the imaginary line L2 (the imaginary line whose distance from the electrodes 160, 161 is L1). In other words, if the primary-side carrier balun 42 and the primary-side peak balun 52 are placed on the surface 102 of the substrate 101, the distance between the primary-side carrier balun 42 and the primary-side peak balun 52 would be L3 at the smallest.

[0116] On the other hand, in this embodiment, the primary-side carrier balun 42 is not provided on the surface 102 (first insulating layer 110) of the substrate 101. That is, there is no possibility that the solder joining the capacitor 62 to the electrodes 160, 161 will be connected to the primary-side carrier balun 42. For this reason, the primary-side carrier balun 42 can be disposed closer to the primary-side peak balun 52, beyond the imaginary line L2.

[0117] Also, when viewed from the stacking direction, the carrier balun 41 overlaps with the electrode 161. That is, the interval between the carrier balun 41 and the peak balun 51 in this embodiment is smaller by a distance L4 than the interval L3 when both the primary-side carrier balun 42 and the primary-side peak balun 52 are arranged on the substrate 101. This makes it possible to reduce the size of the power amplifier 100.

[0118] The first embodiment has been described above. Next, a modified example in which a part of the first embodiment is modified will be described. Note that the following description will focus on the differences from the first embodiment.

[0119] (First Modification) Fig. 11 is a plan view showing the front surface of the substrate of the power amplifier device of the first modified example. As shown in Fig. 11, the power amplifier device 100A of the first modified example differs from the first embodiment in that not only the carrier balun 41 but also the peak balun 51 is provided in the insulating layer in the first lamination direction from the front surface 102. That is, in the first modified example, the primary-side peak balun 52 is provided in the second insulating layer 120, and the secondary-side peak balun 53 is provided in the third insulating layer 130.

[0120] As described above, even in the first modified example, the power amplifier device 100A can be miniaturized similarly to the first embodiment. Note that in the first modified example, the peak balun 51 does not overlap with the electrode 161 when viewed from the stacking direction, but in the present disclosure, the peak balun 51 may overlap with the electrode 161 like the carrier balun 41, which is preferable because it allows for further miniaturization.

[0121] Although the first embodiment and the first modified example have been described above, the present disclosure is not limited thereto. For example, in the first embodiment, an example in which one of the two baluns is provided on the surface 102 has been described, but the balun provided on the surface 102 is not limited to the peak balun 51 shown in the first embodiment, and may be the carrier balun 41.

[0122] Furthermore, the present disclosure may include, instead of the adjustment circuit 60 (capacitor 62), a λ / 4 transformer that delays the phase of the high-frequency signals output from the differential amplifiers 17a and 17b by 90°.

[0123] In addition, in the first embodiment, the adjustment circuit components (capacitor 62) are arranged in the dead space, but the present disclosure may be components other than the adjustment circuit components. In other words, there is no particular restriction as long as the components are surface-mounted components mounted on the surface 102. Below, an example in which surface-mounted components are arranged in the dead space will be described.

[0124] (Second Modification) Fig. 12 is a diagram showing a circuit configuration of a Doherty circuit of a power amplifier device of the second modified example. As shown in Fig. 12, the Doherty amplifier circuit 10 of a power amplifier device 100B of the second modified example differs from that of the first embodiment 1 in that it has an inductor 54. The inductor 54 is interposed between a power supply potential Vcc and a midpoint 52a of a primary-side peak balun 52. The inductor 54 is a surface-mounted component mounted on a surface 102 of a substrate 101. The layout will be described in detail below.

[0125] Fig. 13 is a plan view of the surface of the substrate in the power amplifier device of the second modification. Fig. 14 is a diagram for explaining the layout of the second insulating layer in the power amplifier device of the second modification. Fig. 15 is a diagram for explaining the layout of the third insulating layer in the power amplifier device of the second modification.

[0126] 13, the power amplifying device 100B of the second modification differs from the first embodiment in that a primary-side carrier balun 42 is provided on the surface 102 (first insulating layer 110) of the substrate 101. As shown in FIG. 14, the power amplifying device 100B of the second modification differs from the first embodiment in that a secondary-side carrier balun 43 is provided on the second insulating layer 120.

[0127] Also, when viewed from the stacking direction, the inductor 54 is disposed between the primary-side carrier balun 42 and the primary-side peak balun 52. The inductor 54 is soldered to the electrodes 171, 172. Note that the present embodiment differs from the first embodiment in that the primary-side carrier balun 42 and the primary-side peak balun 52 do not overlap with the electrodes 171, 172 to which the inductor 54 is joined, respectively.

[0128] Moreover, the capacitor 62 is disposed on one side in the first planar direction X with respect to the inductor 54. The capacitor 62 is soldered to the electrodes 163 and 164.

[0129] 14, one end 53a of the secondary peak balun 53 is connected to the reference potential GND by an interlayer connection conductor 140. The other end 53b of the secondary peak balun 53 is connected to one end 43a of the secondary carrier balun 43 via a wiring 141 extending in the second planar direction Y. In addition, the other end 43b of the secondary carrier balun 43 is connected to a load (antenna) 70, although not particularly shown.

[0130] As shown in FIG. 12, the second insulating layer 120 is provided with an electrode 142 disposed between the secondary-side carrier balun 43 and the secondary-side peak balun 53. The electrode 142 is connected to a power supply potential Vcc. The electrode 142 is provided with an interlayer connection conductor 143 extending to the third insulating layer 130 and the first insulating layer. As shown in FIG. 15, the interlayer connection conductor 143 is connected to one end of a wiring 144 provided in the third insulating layer 130. The other end of the wiring 144 is connected to an interlayer connection conductor 145 extending to the first insulating layer 110. As shown in FIG. 13, the interlayer connection conductor 145 is connected to an electrode 146 connected to the midpoint 42a of the primary-side carrier balun 42. As a result, the power supply potential Vcc is supplied to the midpoint 42a of the primary-side carrier balun 42.

[0131] As shown in FIG. 13, the interlayer connection conductor 143 is connected to an electrode 171 of the first insulating layer 110. The electrode 172 is provided with an interlayer connection conductor 172a. As shown in FIG. 15, the interlayer connection conductor 172a extends to the third insulating layer 130 and is connected to one end of the wiring 147. The other end of the wiring 147 is connected to the interlayer connection conductor 148. Also, as shown in FIG. 13, the interlayer connection conductor 148 extends to the first insulating layer 110 and is connected to an electrode 149 that is connected to the midpoint 52a of the primary-side peak balun 52. As a result, the power supply potential Vcc is supplied to the midpoint 52a of the primary-side peak balun 52.

[0132] As shown in Fig. 15, the third insulating layer 130 is provided with an electrode 165 connected to the reference potential GND. The electrode 165 is provided with an interlayer connection conductor 166. As shown in Fig. 13, the interlayer connection conductor 166 extends to the first insulating layer 110 and is connected to an electrode 164 joined to the capacitor 62. The electrode 163 is provided with an interlayer connection conductor 167. As shown in Fig. 14, the interlayer connection conductor 167 extends to the second insulating layer 120 and is connected to the wiring 141. Thus, the capacitor 62 and the secondary-side peak balun 53 are connected in parallel.

[0133] Fig. 16 is a schematic diagram of a cross section taken along line XVI-XVI in Fig. 15. As shown in Fig. 16, the inductor 54 is a winding centered on a center line (not shown) extending in the second planar direction Y. Therefore, the direction of the magnetic field passing through the inside of the inductor 54 (see arrow M1 in Fig. 16) is the second planar direction Y. On the other hand, as shown in Fig. 16, the direction of the magnetic field passing through the insides of the carrier balun 41 and the peak balun 51 (see arrow M2 in Fig. 16) is the lamination direction.

[0134] As described above, according to the third modification, the inductor 54 is disposed in an area that was previously a dead space, and the power amplifier 100B is miniaturized. As shown in Fig. 16, the magnetic fields of the carrier balun 41 and the peak balun 51 are perpendicular to the magnetic field of the inductor 54. Therefore, the carrier balun 41 and the peak balun 51 are unlikely to be magnetically coupled to the inductor 54. In addition, the magnetic field of the inductor 54 exerts a shielding effect, and the magnetic fields of the carrier balun 41 and the peak balun 51 are unlikely to interfere with each other.

[0135] In the third modified example, the carrier balun 41 (primary side carrier balun 42) and the peak balun 51 (primary side peak balun 52) are provided on the surface 102 of the substrate 101, but in the present disclosure, one of the carrier balun 41 (primary side carrier balun 42) and the peak balun 51 (primary side peak balun 52) may be provided on the surface 102 of the substrate 101. That is, one of the carrier balun 41 and the peak balun 51 may be provided on an insulating layer arranged in the first stacking direction from the first insulating layer 110 constituting the surface 102. Furthermore, the other of the carrier balun 41 and the peak balun 52 may also be provided on an insulating layer arranged in the first stacking direction from the first insulating layer 110 constituting the surface 102. That is, both the carrier balun 41 and the peak balun 51 may not be provided on the first insulating layer 110, but may be provided on an insulating layer below the second insulating layer 120.

[0136] The present disclosure may also be implemented in the following combinations: (1) a substrate having a surface; an integrated circuit provided on the surface, the integrated circuit having a carrier amplifier and a peak amplifier; A carrier balun connected to the carrier amplifier; A peak balun connected to the peak amplifier; A surface mount component provided on the surface; Equipped with the carrier amplifier and the peak amplifier are each a pair of differential amplifiers, a direction in which the integrated circuit and the substrate are arranged is defined as a lamination direction; a first stacking direction in which the substrate is disposed as viewed from the integrated circuit; A direction parallel to the surface is defined as a first plane direction, a second planar direction is a direction parallel to the surface and intersects with the first planar direction; the substrate has a plurality of insulating layers arranged in the stacking direction, The surface is provided with electrodes to which the surface mount components are soldered; When viewed from the stacking direction, the carrier balun, the electrode, and the peak balun are arranged in order in the second planar direction on one side of the first planar direction of the integrated circuit, One of the carrier balun and the peak balun is provided on the insulating layer disposed in the first stacking direction further than the insulating layer constituting the surface, and at least a portion of the insulating layer overlaps with the electrode when viewed from the stacking direction. Power amplifier. (2) a substrate having a surface; an integrated circuit provided on the surface, the integrated circuit having a carrier amplifier and a peak amplifier; A carrier balun connected to the carrier amplifier; A peak balun connected to the peak amplifier; an inductor that is a surface mount component provided on the surface; Equipped with the carrier amplifier and the peak amplifier are each a pair of differential amplifiers, a direction in which the integrated circuit and the substrate are arranged is defined as a lamination direction; a first stacking direction in which the substrate is disposed as viewed from the integrated circuit; A direction parallel to the surface is defined as a first plane direction, a second planar direction is a direction parallel to the surface and intersects with the first planar direction; the substrate has a plurality of insulating layers arranged in the stacking direction, the carrier balun includes a primary carrier balun and a secondary carrier balun, each of which has a center line of a winding extending in the lamination direction; one of the primary carrier balun and the secondary carrier balun is provided on the surface, and the other is provided on the insulating layer disposed in the first stacking direction further than the insulating layer constituting the surface, the peak balun includes a primary peak balun and a secondary peak balun, each of which has a center line of a winding extending in the lamination direction; one of the primary-side peak balun and the secondary-side peak balun is provided on the surface, and the other is provided on the insulating layer disposed in the first stacking direction relative to the insulating layer constituting the surface, When viewed from the stacking direction, the carrier balun, the inductor, and the peak balun are arranged in order in the second planar direction on one side of the first planar direction of the integrated circuit, A center line of the inductor winding extends in the second plane direction. Power amplifier. (3) a substrate having a surface; an integrated circuit provided on the surface, the integrated circuit having a carrier amplifier and a peak amplifier; A carrier balun connected to the carrier amplifier; A peak balun connected to the peak amplifier; an inductor that is a surface mount component provided on the surface; Equipped with the carrier amplifier and the peak amplifier are each a pair of differential amplifiers, a direction in which the integrated circuit and the substrate are arranged is defined as a lamination direction; a first stacking direction in which the substrate is disposed as viewed from the integrated circuit; A direction parallel to the surface is defined as a first plane direction, a second planar direction is a direction parallel to the surface and intersects with the first planar direction; the substrate has a plurality of insulating layers arranged in the stacking direction, When viewed from the stacking direction, the carrier balun, the inductor, and the peak balun are arranged in order in the second planar direction on one side of the first planar direction of the integrated circuit, the carrier baluns each have a center line of a winding extending in the lamination direction, and include a primary carrier balun and a secondary carrier balun provided on different insulating layers, the peak balun includes a primary peak balun and a secondary peak balun, each of which has a center line of a winding extending in the lamination direction and is provided on a different insulating layer, one of the carrier balun and the peak balun is provided on the insulating layer disposed in the first stacking direction further than the insulating layer constituting the surface, A center line of the inductor winding extends in the second plane direction. Power amplifier. (4) The other of the carrier balun and the peak balun is provided on the insulating layer disposed in the first stacking direction further than the insulating layer constituting the surface. A power amplifier device according to (1). (5) The power amplifier according to (1) or (4), wherein the surface mount components are components for an adjustment circuit. (6) The power amplifier according to (5), wherein the adjustment circuit component is a capacitor. (7) The power amplifier device according to (3), wherein the other of the carrier balun and the peak balun is provided on the insulating layer arranged in the first stacking direction further than the insulating layer constituting the surface. [Explanation of symbols]

[0137] 1 Power amplifier circuit 10 Doherty amplifier 12, 13 Carrier amplifier 13a, 13b, 17a, 17b Differential Amplifiers 16, 17 Peak amplifier 21 Control circuit 22 Detector circuit 26 Drive level detection circuit 40 Combiner 41 Carrier Balun 42 Primary side carrier balun 43 Balun for secondary carrier 51 Peak Balun 52 Primary peak balun 53 Secondary peak balun 54 Inductor 60 Adjustment circuit 62 Capacitor 100, 100A, 100B Power Amplifier 101 Substrate 102 Surface 110 First insulating layer 120 Second insulating layer 130 Third insulating layer 160, 161 electrode

Claims

1. a substrate having a surface; an integrated circuit provided on the surface, the integrated circuit having a carrier amplifier and a peak amplifier; A carrier balun connected to the carrier amplifier; A peak balun connected to the peak amplifier; A surface mount component provided on the surface; Equipped with the carrier amplifier and the peak amplifier are each a pair of differential amplifiers, a direction in which the integrated circuit and the substrate are arranged is defined as a lamination direction; a first stacking direction in which the substrate is disposed as viewed from the integrated circuit; A direction parallel to the surface is defined as a first plane direction, a second planar direction is a direction parallel to the surface and intersects with the first planar direction; the substrate has a plurality of insulating layers arranged in the stacking direction, The surface is provided with electrodes to which the surface mount components are soldered; the carrier balun, the electrode, and the peak balun are arranged in order in the second planar direction on one side of the first planar direction of the integrated circuit when viewed from the stacking direction, One of the carrier balun and the peak balun is provided on the insulating layer disposed in the first stacking direction relative to the insulating layer constituting the surface, and at least a portion of the insulating layer overlaps with the electrode when viewed from the stacking direction. Power amplifier.

2. a substrate having a surface; an integrated circuit provided on the surface, the integrated circuit having a carrier amplifier and a peak amplifier; A carrier balun connected to the carrier amplifier; A peak balun connected to the peak amplifier; an inductor that is a surface mount component provided on the surface; Equipped with the carrier amplifier and the peak amplifier are each a pair of differential amplifiers, a direction in which the integrated circuit and the substrate are arranged is defined as a lamination direction; a first stacking direction in which the substrate is disposed as viewed from the integrated circuit; A direction parallel to the surface is defined as a first plane direction, a second planar direction is a direction parallel to the surface and intersects with the first planar direction; the substrate has a plurality of insulating layers arranged in the stacking direction, the carrier balun includes a primary carrier balun and a secondary carrier balun, each of which has a center line of a winding extending in the lamination direction; one of the primary carrier balun and the secondary carrier balun is provided on the surface, and the other is provided on the insulating layer disposed in the first stacking direction relative to the insulating layer constituting the surface, the peak balun includes a primary peak balun and a secondary peak balun, each of which has a center line of a winding extending in the lamination direction; one of the primary-side peak balun and the secondary-side peak balun is provided on the surface, and the other is provided on the insulating layer disposed in the first stacking direction relative to the insulating layer constituting the surface, the carrier balun, the inductor, and the peak balun are arranged in order in the second planar direction on one side of the first planar direction of the integrated circuit when viewed from the stacking direction, A centerline of the inductor winding extends in the second plane direction. Power amplifier.

3. a substrate having a surface; an integrated circuit provided on the surface, the integrated circuit having a carrier amplifier and a peak amplifier; A carrier balun connected to the carrier amplifier; A peak balun connected to the peak amplifier; an inductor that is a surface mount component provided on the surface; Equipped with the carrier amplifier and the peak amplifier are each a pair of differential amplifiers, a direction in which the integrated circuit and the substrate are arranged is defined as a lamination direction; a first stacking direction in which the substrate is disposed as viewed from the integrated circuit; A direction parallel to the surface is defined as a first plane direction, a second planar direction is a direction parallel to the surface and intersects with the first planar direction; the substrate has a plurality of insulating layers arranged in the stacking direction, the carrier balun, the inductor, and the peak balun are arranged in order in the second planar direction on one side of the first planar direction of the integrated circuit when viewed from the stacking direction, the carrier baluns each have a center line of a winding extending in the lamination direction, and include a primary carrier balun and a secondary carrier balun provided on different insulating layers, the peak balun includes a primary peak balun and a secondary peak balun, each of which has a center line of a winding extending in the lamination direction and is provided on a different insulating layer, one of the carrier balun and the peak balun is provided on the insulating layer disposed in the first stacking direction further than the insulating layer constituting the surface, A centerline of the inductor winding extends in the second plane direction. Power amplifier.

4. The other of the carrier balun and the peak balun is provided on the insulating layer disposed in the first stacking direction further than the insulating layer constituting the surface.

2. The power amplifier according to claim 1.

5. 5. The power amplifier according to claim 1, wherein the surface mount components are components for an adjustment circuit.

6. 6. The power amplifier according to claim 5, wherein the adjustment circuit component is a capacitor.

7. The other of the carrier balun and the peak balun is provided on the insulating layer disposed in the first stacking direction further than the insulating layer constituting the surface.

4. The power amplifier according to claim 3.

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