Active transistor random number generator (RNG) circuit with MEMS entropy
Patent Information
- Application Number
- JP2024120829
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-05-10
- Filing Date
- 2024-07-26
- Publication Date
- 2025-02-14
Smart Images
Figure 2025022795000001_ABST
Abstract
Description
[Technical field]
[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Application No. 63 / 516,949, entitled “DUAL USE MICROELECTROMECHANICAL SYSTEM (MEMS) DEVICE,” filed August 1, 2023, the contents of which are incorporated by reference in their entirety herein.
[0002] This application is related to U.S. application Ser. No. 18 / 661,373 (Attorney Docket No. H232672-US2), entitled "DUAL USE MICROELECTROMECHANICAL SYSTEM (MEMS) DEVICE," filed on the same day as this application, U.S. application Ser. No. 18 / 661,400 (Attorney Docket No. H233692-US), entitled "CODEPENDENT PHYSICAL UNCLONABLE FUNCTION / RANDOM NUMBER GENERATOR PAIRING FOR PHYSICAL PROVENANCE," filed on the same day as this application, U.S. application Ser. No. 18 / 661,416 (Attorney Docket No. H233693-US), entitled "MEMS BASED PUF FOR MECHANICAL TRUST EXTENSION," filed on the same day as this application, and U.S. application Ser. No. 18 / 661,420 (Attorney Docket No. H233692-US), entitled "ACTIVE TRANSISTOR PHYSICAL UNCLONABLE FUNCTION (PUF) CIRCUIT WITH MEMS No. 18 / 661,426 (Attorney Docket No. H233694-US), entitled "METHOD UNIQUENESS," all of which are incorporated herein by reference in their entireties. [Background technology]
[0003] Systems that can provide high quality sources of randomness are needed in cryptography. The random sources in these systems are ideally low power, small, and provide high quality randomness. Random numbers are used to improve the security of cryptographic network operations by ensuring that communication sessions are non-repetitive and unpredictable. Summary of the Invention
[0004] In some aspects, a random number generator (RNG) circuit is described herein. The RNG circuit includes one or more microelectromechanical (MEMS) structures configured to provide an output, the output including an active oscillation, a charge, a resistance, a capacitance, and / or an inductance value. The RNG circuit further includes active transistor RNG circuitry communicatively coupled to the one or more MEMS structures. The active transistor RNG circuitry is configured to generate a random number output based on the output provided by the one or more MEMS structures. The random number output generated by the active transistor RNG circuitry is an output of the RNG circuit.
[0005] In some aspects, a device is described herein. The device includes a random number generator (RNG) circuit. The RNG circuit includes a microelectromechanical (MEMS) structure configured to output an active oscillation, a charge, a resistance, a capacitance, and / or an inductance value. The RNG circuit further includes active transistor RNG circuitry communicatively coupled to the MEMS structure. The active transistor RNG circuitry is configured to generate a random number output of the RNG circuit based on the active oscillation, the charge, the resistance, the inductance, and / or the capacitance value output by the one or more MEMS structures. The device further includes one or more additional circuits configured to utilize the random number output for one or more cryptographic processes.
[0006] In some aspects, a system is described herein. The system includes a plurality of devices configured to communicate with each other over a network. Each device of the plurality of devices includes a random number generator (RNG) circuit. The RNG circuit includes a microelectromechanical (MEMS) structure configured to provide an output, the output including an active oscillation, a charge, a resistance, a capacitance, and / or an inductance value. The active transistor RNG circuitry is configured to generate a random number output for the RNG circuit based on the output by the MEMS structure. Each device of the plurality of devices further includes one or more additional circuits configured to utilize the random number output for one or more cryptographic processes when communicating with other devices over the network. [Brief description of the drawings]
[0007] Example embodiments will be described with additional specificity and detail using the accompanying drawings, with the understanding that the drawings illustrate example embodiments only and should not be considered limiting in scope. [Figure 1A] FIG. 1 is a block diagram of an exemplary random number generator (RNG) circuit including a MEMS structure(s) and active transistor RNG circuitry. [Figure 1B] FIG. 1 is a block diagram of an exemplary random number generator (RNG) circuit including a MEMS structure(s) and active transistor RNG circuitry. [Figure 2A] 1A-1C are diagrams of example configurations of RNG circuits including MEMS structure(s) and active transistor circuit configurations based on different manufacturing technologies. [Figure 2B] 1A-1C are diagrams of example configurations of RNG circuits including MEMS structure(s) and active transistor circuit configurations based on different manufacturing technologies. [Figure 2C] 1A-1C are diagrams of example configurations of RNG circuits including MEMS structure(s) and active transistor circuit configurations based on different manufacturing technologies. [Diagram 3] FIG. 1 is a block diagram of an exemplary system.
[0008] In accordance with common practice, the various features described are not drawn to scale but rather are drawn to emphasize particular features relevant to the exemplary embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0009] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific illustrative embodiments. It should be understood, however, that other embodiments may be utilized and that logical, mechanical, and electrical changes may be made. Furthermore, the methods presented in the drawings and specification should not be construed as limiting the order in which individual steps may be performed. Accordingly, the following detailed description is not to be construed in a limiting sense.
[0010] Examples described herein include a random number generator (RNG) circuit, which includes one or more microelectromechanical mechanical systems (MEMS) structures and an active transistor RNG circuit configuration that utilizes the one or more MEMS structures to provide a source of entropy. The active transistor RNG circuit configuration can include different RNG topologies that utilize active oscillations, charge, resistance, inductance, and capacitance values output by the one or more MEMS structures as an entropy source. In some examples, the one or more MEMS structures are designed to collect environmental noise to "seed" non-determinism in the RNG in a manner that the one or more MEMS structures cannot be biased by the environment so that the RNG is deterministic. In some examples, the multiple MEMS structures have tuning offsets to ensure that the redundant MEMS inputs have different resonance points. In some examples, when an external bias is applied to the RNG circuit, the RNG circuit can be strongly biased and generate a detectable non-random output.
[0011] 1A is a block diagram of an example random number generator (RNG) circuit 100. In the example shown in FIG. 1A, the RNG circuit 100 is implemented using a combination of one or more MEMS structures 102 and active transistor RNG circuitry 104. In some examples, the RNG circuit 100 is an example implementation of the RNG circuitry described in co-pending U.S. patent application Ser. No. 18 / 661,400 (Attorney Docket No. H233692-US), entitled “CODEPENDENT PHYSICAL UNCLONABLE FUNCTION / RANDOM NUMBER GENERATOR PAIRING FOR PHYSICAL PROVENANCE.”
[0012] In some examples, the one or more MEMS structures 102 include multiple MEMS structures. In other examples, the one or more MEMS structures 102 include a single MEMS structure. In general, the more MEMS structures 102, the better, as having more MEMS structures 102 increases the entropy of the RNG circuit 100 and improves the performance of the RNG circuit 100.
[0013] The one or more MEMS structures 102 may be any type of MEMS device, such as an accelerometer, a gyroscope, a pressure sensor, a temperature sensor, an airflow sensor, or other similar MEMS structures. When included in the RNG circuit 100, the one or more MEMS structures 102 may serve as an additional source of entropy for the active transistor RNG circuitry 104.
[0014] In some examples, the one or more MEMS structures 102 include one or more RNG MEMS structures used exclusively for the RNG circuit 100. In other examples, the one or more MEMS structures 102 include one or more shared MEMS structures shared with another circuit (e.g., a physical unclonable function (PUF) circuit). In some examples, the one or more MEMS structures 102 include both one or more RNG MEMS structures used exclusively for the RNG circuit 100 and one or more shared MEMS structures shared with another circuit.
[0015] The one or more MEMS structures 102 are configured to supply entropy for the RNG circuit 100 by harvesting environmental noise and providing active oscillation, charge, resistance, inductance, and / or capacitance values to the active transistor RNG circuitry 104. In some examples, the one or more MEMS structures 102 are active components. In other examples, the one or more MEMS structures 102 are passive components.
[0016] The RNG circuit 100 generates a sequence of numbers or symbols that cannot be reasonably predicted better than by random chance, or extracts randomness from physical phenomena to generate numbers (e.g., acts as a true RNG). In some examples, one or more MEMS structures 102 act as an entropy source for the active transistor RNG circuitry 104, which includes a combination of noise sources, health tests, and optional tuning components that generate the random bit strings used by the active transistor RNG circuitry 104. The noise source is the component of the entropy source that includes non-deterministic entropy generating activities (e.g., environmental noise, thermal noise, or hard drive seek times).
[0017] In some examples, the one or more MEMS structures 102 include multiple MEMS structures 102, where the MEMS structures 102 are configured with tuning offsets such that different MEMS structures 102 have different resonance points. This can help prevent the MEMS structures 102 from being biased by the environment and the RNG circuit 100 from being deterministic, as the MEMS structures 102 will be biased differently depending on the environment.
[0018] In some examples, the one or more MEMS structures 102 are configured to receive feedback from the active transistor RNG circuitry 104 to set the tuning of the one or more MEMS structures 102. In some examples, the one or more MEMS structures 102 are designed to harmonically resonate at different frequencies based on feedback from the active transistor RNG circuitry 104. However, when an external bias is introduced to the RNG circuit 100, the one or more MEMS structures 102 are configured to lock up to prevent an output that may pass as random. In some examples, the one or more MEMS structures 102 are configured to lock up and interfere with each other such that the RNG circuit 100 is strongly biased and generates an RNG output, such as, for example, a periodic waveform, all zeros, or all ones, instead of a random output. This approach can help avoid problems with bad random outputs going undetected (e.g., when the output generated by the RNG circuit 100 is non-random but passes as random).
[0019] In some examples, components of the active transistor RNG circuitry 104 are implemented using transistor-based integrated circuits. For example, the active transistor RNG circuitry 104 may be implemented in an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or another type of integrated circuit.
[0020] In some examples, the active transistor RNG circuitry 104 may include, but is not limited to, circuitry configured to generate a random number output. For example, if the active transistor RNG circuitry 104 is configured to implement a ring oscillator RNG, the active transistor RNG circuitry 104 may include, but is not limited to, an array of ring oscillator loops coupled to exclusive-OR (XOR) components, sampling circuitry, or the like.
[0021] In some examples, the active transistor RNG circuitry 104 is dedicated to the RNG circuit 100. In other examples, at least some components of the active transistor RNG circuitry 104 of the RNG circuit 100 are shared with another circuit (e.g., a physically unclonable function (PUF) circuit).
[0022] In some examples, the circuit connections between one or more MEMS structures 102 and the active transistor RNG circuitry 104 allow the operation of one or more MEMS structures 102 to be influenced by the active transistor RNG circuitry 104, and vice versa, as shown in FIG. 1A using the bidirectional arrows between these components. One or more MEMS structures 102 should influence the active transistor RNG circuitry 104, and the active transistor RNG circuitry 104 should influence one or more MEMS structures 102, such that these components of the RNG circuit 100 are codependent. In some examples, changes to one or more MEMS structures 102 or the active transistor RNG circuitry 104 result in changes to the RNG output from the RNG circuit 100. These features help prevent a situation in which a MEMS structure 102 can be removed, characterized, and replaced to spoof or modify the operation of the RNG circuit 100 for fraudulent purposes.
[0023] In the example shown in FIG. 1A, the RNG circuit 100 is configured to generate a random number output based on an output from the MEMS structure 102. In some examples, the RNG circuit 100 is configured to generate a random number output based on physical characteristics of the active transistor RNG circuitry 104, among other factors. The output of the active transistor RNG circuitry 104 is random and non-deterministic. In some examples, the output of the active transistor RNG circuitry 104 is affected over time due to aging or other factors. The active transistor RNG circuitry 104 can be configured to implement a variety of RNG architectures (e.g., a ring oscillator, etc.) and can include a variety of different electronic components.
[0024] 1A, the randomness of the random number output is affected by the number of components (e.g., more ring oscillator loops or MEMS structures) of the active transistor circuitry and one or more MEMS structures, component-to-component variations (e.g., variations between multiple ring oscillator loops or similar MEMS structures of different lengths), noise (e.g., due to manufacturing processes), etc. In general, the randomness of the random number output is increased by using active oscillation, charge, resistance, inductance, and / or capacitance values output from one or more MEMS structures 102 in addition to the active transistor RNG circuitry 104, as compared to an RNG circuit including only active transistor circuitry.
[0025] In some examples, the RNG circuit 100 includes at least some shared active transistor circuitry that is shared with another circuit, in addition to the active transistor RNG circuitry 104 that is used exclusively for the RNG circuit 100.
[0026] 1B is a block diagram of an example random number generator (RNG) circuit 110. In the example shown in FIG. 1B, the RNG circuit 110 is implemented using a combination of one or more MEMS structures 102 and active transistor RNG circuitry 104. In some examples, the RNG circuit 110 is an example implementation of RNG circuitry as described in co-pending U.S. patent application Ser. No. 18 / 661,400 (Attorney Docket No. H233692-US), entitled “CODEPENDENT PHYSICAL UNCLONABLE FUNCTION / RANDOM NUMBER GENERATOR PAIRING FOR PHYSICAL PROVENANCE.”
[0027] The exemplary RNG circuit 110 shown in Figure 1B is a specific example of the RNG circuit 100 described above with respect to Figure 1A. In the example shown in Figure 1B, the RNG circuit 110 implements a ring oscillator RNG topology. It should be understood that different topologies for the active transistor RNG circuitry 104 can also be used in combination with one or more MEMS structures 102 to implement the RNG circuit 100.
[0028] 1B, the one or more MEMS structures 102 include an array of MEMS structures 112. The MEMS structures 112 are configured to output active oscillation, charge, resistance, inductance, and / or capacitance values to a ring oscillator loop 114. The MEMS structures 112 provide additional entropy to the ring oscillator loop 114.
[0029] In the example shown in FIG. 1B, the active transistor RNG circuitry 104 includes an array of ring oscillator loops 114 each having a different length (e.g., by including a different number of inverter components in the loop), which ensures that the frequencies of the ring oscillator loops 114 are never the same. In the example shown in FIG. 1B, the frequency of each of the ring oscillator loops 114 depends on the loop delay and active oscillation from the MEMS structure 112, the charge, resistance, inductance, and / or capacitance values, which affect the rise and fall times of the inverter links. In the example shown in FIG. 1B, each of the ring oscillator loops 114 includes a particular number of inverters, but it should be understood that other odd numbers of inverters can also be used for the ring oscillator loops 114.
[0030] 1B, each of the MEMS structures 112 is coupled to a respective ring oscillator loop 114, and each ring oscillator loop 114 is coupled to at least one MEMS structure 112. In the example shown in FIG. 1B, four MEMS structures 112 are coupled to different points of the top ring oscillator loop 114. In some examples, two or more of the ring oscillator loops 114 have multiple MEMS structures 112 coupled to different points of the ring oscillator loop 114. The multiple MEMS structures 112 add active oscillation, charge, resistance, inductance, and / or capacitance values at different points in the ring oscillator loop 114.
[0031] In the example shown in FIG. 1B , some of the MEMS structures 112 are coupled to the ring oscillator loop 114 via signal conditioning blocks. In some examples, the signal conditioning blocks are configured to perform one or more signal conditioning functions on signals communicated from the MEMS structures 112 to the ring oscillator loop 114 or from the ring oscillator loop 114 to the MEMS structures 112. In some examples, the signal conditioning blocks include AC coupling circuitry, voltage dividers, and / or other circuitry. In some examples, the signal conditioning blocks are configured to perform level translation, amplification, DC offset isolation (e.g., using AC coupling), and / or other signal conditioning functions. In some examples, the signal conditioning blocks used to interface between each MEMS structure 112 and its corresponding ring oscillator loop 114 provide a unique interface between each individual MEMS structure 112 and its corresponding ring oscillator loop 114.
[0032] In some examples, the signal conditioning block is not required for the RNG circuit 110, but one or more of the MEMS structure 102, the active transistor RNG circuitry 104, and / or the signal conditioning block are shared by the RNG circuit 110 and a physically unclonable function (PUF) circuit. In such examples, the signal conditioning block may be disabled when the shared circuitry is configured to operate in the RNG configuration.
[0033] In general, it is better to have more MEMS structures 112 coupled to each of the ring oscillator loops 114 in order to increase the effect of active oscillation, charge, resistance, inductance, and capacitance from the MEMS structures 112 to provide entropy to the ring oscillator loops 114. Also, having more ring oscillator loops 114 generally increases the entropy of the RNG circuit 100, so it is better to have more ring oscillator loops 114.
[0034] 1B, the active transistor RNG circuitry 104 of the RNG circuit 110 further includes exclusive-or (XOR) blocks 118 communicatively coupled respectively to each of the ring oscillator loops 114 in the array of ring oscillator loops 114. The XOR blocks 118 output a signal having a varying frequency and duty cycle.
[0035] In the example shown in FIG. 1B, the active transistor RNG circuitry 104 of the RNG circuit 110 further includes sampling circuitry including a clock divider 116 coupled to the bottom ring oscillator loop 114 and the flip-flop 120. In some examples, the clock divider 116 may be coupled to a different ring oscillator loop 114. The clock divider 116 is configured to generate a sample clock signal that is fed to the flip-flop 120 and determines when the flip-flop 120 samples the signal output by the XOR block 118. In some examples, the clock divider 116 is configured to generate a sample clock signal having a relatively low frequency, which results in under-sampling of the signal output by the XOR block 118 and makes the sampled value random. In general, the length of the clock divider 116 improves the randomness of the output bits (random number output).
[0036] In some examples, the MEMS structures 112 are configured to have tuning offsets such that different MEMS structures 112 have different resonance points. This can help prevent the MEMS structures 112 from being biased by the environment and the RNG circuit 100 from being deterministic, as the MEMS structures 112 will be biased differently depending on the environment.
[0037] In some examples, the MEMS structures 112 are configured to receive feedback from the active transistor RNG circuitry 104 (e.g., from the ring oscillator loop 114) to set the tuning of the MEMS structures 112. In some examples, the MEMS structures 112 are designed to harmoniously resonate at different frequencies based on feedback from the respective ring oscillator loops 114 of the active transistor RNG circuitry 104. However, when an external bias is introduced to the RNG circuitry 110, the MEMS structures 112 are configured to lock up to prevent an output that may pass as random. In some examples, the MEMS structures 112 are configured to lock up and interfere with each other such that the RNG circuitry 110 is strongly biased and generates an RNG output, such as, for example, a periodic waveform, all zeros, or all ones, instead of a random output. This approach can help avoid issues with bad random outputs going undetected (e.g., when the output generated by the RNG circuitry 110 is non-random but passes as random).
[0038] It should be understood that while a particular number of MEMS structures 112 and ring oscillator loops 114 are shown in FIG. 1B, this is by way of example only and that different numbers of MEMS structures 112 and / or ring oscillator loops 114 can be included in the RNG circuit 110 and different configurations of the MEMS structures 112 and ring oscillator loops 114 can be used to generate random number outputs with sufficient non-determinism.
[0039] 1A-1B, it should be understood that other configurations are possible. For example, two or more instances of the RNG circuits 100, 110 may be included in a single device or system. Furthermore, the RNG circuits 100, 110 may be integrated into a larger device or system that includes additional circuitry beyond that shown for the RNG circuits 100, 110 to perform additional functions that utilize the random number output for cryptographic processes.
[0040] 2A-2C are diagrams of example RNG circuits including one or more MEMS structures and active transistor RNG circuit configurations fabricated using different fabrication techniques. The example configurations of RNG circuits and fabrication techniques described with respect to FIGs. 2A-2C are not intended to be exhaustive. It should be understood that other configurations of RNG circuits including one or more MEMS structures and active transistor RNG circuit configurations may also be fabricated using other fabrication techniques.
[0041] FIG. 2A shows a diagram of a RNG circuit 200 that includes one or more MEMS structures 202 and active transistor RNG circuitry 204 and is fabricated using a first fabrication technique.
[0042] 2A , the one or more MEMS structures 202 are fabricated separately from the active transistor RNG circuitry 204 and connected to the active transistor RNG circuitry 204 using a substrate 206. In some examples, the one or more MEMS structures 202 and the active transistor RNG circuitry 204 may be fabricated on separate dies, but then the one or more MEMS structures 202 and the active transistor RNG circuitry 204 are mounted on the substrate 206. In some examples, the one or more MEMS structures 202 are packaged separately from the active transistor RNG circuitry 204 and connected on a circuit board.
[0043] To connect the one or more MEMS structures 202 to the active transistor RNG circuitry 204, interconnects are used between the one or more MEMS structures 202 and the active transistor RNG circuitry 204. In some examples, increasing the length of the interconnects between the one or more MEMS structures 202 and the active transistor RNG circuitry 204 can be beneficial because increasing the length of the interconnects can introduce unpredictability into the RNG circuit 200. Thus, in some implementations of the RNG circuit 200, the one or more MEMS structures 202 and the active transistor RNG circuitry 204 are disposed at opposite ends of a substrate 206, respectively.
[0044] FIG. 2B shows a diagram of a second RNG circuit 210 including one or more MEMS structures 212 and active transistor RNG circuitry 214 and fabricated using a second fabrication technique.
[0045] 2B , the one or more MEMS structures 212 are fabricated separately from the active transistor RNG circuitry 214 and stacked on top of the active transistor RNG circuitry 214. In some examples, the one or more MEMS structures 212 and the active transistor RNG circuitry 214 may be fabricated on separate die, but then the one or more MEMS structures 212 are stacked on top of the active transistor RNG circuitry 214. In some examples, the one or more MEMS structures 212 are packaged separately from the active transistor RNG circuitry 214 and stacked (e.g., on a circuit board) on top of the active transistor RNG circuitry 214.
[0046] To connect the one or more MEMS structures 212 to the active transistor RNG circuitry 214, vertical interconnects are used between the one or more MEMS structures 212 and the active transistor RNG circuitry 214. The vertical connections generally reduce the length of the interconnects between the one or more MEMS structures 212 and the active transistor RNG circuitry 214 compared to the interconnects used in FIG. 2A. When the one or more MEMS structures 212 are aligned with corresponding components of the active transistor RNG circuitry 214, the length of the interconnects is further reduced. Thus, in some implementations of the second RNG circuit 210, the one or more MEMS structures 212 and the active transistor RNG circuitry 214 are stacked and aligned to increase the length of the vertical interconnects as much as possible. In some circumstances, the vertical stacking of the one or more MEMS structures 212 and the active transistor RNG circuitry 214 may also improve resistance to physical tampering.
[0047] FIG. 2C shows a diagram of a third RNG circuit 220 including one or more MEMS structures 222 and active transistor RNG circuitry 224 and fabricated using a third fabrication technique.
[0048] 2C, one or more MEMS structures 222 are fabricated with active transistor RNG circuitry 224. In some examples, one or more MEMS structures 222 and active transistor RNG circuitry 224 may be fabricated on the same die, but then one or more MEMS structures 202 are stacked on top of the active transistor RNG circuitry 204.
[0049] To connect the one or more MEMS structures 222 to the active transistor RNG circuitry 224, an interconnect is used between the one or more MEMS structures 222 and the active transistor RNG circuitry 224. Because the one or more MEMS structures 222 and the active transistor RNG circuitry 224 are fabricated on the same die, the one or more MEMS structures 222 and the active transistor RNG circuitry 224 will generally be closer to each other. Thus, the length of the interconnect between the one or more MEMS structures 222 and the active transistor RNG circuitry 224 will likely be shorter compared to the interconnect used in FIG. 2A. In some implementations of the third RNG circuit 220, the one or more MEMS structures 222 and the active transistor RNG circuitry 224 are placed as far apart as feasible on the same die.
[0050] 3 is a block diagram of a system 300 that includes secure communications between nodes 301 in an exclusive community over a network 303 using a random component generated by a RNG circuit 302 in the node 301. Several example protocols for creating the random component from the RNG circuit 302 are described in more detail herein.
[0051] In the example shown in Figure 3, system 300 is shown with two nodes 301, labeled node 301-A and node 301-B. It should be understood that system 300 may include any suitable number of nodes 301, and thus system 300 is not limited to a system having two nodes 301. Furthermore, Figure 3 shows node 301-A coupled to node 301-B via network 303. It should be understood that network 303 may comprise one or more of wireless access points, communication links, a wide area network (WAN), a local area network (LAN) such as an Ethernet network, cable groups, optical fibers, direct connections, or any other suitable system for communicatively coupling the nodes 301 of system 300.
[0052] 3, node 301-A and node 301-B each include similar components for secure communications in system 300. Thus, for the sake of brevity and simplicity, only node 301-A will be described in detail using reference numbers for each component followed by the designator "-A." It should be understood that similar components are also included in node 301-B, identified by the same reference numbers followed by the designator "-B."
[0053] In the example shown in FIG. 3, node 301-A includes an RNG circuit 302-A. In some examples, the RNG circuit 302-A may be implemented as an RNG circuit 100 or an RNG circuit 110, as described above with respect to FIGS. 1A-1B. In some examples, the RNG circuit 302-A supports more than one function for node 301-A by providing one or more outputs. In some examples, the output may include a standard component and a random component. In some examples, the random component includes a random number output, as described above.
[0054] A first function supported by the RNG circuit 302-A uses a standard component of the output from the RNG circuit 302-A. For example, the RNG circuit 302-A may include a sensor (e.g., a MEMS sensor) and the standard component may be acceleration, rotational speed, pressure, temperature, airflow, or other measurement associated with the sensor.
[0055] A second function supported by the RNG circuit 302-A is the use of a random component for secure communications with other nodes 301 in the system 300. In some examples, the RNG circuit 302-A generates the random component using one or more sources of entropy and process variations during manufacturing that create the random aspect of the RNG circuit 302-A. In some examples, the random component output by the RNG circuit 302-A may be derived from active transistor circuitry and / or one or more MEMS structures included in the RNG circuit 302-A.
[0056] In some examples, node 301-A also includes one or more processors and memory for storing software or instructions for implementing functions for node 301-A. In the example shown in Figure 3, node 301-A includes standard function 307-A that supports a first function of node 301-A. Standard function 307-A, among other things, uses a standard component of the output of RNG circuit 302-A to cause node 301-A to implement its standard function that is implemented based on the output of RNG circuit 302-A.
[0057] Node 301-A also includes instructions or software for implementing a second function of node 301-A. In the example shown in FIG. 3, node 301-A includes origin determination function 308-A, encryption / decryption circuitry 312-A, and verification / validation function 314-A. In some examples, RNG circuitry 302-A is configured to output a random number from the RNG circuitry, and the random number output is used in conjunction with encryption / decryption circuitry 312-A to securely transmit data over network 303. In some examples, node 301-A uses origin determination function 308-A in conjunction with verification / validation function 314-A to implement authentication that data received or transmitted by node 301-A is from an authorized node in system 300.
[0058] 3, the system 300 also includes a master node 320 that is used to set up trust relationships between the nodes 301 of the system 300 that are in the exclusive community. The master node 320 is communicatively coupled to each of the nodes 301 via the network 303.
[0059] In some examples, each corresponding node 301 generates many registries (e.g., thousands or tens of thousands of registries) using the provenance determination function 308 and a unique component of the output of the MEMS structure of the RNG circuit 302-A or PUF circuit (not shown) of each node 301. These registries uniquely identify the particular node 301 as part of the trusted system 300. The master node 320 takes the registries generated by each node 301 (e.g., when the node 301 is set up) and provides the registries to all other nodes 301 in the system 300. These registries are stored as part of the provenance determination function 308 of each node 301 in the exclusive community, and effectively become a library of authorized users in the exclusive community of the system 300. By using these registry values, a given node 301 will only recognize data received from similarly equipped nodes 301. When data is received over network 303, the receiving node 301 uses the registries in the origination function 308 in conjunction with verification / validation function 314 to authenticate that the input originated from an authorized user. For example, the receiving node 301 may verify that the node 301 sending the data generated an output of the origination function 308 that corresponds to one of the registries provided by the master node 320 and contained in its own origination function 308.
[0060] In another example, the master node 320 is configured to act as a certification authority (CA) for applications that use asymmetric cryptography. In such an example, the master node 320 is configured to issue digital certificates to the nodes 301, and the verification / validation function 314 uses the issued digital certificates to authenticate that input originates from an authorized user.
[0061] In the example shown in Figure 3, node 301-A also includes a transceiver 316-A that provides an interface for communicating with other nodes 301, such as node 301-B, over network 303. Although a single transceiver 316-A is shown in Figure 3, it should be understood that the single transceiver 316-A may be replaced with separate and distinct transmitter and receiver components.
[0062] In various aspects, the system elements, method steps, or examples (e.g., devices, systems, or components thereof) described throughout this disclosure may be implemented on one or more computer systems, including central processing units (CPUs), graphics processing units (GPUs), Field Programmable Gate Arrays (FPGAs), Application Specific Integrated Circuits (ASICs), and / or similar devices with hardware to execute code to implement those elements, processes, or examples, which code is stored in non-transitory data storage devices. These devices include or function with software programs, firmware, or other computer readable instructions to perform various method, process tasks, computations, and control functions.
[0063] These instructions are typically stored on any suitable computer-readable medium used for storing computer-readable instructions or data structures. Computer-readable media can be implemented as any available medium that can be accessed by a general purpose or specialized computer or processor, or any programmable logic device. Suitable processor-readable media can include storage or memory media, such as magnetic or optical media. For example, storage or memory media may include volatile or non-volatile media, such as conventional hard disks, Compact Disk - Read Only Memory (CD-ROM), Random Access Memory (RAM) (including but not limited to Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate (DDR) RAM, RAMBUS Dynamic RAM (RDRAM), Static RAM (SRAM), etc.), Read Only Memory (ROM), Electrically Erasable Programmable ROM (EEPROM), and Flash memory. Suitable processor-readable media may also include transmission media, such as electrical, electromagnetic, or digital signals conveyed over a communications medium, such as a network and / or wireless link.
[0064] The methods and techniques described herein may be implemented in digital electronic circuitry, or with a programmable processor (e.g., a special purpose processor or a general purpose processor such as a computer), firmware, software, or a combination thereof. Apparatus embodying these techniques may include suitable input and output devices, a programmable processor, and a storage medium tangibly embodying program instructions for execution by the programmable processor. Processes embodying these techniques may be performed by a programmable processor executing a program of instructions to perform a desired function by operating on input data and generating appropriate output. The techniques may be advantageously implemented in one or more programs executable on a programmable system including at least one programmable processor coupled to receive data and instructions from and transmit data and instructions to a data storage system, at least one input device, and at least one output device. In general, the processor receives instructions and data from a read-only memory and / or a random access memory. Suitable storage devices for tangibly embodying computer program instructions and data include all forms of non-volatile memory, including, for example, semiconductor memory devices (EPROM, EEPROM, and Flash memory devices), magnetic disks (internal hard disk or removable disk), magneto-optical disks, and DVD disks. Any of the foregoing may be supplemented by, or incorporated in, specially designed application-specific integrated circuits (ASICs).
[0065] Exemplary embodiments Example 1 includes a random number generator (RNG) circuit, the RNG circuit comprising one or more microelectromechanical (MEMS) structures configured to provide an output comprising an active oscillation, a charge, a resistance, a capacitance, and / or an inductance value, and active transistor RNG circuitry communicatively coupled to the one or more MEMS structures, the active transistor RNG circuitry configured to generate a random number output based on the output provided by the one or more MEMS structures, and the random number output generated by the active transistor RNG circuitry is an output of the RNG circuit.
[0066] Example 2 includes the RNG circuit of example 1, where one or more MEMS structures and / or active transistor RNG circuit configurations are dedicated to the RNG circuit.
[0067] A third embodiment includes the RNG circuit of any one of the first and second embodiments, and the one or more MEMS structures includes a plurality of MEMS structures.
[0068] Example 4 includes the RNG circuit of example 3, and the multiple MEMS structures are configured to have tuning offsets such that each of the multiple MEMS structures has a different resonance point.
[0069] Example 5 includes the RNG circuit of any of Examples 3-4, wherein the plurality of MEMS structures is configured to receive feedback from the active transistor RNG circuitry for tuning the plurality of MEMS structures.
[0070] Example 6 includes the RNG circuit of any of Examples 1 to 5, wherein in response to an external bias applied to the RNG circuit, the RNG circuit is configured to generate a detectable non-random output.
[0071] Example 7 includes the RNG circuit of any of Examples 1-6, where the active transistor RNG circuit configuration is further configured to generate the random number output based on manufacturing variations in components of the active transistor RNG circuit configuration.
[0072] Example 8 includes the RNG circuit of any of Examples 1-7, wherein the RNG circuit further includes a corresponding signal conditioning circuit coupled between at least one MEMS structure of the one or more MEMS structures and the active transistor RNG circuit configuration.
[0073] Example 9 includes the RNG circuit of any of Examples 1-8, wherein one or more MEMS structures are stacked on top of the active transistor RNG circuit configuration.
[0074] Example 10 includes the RNG circuit of any of Examples 1-9, wherein the one or more MEMS structures and the active transistor RNG circuit configuration are coupled using interconnects, and the one or more MEMS structures and the active transistor RNG circuit configuration are disposed on the same die or substrate.
[0075] Example 11 includes the RNG circuit of any of Examples 1 to 10, and the active transistor RNG circuit configuration includes a plurality of ring oscillator loops having different lengths, an exclusive-or (XOR) block coupled to the plurality of ring oscillator loops, and a sampling circuit coupled to the XOR block.
[0076] Example 12 includes the RNG circuit of any of Examples 10-11, wherein the plurality of MEMS structures are coupled to the at least one ring oscillator loop.
[0077] Example 13 includes the RNG circuit of any of Examples 1-12, wherein the active transistor RNG circuit configuration is communicatively coupled to the one or more MEMS structures using circuit connections that enable operation of the one or more MEMS structures to be affected by the active transistor RNG circuit configuration and that enable operation of the active transistor RNG circuit configuration to be affected by the one or more MEMS structures.
[0078] Example 14 includes a device, the device including a random number generator (RNG) circuit including one or more microelectromechanical (MEMS) structures configured to output active oscillation, charge, resistance, capacitance, and / or inductance values, and active transistor RNG circuitry communicatively coupled to the one or more MEMS structures and configured to generate a random number output of the RNG circuit based on the active oscillation, charge, resistance, inductance, and / or capacitance values output by the one or more MEMS structures, and one or more additional circuits configured to utilize the random number output for one or more cryptographic processes.
[0079] Example 15 includes the device of example 14, wherein each of the one or more MEMS structures is configured to have a different resonant point than the other MEMS structures based on feedback from the active transistor RNG circuitry.
[0080] Example 16 includes the device of any of Examples 14-15, wherein the RNG circuit is configured to generate a detectable non-random output in response to an external bias applied to the RNG circuit.
[0081] Example 17 includes the device of any of examples 14-16, wherein the active transistor RNG circuitry includes a plurality of ring oscillator loops having different lengths, an exclusive-or (XOR) block coupled to the plurality of ring oscillator loops, and a sampling circuitry coupled to the XOR block.
[0082] Example 18 includes the device of example 17, wherein two or more MEMS structures are coupled to at least one of the ring oscillator loops.
[0083] Example 19 includes the device of any of examples 14-18, wherein the active transistor RNG circuitry is further configured to generate the random number output based on manufacturing variations in components of the active transistor RNG circuitry.
[0084] Example 20 includes a system comprising a plurality of devices configured to communicate with each other over a network, each device of the plurality of devices including a random number generator (RNG) circuit, the RNG circuit including a microelectromechanical (MEMS) structure configured to provide an output including an active oscillation, a charge, a resistance, a capacitance, and / or an inductance value, and an active transistor RNG circuitry communicatively coupled to the MEMS structure, the active transistor RNG circuitry configured to generate a random number output for the RNG circuit based on the output by the MEMS structure, and one or more additional circuits configured to utilize the random number output for one or more cryptographic processes when communicating with other devices over the network.
[0085] Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that any configuration which is expected to achieve the same purpose may be substituted for the specific embodiments shown. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
Claims
1. A random number generator (RNG) circuit (100, 110, 200, 210, 220) comprising: one or more microelectromechanical (MEMS) structures configured to provide an output including an active oscillation, a charge, a resistance, a capacitance, and / or an inductance value; and active transistor RNG circuitry (104) communicatively coupled to the one or more MEMS structures (102), the active transistor RNG circuitry (104) is configured to generate a random number output based on the output provided by the one or more MEMS structures (102); An RNG circuit (100, 110, 200, 210, 220), wherein the random number output generated by the active transistor RNG circuitry (104) is the output of the RNG circuit (100, 110, 200, 210, 220).
2. 2. The RNG circuit of claim 1, wherein the one or more MEMS structures include a plurality of MEMS structures configured to have a tuning offset such that each of the plurality of MEMS structures has a different resonance point.
3. The RNG circuit (100, 110, 200, 210, 220) of claim 1 or 2, wherein in response to an external bias applied to the RNG circuit (100, 110, 200, 210, 220), the RNG circuit (100, 110, 200, 210, 220) is configured to generate a detectably non-random output.