Display device

Abstract

To provide a display device having an extreme narrow bezel structure.SOLUTION: A display device contains: a substrate that contains a display region where a plurality of sub-pixels is disposed and a non-display region containing a pad region positioned in a first direction from the display region; an insulation film stack that is positioned onto the substrate, and includes an outer side surface; a cathode that is positioned onto the insulation film stack, and is arranged so as to be extended to one part of the non-display region from the display region; a first inorganic film that is positioned onto the cathode, and is extended to the non-display region from the display region; an organic film that is positioned onto one part of the first inorganic film, and includes an outer side inclination surface; a second inorganic film that is positioned onto the organic film, is arranged so as to be extended to the non-display region from the display region, and is arranged so as to be extended along the outer side inclination surface; and a stopper that is positioned to the insulation film stack, and is arranged to an outline of the organic film.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] TECHNICAL FIELD The embodiments of the present disclosure relate to a display device. [Background technology]

[0002] A display panel of a display device may include a display area where an image is displayed and a non-display area where an image is not displayed. Various structures, circuits, and wiring may be arranged in the non-display area (also called a "bezel") of the display panel. This makes it difficult to reduce the bezel of the display panel. Summary of the Invention [Problem to be solved by the invention]

[0003] The embodiments of the present disclosure can provide a display device having an extremely narrow bezel structure.

[0004] The embodiments of the present disclosure can provide a display device having an organic film overflow prevention structure that enables an extremely narrow bezel.

[0005] Embodiments of the present disclosure can provide a display device that includes a gate-in-panel circuit structure that allows for extremely narrow bezels.

[0006] Embodiments of the present disclosure can provide a display device with a touch routing structure that allows for an extremely narrow bezel. [Means for solving the problem]

[0007] A display device according to an embodiment of the present disclosure includes a substrate including a display region in which a plurality of subpixels are arranged and a non-display region including a pad region located in a first direction from the display region, an insulating film stack located on the substrate and having an outer side of the non-display region, a stopper located on the insulating film stack, a cathode located on the insulating film stack and extending from the display region to a portion of the non-display region and overlapping an upper surface of at least a portion of the stopper, a first inorganic film located on the cathode and arranged to extend from the display region to the non-display region, an organic film located on a portion of the first inorganic film and having an outer inclined surface, and a second inorganic film located on the organic film and arranged to extend from the display region to the non-display region and arranged to extend along the outer inclined surface of the organic film.

[0008] The stopper may be disposed in the non-display region and may be located further outward than the organic film. The outer surface of the stopper may have a steeper slope than the inner surface of the stopper.

[0009] An end of the common intermediate layer and an end of the cathode may be located on the stopper, and the end of the cathode may protrude further outward than the upper layer of the outer surface of the stopper and the end of the common intermediate layer.

[0010] A display device according to an embodiment of the present disclosure may include a substrate, an insulating film stack on the substrate, a plurality of light-emitting elements on the insulating film stack, an organic film on the plurality of light-emitting elements, and a stopper disposed on an outer periphery of the organic film.

[0011] The stopper may be disposed on an outer surface of an outermost light emitting device among the plurality of light emitting devices, and may have a thickness greater than that of the anode of the outermost light emitting device.

[0012] According to the embodiment of the present disclosure, it is possible to provide a display device having an extremely narrow bezel structure.

[0013] According to an embodiment of the present disclosure, a display device having an organic film overflow prevention structure that enables an extremely narrow bezel can be provided.

[0014] According to an embodiment of the present disclosure, a display device can be provided that includes a gate-in-panel circuit structure that enables an extremely narrow bezel.

[0015] According to an embodiment of the present disclosure, a display device can be provided with a touch routing structure that allows for an extremely narrow bezel.

[0016] According to the embodiment of the present disclosure, an extremely narrow bezel structure can be provided, thereby enabling the display device to be made lighter. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a system configuration diagram of a display device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 illustrates a display panel according to an embodiment of the present disclosure. [Diagram 3] FIG. 2 illustrates a substrate of a display panel according to an embodiment of the present disclosure. [Figure 4] FIG. 2 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. [Diagram 5] FIG. 2 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. [Figure 6] 4 is a cross-sectional view of an outer region of a display panel according to an embodiment of the present disclosure. [Figure 7] FIG. 2 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. [Figure 8] FIG. 2 is another cross-sectional view of a display panel according to an embodiment of the present disclosure. [Figure 9] FIG. 2 is a plan view illustrating a touch sensor included in a display panel according to an embodiment of the present disclosure. [Figure 10] 2 is a diagram illustrating an exemplary detailed view of a portion of a touch sensor included in a display panel according to an embodiment of the present disclosure. [Figure 11] FIG. 2 illustrates a substrate and an encapsulation layer of a display panel according to an embodiment of the present disclosure. [Figure 12] FIG. 2 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. [Figure 13] FIG. 2 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. [Figure 14] FIG. 2 is a diagram showing a gate drive circuit of a display device according to an embodiment of the present disclosure. [Figure 15] FIG. 13 is a diagram showing the vertical structure of a display panel when a gate-in-panel circuit is disposed over the entire display area of ​​the display panel according to an embodiment of the present disclosure. [Figure 16] 2 is a cross-sectional view of a display area of ​​a display panel according to an embodiment of the present disclosure. [Figure 17] 1A and 1B are diagrams illustrating the vertical and planar structures of a display panel when a gate-in-panel circuit is disposed in a portion of the display area of ​​the display panel according to an embodiment of the present disclosure. [Figure 18] 1A and 1B are diagrams illustrating the vertical and planar structures of a display panel when a gate-in-panel circuit is disposed in a portion of the display area of ​​the display panel according to an embodiment of the present disclosure. [Figure 19] FIG. 2 is a plan view of a partial area of ​​a display panel according to an embodiment of the present disclosure. [Figure 20] FIG. 2 is a diagram showing the correspondence between sub-pixel circuits and light-emitting elements in a display panel according to an embodiment of the present disclosure. [Figure 21] FIG. 2 is a cross-sectional view of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] Some embodiments of the present disclosure will be described in detail below with reference to the exemplary drawings. When adding reference symbols to components in each drawing, the same symbols can be attached to the same components as much as possible even if they are displayed on different drawings. In addition, when describing the present disclosure, if it is determined that a specific description of a related publicly known configuration or function makes the gist of the present disclosure unclear, the detailed description can be omitted. When "includes," "has," "performed," and the like are used in this specification, other parts may be added unless "only" is used. When a component is expressed as a singular number, it may include a case where a plurality is included unless otherwise explicitly stated.

[0019] In addition, in describing components of the present disclosure, terms such as first, second, A, B, A, B, etc. are used. These terms are used to distinguish the components from other components, and do not limit the essence, order, procedure, number, etc. of the components.

[0020] In describing the positional relationship of components, when two or more components are described as being "coupled," "coupled," or "connected," it should be understood that the two or more components may be directly "coupled," "coupled," or "connected," but that the two or more components may also be "coupled," "coupled," or "connected" through an additional "intervening" component. Here, the additional component may be included in one or more of the two or more components that are "coupled," "coupled," or "connected" to each other.

[0021] In describing a temporal sequence of components, methods of operation, methods of production, etc., when the temporal or chronological sequence is described using, for example, "after," "following," "after," or "before," this can include cases where the sequence is not consecutive, unless "immediately" or "directly" is used.

[0022] On the other hand, when referring to numerical values ​​or corresponding information (e.g., levels, etc.) for components, even if there is no explicit mention otherwise, the numerical values ​​or corresponding information can be interpreted as including an error range that may arise due to various factors (e.g., process factors, internal or external impacts, noise, etc.).

[0023] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0024] FIG. 1 is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0025] 1, a display device 100 according to an embodiment of the present disclosure may include a display panel 110 and a display driving circuit as components for displaying an image. The display driving circuit may include a data driving circuit 120, a gate driving circuit 130, a display controller 140, etc. as circuits for driving the display panel 110.

[0026] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111 .

[0027] A substrate 111 of the display panel 110 can include a display area DA capable of displaying an image, and a non-display area NDA located on the periphery of the display area DA.

[0028] A plurality of sub-pixels SP for displaying an image are arranged in the display area DA, and the non-display area NDA may include a pad area PA located in a first direction from the display area DA.

[0029] In the display panel 110 according to the embodiment of the present disclosure, the non-display area NDA may be very small. In this specification, the non-display area NDA is also referred to as a "bezel."

[0030] For example, the non-display area NDA may include a first non-display area located on the periphery of the display area DA in a first direction, a second non-display area located on the periphery of the display area DA in a second direction intersecting the first direction, a third non-display area located on the periphery of the display area DA in a direction opposite to the first direction, and a fourth non-display area located on the periphery of the display area DA in a direction opposite to the second direction. One or two of the first to fourth non-display areas may include a pad area to which the data driving circuit 120 is connected or bonded. Two or three of the first to fourth non-display areas that do not include the pad area may be very small in size.

[0031] As another example, the boundary area between the display area DA and the non-display area NDA can be curved, with the non-display area NDA located at the bottom of the display area, in which case little or none of the non-display area NDA may be visible to the user when the user views the display device 100 from the front.

[0032] On the substrate 111 of the display panel 110, various types of signal lines for driving the sub-pixels SP may be arranged.

[0033] The display device 100 according to the embodiment of the present disclosure may be a liquid crystal display device or the like, or may be a self-emitting display device in which the display panel 110 emits light by itself. When the display device 100 according to the embodiment of the present disclosure is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting element.

[0034] For example, the display device 100 according to the embodiment of the present disclosure may be an organic light emitting display device in which the light emitting element is an organic light emitting diode (OLED). As another example, the display device 100 according to the embodiment of the present disclosure may be an inorganic light emitting display device in which the light emitting element is an inorganic-based light emitting diode. As yet another example, the display device 100 according to the embodiment of the present disclosure may be a quantum dot display device in which the light emitting element is a quantum dot, which is a semiconductor crystal that emits light by itself.

[0035] The structures of the subpixels SP may differ depending on the type of the display device 100. For example, when the display device 100 is a self-emitting display device in which the subpixels SP emit light by themselves, each subpixel SP may include a light-emitting element that emits light by itself, one or more transistors, and one or more capacitors.

[0036] For example, various types of signal lines may include a plurality of data lines DL transmitting N data signals (also called data voltages or video signals) and a plurality of gate lines GL transmitting gate signals (also called scan signals).

[0037] For example, the data lines DL and the gate lines GL may cross each other. Each of the data lines DL may be arranged to extend in a first direction, and each of the gate lines GL may be arranged to extend in a second direction. Here, the first direction may be a column direction, and the second direction may be a row direction. Alternatively, the first direction may be a row direction, and the second direction may be a column direction. In the following, for convenience of explanation, it is taken as an example that each of the data lines DL is arranged in the column direction, and each of the gate lines GL is arranged in the row direction.

[0038] The data driving circuit 120 is a circuit for driving a plurality of data lines DL, and can output data signals to the plurality of data lines DL.

[0039] The data driving circuit 120 receives digital image data DATA from the display controller 140, and converts the received image data DATA into analog data signals and outputs them to a plurality of data lines DL.

[0040] For example, the data driving circuit 120 may be connected to the display panel 110 using a Tape Automated Bonding (TAB) method, connected to a bonding pad of the display panel 110 using a Chip On Glass (COG) or Chip On Panel (COP) method, or implemented and connected to the display panel 110 using a Chip On Film (COF) method.

[0041] The data driving circuit 120 may be connected to one side (e.g., the upper or lower side) of the display panel 110. Alternatively, the data driving circuit 120 may be connected to both sides (e.g., the upper and lower sides) of the display panel 110 or to two or more of the four sides of the display panel 110 depending on the driving method, panel design method, etc.

[0042] The data driving circuit 120 can be connected to the periphery of the display area DA of the display panel 110, but can also be disposed within the display area DA of the display panel 110 instead.

[0043] The gate driving circuit 130 is a circuit for driving a plurality of gate lines GL, and can output gate signals to the plurality of gate lines GL.

[0044] The gate drive circuit 130 is supplied with a first gate voltage corresponding to a turn-on level voltage and a second gate voltage corresponding to a turn-off level voltage, along with various gate drive control signals GCS, and can generate gate signals and supply the generated gate signals to multiple gate lines GL.

[0045] In the display device 100 according to the embodiment of the present disclosure, the gate driving circuit 130 can be of a gate in panel (GIP) type and can be built into the display panel 110. When the gate driving circuit 130 is of the gate in panel type, the gate driving circuit 130 can be formed on the substrate 111 of the display panel 110 during the manufacturing process of the display panel 110.

[0046] In the display device 100 according to the embodiment of the present disclosure, the gate driving circuit 130 can be disposed in the display area DA of the display panel 110. For example, the gate driving circuit 130 can be disposed in a first part of the display area DA (e.g., a left part or a right part of the display area DA). As another example, the gate driving circuit 130 can be disposed in a first part of the display area DA (e.g., a left part or a right part of the display area DA) and a second part of the display area DA (e.g., a right part or a left part of the display area DA).

[0047] In this disclosure, the gate driving circuit 130 built into the display panel 110 of the gate-in-panel type is referred to as a "gate-in-panel circuit."

[0048] The display controller 140 is a device for controlling the data driving circuit 120 and the gate driving circuit 130, and can control the driving timing for a plurality of data lines DL and the driving timing for a plurality of gate lines GL.

[0049] The display controller 140 may provide data drive control signals DCS to the data drive circuit 120 for controlling the data drive circuit 120 and provide gate drive control signals GCS to the gate drive circuit 130 for controlling the gate drive circuit 130.

[0050] The display controller 140 can receive input image data from a host system 150 and provide image data DATA to the data driving circuit 120 based on the input image data.

[0051] The display controller 140 may be implemented as a separate component from the data driving circuit 120, or may be integrated with the data driving circuit 120 and implemented as an integrated circuit.

[0052] The display controller 140 may be a timing controller used in a typical display technology, or may be a control device including a timing controller and capable of performing other control functions, or may be a control device different from the timing controller, or may be a circuit within the control device. The display controller 140 may be realized by various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0053] The display controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 via the printed circuit board, the flexible printed circuit, or the like.

[0054] The display controller 140 can transmit and receive signals to and from the data driving circuit 120 according to one or more predetermined interfaces. For example, the interfaces can include a Low Voltage Differential Signaling (LVDS) interface, an Embedded Clock Point-Point Interface (EPI) interface, a Serial Peripheral Interface (SPI), etc.

[0055] The display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or a pen, and detects the touch position, in order to provide not only an image display function but also a touch sensing function.

[0056] The touch sensing circuit may include a touch driving circuit that drives and senses a touch sensor to generate and output touch sensing data, and a touch controller that can sense the occurrence of a touch or detect a touch position using the touch sensing data.

[0057] The touch sensor may include a plurality of touch electrodes, and may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to a touch driving circuit.

[0058] The touch sensor may be present in the form of a touch panel outside the display panel 110, or may be present inside the display panel 110. When the touch sensor is present in the form of a touch panel outside the display panel 110, the touch sensor is called an external type. When the touch sensor is an external type, the touch panel and the display panel 110 may be manufactured separately and combined during an assembly process. The external type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0059] When the touch sensor is present inside the display panel 110, the touch sensor may be formed on a substrate together with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0060] The touch drive circuit can supply a touch drive signal to at least one of the multiple touch electrodes, and sense the at least one of the multiple touch electrodes to generate touch sensing data.

[0061] The touch sensing circuit can perform touch sensing using a self-capacitance sensing method or a mutual-capacitance sensing method.

[0062] When the touch sensing circuit performs touch sensing using a self-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger, a pen, etc.). According to the self-capacitance sensing method, each of the plurality of touch electrodes can serve as both a driving touch electrode and a sensing touch electrode. The touch driving circuit can drive all or a part of the plurality of touch electrodes and sense all or a part of the plurality of touch electrodes.

[0063] When the touch sensing circuit performs touch sensing using a mutual-capacitance sensing method, the touch sensing circuit can perform touch sensing based on the capacitance between the touch electrodes. According to the mutual-capacitance sensing method, the multiple touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0064] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented as separate devices or may be implemented as one device, and the touch driving circuit and the data driving circuit may be implemented as separate devices or may be implemented as one device.

[0065] The display device 100 may further include a power supply circuit that supplies various power sources to the display driving circuit and / or the touch sensing circuit.

[0066] The display device 100 according to an embodiment of the present disclosure may be a mobile terminal such as a smartphone or a tablet, or may be a monitor or television (TV) of various sizes, but is not limited thereto and may be displays of various types and sizes capable of displaying information or images.

[0067] The display device 100 according to the embodiment of the present disclosure may further include electronic devices such as a camera (image sensor), a detection sensor, etc. For example, the detection sensor may be a sensor that receives light such as infrared rays, ultrasonic waves, or ultraviolet rays to detect an object or a human body.

[0068] FIG. 2 shows a display panel 110 according to an embodiment of the present disclosure.

[0069] 2, the display panel 110 may include a substrate 111 disposed on a plurality of sub-pixels SP, and an encapsulation layer 200 on the substrate 111. Here, the encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation portion.

[0070] Referring to FIG. 2, when the display device 100 according to an embodiment of the present disclosure is a self-emitting display device, each of the multiple sub-pixels SP arranged on the substrate 111 may include a light-emitting element ED and a sub-pixel circuit SPC for driving the light-emitting element ED.

[0071] 2, the sub-pixel circuit SPC may include a plurality of pixel driving transistors and at least one capacitor for driving the light-emitting element ED. In the present disclosure, the sub-pixel circuit SPC may drive the light-emitting element ED by supplying a driving current to the light-emitting element ED at a predetermined timing. The light-emitting element ED may be driven by the driving current to emit light.

[0072] The pixel driving transistors may include a driving transistor DT for driving the light emitting element ED and a scan transistor ST which is turned on or off in response to a scan signal SC.

[0073] The driving transistor DT can supply a driving current to the light emitting element ED.

[0074] The scan transistor ST may be configured to control the electrical state of a corresponding node in the sub-pixel circuit SPC, or to control the state or operation of the drive transistor DT.

[0075] The at least one capacitor may include a storage capacitor Cst for maintaining a constant voltage during a frame.

[0076] To drive the sub-pixels SP, a data signal VDATA, which is an image signal, a scan signal SC, which is a gate signal, etc. may be applied to the sub-pixels SP. In addition, to drive the sub-pixels SP, common pixel driving voltages including a first common driving voltage VDD and a second common driving voltage VSS may be applied to the sub-pixels SP.

[0077] The light-emitting element ED can include an anode AND, a light-emitting element intermediate layer EL, and a cathode CAT. The light-emitting element intermediate layer EL can be disposed between the anode AND and the cathode CAT.

[0078] When the light-emitting element ED is an organic light-emitting element, the light-emitting element intermediate layer EL may include an emitting layer EML, a first common intermediate layer COM1 between the anode AND and the emitting layer EML, and a second common intermediate layer COM2 between the emitting layer EML and the cathode. The emitting layer EML may be disposed for each subpixel SP. In contrast, the first common intermediate layer COM1 and the second common intermediate layer COM2 may be disposed in common across a plurality of subpixels SP. The emitting layer EML may be disposed for each emitting region, and the first common intermediate layer COM1 and the second common intermediate layer COM2 may be disposed in common across a plurality of emitting regions and non-emitting regions. The first common intermediate layer COM1 and the second common intermediate layer COM2 are collectively referred to as a common intermediate layer EL_COM.

[0079] For example, the first common intermediate layer COM1 can include a hole injection layer (HIL, Hole Injection Layer) and a hole transport layer (HTL, Hole Transfer Layer), etc. The second common intermediate layer COM2 can include an electron transport layer (ETL, Electron Transfer Layer) and an electron injection layer (EIL, Electron Injection Layer), etc. The hole injection layer can inject holes from the anode AND to the hole transport layer, the hole transport layer can transport the holes to the light emitting layer EML, the electron injection layer can inject electrons from the cathode CAT to the electron transport layer, and the electron transport layer can transport the electrons to the light emitting layer EML.

[0080] For example, the cathode CAT can be electrically connected to a second common driving voltage line VSSL. A second common driving voltage VSS, which is a type of common pixel driving voltage, can be applied to the cathode CAT via the second common driving voltage line VSSL. The anode AND can be electrically connected to a first node N1 of the driving transistor DT of each subpixel SP. In the present disclosure, the second common driving voltage VSS can also be described as a base voltage VSS, and the second common driving voltage line VSSL can also be described as a base voltage line VSSL.

[0081] For example, the anode AND may be a pixel electrode disposed in each subpixel SP, and the cathode CAT may be a common electrode disposed in common to a plurality of subpixels SP. As another example, the cathode CAT may be a pixel electrode disposed in each subpixel SP, and the anode AND may be a common electrode disposed in common to a plurality of subpixels SP. In the following, for convenience of explanation, it is assumed that the anode AND is a pixel electrode and the cathode CAT is a common electrode.

[0082] Each light-emitting element ED may be composed of an overlapping portion of an anode AND, a light-emitting element intermediate layer EL, and a cathode CAT. A predetermined light-emitting region may be formed by each light-emitting element ED. For example, the light-emitting region of each light-emitting element ED may include an overlapping region of an anode AND, a light-emitting element intermediate layer EL, and a cathode CAT.

[0083] For example, the light emitting device ED may be an organic light emitting diode (OLED), an inorganic-based light emitting diode (LED), a quantum dot light emitting device, etc. For example, when the light emitting device ED is an organic light emitting diode (OLED), the light emitting device intermediate layer EL of the light emitting device ED may include a light emitting device intermediate layer EL including an organic material.

[0084] The driving transistor DT may be a driving transistor for supplying a driving current to the light emitting element ED. The driving transistor DT may be connected between a first common driving voltage line VDDL and the light emitting element ED.

[0085] The driving transistor DT may include a first node N1 electrically connected to the light emitting element ED, a second node N2 to which a data signal VDATA may be applied, and a third node N3 to which a driving voltage VDD is applied from a driving voltage line DVL.

[0086] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. In the following, for convenience of explanation, in the driving transistor DT, the second node N2 is a gate node, the first node N1 may be a source node, and the third node N3 is a drain node.

[0087] The scan transistor ST included in the sub-pixel circuit SPC illustrated in FIG. 2 may be a switching transistor for transmitting a data signal VDATA, which is an image signal, to the second node N2, which is the gate node of the driving transistor DT.

[0088] The scan transistor ST is controlled to be turned on and off by a scan signal SC, which is a gate signal applied via a scan line SCL, which is a type of gate line GL, and can control an electrical connection between the second node N2 of the driving transistor DT and the data line DL. A drain electrode or a source electrode of the scan transistor ST can be electrically connected to the data line DL, a source electrode or a drain electrode of the scan transistor ST can be electrically connected to the second node N2 of the driving transistor DT, and a gate electrode of the scan transistor ST can be electrically connected to the scan line SCL.

[0089] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst may include a first capacitor electrode electrically connected to or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to or corresponding to the second node N2 of the driving transistor DT.

[0090] The storage capacitor Cst may be an external capacitor intentionally designed outside the driving transistor DT, rather than a parasitic capacitor (e.g., Cgs, Cgd), which is an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor DT.

[0091] Each of the drive transistor DT and the scan transistor ST may be an n-type transistor or a p-type transistor.

[0092] The display panel 110 may have a top emission structure or a bottom emission structure.

[0093] If the display panel 110 has a top emission structure, at least a portion of the sub-pixel circuit SPC may overlap at least a portion of the light-emitting element ED in the vertical direction. Alternatively, if the display panel 110 has a bottom emission structure, the sub-pixel circuit SPC may not overlap the light-emitting element ED in the vertical direction.

[0094] The subpixel circuit SPC may have a 2T (Transistor) 1c (Capacitor) structure including two transistors DT, ST and one capacitor Cst, as shown in FIG. 2, and may further include one or more transistors or one or more capacitors in some cases.

[0095] For example, the sub-pixel circuit SPC may have an 8T1C structure including eight transistors and one capacitor. As another example, the sub-pixel circuit SPC may have a 6T2C structure including six transistors and two capacitors. As yet another example, the sub-pixel circuit SPC may have a 7T1C structure including seven transistors and one capacitor.

[0096] Depending on the structure of the sub-pixel circuit SPC, the type and number of gate lines for supplying gate signals to the sub-pixels SP may be different.

[0097] Furthermore, the type and number of common pixel driving voltages supplied to the sub-pixels SP may vary depending on the structure of the sub-pixel circuits SPC.

[0098] Since the circuit elements (particularly, the light emitting element ED realized by an organic light emitting diode OLED including an organic material) in each subpixel SP are vulnerable to external moisture and oxygen, an encapsulation layer 200 for preventing external moisture and oxygen from penetrating into the circuit elements (particularly, the light emitting element ED) may be disposed in the display panel 110. The encapsulation layer 200 may be configured in various forms to prevent the light emitting element ED from coming into contact with moisture and oxygen.

[0099] Referring to FIG. 2, the display device 100 according to an embodiment of the present disclosure may further include a touch sensor layer TSL including a plurality of sensor electrodes for sensing a user's touch, and a touch sensing circuit 210 configured to sense the plurality of sensor electrodes to determine the presence or absence of a touch or touch coordinates.

[0100] The touch sensor layer TSL can be integrated into the display panel 110. For example, the touch sensor layer TSL can be disposed on the encapsulation layer 200 in the display panel 110.

[0101] The display panel 110 may not only include a touch sensor layer TSL, but also include a plurality of touch pads electrically connected to the touch sensing circuit 210, and a plurality of touch routing wirings TL for electrically connecting a plurality of sensor electrodes included in the touch sensor layer TSL and a plurality of touch pads connected to the touch sensing circuit 210.

[0102] Meanwhile, the display device 100 according to the embodiment of the present disclosure may have an extremely narrow bezel structure in which the non-display area NDA of the display panel 110 is very small or almost non-existent. The extremely narrow bezel structure of the display panel 110 of the display device 100 according to the embodiment of the present disclosure will be described below.

[0103] FIG. 3 shows a substrate 111 of a display panel 110 according to an embodiment of the present disclosure.

[0104] Referring to FIG. 3, a substrate 111 of a display panel 110 according to an embodiment of the present disclosure may include a display area DA where an image may be displayed, and a non-display area NDA where no image is displayed.

[0105] 3, the non-display area NDA may include a first non-display area NDA1 located in a first direction from the display area DA, a second non-display area NDA2 located in a second direction from the display area DA, a third non-display area NDA3 located in an opposite direction from the display area DA to the first direction, and a fourth non-display area NDA4 located in an opposite direction from the display area DA to the second direction. For example, the first direction may be a column direction (Y-axis direction), and the second direction intersecting the first direction may be a row direction (X-axis direction).

[0106] Referring to FIG. 3, the first non-display area NDA1 may include a pad area PA in which a plurality of pads are arranged.

[0107] A plurality of pads to which driving circuits are electrically connected may be disposed in the pad area PA. A plurality of driving circuits or printed circuit boards may be electrically connected. For example, the plurality of pads may include a plurality of display pads and a plurality of touch pads. A plurality of data lines, a first common driving voltage line VDDL, a second common driving voltage line VSSL, etc. may be electrically connected to the plurality of display pads. A plurality of touch routing wirings TL may be electrically connected to the plurality of touch pads.

[0108] 3, the first non-display area NDA1 may further include a bending area BA. In this case, the substrate 111 may be a flexible substrate. In some cases, the first non-display area NDA1 may not include the bending area BA.

[0109] 3, the display panel 110 may further include a ground wiring disposed in the non-display area NDA of the substrate 111. The ground wiring may be disposed from a certain portion of the pad area PA to another portion of the pad area PA via the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4.

[0110] 3, in the display panel 110 according to the embodiment of the present disclosure, the encapsulation layer 200 may have a structure in which an inorganic film and an organic film are stacked together, and in this case, the edge of the encapsulation layer 200 may be regarded as the edge of the organic film.

[0111] Referring to FIG. 3, the display panel 110 according to the embodiment of the present disclosure may include a stopper (STP) as an organic layer overflow prevention structure for preventing overflow of an organic layer included in the encapsulation layer 200.

[0112] Referring to FIG. 3, in the display panel 110 according to the embodiment of the present disclosure, the stoppers STP are disposed in the non-display area NDA, and may be disposed in a ring shape surrounding the periphery of the organic film PCL.

[0113] Referring to FIG. 3, the stopper STP may be located between the display area DA and the pad area PA.

[0114] 3, in the display panel 110 according to the embodiment of the present disclosure, the stopper STP may be disposed in the non-display area NDA. In this manner, although the stopper STP is disposed in the non-display area NDA, the size of the non-display area NDA is not increased by the stopper STP.

[0115] In the display panel 110 according to the embodiment of the present disclosure, the stopper STP may have a structure that prevents the overflow of the organic film, but rather reduces the non-display area NDA.

[0116] Hereinafter, the stopper STP, which is an organic film overflow prevention structure capable of preventing overflow of the organic film included in the encapsulation layer 200 and is one of extremely narrow bezel structures capable of reducing the bezel size, will be described in more detail.

[0117] Fig. 4 is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure. However, Fig. 4 is a cross-sectional view of a region 320 including the second non-display area NDA2 in Fig. 3. In Fig. 3, the vertical structures of the region 330 including the third non-display area NDA3 and the region 1510 including the fourth non-display area NDA4 may be the same as the vertical structure of the region 320 including the second non-display area NDA2.

[0118] Referring to FIG. 4, a display panel 110 according to an embodiment of the present disclosure may include a substrate 111, an insulating film stack INS on the substrate 111, a plurality of light-emitting elements ED1, ED2, and ED3 on the insulating film stack INS, an organic film PCL on the plurality of light-emitting elements ED1, ED2, and ED3, and a stopper STP arranged on the outer periphery of the organic film PCL.

[0119] The substrate 111 may include a display area DA and a non-display area NDA, and the non-display area NDA may include a second non-display area NDA2 located in a second direction from the display area DA.

[0120] The insulating film stack INS may include a plurality of insulating films located between the substrate 111 and a plurality of light emitting elements ED1, ED2, and ED3.

[0121] The insulating film stack INS may be located on the substrate 111 and may have an outer side SIDE_INS from the non-display area NDA. The insulating film stack INS may include multiple insulating films.

[0122] The insulating film stack INS may include a plurality of insulating films necessary to form a transistor. The insulating film stack INS may include an organic insulating film stack including at least one organic insulating film and an inorganic insulating film including at least one inorganic insulating film. For example, the organic insulating film stack may include at least one planarization layer, and the inorganic insulating film stack may include at least one buffer layer, at least one gate insulating film, or at least one interlayer insulating film, etc.

[0123] In order to form multiple light-emitting elements ED1, ED2, and ED3 on the insulating film stack INS, the display panel 110 may include a bank BK having multiple openings and located on the insulating film stack INS as a subpixel defining film for dividing multiple light-emitting areas EA1, EA2, and EA3, multiple anodes AND1, AND2, and AND3 located on the insulating film stack INS and overlapping with the multiple openings of the bank BK, multiple light-emitting layers EML1, EML2, and EML3 located on the multiple anodes AND1, AND2, and AND3, and a cathode CAT located on the multiple light-emitting layers EML1, EML2, and EML3 and arranged to extend from the display area DA to a portion of the non-display area NDA.

[0124] A plurality of anodes AND1, AND2, and AND3, a plurality of light emitting layers EML1, EML2, and EML3, and a cathode CAT are overlapped to form a plurality of light emitting elements ED1, ED2, and ED3.

[0125] Referring to FIG. 4, the insulating film stack INS may include multiple insulating films disposed between a substrate 111 and multiple anodes AND1, AND2, AND3.

[0126] Referring to FIG. 4, the display panel 110 according to the embodiment of the present disclosure may include a stopper STP, which is one of the extremely narrow bezel structures, as well as an organic film overflow prevention structure.

[0127] 4, the stopper STP may be located on the insulating film stack INS, may be disposed in the non-display area NDA, and may be located further outward than the organic film PCL. The cathode CAT may be located on the insulating film stack INS, may extend from the display area DA to a portion of the non-display area NDA, and may overlap at least a portion of the top surface of the stopper STP.

[0128] In the display panel 110 according to the embodiment of the present disclosure, the stopper STP may be disposed further outward than the third light emitting element ED3, which is the outermost light emitting element ED, among the plurality of light emitting elements ED1, ED2, ED3. The stopper STP may be disposed on the outer surface of the third light emitting element ED3, which is the outermost light emitting element ED, among the plurality of light emitting elements ED1, ED2, ED3. The stopper STP may be disposed further outward than the bank BK.

[0129] The stopper STP may comprise an organic substance.

[0130] The stopper STP may have a thickness greater than that of the anode AND3 of the third light emitting element ED3, which is the outermost light emitting element ED. For example, the stopper STP may have a thickness greater than the sum of the thicknesses of the anode AND3, the light emitting element intermediate layer EL, and the cathode CAT of the third light emitting element ED3, which is the outermost light emitting element ED. The light emitting element intermediate layer EL of the third light emitting element ED3, which is the outermost light emitting element ED, may include a first common intermediate layer COM1, a third light emitting layer EML3, and a second common intermediate layer COM2.

[0131] For example, the highest upper surface of the stopper STP may be located higher than the upper surfaces of the cathodes CAT in the light emitting areas EA1, EA2, and EA3, so that the cathodes CAT may be disposed along the inner side surfaces of the stoppers STP and extend upward to the tops of the stoppers STP.

[0132] Referring to FIG. 4, for example, the multiple light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1 located in the first light-emitting area EA1, a second light-emitting element ED2 located in the second light-emitting area EA2, and a third light-emitting element ED3 located in the third light-emitting area EA3.

[0133] The first light-emitting element ED1 may include a first anode AND1, a first light-emitting element intermediate layer EL and a cathode CAT, and the first light-emitting element intermediate layer EL of the first light-emitting element ED1 may include a first common intermediate layer COM1, a first light-emitting layer EML1 and a second common intermediate layer COM2.

[0134] The second light-emitting element ED2 may include a second anode AND2, a second light-emitting element intermediate layer EL, and a cathode CAT, and the second light-emitting element intermediate layer EL of the second light-emitting element ED2 may include a first common intermediate layer COM1, a second light-emitting layer EML2, and a second common intermediate layer COM2.

[0135] The third light-emitting element ED3 may include a third anode AND3, a third light-emitting element intermediate layer EL and a cathode CAT, and the third light-emitting element intermediate layer EL of the third light-emitting element ED3 may include a first common intermediate layer COM1, a third light-emitting layer EML3 and a second common intermediate layer COM2.

[0136] The first anode AND1, the second anode AND2, and the third anode AND3 may be disposed in the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3, respectively.

[0137] The first light emitting layer EML1, the second light emitting layer EML2, and the third light emitting layer EML3 may be disposed in the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3, respectively.

[0138] The first common intermediate layer COM1, the second common intermediate layer COM2, and the cathode CAT can be disposed over the entire display area DA and can extend from the display area DA to at least a part of the non-display area NDA. In this specification, the first common intermediate layer COM1 and the second common intermediate layer COM2 are collectively referred to as the common intermediate layer EL_COM.

[0139] Referring to FIG. 4, a display panel 110 according to an embodiment of the present disclosure may include a first inorganic film PAS1, an organic film PCL, and a second inorganic film PAS2.

[0140] Referring to FIG. 4, the first inorganic film PAS1 is located on the cathode CAT and can be arranged to extend from the display area DA to the non-display area NDA including the second non-display area NDA2.

[0141] Referring to FIG. 4, the organic film PCL is located on a portion of the first inorganic film PAS1 and may have an outer inclined surface SLP_PCL.

[0142] Referring to FIG. 4, the second inorganic film PAS2 is located on the organic film PCL and may be arranged to extend from the display area DA to the non-display area NDA, and may be arranged to extend along the outer inclined surface SLP_PCL of the organic film PCL.

[0143] The first inorganic film PAS1, the organic film PCL, and the second inorganic film PAS2 may be layers that constitute the sealing layer 200.

[0144] The stopper STP is located on the insulating film stack INS, and can be disposed further outward than the organic film PCL.

[0145] The first inorganic film PAS1 may extend along the top and outside of the stopper STP to the outer side SIDE_INS of the insulating film stack INS.

[0146] The second inorganic film PAS2 may be located on the first inorganic film PAS1 extending along the outer edge of the outer inclined surface SLP_PCL of the organic film PCL and extending along the upper and outer sides of the stoppers STP to the outer surfaces SIDE_INS of the insulating film stack INS.

[0147] The bank BK is located on the insulating film stack INS and may have first to third openings. The first to third openings may correspond to the first to third light emitting regions EA1, EA2, and EA3.

[0148] The first to third anodes AND1, AND2, and AND3 are located on the insulating film stack INS, and may overlap the first to third openings of the bank BK, respectively.

[0149] The first common intermediate layer COM1 can be disposed in common on the first to third anodes AND1, AND2, and AND3, and can also be disposed on the bank BK.

[0150] The first, second, and third light emitting layers EML1, EML2, and EML3 are located on the first common intermediate layer COM1 and may overlap the first, second, and third anodes AND1, AND2, and AND3. The first, second, and third light emitting layers EML1, EML2, and EML3 may correspond to the first, second, and third light emitting regions EA1, EA2, and EA3.

[0151] The second common intermediate layer COM2 can be disposed commonly on the first to third light emitting layers EML1, EML2, EML3, and can also be disposed on the bank BK.

[0152] The common intermediate layer EL_COM including the first common intermediate layer COM1 and the second common intermediate layer COM2 may be present on the bank BK and may be disposed throughout the display area DA. The common intermediate layer EL_COM including the first common intermediate layer COM1 and the second common intermediate layer COM2 may include an organic material.

[0153] The cathode CAT may be located on the second common intermediate layer COM2.

[0154] Referring to FIG. 4, the common intermediate layer EL_COM and the cathode CAT can extend to the top of the stopper STP so as to overlap at least a portion of the stopper STP.

[0155] For example, the common intermediate layer EL_COM and the cathode CAT can extend to the upper and outer surfaces of the stopper STP. If the common intermediate layer EL_COM and the cathode CAT extend further, the common intermediate layer EL_COM and the cathode CAT can extend through the upper and outer surfaces of the stopper STP to the outer surface SIDE_INS of the insulating film stack INS.

[0156] 4, the display panel 110 may further include a capping layer CPL disposed between the cathode CAT and the first inorganic film PAS1 and extending from the display area DA to the non-display area NDA. The capping layer CPL may extend to an outer side SIDE_INS of the insulating film stack INS along the top and outer sides of the stoppers STP.

[0157] Referring to FIG. 4, a common intermediate layer EL_COM, a cathode CAT, and a capping layer CPL may be disposed on an outer surface SIDE_INS of the insulating film stack INS.

[0158] As described above, the stopper STP is disposed on the outer surface of the third light-emitting element ED3, which is the outermost light-emitting element ED, among the plurality of light-emitting elements ED1, ED2, and ED3 corresponding to the plurality of sub-pixels SP, and may have a thickness greater than that of the third anode AND3 of the third light-emitting element ED3, which is the outermost light-emitting element ED.

[0159] 4, the lower surface of the stopper STP may have a larger area than the upper surface of the stopper STP. The stopper STP may include a first stopper on the insulating film stack INS and a second stopper on the first stopper. The first stopper may include the same material as the bank BK, and the second stopper may include the same material as the spacer on the bank BK. The bank BK and the spacer may include an organic material.

[0160] Each of the first inorganic film PAS1 and the second inorganic film PAS2 can be formed from silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium oxide.

[0161] For example, the organic film PCL can be made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. The organic film PCL can be applied in liquid form through an inkjet process and then cured.

[0162] FIG. 5 is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure, and FIG. 6 is a cross-sectional view of an outer region of the display panel 110 according to an embodiment of the present disclosure, showing an enlarged view of an area where a stopper STP is located.

[0163] 5 is a cross-sectional view of an area 320 including the second non-display area NDA2 and the display area DA in the vicinity thereof, similar to the cross-sectional view of FIG.

[0164] The cross-sectional view of Fig. 5 differs from the cross-sectional view of Fig. 4 only in the shape and structure of the stopper STP and the patterning shapes and positions of the common intermediate layer EL_COM and the cathode CAT, and the rest are all the same. Therefore, the following description will focus on the points that differ from the cross-sectional view of Fig. 4.

[0165] 5 and 6, the outer surface of the stopper STP may be an etched surface, and therefore the inner and outer surfaces of the stopper STP may have different shapes and inclinations.

[0166] 5 and 6, the outer surface OS of the stopper STP may have an inclination angle close to a vertical angle, and the inner surface IS of the stopper STP may have an inclination angle that is gentler than that of the outer surface OS of the stopper STP. That is, the outer surface OS of the stopper STP may have an inclination angle that is steeper than that of the inner surface IS of the stopper STP.

[0167] 5 and 6, the stopper STP may include a first stopper STP on the insulating film stack INS and a second stopper STP on the first stopper STP.

[0168] The first stopper STP may include the same material as the bank BK, and the second stopper STP may include the same material as the spacer (SPCR in FIG. 16) located on the bank BK. That is, the first stopper STP may be located in the same material layer as the bank BK, and the second stopper STP may be located in the same material layer as the spacer. The bank BK and the spacer may include an organic material.

[0169] 5 and 6, the end of the common intermediate layer EL_COM and the end of the cathode CAT may be located on the stopper STP. That is, the common intermediate layer EL_COM and the cathode CAT may end on the top of the stopper STP and may not extend to the outer surface of the stopper STP.

[0170] Referring to Figures 5 and 6, the common intermediate layer EL_COM and the cathode CAT terminate at the top of the stopper STP, but the capping layer CPL, the first inorganic film PAS1 and the second inorganic film PAS2 do not terminate at the top of the stopper STP but can extend through the outer surface of the stopper STP to the outer surface SIDE_INS of the insulating film stack INS.

[0171] 5 and 6, the second stopper STP2 and the common intermediate layer EL_COM may include an organic material, and the cathode CAT may include an inorganic material. Thus, when the second stopper STP2, the common intermediate layer EL_COM, and the cathode CAT are etched through an etching process (e.g., a dry etching process) during the manufacture of the panel, the etching characteristics of the second stopper STP2 and the common intermediate layer EL_COM may be different from the etching characteristics of the cathode CAT. Thus, the end of the cathode CAT may protrude further outward than the outer surface OS of the second stopper STP and the end of the common intermediate layer EL_COM.

[0172] 5 and 6, an end of the common intermediate layer EL_COM may be located on the insulating film stack INS. The end of the common intermediate layer EL_COM may overlap the insulating film stack INS.

[0173] Referring to FIG. 5, the stopper STP may include a cliff portion STP_CLF extending from the top to a point where the inclination of the outer surface becomes gentler than a certain level or where there is a step.

[0174] Referring to FIG. 5, a value H2 obtained by combining the height Hc of the cliff portion STP_CLF of the stopper STP and the height H1 of the common intermediate layer EL_COM may be greater than the sum of the thicknesses of the first inorganic film PAS1 and the second inorganic film PAS2.

[0175] Referring to FIG. 5, a value H2 obtained by combining the height Hc of the cliff portion STP_CLF of the stopper STP and the height H1 of the common intermediate layer EL_COM may be greater than the sum of the thicknesses of the first inorganic film PAS1 and the second inorganic film PAS2.

[0176] For example, the combined value H2 of the height Hc of the cliff portion STP_CLF of the stopper STP and the height H1 of the common intermediate layer EL_COM may be 1.3 times or more the combined value of the thickness T1 of the first inorganic film PAS1 and the thickness T1 of the second inorganic film PAS2 (H2≧(T1+T2)×1.3).

[0177] Referring to FIG. 5, the outer surface of the stopper STP may be etched so that the width of the bottom surface of the stopper STP is greater than the width of the top surface of the stopper STP.

[0178] 5 and 6, the inclination of the outer surface of the cliff portion STP_CLF of the stopper STP may be approximately vertical. The height Hc of the cliff portion STP_CLF of the stopper STP may be adjusted according to the dry etching time. The longer the dry etching time, the higher the height Hc of the cliff portion STP_CLF of the stopper STP may be.

[0179] Referring to FIG. 6, a lower end of the outer surface of the first stopper STP may protrude further outward than an upper end of the outer surface of the second stopper STP.

[0180] For example, when the dry etching time is set shorter than the first time, only a part of the outer surface of the second stopper STP2 may be etched, and the outer surface of the first stopper STP1 may not be etched. In this case, the cliff height Hc of the stopper STP may be a part of the thickness of the second stopper STP2.

[0181] As another example, when the dry etching time is set to the first time, the outer surface of the second stopper STP2 may be entirely etched, and the outer surface of the first stopper STP1 may not be etched. In this case, the cliff height Hc of the stopper STP may be the thickness of the second stopper STP2.

[0182] As yet another example, when the dry etching time is set to a second time longer than the first time, both the outer surface of the second stopper STP2 and the outer surface of the first stopper STP1 may be etched. In this case, the cliff height Hc of the stopper STP may be a value obtained by adding the thickness of the second stopper STP2 and the thickness of the first stopper STP1.

[0183] As yet another example, when the dry etching time is set to be longer than the first time and shorter than the second time, the entire outer surface of the second stopper STP2 may be etched, and only a portion of the outer surface of the first stopper STP1 may be etched, as shown in Fig. 6. In this case, the height Hc of the cliff of the stopper STP may be a value obtained by adding the thickness of the second stopper STP2 and the depth to which the first stopper STP1 is etched, as shown in Fig. 6. Also, the outer surface of the first stopper STP may protrude further outward than the outer surface of the second stopper STP.

[0184] As yet another example, when the dry etching time is set to be longer than the second time, both the outer surface of the second stopper STP2 and the outer surface of the first stopper STP1 may be etched, and a part of the upper layer of the insulating film stack INS may also be etched. In this case, the height Hc of the cliff of the stopper STP may be a value obtained by combining the thickness of the second stopper STP2, the thickness of the first stopper STP1, and the depth to which the insulating film stack INS is etched.

[0185] Referring to FIG. 6, the outer surface of the stopper STP may be etched so that the width W1 of the bottom surface of the first stopper STP is larger than the width W2 of the top surface of the second stopper STP.

[0186] FIG. 7 is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure.

[0187] Fig. 7 is a cross-sectional view of an area 310 including the first non-display area NDA1 and the display area DA in the vicinity thereof in Fig. 3. In the following explanation, the same contents as in the cross-sectional structure of Fig. 5 will not be described, and differences from the cross-sectional structure of Fig. 5 will be mainly explained.

[0188] Referring to FIG. 7, the first non-display area NDA1 may include a bending area BA and a pad area PA.

[0189] The bending area BA may include a bending film 730 disposed on the substrate 111. The bending film 730 may be a bending organic film including an organic material.

[0190] The pad area PA may include a display pad DP to which a circuit for driving the display (e.g., a data driving circuit, etc.) or a printed circuit board, etc. is electrically connected. The display pad DP may be electrically connected to display signal wiring (e.g., a data line, a first common driving voltage line, a second common driving voltage line, etc.) arranged in the display area DA.

[0191] The display panel 110 may have display connection wiring 710 that electrically connects display signal wiring (e.g., data lines, first common driving voltage lines, second common driving voltage lines, etc.) arranged in the display area DA to the display pads DP.

[0192] The display connection wiring 710 can pass through the bending region BA and extend to the pad region PA. Therefore, while the display connection wiring 710 passes through the bending region BA, the display connection wiring 710 may pass under the bending film 730 in the bending region BA.

[0193] The display connection wiring 710 may overlap the bending film 730 in the bending area BA. An insulating film 720 may be disposed between the display connection wiring 710 and the bending film 730. The insulating film 720 may be a layer extending from the display area DA, or may be a layer included in the insulating film stack INS.

[0194] The display connection wiring 710 may include the same material as the source-drain electrodes of the transistors (eg, DT, ST) disposed in the display area DA.

[0195] Alternatively, the display connection wiring 710 may be composed of a first touch connection pattern including the same material as the source-drain electrodes of the transistors (e.g., DT, ST) arranged in the display area DA, and a second touch connection pattern including the same material as the gate electrodes or gate lines GL of the transistors (e.g., DT, ST).

[0196] The bending film 730 may be disposed in the bending region BA to cover an upper portion of the display connection wiring 710. The bending film 730 may play a role in preventing the display connection wiring 710 from being exposed to the outside in the bending region BA where the substrate 111 is bent, and in protecting the display connection wiring 710. In addition, the bending film 730 may be provided with an open hole that exposes the upper portion. That is, the open hole may be formed by removing an inorganic film (e.g., a first inorganic film PAS1, a second inorganic film PAS2, etc.) that may be disposed on the bending film 730. When an inorganic film is disposed on the bending film 730, a crack may occur in the inorganic film when the bending region BA is bent, and moisture may penetrate the inorganic film in which the crack occurs, so the inorganic film provided on the bending film 730 is removed.

[0197] The pattern protection film 731 is disposed to wrap the end of the display connection line 710, thereby protecting the end of the touch connection pattern 1200 disposed on the edge of the first non-display area NDA1.

[0198] The bending film 730 and the pattern protection film 731 are disposed in the same layer as the planarization film included in the insulating film stack INS, and can be made of the same material.

[0199] For example, the bending film 730 and the pattern protection film 731 can be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0200] FIG. 8 is another cross-sectional view of a display panel 110 according to an embodiment of the present disclosure.

[0201] Referring to FIG. 8, the display panel 110 according to the embodiment of the present disclosure may further include a patterning organic material MPL disposed on the outer periphery of the stopper STP.

[0202] At the outer side SIDE_INS of the insulating film stack INS, a patterning organic MPL can be disposed between the outer side SIDE_INS of the insulating film stack INS and the capping layer CPL.

[0203] Patterning organics MPL can also be disposed on the substrate 111 .

[0204] As shown in FIGS. 5 to 7, the cathode CAT exists as a display area DA only up to the top of the stopper STP, and does not extend beyond the outer surface of the stopper STP.

[0205] The reason why the cathode CAT is arranged in this manner is related to the cathode patterning process method.

[0206] The cathode patterning process is carried out as follows.

[0207] A patterning organic material MPL is deposited on the region where the cathode CAT is not disposed (i.e., the outer region of the stopper STP), and a cathode material is deposited thereon. For example, the patterning organic material MPL may include an organic material. The cathode electrode material may include a magnesium-silver (Mg-Ag) alloy.

[0208] At this time, the cathode material can be deposited only in the area without the patterned organic material MPL, so that the cathode CAT may be formed only in the desired area (the area without the patterned organic material MPL).

[0209] The patterning organic MPL may have low adhesion to the metal due to low surface energy of the material itself or high interfacial energy between the material and the cathode material (metal). This may significantly increase the probability of desorption of the cathode material (metal) on the surface of the patterning organic MPL during deposition of the cathode material (metal). This prevents nucleation of the cathode material (metal). Therefore, the cathode material can be deposited only in areas without the patterning organic MPL.

[0210] Meanwhile, as shown in FIGS. 5 and 7, the display panel 110 after the manufacturing process may be in a state where the metal patterning layer MPL is completely removed.

[0211] Alternatively, as shown in FIG. 8, the display panel 110 after the manufacturing process may have the patterned organic material MPL entirely or partially remaining.

[0212] As described above, in the display panel 110 according to the embodiment of the present disclosure, as shown in Figs. 5 to 8, the stopper STP, which is an organic film overflow prevention structure, is not disposed on the side of the insulating film stack INS, but is disposed on the insulating film stack INS. This makes it possible to prevent the bezel from increasing due to the stopper STP, which is an organic film overflow prevention structure. That is, in the display panel 110 according to the embodiment of the present disclosure, the stopper STP may be not only an organic film overflow prevention structure, but also any of an extremely narrow bezel structure.

[0213] Meanwhile, in the case of the display panel 110 of Fig. 5, the outer surface of the stopper STP is not etched, and the common intermediate layer EL_COM and the cathode CAT are disposed extending to the outer periphery of the stopper STP. When the common intermediate layer EL_COM, which is an organic layer included in the intermediate layer EL of the light-emitting element, is disposed extending to the outer periphery of the stopper STP, the characteristics of the common intermediate layer EL_COM in the outer region of the stopper STP may change due to external factors. Therefore, when the common intermediate layer EL_COM is disposed extending to the outer periphery of the stopper STP, there is a slight possibility that the reliability of the light-emitting element ED may be reduced.

[0214] As shown in FIG. 5, the outer surface of the stopper STP is not etched, and the common intermediate layer EL_COM and the cathode CAT are disposed to extend to the outer periphery of the stopper STP, so that the bezel can be increased to some extent.

[0215] In contrast, in the case of the display panel 110 of FIGS. 6 to 8, the outer surface of the stopper STP is etched, and the common intermediate layer EL_COM and the cathode CAT do not extend to the outer periphery of the stopper STP.

[0216] 6 to 8, the reliability of the light-emitting element ED can be relatively high and the bezel can be smaller than that of the display panel 110 of FIG.

[0217] The stopper STP has been described above as an extremely narrow bezel structure. In the following, an internal touch routing structure, which is another extremely narrow bezel structure, will be described with reference to FIGS.

[0218] FIG. 9 is a plan view illustrating a touch sensor included in a display panel 110 according to an embodiment of the present disclosure.

[0219] Referring to FIG. 9, a substrate 111 of a display panel 110 according to an embodiment of the present disclosure may include a display area DA in which a plurality of sub-pixels SP are arranged, and a non-display area NDA which is an outer area of ​​the display area DA.

[0220] 9, the non-display area NDA may include a first non-display area NDA1 located in a first direction from the display area DA, a second non-display area NDA2 located in a second direction from the display area DA, a third non-display area NDA3 located in an opposite direction from the display area DA in the first direction, and a fourth non-display area NDA4 located in an opposite direction from the display area DA in the second direction. The first non-display area NDA1 may include a pad area PA where a plurality of touch pads TP are arranged.

[0221] 9, the display panel 110 according to the embodiment of the present disclosure may include a touch sensor layer TSL disposed on the second inorganic film PAS2 and including a plurality of sensor electrodes SE disposed in the display area DA. The display panel 110 according to the embodiment of the present disclosure may further include a plurality of touch routing lines TL for electrically connecting the plurality of sensor electrodes SE and the plurality of touch pads TP. The plurality of touch routing lines TL may also be considered as a component included in the touch sensor.

[0222] Referring to FIG. 9, the plurality of sensor electrodes SE may include a first sensor electrode SE1, a second sensor electrode SE2, a third sensor electrode SE3, a fourth sensor electrode SE4, and a fifth sensor electrode SE5.

[0223] Each of the first sensor electrode SE1, the second sensor electrode SE2, the third sensor electrode SE3, and the fifth sensor electrode SE5 may extend in a second direction, which may correspond to a direction in which the gate line GL extends.

[0224] The fourth sensor electrode SE4 may extend in a first direction, which may correspond to the direction in which the data line DL extends.

[0225] Referring to FIG. 9, the multiple touch routing wirings TL may include a first touch routing wiring TL1 for electrically connecting the first sensor electrode SE1 to a first touch pad TP1 arranged in the pad area PA, a second touch routing wiring TL2 for electrically connecting the second sensor electrode SE2 to a second touch pad TP2 arranged in the pad area PA, a third touch routing wiring TL3 for electrically connecting the third sensor electrode SE3 to a third touch pad TP3 arranged in the pad area PA, a fourth touch routing wiring TL4 for electrically connecting the fourth sensor electrode SE4 to a fourth touch pad TP4 arranged in the pad area PA, and a fifth touch routing wiring TL5 for electrically connecting the fifth sensor electrode SE5 to a fifth touch pad TP5 arranged in the pad area PA.

[0226] Referring to FIG. 9, the first touch routing line TL1, the second touch routing line TL2, the third touch routing line TL3, and the fifth touch routing line TL5 may each be connected to sensor electrodes SE1, SE2, SE3, and SE5 extending in the second direction (row direction).

[0227] Referring to FIG. 9, each of the first touch routing wiring TL1, the second touch routing wiring TL2, the third touch routing wiring TL3 and the fifth touch routing wiring TL5 can extend in the first direction across the display area DA to the first non-display area NDA1 without bypassing the second non-display area NDA2 and the fourth non-display area NDA4.

[0228] 9, the sensor electrodes SE may include a plurality of transmitting sensor electrodes SE_TX and a plurality of receiving sensor electrodes SE_RX. The touch routing lines TL may include a plurality of transmitting touch routing lines TL_TX and a plurality of receiving touch routing lines TL_RX. The touch pads TP may include a plurality of transmitting touch pads TP_TX and a plurality of receiving touch pads TP_RX.

[0229] A touch driving signal output from the touch sensing circuit 210 may be applied to at least one of the multiple transmitting sensor electrodes SE_TX. Here, the touch driving signal may be a signal whose voltage level fluctuates. For example, the touch driving signal may be a pulse signal having a predetermined frequency and amplitude, or may be a signal having various signal waveforms such as a triangular wave, a square wave, or a sine wave.

[0230] 9, the transmitting sensor electrodes SE_TX and the receiving sensor electrodes SE_RX may be arranged to cross each other. For example, each of the transmitting sensor electrodes SE_TX may be arranged to extend in a first direction. Each of the receiving sensor electrodes SE_RX may be arranged to extend in a second direction different from the first direction.

[0231] The shapes of each of the plurality of transmitting sensor electrodes SE_TX and the plurality of receiving sensor electrodes SE_RX can be modified in various ways. For example, each of the plurality of transmitting sensor electrodes SE_TX and the plurality of receiving sensor electrodes SE_RX may be bar-shaped. As another example, each of the plurality of receiving sensor electrodes SE_RX may be composed of several sub-sensor electrodes electrically connected to each other, and each of the plurality of transmitting sensor electrodes SE_TX may be composed of several sub-sensor electrodes electrically connected to each other. For example, each of the several sub-sensor electrodes may have various shapes such as a square, a diamond, or a comb shape.

[0232] Referring to FIG. 9, a display panel 110 according to an embodiment of the present disclosure can include an internal touch routing structure as an ultra-narrow bezel structure.

[0233] The internal touch routing structure may be a structure in which the touch routing wiring TL is not arranged in the second to fourth non-display areas NDA2 to NDA4, excluding the first non-display area NDA1 which includes the pad area PA, among the first to fourth non-display areas NDA1 to NDA4.

[0234] According to the internal touch routing structure, among the multiple transmitting touch routing wirings TL_TX and the multiple receiving touch routing wirings TL_RX, multiple touch routing wirings (e.g., multiple receiving touch routing wirings TL_RX) that each extend in the row direction (second direction) can extend across the display area DA to the pad area PA in the first non-display area NDA1 without detouring the second to fourth non-display areas NDA2 to NDA4 outside the display area DA.

[0235] For example, among the multiple transmitting touch routing wirings TL_TX and the multiple receiving touch routing wirings TL_RX, the multiple receiving touch routing wirings TL_RX each extending in the second direction can extend across the display area DA to the pad area PA in the first non-display area NDA1 without detouring the second to fourth non-display areas NDA2 to NDA4 outside the display area DA.

[0236] When the multiple receiving touch routing wirings TL_RX cross the display area DA, the multiple receiving touch routing wirings TL_RX can be arranged to avoid the light emitting areas of the multiple subpixels SP in the display area DA, thereby making it possible to design an internal touch routing structure that does not degrade the light emitting performance.

[0237] In this case, the multiple receiving touch routing lines TL_RX may cross the multiple receiving sensor electrodes SE_RX, i.e., the multiple receiving touch routing lines TL_RX may be located in a metal layer different from the multiple receiving sensor electrodes SE_RX and overlap the multiple receiving sensor electrodes SE_RX.

[0238] According to the internal touch routing structure of the display panel 110 according to the embodiment of the present disclosure, the size of the non-display area NDA can be significantly reduced. That is, the sizes of the second to fourth non-display areas NDA2, NDA3, and NDA4 not including the pad area PA can be significantly reduced.

[0239] 9, when the internal touch routing structure of the display panel 110 according to the embodiment of the present disclosure is applied, among the first to fourth non-display areas NDA1 to NDA4, a plurality of touch routing lines TL may be arranged in the first non-display area NDA1 including the pad area PA, but a plurality of touch routing lines TL may not be arranged in the second non-display area NDA2 and the fourth non-display area NDA4. This allows the sizes of the second to fourth non-display areas NDA2, NDA3, and NDA4 among the first to fourth non-display areas NDA1 to NDA4 to be reduced to the minimum.

[0240] Referring to FIG. 9, the plurality of transmitting sensor electrodes SE_TX and the plurality of receiving sensor electrodes SE_RX may include a sensor metal.

[0241] The plurality of transmitting touch routing traces TL_TX or the plurality of receiving touch routing traces TL_RX can cross the plurality of transmitting sensor electrodes SE_TX or the plurality of receiving sensor electrodes SE_RX, such that the plurality of transmitting touch routing traces TL_TX or the plurality of receiving touch routing traces TL_RX can include a bridge metal that is different from the sensor metal included in the plurality of transmitting sensor electrodes SE_TX or the plurality of receiving sensor electrodes SE_RX.

[0242] For example, as shown in FIG. 9, of the multiple transmitting touch routing lines TL_TX and the multiple receiving touch routing lines TL_RX, the multiple receiving touch routing lines TL_RX can cross the multiple receiving sensor electrodes SE_RX across the display area DA.

[0243] In this case, the plurality of receiving touch routing wires TL_RX may include a bridge metal different from the sensor metal, and the plurality of transmitting touch routing wires TL_TX may include the sensor metal or the bridge metal.

[0244] As another example, among the plurality of transmitting touch routing lines TL_TX and the plurality of receiving touch routing lines TL_RX, the plurality of transmitting touch routing lines TL_TX may cross the plurality of transmitting sensor electrodes SE_TX across the display area DA. In this case, the plurality of transmitting touch routing lines TL_TX may include a bridge metal different from the sensor metal. In this case, the plurality of receiving touch routing lines TL_RX may include a sensor metal or a bridge metal.

[0245] Meanwhile, outside the display area DA (i.e., the first non-display area NDA1), the touch routing line TL may be changed from a sensor metal to a bridge metal, or from a bridge metal to a sensor metal. If necessary, a third metal different from the sensor metal and the bridge metal may be used as a part of the metal of the touch routing line TL.

[0246] 10 illustrates an exemplary detailed view of a portion 900 of a touch sensor included in a display panel 110 according to an embodiment of the present disclosure, and shows an enlarged view of a unit sensor 1000 in the portion 900 of the touch sensor. Here, the unit sensor 800 may refer to an area where one transmitting touch electrode SE_TX and one receiving touch sensor electrode SE_RX intersect.

[0247] FIG. 10 is an enlarged plan view of a portion 300 of FIG. 9, showing an example in which each sensor electrode SE included in the touch sensor has a comb-like shape.

[0248] Referring to FIG. 10, one sensor electrode SE can be composed of one integrated electrode or can be composed of several sub-sensor electrodes that are electrically connected.

[0249] 10, a first receiving sensor electrode SE_RX1 and a second receiving sensor electrode SE_RX2 each extending in a second direction (e.g., row direction) may be arranged in a portion 300 of the touch sensor in Fig. 9, and a first transmitting sensor electrode SE_TX1, a second transmitting sensor electrode SE_TX2, and a third transmitting sensor electrode SE_TX3 each extending in a first direction (e.g., column direction) may be arranged. Here, the first direction and the second direction may intersect with each other.

[0250] Referring to FIG. 10, a first receiving touch routing wiring TL_RX1 electrically connected to the first receiving sensor electrode SE_RX1 and a second receiving touch routing wiring TL_RX2 electrically connected to the second receiving sensor electrode SE_RX2 may be further arranged in a portion 300 of the touch sensor of FIG. 9.

[0251] Referring to FIG. 10, the first transmitting sensor electrode SE_TX1, the second transmitting sensor electrode SE_TX2, and the third transmitting sensor electrode SE_TX3 may be electrically connected to the first transmitting touch routing wiring TL_TX1, the second transmitting touch routing wiring TL_TX2, and the third transmitting touch routing wiring TL_TX3, respectively, in or near the first non-display area NDA1.

[0252] Hereinafter, the first receiving sensor electrode SE_RX1 is also referred to as the first sensor electrode SE1, the second receiving sensor electrode SE_RX2 is also referred to as the second sensor electrode SE2, and the first transmitting sensor electrode SE_TX1 is also referred to as the fourth sensor electrode SE4. In addition, the first receiving touch routing wiring TL_RX1 is also referred to as the first touch routing wiring TL1, the second receiving touch routing wiring TL_RX2 is also referred to as the second touch routing wiring TL2, and the first transmitting touch routing wiring TL_TX1 is also referred to as the fourth touch routing wiring TL4. In addition, the first receiving touchpad TP_RX to which the first receiving sensor electrode SE_RX1 is connected via the first receiving touch routing wiring TL_RX1 is also referred to as the first touchpad TP1, the second receiving touchpad TP_RX to which the second receiving sensor electrode SE_RX2 is connected via the second receiving touch routing wiring TL_RX2 is also referred to as the second touchpad TP2, and the first transmitting touchpad TP_TX to which the first transmitting sensor electrode SE_TX1 is connected via the first transmitting touch routing wiring TL_TX1 is also referred to as the fourth touchpad TP4.

[0253] Similarly, the third receiving sensor electrode SE_RX arranged adjacent to the second receiving sensor electrode SE2 in the first direction is also referred to as the third sensor electrode SE3, and the receiving sensor electrode SE_RX arranged closest to the pad area PA among the multiple receiving sensor electrodes SE_RX is also referred to as the fifth sensor electrode SE5. In addition, the receiving touch routing wiring TL_RX connected to the third sensor electrode SE3 is also referred to as the third touch routing wiring TL3, and the receiving touch routing wiring TL_RX connected to the fifth sensor electrode SE5 is also referred to as the fifth touch routing wiring TL5. In addition, the receiving touchpad TP_RX connected to the third sensor electrode SE3 via the third touch routing wiring TL3 is also referred to as the third touchpad TP3, and the receiving touchpad TP_RX connected to the fifth sensor electrode SE5 via the fifth touch routing wiring TL5 is also referred to as the fifth touchpad TP5.

[0254] Each of the first, second and third transmitting sensor electrodes SE_TX1, SE_TX1, SE_TX2, SE_TX3 may be configured as a single integrated electrode. The first receiving sensor electrode SE_RX1 may be configured as a plurality of first sub-sensor electrodes SUB1a, SUB1b, SUB1c, SUB1d electrically connected by a first bridge BRG1. The second receiving sensor electrode SE_RX2 may be configured as a plurality of second sub-sensor electrodes SUB2a, SUB2b, SUB2c, SUB2d electrically connected by a second bridge BRG2.

[0255] The first bridge BRG1 may overlap the first, second, and third transmitting sensor electrodes SE_TX1, SE_TX2, and SE_TX3. The second bridge BRG2 may overlap the first, second, and third transmitting sensor electrodes SE_TX1, SE_TX2, and SE_TX3.

[0256] Referring to FIG. 10, the first transmitting sensor electrode SE_TX1 can pass between the two first sub-sensor electrodes SUB1a, SUB1b included in the first receiving sensor electrode SE_RX1 and between the two second sub-sensor electrodes SUB2a, SUB2b included in the second receiving sensor electrode SE_RX2.

[0257] The first bridge BRG1 electrically connecting the two first sub-sensor electrodes SUB1a and SUB1b included in the first receiving sensor electrode SE_RX1 may overlap the first transmitting sensor electrode SE_TX1.

[0258] The second bridge BRG2 electrically connecting the two second sub sensor electrodes SUB2a and SUB2b included in the second receiving sensor electrode SE_RX2 may overlap the first transmitting sensor electrode SE_TX1.

[0259] Referring to FIG. 10, the second transmitting sensor electrode SE_TX2 can pass between the other two first sub-sensor electrodes SUB1b, SUB1c included in the first receiving sensor electrode SE_RX1, and between the other two second sub-sensor electrodes SUB2b, SUB2c included in the second receiving sensor electrode SE_RX2.

[0260] The first bridge BRG1 electrically connecting the other two first sub sensor electrodes SUB1b and SUB1c included in the first receiving sensor electrode SE_RX1 may overlap the second transmitting sensor electrode SE_TX2.

[0261] A second bridge BRG2 electrically connecting the other two second sub sensor electrodes SUB2b and SUB2c included in the second receiving sensor electrode SE_RX2 may overlap the second transmitting sensor electrode SE_TX2.

[0262] Referring to FIG. 10, the third transmitting sensor electrode SE_TX3 can pass between two further first sub-sensor electrodes SUB1c, SUB1d included in the first receiving sensor electrode SE_RX1, and between two further second sub-sensor electrodes SUB2c, SUB2d included in the second receiving sensor electrode SE_RX2.

[0263] The first bridge BRG1 electrically connecting two other first sub-sensor electrodes SUB1c and SUB1d included in the first receiving sensor electrode SE_RX1 may overlap the third transmitting sensor electrode SE_TX3.

[0264] A second bridge BRG2 electrically connecting two other second sub sensor electrodes SUB2c, SUB2d included in the second receiving sensor electrode SE_RX2 may overlap the third transmitting sensor electrode SE_TX3.

[0265] Referring to FIG. 10, the first receiving touch routing wiring TL_RX1 can be electrically connected to at least one (e.g., SUB1a) of the multiple first sub-sensor electrodes SUB1a, SUB1b, SUB1c, and SUB1d that constitute the first receiving sensor electrode SE_RX1 via a contact hole CNT.

[0266] The second reception touch routing wiring TL_RX2 can be electrically connected to at least one (for example, SUB2a) of the multiple second sub sensor electrodes SUB2a, SUB2b, SUB2b, SUB2c, and SUB2d that constitute the second reception sensor electrode SE_RX2 via a contact hole CNT.

[0267] 10, the first transmitting sensor electrode SE_TX1 may be electrically connected to the first transmitting touch routing line TL_TX1 at a location closest to the first non-display area NDA1. Alternatively, the first transmitting sensor electrode SE_TX1 may extend to the first non-display area NDA1. A portion extending from the first transmitting sensor electrode SE_TX1 to the first non-display area NDA1 may correspond to the first transmitting touch wiring TL_TX1.

[0268] The second transmitting sensor electrode SE_TX2 may be electrically connected to the second transmitting touch routing line TL_TX2 at a location closest to the first non-display area NDA1. Alternatively, the second transmitting sensor electrode SE_TX2 may extend to the first non-display area NDA1. A portion extending from the second transmitting sensor electrode SE_TX2 to the first non-display area NDA1 may correspond to the second transmitting touch routing line TL_TX2.

[0269] The third transmitting sensor electrode SE_TX3 may be electrically connected to the third transmitting touch routing line TL_TX3 at a location closest to the first non-display area NDA1. Alternatively, the third transmitting sensor electrode SE_TX3 may extend to the first non-display area NDA1. A portion extending from the third transmitting sensor electrode SE_TX3 to the first non-display area NDA1 may correspond to the third transmitting touch routing line TL_TX3.

[0270] Referring to FIG. 10, a plurality of first sub-sensor electrodes SUB1a, SUB1b, SUB1b, SUB1c, and SUB1d included in the first receiving sensor electrode SE_RX1 and a plurality of second sub-sensor electrodes SUB2a, SUB2b, SUB2b, SUB2c, and SUB2d included in the second receiving sensor electrode SE_RX2 may be made of a sensor metal disposed in a sensor metal layer.

[0271] The first bridge BRG1 and the second bridge BRG2 can be made of a bridge metal arranged in a bridge metal layer, which is a metal layer different from the sensor metal layer.

[0272] An insulating layer may be present between the bridge metal layer and the sensor metal layer.

[0273] 10, the first receive touch routing line TL_RX1 is disposed in a sensor metal layer and may overlap the first transmit sensor electrode SE_TX1 and / or the second receive sensor electrode SE_RX2 that should be electrically isolated. Therefore, the first receive touch routing line TL_RX1 must be disposed in a bridge metal layer different from the sensor metal layer. That is, the first receive touch routing line TL_RX1 may include a bridge metal.

[0274] The second receive touch routing line TL_RX2 may be disposed in a sensor metal layer and overlap with the first transmit sensor electrode SE_TX1 and / or the first receive sensor electrode SE_RX1, which should be electrically isolated from each other. Therefore, the second receive touch routing line TL_RX2 must be disposed in a bridge metal layer different from the sensor metal layer. That is, the second receive touch routing line TL_RX2 may include a bridge metal.

[0275] 10, the first transmitting touch routing line TL_TX1, the second transmitting touch routing line TL_TX2, and the third transmitting touch routing line TL_TX3 may be disposed in a sensor metal layer or a bridge metal layer, that is, the first transmitting touch routing line TL_TX1, the second transmitting touch routing line TL_TX2, and the third transmitting touch routing line TL_TX3 may include a sensor metal or a bridge metal.

[0276] For example, in the first non-display area NDA1, if at least one of the first transmitting touch routing wiring TL_TX1, the second transmitting touch routing wiring TL_TX2, and the third transmitting touch routing wiring TL_TX3 crosses and overlaps with at least one of the first receiving touch routing wiring TL_RX1 and the second receiving touch routing wiring TL_RX2, the first transmitting touch routing wiring TL_TX1, the second transmitting touch routing wiring TL_TX2, and the third transmitting touch routing wiring TL_TX3 must be arranged in a different metal layer from the first receiving touch routing wiring TL_RX1 and the second receiving touch routing wiring TL_RX2.

[0277] Therefore, in the first non-display area NDA1, when at least one of the first transmitting touch routing line TL_TX1, the second transmitting touch routing line TL_TX2, and the third transmitting touch routing line TL_TX3 crosses and overlaps with at least one of the first receiving touch routing line TL_RX1 and the second receiving touch routing line TL_RX2, the first transmitting touch routing line TL_TX1, the second transmitting touch routing line TL_TX2, and the third transmitting touch routing line TL_TX3 can be disposed in a sensor metal layer, that is, the first transmitting touch routing line TL_TX1, the second transmitting touch routing line TL_TX2, and the third transmitting touch routing line TL_TX3 can be made of a sensor metal.

[0278] 10, the first sensor electrode SE1 may include two or more first sub-sensor electrodes SUB1a, SUB1b, SUB1c, and SUB1d arranged in a second direction, and a first bridge BRG1 electrically connecting the two or more first sub-sensor electrodes SUB1a, SUB1b, SUB1c, and SUB1d. For example, the first sensor electrode SE1 may be a first receiving sensor electrode SE_RX1.

[0279] 10, the first touch routing line TL1 may be electrically connected to the first sensor electrode SE1 and the first touch pad TP1. A portion of the first touch routing line TL1 may be electrically connected to at least one of the two or more first sub-sensor electrodes SUB1a, SUB1b, SUB1c, and SUB1d included in the first sensor electrode SE1, and another portion of the first touch routing line TL1 may be electrically connected to the first touch pad TP1.

[0280] 10, the second sensor electrode SE2 may include two or more second sub-sensor electrodes SUB2a, SUB2b, SUB2c, and SUB2d arranged in a second direction, and a second bridge BRG2 electrically connecting the two or more second sub-sensor electrodes SUB2a, SUB2b, SUB2c, and SUB2d. For example, the second sensor electrode SE2 may be a second receiving sensor electrode SE_RX2.

[0281] 10, the second touch routing line TL2 may be electrically connected to the second sensor electrode SE2 and the second touch pad TP2. A portion of the second touch routing line TL2 may be electrically connected to at least one of the two or more second sub-sensor electrodes SUB2a, SUB2b, SUB2c, and SUB2d included in the second sensor electrode SE2, and another portion of the second touch routing line TL2 may be electrically connected to the second touch pad TP2.

[0282] Referring to FIG. 10, the fourth sensor electrode SE4 may be disposed between the two first sub-sensor electrodes SUB1a, SUB1b included in the first sensor electrode SE1 and between the two second sub-sensor electrodes SUB2a, SUB2b included in the second sensor electrode SE2.

[0283] Referring to FIG. 10, the fourth sensor electrode SE4 may overlap the first bridge BRG1 and the second bridge BRG2.

[0284] The fourth touch routing wiring TL4 may electrically connect the fourth touch pad TP4 arranged in the pad area PA included in the first non-display area NDA1 to the fourth sensor electrode SE4 arranged in the display area DA.

[0285] 10, the sensor electrodes SE1 and SE4 in the touch sensor included in the display panel 110 according to the embodiment of the present disclosure may be a mesh-shaped sensor metal having an opening OA formed therein. Here, the opening OA formed in the sensor electrodes SE1 and SE4 may overlap the light-emitting area of ​​the sub-pixel SP.

[0286] In this case, the first touch routing wiring TL1 connected to the first sensor electrode SE1 and / or the first bridge BRG1 included in the first sensor electrode SE1 may be disposed along the mesh-shaped sensor metal constituting the first sensor electrode SE1. That is, the first bridge BRG1 may be disposed by bending or sagging along the mesh-shaped sensor metal of the fourth sensor electrode SE4.

[0287] As a result, the first touch routing wiring TL1 connected to the first sensor electrode SE1 and / or the first bridge BRG1 included in the first sensor electrode SE1 may vertically overlap with the mesh-shaped sensor metal constituting the first sensor electrode SE1.

[0288] As a result, the opening OA formed in the first sensor electrode SE1 and the fourth sensor electrode SE4 is no longer hidden by the first touch routing wiring TL1 and / or the first bridge BRG1, the light-emitting area of ​​the sub-pixel SP is enlarged, and the light-emitting efficiency is improved.

[0289] FIG. 11 shows a substrate 111 and an encapsulation layer 200 of a display panel 110 according to an embodiment of the present disclosure.

[0290] Referring to FIG. 11, the non-display area NDA may include a first non-display area NDA1 positioned in a first direction from the display area DA, a second non-display area NDA2 positioned in a second direction from the display area DA, a third non-display area NDA3 positioned in the opposite direction from the display area DA in the first direction, and a fourth non-display area NDA4 positioned in the opposite direction from the display area DA in the second direction.

[0291] Referring to FIG. 11, the sealing layer 200 is disposed in the display area DA, but may extend to a portion of the non-display area NDA.

[0292] 11, the encapsulation layer 200 may include a first inclined surface SLP1 located at an outer edge in a first direction with respect to the center, a second inclined surface SLP2 located at an outer edge in a second direction intersecting the first direction with respect to the center, a third inclined surface SLP3 located at an outer edge in a direction opposite to the first direction with respect to the center, and a fourth inclined surface SLP4 located at an outer edge in a direction opposite to the second direction with respect to the center. In this case, the edge of the encapsulation layer 200 may be regarded as an edge of an organic film, and the first to fourth inclined surfaces SLP1, SLP2, SLP3, and SLP4 of the encapsulation layer 200 may be inclined surfaces of the organic film PCL. The inclinations of the first to fourth inclined surfaces SLP1, SLP2, SLP3, and SLP4 of the encapsulation layer 200 may be the inclinations of the organic film PCL.

[0293] Referring to FIG. 11, the first inclined surface SLP1, the second inclined surface SLP2, the third inclined surface SLP3, and the fourth inclined surface SLP4 of the encapsulation layer 200 may be located in the non-display area NDA.

[0294] Referring to FIG. 11, among the first sloping surface SLP1, the second sloping surface SLP2, the third sloping surface SLP3 and the fourth sloping surface SLP4 of the encapsulation layer 200, no metal (e.g., touch routing wiring) is arranged on the second sloping surface SLP2 and the fourth sloping surface SLP4, and a touch routing wiring TL extending in the first direction can pass on the first sloping surface SLP1.

[0295] For example, the first touch routing wiring TL1 is not arranged on the second inclined surface SLP2 and the fourth inclined surface SLP4, but descends along the first inclined surface SLP1 and can be electrically connected to the second touch pad TP2 in the pad area PA.

[0296] The first touch routing wiring TL1 may extend across the display area DA in the first direction to the first non-display area NDA1 including the pad area PA without detouring the second non-display area NDA2 and the fourth non-display area NDA4. A part of the first touch routing wiring TL1 extending to the first non-display area NDA1 may overlap with a stopper STP in the first non-display area NDA1.

[0297] Fig. 12 is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure, which is a cross-sectional view of a region 1120 including the second non-display region NDA2 in Fig. 11. In Fig. 11, the vertical structures of the region 1130 including the third non-display region NDA3 and the region 1140 including the fourth non-display region NDA4 may be the same as the vertical structure of the region 1120 including the second non-display region NDA2.

[0298] 12, a vertical structure of a region including the second non-display area NDA2 and a part of the adjacent display area DA will be described. For this purpose, a vertical cross-sectional structure of a region where the first sensor electrode SE1 and the first touch routing line TL1 are connected will be exemplarily described. In the following description, the same content as that of the vertical cross-sectional structure of FIG. 5 will be omitted, and the description will focus on the content different from that of FIG. 5.

[0299] Referring to FIG. 12, the second non-display area NDA2 is an area located in a second direction (eg, a right area) from the display area DA, and does not include the bending area BA and the pad area PA.

[0300] Referring to FIG. 12, the touch sensor layer TSL may be formed on the encapsulation layer 200.

[0301] Referring to FIG. 12, the touch sensor layer TSL may include a touch buffer film T-BUF on the encapsulation layer 200, a touch interlayer insulating film T-ILD on the touch buffer film T-BUF, and a touch protection film PAC on the touch interlayer insulating film T-ILD.

[0302] Referring to FIG. 12, the touch sensor layer TSL may include a bridge metal layer between the touch buffer film T-BUF and the touch interlayer insulating film T-ILD, and a sensor metal layer between the touch interlayer insulating film T-ILD and the touch protective film PAC.

[0303] 12, the touch buffer film T-BUF may be omitted. The touch buffer film T-BUF may be an inorganic buffer film or an organic buffer film.

[0304] Referring to FIG. 12, the touch interlayer insulating film T-ILD is an insulating film for electrical isolation between the bridge metal layer and the sensor metal layer, and may be an organic buffer film or an inorganic buffer film.

[0305] 12, the touch protection film PAC can protect the touch sensor by blocking harmful external environments and can maintain stable characteristics of the display device 100. For example, the touch protection film PAC can be an organic film. The touch protection film PAC can be disposed to extend to the non-display area NDA.

[0306] 12, a first touch sensor SE1 disposed in the display area DA and extending in a second direction (eg, a row direction) may be disposed on the encapsulation layer 200. As shown in FIG.

[0307] Referring to FIG. 12, the first sensor electrode SE1 may include a plurality of first sub-sensor electrodes SUB1a, SUB1b and a first bridge BRG1 electrically connecting the plurality of first sub-sensor electrodes SUB1a, SUB1b.

[0308] The first bridge BRG1 of the first sensor electrode SE1 extending in the second direction (eg, the row direction) can overlap with the fourth sensor electrode SE4 extending in the first direction (eg, the column direction).

[0309] The first sub-sensor electrodes SUB1a, SUB1b and the fourth sensor electrode SE4 included in the first sensor electrode SE1 may be disposed on a sensor metal layer SML, that is, the first sub-sensor electrodes SUB1a, SUB1b and the fourth sensor electrode SE4 included in the first sensor electrode SE1 may include a sensor metal.

[0310] The first bridge BRG1 may be disposed in a bridge metal layer BML, i.e., the first bridge BRG1 may be made of a bridge metal.

[0311] The first touch routing wiring TL1 electrically connected to one (e.g., SUB1a) of the plurality of first sub-sensor electrodes SUB1a and SUB1b included in the first sensor electrode SE1 may be disposed on the bridge metal layer BML. That is, the first touch routing wiring TL1 may be made of a bridge metal.

[0312] The first touch routing wiring TL1 extends across the display area DA to the first non-display area NDA1 without detouring the second non-display area NDA2, and can be connected to the first touch pad TP1 in the pad area PA included in the first non-display area NDA1.

[0313] Therefore, the first touch routing wiring TL1 is not arranged on the second inclined surface SLP2 of the encapsulation layer 200, but extends across the display area DA to the first non-display area NDA1 and is arranged along the first inclined surface SLP1 of the encapsulation layer 200, and can extend to the pad area PA.

[0314] 12, when the first touch routing line TL1 crosses the display area DA without detouring the second non-display area NDA2, the first touch routing line TL1 can be arranged to avoid the light emitting area EA of each of the sub-pixels SP in the display area DA. That is, the first touch routing line TL1 can overlap the bank BK without overlapping the light emitting area EA of each of the sub-pixels SP. This makes it possible to design an internal touch routing structure that does not deteriorate the light emitting performance.

[0315] Referring to FIG. 12, not only the first touch routing line TL1 but also the first sensor electrode SE1 electrically connected to the first touch routing line TL1 can overlap the bank BK without overlapping with the light emitting area EA of each of the multiple subpixels SP.

[0316] Fig. 13 is a cross-sectional view of a display panel 110 according to an embodiment of the present disclosure. Fig. 13 is a cross-sectional view of an area 1110 including the first non-display area NDA1 in Fig. 11. In the following description, the same content as in the vertical cross-sectional structure in Fig. 7 will be omitted, and the description will focus on the content that is different from the vertical cross-sectional structure in Fig. 7.

[0317] 13, a substrate 111 includes a display area DA and a first non-display area NDA1 that is an outer area of ​​the display area DA in a first direction, and the first non-display area NDA1 may include a bending area BA and a pad area PA.

[0318] 13, a fifth bridge BRG5 made of a bridge metal may be disposed on the encapsulation layer 200. A touch interlayer insulating film T-ILD may be disposed on the fifth bridge BRG5. A fourth sensor electrode SE4 made of a sensor metal may be disposed on the touch interlayer insulating film T-ILD.

[0319] 13, a portion extending from the fourth sensor electrode SE to the first non-display area NDA1 may be a fourth touch routing line TL4. Therefore, the fourth touch routing line TL4 may be made of a sensor metal.

[0320] The fourth touch routing line TL4 can descend along the first inclined surface SLP1 of the encapsulation layer 200 and extend to the pad area PA of the first non-display area NDA1.

[0321] The touch protective film PAC may be disposed on the sensor electrodes SE including the fourth sensor electrode SE4 and the fifth sensor electrode SE5. The touch protective film PAC may protect the touch sensor by blocking harmful external environments and maintain stable characteristics of the display device 100. For example, the touch protective film PAC may be an organic film. The touch protective film PAC may be disposed to extend to the non-display area NDA.

[0322] The fourth touch routing wiring TL4 may extend along the first inclined surface SLP1 of the encapsulation layer 200, and may further extend to the top of the stopper STP and be disposed along the outer side surface of the insulating film stack INS. The fourth touch routing wiring TL4 may overlap the organic film PCL of the encapsulation layer 200 and overlap the stopper STP.

[0323] 13, a fourth touch pad TP4 may be disposed in the pad area PA. The fourth touch pad TP4 may be electrically connected to the fourth touch routing line TL4 and may be electrically connected to the touch sensing circuit 210.

[0324] 13, the bending area BA may include a bending film 730 disposed on the substrate 111, and a touch connection pattern 1200 located under the bending film 730 and electrically connecting the fourth touch routing line TL4 and the fourth touch pad TP4. An insulating film 720 may be disposed on the touch connection pattern 1200.

[0325] 13, the fourth touch routing line TL4 may not be disposed in the bending area BA. Therefore, the fourth touch routing line TL4 may be electrically connected to the fourth touch pad TP4 through the touch connection pattern 1200 disposed in the bending area BA.

[0326] 13, the fourth touch routing line TL4 may be electrically connected to a part of the touch connection pattern 1200 through a first contact hole CNT1 of the insulating film 720. The fourth touch pad TP4 may be electrically connected to another part of the touch connection pattern 1200 through a second contact hole CNT2 of the insulating film 720.

[0327] Referring to FIG. 13, the touch connection pattern 1200 may include the same material as the source-drain electrodes of the transistors (eg, DT, ST) disposed in the display area DA.

[0328] The touch connection pattern 1200 may be composed of a first touch connection pattern including the same material as the source-drain electrodes of the transistors (e.g., DT, ST) arranged in the display area DA, and a second touch connection pattern including the same material as the gate electrodes or gate lines GL of the transistors (e.g., DT, ST).

[0329] The bending film 730 may be disposed in the bending area BA to cover an upper portion of the touch connection pattern 1200. The bending film 730 may play a role in preventing the touch connection pattern 1200 from being exposed to the outside in the bending area BA where the substrate 111 is bent, and in protecting the touch connection pattern 1200. In addition, the bending film 730 may be provided with an open hole that exposes the upper portion. That is, the open hole may be formed by removing an inorganic film (for example, the first inorganic film PAS1, the second inorganic film PAS2, and the touch interlayer insulating film T-ILD) that may be disposed on the bending film 730. When an inorganic film is disposed on the bending film 730, a crack may occur in the inorganic film when the bending area BA is bent, and moisture may penetrate into the inorganic film in which the crack occurs, so the inorganic film provided on the bending film 730 is removed.

[0330] The pattern protection film 731 is disposed to enclose the end of the touch connection pattern 1200, thereby protecting the end of the touch connection pattern 1200 disposed on the edge of the first non-display area NDA1.

[0331] The bending film 730 and the pattern protection film 731 are disposed in the same layer as the planarization film included in the insulating film stack INS, and can be made of the same material.

[0332] For example, the bending film 730 and the pattern protection film 731 can be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0333] The stopper STP and the internal touch routing structure have been described above as an extremely narrow bezel structure. In the following, the gate drive circuit 130 arranged in the display area DA will be described as yet another extremely narrow bezel structure with reference to FIGS. 14 to 21.

[0334] FIG. 14 shows a gate drive circuit 130 of a display device 100 according to an embodiment of the present disclosure.

[0335] Referring to FIG. 14 , a display panel 110 according to an embodiment of the present disclosure may include a gate-in-panel circuit GIPC configured to supply gate signals to a plurality of sub-pixels SP and overlapping the organic film PCL of the encapsulation layer 200.

[0336] 14, the gate-in-panel circuit GIPC is a gate driving circuit 130 built into the display panel 110. That is, the gate-in-panel circuit GIPC may be a gate driving circuit 130 of a gate in panel type.

[0337] Referring to FIG. 14, the gate-in-panel circuit GIPC may include an output buffer 1410 configured to output a gate signal Vout and a control circuit 1420 configured to control the output buffer 1410.

[0338] The output buffer 1410 may include a pull-up transistor Tu connected between a clock node Nclk to which a clock signal CLK is input and an output node Nout to which a gate signal Vout is output, and a pull-down transistor Td connected between the output node Nout to which a gate signal Vout is output and a low voltage node Nvgl to which a second gate voltage VGL is input.

[0339] The gate signal Vout may be the scan signal SC in FIG.

[0340] The output node Nout can be electrically connected to a gate line GL such as a scan line SCL.

[0341] The gate node of the pull-up transistor Tu can correspond to the Q node. Depending on the voltage level of the Q node, the pull-up transistor Tu can be turned on or off.

[0342] The gate node of the pull-down transistor Td can correspond to the QB node. Depending on the voltage level of the QB node, the pull-down transistor Td can be turned on or off.

[0343] The voltage level of the Q node and the voltage level of the QB node may be opposite to each other, i.e., when the voltage level of the Q node is high, the voltage level of the QB node may be low, and when the voltage level of the Q node is low, the voltage level of the QB node may be high.

[0344] As the voltage levels of the Q node and the QB node are opposite to each other, the on / off state of the pull-up transistor Tu and the on / off state of the pull-down transistor Td may be different from each other. That is, when the pull-up transistor Tu is turned on, the pull-down transistor Td may be turned off. When the pull-up transistor Tu is turned off, the pull-down transistor Td may be turned on.

[0345] The control circuit 1420 receives control signals such as a start signal STR and a reset signal RST, and can control the voltage levels of the Q node and the QB node.

[0346] The control circuit 1420 can include multiple transistors.

[0347] When the control circuit 1420 causes the voltage level of the Q node to become high and the voltage level of the QB node to become low, the pull-up transistor Tu is turned on and a gate signal Vout having the high-level voltage of the clock signal CLK can be output to the output node Nout.

[0348] When the control circuit 1420 causes the voltage level of the Q node to become low and the voltage level of the QB node to become high, the pull-down transistor Td is turned on and a gate signal Vout having a second gate voltage VGL corresponding to a low-level voltage can be output to the output node Nout.

[0349] The transistors Tu and Td included in the output buffer 1410 and the transistors included in the control circuit 1420 are referred to as "gate driving transistors." Meanwhile, the driving transistor DT and the scan transistor ST included in the sub-pixel circuit SPC are referred to as "pixel driving transistors."

[0350] FIG. 15 shows a vertical structure of the display panel 110 when the gate-in-panel circuit GIPC is disposed over the entire display area DA of the display panel 110 according to an embodiment of the present disclosure.

[0351] Referring to FIG. 15, a display panel 110 according to an embodiment of the present disclosure may include a substrate 111 , a base circuit layer 1510 , a pixel array layer 1530 , and an encapsulation layer 200 .

[0352] 15, a pixel array layer 1530 is a layer in which a plurality of sub-pixels SP are formed and may be located on a substrate 111. The pixel array layer 1530 may include a plurality of sub-pixels SP arranged in a display area DA where an image is displayed.

[0353] 15, the base circuit layer 1510 is a layer in which a gate-in-panel circuit GIPC, which is a gate driving circuit 130 of a gate in panel type, is formed, and may be located between the substrate 111 and the pixel array layer 1530. That is, the base circuit layer 1510 may include a gate-in-panel circuit GIPC, which is a gate driving circuit 130 of a gate in panel type.

[0354] For example, the base circuit layer 1510 may include a gate-in-panel circuit GIPC arranged across the entire display area DA (see FIGS. 15 and 16). As another example, the base circuit layer 1510 may include a gate-in-panel circuit GIPC arranged in at least a portion of the display area DA (see FIGS. 17 to 21). FIGS. 15 to 16 will be used to explain an example in which the gate-in-panel circuit GIPC included in the base circuit layer 1510 is arranged across the entire display area DA.

[0355] 15, the base circuit layer 1510 may be a layer in which two or more power lines are formed to which two or more common pixel driving voltages are applied to the pixel array layer 1530. That is, the base circuit layer 1510 may further include two or more power lines to which two or more common pixel driving voltages are applied to the pixel array layer 1530.

[0356] For example, the two or more common pixel driving voltages may include a first common driving voltage VDD and a second common driving voltage VSS supplied to the pixel array layer 1530. The two or more power supply lines may include a first common driving voltage line VDDL and a second common driving voltage line VSSL. The two or more power supply lines may be electrically connected to a pattern (metal) in the pixel array layer 1530. The two or more power supply lines may also include a pattern (metal) in the pixel array layer 1530.

[0357] 15, the encapsulation layer 200 may be disposed on a pixel array layer 1530. The encapsulation layer 200 may prevent an organic film disposed in the pixel array layer 1530 from being exposed to moisture or oxygen.

[0358] As mentioned above, in conventional display devices, the gate driving circuit was connected to or formed in the non-display area (bezel), but in the display device 100 according to the embodiment of the present disclosure, the gate-in-panel circuit GIPC is arranged within the display area DA, thereby significantly reducing the size of the non-display area NDA.

[0359] Furthermore, while in conventional display devices various power supply wirings are arranged in the non-display area NDA, in the display device 100 according to an embodiment of the present disclosure, various power supply wirings are arranged within the display area DA, thereby further reducing the size of the non-display area NDA.

[0360] Furthermore, even if the gate-in-panel circuit GIPC and / or various power supply wirings are arranged within the display area DA, the space in which the sub-pixels SP are arranged is not reduced by vertically overlapping the pixel array layer 1530. This makes it possible to reduce the size of the non-display area NDA without reducing the aperture ratio of the display area DA of the display panel 110.

[0361] Referring to FIG. 15, the display panel 110 according to the embodiment of the present disclosure may further include a shielding layer 1520 located between the base circuit layer 1510 and the pixel array layer 1530 .

[0362] The shielding layer 1520 can shield the electric field between the base circuit layer 1510 and the pixel array layer 1530, thereby preventing the base circuit layer 1510 and the pixel array layer 1530 from exerting undesired electrical influence on each other.

[0363] Referring to FIG. 15, in order to improve the shielding performance of the shielding layer 1520, the shielding layer 1520 can be electrically connected with the power lines located in the base circuit layer 1510.

[0364] For example, the shielding layer 1520 may be electrically connected to a first power line among two or more power lines located in the base circuit layer 1510. Here, the first power line may be a power line to which a first common driving voltage VDD to be supplied to the pixel array layer 1530 is applied. Thus, the first power line may be electrically connected to a first common driving voltage line VDDL disposed in the pixel array layer 1530.

[0365] As another example, the shielding layer 1520 may be electrically connected to a second power line among two or more power lines located in the base circuit layer 1510. Here, the second power line may be a power line to which a second common driving voltage VSS is applied to the pixel array layer 1530. Thus, the second power line may be electrically connected to a second common driving voltage line VSSL disposed in the pixel array layer 1530.

[0366] Referring to FIG. 4, in order to improve the shielding performance of the shielding layer 1520, the shielding layer 1520 can be electrically connected to a metal located in the pixel array layer 1530.

[0367] For example, the shielding layer 1520 may be electrically connected to a first metal located in the pixel array layer 1530. Here, the first metal may be a metal to which the first common driving voltage VDD is applied. Here, the first metal is a metal to which the first common driving voltage VDD is applied, and may be a first common driving voltage line VDDL or a connection pattern connected to the first common driving voltage line VDDL.

[0368] As another example, the shielding layer 1520 may be electrically connected to a second metal located in the pixel array layer 1530. Here, the second metal is a metal to which the second common driving voltage VSS is applied, and may be a second common driving voltage line VSSL or a connection pattern connected to the second common driving voltage line VSSL.

[0369] Referring to FIG. 15, the shielding layer 1520 may electrically connect metal located in the pixel array layer 1530 and metal located in the base circuit layer 1510 .

[0370] For example, the shielding layer 1520 may electrically connect a first metal located in the pixel array layer 1530 and a first power line located in the base circuit layer 1510. Here, the first metal may be a metal to which the first common driving voltage VDD is applied. Here, the first metal is a metal to which the first common driving voltage VDD is applied, and may be a first common driving voltage line VDDL or a connection pattern connected to the first common driving voltage line VDDL. The first power line may be a power line to which the first common driving voltage VDD supplied to the pixel array layer 1530 is applied.

[0371] In this example, the shielding layer 1520 may be electrically connected to the light emitting element ED included in each of the sub-pixels SP and a source electrode or a drain electrode of one of the pixel driving transistors among the plurality of pixel driving transistors. Referring to the equivalent circuit of the sub-pixel SP illustrated in FIG. 2, the shielding layer 1520 may be electrically connected to a third node N3 of the driving transistor DT among the plurality of pixel driving transistors included in each of the sub-pixels SP. The third node N3 of the driving transistor DT may be a drain electrode or a source electrode.

[0372] As another example, the shielding layer 1520 may electrically connect a second metal located in the pixel array layer 1530 and a second power supply line located in the base circuit layer 1510. Here, the second metal is a metal to which a second common driving voltage VSS is applied, and may be a second common driving voltage line VSSL or a connection pattern connected to the second common driving voltage line VSSL. The second power supply line may be a power supply line to which the second common driving voltage VSS supplied to the pixel array layer 1530 is applied.

[0373] In this example, the shielding layer 1520 may be electrically connected to the cathode CAT of the light-emitting element ED included in each of the sub-pixels SP.

[0374] Referring to FIG. 15, a display panel 110 according to an embodiment of the present disclosure may include a substrate 111, a pixel array layer 1530 located on the substrate 111 and in which multiple subpixels SP are arranged in a display area DA where an image is displayed, a base circuit layer 1510 located between the substrate 111 and the pixel array layer 1530, and a shielding layer 1520 located between the base circuit layer 1510 and the pixel array layer 1530.

[0375] The base circuit layer 1510 may include an organic film disposed on a gate driving transistor included in the gate-in-panel circuit GIPC. The base circuit layer 1510 may include two or more power lines to which two or more common pixel driving voltages supplied to the pixel array layer 1530 are applied.

[0376] The shielding layer 1520 can electrically connect the metal disposed on the pixel array layer 1530 and the metal (power supply line) disposed on the base circuit layer 1510 .

[0377] The pixel array layer 1530 may include a sub-pixel circuit layer SPCL in which a plurality of sub-pixel circuits SPC are arranged, and a light-emitting element layer EDL in which a plurality of light-emitting elements ED are arranged.

[0378] Referring to FIG. 15, a display panel 110 according to an embodiment of the present disclosure may include a gate-in-panel circuit GIPC configured to provide gate signals to a plurality of sub-pixels SP and overlapping the organic film PCL of the encapsulation layer 200.

[0379] Referring to FIG. 15, the display panel 110 according to an embodiment of the present disclosure may further include a base circuit layer 1510 on a substrate 111, a light-emitting element layer EDL located on the base circuit layer 1510 and including a plurality of light-emitting elements ED included in a plurality of subpixels SP, and a shielding layer 1520 located between the base circuit layer 1510 and the light-emitting element layer EDL.

[0380] 15, the sub-pixel circuit layer SPCL may be disposed between a shielding layer 1520 and a light-emitting element layer EDL. The sub-pixel circuit layer SPCL and the light-emitting element layer EDL may form a pixel array layer 1530.

[0381] Referring to FIG. 15, a base circuit layer 1510 may include a gate-in-panel circuit GIPC disposed in the display area DA.

[0382] FIG. 16 is a cross-sectional view of a display area DA of a display panel 110 according to an embodiment of the present disclosure.

[0383] Referring to FIG. 16, the display area DA of the display panel 110 may include a substrate 111 , a base circuit layer 1510 , a shielding layer 1520 , a pixel array layer 1530 and an encapsulation layer 200 .

[0384] The substrate 111 may include a first substrate 1601, an intermediate layer 1602, and a second substrate 1603. The intermediate layer 1602 may be disposed between the first substrate 1601 and the second substrate 1603. For example, at least one of the first substrate 1601 and the second substrate 1603 may be a substrate including polyimide (PI).

[0385] A base circuit layer 1510 may be located on the substrate 111 .

[0386] The base circuit layer 1510 may include a lower shield metal 1605, a plurality of gate drive transistors Tg constituting the gate drive circuit 130, and various insulating films 1610, 1620, 1621 for forming the plurality of gate drive transistors Tg.

[0387] Each of the multiple gate driving transistors Tg may include a first active layer ACT1, a first source electrode A, a first drain electrode B and a first gate electrode C.

[0388] The various insulating layers 1611 , 1612 , 1620 , and 1621 may include a first buffer layer 1610 , a first gate insulating layer 1620 , and a first interlayer insulating layer 1621 .

[0389] A bottom shield metal 1605 may be disposed on the substrate 111 .

[0390] A first buffer layer 1610 may be disposed on the bottom shield metal 1605 .

[0391] The first buffer layer 1610 may include a multi-buffer layer 1611 and an active buffer layer 1612. The multi-buffer layer 1611 may be disposed on the lower shield metal 1605, and the active buffer layer 1612 may be disposed on the multi-buffer layer 1611.

[0392] A first active layer ACT1 may be disposed on the active buffer layer 1612.

[0393] A first gate insulating film 1620 may be disposed on the first active layer ACT1.

[0394] The first gate electrode C is disposed on the first gate insulating film 1620 and can overlap a portion of the first active layer ACT1. The portion of the first active layer ACT1 that overlaps with the first gate electrode C may be a channel region.

[0395] The first interlayer insulating film 1621 may be disposed on the first gate electrode C.

[0396] The first source electrode A and the first drain electrode B may be disposed on the first interlayer insulating film 1621. The first source electrode A may be directly or indirectly connected to a first portion of the first active layer ACT1 through a first hole in the first interlayer insulating film 1621. The first drain electrode B may be directly or indirectly connected to a second portion of the first active layer ACT1 through a second hole in the first interlayer insulating film 1621. A region between the first and second portions of the first active layer ACT1 may be a channel region.

[0397] The transistor included in the gate drive circuit 130 is referred to as a gate drive transistor Tg. The transistor included in the gate drive circuit 130 may include a pull-up transistor Tu and a pull-down transistor Td included in the output buffer 1310, and a plurality of transistors included in the control circuit 1320.

[0398] The base circuit layer 1510 may include not only the gate driving circuit 130 but also a plurality of power supply lines PL1 to PLm to which a plurality of pixel driving voltages are applied to the pixel array layer 1530. The plurality of power supply lines PL1 to PLm may include a second power supply line PL2 to which a second driving voltage VSS is applied to the pixel array layer 1530.

[0399] The base circuit layer 1510 may include an intermediate organic film 1622 disposed on a plurality of gate drive transistors Tg included in the gate drive circuit 130.

[0400] The intermediate organic film 1622 is disposed on the gate driving transistors Tg and the power lines PL1 to PLm included in the gate driving circuit 130, and can reduce steps in the base circuit layer 1510.

[0401] Additionally, the intermediate organic film 1622 can reduce unnecessary parasitic capacitance between metal disposed on the base circuit layer 1510 and metal disposed within the base circuit layer 1510 .

[0402] The upper surface of the intermediate organic film 1622 may have a smaller step than the rear surface of the intermediate organic film 1622 .

[0403] The intermediate organic film 1622 may have a thickness T that is greater than the thickness of the first gate insulating film 1620 between the first gate electrode C and the first active layer ACT1 of each of the plurality of gate driving transistors Tg.

[0404] The shielding layer 1520 may be disposed on the base circuit layer 1510, and the pixel array layer 1530 may be disposed on the shielding layer 1520. That is, the shielding layer 1520 may be located between the base circuit layer 1510 and the pixel array layer 1530. This allows for shielding of the electric field between the base circuit layer 1510 and the pixel array layer 1530.

[0405] The shielding layer 1520 may be electrically connected to a second power line PL2, which is one of the two or more power lines PL1 to PLm, through a hole in the intermediate organic film 1622. The second power line PL2 may be a power line to which a second driving voltage VSS is applied.

[0406] The power lines PL1 to PLm disposed in the base circuit layer 1510 may include the same material as the first source electrode A and the first drain electrode B of the gate driving transistor Tg.

[0407] The pixel array layer 1530 may include a plurality of pixel driving transistors TP, a plurality of storage capacitors Cst, and a plurality of light emitting elements ED.

[0408] The pixel array layer 1530 may include a second buffer layer 1630, a second interlayer insulating film 1631, a third interlayer insulating film 1632, a second gate insulating film 1633, a fourth interlayer insulating film 1634, a planarization film 1640, a bank BK, a spacer SPCR, etc. Here, the planarization film 1640 may include a first planarization film 1641 and a second planarization film 1642.

[0409] Each of the plurality of pixel driving transistors TP may include a second active layer ACT2, a second source electrode D, a second drain electrode E and a second gate electrode F.

[0410] Each of the plurality of storage capacitors Cst may include a first capacitor electrode PLT1 and a second capacitor electrode PL2.

[0411] Each of the plurality of light-emitting elements ED can include an anode AND1, AND2, an element intermediate layer EL, and a cathode CAT.

[0412] A second buffer layer 1630 can be disposed on the shielding layer 1520 .

[0413] A first capacitor electrode PLT1 may be disposed on the second buffer layer 1630, a second interlayer insulating film 1631 may be disposed on the first capacitor electrode PLT1, and a second capacitor electrode PLT2 may be disposed on the second interlayer insulating film 1631.

[0414] The first capacitor electrode PLT1 and the second capacitor electrode PLT2 may overlap each other to form a storage capacitor Cst.

[0415] A third interlayer insulating film 1632 can be disposed on the second capacitor electrode PLT2.

[0416] The second active layer ACT2 can be disposed on the third interlayer insulating film 1632.

[0417] A second gate insulating film 1633 may be disposed on the second active layer ACT2, and a second gate electrode F may be disposed on the second gate insulating film 1633. The second gate electrode F may overlap a portion of the second active layer ACT2. In the second active layer ACT2, a region overlapping with the second gate electrode F may be a channel region.

[0418] A fourth interlayer insulating film 1634 may be disposed on the second gate electrode F, and a second source electrode E and a second drain electrode D may be disposed on the fourth interlayer insulating film 1634.

[0419] The second source electrode E can be electrically connected to a first portion of the second active layer ACT2 through a first hole in the fourth interlayer insulating film 1634, and the second drain electrode D can be electrically connected to a second portion of the second active layer ACT2 through a second hole in the fourth interlayer insulating film 1634. The region between the first and second portions of the second active layer ACT2 can be a channel region.

[0420] The planarization film 1640 may be disposed on the second source electrode E and the second drain electrode D. The anodes AND1 and AND2 may be disposed on the planarization film 1640 and electrically connected to the second source electrode E or the second drain electrode D through holes in the planarization film 1640.

[0421] When the planarization film 1640 includes a first planarization film 1641 and a second planarization film 1642, the first planarization film 1641 is disposed on the second source electrode E and the second drain electrode D, and the relay electrode RE is disposed on the first planarization film 1641 and can be electrically connected to the second source electrode E or the second drain electrode D through a hole in the first planarization film 1641. The second planarization film 1642 can be disposed on the relay electrode RE. The anodes AND1 and AND2 are disposed on the second planarization film 1642 and can be electrically connected to the relay electrode RE through a hole in the second planarization film 1642.

[0422] If the subpixel SP has the same structure as in FIG. 2, the pixel driving transistor TP shown in FIG. 16 may be the driving transistor DT in FIG. 2, since the pixel driving transistor TP shown in FIG. 16 includes a second source electrode E electrically connected to the anodes AND1 and AND2 of the light-emitting element ED.

[0423] The bank BK is disposed on the anodes AND1 and AND2, and can have an opening corresponding to the light emitting area EA.

[0424] The element intermediate layer EL is disposed on the bank BK and can be in contact with the anodes AND1 and AND2 at the openings of the bank BK. The spacer SPCR can be located on the bank BK at some locations (for example, locations overlapping with the anodes AND1 and AND2, or at the boundaries of the light-emitting areas EA).

[0425] The cathode CAT can be disposed on the device intermediate layer EL.

[0426] The overlapping regions of the anodes AND1, AND2, the element intermediate layer EL, and the cathode CAT can form the light-emitting regions EA1, EA2. In Fig. 16, the common intermediate layer EL_COM is shown together with the first common intermediate layer COM1 and the second common intermediate layer COM2 included in the element intermediate layer EL, and the first light-emitting layer EML1 and the second light-emitting layer EML2 are omitted.

[0427] The encapsulation layer 200 may be disposed over the pixel array layer 1530 .

[0428] The encapsulation layer 200 may include a first inorganic film PAS1, an organic film PCL, and a second inorganic film PAS2. For example, the first inorganic film PAS1 and the second inorganic film PAS2 may be inorganic films, and the organic film PCL may be an organic film.

[0429] The first metal GA in the base circuit layer 1510 and the second metal GB in the pixel array layer 1530 can be electrically connected through the opening in the shielding layer 1520.

[0430] In addition, the first metal GA in the base circuit layer 1510 and the second metal GB in the pixel array layer 1530 can be electrically connected through a connection metal GCP separated from the shielding layer 1520. Here, the connection metal GCP can include the same material as the shielding layer 1520 and be located in the same layer as the shielding layer 1520. The connection metal GCP is also referred to as a gate link wiring GCP.

[0431] The second metal GB in the pixel array layer 1530 may be disposed on the second gate insulating film 1633. The second metal GB may include the same material as the second gate electrode F and may be located in the same layer.

[0432] The first metal GA in the base circuit layer 1510 can be disposed on the first interlayer insulating film 1621. The second metal GB in the pixel array layer 1530 can be electrically connected to the first metal GA in the base circuit layer 1510 through the second buffer layer 1630, the second interlayer insulating film 1631, the third interlayer insulating film 1632, the second gate insulating film 1633, the shielding layer 1520, and a hole in the organic film 1622.

[0433] The first metal GA in the base circuit layer 1510 may be a metal that electrically corresponds to the output nodes Nout1a, Nout1b, Nout1, and Nout2 in the base circuit layer 1510 in FIGS.

[0434] The second metal GB in the pixel array layer 1530 may be a metal electrically corresponding to the input nodes Nin1 and Nin2 in the pixel array layer 1530 in Figures 11 and 12. For example, the second metal GB in the pixel array layer 1530 may be any one of the first scan line SCL1, the second scan line SCL2, the third scan line SCL3, the first light-emitting control line EML1, and the second light-emitting control line EML2.

[0435] Referring to FIG. 16, the base circuit layer 1510 may include a gate driving transistor Tg including a first active layer ACT1, and the pixel array layer 1530 may include a pixel driving transistor TP including a second active layer ACT2.

[0436] The first active layer ACT1 and the second active layer ACT2 may include different semiconductor materials. For example, the first active layer ACT1 may include a silicon-based semiconductor material. The second active layer ACT2 may include an oxide-based semiconductor material.

[0437] For example, the silicon-based semiconductor material may include amorphous silicon (a-Si) or LTPS (Low-Temperature Polycrystalline Silicon), etc. For example, the oxide-based semiconductor material may include IGZO (Indium gallium zinc oxide), IGZTO (Indium gallium zinc tin oxide), ZnO (zinc oxide), CdO (cadmium oxide), InO (indium oxide), ZTO (zinc tin oxide), ZITO (zinc indium tin oxide), etc., and may also include LTPO (Low-Temperature Polycrystalline Oxide).

[0438] The first active layer ACT1 and / or the second active layer ACT2 may be a single layer or a multi-layer. For example, when the first active layer ACT1 and / or the second active layer ACT2 are a multi-layer, the multi-layer may be made of the same semiconductor material or may be made of two or more different semiconductor materials.

[0439] Referring to FIG. 16, the encapsulation layer 200 and the cathode CAT may overlap the gate drive circuit 130.

[0440] 16, the cathode CAT may be an electrode capable of transmitting light. The anodes AND1 and AND2 may be reflective electrodes and may overlap at least a portion of the gate driving circuit 130. This allows the display panel 110 to have a structure capable of top emission.

[0441] Referring to FIG. 16, a second driving voltage VSS may be applied to a shielding layer 1510 included in a display panel 110 according to an embodiment of the present disclosure.

[0442] Referring to FIG. 16, the shielding layer 1520 may be electrically connected to a cathode CAT to which a second driving voltage VSS, which is one type of pixel driving voltage, is applied.

[0443] The cathode CAT and the shielding layer 1520 may be electrically connected through a first connection pattern CP1 and a second connection pattern CP2. The first connection pattern CP1 may be a metal disposed on the fourth interlayer insulating film 1634. The first connection pattern CP1 may be connected to the shielding layer 1520 through holes in the second buffer layer 1630, the second interlayer insulating film 1631, the third interlayer insulating film 1632, the second gate insulating film 1633, and the fourth interlayer insulating film 1634. The second connection pattern CP2 may be a metal disposed on the first planarization film 1641. The second connection pattern CP2 may be connected to the first connection pattern CP1 through holes in the first planarization film 1641.

[0444] The first connection pattern CP1 and the second connection pattern CP2 may be electrically connected to a second driving voltage line VSSL disposed on the pixel array layer 1530. At least one of the first connection pattern CP1 and the second connection pattern CP2 may be the second driving voltage line VSSL disposed on the pixel array layer 1530.

[0445] The cathode CAT in the pixel array layer 1530 and the second power line PL2 in the base circuit layer 1510 can be electrically connected via the first and second connection patterns CP1, CP2 and the shielding layer 1520.

[0446] Referring to FIG. 16, a second common driving voltage line VSSL is disposed on the substrate 111 and can supply a second common pixel driving voltage VSS to the cathode CAT.

[0447] The second common driving voltage line VSSL may be disposed in the display area DA. The cathode CAT may be electrically connected to the second common driving voltage line VSSL in the display area DA. This may further reduce the size of the non-display area NDA.

[0448] 16, a voltage having a certain voltage level may be applied to the shielding layer 1520. For example, a second common pixel driving voltage VSS may be applied to the shielding layer 1520. To this end, the shielding layer 1520 may be electrically connected to the cathode CAT and electrically connected to the second common driving voltage line VSSL.

[0449] Referring to FIG. 16, the bank BK is located on the insulating film stack INS and may have a first opening and a second opening.

[0450] The first anode AND1 and the second anode AND2 are located on the insulating film stack INS and may overlap the first opening and the second opening, respectively.

[0451] A first common intermediate layer COM1 may be commonly disposed on the first anode AND1 and the second anode AND2.

[0452] The first light emitting layer EML1 and the second light emitting layer EML2 are located on the first common intermediate layer COM1 and can overlap the first anode AND1 and the second anode AND2.

[0453] A second common intermediate layer COM2 may be disposed in common on the first light-emitting layer EML1 and the second light-emitting layer EML2.

[0454] In FIG. 16, the common intermediate layer EL_COM including the first common intermediate layer COM1 and the second common intermediate layer COM2 is shown, and the first light-emitting layer EML1 and the second light-emitting layer EML2 are omitted.

[0455] Referring to FIG. 16, the cathode CAT can be located on the common intermediate layer EL_COM.

[0456] Referring to FIG. 16, the cathode CAT and the second common driving voltage line VSSL can be electrically connected through a hole penetrating at least a portion of the common intermediate layer EL_COM including the first common intermediate layer COM1 and the second common intermediate layer COM2, the bank BK, and the insulating film stack INS.

[0457] The sub-pixel circuit layer SPCL is located between the shielding layer 1520 and the light-emitting element layer EDL, and may include a plurality of sub-pixel circuits SPC for driving a plurality of light-emitting elements ED.

[0458] 16, the gate link wiring GCP can connect a gate-in-panel circuit GIPC and a plurality of sub-pixel circuits SPC arranged in the base circuit layer 1520. The gate link wiring GCP can overlap the organic film PCL of the encapsulation layer 200.

[0459] 17 and 18 show vertical and planar structures of a display panel 110 when a gate-in-panel circuit GIPC is disposed in a part of a display area DA of the display panel 110 according to an embodiment of the present disclosure.

[0460] 17 and 18, the display area DA of the display panel 110 can include a first display area DA1 and a second display area DA2. As shown in Fig. 17 and 18, the first display area DA1 can be disposed on both one side and the other side of the second display area DA2. Alternatively, the first display area DA1 can be disposed on only one side or the other side of the second display area DA2.

[0461] 17 and 18, a display panel 110 according to an embodiment of the present disclosure may include a substrate 111, a base circuit layer 1710, a light emitting element layer EDL, and an encapsulation layer 200.

[0462] 17 and 18, a base circuit layer 1710 may be located on a substrate 111 and may include a gate-in-panel circuit GIPC. The base circuit layer 1710 may further include a sub-pixel circuit array SPCA including a plurality of sub-pixel circuits SPC for driving a plurality of light-emitting elements ED, in addition to the gate-in-panel circuit GIPC.

[0463] 17 and 18, the light emitting element layer EDL may be disposed on a base circuit layer 1710. A plurality of light emitting elements ED may be disposed in the light emitting element layer EDL.

[0464] 17 and 18, the gate-in-panel circuit GIPC may be disposed in a first display area DA1, and the sub-pixel circuit array SPCA may be disposed in a second display area DA2. In the first display area DA1, the gate-in-panel circuit GIPC may overlap with the organic film PCL.

[0465] Referring to Figures 17 and 18, the multiple light-emitting elements ED arranged in the light-emitting element layer EDL may include two or more first light-emitting elements ED arranged in the first display area DA1 and two or more second light-emitting elements ED arranged in the second display area DA2.

[0466] 17 and 18, at least a portion of the two or more first light-emitting elements ED arranged in the first display area DA1 may overlap at least a portion of the gate-in-panel circuit GIPC, and at least a portion of the two or more second light-emitting elements ED arranged in the second display area DA2 may overlap at least a portion of the sub-pixel circuit array SPCA.

[0467] Referring to FIG. 17, the display panel 110 according to the embodiment of the present disclosure may further include an anode extension link layer 1730 between the base circuit layer 1710 and the light emitting element layer EDL.

[0468] Anode extension links (also referred to as extension links or connection patterns, AEL in FIG. 20) may be arranged on the anode extension link layer 1730. The anode extension links may electrically connect the sub-pixel circuits SPC included in the sub-pixel circuit array SPC arranged in the second display area DA2 to the first light-emitting element ED arranged in the first display area DA1.

[0469] As described above, in the display panel 110 according to an embodiment of the present disclosure, the gate-in-panel circuit GIPC is not disposed in the non-display area NDA but is disposed in the first display area DA1 included in the display area DA, so that the bezel corresponding to the non-display area NDA can be made smaller.

[0470] Referring to FIG. 17, the display panel 110 according to the embodiment of the present disclosure may further include a shielding layer 1720 located between the gate-in-panel circuit GIPC included in the base circuit layer 1710 and the light emitting element layer EDL.

[0471] Referring to FIG. 17, the shielding layer 1720 may be disposed in the first display area DA1 and located between the anode extension link layer 1730 and the gate-in-panel circuit GIPC.

[0472] At least a portion of the shielding layer 1720 can overlap the extension links (anode extension links) and the gate-in-panel circuit GIPC disposed in the anode extension link layer 1730. This allows the anode extension links AEL and the gate-in-panel circuit GIPC electrically connected to the anode AND to not have an undesired electrical effect on each other, which can improve image quality.

[0473] FIG. 19 is a plan view of a partial area 1800 of the display panel 110 of FIG.

[0474] 19, the display panel 110 includes a display area DA and a non-display area NDA1, and the display area DA may include a first display area DA1 and a second display area DA2. The non-display area NDA is also called a bezel.

[0475] Referring to FIG. 19, a first display area DA1 may be located between a non-display area NDA and a second display area DA2.

[0476] 19, the display area DA may include a plurality of light-emitting elements ED. For example, the plurality of light-emitting elements ED may include a red light-emitting element ED_R for emitting red light, a green light-emitting element ED_G for emitting green light, and a blue light-emitting element ED_B for emitting blue light.

[0477] Referring to FIG. 19, the plurality of light-emitting elements ED arranged in the display area DA may include a plurality of first light-emitting elements ED1 arranged in the first display area DA1 and a plurality of second light-emitting elements ED2 arranged in the second display area DA2.

[0478] 19, a sub-pixel circuit array SPCA may be disposed in the second display area DA2. The sub-pixel circuit array SPCA may include a plurality of sub-pixel circuits SPC.

[0479] The multiple sub-pixel circuits SPC may include at least one first sub-pixel circuit SPC for driving multiple first light-emitting elements ED1 arranged in the first display area DA1 and multiple second sub-pixel circuits SPC for driving multiple second light-emitting elements ED2 arranged in the second display area DA2.

[0480] In the first display area DA1, all or a part of the gate-in-panel circuit GIPC may be disposed.

[0481] In other words, the multiple light-emitting elements ED may include a first light-emitting element ED1 arranged in the first display area DA and overlapping at least a portion of the gate-in-panel circuit GIPC, and a second light-emitting element ED2 arranged in the second display area DA and overlapping at least a portion of the sub-pixel circuit array SPCA.

[0482] Referring to FIG. 19, the multiple subpixel circuits SPC included in the subpixel circuit array SPCA may include a first subpixel circuit SPC arranged in the second display area DA and configured to drive a first light-emitting element ED1 arranged in the first display area DA, and two or more second subpixel circuits SPC arranged in the second display area DA and configured to drive a second light-emitting element ED2 arranged in the second display area DA.

[0483] 19, the display panel 110 according to the embodiment of the present disclosure may include a link area LKA in which links for transmitting various gate signals output from the gate-in-panel circuit GIPC to the sub-pixel circuit array SPCA are arranged. For example, the links arranged in the link area LKA may electrically connect the output point of the gate-in-panel circuit GIPC and the gate line GL. When the output point of the gate-in-panel circuit GIPC is a first metal layer and the gate line GL is a second metal layer different from the first metal layer, the links may include jumping metals connecting the first metal layer and the second metal layer to each other.

[0484] 19, the link area LKA may be located between the gate-in-panel circuit GIPC and the sub-pixel circuit array SPCA. The link area LKA may be included in the first display area DA1.

[0485] Referring to FIG. 19, a display panel 110 according to an embodiment of the present disclosure may include a crack management area CRA in which crack detection wiring and / or crack stopper patterns are arranged.

[0486] 19, the crack management area CRA may be included in the non-display area NDA. In this case, the crack detection wiring and / or the crack stopper pattern may not overlap with the first light-emitting element ED1 arranged in the first display area DA1.

[0487] As another example, the crack management area CRA may be included in the first display area DA1. In this case, the crack detection wiring and / or the crack stopper pattern may overlap the first light emitting element ED1 arranged in the first display area DA1.

[0488] Referring to FIG. 19, the display panel 110 according to the embodiment of the present disclosure may further include a base voltage line area VSSA in which the base voltage line VSSL is arranged.

[0489] 19, in the display panel 110 according to the embodiment of the present disclosure, the base voltage line VSSL may be disposed in the display area DA. For example, the base voltage line VSSL may be disposed in at least one of the first display area DA1 and the second display area DA2 included in the display area DA. Thus, the cathode CAT may be electrically connected to the base voltage line VSSL in at least one of the first display area DA1 and the second display area DA2 included in the display area DA.

[0490] Therefore, the base voltage line area VSSA does not need to exist in the non-display area NDA, which can further reduce the size of the bezel between the trimming line TRL and the display area DA.

[0491] FIG. 20 shows the correspondence between the sub-pixel circuits SPC1, SPC2_TRANS, SPC2 and the light-emitting elements ED1, ED2 in the display panel 110 according to the embodiment of the present disclosure.

[0492] 20, from the perspective of a planar structure, the display panel 110 may include a display area DA and a non-display area NDA. The display area DA may include a first display area DA1 and a second display area DA2.

[0493] Referring to FIG. 20, from the perspective of a vertical structure, the display panel 110 may include a base circuit layer 1710 and a light emitting element layer EDL.

[0494] 20, in the base circuit layer 1710, all or most of the gate-in-panel circuit GIPC can be disposed in the first display area DA1. In the base circuit layer 1710, the sub-pixel circuit array SPCA including the sub-pixel circuits SPC1, SPC2_TRANS, and SPC2 can be disposed in the second display area DA2.

[0495] Referring to FIG. 20, in the base circuit layer 1710, the link area LKA can be disposed in the first display area DA1 or the second display area DA2, or disposed across the first display area DA1 and the second display area DA2.

[0496] 20, a plurality of light-emitting elements ED arranged in the light-emitting element layer EDL may be arranged in a display area DA. The plurality of light-emitting elements ED arranged in the light-emitting element layer EDL may include a plurality of first light-emitting elements ED1 arranged in the first display area DA1 and a plurality of second light-emitting elements ED2 arranged in the second display area DA2.

[0497] Referring to FIG. 20, the multiple subpixel circuits SPC included in the subpixel circuit array SPCA may include at least one first subpixel circuit SPC1 configured to drive a plurality of first light-emitting elements ED1 arranged in the first display area DA1, and a plurality of second subpixel circuits SPC2 configured to drive a plurality of second light-emitting elements ED2 arranged in the second display area DA2.

[0498] Referring to FIG. 20, a plurality of subpixel circuits SPC included in the subpixel circuit array SPCA can be classified into a first group GR1[1:n], a transition group GR_TRANS[1:n], and a second group GR2[1:1].

[0499] 20, the second group GR2[1:1] may include a plurality of second sub-pixel circuits SPC2. The second group GR2[1:1] may drive one second light-emitting element ED2 arranged in the second display area DA2 in a one-to-one (1:1) driving manner.

[0500] Each of the second subpixel circuits SPC2 included in the second group GR2[1:1] can drive one second light-emitting element ED2 arranged in the second display region DA2. That is, one second subpixel circuit SPC2 included in the second group GR2[1:1] can drive one second light-emitting element ED2 arranged in the second display region DA2. This allows the second anode AND2 of one second light-emitting element ED2 to be connected one-to-one to one second subpixel circuit SPC2.

[0501] 20, the first group GR1[1:n] may include a plurality of first sub-pixel circuits SPC1. The first group GR1[1:n] may drive two or more first light-emitting elements ED1 arranged in the first display area DA1 in a one-to-many driving manner or a common driving manner.

[0502] Each of the plurality of first sub-pixel circuits SPC1 included in the first group GR1[1:n] can drive two or more first light-emitting elements ED1 arranged in the first display region DA1 together, that is, one first sub-pixel circuit SPC1 included in the first group GR1[1:n] can drive two or more first light-emitting elements ED1 arranged in the first display region DA1 together.

[0503] For example, as shown in FIG. 20, one first subpixel circuit SPC1 included in a first group GR1[1:n] can jointly drive two first light-emitting elements ED1 arranged in a first display area DA1.

[0504] Referring to FIG. 20, in order for one first sub-pixel circuit SPC1 arranged in the second display area DA2 to drive two or more first light-emitting elements ED1 arranged in the first display area DA1 together, the display panel 110 according to an embodiment of the present disclosure may further include an anode extension link AEL for connecting one first sub-pixel circuit SPC1 arranged in the second display area DA2 to two or more first light-emitting elements ED1 arranged in the first display area DA1.

[0505] The anode extension link AEL may be disposed in the anode extension link layer 320 located between the base circuit layer 1710 and the light emitting element layer EDL. Thus, the anode extension link AEL may include a metal (anode extension link layer metal) located between the base circuit layer 1710 and the light emitting element layer EDL.

[0506] Referring to FIG. 20, some of the multiple first sub-pixel circuits SPC1 included in the first group GR1[1:n] may be connected to one scan line SCL and may be supplied with a scan signal SC from the one scan line SCL.

[0507] Referring to FIG. 20, two or more first light emitting elements ED1 driven together by one first sub-pixel circuit SPC1 included in a first group GR1[1:n] may emit light of the same color.

[0508] Referring to FIG. 20, one first sub-pixel circuit SPC1 included in the first group GR1[1:n] is supplied with a scan signal SC and a data signal VDATA, and can drive two or more first light-emitting elements ED1 together based on the scan signal SC and the data signal VDATA.

[0509] 20, the transition group GR_TRANS[1:n] may include a plurality of transition subpixel circuits SPC2_TRASN, and the transition group GR_TRANS[1:n] may drive two or more second light-emitting elements ED2 arranged in the second display area DA2 in a one-to-many driving manner or a common driving manner.

[0510] Each of the transition subpixel circuits SPC2_TRASN included in the transition group GR_TRANS[1:n] can drive two or more second light-emitting elements ED2 arranged in the second display area DA2. That is, one transition subpixel circuit SPC2_TRASN included in the transition group GR_TRANS[1:n] can drive two or more second light-emitting elements ED2 arranged in the second display area DA2.

[0511] Referring to FIG. 20, two or more second light-emitting elements ED2 driven together by one transition sub-pixel circuit SPC2_TRASN according to the one-to-many driving scheme may be adjacent light-emitting elements ED emitting light of the same color.

[0512] According to the one-to-many driving method, two or more second light-emitting elements ED2 driven together by one transition subpixel circuit SPC2_TRASN emit light of the same color, and are configured with adjacently arranged light-emitting elements ED, so that the two or more second light-emitting elements ED2 exhibit similar light-emitting characteristics. Therefore, the image quality by the one-to-many driving can have the same level as that by the one-to-one driving.

[0513] Referring to FIG. 20, in order for one transition subpixel circuit SPC2_TRASN arranged in the second display area DA2 to drive two or more second light-emitting elements ED2 arranged in the second display area DA1 together, the display panel 110 according to an embodiment of the present disclosure may further include a transition anode extension link AEL for connecting one transition subpixel circuit SPC2_TRASN arranged in the second display area DA2 to two or more second light-emitting elements ED2 arranged in the second display area DA2.

[0514] Referring to FIG. 20, the second light-emitting element ED2 driven by the transition subpixel circuit SPC2_TRASN included in the transition group GR_TRANS[1:n] may be arranged adjacent to the first light-emitting element ED1 driven by the first subpixel circuit SPC1 included in the first group GR1[1:n].

[0515] Referring to FIG. 20, the second light-emitting element ED2 driven by the transition subpixel circuit SPC2_TRASN included in the transition group GR_TRANS[1:n] can be arranged between the first light-emitting element ED1 driven by the first subpixel circuit SPC1 included in the first group GR1[1:n] and the second light-emitting element ED2 driven by the second subpixel circuit SPC2 included in the second group GR2[1:1].

[0516] Referring to FIG. 20, the transition group GR_TRANS[1:n] can be placed between the first group GR1[1:n] and the second group GR2[1:1].

[0517] As described above, the extension link AEL can connect the first sub-pixel circuit SPC1 arranged in the second display area DA to the first light-emitting element ED1 arranged in the first display area DA. At least a portion of the extension link AEL can overlap at least a portion of the gate-in-panel circuit GIPC, and the extension link AEL can overlap the organic film PCL.

[0518] FIG. 21 is a cross-sectional view showing a vertical structure of a display panel 110 according to an embodiment of the present disclosure.

[0519] 21, a display panel 110 according to an embodiment of the present disclosure may include a display area DA and a non-display area NDA. The display area DA may include a first display area DA1 and a second display area DA2. The first display area DA1 may be located between the second display area DA2 and the non-display area NDA.

[0520] Referring to FIG. 21, a display panel 110 according to an embodiment of the present disclosure may include a substrate 111 , a base circuit layer 1710 on the substrate 111 , and a light emitting element layer EDL on the base circuit layer 1710 .

[0521] The display panel 110 according to the embodiment of the present disclosure may further include at least one insulating layer disposed between the base circuit layer 1710 and the light emitting element layer EDL.

[0522] For example, as shown in Fig. 21, first to third insulating layers INS1, INS2, and INS3 may be disposed between the base circuit layer 1710 and the light emitting element layer EDL. For example, the first insulating layer INS1 may be an inorganic film or an organic film. The second insulating layer INS2 and the third insulating layer INS3 may serve as planarizing films and may be organic films.

[0523] Referring to FIG. 21, a sub-pixel circuit array SPCA, a link area LKA, a gate-in-panel circuit GIPC, etc. may be disposed on a base circuit layer 1710.

[0524] The sub-pixel circuit array SPCA can be disposed in the second display area DA, the link area LKA can be disposed in the first display area DA, and the gate-in-panel circuit GIPC can be disposed in the first display area DA.

[0525] 21, a plurality of light-emitting elements ED may be arranged in the light-emitting element layer EDL. The plurality of light-emitting elements ED arranged in the light-emitting element layer EDL may include a plurality of first light-emitting elements ED1 arranged in the first display area DA1 and a plurality of second light-emitting elements ED2 arranged in the second display area DA2.

[0526] Two or more first light-emitting elements ED1 arranged in the first display area DA1 can be driven in a one-to-many driving manner (common driving manner) by at least one first subpixel circuit SPC1 of the multiple subpixel circuits SPC included in the subpixel circuit array SPCA.

[0527] Most of the second light emitting elements ED2 arranged in the second display area DA2 can be driven in a one-to-one driving manner by the second sub-pixel circuit SPC2 among the sub-pixel circuits SPC included in the sub-pixel circuit array SPCA.

[0528] Some of the multiple second light-emitting elements ED2 arranged in the second display area DA2 can be driven in a common driving manner by a transition subpixel circuit SPC2_TRANS among the multiple subpixel circuits SPC included in the subpixel circuit array SPCA (see FIG. 7).

[0529] Referring to FIG. 21, the light-emitting element layer EDL may include two or more first anodes AND1 arranged in the first display area DA1 and two or more first emission layers EML1 arranged in the first display area DA1 and positioned respectively on the two or more first anodes AND1.

[0530] Referring to FIG. 21, the light-emitting element layer EDL may include two or more second anodes AND2 arranged in the second display area DA2 and two or more second light-emitting layers EML2 arranged in the second display area DA2 and positioned respectively on the two or more second anodes AND2.

[0531] 21, the light emitting element layer EDL is disposed across the first display area DA1 and the second display area DA2 and may include a cathode CAT located on two or more first emission layers EML1 and two or more second emission layers EML2. A base voltage VSS, which is a second driving voltage, may be applied to the cathode CAT.

[0532] Referring to FIG. 21, two or more first light-emitting elements ED1 may be configured in the first display area DA1 by two or more first anodes AND1, two or more first light-emitting layers EML1 and cathodes CAT.

[0533] Referring to FIG. 21, two or more second anodes AND2, two or more second light emitting layers EML2 and cathodes CAT may form two or more second light emitting elements ED2 in the second display area DA2.

[0534] 21, the first common layer COM1 and the second common layer COM2 can be disposed over the entire display area DA. The first common layer COM1 is located between the anodes AND1, AND2 and the light-emitting layers EML1, EML2, and can be disposed over the entire display area DA. The second common layer COM2 is located between the light-emitting layers EML1, EML2 and the cathode CAT, and can be disposed over the entire display area DA.

[0535] 21, in the display area DA, the light-emitting areas of the light-emitting elements ED1 and ED2 can be defined by openings in the bank BK. The bank BK is located on the anodes AND1 and AND2 and can have openings that expose parts of the anodes AND1 and AND2. The openings in the bank BK can be light-emitting areas. The bank BK can be a light-emitting portion defining film.

[0536] Referring to FIG. 21, the display panel 110 according to the embodiment of the present disclosure may include a connection metal structure for connection between the base circuit layer 1710 and the light emitting element layer EDL.

[0537] Referring to FIG. 21, the connection metal structure of the display panel 110 according to an embodiment of the present disclosure may include a first metal layer arranged between the first insulating layer INS1 and the second insulating layer INS2, a second metal layer arranged between the second insulating layer INS2 and the third insulating layer INS3, and a third metal layer arranged between the third insulating layer INS3 and the light-emitting element layer EDL.

[0538] Referring to FIG. 21, the display panel 110 according to an embodiment of the present disclosure may include a second anode connection structure for electrically connecting a second anode AND2 arranged in the light-emitting element layer EDL and a second subpixel circuit SPC2 arranged in the base circuit layer 1710 in a one-to-one manner.

[0539] 21, the second anode connection structure of the display panel 110 according to the embodiment of the present disclosure may include a second anode connection pattern CP_AND2. Each of the two or more second anodes AND2 may be electrically connected to a second sub-pixel circuit SPC2 disposed in the base circuit layer 1710 through the second anode connection pattern CP_AND2.

[0540] Referring to FIG. 21, the second anode connection pattern CP_AND2 may include a second metal connection pattern CP2_AND2 and a first metal connection pattern CP1_AND2.

[0541] 21, two or more second anodes AND2 may be disposed in the third metal layer. One second anode AND2 may be electrically connected to a second metal connection pattern CP2_AND2 disposed in the second metal layer through a hole in the third insulating layer INS3, the second metal connection pattern CP2_AND2 may be electrically connected to a first metal connection pattern CP1_AND2 disposed in the first metal layer through a hole in the second insulating layer INS2, and the first metal connection pattern CP1_AND2 may be electrically connected to a second subpixel circuit SPC2 disposed in the base circuit layer 1710 through a hole in the first insulating layer INS1.

[0542] Referring to FIG. 21, two or more first anodes AND1 can be electrically connected to a first subpixel circuit SPC1 arranged in the base circuit layer 1710 via an anode extension link AEL arranged in the anode extension link layer 1730.

[0543] Referring to FIG. 21, a display panel 110 according to an embodiment of the present disclosure may include a first anode connection structure for electrically connecting two or more first anodes AND1 arranged in the light-emitting element layer EDL and a first sub-pixel circuit SPC1 arranged in the base circuit layer 1710.

[0544] Referring to FIG. 21, a first anode connection structure of a display panel 110 according to an embodiment of the present disclosure may include an anode extension link AEL and an anode connection pattern CP1_AND1.

[0545] 21, two or more first anodes AND1 may be disposed in the third metal layer. The anode extension link layer 1730 may be the second metal layer on the second insulating layer INS2. The anode connection pattern CP1_AND1 may include a first metal connection pattern CP1_AND1 located in the first metal layer on the first insulating layer INS1.

[0546] 21, in the first display area DA1, each of the two or more first anodes AND1 may be electrically connected to one anode extension link AEL located in the second metal layer through a hole in the third insulating layer INS3, where the second metal layer may be the anode extension link layer 1730.

[0547] Referring to FIG. 21, the anode extension link AEL can be electrically connected to the first metal connection pattern CP1_AND1 located in the first metal layer through a hole in the second insulating layer INS2, and the first metal connection pattern CP1_AND1 can be electrically connected to the first subpixel circuit SPC1 arranged in the base circuit layer 1710 through a hole in the first insulating layer INS1.

[0548] 21, the anode extension link AEL may include a first portion electrically connecting to two or more first anodes AND1 located in the light emitting element layer EDL in the first display area DA1, and a second portion connecting to a first subpixel circuit SPC1 located in the base circuit layer 1710 in the second display area DA2. Here, the first portion may be located in the first display area DA1, and the second portion may be located in the second display area DA2.

[0549] 21, the anode extension link AEL may be disposed to extend in a planar manner from the first display area DA1 to the second display area DA2. The first anode connecting structure including the anode extension link AEL may be disposed vertically from the base circuit layer 1710 to the light emitting element layer EDL.

[0550] Referring to FIG. 21, in the base circuit layer 1710, the link area LKA may be located between the sub-pixel circuit array SPCA and the gate-in-panel circuit GIPC.

[0551] Referring to FIG. 21, a shielding layer 1720 may be disposed between a gate-in-panel circuit GIPC included in a base circuit layer 1710 and a light emitting element layer EDL.

[0552] A shielding layer 1720 can be disposed in the first display area DA1.

[0553] The shielding layer 1720 may be electrically connected to the cathode connection pattern CP_VSS, so that the base voltage VSS applied to the cathode CAT of the light emitting elements ED1 and ED2 may be applied to the shielding layer 1720.

[0554] The shielding layer 1720 is disposed in the first display area DA1 and may be located between the gate-in-panel circuit GIPC and the anode extension link AEL. The shielding layer 1720 may overlap the gate-in-panel circuit GIPC and the anode extension link AEL.

[0555] This prevents the anode extension link AEL from being electrically affected by the gate-in-panel circuit GIPC.This prevents the anode extension link AEL from being electrically affected by the gate-in-panel circuit GIPC.

[0556] Referring to FIG. 21, a display panel 110 according to an embodiment of the present disclosure may include a substrate 111 including a display area DA including a first display area DA1 and a second display area DA2, a non-display area NDA on the periphery of the display area DA, two or more first light-emitting elements ED1 arranged in the first display area DA1, two or more second light-emitting elements ED2 arranged in the second display area DA2, one first sub-pixel circuit SPC1 commonly connected to the two or more first light-emitting elements ED1, and two or more second sub-pixel circuits SPC2 respectively connected to the two or more second light-emitting elements ED2.

[0557] Referring to FIG. 21, the display panel 110 according to the embodiment of the present disclosure may further include a gate-in-panel circuit GIPC disposed in the first display area DA1.

[0558] Referring to FIG. 21, a display panel 110 according to an embodiment of the present disclosure may further include an extension link AEL for electrically connecting two or more first light emitting elements ED1 and one first sub-pixel circuit SPC1.

[0559] Referring to FIG. 21, the display panel 110 according to an embodiment of the present disclosure may further include a shielding layer 1720 disposed between the gate-in-panel circuit GIPC and the extension link AEL.

[0560] 21, in the display panel 110 according to the embodiment of the present disclosure, the base voltage line VSSL may be disposed in the display area DA. For example, the base voltage line VSSL may be disposed in at least one of the first display area DA1 and the second display area DA2 included in the display area DA. Thus, the cathode CAT can be electrically connected to the base voltage line VSSL in at least one of the first display area DA1 and the second display area DA2 included in the display area DA.

[0561] This means that the base voltage line area VSSA does not need to be present in the non-display area NDA, and therefore the bezel which is the non-display area NDA can be made smaller.

[0562] 21, in the display panel 110 according to the embodiment of the present disclosure, the base voltage line VSSL may be located in the display area DA. The display panel 110 according to the embodiment of the present disclosure includes a cathode connection structure for electrically connecting the cathode CAT and the base voltage line VSSL, and the cathode connection structure may be located in the display area DA.

[0563] For example, the base voltage line VSSL may be disposed in at least one of the first display area DA1 and the second display area DA2 included in the display area DA. Thus, the cathode CAT can be electrically connected to the base voltage line VSSL through a cathode connection structure located in at least one of the first display area DA1 and the second display area DA2 included in the display area DA.

[0564] 21, a cathode connection pattern CP_VSS, which is a cathode connection structure for connecting a cathode CAT and a base voltage line VSSL, may be located in a display area DA. That is, the cathode connection pattern CP_VSS may be located in at least one of a first display area DA1 and a second display area DA2 included in the display area DA.

[0565] Referring to FIG. 21, the cathode CAT can be electrically connected to the cathode connection pattern CP_VSS located under the bank BK through a hole in the bank BK located between two or more second anodes.

[0566] 21, the base voltage line VSSL may be located in a first metal layer on a first insulating layer INS1. The cathode connection pattern CP_VSS may include a first cathode connection pattern CP2_VSS located in a second metal layer on a second insulating layer INS2.

[0567] The cathode CAT can be electrically connected to the first cathode connection pattern CP2_VSS through the second common layer COM2, the first common layer COM1, the bank BK, and through holes in the third insulating layer INS3.

[0568] The first cathode connection pattern CP2_VSS may be electrically connected to the base voltage line VSSL located on the first insulating layer INS1 through a hole in the second insulating layer INS2.

[0569] Referring to FIG. 21, the through holes of the second common layer COM2, the first common layer COM1, the bank BK, and the third insulating layer INS3 may be formed by a laser drilling process.

[0570] As described above, the base voltage line VSSL and the cathode connection pattern CP_VSS, which is a cathode connection structure, do not need to be disposed in the non-display area NDA, which can further reduce the bezel to a minimum.

[0571] The display panel 110 according to the embodiment of the present disclosure may include a connection metal structure for connection between the base circuit layer 1710 and the light emitting element layer EDL, and may include three insulating layers INS1 to INS3 and three metal layers between the base circuit layer 1710 and the light emitting element layer EDL. Here, the three insulating layers INS1 to INS3 may be included in an insulating film stack INS. The three metal layers may include a first metal layer disposed between the first insulating layer INS1 and the second insulating layer INS2, a second metal layer disposed between the second insulating layer INS2 and the third insulating layer INS3, and a third metal layer disposed between the third insulating layer INS3 and the light emitting element layer EDL. Here, the third metal layer may be a metal layer in which the anodes AND1 and AND2 are disposed.

[0572] The display panel 110 according to the embodiment of the present disclosure may have a different connection metal structure between the base circuit layer 1710 and the light emitting element layer EDL than the connection metal structure (three insulating layers, three metal layers).

[0573] Referring to FIG. 21, a voltage having a constant voltage level may be applied to the shielding layer 1720 .

[0574] Referring to FIG. 21, the display panel 110 is disposed on a substrate 111 and may further include a base voltage line VSSL, which is a second common driving voltage line, for supplying a base voltage VSS, which is a second common pixel driving voltage, to the cathode CAT.

[0575] A base voltage line VSSL, which is a second common driving voltage line, can be disposed in the display area DA. The cathode CAT can be electrically connected to the base voltage line VSSL, which is the second common driving voltage line, in the display area DA.

[0576] The bank BK is located on the insulating film stack INS and can have a first opening and a second opening.

[0577] The first anode AND1 and the second anode AND2 are located on the insulating film stack INS and may overlap the first opening and the second opening, respectively.

[0578] The first common intermediate layer COM1 may be commonly disposed on the first anode AND1 and the second anode AND2.

[0579] The first light emitting layer EML1 and the second light emitting layer EML2 are located on the first common intermediate layer COM1 and can overlap the first anode AND1 and the second anode AND2.

[0580] The second common intermediate layer COM2 can be disposed in common on the first light-emitting layer EML1 and the second light-emitting layer EML2.

[0581] The first common intermediate layer COM1 and the second common intermediate layer COM2 may be combined to form a common intermediate layer EL_COM.

[0582] The cathode CAT may be located on the common intermediate layer EL_COM.

[0583] The cathode CAT and the base voltage line VSSL, which is a second common driving voltage line, can be electrically connected via a hole penetrating at least a portion of the second common intermediate layer COM2, the first common intermediate layer COM1, the bank BK, and the insulating film stack INS.

[0584] The first anode AND1, the first common intermediate layer COM1, the first light emitting layer EML1, the second common intermediate layer COM2, and the cathode CAT may be overlapped to form a first light emitting element ED1.

[0585] The second anode AND2, the first common intermediate layer COM1, the second light emitting layer EML2, the second common intermediate layer COM2, and the cathode CAT may be overlapped to form a second light emitting element ED2.

[0586] In FIGS. 17 to 21, one of the plurality of first light-emitting elements ED1 arranged in the first display region DA1 may be the outermost light-emitting element ED.

[0587] 21, a stopper STP may be disposed on an outer surface of a first light emitting element ED1, which is the outermost light emitting element ED. The stopper STP and its surrounding structure may be the same as those in FIG.

[0588] 21, the stopper STP may be disposed further outward than the organic film PCL of the encapsulation layer 200. The stopper STP may be disposed further outward than the bank BK.

[0589] Referring to FIG. 21, at least a portion of the stopper STP can overlap at least a portion of the gate-in-panel circuit GIPC disposed on the base circuit layer 1710.

[0590] The above-described embodiment of the present disclosure can be briefly described as follows.

[0591] A display device according to an embodiment of the present disclosure includes a substrate including a display region in which a plurality of subpixels are arranged and a non-display region including a pad region located in a first direction from the display region, an insulating film stack located on the substrate and having an outer surface in the non-display region, a stopper located on the insulating film stack, a cathode located on the insulating film stack and extending from the display region to a portion of the non-display region and overlapping an upper surface of at least a portion of the stopper, a first inorganic film located on the cathode and disposed extending from the display region to the non-display region, an organic film located on a portion of the first inorganic film and having an outer inclined surface, and a second inorganic film located on the organic film and disposed extending from the display region to the non-display region and disposed extending along the outer inclined surface of the organic film.

[0592] In the display device according to the embodiment of the present disclosure, the stopper may be disposed in the non-display region and may be located further outward than the organic film.

[0593] The display device according to the embodiments of the present disclosure may further include a bank located on the insulating film stack and having a plurality of openings, a plurality of anodes located on the insulating film stack and overlapping the plurality of openings, and a plurality of light-emitting layers located on the plurality of anodes.

[0594] The cathode is located on the plurality of light emitting layers, and the plurality of anodes, the plurality of light emitting layers and the cathode are overlapped to form a plurality of light emitting elements. The stopper may be located further outward than the bank.

[0595] The first inorganic film can extend along the top and exterior of the stopper and onto the exterior surface of the insulating film stack.

[0596] The second inorganic film may extend outwardly around the outer sloping surface of the organic film and overlie the first inorganic film that extends along the top and outside of the stopper and onto the outer surface of the insulating film stack.

[0597] The outer surface of the stopper may have a steeper slope than the inner surface of the stopper.

[0598] A display device according to an embodiment of the present disclosure may further include a bank located on the insulating film stack and having first to third openings, first to third anodes located on the insulating film stack and overlapping the first to third openings, respectively, and a first common intermediate layer commonly disposed on the first to third anodes, first to third light-emitting layers located on the first common intermediate layer and overlapping the first to third anodes, and a second common intermediate layer commonly disposed on the first to third light-emitting layers.

[0599] The common intermediate layer, including the first common intermediate layer and the second common intermediate layer, comprises an organic material, the cathode is located on the second common intermediate layer, and the common intermediate layer and the cathode can extend to the top of the stopper.

[0600] The display device according to the embodiment of the present disclosure may further include a capping layer disposed between the cathode and the first inorganic film and extending from the display area to the non-display area. The capping layer may extend along the top and outer sides of the stopper to the outer surface of the insulating film stack.

[0601] The stopper may include a first stopper on the insulating film stack and a second stopper on the first stopper. The first stopper may include the same material as the bank, and the second stopper may include the same material as the spacer located on the bank.

[0602] An end of the common intermediate layer and an end of the cathode are located on the stopper, and the end of the cathode may protrude further outward than the upper layer of the outer surface of the stopper (e.g., the outer surface of the second stopper) and the end of the common intermediate layer.

[0603] A lower end of the outer surface of the first stopper may protrude further outward than an upper end of the outer surface of the second stopper.

[0604] The stopper may include a cliff portion from the top to a point where the inclination of the outer surface becomes gentler or has a step below a certain level. The total height of the cliff portion of the stopper and the height of the common intermediate layer may be greater than the total thickness of the first inorganic film and the second inorganic film.

[0605] The stopper may be disposed on a side of an outermost light emitting device among a plurality of light emitting devices corresponding to a plurality of subpixels, and may have a thickness greater than that of the anode of the outermost light emitting device.

[0606] The width of the bottom surface of the stopper may be greater than the width of the top surface of the stopper.

[0607] A display device according to an embodiment of the present disclosure may further include a display signal wiring arranged in the display area, a display connection wiring electrically connecting the display signal wiring and a display pad arranged in the pad area, and a bending organic film located between the display area and the pad area.

[0608] A portion of the display connection wiring can overlap the bending organic film.

[0609] The non-display area may include a first non-display area located in a first direction from the display area, a second non-display area located in a second direction from the display area, a third non-display area located in an opposite direction from the display area in the first direction, and a fourth non-display area located in an opposite direction from the display area in the second direction. The pad area may be included in the first non-display area.

[0610] The stopper may be disposed in the non-display area and may be disposed in a ring shape surrounding the periphery of the organic film, and the stopper may be located between the display area and the pad area.

[0611] A display device according to an embodiment of the present disclosure may further include a first sensor electrode disposed on the second inorganic film and extending in a second direction, and a first touch routing wiring for electrically connecting the first sensor electrode to a first touch pad disposed in the pad region.

[0612] The first touch routing line may extend across the display area in a first direction to the first non-display area without bypassing the second non-display area and the fourth non-display area.

[0613] A portion of the first touch routing line extending into the first non-display area can overlap with a stopper in the first non-display area.

[0614] The display device according to the embodiment of the present disclosure may further include a gate-in-panel circuit configured to provide gate signals to the plurality of sub-pixels. The gate-in-panel circuit may be disposed on the substrate and overlap the organic film.

[0615] A display device according to an embodiment of the present disclosure may further include a base circuit layer on a substrate, a light emitting element layer located on the base circuit layer and including a plurality of light emitting elements included in a plurality of subpixels, and a shielding layer located between the base circuit layer and the light emitting element layer.

[0616] The base circuit layer can include gate-in-panel circuitry disposed in the display area.

[0617] A voltage having a constant voltage level may be applied to the shielding layer.

[0618] The display device according to the embodiment of the present disclosure may further include a common driving voltage line disposed on the substrate for supplying a common pixel driving voltage to the cathodes, the common driving voltage line being disposed in the display area, and the cathodes may be electrically connected to the common driving voltage line in the display area.

[0619] The display device according to the embodiment of the present disclosure may further include a sub-pixel circuit layer located between the shielding layer and the light-emitting element layer, the sub-pixel circuit layer including a plurality of sub-pixel circuits for driving a plurality of light-emitting elements, and a gate link wiring connecting a gate-in-panel circuit arranged in the base circuit layer to the plurality of sub-pixel circuits.

[0620] The gate link wiring can overlap the organic film.

[0621] The display area may include a first display area and a second display area.

[0622] The base circuit layer may further include a sub-pixel circuit array including a plurality of sub-pixel circuits for driving a plurality of light-emitting elements, as well as a gate-in-panel circuit.

[0623] The gate-in-panel circuitry can be disposed in a first display area, and the sub-pixel circuit array can be disposed in a second display area.

[0624] The plurality of light-emitting elements may include a first light-emitting element disposed in the first display region and overlapping at least a portion of the gate-in-panel circuitry, and a second light-emitting element disposed in the second display region and overlapping at least a portion of the sub-pixel circuit array.

[0625] The multiple subpixel circuits may include a first subpixel circuit configured to drive a first light-emitting element and disposed in the second display area, and two or more second subpixel circuits configured to drive a second light-emitting element and disposed in the second display area.

[0626] The display device according to the embodiment of the present disclosure may further include an extension link connecting a first sub-pixel circuit arranged in the second display area with a first light-emitting element arranged in the first display area.

[0627] At least a portion of the extension link can overlap at least a portion of the gate-in-panel circuitry. The extension link can overlap the organic film.

[0628] A display device according to an embodiment of the present disclosure may further include a base voltage line located in at least one of the first display area and the second display area, and a cathode connection pattern located in at least one of the first display area and the second display area, connecting the cathode and the base voltage line.

[0629] The display device according to the embodiment of the present disclosure may further include a patterning organic material disposed on an outer periphery of the stopper.

[0630] A display device according to an embodiment of the present disclosure may include a substrate, an insulating film stack on the substrate, a plurality of light-emitting elements on the insulating film stack, an organic film on the plurality of light-emitting elements, and a stopper disposed on an outer periphery of the organic film.

[0631] The stopper may be disposed on an outer surface of an outermost light emitting device among the plurality of light emitting devices, and may have a thickness greater than that of the anode of the outermost light emitting device.

[0632] The display device according to the embodiment of the present disclosure may further include a bank for separating the plurality of light emitting devices and a spacer on the bank.

[0633] The stopper can include a first stopper on the insulating film stack and a second stopper on the first stopper. The first stopper can include the same material as the bank, and the second stopper can include the same material as the spacer.

[0634] The outer surface of the stopper may have a steeper slope than the inner surface of the stopper.

[0635] According to the embodiment of the present disclosure described above, it is possible to provide a display device having an extremely narrow bezel structure.

[0636] According to an embodiment of the present disclosure, a display device having an organic film overflow prevention structure that enables an extremely narrow bezel can be provided.

[0637] According to an embodiment of the present disclosure, a display device can be provided that includes a gate-in-panel circuit structure that enables an extremely narrow bezel.

[0638] According to an embodiment of the present disclosure, a display device can be provided with a touch routing structure that allows for an extremely narrow bezel.

[0639] According to the embodiment of the present disclosure, the display device has an extremely narrow bezel structure, which enables the display device to be lightweight.

[0640] The above description is merely an illustrative example of the technical idea of ​​the present disclosure, and various modifications and variations are possible within the scope of the essential characteristics of the present disclosure, if one has ordinary knowledge in the technical field to which the present disclosure belongs. In addition, the examples disclosed in the present disclosure are intended to explain, rather than limit, the technical idea of ​​the present disclosure, and such examples do not limit the scope of the technical idea of ​​the present disclosure.

Claims

1. a substrate including a display area in which a plurality of sub-pixels are arranged, and a non-display area including a pad area located in a first direction from the display area; a dielectric film stack overlying the substrate, the dielectric film stack having an outer surface in the non-display region; a stopper located on the insulating film stack; a cathode located on the insulating film stack, extending from the display area to a portion of the non-display area and overlapping a top surface of at least a portion of the stopper; a first inorganic film disposed on the cathode and extending from the display area to the non-display area; an organic film located on a portion of the first inorganic film and having an outer inclined surface; and a second inorganic film disposed on the organic film, extending from the display area to the non-display area, and extending along the outer inclined surface; the stopper is disposed in the non-display area and positioned outside the organic film.

2. The display device according to claim 1 , further comprising a bank located on the insulating film stack for partitioning a plurality of light-emitting regions, the stopper being disposed on an outer periphery of the bank.

3. the first inorganic film extends along the top and outside of the stopper to the outer surface of the insulating film stack; The display device of claim 1 , wherein the second inorganic film extends around the outer sloping surface of the organic film and is positioned on the first inorganic film that extends along the top and outside of the stopper to the outer surface of the insulating film stack.

4. The display device according to claim 1 , wherein an outer surface of the stopper has a steeper inclination than an inner surface of the stopper.

5. a bank located on the insulating film stack, the bank having first to third openings; first, second, and third anodes disposed on the insulating film stack and overlapping the first, second, and third openings, respectively; a first common intermediate layer disposed in common on the first to third anodes; first to third light-emitting layers located on the first common intermediate layer and overlapping the first to third anodes; and a second common intermediate layer disposed in common on the first to third light emitting layers; Further comprising: the common intermediate layer including the first common intermediate layer and the second common intermediate layer includes an organic material; the cathode is located on the second common intermediate layer; The display device according to claim 1 , wherein the common intermediate layer and the cathode extend to an upper portion of the stopper.

6. a capping layer disposed between the cathode and the first inorganic film and extending from the display area to the non-display area; The display device of claim 5 , wherein the capping layer extends onto the outer surface of the insulating film stack along the top and outside of the stoppers.

7. an end of the common intermediate layer and an end of the cathode are located on the stopper; The display device according to claim 5 , wherein an end of the cathode protrudes outward beyond an upper layer portion of an outer surface of the stopper and an end of the common intermediate layer.

8. The stopper includes a cliff portion from the upper portion to a portion where the inclination of the outer surface becomes gentler than a predetermined level or where there is a step, The display device according to claim 5 , wherein a combined value of a height of the cliff portion of the stopper and a height of the common intermediate layer is greater than a total thickness of the first inorganic film and a thickness of the second inorganic film.

9. The stopper is a first stopper on the insulating film stack; and A second stopper on the first stopper Including, the first stopper contains the same material as the bank; The display device according to claim 5 , wherein the second stopper comprises the same material as the spacer located on the bank.

10. The display device according to claim 9 , wherein a lower end of an outer surface of the first stopper protrudes outward beyond an upper end of an outer surface of the second stopper.

11. The display device of claim 1 , wherein the stopper is disposed on a side of an outermost light emitting element among a plurality of light emitting elements corresponding to the plurality of subpixels, and has a thickness greater than that of the anode of the outermost light emitting element.

12. The display device according to claim 1 , wherein a width of a bottom surface of the stopper is greater than a width of a top surface of the stopper.

13. display signal wiring disposed in the display area; display connection wiring that electrically connects the display signal wiring and the display pads arranged in the pad area; and A bending organic film disposed between the display area and the pad area. Further comprising: The display device according to claim 1 , wherein a portion of the display connection wiring overlaps with the bending organic film.

14. The non-display area is a first non-display area positioned in the first direction from the display area; a second non-display area located in a second direction from the display area; a third non-display area located in a direction opposite to the first direction from the display area; and a fourth non-display area located in a direction opposite to the second direction from the display area; Including, the pad area is included in the first non-display area, The display device according to claim 1 , wherein the stopper is disposed in the non-display area, is disposed in a ring shape surrounding a periphery of the organic film, and the stopper is located between the display area and the pad area.

15. a first sensor electrode disposed on the second inorganic film and extending in the second direction; and a first touch routing trace for electrically connecting the first sensor electrode to a first touch pad disposed in the pad area; Further comprising: the first touch routing wiring does not detour around the second non-display area and the fourth non-display area, crosses the display area in the first direction, and extends to the first non-display area; The display device of claim 14 , wherein a portion of the first touch routing wiring that extends to the first non-display area overlaps with the stopper in the first non-display area.

16. a gate-in-panel circuit configured to provide a gate signal to the plurality of sub-pixels; The display device of claim 1 , wherein the gate-in-panel circuit is disposed on the substrate and overlaps the organic film.

17. a base circuit layer on said substrate; a light emitting element layer located on the base circuit layer, the light emitting element layer including a plurality of light emitting elements included in the plurality of subpixels; and A shielding layer located between the base circuit layer and the light emitting element layer. Further comprising: The display device according to claim 16 , wherein the base circuit layer includes the gate-in-panel circuit disposed in the display area.

18. The display device of claim 17, wherein a voltage having a predetermined voltage level is applied to the shielding layer.

19. a common driving voltage line disposed on the substrate for supplying a common pixel driving voltage to the cathode; The display device according to claim 17 , wherein the common driving voltage line is disposed in the display area, and the cathode is electrically connected to the common driving voltage line in the display area.

20. a subpixel circuit layer located between the shielding layer and the light-emitting element layer, the subpixel circuit layer including a plurality of subpixel circuits for driving a plurality of light-emitting elements; and Gate link wiring that connects the gate-in-panel circuit arranged in the base circuit layer and the plurality of sub-pixel circuits Further comprising: The display device according to claim 17 , wherein the gate link wiring overlaps with the organic film.

21. the display area includes a first display area and a second display area, the base circuit layer further includes a sub-pixel circuit array including a plurality of sub-pixel circuits for driving the plurality of light-emitting elements as well as the gate-in-panel circuit; the gate-in-panel circuit is disposed in the first display area; the subpixel circuit array is disposed in the second display area; The plurality of light-emitting elements include a first light-emitting element disposed in the first display area and overlapping at least a portion of the gate-in-panel circuit; and A second light-emitting element disposed in the second display region and overlapping at least a portion of the sub-pixel circuit array. Including, The plurality of subpixel circuits include a first subpixel circuit configured to drive the first light emitting element and disposed in the second display area; and two or more second subpixel circuits configured to drive the second light-emitting elements and disposed in the second display area; The display device of claim 17 , comprising:

22. an extension link connecting the first subpixel circuit disposed in the second display area to the first light emitting element disposed in the first display area; Further comprising:

22. The display device of claim 21, wherein at least a portion of the extension link overlaps at least a portion of the gate-in-panel circuitry, and the extension link overlaps the organic film.

23. a base voltage line located in at least one of the first display area and the second display area; and The display device according to claim 21 , further comprising a cathode connection pattern located in at least one of the first display area and the second display area, connecting the cathode and the base voltage line.

24. The display device of claim 1 , further comprising a patterning organic material disposed on an outer periphery of the stopper.

25. substrate; an insulating film stack on the substrate; a plurality of light emitting devices on the insulating film stack; an organic film on the plurality of light-emitting elements; and A stopper disposed on the outer periphery of the organic film Including, The stopper is disposed on an outer surface of an outermost light emitting element of the plurality of light emitting elements, and has a thickness greater than that of an anode of the outermost light emitting element.

26. A bank for dividing the plurality of light emitting elements; and Spacers on the bank Further comprising: the stopper includes a first stopper on the insulating film stack and a second stopper on the first stopper; the first stopper contains the same material as the bank; The display device of claim 25 , wherein the second stoppers include the same material as the spacers.

27. The display device of claim 25 , wherein an outer surface of the stopper has a steeper slope than an inner surface of the stopper.

Images