Light detection device

Abstract

To provide a light detection device with a plurality of avalanche photodiodes formed on a semiconductor substrate composed of compound semiconductor, improving both light detection sensitivity and light detection time resolution.SOLUTION: A light detection device comprises a first layer 10 composed of compound semiconductor, and a second layer 50 composed of silicon. The first layer 10 includes a plurality of avalanche photodiodes 20 disposed in a two-dimensional layout and operating in Geiger mode. The second layer 50 incudes a plurality of output units 30 which are overlapped on the first layer. Each output unit 30 has a quenching element 31. The quenching element 31 is serially connected to at least one of the plurality of avalanche photodiodes 20.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a light detection device. [Background technology]

[0002] A photodetector in which a plurality of avalanche photodiodes are arranged two-dimensionally is known (for example, Patent Document 1). The plurality of avalanche photodiodes operate in Geiger mode. The plurality of avalanche photodiodes are formed on a semiconductor substrate made of a compound semiconductor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2012-531753 Summary of the Invention [Problem to be solved by the invention]

[0004] When a plurality of avalanche photodiodes formed on a semiconductor substrate made of a compound semiconductor are operated in a Geiger mode, dark pulses and afterpulses increase in response to temperature changes. If noise increases due to the dark pulses and afterpulses, there is a risk that signals from the avalanche photodiodes will not be detected properly.

[0005] It is known that when an avalanche photodiode is operated in the Geiger mode, a passive quenching element is arranged in series with the avalanche photodiode to quench the avalanche multiplication. Depending on the resistance value of this passive quenching element, it is determined whether the avalanche multiplication process occurring inside the avalanche photodiode connected to the passive quenching element is properly quenched or not. If the resistance value of the quenching element is insufficient, proper quenching may not be achieved due to the generation of latching current, etc. For proper quenching, it is necessary to select a necessary and sufficient resistance value of the quenching element.

[0006] The larger the resistance value of the passive quenching element, the longer the time required to quench the avalanche photodiode connected in series with the passive quenching element. If the time required for quenching increases, the dead time during which the avalanche photodiode cannot detect light increases. Thus, in order to achieve both appropriate quenching and reduced dead time and to ensure light detection sensitivity and light detection time resolution, a circuit design that has a passive quenching element with an optimal resistance value is required.

[0007] Since the parasitic capacitance in the passive quenching element also affects the pulse signal, it is also required to remove the parasitic capacitance. Furthermore, in order to improve the photodetection time resolution, it is also required to improve the peak value of the pulse signal. It is extremely difficult to design a device that operates multiple avalanche photodiodes formed on a semiconductor substrate made of compound semiconductors in the Geiger mode so as to satisfy all of the above desired conditions.

[0008] One aspect of the present invention aims to provide a photodetection device that achieves both improved photodetection sensitivity and photodetection time resolution in a configuration in which multiple avalanche photodiodes are formed on a semiconductor substrate made of a compound semiconductor. [Means for solving the problem]

[0009] A photodetector according to an aspect of the present invention includes an avalanche photodiode array substrate and a circuit substrate. The avalanche photodiode array substrate is made of a compound semiconductor. An avalanche photodiode array substrate is mounted on the circuit substrate. A plurality of avalanche photodiodes are two-dimensionally arranged on the avalanche photodiode array substrate. The plurality of avalanche photodiodes operate in a Geiger mode. The circuit substrate has a plurality of output units connected in parallel to each other. The plurality of output units form at least one channel. Each output unit has a passive quenching element and a capacitance element. The passive quenching element is connected in series with at least one of the plurality of avalanche photodiodes. The capacitance element is connected in series with the at least one avalanche photodiode and in parallel with the passive quenching element.

[0010] In this aspect, a plurality of output units having a passive quenching element and a capacitance element are provided on a circuit board separate from the avalanche photodiode array substrate. Therefore, a space in which the plurality of output units can be formed can be expanded compared to a case in which the plurality of output units are arranged on the avalanche photodiode array substrate. If the output unit is provided on a circuit board separate from the avalanche photodiode array substrate, a parasitic capacitance occurring between the configuration of the avalanche photodiode and the output unit can be reduced. In this case, it is also possible to use a manufacturing process separate from the avalanche diode array substrate. Therefore, the design of the plurality of output units can be facilitated. The capacitance element of the photodetector is connected in series to at least one avalanche photodiode and in parallel to the passive quenching element. Therefore, the peak value of the pulse signal from the avalanche photodiode connected in series to the capacitance element can be improved by the capacitance of the capacitance element. Therefore, the pulse signal from the plurality of avalanche photodiodes can be easily detected, and the photodetection time resolution can be further improved.

[0011] In this embodiment, the passive quenching element may be formed by a first polysilicon layer provided on the circuit board. The capacitive element may be formed by a second polysilicon layer provided on the circuit board, a dielectric layer stacked on the second polysilicon layer, and a third polysilicon layer stacked on the dielectric layer. The first polysilicon layer is formed at the same height as the second polysilicon layer or the third polysilicon layer in the thickness direction of the circuit board. In this case, the plurality of output units can be formed by a simple manufacturing process. Effect of the Invention

[0012] According to one aspect of the present invention, there is provided a photodetection device that can ensure the accuracy of photodetection with a simple design in a configuration in which a plurality of avalanche photodiodes are formed on a semiconductor substrate made of a compound semiconductor. [Brief description of the drawings]

[0013] [Figure 1] FIG. 1 is a perspective view of a light detection device according to an embodiment. [Diagram 2] FIG. 2 is a diagram showing a cross-sectional configuration of the photodetector. [Diagram 3] FIG. 3 is a plan view of the circuit board. [Figure 4] FIG. 4 is a plan view of the photodetection region of the avalanche photodiode array substrate. [Diagram 5] FIG. 5 is a diagram showing the configuration of the circuit board. [Figure 6] FIG. 6 is a diagram showing a circuit configuration used in the photodetector. [Figure 7] FIG. 7 is a diagram showing a circuit configuration used in a photodetector according to a modified example of this embodiment. [Figure 8] FIG. 8 is a plan view of the mounting area of ​​the circuit board. [Figure 9] FIG. 9 is a diagram showing components of a pulse signal from an avalanche photodiode. [Figure 10] FIG. 10 is a diagram showing the characteristics of a recharge pulse. [Figure 11] FIG. 11 is a diagram showing the characteristics of a fast pulse. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same elements or elements having the same functions will be denoted by the same reference numerals, and duplicated description will be omitted.

[0015] First, the overall configuration of the photodetector according to this embodiment will be described with reference to Figs. 1 to 8. Fig. 1 is a perspective view of the photodetector according to this embodiment. Fig. 2 is a diagram showing a cross-sectional configuration of the photodetector according to this embodiment. In Fig. 2, hatching is omitted to improve visibility. Fig. 3 is a plan view of a circuit board. Fig. 4 is a plan view showing a part of an avalanche photodiode array board. Fig. 6 is a diagram showing a circuit configuration used in the photodetector according to this embodiment. Fig. 8 is a plan view showing a part of a circuit board.

[0016] As shown in Fig. 1, the photodetector 1 includes an avalanche photodiode array substrate 10 and a circuit substrate 50. Hereinafter, "avalanche photodiode" will be referred to as "APD." "Avalanche photodiode array substrate" will be referred to as "APD array substrate." The circuit substrate 50 is disposed opposite the APD array substrate 10. Both the APD array substrate 10 and the circuit substrate 50 have a rectangular shape in a plan view.

[0017] The APD array substrate 10 includes main surfaces 10A, 10B, and a side surface 10C that face each other. The circuit substrate 50 includes main surfaces 50A, 50B, and a side surface 50C that face each other. The main surface 10B of the APD array substrate 10 faces the main surface 50A of the circuit substrate 50. A plane parallel to each of the main surfaces of the APD array substrate 10 and the circuit substrate 50 is the XY-axis plane, and the direction perpendicular to each of the main surfaces is the Z-axis direction.

[0018] The side surface 50C of the circuit board 50 is located outside the side surface 10C of the APD array substrate 10 in the XY-axis plane direction. That is, in a plan view, the area of ​​the circuit board 50 is larger than the area of ​​the APD array substrate 10. The side surface 10C of the APD array substrate 10 and the side surface 50C of the circuit board 50 may be flush with each other. In this case, the outer edge of the APD array substrate 10 and the outer edge of the circuit board 50 coincide with each other in a plan view.

[0019] A glass substrate may be disposed on the main surface 10A of the APD array substrate 10. The glass substrate and the APD array substrate 10 are optically connected by an optical adhesive. The glass substrate may be formed directly on the APD array substrate 10. The side surface 10C of the APD array substrate 10 and the side surface of the glass substrate may be flush with each other. In this case, the outer edge of the APD array substrate 10 and the outer edge of the glass substrate coincide with each other in a plan view. The side surface 10C of the APD array substrate 10, the side surface 50C of the circuit substrate 50 and the side surface of the glass substrate may also be flush with each other. In this case, the outer edge of the APD array substrate 10, the outer edge of the circuit substrate 50 and the outer edge of the glass substrate coincide with each other in a plan view.

[0020] The APD array substrate 10 is mounted on a circuit substrate 50. As shown in Fig. 2, the APD array substrate 10 and the circuit substrate 50 are connected by bump electrodes 25. Specifically, when viewed in the thickness direction of the APD array substrate 10, the APD array substrate 10 is connected by the bump electrodes 25 on a mounting region α disposed in the center of the circuit substrate 50 as shown in Fig. 3. In this embodiment, the mounting region α has a rectangular shape.

[0021] The circuit board 50 has a ground line 3, a cathode line 5, and an anode line 7 around the mounting area α. The ground line 3, the cathode line 5, and the anode line 7 extend from the mounting area α. The ground line 3 is connected to a ground electrode 63, which will be described later. The cathode line 5 is electrically connected to the APD array substrate 10 mounted in the mounting area α, and is used to apply a voltage to the APD array substrate 10. The anode line 7 is connected to metal layers 65 and 66, which will be described later, and is used to read out signals from the APD array substrate 10.

[0022] The APD array substrate 10 has a plurality of APDs 20 that operate in the Geiger mode. As shown in Fig. 4, the plurality of APDs 20 are two-dimensionally arranged in a light detection region β of the semiconductor substrate 11 when viewed in the thickness direction of the APD array substrate 10. The light detection region β has a rectangular shape, and overlaps with a mounting region α of the circuit board 50 when viewed in the thickness direction of the APD array substrate 10.

[0023] The APD array substrate 10 has an N-type semiconductor substrate 11 made of a compound semiconductor. The semiconductor substrate 11 has a substrate 12 made of InP forming a main surface 10A. On the substrate 12, a buffer layer 13 made of InP, an absorption layer 14 made of InGaAsP, an electric field relaxation layer 15 made of InGaAsP, and a multiplication layer 16 made of InP are formed in this order from the main surface 10A side to the main surface 10B side. The absorption layer 14 may be made of InGaAs. The semiconductor substrate 11 may be formed of GaAs, InGaAs, AlGaAs, InAlGaAs, CdTe, HgCdTe, or the like.

[0024] As shown in FIG. 2 and FIG. 4, each APD 20 is surrounded by an insulating portion 21 when viewed from the thickness direction of the APD array substrate 10. Each APD 20 has a P-type active area 22 formed by doping an impurity into the multiplication layer 16 from the main surface 10B side. The doped impurity is, for example, Zn (zinc). The insulating portion 21 is formed by forming a polyimide film in a trench groove formed by wet etching or dry etching. The active area 22 is formed in a circular shape when viewed from the thickness direction, and the insulating portion 21 is formed in an annular shape along the edge of the active area 22. The insulating portion 21 reaches the substrate 12 from the main surface 10B side of the semiconductor substrate 11 in the thickness direction of the APD array substrate 10.

[0025] 5 is a diagram showing a part of an avalanche photodiode array substrate used in a photodetector according to a modified example of this embodiment. As shown in FIG. 5, the active area 22 may be formed in a substantially rectangular shape when viewed in the thickness direction. Here, the substantially rectangular shape refers to a rectangular shape with rounded corners. This suppresses the concentration of the electric field at the corners of the active area 22. In this case, the insulating portion 21 is formed in a ring shape along the edge of the substantially rectangular active area 22.

[0026] The APD array substrate 10 has an insulating layer 23 and a plurality of electrode pads 24. The insulating layer 23 covers the semiconductor substrate 11 on the main surface 10B side. The electrode pads 24 are formed on the semiconductor substrate 11 on the main surface 10B side for each APD 20, and are in contact with the active area 22. The electrode pads 24 are exposed from the insulating layer 23, and are connected to the circuit substrate 50 through bump electrodes 25.

[0027] As shown in Fig. 2, the circuit board 50 is connected to the APD array substrate 10 on the main surface 50A side through the bump electrodes 25. The circuit board 50 has a plurality of output units 30. As shown in Fig. 6, the plurality of output units 30 are connected in parallel to each other to form one channel 40. Each of the plurality of output units 30 is connected in series to each APD 20 provided on the APD array substrate 10. Each output unit 30 has a passive quenching element 31 and a capacitance element 32 connected in parallel to each other. Both the passive quenching element 31 and the capacitance element 32 are connected in series to the APD 20.

[0028] Fig. 7 is a diagram for explaining a circuit configuration used in a photodetector according to a modified example of this embodiment. As shown in Fig. 7, a plurality of channels 40 may be formed on a circuit board 50. In this case, each channel 40 is formed by a plurality of output units 30 connected in parallel to each other. It is sufficient that at least one of the plurality of channels 40 is formed by a plurality of output units 30 connected in parallel to each other.

[0029] The circuit board 50 has a silicon substrate 51 and a wiring layer 61 laminated on the silicon substrate 51. As shown in FIG. 2, the silicon substrate 51 is provided with a P + Layer 52 and P - Layer 53 and P + layer 54. + Layer 52 is P - It is provided by doping layer 53 with an impurity. + Layer 54 is P - It is provided by doping layer 53 with an impurity. - The impurity doped in the layer 53 is, for example, boron. Between the silicon substrate 51 and the wiring layer 61, an oxide film layer 60 is provided, which is formed, for example, in an element isolation process by thermal oxidation. + The layer 54 is exposed from the oxide film layer 60 and is in contact with the wiring layer 61 .

[0030] The wiring layer 61 includes an insulating layer 62, a ground electrode 63, an electrode pad 64, metal layers 65 and 66, vias 67, 68, 69 and 70, polysilicon layers 71, 72 and 73, and a dielectric layer 74. The ground electrode 63, the electrode pad 64, the metal layers 65 and 66, the vias 67, 68, 69 and 70, the polysilicon layers 71, 72 and 73, and the dielectric layer 74 are provided for each APD 20. The ground electrode 63, the electrode pad 64, and the metal layers 65 and 66 are formed in the same layer. In other words, the ground electrode 63, the electrode pad 64, and the metal layers 65 and 66 are formed at the same height in the thickness direction of the circuit board 50.

[0031] The insulating layer 62 is formed of, for example, SiO2. The ground electrode 63, the electrode pad 64, and the metal layers 65 and 66 are formed of, for example, Al, AlCu, or AlSiCu. The ground electrode 63, the electrode pad 64, and the metal layers 65 and 66 may be formed of the same material. The vias 67, 68, 69, and 70 are formed of, for example, W (tungsten). The dielectric layer 74 is formed of, for example, SiO2 or Si3N4.

[0032] The wiring layer 61 is covered with an insulating layer 62. + The layer 54 is connected to a via 67 exposed on the silicon substrate 51 side from the insulating layer 62 of the wiring layer 61. + Layer 54 is connected to ground electrode 63 through via 67. Ground electrode 63 is disposed at the height where ground electrode 63 is disposed in the thickness direction of circuit board 50, with insulating layer 62 interposed between electrode pad 64 and metal layers 65, 66. Ground electrode 63 is not directly connected to electrode pad 64 and metal layers 65, 66.

[0033] The electrode pads 64 are exposed from the insulating layer 62 and connected to the APD 20 through the bump electrodes 25. The electrode pads 64 are two-dimensionally arranged on the main surface 50A side as shown in FIG. 8. The electrode pads 64 are connected to the polysilicon layer 71 through a via 68. The polysilicon layer 71 is connected to the metal layer 65 through a via 69. The electrode pads 64 are arranged with the insulating layer 62 interposed between them and the metal layers 65 and 66 at a height where the electrode pads 64 are arranged in the thickness direction of the circuit board 50. The electrode pads 64 are not directly connected to the metal layers 65 and 66. The polysilicon layer 71 is included in the first polysilicon layer.

[0034] The polysilicon layer 71 constitutes the passive quenching element 31. With the above-mentioned configuration, the passive quenching element 31 is connected in series to the APD 20 through the bump electrode 25, the electrode pad 64, and the via 68. That is, a pulse signal from the APD 20 is input to the passive quenching element 31 through the bump electrode 25, the electrode pad 64, and the via 68. The pulse signal input to the passive quenching element 31 is output from the channel 40 through the passive quenching element 31, the via 69, and the metal layer 65.

[0035] The electrode pad 64 is connected to the metal layer 66 at a height where the electrode pad 64 is disposed in the thickness direction of the circuit board 50. The metal layer 66 is connected to the polysilicon layer 72 through the via 70. The polysilicon layer 72 is laminated on the dielectric layer 74. The dielectric layer 74 is laminated on the polysilicon layer 73. The polysilicon layer 73 is connected to the metal layer 65 through a via (not shown). The polysilicon layer 71 and the polysilicon layer 73 are formed at the same height in the thickness direction of the circuit board 50. The polysilicon layer 71 and the polysilicon layer 72 may be formed at the same height in the thickness direction of the circuit board 50. The polysilicon layer 72 is included in the third polysilicon layer. The polysilicon layer 73 is included in the second polysilicon layer.

[0036] The polysilicon layer 72, the dielectric layer 74, and the polysilicon layer 73 constitute the capacitance element 32. With the above-mentioned configuration, the capacitance element 32 is connected in series to the APD 20 through the bump electrode 25, the electrode pad 64, and the via 68. That is, a pulse signal from the APD 20 is input to the polysilicon layer 72 of the capacitance element 32 through the bump electrode 25, the electrode pad 64, and the via 68. In response to the input of the pulse signal to the polysilicon layer 72 of the capacitance element 32, a pulse signal is output from the polysilicon layer 73 of the capacitance element 32. The pulse signal output from the capacitance element 32 is output from the channel 40 through a via and a metal layer 65 (not shown).

[0037] Both the passive quenching element 31 and the capacitance element 32 are electrically connected to the electrode pad 64 and the metal layer 65. Therefore, the passive quenching element 31 and the capacitance element 32 are connected in parallel with each other.

[0038] Next, the function and effect of the photodetector 1 will be described with reference to Fig. 9 to Fig. 11. Fig. 9 shows a pulse signal output from the APD 20. As shown in Fig. 9, a pulse signal 26 from the APD 20 is divided into a fast pulse 27 and a recharge pulse 28. The fast pulse 27 is a pulse component having a peak value of the pulse signal. The recharge pulse 28 is a component that is detected after the fast pulse 27 is detected and has a pulse width longer than that of the fast pulse 27.

[0039] Fig. 10 shows the waveform of a pulse signal output from the APD 20 when the capacitive element 32 is removed from the output unit 30 and the resistance value of the passive quenching element 31 is used as a parameter. Fig. 10 is an integer graph with the vertical axis in units of current (A) and the horizontal axis in units of time (s). Data a, b, c, and d are data of a pulse signal when passive quenching elements 31 having different resistance values ​​are provided in the output unit 30. The passive quenching elements 31 having higher resistance values ​​are provided in the order of data a, b, c, and d.

[0040] 10, the smaller the resistance value of the passive quenching element 31, the steeper the slope of the recharge pulse 28. The steeper the slope of the recharge pulse 28, the shorter the time required for quenching and the shorter the dead time during which the APD 20 cannot detect light. By using a passive quenching element 31 with a high resistance value, it is possible to achieve appropriate quenching that suppresses the occurrence of latching currents, etc. However, the higher the resistance value, the longer the dead time becomes.

[0041] The pulse width of the pulse signal from the APD 20 connected to the passive quenching element 31 also changes depending on the resistance value of the passive quenching element 31. As shown in Fig. 10, the larger the resistance value of the passive quenching element 31, the longer the dead time of the APD 20 connected in series to the passive quenching element 31. Therefore, in order to achieve both appropriate quenching and reduced dead time and to ensure photodetection sensitivity and photodetection time resolution, a circuit design having a passive quenching element 31 with an optimal resistance value is required.

[0042] In the photodetector 1, a plurality of output units 30 each having a passive quenching element 31 and a capacitive element 32 are provided on a circuit board 50 separate from the APD array substrate 10. This allows a larger space for forming the plurality of output units 30 compared to a case in which the plurality of output units 30 are disposed on the APD array substrate 10. This allows the plurality of output units 30 to be easily designed.

[0043] Since the multiple output units 30 are provided on the circuit board 50 separate from the APD array substrate 10, it is possible to reduce parasitic capacitance occurring between the configuration of the APD 20 and the output units 30. It is also possible to use a manufacturing process separate from that for the APD array substrate 10. Since it is possible to use manufacturing processes suitable for each of the APD array substrate 10 and the circuit board 50, it is possible to facilitate the design of the multiple output units 30.

[0044] Fig. 11 shows the waveform of a pulse signal output from the APD 20, with the passive quenching element 31 set to a constant value and the capacitance of the capacitive element 32 as a parameter. Fig. 11 is a single-variable graph with the vertical axis in units of current (A) and the horizontal axis in units of time (s). Data a is data of a pulse signal when the capacitive element 32 is removed from the output unit 30. Data b, c, and d are data of a pulse signal when capacitive elements 32 having different capacitances are provided in the output unit 30. Data b, c, and d indicate capacitive elements 32 with higher capacitances are provided in this order.

[0045] 11, the provision of the capacitive element 32 improves the peak value of the fast pulse 27. The higher the capacitance of the capacitive element 32, the larger the peak value of the fast pulse 27. Therefore, the provision of the capacitive element 32 improves the time resolution of the pulse signals from the multiple APDs 20. The higher the peak value of the fast pulse 27, the easier it is to detect the pulse signals from the multiple APDs 20.

[0046] The photodetector 1 has a capacitive element 32 connected in series to at least one APD 20 and connected in parallel to a passive quenching element 31. According to the above configuration, due to the characteristics described with reference to FIG. 11, the peak value of the pulse signal from the APD 20 connected in series to the capacitive element 32 can be improved by the capacitance of the capacitive element 32. Therefore, pulse signals from multiple APDs 20 can be easily detected, and the photodetection time resolution can be improved. The photodetector 1 can count the number of incident photons while achieving desired photodetection sensitivity and photodetection time resolution.

[0047] In a configuration in which a plurality of APDs 20 operate in the Geiger mode on the APD array substrate 10 made of a compound semiconductor, the influence of noise can be suppressed by reducing the electric field intensity applied to each APD 20.

[0048] The photodetector 1 includes polysilicon layers 71 and 73 provided on a circuit board 50, a dielectric layer 74 provided on the polysilicon layer 73, and a polysilicon layer 72 provided on the dielectric layer 74. The passive quenching element 31 is formed by the polysilicon layer 71, and the capacitive element 32 is formed by the polysilicon layer 73, the dielectric layer 74, and the polysilicon layer 72. The polysilicon layer 71 is formed at the same height as the polysilicon layer 72 or the polysilicon layer 73 in the thickness direction of the circuit board 50. In this case, the plurality of output units 30 can be formed by a simple manufacturing process.

[0049] Although the embodiment of the present invention has been described above, the present invention is not necessarily limited to the above-described embodiment, and various modifications are possible without departing from the gist of the present invention.

[0050] For example, the passive quenching element 31 may be formed of a metal thin film instead of the polysilicon layer 71. The capacitive element 32 may be formed of two metal layers instead of the polysilicon layers 72 and 73. In this case, the capacitive element 32 has a configuration in which a dielectric layer 74 is sandwiched between two parallel metal layers. [Explanation of symbols]

[0051] 1...photodetector device, 10...APD array substrate, 20...APD, 30...output unit, 31...passive quenching element, 32...capacitive element, 40...channel, 50...circuit board, 71, 72, 73...polysilicon layer, 74...dielectric layer.

Claims

1. 1. A light detection device, comprising: a first layer made of a compound semiconductor in which a plurality of avalanche photodiodes operating in Geiger mode are two-dimensionally arranged; a second layer comprising silicon, the second layer including a plurality of output units and overlying the first layer; Each of the output units includes a quenching element connected in series with one of the plurality of avalanche photodiodes.

2. 2. The optical detection device according to claim 1, Each of the avalanche photodiodes has an active area surrounded by an insulating portion when viewed in a thickness direction of the first layer, The insulating portion is formed from a trench.

3. 3. The light detection device according to claim 2, The active area of ​​each of the avalanche photodiodes is formed in a circular shape when viewed in the thickness direction, The insulating portion is formed in a circular ring shape along the edge of the active area.

4. 2. The optical detection device according to claim 1, the first layer is formed from a third layer and a fourth layer disposed on the third layer, such that the third layer is located between the second layer and the fourth layer; the third layer faces the second layer, is made of a compound semiconductor, and includes a buffer layer, an absorption layer, and an electric field relaxation layer; The insulating portion extends from the third layer to the fourth layer.

5. 2. The optical detection device according to claim 1, The second layer is formed from a silicon layer and a wiring layer disposed on the silicon layer, such that the wiring layer is located between the silicon layer and the first layer.

6. 2. The optical detection device according to claim 1, the second layer includes a plurality of channels; Each of the plurality of channels is formed from a plurality of the output units connected in parallel to each other.

7. 2. The optical detection device according to claim 1, The first layer and the second layer are connected by a bump electrode.

8. 2. The optical detection device according to claim 1, The quenching element includes a passive quenching element.

9. 9. The light detection device according to claim 8, The second layer includes a capacitive element connected in series with one of the avalanche photodiodes and in parallel with the passive quenching element.

10. 10. The light detection device according to claim 9, the passive quenching element is formed by a first polysilicon layer provided on the second layer; the capacitance element is formed by a second polysilicon layer provided in the second layer, a dielectric layer stacked on the second polysilicon layer, and a third polysilicon layer stacked on the dielectric layer; The first polysilicon layer is formed at the same height as the second polysilicon layer or the third polysilicon layer in the thickness direction of the second layer.

11. 10. The light detection device according to claim 9, the passive quenching element is formed by a first metal layer provided on the second layer; the capacitive element is formed by a second metal layer provided on the second layer, a dielectric layer stacked on the second metal layer, and a third metal layer stacked on the dielectric layer; The first metal layer is formed at the same height as the second metal layer or the third metal layer in the thickness direction of the second layer.

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