Semiconductor device

Abstract

To configure a buffer circuit, an inverter circuit and the like by using only an n-channel TFT that uses an oxide semiconductor layer.SOLUTION: A buffer circuit, an inverter circuit and the like are configured by combining: a first transistor in which both of a source electrode and a drain electrode overlap a gate electrode; and a second transistor in which the source electrode overlaps the gate electrode and the drain electrode does not overlap the gate electrode. By configuring the second transistor as above, capacitance Cp can be reduced and large VA' can be obtained even when potential difference VDD-VSS is small.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including an oxide semiconductor and a manufacturing method thereof.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] Thin film transistors (TFTs) are fabricated using semiconductor thin films formed on substrates with insulating surfaces. Research into the technology that makes up the thin-film transistor is currently underway. It is widely used in electronic devices, especially in image display devices (liquid crystal display devices and EL display devices). It is used as an etching element.

[0004] Thin-film transistors are used as switching elements in image display devices (liquid crystal display devices and EL display devices). The display device used in this case is called an active matrix display device, and its advantage is that A shift register circuit, a latch circuit, or a buffer circuit is used as a driving circuit for transmitting a signal to the The advantage of this technology is that it is possible to form circuits such as transistors and transistor paths on the same insulator using TFTs.

[0005] However, the manufacturing process for TFTs in active matrix displays is complicated. The problem was that the manufacturing costs were high. In addition, the manufacturing cost was high because multiple TFTs were formed simultaneously. Therefore, if the manufacturing process becomes complicated, it becomes difficult to ensure the yield. If a pixel is too small, it can cause a linear defect in which a row of pixels does not work.

[0006] Patent Document 1 discloses a technology for forming pixel sections and driver circuits entirely from n-channel transistors. It has been done.

[0007] In addition, this is not limited to display devices, but can also be used in combination with inverter circuits (logical negation circuits) and buffer circuits. By combining these two techniques, various semiconductor integrated circuits such as LSIs can be produced. The inverter circuit and buffer circuit are made up of n-channel and p-channel TFTs. It is composed of a CMOS circuit that combines [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2002-49333 A Summary of the Invention [Problem to be solved by the invention]

[0009] Buffer circuits, inverter circuits, etc. are made using only n-channel TFTs with oxide semiconductor layers. One of the objectives of the project is to create a [Means for solving the problem]

[0010] When configuring a buffer circuit or inverter circuit using only n-channel TFTs, A technique called a test strap is used when constructing a buffer circuit or an inverter circuit. The output section used is shown in FIG.

[0011] In FIG. 1A, a gate electrode of a first transistor 301 is electrically connected to a control unit 304. The gate electrode of the second transistor 302 is also electrically connected to the control unit 304. In addition, the gate electrode of the second transistor 302 and one of the electrodes are electrically connected to each other. has a capacitance 303, and the other electrode of the capacitance is electrically connected to the source electrode of the second transistor 302 and is electrically connected thereto.

[0012] The bootstrap is configured as the circuit shown in FIG. 1(A) so that OUT does not become smaller than VDD when the output becomes high. FIGS. 1(B) and 1( C) show how the potential of node A in FIG. 1(A) changes due to the bootstrap. At this time, V ’ can be obtained by the following equation. A ’ can be obtained by the following equation.

[0013] [Equation]

[0014] When using a circuit as shown in FIG. 1(A), it is important to reduce the capacitance Cp. In particular, when the potential difference VDD-VSS is small, a very large capacitance C is required so that V ’ < VDD. When a circuit is configured using transistors with an oxide semiconductor, depending on the transistor structure, the capacitance Cp may increase. In a transistor with a large capacitance Cp structure, there are problems such as difficulty in operating the circuit, a small margin, and inability to obtain desired frequency characteristics A (also called f characteristics). When using a transistor with an oxide semiconductor to configure a circuit, depending on the transistor structure, the capacitance Cp may increase. In a transistor with a large capacitance Cp structure, there are problems such as difficulty in operating the circuit, a small margin, and inability to obtain desired frequency characteristics (also called f characteristics). When the source electrode and the drain electrode of a transistor with an oxide semiconductor are overlapped with the gate electrode, the capacitance Cp increases. Therefore, if the transistor structure is such that both the source electrode and the drain electrode do not overlap the gate electrode, the on-current decreases. In particular, in a transistor structure where the source electrode does not overlap the gate electrode, the on-current significantly decreases

[0015] In a transistor using an oxide semiconductor, if the source electrode is overlapped with the gate electrode and the drain electrode also overlaps the gate electrode, the capacitance Cp increases. Therefore, if the transistor structure is such that both the source electrode and the drain electrode do not overlap the gate electrode, the on-current decreases. In particular, in a transistor structure where the source electrode does not overlap the gate electrode, the on-current significantly decreases electrode do not overlap the gate electrode, the on-current decreases. In particular, in a transistor structure where the source electrode does not overlap the gate electrode, the on-current significantly decreases electrode do not overlap the gate electrode, the on-current decreases. In particular, in a transistor structure where the source electrode does not overlap the gate electrode, the on-current significantly decreases ​It will decrease.

[0016] In one embodiment of the present invention, the gate electrode of the second transistor 302 in the circuit of FIG. One end face is connected to the source electrode of the second transistor 302 and the drain electrode of the second transistor 302. The gate electrode is formed at a position overlapping the gap of the drain electrode, and the other end surface of the gate electrode is connected to the source electrode. By making the second transistor have such a structure, the capacitance Cp Even if the potential difference between VDD and VSS is small, A ' can be obtained larger.

[0017] According to one aspect of the present invention, there is provided a first transistor, and a drain electrode of the first transistor electrically connected to the drain electrode of the first transistor. a second transistor having a source electrode connected to the first transistor; and a capacitance to which the electrode of the second transistor is electrically connected, and the other electrode of the capacitance is The gate electrode of the first transistor is electrically connected to the source electrode of the second transistor through the gate insulating layer. The source electrode and the drain electrode of the first transistor overlap each other through the second transistor. The gate electrode of the first transistor overlaps with the source electrode of the second transistor via the gate insulating layer. One end face of the gate electrode of the first transistor is connected to the source electrode of the second transistor and The drain electrode of the first transistor overlaps the gap, and the drain electrode of the second transistor overlaps the gap. The transistor is a semiconductor device characterized in that it is an n-channel transistor.

[0018] In addition, the parasitic capacitance of the second transistor 302 can be used instead of the capacitor 303. In this case, the capacitor 303 does not need to be provided separately.

[0019] In the case where the capacitor 303 is not provided, in one embodiment of the present invention, a drain electrode of the first transistor and a source electrode of the second transistor electrically connected to the drain electrode of the first transistor; The gate electrode of the first transistor is connected to the source electrode of the second transistor through the gate insulating layer. and the drain electrode of the second transistor is overlapped with the gate electrode of the first transistor through the gate insulating layer. The source electrode of the second transistor is overlapped with one end of the gate electrode of the second transistor. The surface overlaps with the gap between the source electrode of the second transistor and the drain electrode of the second transistor. The first transistor and the second transistor are n-channel transistors. The semiconductor device is characterized by the above.

[0020] In the above structure, the semiconductor layer of the first transistor and the semiconductor layer of the second transistor It is preferable that the alloy contains at least indium (In) or zinc (Zn). In addition, the oxide semiconductor preferably contains Zn. In addition, it contains gallium (Ga) as a stabilizer to reduce variation. It is also preferable to have tin (Sn) as a stabilizer. It is also preferable to have hafnium (Hf) as a stabilizer. It is preferred to have aluminum (Al) as the riser.

[0021] Other stabilizers include the lanthanides lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Ho, Erbium, Thulium, Ytterbium, Ru The element may contain one or more of the elements tetraethynyl (Te) and tetraethynyl (Lu).

[0022] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides , In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, I n-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In -Lu-Zn ​​oxides, In-Sn-Ga-Zn oxides, which are oxides of quaternary metals, I n-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al- Zn-based oxide, In-Sn-Hf-Zn-based oxide, In-Hf-Al-Zn-based oxide are used. There can be.

[0023] In this case, for example, In-Ga-Zn oxide is a material containing In, Ga, and Zn as main components. The ratio of In, Ga, and Zn does not matter. Metal elements other than a and Zn may be present.

[0024] For example, In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:G In-Ga-Zn system oxide with an atomic ratio of a:Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Alternatively, In:Sn:Zn=1 :1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is advisable to use an In--Sn--Zn-based oxide having an atomic ratio or an oxide having a composition close to that. Effect of the Invention

[0025] Since buffer circuits can be configured using only n-channel transistors, This allows the semiconductor circuit to be driven with low power consumption. [Brief description of the drawings]

[0026] [Figure 1] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Diagram 2] 1A and 1B are a cross-sectional view and a top view illustrating one embodiment of the present invention. [Diagram 3] FIG. 1 is a cross-sectional structural view illustrating one embodiment of the present invention. [Figure 4] FIG. 13 is a diagram illustrating the gate voltage dependence of mobility obtained by calculation. [Diagram 5] FIG. 13 is a diagram illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 6] FIG. 13 is a diagram illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 7] FIG. 13 is a diagram illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 8] FIG. 13 illustrates a cross-sectional structure of a transistor used in calculation. [Figure 9] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 10] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. [Figure 11] 1A to 1C are diagrams illustrating a structure of an oxide material according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following description, and various modifications in form and details are possible by those skilled in the art. The present invention is not limited to the description of the following embodiments. It is not something that can be done.

[0028] (Embodiment 1) In this embodiment, it corresponds to an output section used when configuring a buffer circuit or an inverter circuit. An example of the circuit and its configuration will be described with reference to FIG. 1(A), FIG. 2(A), and FIG. 2(B). do.

[0029] The circuit shown in FIG. 1A includes a first transistor 301 and a drain a second transistor 302 having a source electrode electrically connected to the electrode; The gate electrode of the semiconductor device is electrically connected to one of the electrodes of the capacitor 303. The other electrode is electrically connected to the source electrode of the second transistor 302 .

[0030] FIG. 2B is a top view of the second transistor 302. 1(B) is a cross-sectional view corresponding to dashed line AB.

[0031] As shown in FIG. 2B, the drain electrode 315 of the second transistor In other words, the position of one end face of the gate electrode is The second transistor source electrode 314 and the second transistor drain electrode 315 The gap is between the end face of the gate electrode 310 of the second transistor and the drain electrode 315. The distance in the channel length direction at the time of the dc current is indicated as Loff in Fig. 2(B). The longer it is, the smaller the Cp of the capacitance 305 becomes.

[0032] As shown in FIG. 2B, the source electrode 314 of the second transistor The gate electrode 310 of the first transistor overlaps the gate electrode 310 of the second transistor. The distance in the channel length direction from the source electrode 314 to the source electrode 314 is Lov (also called overlap length). 2B. In addition, the source electrode 31 for the oxide semiconductor layer 306 is The protrusion of 4 (or the drain electrode 315) is called dW.

[0033] A manufacturing process of the second transistor 302 using an oxide semiconductor is described below.

[0034] First, an insulating layer serving as a base layer is formed on the substrate 300 with a thickness of 50 nm to 300 nm, preferably 1 The substrate 300 is formed to a thickness of 00 nm or more and 200 nm or less. In addition to the substrate, a plastic substrate or the like that has heat resistance sufficient to withstand the processing temperature of this manufacturing process is used. In addition, when the substrate does not need to be transparent, a metal such as a stainless steel alloy can be used. A substrate having an insulating layer on the surface of a semiconductor substrate may be used.

[0035] The underlayer is aluminum nitride, aluminum oxynitride, silicon nitride, silicon oxide, or nitride. A laminated structure of one or more insulating layers selected from silicon oxide or silicon oxynitride. This has the function of preventing the diffusion of impurity elements from the substrate 300. It is not necessary to provide a base layer.

[0036] Next, a layer of 100 nm or less is deposited on the underlayer using sputtering, vacuum deposition, or plating. A conductive layer is formed to a thickness of 500 nm or less, preferably 200 nm or more and 300 nm or less, A resist mask is formed by a first photolithography process, and the conductive layer is selectively etched. The film is then removed to form the gate electrode 310 .

[0037] The conductive layer for forming the gate electrode 310 is made of molybdenum (Mo), titanium (Ti), or tantalum (Ta). W, Tantalum (Ta), Aluminum (Al), Copper (Cu), Chromium (Cr ), neodymium (Nd), scandium (Sc), or other metallic materials or alloys containing these as the main components. The gold material can be used to form a single layer or a multilayer structure.

[0038] Since the conductive layer will be the wiring, it is preferable to use low resistance materials such as Al and Cu. By using u, it is possible to reduce signal delay and achieve high image quality. It has low heat resistance and is prone to defects due to hillocks, whiskers, or migration. In order to prevent migration of Al, Mo, Ti, W, etc. are added to Al. It is preferable to laminate metal materials with high melting points. In addition, materials containing Al are used for the conductive layers. In this case, it is preferable to set the maximum process temperature in the subsequent steps to 380° C. or less. It is recommended to keep the temperature below 350℃.

[0039] Next, a gate insulating layer 308 is formed on the gate electrode 310 to a thickness of preferably 5 nm to 300 nm. The gate insulating layer 308 is formed to a thickness of 10 nm or more and 200 nm or less. Con, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride , aluminum oxide nitride, tantalum oxide, gallium oxide, yttrium oxide, hafnium oxide Hafnium silicate (HfSi x O y (x>0, y>0)), nitrogen was introduced Hafnium silicate, hafnium aluminate with nitrogen, etc. can be used. The gate insulating layer can be formed by a plasma CVD method, a sputtering method, or the like. The layer 308 is not limited to a single layer, but may be a laminate of different layers.

[0040] Next, a method for forming an oxide semiconductor layer so as to prevent hydrogen, hydroxyl groups, and moisture from being contained in the oxide semiconductor layer is performed. In order to form an oxide semiconductor layer, a base is heated in a preheating chamber of a sputtering apparatus as a pretreatment. The substrate 300 is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 300 and the gate insulating layer 308. It is preferable to desorb and evacuate the impurities.

[0041] In this embodiment, an In-Sn-Zn-O film, which is an oxide semiconductor film, is formed to a thickness of 15 nm. Preferably, the atomic ratio of In:Sn:Zn is 2:1:3, In:Sn:Zn is 1 :2:2, In:Sn:Zn=1:1:1 or In:Sn:Zn=20:45:35 The In-Sn-Zn-O target having the above composition ratio is used. By forming an oxide semiconductor film using a Zn-O target, polycrystalline or CAAC( CAAC: Also called C Axis Aligned Crystal. It becomes.

[0042] The In-Sn-Zn-O film was formed using a sputtering device with a volume ratio of argon:oxygen=2:3. The film is formed in a mixed atmosphere of In: An In-Sn-Zn-O target with an atomic ratio of Sn:Zn = 1:1:1 is used. The substrate heating temperature during film formation is set to 200°C.

[0043] To remove residual moisture in the deposition chamber, an adsorption type vacuum pump, such as a cryopump, is used. It is preferable to use an ion pump or a titanium sublimation pump. The stage may be a turbomolecular pump plus a cold trap. The deposition chamber is evacuated using an opto-pump, and contains hydrogen atoms, water (H2O), and other gases. Since compounds containing carbon atoms (and more preferably compounds containing carbon atoms) are exhausted from the deposition chamber, The concentration of impurities contained in the formed oxide semiconductor layer can be reduced.

[0044] Next, a heat treatment is performed. The heat treatment is performed in a reduced pressure atmosphere, an inert atmosphere, or an oxidizing atmosphere. By the heat treatment, the impurity concentration in the oxide semiconductor film can be reduced.

[0045] The heat treatment is carried out in a reduced pressure or inert atmosphere, and then the temperature is maintained while degassing the material in an acid bath. It is preferable to switch to a chemical atmosphere and carry out further heat treatment. When heat treatment is performed in an active atmosphere, the impurity concentration in the oxide semiconductor film can be effectively reduced. However, at the same time, oxygen vacancies are also generated. This can be reduced by heat treatment in an oxidizing atmosphere.

[0046] In this embodiment, first, a heat treatment is performed in a nitrogen atmosphere for 1 hour, and then the temperature is increased to 250° C. to 650° C. While maintaining the temperature, heat treatment is further performed for 1 hour in an oxygen atmosphere.

[0047] Then, the oxide semiconductor film is processed by a second photolithography process to form an oxide semiconductor In this embodiment, the oxide semiconductor film is etched by dry etching. Etching is performed. BCl3 and Cl2 are used as etching gas. A dry etching device using a high density plasma source such as ECR or ICP is used on top.

[0048] Next, a metal film is formed to form an electrode that functions as a source electrode or a drain electrode. The metal film is made of molybdenum, titanium, tantalum, tungsten, and aluminum. Metallic materials such as copper, chromium, neodymium, and scandium, or alloy materials containing these as the main components The metal film may be formed as a single layer structure or a multilayer structure. Good too.

[0049] Next, the metal film is processed by a third photolithography process to form the source electrode 314 and A drain electrode 315 is formed on the semiconductor substrate 311. Therefore, the source electrode 314 of the second transistor and the drain electrode 31 The position of the gate electrode 310 of the second transistor 302 is determined by the gate insulating layer 5. 314 of the second transistor through the gate electrode 313 of the second transistor. One end surface of the electrode is connected to the source electrode 314 of the second transistor and the drain electrode 315 of the second transistor. It is formed to overlap with the gap of the rain electrode 315 .

[0050] Next, a protective insulating film 320 is formed to cover the source electrode 314 and the drain electrode 315 . It is preferable that the protective insulating film 320 is an insulating film having good step coverage. The materials for 0 include silicon oxide film, gallium oxide film, aluminum oxide film, silicon oxynitride film, etc. The insulating layer can be formed by using a silicon film, an aluminum oxynitride film, or a silicon nitride oxide film. In this embodiment, a silicon oxide film that becomes the protective insulating film 320 is formed by sputtering. The silicon oxide film is formed by sputtering to a thickness of 300 nm. In a rare gas (typically argon) atmosphere, in an oxygen atmosphere, or in a mixture of rare gas and oxygen atmosphere The target may be silicon oxide or silicon. For example, silicon can be used as a target and sputtered in an atmosphere containing oxygen. By performing the above process, a silicon oxide film can be formed.

[0051] In order to remove residual moisture in the deposition chamber during deposition of the protective insulating film 320, an adsorption type evaporator is used. It is preferable to use an air pump (such as a cryopump). The sputtering gas used for the deposition is free of impurities such as hydrogen, water, hydroxyl groups, and hydrides. It is preferable to use a high purity gas.

[0052] Then, the mixture is subjected to a reduced pressure atmosphere, an inert gas atmosphere, an oxygen gas atmosphere, or an ultra-dry air atmosphere. A second heat treatment is performed under atmospheric pressure (preferably at 200° C. or higher and 600° C. or lower, for example at 250° C. or higher and 55° C. or lower). When the second heat treatment is performed, a part of the oxide semiconductor layer (channel The temperature of the formation region is raised while the region is in contact with the protective insulating film 320, and the oxygen-containing protective insulating film 320 From this, oxygen can be supplied to the oxide semiconductor layer 306. Note that the above atmosphere does not include water, hydrogen, or the like. It is preferable that the above is not included.

[0053] Through the above steps, the second transistor 302 shown in FIGS. 2A and 2B is manufactured. can be done.

[0054] The first transistor 301 is formed by the photolithography process described above. The position of the source electrode and the drain electrode of the first transistor 301 is determined by the mask. The source electrode and the drain electrode of the first transistor 301 are connected to the first transistor 302 via a gate insulating layer. 1 overlaps with the gate electrode of transistor 301.

[0055] In the second transistor 302 described in this embodiment, the top surface of the oxide semiconductor layer has a rectangular shape. However, the drain electrode 315 is not limited to a U-shape (C-shape, U-shape, Alternatively, the source electrode 314 may be shaped like a horseshoe or a square. This makes it possible to ensure a sufficient channel width even if the transistor area is small. This makes it possible to increase the amount of current that flows when the transistor is on (also called on-state current). become.

[0056] (Embodiment 2) In this embodiment mode, an example in which the capacitor 303 shown in FIG. 1A is not provided will be described below.

[0057] Instead of the capacitance 303 shown in FIG. 1A, a parasitic capacitance 323 is used as shown in FIG. This allows almost the same operation as the circuit shown in FIG.

[0058] The connection electrode 325 functioning as the source electrode of the second transistor 302 is a part of the parasitic capacitance. The surface of the region that functions as the first electrode and overlaps with the gate electrode 310 of the second transistor 302 The capacity can be increased by widening the product, i.e., by lengthening Lov.

[0059] The drain electrode of the second transistor is the same as that of the first embodiment. The gate electrode 310 and the drain electrode 302 are formed at a position where they do not overlap. The distance between the electrodes 315 is Loff (also called the offset length).

[0060] In addition, the connection electrode 325 functions as a drain electrode of the first transistor 301 .

[0061] The gate electrode 330 of the first transistor 301 is connected to the source electrode 324 and the connection electrode The source electrode 324 and the connection electrode 325 overlap each other. The width of overlap with pole 330, Lov, is approximately the same.

[0062] In this embodiment, since it is not necessary to separately form the capacitor 303, the circuit is simpler than that in the first embodiment. The area occupied by the road can be reduced.

[0063] In addition, this embodiment mode can be freely combined with the first embodiment mode.

[0064] (Embodiment 3) The field-effect mobility of the first transistor 301 used in the circuit illustrated in FIG. 1 of Embodiment 1 is It is desirable that the ratio is high, and is greater than 10, preferably 30 or more, and more preferably 50 or more. A transistor having a field effect mobility is used. The second transistor 302 is It is formed in the same process as the first transistor, and the source electrode overlaps the gate electrode, and the drain The power supply electrode and the gate electrode do not overlap. This reduces the potential difference between VDD and VSS. Even if V A In particular, semiconductors that can obtain high field effect mobility If a material, specifically an In-Sn-Zn-O film, is used for the semiconductor layer, the on-current is not particularly decreased. It's not a problem.

[0065] The field effect mobility of insulated gate transistors, not limited to oxide semiconductors, is actually measured as However, due to various reasons, the mobility becomes lower than it should be. The factors that reduce the mobility are There are defects inside the semiconductor and at the interface between the semiconductor and the insulating film, but the Levinson model Using this method, we can theoretically derive the field effect mobility assuming that there are no defects inside the semiconductor. Can.

[0066] The following calculations are based on a top-gate transistor structure. Even in a multi-gate transistor, a comparable field effect mobility can be obtained.

[0067] The inherent mobility of the semiconductor is μ0, and the measured field-effect mobility is μ. Assuming the existence of potential barriers (such as grain boundaries), this can be expressed by the following equation:

[0068]

number

[0069] where E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. In addition, if we assume that the potential barrier originates from defects, the Levinson model gives , expressed by the following formula:

[0070]

number

[0071] Here, e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the Dielectric constant, n is the number of carriers contained in the channel per unit area, C ox is per unit area Capacity, V g is the gate voltage, and t is the channel thickness. In the case of a semiconductor layer, the thickness of the channel may be the same as the thickness of the semiconductor layer. Drain current I d is expressed by the following formula:

[0072]

number

[0073] Here, L is the channel length and W is the channel width, where L=W=10 μm. Also, V d is the drain voltage. Dividing both sides of the above equation by Vg and then taking the logarithm of both sides gives us It looks like this:

[0074]

number

[0075] The right hand side of number 5 is V g As can be seen from this formula, the vertical axis is ln(Id / Vg), The defect density N is calculated from the slope of the line obtained by plotting the measured values ​​on the horizontal axis of 1 / Vg. That is, the I d -V g From the characteristics, the defect density can be evaluated. As an oxide semiconductor, the ratio of indium (In), tin (Sn), and zinc (Zn) is I In the case of n:Sn:Zn=1:1:1, the defect density N is 1×10 12 / cm 2 That's about it.

[0076] Based on the defect density thus obtained, equations 2 and 3 are used to calculate μ0 = 120 cm 2 / Vs The mobility measured in the defective In-Sn-Zn oxide is 35 cm 2 / V However, the oxide semiconductor without defects inside the semiconductor and at the interface between the semiconductor and the insulating film The mobility of the conductor is μ0 120 cm 2 It can be expected that / Vs.

[0077] However, even if there are no defects inside the semiconductor, there is a possibility that the diffusion of the semiconductor at the interface between the channel formation region and the gate insulating layer may occur. The transport properties of the transistor are affected by the disturbances at the gate-insulator interface. The mobility μ1 at a distance of 1 μ m is expressed by the following formula:

[0078]

number

[0079] Here, D is the electric field in the gate direction, and B and G are constants. B and G are determined by actual measurements. From the above measurement results, B = 4.75 × 10 7 cm / s, G=10 nm (depth of interface scattering). D increases (i.e., gate voltage increases). Since the second term of equation 6 increases, it can be seen that the mobility μ1 decreases.

[0080] A transistor that uses an ideal oxide semiconductor with no internal defects in the channel formation region The results of the calculation of the mobility μ2 of the MOSFET are shown in Figure 4. The calculation was performed using a Synopsys device simulator. Using the Sentaurus Device simulation software, The band gap, electron affinity, dielectric constant, and thickness are 2.8 eV and 4.7 eV, respectively. These values ​​are for thin films formed by sputtering. This was obtained by measurement.

[0081] In addition, the work functions of the gate electrode, source electrode, and drain electrode are set to 5.5 eV. The gate insulating layer was 100 nm thick, 4.6 eV, and 4.6 eV. The channel length and width were both 10 μm, and the drain Voltage V d is 0.1V.

[0082] As shown in Figure 4, the mobility is 100 cm at a gate voltage of just over 1 V. 2 / Vs or higher peak However, if the gate voltage is increased further, the interface scattering increases and the mobility decreases. In order to reduce interface scattering, it is necessary to flatten the semiconductor layer surface at the atomic level (Ato Specifically, the average surface roughness (Ra) The surface has a thickness of 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. A conductor layer may be formed.

[0083] In addition, Ra is the center line average roughness defined in JIS B0601 that can be applied to the surface. This is a three-dimensional extension of the method, which is based on the principle of averaging the absolute value of the deviation from the reference surface to the specified surface. This can be expressed as the "value obtained by dividing the total number of bits by the number of bits" and is defined by the following formula:

[0084]

number

[0085] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y1 )(x2, y2)) and Z0 is the average height of the measurement surface. Ra refers to the strength of the atomic force microscope (AFM). It can be evaluated using OPE.

[0086] The characteristics of a miniaturized transistor manufactured using an oxide semiconductor having such mobility are as follows: The results of the calculations are shown in Figures 5, 6, and 7. The surface structure is shown in Fig. 8. The transistor shown in Fig. 8 has an n-type oxide semiconductor layer. + Conductivity type of The semiconductor region 103a and the semiconductor region 103c are The resistivity of the body region 103c is 2×10 -3 Let it be Ωcm.

[0087] The transistor shown in FIG. 8A includes a base insulator 101 and a The insulating layer 102 is formed on a buried insulator 102 made of aluminum oxide that is formed so as to be The transistor is made up of a semiconductor region 103a and a semiconductor region 103c, and a channel The gate electrode 105 is formed in an intrinsic semiconductor region 103b. The width of 05 is 33 nm.

[0088] Between the gate electrode 105 and the semiconductor region 103b, there is a gate insulating layer 104. On both sides of the gate electrode 105, there are sidewall insulators 106a and 106b, and a gate electrode An insulator 107 is provided on the upper portion of the gate electrode 105 to prevent short circuits between the gate electrode 105 and other wiring. The width of the sidewall insulator is set to 5 nm. A source electrode 108a and a drain electrode 108b are provided in contact with the transistor 103c. The channel width of the transistor is set to 40 nm.

[0089] The transistor shown in FIG. 8B is made of a base insulator 101 and a buried insulating film made of aluminum oxide. The semiconductor region 103a and the semiconductor region 103c are formed on the insulating layer 102. The intrinsic semiconductor region 103b sandwiched between the gate electrode 105 and the gate insulating layer 106 has a width of 33 nm. 104, sidewall insulator 106a, sidewall insulator 106b, insulator 107, and source electrode 10 8(A) in that it has a drain electrode 108a and a drain electrode 108b. do.

[0090] The difference between the transistor shown in FIG. 8A and the transistor shown in FIG. 8B is that the sidewall insulator The conductivity type of the semiconductor region under the sidewall insulator 106a and the sidewall insulator 106b is shown in FIG. In the transistor, the semiconductor regions under the sidewall insulators 106a and 106b are n + The semiconductor region 103a and the semiconductor region 103c have the conductivity type shown in FIG. In the transistor shown in FIG. 8(B), the intrinsic semiconductor region 103b is the intrinsic semiconductor region 103b. In the semiconductor layer, the semiconductor region 103a (the semiconductor region 103c) and the gate electrode 105 are There is a non-overlapping area of ​​Loff. This area is called the offset area, and its width is L As is clear from the figure, the offset length is the length of the sidewall insulator 10 It is the same as the width of 6a (sidewall insulator 106b).

[0091] The first transistor 301 shown in FIG. 3 is a bottom gate type, but the transistor shown in FIG. That is, the semiconductor layer overlapping the gate electrode 105 in FIG. The body region 103b corresponds to the oxide semiconductor layer 326 in FIG. 3, and the n + The conductivity type of The semiconductor region 103a and the semiconductor region 103c are the source electrode 324 and The gate insulating layer 3 corresponds to a contact portion between the connection electrode 325 and the oxide semiconductor layer 326. The interface state between the oxide semiconductor layer 326 and the protective insulating film 320 By reducing the interface state with the SiO2, high field effect mobility was achieved, similar to the results shown in the calculation. It is possible to obtain the following.

[0092] The other parameters used in the calculation are as described above. The simulation software Sentaurus Device was used. The drain current (Id, solid line) and mobility (μ The graph shows the gate voltage (Vg, the potential difference between the gate electrode and the source electrode) dependence of the drain current (Vd, dotted line). The drain voltage (potential difference between the drain electrode and the source electrode) is set to +1V, and the transfer current Id is The degree μ is calculated assuming a drain voltage of +0.1V.

[0093] In Fig. 5(A), the thickness of the gate insulating film is 15 nm, and in Fig. 5(B), the thickness is 10 nm. In FIG. 5(C), it is set to 5 nm.

[0094] FIG. 6 shows a transistor having the structure shown in FIG. 8(B) with an offset length Loff of 5 nm. The gate voltage Vg dependence of the drain current Id (solid line) and mobility μ (dotted line) for the The drain current Id is calculated by setting the drain voltage to +1 V, and the mobility μ is calculated by setting the drain voltage to +0 The calculation was performed with a gate insulating film thickness of 15 nm. FIG. 6(B) shows a case where the thickness is 10 nm, and FIG. 6(C) shows a case where the thickness is 5 nm. do.

[0095] FIG. 7 shows a transistor having the structure shown in FIG. 8B with an offset length Loff of 1 Drain current Id (solid line) and mobility μ (dotted line) dependence on gate voltage for the 5 nm The drain current Id is calculated by assuming a drain voltage of +1 V, and the mobility μ is calculated by assuming a drain voltage of +1 V. The calculation was performed with a voltage of +0.1 V. Figure 7(A) shows the gate insulating film with a thickness of 15 nm. FIG. 7(B) shows the result when the thickness is 10 nm, and FIG. 7(C) shows the result when the thickness is 5 nm. It is.

[0096] In addition, the peak of the mobility μ is 80 cm in Fig. 5. 2 / Vs, but in Figure 6, 2 / Vs, 40 cm in Figure 7 2 / Vs and the offset length Loff increase The off-current also has a similar tendency. On the other hand, the on-current increases with increasing offset length Loff. The decrease with increasing the gate capacitance is much slower than the decrease in the off-state current.

[0097] (Embodiment 4) In this embodiment, the c-axis is oriented and has a triangular or triangular shape when viewed from the ab plane, surface, or interface direction. The atomic arrangement is hexagonal or hexagonal, and the metal atoms are arranged in layers or in a combination of metal atoms and oxygen atoms along the c axis. The molecules are arranged in layers, and the a-axis and b-axis directions are different in the ab plane (the c-axis is the center). C-Axis Aligned Crystal (CAAC) This article will explain oxides containing .

[0098] In a broad sense, oxides containing CAAC are non-single crystals that are not crystalline when viewed from a direction perpendicular to the ab plane. The atomic arrangement is a triangle, a hexagon, an equilateral triangle, or an equilateral hexagon, and is perpendicular to the c-axis direction. From the viewpoint of the direction, it is an acid containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. It refers to a monster.

[0099] CAAC is not a single crystal, but it is not composed of only amorphous matter. AC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is not clearly defined. Sometimes it is not possible to determine with certainty.

[0100] When oxygen is contained in CAAC, a part of the oxygen may be replaced with nitrogen. The c-axes of the individual crystal parts that make up the CAAC are aligned in a certain direction (e.g., the substrate surface on which the CAAC is formed, The CAAC may be aligned in a direction perpendicular to the surface of the CAAC. The normal of the ab plane of each crystal part is in a certain direction (e.g., the substrate surface on which the CAAC is formed, the CA The AC may be oriented in a direction perpendicular to the surface of the AC.

[0101] An example of such a CAAC is a film-like CAAC that is perpendicular to the film surface or the supporting substrate surface. When observed from the direction, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, When the metal atoms are mixed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Crystals may also be mentioned.

[0102] An example of a crystal structure contained in CAAC will be described in detail with reference to FIGS. Unless otherwise specified, the upward direction in FIG. 9 to FIG. 11 is the c-axis direction, and the The plane is the ab plane. When we simply say the upper half and the lower half, we mean the upper half when the ab plane is the boundary. In Figure 9, the circled O indicates a 4-coordinate O, and the double circled O indicates a 4-coordinate O. The O in the figure indicates a three-coordinate O.

[0103] Figure 9(A) shows one hexacoordinate In atom and six tetracoordinate oxygen atoms (hereafter referred to as tetracoordinate) adjacent to the In atom. In this case, there is one metal atom and one oxygen atom nearby. The structure shown in Fig. 9(A) is an octahedral structure, but The upper and lower halves of FIG. 9(A) each have three The small group shown in Figure 9(A) has a charge of 0.

[0104] In Fig. 9(B), one pentagonal Ga atom and three trigonal oxygen atoms (hereafter referred to as trigonal) adjacent to the Ga atom are shown. The structure shows a structure having a tetracoordinate O and two adjacent tetracoordinate O. In the upper and lower halves of Figure 9(B), there is one tetracoordinate O atom. In addition, since In also has a 5-coordinate structure, it can have the structure shown in Figure 9(B). The small group shown has a charge of zero.

[0105] FIG. 9(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 9(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. Or, in Figure 9(C), there are three 4-coordinate O atoms in the upper half and one 4-coordinate O atom in the lower half. There may be O. The small group shown in Figure 9(C) has a charge of 0.

[0106] FIG. 9(D) shows a structure having one hexacoordinate Sn and six tetracoordinate O atoms adjacent to the Sn. In the upper half of Figure 9(D), there are three tetracoordinate O atoms, and in the lower half, there are three tetracoordinate O atoms. The small group shown in Figure 9(D) has a charge of +1.

[0107] Figure 9(E) shows a small group containing two Zn atoms. The upper half of Figure 9(E) shows one 4-coordinate The small group shown in Figure 9(E) has a charge of 1.5-coordinate O, and one 4-coordinate O in the lower half. will be -1.

[0108] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a These are called large groups (also called unit cells).

[0109] Here, we will explain the rules for combining these small groups. The three O's in the upper half of the In configuration each have three adjacent In's downward, and the three in the lower half Each O has three adjacent In atoms in the upward direction. Each O in the bottom half has one neighbor Ga below it, and each O in the bottom half has one neighbor Ga above it. The Zn in the upper half of the 4-coordinated structure shown in FIG. 9(C) has one O atom adjacent to it in the downward direction. Zn, and the three Os in the lower half each have three adjacent Zns in the upward direction. The number of 4-coordinated O atoms above a metal atom is equal to the number of adjacent metal atoms below that O. Similarly, the number of 4-coordinated O atoms below the metal atom and the number of adjacent metal atoms above the O is equal. Since O is 4-coordinated, the number of neighboring metal atoms below is equal to the number of neighboring metal atoms above. The sum of the number of atoms is 4. Therefore, the number of 4-coordinated O atoms above the metal atom and the number of other metal When the sum of the number of tetracoordinated O atoms below the atom is 4, two types of small groups containing metal atoms are The reason is as follows. For example, a 6-coordinate metal atom ( When In or Sn) is bonded through a tetracoordinate O in the lower half, there are three tetracoordinate Os. Therefore, either a five-coordinate metal atom (Ga or In) or a four-coordinate metal atom (Zn) It will be combined with

[0110] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinate oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0111] Figure 10(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 10(B) shows a large group consisting of three medium groups. FIG. 10C shows the atomic arrangement when the layer structure of FIG. 10B is observed from the c-axis direction.

[0112] In FIG. 10(A), for simplicity, the tricoordinate O is omitted, and only the number of the tetracoordinate O is shown. For example, the upper and lower halves of Sn each contain three 4-coordinate O atoms, as shown in the circle. Similarly, in FIG. 10(A), the upper and lower halves of In are Each has one 4-coordinate O atom, which is indicated by the circle 1. Similarly, in Figure 10 In (A), there is one tetracoordinate O in the lower half and three tetracoordinate O in the upper half. Zn with one tetrahedral O atom in the upper half and three tetrahedral O atoms in the lower half. This shows that:

[0113] In FIG. 10(A), the middle group, which is composed of an In-Sn-Zn-O system layer structure, is Sn has three tetracoordinate O atoms in the upper half and three in the lower half, and one tetracoordinate O atom in the upper half. The In is bonded to the In in the upper and lower halves of the Z atom, which has three tetracoordinate O atoms in the upper half. n, and three tetracoordinate O atoms are bonded to the upper half of the Zn via one tetracoordinate O atom in the lower half of the Zn. and In in the lower half, which is bonded to Zn2 with one 4-coordinated O in the upper half. It bonds to a small group of 4-coordinate O atoms in the lower half of this small group. The structure has three O atoms bonded to Sn atoms in the upper and lower halves. Multiple loops are combined to form large groups.

[0114] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.6, respectively. 67, -0.5. For example, In (6 or 5 coordinates), Zn (4 The charges of Sn (5 or 6 coordinated) are +3, +2, and +4, respectively. Therefore, the small group containing Sn has a charge of +1. Therefore, a layer structure containing Sn is formed. To do this, we need a charge of -1 to cancel out the charge of +1. As shown in (E), a small group containing two Zn is included. For example, a small group containing Sn is If there is one small group containing two Zn atoms for every group, the charges are cancelled out. Therefore, the total charge of the layer structure can be set to zero.

[0115] Specifically, the large group shown in FIG. 10(B) is repeated to form the In-Sn-Zn In-Sn-ZnO crystals (In2SnZn3O8) can be obtained. -The layered structure of the Zn-O system is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) This can be expressed by the composition formula:

[0116] For example, Figure 11(A) shows a model of the middle group consisting of an In-Ga-Zn-O layer structure. A diagram of the rule is shown.

[0117] In FIG. 11(A), the middle group, which is made up of an In-Ga-Zn-O-based layer structure, is In the upper half and lower half, there are three tetracoordinate O atoms, and in the lower half, there is one tetracoordinate O atom. It bonds to Zn at the bottom of the Zn atom, and one tetracoordinate O atom is bonded to the Zn atom via the three tetracoordinate O atoms in the bottom half of the Zn atom. It bonds to Ga in the upper and lower halves, respectively, and is bonded to one tetracoordinate O in the lower half of the Ga. The structure is such that three 4-coordinate O atoms are bonded to In atoms in the upper and lower halves. These medium groups combine to form large groups.

[0118] Figure 11(B) shows a large group consisting of three medium groups. 11(B) shows the atomic arrangement when the layer structure of FIG. 11(B) is observed from the c-axis direction.

[0119] Here, the charges of In (6 or 5 coordinates), Zn (4 coordinates), and Ga (5 coordinates) are Since the valence numbers are +3, +2, and +3, respectively, the small group containing either In, Zn, or Ga is , the charge is 0. Therefore, if these small groups are combined, the combination of the medium groups The total charge will always be zero.

[0120] The middle group, which is made up of an In-Ga-Zn-O-based layer structure, is shown in FIG. Not limited to the middle group, large-scale combination of middle groups with different arrangements of In, Ga, and Zn Groups are also possible.

[0121] The CAAC described above can be obtained by the manufacturing process described in embodiment 1. The CAAC has an average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, and more preferably In addition, if the heating temperature during film formation is high, CA AC is easily formed.

[0122] This embodiment mode can be freely combined with other embodiment modes. [Explanation of symbols]

[0123] 101 Undercoat insulation 103 Semiconductor area 104 Gate insulation layer 105 Gate electrode 106 Sidewall Insulation 107 Insulation 108 electrode 108a Source electrode 108b Drain electrode 300 Substrates 301 First transistor 302 Second transistor 303 capacity 304 Control Unit 305 capacity 306 Oxide semiconductor layer 308 Gate Insulation Layer 314 Source Electrode 315 Drain electrode 320 Protective insulating film 323 Parasitic capacitance 324 Source Electrode 325 Connection electrode 326 Oxide Semiconductor Layer 330 Gate electrode

Claims

1. a first transistor and a second transistor; A semiconductor device having a function of controlling an output potential in accordance with a conduction state of the first transistor and a conduction state of the second transistor, a first conductive film functioning as a first gate electrode of the first transistor; a second conductive film functioning as a second gate electrode of the second transistor; a first oxide semiconductor film having a channel formation region of the first transistor; a second oxide semiconductor film having a channel formation region of the second transistor; a third conductive film having a region disposed above the first oxide semiconductor film; a fourth conductive film having a region disposed above the first oxide semiconductor film and a region disposed above the second oxide semiconductor film; a fifth conductive film having a region disposed above the second oxide semiconductor film; an insulating film having a region in contact with an upper surface of the third conductive film, a region in contact with an upper surface of the fourth conductive film, and a region in contact with an upper surface of the fifth conductive film; the third conductive film functions as one of a source and a drain of the first transistor, the fourth conductive film functions as the other of the source and the drain of the first transistor and also functions as one of the source and the drain of the second transistor; the fifth conductive film functions as the other of the source and the drain of the second transistor, a region where the fourth conductive film overlaps with the second conductive film is larger than a region where the fourth conductive film overlaps with the first conductive film; a region where the second oxide semiconductor film overlaps with the second conductive film is separated from a region where the second oxide semiconductor film overlaps with the fifth conductive film in a plan view; the potential is output via the fourth conductive film. Semiconductor device.

2. a first transistor and a second transistor; A semiconductor device having a function of controlling an output potential in accordance with a conduction state of the first transistor and a conduction state of the second transistor, a first conductive film functioning as a first gate electrode of the first transistor; a second conductive film functioning as a second gate electrode of the second transistor; a first oxide semiconductor film having a channel formation region of the first transistor; a second oxide semiconductor film having a channel formation region of the second transistor; a third conductive film having a region disposed above the first oxide semiconductor film; a fourth conductive film having a region disposed above the first oxide semiconductor film and a region disposed above the second oxide semiconductor film; a fifth conductive film having a region disposed above the second oxide semiconductor film; an insulating film having a region in contact with an upper surface of the third conductive film, a region in contact with an upper surface of the fourth conductive film, and a region in contact with an upper surface of the fifth conductive film; the third conductive film functions as one of a source and a drain of the first transistor, the fourth conductive film functions as the other of the source and the drain of the first transistor and also functions as one of the source and the drain of the second transistor; the fifth conductive film functions as the other of the source and the drain of the second transistor, a region where the fourth conductive film overlaps with the second conductive film is larger than a region where the fourth conductive film overlaps with the first conductive film; a region where the second oxide semiconductor film overlaps with the second conductive film is separated from a region where the second oxide semiconductor film overlaps with the fifth conductive film in a plan view; a first potential applied to the fifth conductive film is higher than a second potential applied to the third conductive film; the potential is output via the fourth conductive film. Semiconductor device.

3. In claim 1 or 2, each of the first oxide semiconductor film and the second oxide semiconductor film is an oxide containing indium or zinc; Semiconductor device.

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