Circuit arrangement and physical quantity sensor

Abstract

To allow failure detection to be performed during use of a detection circuit.SOLUTION: A circuit arrangement comprises: a detection circuit that includes a first A / D conversion circuit performing A / D conversion of a signal output from a sensor element and outputting a first digital signal, and generates a detection signal on the basis of the first digital signal; a pseudo detection circuit that includes a second A / D conversion circuit performing A / D conversion of a signal output from the sensor element and outputting a second digital signal, and generates a pseudo detection signal on the basis of the second digital signal; and a failure detection circuit that detects a failure in the detection circuit on the basis of a comparison result of comparison between the value of the detection signal and the value of the pseudo detection signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit device and a physical quantity sensor. [Background technology]

[0002] There is known a configuration for detecting a fault in a circuit device. For example, Patent Document 1 discloses a configuration in which a diagnostic process is executed after power is turned on and before a normal operation period. The diagnostic process inputs a diagnostic signal to a detection circuit that detects an output signal of a physical quantity transducer, and diagnoses whether the detection circuit is operating normally based on the response to the signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-170136 A Summary of the Invention [Problem to be solved by the invention]

[0004] Faults may occur while the detection circuit is in use, and it would be desirable to be able to detect faults while the detection circuit is in use, and not just prior to periods of normal operation. [Means for solving the problem]

[0005] The circuit device is equipped with: a detection circuit including a first A / D conversion circuit that performs A / D conversion on the signal output from the sensor element and outputs a first digital signal, and generates a detection signal based on the first digital signal; a pseudo detection circuit including a second A / D conversion circuit that performs A / D conversion on the signal output from the sensor element and outputs a second digital signal, and generates a pseudo detection signal based on the second digital signal; and a fault detection circuit that detects a fault in the detection circuit based on a comparison result between the value of the detection signal and the value of the pseudo detection signal.

[0006] The physical quantity sensor includes a sensor element, a detection circuit including a first A / D conversion circuit that performs A / D conversion on a signal output from the sensor element and outputs a first digital signal and generates a detection signal based on the first digital signal, a pseudo detection circuit including a second A / D conversion circuit that performs A / D conversion on the signal output from the sensor element and outputs a second digital signal and generates a pseudo detection signal based on the second digital signal, and a fault detection circuit that detects a fault in the detection circuit based on a comparison result between the value of the detection signal and the value of the pseudo detection signal. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram of a physical quantity sensor including a circuit device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing a configuration example of a driver circuit. [Diagram 3] FIG. 4 is a diagram showing an example of the configuration of a detection circuit and a pseudo detection circuit. [Figure 4] 4A and 4B are diagrams showing examples of input and output of a clip processing unit; [Diagram 5] 4A and 4B are diagrams showing examples of input and output of a clip processing unit; [Figure 6] FIG. 2 is a diagram showing an example of the configuration of a failure detection circuit. [Figure 7] FIG. 4 is a diagram showing an example of the configuration of a value determination unit. [Figure 8] FIG. 4 is a diagram showing an example of the configuration of a change rate determination unit. [Figure 9] A diagram showing a sine wave. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] 1. First embodiment Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. Furthermore, not all of the configurations described below are necessarily essential configuration conditions of the present invention. Below, the embodiments will be described using a sensor element that detects angular velocity, i.e., an angular velocity sensor, as an example.

[0009] Fig. 1 is a block diagram showing an example of the configuration of a physical quantity sensor 1 including a circuit device of the present embodiment. The physical quantity sensor 1 shown in Fig. 1 includes a sensor element 10, a drive circuit 20, an amplifier circuit 30, a detection circuit 40, a pseudo detection circuit 50, a fault detection circuit 60, a control unit 70, a register unit 80, and a temperature sensor 90.

[0010] In this embodiment, the sensor element 10 is an angular velocity sensor. The angular velocity sensor can be realized by various known configurations. For example, the sensor element 10 can be configured by an element that outputs vibration based on the Coriolis force acting on the vibrating arm. Of course, the shape of the sensor is not limited, and sensors of various shapes such as double T type, tuning fork type, and H type can be used.

[0011] The sensor element 10 has an input terminal to which a drive signal DQ is input from the drive circuit 20, and an output terminal to which a feedback signal DI is output to the drive circuit 20. In this embodiment, the input terminal is electrically connected to a pad PD4. The output terminal is electrically connected to a pad PD3. The sensor element 10 has two detection signal output terminals that output detection signals, and each detection signal output terminal is electrically connected to a pad PD1, PD2.

[0012] The drive circuit 20 drives the sensor element 10. The drive circuit 20 is electrically connected to the sensor element 10 via pads PD3 and PD4. The drive circuit 20 receives a feedback signal DI from the sensor element 10 via pad PD3, and drives the sensor element 10 by outputting a drive signal DQ corresponding to the feedback signal DI via pad PD4.

[0013] The driving circuit 20 can be realized by various known circuits. Fig. 2 shows an example of the configuration of the driving circuit 20. The driving circuit 20 shown in Fig. 2 can be realized by a configuration including a current-voltage converter (I / V converter) 21, a gain control circuit 22, a comparator 23, and a comparator 24. Each of these circuits can be realized by a known configuration.

[0014] In the example shown in FIG. 2, when a feedback signal DI is input from the sensor element 10 to the current-voltage converter 21 via the pad PD3, the current-voltage converter 21 converts it into an AC voltage signal having the same frequency as the vibration frequency of the feedback signal DI and outputs it.

[0015] The AC voltage signal output from the current-voltage converter 21 is input to the comparator 23 and the comparator 24. The comparator 23 converts the AC voltage signal from the current-voltage converter 21 into a square wave and inputs it to the sensor element 10 as a drive signal DQ. As a result, the sensor element 10 is driven by the drive signal DQ. The gain control circuit 22 controls the reference voltage of the comparator 23 so as to maintain the amplitude of the input AC voltage signal at a constant value.

[0016] The comparator 24 compares the AC voltage signal with a reference voltage signal, using the center of amplitude of the AC voltage signal from the current-voltage converter 21 as a reference voltage, and outputs a square-wave voltage signal whose output level changes so that the output is high when the former is large and low when the latter is large. The square-wave voltage signal is a signal generated based on the drive signal DQ, and is used for synchronous detection, which will be described later, so that the square-wave voltage signal is referred to as a synchronous detection signal SDET here. The synchronous detection signal SDET is input to the detection circuit 40 and the pseudo detection circuit 50.

[0017] The sensor element driven by the drive circuit 20 outputs first and second detection signals IQ1, IQ2 from the detection signal output terminals. The first and second detection signals IQ1, IQ2 are differential signals, and are input to the amplifier circuit 30 via the pads PD1, PD2. The amplifier circuit 30 is a Q / V conversion circuit, and has a Q / V conversion circuit to which the first detection signal IQ1 is input, and a Q / V conversion circuit to which the second detection signal IQ2 is input. The Q / V conversion circuit (charge amplifier) ​​is a circuit that converts a charge signal (a minute charge signal, a minute current signal) from the sensor element 10 into a voltage signal, and can also be considered as a type of I / V conversion circuit.

[0018] The first and second detection signals IQ1 and IQ2 are converted into differential signals having opposite phases, and the output first and second voltage signals are also differential signals having opposite phases, but for simplicity, the output signal is shown by a single arrow in Fig. 1. The first and second voltage signals output from the amplifier circuit 30 are input to the detection circuit 40 and the pseudo detection circuit 50.

[0019] The detection circuit 40 is a circuit that outputs a detection signal indicating the angular velocity detected by the sensor element 10, based on the first and second voltage signals output from the amplifier circuit 30. A detailed configuration of the detection circuit 40 will be described later.

[0020] The pseudo detection circuit 50 includes a circuit that simulates the operation of the detection circuit 40 based on the first and second voltage signals output from the amplifier circuit 30, and outputs a pseudo detection signal that imitates the detection signal. The detailed configuration of the pseudo detection circuit 50 will be described later.

[0021] The fault detection circuit 60 is a circuit that performs fault detection of the detection circuit based on a comparison result between the value of the detection signal output from the detection circuit 40 and the value of the pseudo detection signal output from the pseudo detection circuit 50. A detailed configuration of the fault detection circuit 60 will be described later.

[0022] The control unit 70 performs various control processes. For example, the control unit 70 performs control processes for the detection circuit 40, the pseudo detection circuit 50, and the fault detection circuit 60. The control unit 70 can be realized by, for example, a logic circuit generated by an automatic placement and wiring method such as a gate array, or a processor that operates based on firmware or the like.

[0023] The register unit 80 has a register in which various information is stored. The register unit 80 can be realized by, for example, a memory such as an SRAM, a flip-flop circuit, or the like. In this embodiment, the various information stored in the register unit 80 includes gain (det_gain, Vth_gain), offset (det_offs, Vth_offs), a second threshold del_Vth, a filter coefficient, and the like, which will be described later. These pieces of information are acquired by the control unit 70 and supplied to each circuit.

[0024] The temperature sensor 90 is a sensor that outputs a signal (temperature signal) with a voltage level according to the temperature around it, and may be a positive polarity sensor that outputs a higher output voltage as the temperature increases, or a negative polarity sensor that outputs a lower output voltage as the temperature increases. The temperature sensor 90 may be, for example, a circuit that outputs a voltage proportional to absolute temperature (PTAT (Proportional To Absolute Temperature) voltage). The temperature signal output from the temperature sensor 90 is input to the pseudo detection circuit 50.

[0025] 1.1 Detection circuit configuration: Next, the configuration of the detection circuit 40 will be described in detail. FIG. 3 shows an example of the configuration of the detection circuit 40. In this example, the detection circuit 40 includes a PGA (Programmable Gain Amplifier) ​​41, a first synchronous detection circuit 42, a first low-pass filter (first LPF) 43, a first A / D conversion circuit (first ADC) 44, a clip processing unit 45, an IIR (Infinite Impulse Response) filter 46, and a DSP (Digital Signal Processor) 47. The PGA 41, the first synchronous detection circuit 42, the first low-pass filter 43, and the first A / D conversion circuit 44 can each be realized by various known analog circuits. The clip processing unit 45, the IIR filter 46, and the DSP 47 can each be realized by various known digital circuits. The digital circuits may be realized by various integrated circuits such as a CPU, or may be realized by a programmable gate array or the like.

[0026] The PGA 41 is a circuit that amplifies the signal output from the amplifier circuit 30. The PGA 41 includes a differential amplifier circuit and an AC amplifier circuit, and performs differential amplification based on the first and second voltage signals that are the differential signals output from the amplifier circuit 30, and further amplifies the resulting signal.

[0027] The first synchronous detection circuit 42 is a multiplication circuit that performs synchronous detection by multiplying the signal output from the PGA 41 by the synchronous detection signal SDET output from the comparator 24. In addition, the first low-pass filter 43 is a circuit that smoothes the signal output from the first synchronous detection circuit 42. The first synchronous detection circuit and the first low-pass filter 43 generate a signal having a voltage value corresponding to the angular velocity detected by the sensor element 10, and output from the first low-pass filter 43.

[0028] The first A / D conversion circuit 44 is a circuit that performs A / D conversion on the signal output from the first low-pass filter 43 and outputs it as a first digital signal Dt1. The DSP 47 performs various processes based on the first digital signal Dt1, and generates a detection signal to be output to the outside of the physical quantity sensor 1. The various processes may be known processes, such as various filtering processes and temperature compensation processes. The filtering process may be the same process as the process by the IIR filter 46. The DSP 47 may output the generated detection signal to the outside via an interface (not shown), or may output it to the control unit 70. In this case, the control unit 70 may store the detection signal in a register unit 80 or the like, and output it to the outside in response to a request from an external device or the like.

[0029] In the clip processing unit 45, when an instruction is given by the signal clip_flg from the clip processing unit 55 described later, the magnitude of the output signal output from the clip processing unit 45 is set to a fixed value. Moreover, when an instruction is not given by the signal clip_flg from the clip processing unit 55, the clip processing unit 45 outputs the input signal to the clip processing unit 45 as it is. In other words, the clip processing unit 45 is a circuit that limits the magnitude of the output signal to a fixed value or less, and when limited by the clip processing unit 45, the magnitude of the detection signal output from the IIR filter 46 described later becomes a fixed value.

[0030] The IIR filter 46 is a filter having various functions such as removing signals in a predetermined frequency band. In this embodiment, the control unit 70 determines the filter coefficient of the IIR filter 46 based on the filter coefficient stored in the register unit 80. The IIR filter 46 applies a filter having characteristics determined by the filter coefficient to an input signal and outputs a detection signal Sr. The IIR filter 46 is used, for example, to remove signals in a frequency band different from the angular velocity of the detection target detected by the sensor element 10. The detection signal Sr output from the IIR filter 46 is input to the failure detection circuit 60.

[0031] 1.2 Configuration of pseudo-detection circuit: Next, the configuration of the pseudo detection circuit 50 will be described in detail. FIG. 3 shows an example of the configuration of the pseudo detection circuit 50. In this example, the pseudo detection circuit 50 includes a PGA (Programmable Gain Amplifier) ​​51, a second synchronous detection circuit 52, a second low-pass filter (second LPF) 53, a second A / D conversion circuit (second ADC) 54, a clip processing unit 55, and an IIR (Infinite Impulse Response) filter 56. The PGA 51, the second synchronous detection circuit 52, the second low-pass filter 53, and the second A / D conversion circuit 54 can each be realized by various known analog circuits. The clip processing unit 55 and the IIR filter 56 can be realized by various known digital circuits. The digital circuits may be realized by various integrated circuits such as a CPU, or may be realized by a programmable gate array or the like.

[0032] The second synchronous detection circuit 52 is a multiplication circuit that performs synchronous detection by multiplying the signal output from the amplifier circuit 30 by the synchronous detection signal SDET output from the comparator 24. In addition, the second low-pass filter 53 is a circuit that smoothes the signal output from the second synchronous detection circuit 52. According to the second synchronous detection circuit and the second low-pass filter 53, a signal having a voltage value corresponding to the angular velocity detected by the sensor element 10 is generated and output from the second low-pass filter 53.

[0033] The PGA 51 is a circuit that amplifies the signal output from the second low-pass filter 53. The PGA 51 includes a differential amplifier circuit and an AC amplifier circuit, performs differential amplification based on the signals output from the second low-pass filter 53, and further amplifies the obtained signals. The second A / D conversion circuit 54 is a circuit that A / D converts the signal output from the PGA 51 and outputs it as a second digital signal Dt2.

[0034] The clipping processor 55 executes a process of limiting the magnitude of the output signal to a fixed value when the magnitude (absolute value) of the input signal exceeds a predetermined value, and of treating the input signal as is as the output signal when the magnitude of the input signal is equal to or less than the predetermined value. The predetermined value is a magnitude that is determined in advance and is smaller than the maximum value of the input range of the second A / D conversion circuit 54. In other words, the clipping processor 55 is a circuit that limits the magnitude of the output signal to a fixed value or less, and when the output signal is limited by the clipping processor 55, the magnitude of the pseudo detection signal output from the IIR filter 56 described later becomes a fixed value.

[0035] Furthermore, when the magnitude (absolute value) of the input signal exceeds a predetermined value, the clip processing unit 55 outputs a signal clip_flg indicating an instruction to start clipping to the clip processing unit 45. Therefore, in the clip processing unit 45, when an instruction is given by the signal clip_flg from the clip processing unit 55 described later, the magnitude of the output signal output from the clip processing unit 45 is set to a fixed value. Furthermore, when no instruction is given by the signal clip_flg from the clip processing unit 55, the clip processing unit 45 uses the input signal to the clip processing unit 45 as it is as an output signal. Note that the clip processing unit 55 also outputs the signal clip_flg to the value determination unit 64, and controls the enabling and disabling of value determination by the signal clip_flg.

[0036] The IIR filter 56 is a filter having various functions such as removing signals in a predetermined frequency band. In this embodiment, the control unit 70 determines the filter coefficient of the IIR filter 56 based on the filter coefficient stored in the register unit 80. The IIR filter 56 applies a filter having characteristics determined by the filter coefficient to an input signal, and outputs a pseudo detection signal Sp. In this embodiment, the filter coefficient of the IIR filter 56 is set to a value that outputs a signal having the same characteristics as the IIR filter 46, for example. The pseudo detection signal Sp output from the IIR filter 56 is input to the fault detection circuit 60.

[0037] In this embodiment, the pseudo detection circuit 50 includes switches SW1 to SW4. The switch SW1 is provided between the second low-pass filter 53 and the PGA 51, and the switch SW4 is provided between the second A / D conversion circuit 54 and the clip processing unit 55. The switch SW2 is provided between the temperature sensor 90 and the PGA 51, and the switch SW3 is provided between the second A / D conversion circuit 54 and the DSP 47.

[0038] The switches SW1 to SW4 are controlled to be turned on and off by control signals SEL1 and SEL2 output from the control unit 70. The control signals SEL1 and SEL2 are opposite in phase to each other, and when the control signal SEL1 is on, the control signal SEL2 is off. When the control signal SEL1 is off, the control signal SEL2 is on.

[0039] The switches SW1 and SW4 are controlled by a control signal SEL1, and the switches S2 and S3 are controlled by a control signal SEL2. Therefore, when the switches SW1 and SW4 are turned on by the control signal SEL1, the switches SW2 and SW3 are turned off by the control signal SEL2. In this state, the pseudo detection circuit 50 is not electrically connected to the temperature sensor 90 and the DSP 47, and the pseudo detection circuit 50 is in a state in which it outputs a pseudo detection signal Sp based on the output signal from the amplifier circuit 30.

[0040] When the switches SW1 and SW4 are turned off by the control signal SEL1, the switches SW2 and SW3 are turned on by the control signal SEL2. In this state, the output signal of the second low-pass filter 53 of the pseudo detection circuit 50 is not supplied to the PGA 51, and the output signal of the second A / D conversion circuit 54 is not supplied to the clip processing unit 55. Therefore, the pseudo detection signal Sp is not output. In this state, the temperature sensor 90 is connected to the PGA 51, and the output signal of the second A / D conversion circuit 54 is input to the DSP 47. Therefore, the signal detected by the temperature sensor 90 is amplified in the PGA 51, and converted into a digital temperature detection signal by the second A / D conversion circuit 54 and input to the DSP 47.

[0041] Although the transmission path of the output signal of the temperature sensor 90 is indicated by a single arrow, the output signal of the temperature sensor 90 in this embodiment is a differential signal, and two types of signals are input to the PGA 51. Therefore, the PGA 51 differentially amplifies the signal output by the temperature sensor 90, similar to the signal output by the second low-pass filter 53. The second A / D conversion circuit 54 converts the signal after differential amplification into a digital temperature detection signal and outputs it to the DSP 47.

[0042] As a result, the DSP 47 can acquire the temperature detected by the temperature sensor 90. Based on the acquired temperature detection signal, the DSP 47 performs a temperature compensation process on the detection signal generated from the signal output from the sensor element 10. That is, the DSP 47 performs a predetermined process based on the first digital signal Dt1 to acquire a detection signal indicating the detection result by the sensor element 10, and at this time, performs a correction to offset the characteristic change of the sensor element 10 due to temperature.

[0043] In this embodiment, the control unit 70 controls the switches SW1 to SW4 to switch between a state in which the pseudo detection signal Sp is output from the pseudo detection circuit 50 and a state in which temperature compensation processing is performed based on the detection result of the temperature sensor 90. That is, under the control of the control unit 70, the second A / D conversion circuit 54 performs A / D conversion for generating the pseudo detection signal Sp and A / D conversion for generating the temperature detection signal in a time-division manner. With the above configuration, it is possible to generate the pseudo detection signal Sp and the temperature detection signal using a common circuit, and the physical quantity sensor 1 can be realized at low cost.

[0044] In this embodiment, the circuit is configured in the order of inputting the output signal of the PGA 51 to the second A / D conversion circuit 54 in order to generate a temperature detection signal from the detection result of the temperature sensor 90. However, if temperature compensation processing based on the temperature detection signal is not performed or if temperature compensation processing is performed without sharing with the circuit of the pseudo detection circuit 50, the order of the circuits is not limited. Therefore, in this case, the circuit may be configured so that processing is performed in the same order as the detection circuit 40, for example, in the order of the PGA 51, the second synchronous detection circuit 52, the second low-pass filter 53, and the second A / D conversion circuit 54.

[0045] In this embodiment, the second A / D conversion circuit 54 is used not only to generate the pseudo detection signal Sp but also to generate the temperature detection signal, and is therefore configured as a circuit having a necessary and sufficient performance for generating the temperature detection signal. Therefore, it does not need to have a necessary and sufficient performance for detecting the physical quantity by the sensor element 10, and may be a simpler circuit than the first A / D conversion circuit 44 used in the detection circuit 40.

[0046] Therefore, in this embodiment, the second A / D conversion circuit 54 is configured by a circuit whose resolution is lower than that of the first A / D conversion circuit 44. Specifically, the resolution of the first A / D conversion circuit 44 is 16 bits, while the resolution of the second A / D conversion circuit 54 is 10 bits. With the above configuration, the physical quantity sensor 1 can be realized at low cost compared to a case in which the second A / D conversion circuit 54 is configured by using a circuit equivalent to the first A / D conversion circuit 44 used in the detection circuit 40.

[0047] Furthermore, in this embodiment, the second A / D conversion circuit 54 is configured with a simpler circuit than the first A / D conversion circuit 44, so the input range of the second A / D conversion circuit 54 is smaller than that of the first A / D conversion circuit 44. For example, a configuration is adopted in which the input range of the second A / D conversion circuit 54 is 1.2V, while the input range of the first A / D conversion circuit 44 is 1.8V. In this configuration, the second A / D conversion circuit 54 converts an analog voltage signal of -1.2V to 1.2V into a second digital signal Dt2. On the other hand, the first A / D conversion circuit 44 converts an analog voltage signal of -1.8V to 1.8V into a first digital signal Dt1.

[0048] In this embodiment, the PGA 51, the second synchronous detection circuit 52, and the second low-pass filter 53 have the same functions as the PGA 41, the first synchronous detection circuit 42, and the first low-pass filter 43, and the characteristics of the transfer functions are similar. However, the circuits are not completely identical, and the gains of the PGAs 41 and 51 may differ, so the functional forms of the transfer characteristics (the degree of the variables, the variables appearing in the denominator and numerator, and the forms of addition, subtraction, multiplication, and division for the variables) are the same. On the other hand, the coefficients included in the transfer functions are close to each other but are not completely the same. For this reason, in this embodiment, the magnitude of the signal input to the first A / D conversion circuit 44 based on the signal from the sensor element 10 and the magnitude of the signal input to the second A / D conversion circuit 54 are almost the same in terms of design, and the change characteristics (such as the rate of change over time) are almost the same.

[0049] In this embodiment, the failure detection circuit 60 judges the failure based on whether the difference between the detection signal Sr generated based on the first digital signal Dt1 output by the first A / D conversion circuit 44 and the pseudo detection signal Sp generated based on the second digital signal Dt2 output by the second A / D conversion circuit 54 is greater than a threshold value (details will be described later). Therefore, if the magnitude of the detection signal Sr and the magnitude of the pseudo detection signal Sp deviate beyond a reference even though the circuit is normal, the failure is judged. Such a situation may occur due to the difference in input range between the first A / D conversion circuit 44 and the second A / D conversion circuit 54. For example, a situation may occur in which the output signal of the PGA 51 exceeds the input range of the second A / D conversion circuit 54, but the output signal of the first low-pass filter 43 does not exceed the input range of the first A / D conversion circuit 44. In this case, the second digital signal Dt2 output from the second A / D conversion circuit 54 is a saturated value (e.g., a digital value corresponding to an input analog voltage of 1.2 V), while the first digital signal Dt1 output from the first A / D conversion circuit 44 is a non-saturated value (e.g., a digital value corresponding to an input analog voltage of 1.5 V).

[0050] In this case, the difference between the detection signal Sr and the pseudo detection signal Sp becomes larger than the threshold value, but this situation is not a malfunction. Therefore, in this embodiment, when the magnitude of the second digital signal Dt2 output from the second A / D conversion circuit 54, which has a relatively small input range, exceeds a predetermined value, the first digital signal Dt1 and the second digital signal Dt2 are clipped by the clip processing unit 45 and the clip processing unit 55, respectively, and the above-mentioned determination based on the difference is not performed. That is, when the magnitude of the second digital signal Dt2 output from the second A / D conversion circuit 54 and input to the clip processing unit 55 exceeds a predetermined value, it is considered that the magnitude of the input signal to the second A / D conversion circuit 54 may be a value exceeding the input range, and the malfunction determination is invalidated.

[0051] 4 is a diagram showing the input signal In1 and output signal Out1 of the clip processing unit 45, the input signal In2 and output signal Out2 of the clip processing unit 55, and clip_flg output from the second A / D conversion circuit 54. In FIG. 4, the horizontal axis represents time and the vertical axis represents signal level. As shown in FIG. 4, when the magnitude (absolute value) of the input signal In1 to the clip processing unit 55 exceeds a predetermined value Thi, the output signal Out2 is clipped and fixed to the predetermined value Thi. In the example shown in FIG. 4, during the periods from time t1 to t2 and from time t3 to t4, the magnitude (absolute value) of the input signal In1 exceeds the predetermined value Thi, and the output signal Out2 is clipped.

[0052] When clipping is performed in the clip processing unit 55, the clip processing unit 55 outputs a signal clip_flg indicating an instruction to start clipping to the clip processing unit 45. As a result, the input signal In1 to the clip processing unit 45 shown in FIG. 4 is clipped during the periods from time t1 to t2 and from time t3 to t4, and becomes the output signal Out1. The predetermined value for determining whether or not to perform clipping is a value smaller than the maximum value of the input range of the second A / D conversion circuit 54. Therefore, when clipping is performed when the second digital signal Dt2 is equal to or greater than the predetermined value, clipping is performed at least in a situation where the magnitude of the input signal to the second A / D conversion circuit 54 exceeds the maximum value of the input range. When clipping is performed, the fault detection circuit 60 described later is disabled, so that the fault detection circuit 60 can be disabled in a situation where the magnitude of the input signal to the second A / D conversion circuit 54 exceeds the maximum value of the input range and the second digital signal Dt2 cannot reflect the magnitude of the input signal to the second A / D conversion circuit 54. According to the above configuration, when making a determination based on the difference between the output results of A / D conversion circuits having different input ranges, it is possible to prevent erroneous determination caused by differences in the input ranges.

[0053] On the other hand, when the detection circuit 40 is broken, the magnitude of the second digital signal Dt2 does not exceed the predetermined value, but the magnitude of the first digital signal Dt1 may deviate from the magnitude of the second digital signal Dt2. Typically, a possible failure mode is one in which the first digital signal Dt1, which is the output from the first A / D conversion circuit 44, is saturated at the maximum positive value or the maximum negative value. In such a case, the output from the second A / D conversion circuit 54 does not exceed the predetermined value, so clipping is not performed by the clipping processing units 55, 45.

[0054] FIG. 5 shows an example in which, for example, the PGA 41 fails at time t0, and the first digital signal Dt1 output from the first A / D conversion circuit 44, i.e., the input signal In1 to the clipping processor 45, is saturated. In this example, the second digital signal Dt2 output from the second A / D conversion circuit 54, i.e., the input signal In2 to the clipping processor 55, is equal to or lower than a predetermined value Thi at time t0, so clipping is not performed. Therefore, the fault detection circuit 60 is enabled. In this situation, the output from the clipping processor 45 is also saturated, so the detection signal Sr output from the detection circuit 40 becomes large. As a result, the difference between the detection signal Sr and the pseudo detection signal Sp becomes larger than the threshold value, and the fault can be detected by the fault detection circuit 60.

[0055] In this embodiment, whether or not to perform clipping is determined based on the magnitude of the output signal of the second A / D conversion circuit 54. However, since the magnitude of the input signal to the second A / D conversion circuit 54 and the magnitude of the output signal correspond to each other, whether or not to perform clipping may be determined based on the magnitude of the input signal to the second A / D conversion circuit 54.

[0056] 1.3 Configuration of the fault detection circuit: Next, the configuration of the fault detection circuit 60 will be described in detail. Fig. 6 is a diagram showing the configuration of the fault detection circuit 60. The fault detection circuit 60 is a digital circuit that performs predetermined processing based on the detection signal Sr output from the IIR filter 46 included in the detection circuit 40 and the pseudo detection signal Sp output from the IIR filter 56 included in the pseudo detection circuit 50. The digital circuit may be realized by various integrated circuits such as a CPU, or may be realized by a programmable gate array or the like. Fig. 6 is a diagram showing the digital processing divided into blocks for each function.

[0057] The fault detection circuit 60 includes a rate of change determination unit 61, a multiplication unit 62, an addition unit 63, a value determination unit 64, and a fault determination unit 65. The detection signal Sr and the pseudo detection signal Sp are input to the fault detection circuit 60, and in this embodiment, the pseudo detection signal Sp is multiplied by a gain (det_gain) by the multiplication unit 62, and an offset (det_offs) is added by the addition unit 63. The gain (det_gain) and the offset (det_offs) are determined in advance and stored in the register unit 80. The control unit 70 acquires the gain (det_gain) and offset (det_offs), and adjusts the multiplication unit 62 and the addition unit 63 to achieve the acquired gain (det_gain) and offset (det_offs). The gain (det_gain) and offset (det_offs) are set to eliminate differences in circuit characteristics between the detection circuit 40 and the pseudo detection circuit 50 and differences not anticipated in the design, so that the detection signal Sr and the pseudo detection signal Sp have substantially the same magnitude and characteristics.

[0058] The detection signal Sr and the pseudo detection signal Sp corrected by the gain (det_gain) and offset (det_offs) are input to a change rate determination unit 61. The change rate determination unit 61 calculates a flag ef_del for performing fault detection based on the change in the detection signal Sr and the change in the corrected pseudo detection signal Sp. The calculation method of the flag ef_del will be described later, but the flag ef_del is a flag that is off when the change in the detection signal Sr matches the change in the corrected pseudo detection signal Sp, and is on when they do not match.

[0059] The pseudo detection circuit 50 is a replica of the detection circuit 40. Therefore, if the detection circuit 40 and the pseudo detection circuit 50 are operating normally, the detection signal Sr and the corrected pseudo detection signal Sp should have qualitatively the same characteristics. Therefore, if the detection circuit 40 and the pseudo detection circuit 50 are operating normally, it is presumed that the change characteristics of the detection signal Sr and the pseudo detection signal Sp match. Therefore, in this embodiment, if the change in the detection signal Sr does not match the change in the corrected pseudo detection signal Sp, the change rate determination unit 61 sets the flag ef_del to ON, indicating the possibility of a malfunction.

[0060] The detection signal Sr and the corrected pseudo detection signal Sp are input to a value determination unit 64. The value determination unit 64 obtains the difference between the value of the detection signal Sr and the value of the corrected pseudo detection signal Sp, and calculates a flag ef_val for performing fault detection based on the difference. A method for calculating the flag ef_val will be described later, but the flag ef_val is a flag that obtains the difference between the value of the detection signal Sr and the value of the corrected pseudo detection signal Sp, and is OFF when the difference is equal to or smaller than a threshold, and is ON when the difference is larger than the threshold.

[0061] In this embodiment, a state in which the pseudo detection circuit 50 is broken is not assumed, and the pseudo detection signal Sp is corrected so that the detection signal Sr and the pseudo detection signal Sp have substantially the same magnitude and characteristics. Therefore, if the detection circuit 40 is not broken, it is presumed that the value of the detection signal Sr and the value of the pseudo detection signal Sp are substantially the same. In other words, if the value of the detection signal Sr and the value of the corrected pseudo detection signal Sp do not match, the value determination unit 64 sets the flag ef_val to ON, indicating the possibility of a failure.

[0062] The failure determination unit 65 determines whether or not the detection circuit 40 is faulty based on the flag ef_del set by the rate of change determination unit 61 and the flag ef_val set by the value determination unit 64. Specifically, when the flags ef_del and ef_val are both on (1), the failure detection circuit 60 determines that the detection circuit 40 is faulty. When at least one of the flags ef_del and ef_val is off (0), the failure detection circuit 60 determines that the detection circuit 40 is normal. Thus, in this embodiment, when the possibility of a failure is indicated by both the flags ef_del and ef_val, which indicate the possibility of a failure, a failure is detected. As a result, it is possible to reduce the possibility of erroneously determining that a failure exists, as compared with a configuration in which a failure is detected using only one of the flags.

[0063] FIG. 7 is a diagram showing a configuration example of the value determination unit 64. In the configuration example shown in FIG. 7, the value determination unit 64 includes a selector 64a, adders 64b and 64f, absolute value output units (ABS) 64c and 64d, a multiplier 64e, and a comparator 64g. The selector 64a receives the detection signal Sr and the corrected pseudo detection signal Sp, and performs a process of switching between a state in which the input signal is output and a state in which the input signal is not output. Specifically, when the signal clip_flg input from the clip processing unit 55 is active (high level in this embodiment), that is, when the input signal to the clip processing unit 55 exceeds a predetermined value, the selector 64a does not output the input signal to the selector 64a. In this case, the failure detection circuit 60 does not perform failure detection. As a result, the value determination in the value determination unit 64 is invalidated.

[0064] On the other hand, when the signal clip_flg input from the clip processing unit 55 is inactive (low level in this embodiment), that is, when the input signal to the clip processing unit 55 does not exceed the predetermined value, the selector 64a is set to a state in which the input signal to the selector 64a is output. As a result, the value determination in the value determination unit 64 is enabled.

[0065] The adder 64b adds the detection signal Sr output from the selector 64a and a signal obtained by multiplying the corrected pseudo detection signal Sp by a negative sign. That is, the adder 64b calculates the difference between the value of the detection signal Sr and the value of the corrected pseudo detection signal Sp. The addition result output by the adder 64b is input to the absolute value output unit 64c, which outputs the absolute value of the addition result. That is, an error signal error indicating the magnitude of the difference between the value of the detection signal Sr and the value of the corrected pseudo detection signal Sp is output.

[0066] The corrected pseudo detection signal Sp output from the selector 64a is also input to the absolute value output unit 64d. The absolute value output unit 64d outputs a signal indicating the absolute value of the corrected pseudo detection signal Sp, i.e., the magnitude. This signal is multiplied by a gain (Vth_gain) by the multiplication unit 64e, and an offset (Vth_offs) is added by the addition unit 64f. The gain (Vth_gain) and offset (Vth_offs) are determined in advance and stored in the register unit 80. The control unit 70 acquires the gain (Vth_gain) and offset (Vth_offs), and adjusts the multiplication unit 62 and the addition unit 63 to obtain the acquired gain (Vth_gain) and offset (Vth_offs).

[0067] The value output from the adder 64f becomes a threshold value Vth to be compared with the error signal error. The threshold value Vth is a value for determining whether the error signal error is substantially 0, that is, whether there is no difference between the detection signal Sr and the corrected pseudo detection signal Sp. Even if the detection signal Sr and the corrected pseudo detection signal Sp are substantially the same value, the difference is not necessarily strictly 0 depending on the error of the circuit elements, etc., so the threshold value Vth is set as a value within a range in which the difference can be considered to be 0.

[0068] Furthermore, the range in which the difference between the detection signal Sr and the corrected pseudo detection signal Sp can be considered to be substantially 0 is wider as the magnitude of each signal increases. This is because the noise increases as the magnitude of each signal increases. Therefore, in this embodiment, the threshold value is configured to change according to the magnitude of the signal output from the sensor element, i.e., the pseudo detection signal Sp.

[0069] In this embodiment, the threshold value Vth is determined by a linear equation with the pseudo detection signal Sp as a variable. Specifically, the threshold value Vth is obtained by (absolute value of the pseudo detection signal Sp)×(Vth_gain)+(Vth_offs). With this configuration, it is possible to set the threshold value to be larger as the magnitude of the pseudo detection signal Sp increases by simple processing. Note that this configuration is merely an example, and the threshold value Vth may be determined based on an equation other than the linear equation.

[0070] The comparison unit 64g compares the error signal error with a threshold value Vth, and if the error signal error is greater than the threshold value Vth, it determines that the value of the detection signal Sr does not match the value of the corrected pseudo detection signal Sp, and sets the flag ef_val to ON. If it is not determined that the error signal error is greater than the threshold value Vth, the comparison unit 64g sets the flag ef_val to OFF. The flag set by the comparison unit 64g is input to the failure determination unit 65.

[0071] FIG. 8 is a diagram showing a configuration example of the change rate determination unit 61. In the configuration example shown in FIG. 8, the change rate determination unit 61 includes differentiators 61a and 61b, a sign comparison unit 61c, and a change determination unit 61d. The differentiator 61a includes an adder 61a1 and a delay unit 61a2. The detection signal Sr is input to the differentiator 61a. In the differentiator 61a, the detection signal Sr and a signal obtained by delaying the output of the adder 61a1 by the delay unit 61a2 and adding a negative sign to the delayed signal are input to the adder 61a1. As a result, a signal obtained by time-differentiating the detection signal Sr, i.e., a signal del1 indicating the change rate of the detection signal Sr, is output.

[0072] The differentiator 61b includes an adder 61b1 and a delay unit 61b2. This configuration is similar to that of the differentiator 61a. The differentiator 61b receives the pseudo detection signal Sp and outputs a signal obtained by time-differentiating the pseudo detection signal Sp, i.e., a signal del2 indicating the rate of change of the pseudo detection signal Sp.

[0073] The signals del1 and del2 are input to the sign comparison unit 61c. The sign comparison unit 61c compares the signs of the signals del1 and del2. That is, the sign comparison unit 61c determines whether the signs of the signals del1 and del2 are positive or negative, and determines whether the two match. The sign comparison unit 61c sets the flag ef_del to ON when the signs of the signals del1 and del2 do not match. When the signs of the signals del1 and del2 match, the sign comparison unit 61c sets the flag ef_del to OFF. The flag set by the sign comparison unit 61c is input to the fault determination unit 65.

[0074] When the signs of the signals del1 and del2 do not match, the change trends of the detection signal Sr and the corrected pseudo detection signal Sp are opposite, so that the characteristics of the detection signal Sr and the corrected pseudo detection signal Sp can be considered to be different. Therefore, in this embodiment, when the signs of the signals del1 and del2 do not match, a flag ef_val is set to ON as there is a possibility of a malfunction.

[0075] 6 determines that there is a malfunction when the flag ef_del set based on the difference in values ​​and the flag ef_val set based on the rate of change are both on (1). On the other hand, the malfunction determination unit 65 determines that there is a malfunction when at least one of the flags ef_del and ef_val is off (0). That is, when the difference between the value of the detection signal Sr and the value of the corrected pseudo detection signal Sp is greater than the threshold value and the sign of the change in the detection signal Sr is different from the sign of the change in the corrected pseudo detection signal Sp, a malfunction is determined.

[0076] When the difference between the value of the detection signal Sr and the value of the corrected pseudo detection signal Sp is greater than the threshold value, the value of the detection signal Sr and the value of the corrected pseudo detection signal Sp are not substantially the same, so there is a possibility of a malfunction. Furthermore, when the sign of the change in the detection signal Sr is different from the sign of the change in the corrected pseudo detection signal Sp, the change characteristics of the detection signal Sr and the change characteristics of the corrected pseudo detection signal Sp are different, so there is a possibility of a malfunction. In this embodiment, when both conditions for determining that there is a possibility of a malfunction are satisfied, it is determined that there is a malfunction. As a result, it is possible to reduce the possibility of erroneously determining that there is a malfunction, compared to a configuration in which a malfunction is determined using only one of the conditions.

[0077] In this embodiment, the sign of the signal change is not taken into consideration when the accuracy of the determination based on the sign of the signal change is relatively low and the accuracy of the determination based on the value difference is relatively high. For example, a case will be described in which the detection signal Sr and the pseudo detection signal Sp have a sine wave shape as shown in Fig. 9. In such a signal, the sign of the signal change changes to +, 0, - near the maximum amplitude. Fig. 9 shows times T1, T2, and T3 where the signs are +, 0, and -.

[0078] On the other hand, when the phase changes by 90° from near the maximum amplitude and reaches near the 0 crossing point of the amplitude, the signal decreases monotonically and the sign does not change for a while. FIG. 9 shows that the sign is negative at times T4, T5, and T6 near the 0 crossing point. In the period from time T1 to T3 near the maximum amplitude, the change Δ1 in the signal value is small, but in the period from time T4 to T6 near the 0 crossing point of the amplitude, the change Δ2 in the signal value is relatively large. In this way, in the vicinity of the maximum amplitude, the sign of the signal change fluctuates greatly due to a small signal change, but in a phase region different from the phase near the maximum amplitude, the sign of the signal change is unlikely to change even if the signal changes slightly.

[0079] For this reason, the accuracy of fault detection based on the sign of the signal change is relatively low near the maximum amplitude. In particular, the higher the signal frequency, the lower the accuracy of fault detection. On the other hand, when both the detection signal Sr and the corrected pseudo detection signal Sp are near the maximum amplitude, if the signals are normal, the difference in the signal values ​​is small and the possibility of the difference exceeding the threshold is low. Therefore, even if the sign of the signal change is not used near the maximum amplitude and a fault is determined based on the difference in values, the accuracy of fault detection is unlikely to be low. This situation is not limited to sine waves, but is similar for any signal.

[0080] Therefore, in the change rate determination unit 61, the signal del2 is input to a change determination unit 61d. The change determination unit 61d determines whether or not the change in the signal del2 is substantially 0. In this embodiment, it is determined whether or not the change in the signal del2 is substantially 0 based on a second threshold del_Vth. That is, the second threshold del_Vth indicates the magnitude at which the change in the signal del2 is regarded as 0, and is set in advance. In this embodiment, the second threshold del_Vth is a predetermined fixed value, but may be variable depending on the magnitude of the signal del2, etc.

[0081] Then, when the magnitude of the change in the signal del2 is equal to or less than the second threshold del_Vth, the change in the signal del2 is considered to be substantially 0. When the change in the signal del2 is substantially 0, the change determination unit 61d sets the flag ef_del to ON. In this case, the determination in the sign comparison unit 61c is not reflected in the flag. In this embodiment, the failure determination unit 65 is configured to determine that a failure has occurred when both the flags ef_del and ef_val are ON (1). Therefore, when the flag ef_del is set to ON, the state is such that the failure or not is determined based on whether the flag ef_val is ON or not, regardless of the determination in the sign comparison unit 61c. According to the above configuration, when the magnitude of the change in the corrected pseudo detection signal Sp is equal to or less than the second threshold del_Vth, the failure detection is performed based on the comparison result between the value of the detection signal Sr and the value of the pseudo detection signal Sp, regardless of the change in the detection signal Sr and the change in the pseudo detection signal Sp. According to the above configuration, under conditions where the failure detection accuracy may be low, the determination based on the sign of the signal change is not performed. This makes it possible to prevent a decrease in the accuracy of failure detection.

[0082] 2. Other embodiments The above-described embodiment is an example for carrying out the present invention, and various other embodiments can be adopted. For example, in the above-described embodiment, when the input signal to the clip processing unit 55 exceeds a predetermined value, the input signal to the selector 64a is not output from the selector 64a, and the fault detection is disabled. However, when the input signal to the clip processing unit 55 exceeds a predetermined value, the input signal to the selector 64a may be output from the selector 64a. In this case, the detection signal Sr and the pseudo detection signal Sp generated based on the clipped signal are output from the selector 64a, but these values ​​are fixed by the clip. Therefore, if these fixed values ​​are set to be the same value, the change in the pseudo detection signal Sp is 0, there is no difference between the value of the detection signal Sr and the value of the pseudo detection signal Sp, and it is normal. Therefore, the state in which no fault is detected, that is, the fault detection is disabled.

[0083] Furthermore, when the value determination is invalidated by the selector 64a, the data immediately after switching by the selector 64a may not be used for the value determination.

[0084] The detection circuit includes a first A / D conversion circuit that performs A / D conversion on a signal output from a sensor element and outputs a first digital signal, and generates a detection signal based on the first digital signal. That is, the detection circuit may perform analog / digital conversion on a detection result by the sensor element to generate a digital detection signal. Such a configuration is not limited to the above-mentioned embodiment, and various alternative means may be used, and various functions may be omitted or added. For example, the number of bits of the first A / D conversion circuit is not limited to the above-mentioned configuration, and the order of the detection circuit and the PGA may be reversed. In addition, a downsampling filter may be applied to the output of the first A / D conversion circuit, and gain adjustment and offset adjustment may be performed. Furthermore, various processes, such as gain adjustment and offset adjustment, may be performed on the signal before it is input to the first A / D conversion circuit.

[0085] The sensor element may detect various detection targets, such as physical quantities. The physical quantities are not limited to the angular velocity as described above, and may be acceleration, angular acceleration, velocity, distance, temperature, pressure, sound pressure, magnetic quantity, etc. Of course, two or more of these physical quantities may be detected. The configuration of the detection circuit 40 or the pseudo detection circuit 50 may be changed depending on the physical quantity of the detection target. For example, when a sensor element that outputs a signal that does not require differential amplification is used, a configuration that does not include a differential amplifier circuit may be adopted. Note that the "signal output from the sensor element" may also include a signal that has been subjected to various processes on the output signal of the sensor element.

[0086] The detection signal is a signal indicating an object to be detected by the sensor element, and may be generated based on the first digital signal. In other words, the first digital signal is a signal indicating a result obtained by the sensor element, and the detection signal is a signal that expresses the detection result by the sensor element in a format that can be used by another device. The first digital signal and the detection signal may be the same signal.

[0087] The pseudo detection circuit includes a second A / D conversion circuit that performs A / D conversion on a signal output from the sensor element and outputs a second digital signal, and can generate a pseudo detection signal based on the second digital signal. That is, the pseudo detection circuit can perform analog / digital conversion on the detection result by the sensor element to generate a digital pseudo detection signal. Such a configuration is not limited to the above-mentioned embodiment, and various alternative means may be used, and various functions may be omitted or added. For example, the number of bits of the second A / D conversion circuit is not limited to the above-mentioned configuration, and the order of the detection circuit and the PGA may be reversed. In addition, a downsampling filter may be applied to the output of the second A / D conversion circuit, and gain adjustment and offset adjustment may be performed. Furthermore, various processes, such as gain adjustment and offset adjustment, may be performed on the signal before it is input to the second A / D conversion circuit.

[0088] The pseudo detection signal is a signal indicating the object to be detected by the sensor element, and is generated based on the second digital signal, and is a signal that reproduces the detection signal in a pseudo manner. Since the pseudo detection signal is a signal that reproduces the detection signal in a pseudo manner, the pseudo detection signal does not have to be used for detecting a physical quantity or the like by the sensor element. In addition, the circuit for generating the pseudo detection signal by pseudo-reproducing the detection signal may be the same as the detection circuit, may be a circuit that is at least partially identical, or may be a circuit that has the same circuit function but different specifications. Here, the circuit function being the same corresponds to a circuit whose transfer function has the same properties but different coefficients and constants. In any case, the pseudo detection circuit may be designed so that a difference occurs between the pseudo detection signal and the detection signal when the detection circuit is faulty by reproducing the behavior of the detection signal by the pseudo detection signal. The second digital signal and the pseudo detection signal may be the same signal.

[0089] The fault detection circuit may detect a fault in the detection circuit based on a comparison result of the value of the detection signal and the value of the pseudo detection signal. That is, the fault detection circuit may compare the value of the detection signal generated by the detection circuit with the value of the pseudo detection signal generated by a pseudo detection circuit simulating the detection circuit, and determine whether the detection circuit is normal or not based on the difference. The difference between the value of the detection signal and the value of the pseudo detection signal may be evaluated by various methods. For example, the fault detection is performed based on the difference and change between the value of the detection signal and the value of the pseudo detection signal described above, but the fault detection may be performed based on either the difference or the change. In addition, other factors may be added to the evaluation factors of the difference. In addition, various processes other than clipping may be performed to determine the value of the detection signal and the value of the pseudo detection signal.

[0090] The above-described embodiments are merely examples, and the present invention is not limited to these. The present invention includes configurations that are substantially the same as those described in the embodiments (for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effect). The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments, or configurations that can achieve the same purpose. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments. [Explanation of symbols]

[0091] 1...physical quantity sensor, 7...claim, 10...sensor element, 20...drive circuit, 21...current-voltage converter, 22...gain control circuit, 23...comparator, 24...comparator, 30...amplifier circuit, 40...detection circuit, 42...first synchronous detection circuit, 43...first low-pass filter, 44...first A / D conversion circuit, 45...clip processing unit, 46...IIR filter, 50...pseudo detection circuit, 52...second synchronous detection circuit, 53...second low-pass filter, 54...second A / D conversion circuit, 55...clip processing unit, 56...IIR filter, 60...fault detection circuit, 61... Rate of change determination section, 61a...differentiator, 61a1...adder, 61a2...delay section, 61b...differentiator, 61b1...adder, 61b2...delay section, 61c...sign comparison section, 61d...change determination section, 62...multiplication section, 63...addition section, 64...value determination section, 64a...selector, 64b...addition section, 64c...absolute value output section, 64d...absolute value output section, 64e...multiplication section, 64f...addition section, 64g...comparison section, 65...fault determination section, 70...control section, 80...register section, 90...temperature sensor, PD1...pad, PD2...pad, PD3...pad, PD4...pad, SW1 to SW4...switches

Claims

1. a detection circuit including a first A / D conversion circuit that performs A / D conversion on a signal output from the sensor element to output a first digital signal, and that generates a detection signal based on the first digital signal; a pseudo detection circuit including a second A / D conversion circuit that performs A / D conversion on a signal output from the sensor element to output a second digital signal, and that generates a pseudo detection signal based on the second digital signal; a fault detection circuit for detecting a fault in the detection circuit based on a comparison result of a comparison between a value of the detection signal and a value of the pseudo detection signal; A circuit device comprising:

2. the fault detection circuit detects the fault based on whether a difference between a value of the detection signal and a value of the pseudo detection signal is equal to or smaller than a threshold value; The threshold value varies depending on the signal output from the sensor element. The circuit device according to claim 1 .

3. The threshold value is determined by a linear expression using the pseudo detection signal as a variable. The circuit device according to claim 2 .

4. A drive circuit for generating a drive signal for driving the sensor element is further provided. the detection circuit includes a first synchronous detection circuit that synchronously detects a signal output from the sensor element using a synchronous detection signal based on the drive signal, and a first low-pass filter that smoothes the signal output from the first synchronous detection circuit; the first A / D conversion circuit performs A / D conversion on the signal output from the first low-pass filter; the pseudo detection circuit includes a second synchronous detection circuit that synchronously detects the signal output from the sensor element using the synchronous detection signal, and a second low-pass filter that smoothes the signal output from the second synchronous detection circuit, The second A / D conversion circuit performs A / D conversion on the signal output from the second low-pass filter. The circuit device according to claim 1 .

5. The resolution of the second A / D conversion circuit is lower than the resolution of the first A / D conversion circuit. The circuit device according to claim 1 .

6. the detection circuit performs a temperature compensation process on the detection signal based on a temperature detection signal; the second A / D conversion circuit performs A / D conversion for generating the pseudo detection signal and A / D conversion for generating the temperature detection signal in a time-division manner. The circuit device according to claim 1 .

7. an input range of the second A / D conversion circuit is smaller than an input range of the first A / D conversion circuit; when the magnitude of the output signal from the second A / D conversion circuit exceeds a predetermined value, the detection signal and the pseudo detection signal are set to fixed values; The circuit device according to claim 1 .

8. The fault detection circuit includes: detecting a fault based on the comparison result, the change in the detection signal, and the change in the pseudo detection signal; The circuit device according to claim 1 .

9. The fault detection circuit includes: determining that a malfunction has occurred when the comparison result indicates that the difference between the value of the detection signal and the value of the pseudo detection signal is greater than a threshold value and the sign of the change in the detection signal is different from the sign of the change in the pseudo detection signal; when the change in the pseudo detection signal is equal to or smaller than a second threshold, detecting a fault based on a result of the comparison, regardless of the change in the detection signal and the change in the pseudo detection signal. The circuit arrangement according to claim 8.

10. A sensor element; a detection circuit including a first A / D conversion circuit that performs A / D conversion on a signal output from the sensor element to output a first digital signal, and that generates a detection signal based on the first digital signal; a pseudo detection circuit including a second A / D conversion circuit that performs A / D conversion on a signal output from the sensor element to output a second digital signal, and that generates a pseudo detection signal based on the second digital signal; a fault detection circuit for detecting a fault in the detection circuit based on a comparison result of a comparison between a value of the detection signal and a value of the pseudo detection signal; A physical quantity sensor comprising:

11. Further comprising a drive circuit for driving the sensor element, The signal output from the sensor element corresponds to the angular velocity detected by the sensor element. The physical quantity sensor according to claim 10.

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