Buffer circuit

Abstract

To provide a technology for improving the responsiveness of a buffer circuit while suppressing power consumption in the buffer circuit.SOLUTION: A switch 524 connects a driver circuit 521 with an operational amplifier 522 during a sampling phase when no charge is transferred from a buffer circuit 52 to a CDAC 10. The switch 524 also disconnects the driver circuit 521 from the operational amplifier 522 during an SAR phase when charge is transferred from the buffer circuit 52 to the CDAC 10. The capacitor 525 maintains output voltage of the operational amplifier 522 immediately before it is disconnected by the switch 524 during the SAR phase.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a buffer circuit used to supply a reference voltage. [Background technology]

[0002] Patent Document 1 describes a technique for supplying a reference voltage generated by a reference voltage circuit through a buffer circuit that combines an operational amplifier and a driver circuit. Specifically, the buffer circuit applies a reference voltage to the non-inverting input of the operational amplifier, applies the output voltage of the driver circuit to the inverting input of the operational amplifier, and drives the driver circuit with the output of the operational amplifier, thereby matching the output of the driver circuit with the reference voltage. A source follower circuit is shown as the driver circuit. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2001-147726 A Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, in the buffer circuit of the conventional technology described above, the output of the driver circuit is fed back to the operational amplifier, so even if the driver circuit alone has high speed performance, the operating speed of the buffer circuit as a whole is limited by the operating speed of the operational amplifier.

[0005] For example, in a successive approximation A / D conversion circuit, a reference voltage is repeatedly applied to multiple capacitors that make up a charge redistribution type capacitive D / A converter (hereafter, CDAC) at high speed. In order to increase the speed of a buffer circuit used for such purposes, it is necessary to use an operational amplifier with a high operating speed, but this poses the problem of increasing the power consumption of the operational amplifier and, ultimately, the entire buffer circuit.

[0006] The present disclosure provides a technique for improving the responsiveness of a buffer circuit while suppressing power consumption in the buffer circuit. [Means for solving the problem]

[0007] One aspect of the present disclosure is a buffer circuit, which is connected to an output terminal of a reference voltage source that supplies a constant voltage to a load circuit in which a first operation phase and a second operation phase are alternately executed. The buffer circuit includes a driver circuit, an operational amplifier, a disconnection switch, and a level holding circuit. The driver circuit is configured to increase a current driving capability. The operational amplifier is configured to drive the driver circuit so that an output voltage of the driver circuit is proportional to an output voltage of the reference voltage source. The disconnection switch is configured to connect the driver circuit and the operational amplifier during a first operation phase in which no charge transfer occurs from the buffer circuit to the load circuit. The disconnection switch is configured to disconnect the driver circuit and the operational amplifier during a second operation phase in which charge transfer occurs from the buffer circuit to the load circuit. The level holding circuit is connected to an input terminal of the driver circuit, and is configured to hold an output voltage of the operational amplifier immediately before being disconnected by the disconnection switch during the second operation phase.

[0008] According to such a configuration, it is possible to use an operational amplifier that is slower than the driver circuit, so that it is possible to improve the response of the buffer circuit while suppressing power consumption in the buffer circuit. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is an overall configuration diagram of a sequential drive type A / D conversion circuit. [Diagram 2] FIG. 4 is a timing diagram showing the operation of the CDAC and buffer circuit. [Diagram 3] 1 is a circuit diagram illustrating a configuration of a reference voltage circuit according to a first embodiment. [Figure 4] 1 is a graph showing characteristics of a buffer circuit. [Diagram 5]FIG. 11 is a circuit diagram illustrating a configuration of a reference voltage circuit according to a second embodiment. [Figure 6] 11 is a table showing the results of a simulation of the difference in reference voltage Vref depending on whether or not an auto-zero function is present; [Figure 7] 11 is a graph showing the results of a simulation of the difference in noise depending on whether or not an auto-zero function is present. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. [1. First embodiment] [1-1. Configuration] A sequential acquisition type A / D conversion circuit (hereinafter, referred to as SAR-ADC) 1 to which the buffer circuit 52 of this embodiment is applied will be described.

[0011] As shown in FIG. 1, the SAR-ADC 1 performs AD conversion on the voltage level of an analog input signal AVin input from an input terminal 2, and outputs a digital output signal Dout, which is the result of the AD conversion, from an output terminal 3.

[0012] The SAR-ADC 1 includes a CDAC 10, a comparator 30, a SAR logic circuit 40, and a reference voltage circuit 50. CDAC 10 includes a plurality of binary-weighted capacitors 11-14 and a dummy capacitor 15. Specifically, with C as the unit capacitance, the capacitance of capacitor 11 is set to 8C, the capacitance of capacitor 12 is set to 4C, the capacitance of capacitor 13 is set to 2C, and the capacitances of capacitor 14 and dummy capacitor 15 are set to C. Capacitors 11-14 are associated with each bit of a 4-bit digital value such that capacitor 11 is the most significant bit (hereinafter, MSB) and capacitor 14 is the least significant bit (hereinafter, LSB).

[0013] Here, the case where CDAC10 has four capacitors 11 to 14 excluding dummy capacitor 15 in order to perform 4-bit D / A conversion has been shown, but the number of capacitors provided in CDAC10 is not limited to this. CDAC10 only needs to have a number of capacitors corresponding to the number of bits of the digital value (i.e., the digital output signal Dout) after A / D conversion by SAR-ADC1.

[0014] One end of each of the capacitors 11 to 14 and the dummy capacitor 15 is connected to a signal line 16. The signal line 16 is connected to ground via a switch 26 controlled by a control signal S1. The other ends of each of the capacitors 11 to 14 and the dummy capacitor 15 are connected to a signal line 17 or ground via switches 21 to 25 controlled by control signals S21 to S25, respectively.

[0015] The signal line 17 is connected to the input terminal 2 or the reference voltage circuit 50 via a switch 27 controlled by a control signal S3. The reference voltage circuit 50 is a circuit that supplies a reference voltage Vref. That is, either the analog input voltage VAin or the reference voltage Vref is supplied to the signal line 17 in accordance with the setting of the switch 27.

[0016] The comparator 30 compares the potential VL of the signal line 16 with the ground potential to determine which is larger, and outputs a logical value of 0 if VL is a positive potential, and a logical value of 1 if VL is a negative potential. The SAR logic circuit 40 includes a successive approximation register used to store intermediate results of A / D conversion and to control the switches 21-24 of the CDAC 10. The SAR logic circuit 40 generates control signals S1, S21-S25, and S3 for operating the switches 21-27 according to a clock signal CLK input from the outside, the output of the comparator 30, and the value of the successive approximation register, and executes a successive approximation process. In the successive approximation process, the value of the successive approximation register is determined bit by bit from the MSB to the least significant bit LSB according to the output of the comparator 30 obtained by operating the CDAC 10 according to the control signals S1, S21-S25, and S3. The SAR logic circuit 40 also outputs the value of the successive approximation register determined by the successive approximation process from the output terminal 3 as a digital output value Dout.

[0017] 2, the SAR logic circuit 40 is configured to alternate between two operation phases, a sampling phase and a SAR phase. In this embodiment, the period when the clock signal CLK is at a high level is the sampling phase, and the period when the clock signal CLK is at a low level is the SAR phase.

[0018] In the sampling phase, the SAR logic circuit 40 first operates the control signals S1, S21 to S25, and S3 to turn on the switch 26, set the switches 21 to 25 to the signal line 17 side, and set the switch 27 to the input terminal 2 side. This causes the capacitors 11 to 14 and the dummy capacitor 15 to hold a sampled value of the analog input voltage AVin to be subjected to AD conversion.

[0019] In addition, in the sampling phase, the SAR logic circuit 40 takes in the analog input voltage AVin, and then operates the control signals S1, S21 to S25 to turn off the switch 26 and set the switches 21 to 25 to the ground side. This causes the signal line 16 to be disconnected from the ground, and the potential VL of the signal line 16 becomes VL=-AVin.

[0020] In the following SAR phase, the SAR logic circuit 40 operates according to a binary search algorithm. Specifically, the SAR logic circuit 40 first initializes the successive approximation register. In the initialized successive approximation register, the MSB is set to 1, and bits other than the MSB are set to 0. The bit set to 1 is set as the determination target bit.

[0021] Next, the SAR logic circuit 40 operates the control signal S3 to set the switch 27 so that the reference voltage Vref is applied to the signal line 17. At the same time, the SAR logic circuit 40 operates the control signals S21-S24 to set the switches 21-24 so that the capacitors 11-14 corresponding to the bits in the successive approximation register that are set to 1 are connected to the signal line 17.

[0022] As a result, the potential VL of the signal line 16 becomes equal to the analog input voltage -AVin held in the capacitors 11 to 14 plus the D / A converted value set in the successive approximation register. The potential VL of the signal line 16 is compared with the ground level by the comparator 30, and a logical value according to the comparison result is generated. Specifically, when the D / A converted value is greater than the analog input voltage AVin and the potential VL is positive, a logical value of 0 is generated. When the D / A converted value is less than the analog input voltage AVin and the potential VL is negative, a logical value of 1 is generated.

[0023] The SAR logic circuit 40 updates the successive approximation register according to the logical value generated by the comparator 30. Specifically, the value of the bit to be determined in the successive approximation register is determined by the logical value generated, and the value of the bit representing the next digit of the determined bit is set to 1, and this newly set to 1 bit becomes the new bit to be determined.

[0024] Thereafter, by manipulating the control signals S21 to S24 in accordance with the setting value of the successive approximation register, a logical value representing the comparison result between the analog input voltage AVin and the D / A conversion value set in the successive approximation register is generated, and the setting value of the successive approximation register is updated in accordance with the generated logical value, and the process is repeated.

[0025] When the LSB value of the successive approximation register is determined by the above-mentioned repetitive process, the SAR logic circuit 40 stops the repetitive process, outputs the determined value of the successive approximation register as the digital output signal Dout, and ends the SAR phase.

[0026] That is, in the SAR phase, charging and discharging of the capacitors 11 to 14 by the reference voltage Vref is repeated at high speed the same number of times as the number of bits of the successive approximation register.

[0027] When the SAR phase ends, the SAR logic circuit 40 transitions to the sampling phase and starts the processing in the sampling phase described above.

[0028] [1-2: Reference voltage circuit] Next, the reference voltage circuit 50 will be described. As shown in FIG. 3, the reference voltage circuit 50 includes a reference voltage source 51 and a buffer circuit 52.

[0029] The reference voltage source 51 generates a source voltage Vs that is a stable constant voltage regardless of fluctuations in the power supply voltage or temperature. The buffer circuit 52 is connected to the output terminal of the reference voltage source 51. The buffer circuit 52 is a circuit for preventing the reference voltage Vref supplied from the reference voltage circuit 50 from fluctuating due to the charging current that fluctuates in response to the operation of the CDAC 10.

[0030] That is, as described above, in the SAR phase, the application of the reference voltage Vref to the capacitors 11 to 14 is executed repeatedly at high speed. Also, the voltage accuracy of the reference voltage Vref applied to the capacitors 11 to 14 directly affects the conversion accuracy of the SAR-ADC 1. Therefore, the reference voltage circuit 50 is configured to supply the reference voltage Vref via the buffer circuit 52 so as to enable the charge required for charging the capacitors 11 to 14 to be supplied quickly and stably.

[0031] The buffer circuit 52 includes a driver circuit 521 , an operational amplifier 522 , a voltage divider circuit 523 , a switch 524 , and a capacitor 525 . The driver circuit 521 is a circuit that increases the current driving capability and enables high-speed operation, and for example, a source follower circuit is used.

[0032] The voltage dividing circuit 523 divides the output voltage (i.e., the reference voltage Vref) of the driver circuit 521 to generate a feedback voltage Vfb. The voltage dividing circuit 523 is composed of, for example, two resistors connected in series. In this case, if the resistance values ​​of the two resistors are R1 and R2, the feedback voltage Vfb is expressed by the following formula (1).

[0033] Vfb=Vref×R2 / (R1+R2) (1) In the operational amplifier 522, the source voltage Vs from the reference voltage source 51 is applied to the non-inverting input, and the feedback voltage Vfb from the voltage divider circuit 523 is applied to the inverting input.

[0034] The switch 524 is provided in a signal path from the output of the operational amplifier 522 to the input of the driver circuit 521, and is operated by a control signal S4 from the SAR logic circuit 40. The control signal S4 has the same waveform as the clock signal CLK, as shown in Fig. 2. Therefore, the switch 524 is turned on during the sampling phase in which no charge is transferred from the reference voltage circuit 50 to the CDAC 10, and is turned off during the SAR phase in which charge is transferred from the reference voltage circuit 50 to the CDAC 10.

[0035] Capacitor 525 has one end grounded and an ungrounded end connected to the signal path from switch 524 to the input of driver circuit 521 . The buffer circuit 52 configured in this manner operates as follows. That is, in the sampling phase in which the switch 524 is turned on, the operational amplifier 522 drives the driver circuit 521 so that the feedback voltage Vfb coincides with the source voltage Vs. That is, the operational amplifier 522 operates so that the reference voltage Vref has a magnitude expressed by equation (2). Therefore, by appropriately changing the setting of the voltage division ratio in the voltage divider circuit 523, it is possible to generate a reference voltage Vref of any magnitude proportional to the source voltage Vs.

[0036] Vref = Vs × (1 + R1 / R2) (2) The voltage divider circuit 523 may be omitted in the buffer circuit 52. In this case, the output voltage of the driver circuit 521 (i.e., the reference voltage Vref) is applied as it is to the inverting input of the operational amplifier 522 as the feedback voltage Vbf, and the operational amplifier 522 operates so that Vref=Vs.

[0037] In the sampling phase, the driver circuit 521 and the operational amplifier 522 operate in a serially connected state, and therefore, as shown in Fig. 4, the operating speed of the buffer circuit 52 is limited by the slower operating speed of the operational amplifier 522. However, in the buffer circuit 52, an operation that makes the most of the stability of the operational amplifier 522 is realized.

[0038] Furthermore, in the sampling phase, the driver circuit 521 outputs an output voltage according to the charging voltage of the capacitor 525 as the reference voltage Vref. The capacitor 525 is charged in the sampling phase. During the SAR phase in which the switch 524 is turned off, the output voltage of the operational amplifier 522 immediately before the switch 524 is turned off (i.e., immediately before switching from the sampling phase to the SAR phase) is held in the capacitor 525.

[0039] In the SAR phase, the operational amplifier 522 is separated from the driver circuit 521, and the driver circuit 521 operates independently, so that the operating speed of the buffer circuit 52 is the same as that of the driver circuit 521, as shown in FIG. 4. Therefore, in the buffer circuit 52, an operation that makes use of the high speed of the driver circuit 521 is realized.

[0040] [1-3. Correspondence of terms] In this embodiment, the sampling phase corresponds to the first operation phase, and the SAR phase corresponds to the second operation phase. The switch 524 corresponds to a disconnection switch, the capacitor 525 corresponds to a level holding circuit, and the CDAC 10 corresponds to a load circuit.

[0041] [1-4. Effects] According to the first embodiment described above in detail, the following effects are achieved. (1a) In the sampling phase, the buffer circuit 52 performs feedback control to operate the driver circuit 521 and the operational amplifier 522 together. In the SAR phase, the buffer circuit 52 performs hold control to hold the output voltage of the operational amplifier 522, which is the input voltage of the driver circuit 521, in a capacitor 525, and to separate the operational amplifier 522 and operate the driver circuit 521 independently.

[0042] Therefore, the buffer circuit 52 can achieve the high speed required in the SAR phase by using the operational amplifier 522 that is slower (i.e., has a narrower frequency band) than the driver circuit 521. In other words, the buffer circuit 52 can improve responsiveness while suppressing power consumption.

[0043] [2. Second embodiment] [2-1. Differences from the first embodiment] The second embodiment has a basic configuration similar to that of the first embodiment, and therefore differences will be described below. Note that the same reference numerals as those in the first embodiment indicate the same configuration, and the preceding description will be referred to.

[0044] In the above-described first embodiment, in the SAR phase, the operational amplifier 522 is simply disconnected from the driver circuit 521. In contrast, the second embodiment differs from the first embodiment in that it is configured to execute auto-zero correction of the operational amplifier disconnected from the driver circuit 521 in the SAR phase.

[0045] [2-2. Reference voltage circuit] As shown in FIG. 5, a reference voltage circuit 50a of the second embodiment includes a reference voltage source 51 and a buffer circuit 52a.

[0046] The buffer circuit 52a includes an auto-zero amplifier 522a instead of the operational amplifier 522 in the configuration of the buffer circuit 52 in the first embodiment. The auto-zero amplifier 522a is an operational amplifier equipped with a zero adjustment terminal for adjusting the input offset voltage. When a voltage is applied to the zero adjustment terminal, the output of the auto-zero amplifier 522a shifts according to the applied voltage value. Such an auto-zero amplifier 522a is a publicly known technology described in, for example, Japanese Patent Application Laid-Open No. 2021-197680, and therefore a detailed description thereof will be omitted here.

[0047] The buffer circuit 52a further includes a capacitor 526 and switches 527-529. One end of the capacitor 526 is grounded, and the non-grounded end is connected via a switch 527 to a signal path connecting the output of the auto-zero amplifier 522a and the switch 524, and is also connected to a zero adjustment terminal of the auto-zero amplifier 522a. The switch 524 is operated by a control signal S5 from the SAR logic circuit 40. The control signal S5 is an inverted signal of the control signal S4.

[0048] A switch 528 is provided between the non-inverting and inverting inputs of the auto-zero amplifier 522a and is operated by a control signal S5. A switch 529 is provided in the signal path from voltage divider circuit 523 to the inverting input of auto-zero amplifier 522a and is operated by control signal S4.

[0049] [2-3. Operation] In the buffer circuit 52a configured in this manner, in the SAR phase, the switches 524 and 529 are turned off and the switches 527 and 528 are turned on. In this case, the auto-zero amplifier 522a is disconnected from the driver circuit 521. Furthermore, the non-inverting input and the inverting input of the auto-zero amplifier 522a are shorted via the switch 528, so that the output voltage corresponds to the offset voltage. The output voltage corresponding to the offset voltage is a voltage obtained by adding a correction voltage based on the holding voltage of the capacitor 526 to the offset voltage of the operational amplifier itself included in the auto-zero amplifier 522a. The output voltage corresponding to this offset voltage is held in the capacitor 526 via the switch 527.

[0050] In the buffer circuit 52a, in the sampling phase, the switches 524 and 529 are turned on and the switches 527 and 528 are turned off. In this case, the operation is basically the same as in the first embodiment. However, a correction voltage based on the holding voltage of the capacitor 526 is added to the output of the auto-zero amplifier 522a. The correction voltage acts to cancel the offset voltage included in the output voltage of the auto-zero amplifier 522a.

[0051] [2-4. Effects] According to the second embodiment described above in detail, in addition to the effect (1a) of the first embodiment described above, the following effect is also obtained.

[0052] (2a) In the SAR phase, the auto-zero amplifier 522a constituting the buffer circuit 52a holds a voltage corresponding to the offset voltage of the auto-zero amplifier 522a in the capacitor 526 every time the auto-zero amplifier 522a is disconnected from the driver circuit 521. Then, in the sampling phase, the auto-zero amplifier 522a uses the voltage held in the capacitor 526 to output an output voltage corrected to cancel the offset voltage.

[0053] Therefore, the buffer circuit 52a can suppress the offset voltage and flicker noise of the operational amplifier without making adjustments for each individual unit. Furthermore, the buffer circuit 52a can stably supply a highly accurate reference voltage Vref without stopping the operation of the SAR-ADC1 even if the offset voltage fluctuates due to the ambient temperature, aging, etc. As a result, it is possible to suppress the accuracy of the A / D conversion by the SAR-ADC1 from deteriorating due to the ambient temperature, aging, etc.

[0054] 6 shows the results of simulating the output voltage (i.e., reference voltage) Vref of the buffer circuit 52a depending on the presence or absence of a function for canceling the offset voltage by the auto-zero amplifier 522a (hereinafter, the auto-zero function) and the presence or absence of an offset voltage. However, the voltage divider circuit 523 was set so that Vs=1.0V and Vref=1.5V. As shown in FIG. 6, it can be seen that when there is no auto-zero function, the reference voltage Vref is affected by the offset voltage, and when there is the auto-zero function, the offset voltage is cancelled.

[0055] FIG. 7 shows the results of a simulation of the noise contained in the reference voltage Vref with and without the auto-zero function. However, the operational amplifier has a bandwidth of 10 MHz. As shown in FIG. 7, when the auto-zero function is present, the noise is significantly reduced below 10 kHz. Also, the average effective value of the noise in the range of 1 to 10 MHz is 139.2 μVrms without the auto-zero function, and 123.7 μVrms with the auto-zero function. In other words, the auto-zero function reduces noise by 15.5 μVrms.

[0056] 3. Other embodiments Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be implemented in various modified forms. (3a) In the above embodiment, the case has been described where the reference voltage Vref is supplied to the SAR-ADC1 via the buffer circuit 52, but the supply destination of the reference voltage Vref is not limited to the SAR-ADC1. The supply destination of the reference voltage Vref may be any circuit in which an operation phase requiring a high-speed response of the reference voltage Vref and an operation phase not requiring a high-speed response of the reference voltage Vref are alternately performed.

[0057] (3b) In addition to the above-described buffer circuit 52, the buffer circuit 52 may be realized as a system including the buffer circuit 52 as a component, a method for supplying a reference voltage, etc. [Explanation of symbols]

[0058] 51...reference voltage source, 52, 52a...buffer circuit, 521...driver circuit, 522...operational amplifier, 522a...auto-zero amplifier, 523...voltage divider circuit, 524, 527 to 529...switches, 525, 526...capacitors.

Claims

1. A buffer circuit connected to an output terminal of a reference voltage source that supplies a constant voltage to a load circuit in which a first operation phase and a second operation phase are alternately executed, A driver circuit configured to increase a current driving capability; an operational amplifier configured to drive the driver circuit such that an output voltage of the driver circuit is proportional to an output voltage of the reference voltage source; a disconnection switch configured to connect the driver circuit and the operational amplifier during the first operational phase in which no charge transfer occurs from the buffer circuit to the load circuit, and to disconnect the driver circuit and the operational amplifier during the second operational phase in which charge transfer occurs from the buffer circuit to the load circuit; a level holding circuit connected to an input terminal of the driver circuit and configured to hold the output voltage of the operational amplifier immediately before being disconnected by the disconnection switch during the second operating phase; A buffer circuit comprising:

2. 2. The buffer circuit of claim 1, the load circuit is a charge redistribution type capacitive D / A converter constituting a sequential drive type AD conversion circuit, the disconnection switch is configured to be switched on and off during a period in which the sequential drive type AD conversion circuit samples an input signal to be AD converted, the first operation phase being defined as a period in which the sequential drive type AD conversion circuit AD converts the input signal sampled in the first operation phase, the second operation phase being defined as a period in which the sequential drive type AD conversion circuit samples an input signal to be AD converted, Buffer circuit.

3. 2. The buffer circuit of claim 1, The operational amplifier has an auto-zero function that corrects the output voltage of the operational amplifier so as to cancel an offset voltage; configured to activate the autozero function during the second operational phase. Buffer circuit.

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