Thin film transistor substrate and display apparatus comprising the same

Abstract

SOLUTION: A thin film transistor substrate 100 including a thin film transistor on a substrate, includes an active layer 130, a conductive material layer on the active layer, and a gate electrode 150 spaced apart and partially overlapping the active layer. The active layer includes a channel area 130n partially overlapping the gate electrode in the plane, and a source area 160 and a drain area 170 connected to one side and the other side of the channel area in the plane. The conductive material layer includes a first conductive material layer 165 on the source area and a second conductive material layer 175 on the drain area. The second conductive material layer overlaps at least a portion of the channel area, and an active hole 135 in which the active layer is absent is arranged within an area defined by the active layer. The active hole protrudes in the direction of the drain area from the gate electrode in the plane.EFFECT: Exposure to hydrogen and light for a channel is prevented or suppressed.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a thin film transistor substrate and a display device including the same. [Background technology]

[0002] Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, thin film transistors can be fabricated on glass or plastic substrates, and are therefore widely used as switching devices in display devices such as liquid crystal display devices and organic light emitting devices.

[0003] Based on the material constituting the active layer, thin film transistors can be classified into amorphous silicon thin film transistors in which amorphous silicon is used as the active layer, polycrystalline silicon thin film transistors in which polycrystalline silicon is used as the active layer, and oxide semiconductor thin film transistors in which oxide semiconductor is used as the active layer.

[0004] Amorphous silicon thin film transistors (a-SiTFTs) have the advantage of being able to form an active layer by depositing amorphous silicon in a short time, resulting in a short manufacturing process time and low production costs. However, they have the disadvantage of being limited in use in active matrix organic light emitting devices (AMOLEDs) due to their low mobility, poor current driving capability, and threshold voltage changes.

[0005] Polycrystalline silicon thin film transistors (poly-Si TFTs) are manufactured by depositing amorphous silicon and then crystallizing the amorphous silicon. The manufacturing process of polycrystalline silicon thin film transistors requires a process of crystallizing the amorphous silicon, which increases the number of processes and increases manufacturing costs, and since the crystallization process is performed at a high process temperature, it is difficult to apply polycrystalline silicon thin film transistors to large area devices. In addition, due to the characteristics of polycrystals, it is difficult to ensure the uniformity of polycrystalline silicon thin film transistors.

[0006] In oxide semiconductor thin film transistors, oxide constituting an active layer can be formed at a relatively low temperature, and the oxide has high mobility and a large resistance change depending on the oxygen content, so that desired physical properties can be easily obtained. In addition, oxide semiconductors are transparent due to the characteristics of oxides, so they are also advantageous for realizing transparent displays.

[0007] In the case of an oxide semiconductor thin film transistor, it may be vulnerable to exposure to light or hydrogen. In this case, a structure change is required to control the exposure to light or hydrogen. Therefore, a technique for controlling the exposure to light or hydrogen is being researched. Summary of the Invention [Problem to be solved by the invention]

[0008] SUMMARY OF THE DISCLOSURE One embodiment of the present invention provides a thin film transistor substrate that prevents or suppresses exposure to hydrogen and light by including active holes.

[0009] An embodiment of the present invention provides a thin film transistor substrate that includes active holes, thereby preventing or suppressing a threshold voltage (Vth) shift in the negative (-) direction even if a channel region has a large width.

[0010] SUMMARY OF THE DISCLOSURE One embodiment of the present invention seeks to provide a thin film transistor substrate that prevents or reduces exposure to hydrogen and light by including a conductive material layer overlying a channel region.

[0011] SUMMARY OF THE DISCLOSURE One embodiment of the present invention seeks to provide a thin film transistor substrate having improved reliability by including a conductive layer in which the active layer includes a pattern and overlaps the channel region.

[0012] SUMMARY OF THE DISCLOSURE One embodiment of the present invention provides a thin film transistor substrate that includes an active hole and a conductive layer overlapping a channel region, thereby ensuring optimization of the capacitor area.

[0013] Another embodiment of the present invention provides a display device including such a thin film transistor substrate. [Means for solving the problem]

[0014] In order to achieve the above technical object, one embodiment of the present invention provides a thin film transistor substrate comprising: a substrate; and a thin film transistor on the substrate, the thin film transistor comprising: an active layer; a conductive material layer on the active layer; and a gate electrode spaced from the active layer and partially overlapping the active layer, the active layer comprising: a channel region partially overlapping the gate electrode in a plane; a source region connected to one side of the channel region in the plane; and a drain region connected to the other side of the channel region in the plane, the conductive material layer comprising: a first conductive material layer on the source region and a second conductive material layer on the drain region, the first conductive material layer overlapping at least a portion of the channel region, the active layer comprising: an active hole within an area defined by the active layer where the active layer is not disposed; and the active hole extending from the channel region to the drain region in the plane.

[0015] A portion of the active hole may overlap the gate electrode in the plane.

[0016] The active hole may be spaced apart from the first conductive material layer in a plane.

[0017] The second layer of conductive material may be spaced apart in a plane from the channel region.

[0018] Each of the source region and the drain region is disposed between a base substrate and the first conductive material layer and the second conductive material layer, and each of the first conductive material layer and the second conductive material layer can be in contact with the active layer.

[0019] The gate electrode, the source electrode and the drain electrode may be disposed on the same layer, the gate electrode and the source electrode being spaced apart from each other and in contact with the source region and the drain region, respectively.

[0020] The active hole may include a plurality of sub-active holes that are spaced apart from one another, and each of the sub-active holes may have an elongated shape extending from the channel region to the drain region.

[0021] The conductive material layer may include at least one selected from titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodymium (Nd), calcium (Ca), barium (Ba), and a transparent conductive oxide (TCO).

[0022] A first length may be a shortest distance from the drain region to the first conductive material layer, and a second length may be a shortest length along a length of a channel in the active layer that the first conductive material layer overlaps with the gate electrode in the plane, the first length being longer than the second length.

[0023] A portion of the active hole may overlap with the gate electrode, and a shortest length that the active hole overlaps with the gate electrode in a length direction of a channel of the active layer may be a third length, and a shortest distance from the active hole to the first conductive material layer in a length direction of the channel of the active layer may be a fourth length, and the fourth length may be longer than the third length.

[0024] The thin film transistor may further include a light blocking layer on the substrate, and a storage capacitor in an overlapping region between the light blocking layer and the thin film transistor.

[0025] The storage capacitor includes a first storage capacitor including a first capacitor electrode coupled to the light blocking layer and a second capacitor electrode coupled to the active layer, the first capacitor electrode and the second capacitor electrode being spaced apart from each other and overlapping each other to form a first capacitor.

[0026] The first storage capacitor may include a third capacitor electrode coupled to the gate electrode, the second capacitor electrode and the third capacitor electrode being spaced apart from each other and overlapping each other to form a second capacitor.

[0027] The second capacitor electrode may include a first layer integral with one of the source region and the drain region, and a second layer integral with one of the first conductive material layer and the second conductive material layer.

[0028] The second capacitor electrode may be between the first capacitor electrode and the third capacitor electrode, and the third capacitor electrode may be connected to the first capacitor electrode.

[0029] The storage capacitor may include a second storage capacitor formed by overlapping the gate electrode and the first conductive material layer while being spaced apart from each other.

[0030] The storage capacitor may include a third storage capacitor formed by overlapping the gate electrode and the light blocking layer while being spaced apart from each other.

[0031] The third storage capacitor may be formed in a region overlapping with the active hole.

[0032] The active layer includes an oxide semiconductor material, and the oxide semiconductor material may include at least one of an IZO (InZnO)-based, an IGO (InGaO)-based, an ITO (InSnO)-based, an IGZO (InGaZnO)-based, an IGZTO (InGaZnSnO)-based, a GZTO (GaZnSnO)-based, a GZO (GaZnO)-based, an ITZO (InSnZnO)-based, and a FIZO (FeInZnO)-based oxide semiconductor material.

[0033] Another embodiment of the present invention provides a display device including the thin film transistor substrate. Effect of the Invention

[0034] The thin film transistor substrate according to an embodiment of the present invention includes active holes, thereby preventing or suppressing exposure of the channel to hydrogen and light.

[0035] The thin film transistor substrate according to an embodiment of the present invention includes active holes, thereby preventing or suppressing a threshold voltage (Vth) from shifting in the negative (-) direction.

[0036] A thin film transistor substrate according to an embodiment of the present invention includes a conductive layer overlapping a channel region, thereby preventing or suppressing exposure of the channel to hydrogen and light.

[0037] The thin film transistor substrate according to an embodiment of the present invention includes an active hole and a conductive layer overlapping a channel region, thereby providing safety and excellent reliability.

[0038] A thin film transistor substrate according to an embodiment of the present invention includes an active hole and a conductive layer overlapping a channel region, thereby ensuring optimization of the area of ​​a capacitor.

[0039] In addition to the above-mentioned effects, other features and advantages of the present invention can be described below, and can be clearly understood by those having ordinary skill in the art to which the present invention pertains from such descriptions and explanations. [Brief description of the drawings]

[0040] [Figure 1] 1 is a plan view of a thin film transistor substrate according to an embodiment of the present invention; [Diagram 2] 2 is a cross-sectional view taken along line II' in FIG. 1. [Diagram 3] 2 is a cross-sectional view taken along line II-II' in FIG. [Figure 4] 1 is a plan view of a thin film transistor substrate according to another embodiment of the present invention; [Diagram 5] 5 is a cross-sectional view taken along line II' in FIG. 4. [Figure 6] 5 is a cross-sectional view taken along line II-II' in FIG. 4. [Figure 7] 4 is a cross-sectional view of a thin film transistor substrate according to still another embodiment of the present invention; [Figure 8] 11 is a plan view of a thin film transistor substrate according to still another embodiment of the present invention; [Figure 9] FIG. 2 is a schematic diagram for explaining a capacitor of the present invention. [Figure 10] 2 is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention; FIG. [Figure 11] 4 is a cross-sectional view of a thin film transistor substrate according to a comparative example for explaining a capacitor of the present invention; FIG. [Figure 12A] 11 is a plan view of a thin film transistor substrate according to still another embodiment of the present invention; [Figure 12B] FIG. 12B is a cross-sectional view taken along line II' in FIG. 12A. [Figure 13] 1 is a schematic diagram of a display device according to an embodiment of the present invention; [Figure 14] FIG. 2 is a schematic diagram of a shift resist. [Figure 15] FIG. 14 is a circuit diagram of any one of the pixels in FIG. [Figure 16] FIG. 16 is a plan view of the pixel in FIG. [Figure 17] FIG. 17 is a cross-sectional view taken along line III-III' in FIG. [Figure 18] FIG. 11 is a circuit diagram of one pixel of a display device according to another embodiment of the present invention. [Figure 19] FIG. 11 is a circuit diagram of one pixel of a display device according to still another embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0041] The advantages and features of the present invention, as well as the methods for achieving the same, will become apparent from the following detailed description of various embodiments with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms, and the embodiments are provided only to complete the disclosure of the present invention and to inform those skilled in the art of the technical concept of the present invention of the scope of the technical concept.

[0042] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are merely examples, and the present invention is not limited to the matters shown in the drawings. The same components may be indicated by the same reference numerals throughout the specification. In addition, in the description of the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0043] When the specification uses the words "including," "having," "comprises," and "consists," other parts may be added unless the word "only" is used. When an element is expressed in the singular, the plural is included unless otherwise expressly stated.

[0044] In interpreting the elements, even if there is no separate explicit description, it is interpreted as including a margin of error.

[0045] For example, when describing the relative position of two parts using "on", "at the top of", "at the bottom of", "beside", etc., one or more other parts may be located between the two parts, unless the words "immediately" or "directly" are used.

[0046] Spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like, may be used to easily describe the relationship of one element or component to another element or component as shown in the drawings. Spatially relative terms should be understood to include different orientations of elements in use or operation in addition to the orientation shown in the drawings. For example, if an element shown in the drawings is turned upside down, an element described as "below" or "beneath" another element may be placed "above" the other element. Thus, the exemplary term "below" can include both an orientation of below and above. Similarly, the exemplary terms "above" or "upper" can include both an orientation of above and below.

[0047] When describing a temporal relationship, for example, when describing a temporal precedence relationship using "after", "following", "next to", "before", etc., it is possible to include cases where the relationship is not consecutive, as long as the words "immediately" or "directly" are not used.

[0048] Although the terms "first", "second", etc. are used to describe various components, these components are not limited to these terms. These terms are used only to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical spirit of the present invention.

[0049] The term "at least one" should be understood to include all possible combinations of one or more of the relevant items. For example, "at least one of the first, second and third items" means not only the first, second or third item, but also all possible combinations of two or more of the first, second and third items.

[0050] The various features of the various embodiments of the present invention may be partially or fully combined or combined with each other, and various technical interlocking and driving mechanisms may be possible, and each embodiment may be implemented independently of each other, or may be implemented together in a linked relationship.

[0051] When assigning reference numerals to components in each drawing for explaining the embodiments of the present invention, the same reference numerals may be used to designate the same components even if they are shown in different drawings.

[0052] In the embodiments of the present invention, the source electrode and the drain electrode are distinguished only for convenience of explanation, and the source electrode and the drain electrode may be interchangeable. A source electrode may be a drain electrode, and a drain electrode may be a source electrode. In addition, a source electrode in one embodiment may be a drain electrode in another embodiment, and a drain electrode in one embodiment may be a source electrode in another embodiment.

[0053] In one embodiment of the present invention, for convenience of explanation, the source region and the source electrode may be distinguished, and the drain region and the drain electrode may be distinguished, but the embodiment of the present invention is not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. Also, the source region may be the drain electrode, and the drain region may be the source electrode.

[0054] Fig. 1 is a plan view of a thin film transistor substrate 100 according to an embodiment of the present invention. Fig. 2 is a cross-sectional view taken along line II' in Fig. 1. Fig. 3 is a cross-sectional view taken along line II' in Fig. 1.

[0055] 1, 2 and 3, a thin film transistor substrate 100 according to one embodiment of the present invention includes a thin film transistor TFT on a substrate 110, and the thin film transistor TFT may include an active layer 130, a gate electrode 150, and conductive material layers 165, 175.

[0056] Specifically, referring to Figures 1, 2 and 3, the semiconductor device may include an active layer 130 on a substrate 110, a gate electrode 150 spaced apart from the active layer 130 and at least partially overlapping the active layer 130, and conductive material layers 165, 175 on the active layer 130.

[0057] The thin film transistor substrate 100 according to an embodiment of the present invention may further include a substrate 110. Referring to Figures 2 and 3, the active layer 130 is disposed on the substrate 110.

[0058] The thin film transistor substrate 100 according to an embodiment of the present invention may further include a buffer layer 120. Referring to Figures 2 and 3, the active layer 130 is disposed on the buffer layer 120. Specifically, the buffer layer 120 is disposed between the substrate 110 and the active layer 130.

[0059] The thin film transistor substrate 100 according to an embodiment of the present invention may further include a gate insulating layer 140. Referring to Figures 2 and 3, the gate insulating layer 140 is disposed on the active layer 130. Specifically, the gate insulating layer 140 is disposed between the active layer 130 and the gate electrode 150.

[0060] In the thin film transistor substrate 100 according to an embodiment of the present invention, another layer may be disposed on the gate electrode 150. Specifically, the thin film transistor substrate 100 may further include an interlayer insulating film 180. Referring to FIG. 17 , the interlayer insulating film 180 is disposed on the gate electrode 150. Specifically, the gate electrode 150 is disposed between the gate insulating film 140 and the interlayer insulating film 180.

[0061] The thin film transistor substrate 100 according to an embodiment of the present invention may further include a source electrode 160 and a drain electrode 170. Referring to Figures 1, 2 and 3, the source electrode 160 and the drain electrode 170 are disposed on the gate insulating layer 140.

[0062] Hereinafter, components of the thin film transistor substrate 100 according to an embodiment of the present invention will be described in more detail.

[0063] Glass or plastic can be used as the substrate 110. As the plastic, a transparent plastic having a flexible property, such as polyimide, can be used.

[0064] When polyimide is used as the substrate 110, a heat-resistant polyimide that can withstand high temperatures can be used, considering that a high-temperature deposition process is performed on the substrate 110. In this case, in order to form a thin film transistor, processes such as deposition and etching can be performed in a state where the polyimide substrate is placed on a carrier substrate made of a highly durable material such as glass.

[0065] 2 and 3, a buffer layer 120 may be disposed on a substrate 110.

[0066] The buffer layer 120 is formed on the substrate 110 and may be made of an inorganic or organic material. For example, silicon oxide (SiOx), aluminum oxide (Al 2 O 3 ) may be included as an insulating oxide.

[0067] The buffer layer 120 protects the active layer 130 by blocking impurities such as moisture and oxygen that may flow in from the substrate 110, and serves to planarize the upper surface of the substrate 110. The buffer layer 120 may be formed as a single layer or multiple layers.

[0068] 2 and 3, an active layer 130 may be disposed on the buffer layer 120.

[0069] The active layer 130 may include a channel region 130n, a source region 130a, and a drain region 130b.

[0070] Specifically, the active layer 130 may include a channel region 130n that at least partially overlaps with the gate electrode 150 on a plane, a source region 130a that does not overlap with the gate electrode 150 on a plane and is connected to one side of the channel region 130n, and a drain region 130b that does not overlap with the gate electrode 150 on a plane and is connected to the other side of the channel region 130n.

[0071] According to one embodiment of the present invention, source region 130a and drain region 130b are spaced apart with a channel region 130n therebetween.

[0072] According to an embodiment of the present invention, the active layer 130 may be formed of a semiconductor material. The active layer 130 may include an oxide semiconductor material.

[0073] The oxide semiconductor material may include at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, and an FIZO (FeInZnO)-based oxide semiconductor material. However, the present invention is not limited thereto, and the active layer 130 may be formed of other oxide semiconductor materials known in the art.

[0074] The source region 130a and the drain region 130b may be formed by selectively conducting the active layer 130 made of a semiconductor material. According to an embodiment of the present invention, selectively conducting refers to providing electrical conductivity to a specific portion of the active layer 130 so that it acts as a conductor.

[0075] For example, the active layer 130 may be selectively made conductive by ion doping, thereby forming the source region 130a and the drain region 130b. However, an embodiment of the present invention is not limited thereto, and the active layer 130 may be selectively made conductive by other methods known in the art.

[0076] The source region 130a and the drain region 130b do not overlap with the gate electrode 150. The source region 130a and the drain region 130b have superior electrical conductivity and high mobility compared to the channel region 130n. Therefore, each of the source region 130a and the drain region 130b can function as a wiring.

[0077] 1 and 3, an active hole 135 where no active layer 130 is disposed is disposed within an area whose edge is defined by the active layer 130. According to an embodiment of the present invention, the active hole 135 is disposed within an area defined by the active layer 130 on a plane. Specifically, the active hole 135 can be said to be an area formed by removing a portion of the active layer 130.

[0078] Referring to Figures 1 and 3, the active hole 135 can be said to be a hole formed in the active layer 130 by removing a portion of the active layer 130, and therefore, according to one embodiment of the present invention, the hole is referred to as an "active hole."

[0079] Specifically, according to one embodiment of the present invention, the active hole 135 may protrude from the gate electrode 150 toward the drain region 130b on a plane.

[0080] More specifically, the active layer 130 may not be disposed in a portion of the drain region 130b.

[0081] 1 and 3 show a configuration in which the active hole 135 protrudes from the gate electrode 150 toward the drain region 130b on a plane.

[0082] According to an embodiment of the present invention, a portion of the active hole 135 may overlap with the gate electrode 150. A configuration in which a portion of the active hole 135 overlaps with the gate electrode 150 is shown in FIGS.

[0083] More specifically, the active layer 130 may not be disposed in a portion of the channel region 130n.

[0084] According to an embodiment of the present invention, the active hole 135 may be formed by patterning the active layer 130. Specifically, the active hole 135 may be a region surrounded by the active layer 130. For example, the active hole 135 may be a portion where the active layer 130 is partially patterned and removed.

[0085] In general, when the channel region 130n of the active layer 130 has a large channel width, the conductive material may diffuse significantly in the boundary region between the channel region 130n and the drain region 130b. When the conductive material diffuses, the threshold voltage (Vth) of the thin film transistor may shift in the negative (-) direction, thereby reducing the driving safety of the thin film transistor.

[0086] When the channel region 130n of the active layer 130 has a small channel width, the diffusion of conductor may be reduced in the boundary region between the channel region 130n, the source region 130a, and the drain region 130b. On the other hand, when the channel region 130n of the active layer 130 has a small channel width, the total amount of carriers passing through the channel region 130n of the thin film transistor may be reduced, and the ON current characteristics may be degraded. As a result, when a large current flows through a thin film transistor having a small channel width of the channel region 130n, the thin film transistor may be damaged and the driving safety may be degraded. Therefore, it is necessary to control the diffusion of conductor while the active layer 130 has a large channel width.

[0087] According to an embodiment of the present invention, when the active hole 135 is formed to overlap with the gate electrode 150, the boundary between the channel region 130n and the drain region 130b of the active layer 130 is patterned, so that the region of the channel region 130n of the active layer 130 excluding the active hole is made conductive. As a result, even when the channel region 130n of the active layer 130 has a large channel width, the width of the region to be made conductive is narrowed, so that the penetration of the conductive material into the channel region 130n can be prevented or controlled, and the penetration of light or hydrogen into the channel region 130n of the active layer 130 can be suppressed or prevented.

[0088] According to an embodiment of the present invention, the active hole 135 may have a plurality of sub-active holes. FIG. 1 shows a configuration in which the active hole 135 has a plurality of sub-active holes. When the active hole 135 has a plurality of sub-active holes, each of the sub-active holes overlaps with at least a portion of the gate electrode 150. Also, when the active hole 135 has a plurality of sub-active holes, each of the sub-active holes is spaced apart from each other. However, an embodiment of the present invention is not limited thereto, and the active hole 135 may have a single sub-active hole.

[0089] According to an embodiment of the present invention, the active hole 135 may have a rectangular shape, however, the embodiment of the present invention is not limited thereto, and the active hole 135 according to an embodiment of the present invention may have various shapes.

[0090] According to one embodiment of the present invention, the thin film transistor substrate 100 may include conductive material layers 165, 175 on the active layer .

[0091] Specifically, with reference to Figures 1, 2 and 3, the conductive material layers 165, 175 may include a first conductive material layer 165 over the source region 130a and a second conductive material layer 175 over the drain region 130b.

[0092] More specifically, with reference to FIGS. 1, 2, and 3, first conductive material layer 165 and second conductive material layer 175 are spaced apart from each other with a portion of channel region 130n therebetween.

[0093] 1, 2, and 3, source region 130a and drain region 130b may be disposed between substrate 110 and first and second conductive material layers 165 and 175, respectively.

[0094] More specifically, with reference to Figures 1, 2 and 3, the first conductive material layer 165 and the second conductive material layer 175 can contact the active layer 130 via the source region 130a and the drain region 130b, respectively.

[0095] According to one embodiment of the present invention, the first conductive material layer 165 may overlap at least a portion of the channel region 130n. Figures 1, 2, and 3 show an arrangement in which the first conductive material layer 165 overlaps the channel region 130n. More specifically, the first conductive material layer 165 may overlap at least a portion of the gate electrode 150.

[0096] According to an embodiment of the present invention, when the first conductive material layer 165 overlaps the channel region 130n, the first conductive material layer 165 can protect the boundary region between the source region 130a and the channel region 130n from external light or hydrogen, thereby protecting the channel region 130n of the active layer 130 from external light or hydrogen.

[0097] According to one embodiment of the present invention, the second conductive material layer 175 may not be disposed over the active holes 135. In particular, a configuration in which the second conductive material layer 175 is not disposed over the active holes 135 is shown in FIGS.

[0098] According to an embodiment of the present invention, the active hole 135 may be disposed apart from the first conductive material layer 165. Specifically, the active hole 135 may not overlap with at least a portion of the gate electrode 150. FIG 1 illustrates a configuration in which the active hole 135 is disposed apart from the first conductive material layer 165 in a plan view.

[0099] According to one embodiment of the present invention, the first conductive material layer 165 may overlap the channel region 130n, while the second conductive material layer 175 may be spaced apart from the channel region 130n.

[0100] Specifically, in the case of the source region 130a of the active layer 130, the first conductive material layer 165 overlaps with the channel region 130n to protect the channel region 130n from external light or hydrogen, and in the case of the drain region 130b of the active layer 130, the active hole 135 overlaps with the gate electrode 150 to protect the channel region 130n from external light or hydrogen.

[0101] According to an embodiment of the present invention, the conductive material layers 165 and 175 may include at least one selected from titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodymium (Nd), calcium (Ca), barium (Ba), and transparent conductive oxide (TCO). The conductive material layers 165 and 175 may have reducing properties. According to an embodiment of the present invention, the transparent conductive oxide (TCO) may include ITO (InSnO), IZO (InZnO), IO (InO), TO (SnO), and ZO (ZnO).

[0102] The active layer 130 may be selectively made conductive by the conductive material layers 165 and 175. According to one embodiment of the present invention, the source region 130a and the drain region 130b are in contact with the first conductive material layer 165 and the second conductive material layer 175, respectively. Regions of the active layer 130 in contact with the first conductive material layer 165 and the second conductive material layer 175 may be made conductive to form the source region 130a and the drain region 130b, respectively.

[0103] Specifically, according to one embodiment of the present invention, the portions of the active layer 130 in contact with the conductive material layers 165 and 175 are reduced to form the source region 130a and the drain region 130b.

[0104] For example, when a portion of the active layer 130 that is in contact with and overlaps with the conductive material layers 165 and 175 is reduced, oxygen vacancies are generated in the active layer 130, and thus the active layer 130 can be selectively made conductive. By such selective reduction of the active layer 130, a source region 130a and a drain region 130b can be formed.

[0105] According to an embodiment of the present invention, the active layer 130 can be selectively made conductive by the conductive material layers 165 and 175 without a separate conductive process such as plasma treatment, ion doping, or UV treatment.

[0106] 1, when the shortest distance from the drain region 130b to the first conductive material layer 165 is defined as a first length L1 and the shortest length of the region where the first conductive material layer 165 overlaps with the gate electrode 150 in the longitudinal direction of the channel of the active layer 130 is defined as a second length L2, the first length L1 may be longer than the second length L2. Thus, the source region 130a of the active layer 130 can efficiently block light and hydrogen incident from the outside, thereby improving the reliability of the thin film transistor.

[0107] On the other hand, if the second length L2 is longer than the first length L1, the first conductive material layer 165 may overlap the gate electrode 150 excessively, causing the channel region 130n of the active layer 130 to become excessively conductive, and the threshold voltage (Vth) of the thin film transistor may shift in the negative (-) direction, decreasing the driving safety of the thin film transistor.

[0108] 1, if the shortest length of the region where the active hole 135 overlaps with the gate electrode 150 in the length direction of the channel of the active layer 130 is defined as a third length L3, and the shortest distance from the active hole 135 to the first conductive material layer 165 in the length direction of the channel of the active layer 130 is defined as a fourth length L4, the fourth length L4 may be longer than the third length L3. Thus, the drain region 130b of the active layer 130 can efficiently block light and hydrogen incident from the outside, thereby improving the reliability of the thin film transistor.

[0109] On the other hand, if the third length L3 is longer than the fourth length L4, the active holes 135 may penetrate excessively into the channel region 130n, reducing the total amount of carriers passing through the channel region 130n of the thin film transistor, and the ON current characteristics may be degraded. As a result, if a large current flows through the thin film transistor, the thin film transistor may be damaged, reducing driving safety.

[0110] According to an embodiment of the present invention, the thin film transistor substrate 100 may further include a source electrode 160 and a drain electrode 170 .

[0111] The source electrode 160 and the drain electrode 170 are disposed on the gate insulating film 140, and may be disposed on the same layer as the gate electrode 150. The source electrode 160 and the drain electrode 170 may be formed of the same material as the gate electrode 150 in the same process.

[0112] Each of the source electrode 160, the drain electrode 170, and the gate electrode 150 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). Each of the source electrode 160, the drain electrode 170, and the gate electrode 150 may have a multilayer structure including at least two conductive films having different physical properties.

[0113] 2 and 3, the source electrode 160 and the drain electrode 170 are connected to the active layer 130 through contact holes. Specifically, the source electrode 160 and the drain electrode 170 are connected to the active layer 130 by contacting the first conductive material layer 165 and the second conductive material layer 175, respectively.

[0114] 1, 2 and 3, a light blocking layer 111 may be disposed on a substrate 110. Specifically, the light blocking layer 111 may be disposed between the substrate 110 and the active layer 130. The light blocking layer 111 overlaps the channel region 130n. The light blocking layer 111 blocks light incident from the outside to protect the channel region 130n.

[0115] The light blocking layer 111 may be formed of a material having light blocking properties. The light blocking layer 111 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). According to an embodiment of the present invention, the light blocking layer 111 may have electrical conductivity.

[0116] The light-blocking layer 111 may be omitted. Although not shown in Figures 1, 2 and 3, a buffer layer may be further disposed between the substrate 110 and the light-blocking layer 111. Although not shown, the light-blocking layer 111 may be electrically connected to one of the source electrode 160 and the drain electrode 170. The light-blocking layer 111 may also be electrically connected to the gate electrode 150.

[0117] According to an embodiment of the present invention, the light-blocking layer 111 may be disposed so as to overlap with the front surface of the active layer 130. However, the embodiment of the present invention is not limited thereto, and the light-blocking layer 111 may be disposed so as not to overlap with a portion of the active layer 130 except for the channel region 130n.

[0118] Fig. 4 is a plan view of a thin film transistor substrate 200 according to another embodiment of the present invention, Fig. 5 is a cross-sectional view taken along line II' in Fig. 4, and Fig. 6 is a cross-sectional view taken along line II' in Fig. 4.

[0119] According to an embodiment of the present invention, the thin film transistor substrate 200 may further include a gate insulating layer 140 between the active layer 130 and the gate electrode 150. The source region 130a and the drain region 130b of the active layer 130 may be exposed from the gate insulating layer 140. Figures 5 and 6 show a configuration in which the source region 130a and the drain region 130b of the active layer 130 are exposed from the gate insulating layer 140.

[0120] However, an embodiment of the present invention is not limited thereto, and the gate insulating film 140 may cover the entire upper surface of the active layer 130. In the configuration shown in FIG. 2 and FIG. 3, the gate insulating film 140 covers the entire upper surface of the active layer 130.

[0121] The gate insulating film 140 may include at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating film 140 may have a single film structure or a multi-layer film structure. The gate insulating film 140 protects the channel region 130n.

[0122] FIG. 7 is a cross-sectional view of a thin film transistor substrate 300 according to another embodiment of the present invention, and FIG. 8 is a plan view of a thin film transistor substrate 400 according to another embodiment of the present invention.

[0123] According to an embodiment of the present invention, the active layer 130 of the thin film transistor substrate 300, 400 may have a multi-layer structure. For example, the active layer 130 may include a first active layer 131 and a second active layer 132.

[0124] Specifically, referring to FIG. 7, the active layer 130 may include a first active layer 131 and a second active layer 132 on the first active layer 131 .

[0125] The first active layer 131 and the second active layer 132 may include the same semiconductor material or different semiconductor materials.

[0126] The first active layer 131 supports the second active layer 132. Therefore, the first active layer 131 is also called a “support layer.” The structure in which the active layer 130 is made up of the first active layer 131 and the second active layer 132 is also called a bi-layer structure.

[0127] According to an embodiment of the present invention, the active layer 130 may further include a third active layer 133 on the second active layer 132 .

[0128] 7, the thin film transistor substrate 400 of Fig. 8 further includes an active layer 130 including a third active layer 133 on the second active layer 132. However, the embodiment of the present invention is not limited thereto, and the active layer 130 may further include other semiconductor layers.

[0129] Fig. 9 is a schematic diagram for explaining a capacitor of the present invention, Fig. 10 is a cross-sectional view of a thin film transistor substrate according to an embodiment for explaining a capacitor of the present invention, and Fig. 11 is a cross-sectional view of a thin film transistor substrate according to a comparative example for explaining a capacitor of the present invention.

[0130] 9 is a circuit diagram of one of the pixels P in FIG. 13, and more specifically, an equivalent circuit diagram of the pixel P of a display device 1000 including an organic light emitting diode (OLED) as the display element 710. FIG.

[0131] 9, a pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710. The pixel driving circuit PDC of FIG. 9 includes a first thin film transistor TR1 which is a switching transistor and a second thin film transistor TR2 which is a driving transistor.

[0132] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by a scan signal SS provided through the gate line GL.

[0133] The data line DL provides a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls the application of the data voltage Vdata.

[0134] The driving power line PL provides a driving voltage Vdd to the display element 710, and the first thin film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the display element 710, which is an organic light emitting diode (OLED).

[0135] When the first thin film transistor TR1 is turned on by a scan signal SS applied from the gate driver 320 through the gate line GL, a data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2 connected to the display element 710. The data voltage Vdata is charged in a first storage capacitor C1 formed between the gate electrode and source electrode of the second thin film transistor TR2.

[0136] FIG. 9 shows a gate voltage V GS 1 shows a schematic representation of the capacitance that can occur when

[0137] As shown in FIG. 9 and FIG. 10, a gate voltage V GS When this voltage is applied, a first parasitic capacitor Cp1 is formed between the source region 130a of the active layer 130 and the gate electrode 150, and a second parasitic capacitor Cp2 is formed between the drain region 130b of the active layer 130 and the gate electrode 150.

[0138] FIG. 10 shows a configuration in which a first conductive material layer 165 on the source region 130a overlaps with the gate electrode 150 while being spaced apart from each other to form a first parasitic capacitor Cp1, and a second conductive material layer 175 is spaced from the gate electrode 150 to form a second parasitic capacitor Cp2.

[0139] On the other hand, FIG. 11 shows a configuration in which a first conductive material layer 165 on the source region 130a does not overlap with the gate electrode 150 to form a first parasitic capacitor Cp1, and a second conductive material layer 175 is separated from the gate electrode 150 to form a second parasitic capacitor Cp2.

[0140] 11, the thin film transistor substrate of FIG. 10 has a first conductive material layer 165 on the source region 130a overlapping with the gate electrode 150 to form a first parasitic capacitor Cp1, so that the first parasitic capacitor Cp1 formed in the thin film transistor substrate of FIG. 10 can be larger than the first parasitic capacitor Cp1 formed in the thin film transistor substrate of FIG. 11.

[0141] In addition, compared to the thin film transistor substrate of FIG. 11, the thin film transistor substrate of FIG. 10 includes an active hole 135 that protrudes from the gate electrode 150 in a planar direction toward the drain region 130b and overlaps with the gate electrode 150, so that the second parasitic capacitor Cp2 formed in the thin film transistor substrate of FIG. 10 can be minimized and can be smaller than the second parasitic capacitor Cp2 formed in the thin film transistor substrate of FIG. 11.

[0142] 10, the first conductive material layer 165 on the source region 130a overlaps with the gate electrode 150 to form the first parasitic capacitor Cp1, and includes an active hole 135 that protrudes from the gate electrode 150 toward the drain region 130b on a plane and overlaps with the gate electrode 150, so that the first parasitic capacitor Cp1 is maximized and the second parasitic capacitor Cp2 is minimized. That is, the first parasitic capacitor Cp1 can be larger than the second parasitic capacitor Cp2. Therefore, the first parasitic capacitor Cp1 can function as a second storage capacitor C2.

[0143] As a result, referring to Figures 10, 12A and 12B, when a second storage capacitor C2 based on a first parasitic capacitor Cp1 is further formed in a thin film transistor substrate according to one embodiment of the present invention, the second storage capacitor C2 is formed in parallel with the first storage capacitor C1, thereby making it possible to easily secure the area of ​​the capacitor and improve space efficiency.

[0144] On the other hand, referring to FIG. 11, in the thin film transistor substrate according to the comparative example, the first conductive material layer 165 does not overlap with the gate electrode 150, so the first parasitic capacitor Cp1 cannot be sufficiently secured, and therefore the area of ​​the capacitor cannot be easily secured.

[0145] In addition, the thin film transistor substrate according to the comparative example does not include the active hole 135 in the drain region 130b, so the second parasitic capacitor Cp2 is not minimized. Therefore, an RC delay due to the second parasitic capacitor Cp2 may occur, making it difficult to charge the voltage. In addition, the second parasitic capacitor Cp2 causes heat generation and an increase in current consumption of the transistor.

[0146] According to an embodiment of the present invention, the thin film transistor substrate may include a third storage capacitor. Specifically, the thin film transistor substrate of Fig. 10 includes an active hole 135 that protrudes from the gate electrode 150 in a plan view toward the drain region 130b and overlaps with the gate electrode 150, as compared with the thin film transistor substrate of Fig. 11, and thus includes a third storage capacitor C3 formed such that the gate electrode 150 and the light blocking layer 111 overlap with a space therebetween.

[0147] According to an embodiment of the present invention, the third storage capacitor C3 is formed in a region where the gate electrode 150 and the light blocking layer 111 overlap with the active hole 135.

[0148] As a result, referring to Figures 10, 12A and 12B, when a third storage capacitor C3 is further formed in a thin film transistor substrate according to one embodiment of the present invention, the third storage capacitor C3 is formed in parallel with the first storage capacitor C1 and the second storage capacitor C2, thereby making it possible to easily secure the area of ​​the capacitor and improve space efficiency.

[0149] Meanwhile, referring to FIG. 11, the thin film transistor substrate according to the comparative example does not include the active hole 135, so that the third storage capacitor C3 cannot be secured, and therefore the area of ​​the capacitor cannot be easily secured.

[0150] Fig. 12A is a plan view of a thin film transistor substrate according to still another embodiment of the present invention, and Fig. 12B is a cross-sectional view taken along line II' of Fig. 12A.

[0151] According to an embodiment of the present invention, the thin film transistor substrate 500 includes a storage capacitor Cst. Specifically, the storage capacitor Cst may be provided in an overlapping region between the light blocking layer 111 and the thin film transistor TFT.

[0152] According to an embodiment of the present invention, the storage capacitor Cst includes a first storage capacitor C1, and the first storage capacitor C1 may include a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 and the second capacitor electrode CE2 may overlap each other to form a first capacitor C11.

[0153] According to an embodiment of the present invention, the first capacitor electrode CE1 may be connected to the light blocking layer 111. A configuration in which the first capacitor electrode CE1 is connected to the light blocking layer 111 is shown in FIG 12B.

[0154] According to an embodiment of the present invention, the second capacitor electrode CE2 may be connected to the active layer 130. Specifically, the second capacitor electrode CE2 may be connected to one of the source region 130a and the drain region 130b. Referring to FIG 12A, the second capacitor electrode CE2 may be connected to the source region 130a.

[0155] According to yet another embodiment of the present invention, the second capacitor electrode CE2 may include a first layer CE21 and a second layer CE22 on the first layer CE21. The second capacitor electrode CE2 may include the first layer CE21 integrated with any one of the source region 130a and the drain region 130b, and the second layer CE22 integrated with any one of the first conductive material layer 165 and the second conductive material layer 175.

[0156] FIG. 12A shows a configuration in which the second capacitor electrode CE2 includes a first layer CE21 that is integral with the source region 130a and a second layer CE22 that is integral with the first conductive material layer 165.

[0157] According to one embodiment of the present invention, the second capacitor electrode CE2 can be formed using the active layer 130 and the conductive material layers 165 and 175, so that a separate process for forming the second capacitor electrode CE2 is not required, and as a result, space efficiency is improved and the area of ​​the second capacitor electrode CE2 can be increased.

[0158] 12A and 12B, the thin film transistor substrate 500 according to an embodiment of the present invention may further include a third capacitor electrode CE3 connected to the gate electrode 150. The third capacitor electrode CE3 may be formed of the same material and in the same process as the gate electrode 150, the source electrode 160, and the drain electrode 170.

[0159] According to an embodiment of the present invention, the second capacitor electrode CE2 and the third capacitor electrode CE3 may overlap each other to form a second capacitor C12.

[0160] Since the gate electrode 150 and the third capacitor electrode CE3 are connected to each other, the first capacitor electrode CE1 and the third capacitor electrode CE3 can be connected to each other, and the same voltage can be applied to the first capacitor electrode CE1 and the third capacitor electrode CE3.

[0161] 12A and 12B, the second capacitor electrode CE2 is disposed between the first capacitor electrode CE1 and the third capacitor electrode CE3, which produces the same effect as if two capacitors C11 and C12 were formed with the second capacitor electrode CE2 sandwiched therebetween.

[0162] FIG. 13 is a schematic diagram of a display device 1000 according to yet another embodiment of the present invention.

[0163] A display device 1000 according to another embodiment of the present invention may include a display panel 310, a gate driver 320, a data driver 330, and a controller 340, as shown in FIG.

[0164] The display panel 310 includes gate lines GL and data lines DL, and pixels P are disposed at intersections of the gate lines GL and the data lines DL. Images are displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be disposed on a substrate 110.

[0165] The control unit 340 controls the gate driver 320 and the data driver 330 .

[0166] The controller 340 uses a signal provided from an external system (not shown) to output a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330. In addition, the controller 340 samples input image data provided from the external system, realigns the input image data, and provides the realigned digital image data RGB to the data driver 330.

[0167] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, a gate clock GCLK, etc. The gate control signal GCS may also include a control signal for controlling a shift register.

[0168] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like.

[0169] The data driver 330 supplies a data voltage to the data lines DL of the display panel 310. More specifically, the data driver 330 converts the digital image data RGB input from the controller 340 into an analog data voltage, and supplies the data voltage to the data lines DL.

[0170] According to an embodiment of the present invention, the gate driver 320 may be mounted on the display panel 310. Such a structure in which the gate driver 320 is directly mounted on the display panel 310 is called a Gate In Panel (GIP) structure. Specifically, in the Gate In Panel (GIP) structure, the gate driver 320 may be disposed on the substrate 110.

[0171] The display device 1000 according to an embodiment of the present invention may include the above-described thin film transistor substrates 100, 200, 300, 400, and 500. According to an embodiment of the present invention, the gate driver 320 may include the above-described thin film transistor substrates 100, 200, 300, 400, and 500.

[0172] The gate driver 320 may include a shift register 350 .

[0173] The shift register 350 sequentially supplies gate pulses to the gate lines GL during one frame using a start signal and a gate clock transmitted from the control unit 340. Here, one frame refers to a period during which one image is output through the display panel 310. The gate pulse has a turn-on voltage that can turn on a switching element (thin film transistor) arranged in the pixel P.

[0174] In addition, the shift register 350 supplies a gate-off signal to the gate line GL for turning off the switching element during the remaining period during which the gate pulse is not supplied during one frame. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as a scan signal SS or Scan.

[0175] The shift register 350 may include the thin film transistor substrates 100, 200, 300, 400, and 500 described above.

[0176] FIG. 14 is a schematic diagram of a shift register 350.

[0177] Referring to FIG. 14, the shift register 350 can include g stages 351ST1 to STg.

[0178] The shift register 350 transmits one scan signal SS to a pixel P connected to one gate line GL through one gate line GL. Each of the stages 351 may be connected to one gate line GL. When g gate lines GL are formed on the display panel 310, the shift register 350 may include g stages 351ST1 to STg and may generate g scan signals SS1 to SSg.

[0179] In general, each stage 351 outputs a gate pulse GP once during one frame, and the gate pulse GP is output from each stage 351 in sequence.

[0180] FIG. 15 is a circuit diagram of any one of the pixels P in FIG.

[0181] The circuit diagram of FIG. 15 is an equivalent circuit diagram of a pixel P of a display device 1000 that includes an organic light emitting diode (OLED) as a display element 710.

[0182] 15, a pixel P includes a display element 710 and a pixel driving circuit PDC that drives the display element 710. Specifically, a display device 1000 according to an embodiment of the present invention may include a pixel driving circuit PDC on a substrate 110.

[0183] 15 includes a first thin film transistor TR1 which is a switching transistor and a second thin film transistor TR2 which is a driving transistor. A display device 1000 according to another embodiment of the present invention may include at least one of thin film transistor substrates 100, 200, 300, 400, and 500.

[0184] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by a scan signal SS provided through the gate line GL.

[0185] The data line DL provides a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls the application of the data voltage Vdata.

[0186] The driving power line PL provides a driving voltage Vdd to the display element 710, and the first thin film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the display element 710, which is an organic light emitting diode (OLED).

[0187] When the first thin film transistor TR1 is turned on by a scan signal SS applied from the gate driver 320 through the gate line GL, a data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2 connected to the display element 710. The data voltage Vdata is charged in a storage capacitor C1 formed between the gate electrode and source electrode of the second thin film transistor TR2.

[0188] The amount of current supplied to an organic light emitting diode (OLED) serving as the display element 710 through the second thin film transistor TR2 is controlled by the data voltage Vdata, and thus the gray scale of the light output from the display element 710 can be controlled.

[0189] 16 is a plan view of the pixel of FIG. 15, and FIG. 17 is a cross-sectional view taken along line III-III' of FIG.

[0190] 15 and 16, the first thin film transistor TR1 and the second thin film transistor TR2 are disposed on a substrate 110. The first thin film transistor TR1 and the second thin film transistor TR2 include conductive material layers 165 and 175.

[0191] The substrate 110 may be made of glass or plastic. Plastic having flexible properties, such as polyimide (PI), may be used as the substrate 110.

[0192] The light blocking layer 111 is disposed on the substrate 110. The light blocking layer 111 may have light blocking properties. The light blocking layer 111 may block light incident from the outside to protect the active layers A1 and A2.

[0193] The buffer layer 120 is disposed on the light blocking layer 111. The buffer layer 120 is made of an insulating material and protects the active layers A1 and A2 from moisture, oxygen, and the like that may flow in from the outside.

[0194] On the buffer layer 120, a first active layer A1 of the first thin film transistor TR1 and a second active layer A2 of the second thin film transistor TR2 are disposed.

[0195] The first active layer A1 and the second active layer A2 may include, for example, an oxide semiconductor material. The first active layer A1 and the second active layer A2 may be formed of an oxide semiconductor layer made of an oxide semiconductor material.

[0196] In the first thin film transistor TR1, the first active layer A1 may include a channel region, a source region, and a drain region. The channel region of the first active layer A1 overlaps with the gate electrode G1. According to another embodiment of the present invention, the source region may be referred to as a source electrode S1, and the drain region may be referred to as a drain electrode D1.

[0197] In the second thin film transistor TR2, the second active layer A2 may include a channel region, a source region, and a drain region. The channel region of the second active layer A2 overlaps with the gate electrode G2. According to another embodiment of the present invention, the source region may be referred to as a source electrode S2, and the drain region may be referred to as a drain electrode D2.

[0198] In the first thin film transistor TR1, the first conductive material layer 165 is disposed on the source region of the first active layer A1 and overlaps the gate electrode G1. In the second thin film transistor TR2, the first conductive material layer 165 is disposed on the source region of the second active layer A2 and overlaps the gate electrode G2.

[0199] 16 and 17, a portion of the light blocking layer 111 may become a first capacitor electrode CE1 of a first capacitor C11.

[0200] In addition, a portion of the second active layer A2 may become the second capacitor electrode CE2 of the first capacitor C11, or the second capacitor electrode CE2 of the second capacitor C12.

[0201] A gate insulating film 140 is disposed on the first active layer A1 and the second active layer A2. The gate insulating film 140 may cover the entire top surfaces of the first active layer A1 and the second active layer A2, or may cover only a portion of the first active layer A1 and the second active layer A2.

[0202] On the gate insulating film 140, a gate electrode G1 of the first thin film transistor TR1 and a gate electrode G2 of the second thin film transistor TR2 are disposed.

[0203] The gate electrode G1 of the first thin film transistor TR1 at least partially overlaps the first active layer A1 of the first thin film transistor TR1, and the gate electrode G2 of the second thin film transistor TR2 at least partially overlaps the second active layer A2 of the second thin film transistor TR2.

[0204] A source electrode S1 and a drain electrode D1 of the first thin film transistor TR1 are disposed on the gate insulating film 140. Also, a source electrode S2 and a drain electrode D2 of the second thin film transistor TR2 are disposed.

[0205] The source electrode S1 and the drain electrode D1 of the first thin film transistor TR1 are disposed on the same layer as the source electrode S2 and the drain electrode D2 of the second thin film transistor TR2. Specifically, the gate electrode G1, the source electrode S1 and the drain electrode D1 of the first thin film transistor TR1, the gate electrode G2, the source electrode S2 and the drain electrode D2 of the second thin film transistor TR2 are disposed on the same layer.

[0206] An interlayer insulating film 180 is disposed on the gate electrodes G1 and G2, the source electrodes S1 and S2, and the drain electrodes D1 and D2.

[0207] The data lines DL and the driving power lines PL are disposed on the interlayer insulating film 180 .

[0208] The data line DL contacts a first source electrode S1 formed in the first active layer A1 through a first contact hole H1. According to another embodiment of the present invention, a portion of the data line DL overlapping with the first active layer A1 may be referred to as a first source electrode S1.

[0209] The driving power line PL contacts a second drain electrode D2 formed in the second active layer A2 through an eleventh contact hole H11. According to still another embodiment of the present invention, a part of the driving power line PL overlapping with the second active layer A2 can be referred to as a second drain electrode D2.

[0210] 16 and 17, a portion of the gate electrode G2 of the second thin film transistor TR2 may become the third capacitor electrode CE3 of the second capacitor C12.

[0211] 16 and 17, the first capacitor electrode CE1 overlaps with the second capacitor electrode CE2 to form a first capacitor C11, and the second capacitor electrode CE2 overlaps with the third capacitor electrode CE3 to form a second capacitor C12.

[0212] 16 and 17, a first bridge BR1 is disposed on an interlayer insulating film 180. The first bridge BR1 is connected to the first drain electrode D1 through a fourth contact hole H4 and to the third capacitor electrode CE3 of the second capacitor C12 through a fifth contact hole.

[0213] 16 and 17, the third capacitor electrode CE3 is connected to the light blocking layer 111 through a sixth contact hole H6.

[0214] A planarization layer 190 is disposed on the data line DL, the first bridge BR1, and the driving power line PL. The planarization layer 190 planarizes the tops of the first thin film transistor TR1 and the second thin film transistor TR2 to protect the first thin film transistor TR1 and the second thin film transistor TR2.

[0215] A first electrode 711 of the display element 710 is disposed on the planarization layer 190. The first electrode 711 of the display element 710 contacts a second source electrode S2 of the second thin film transistor TR2 through a ninth contact hole H9 formed in the planarization layer 190 and an eighth contact hole H8 formed in the interlayer insulating film 180. As a result, the first electrode 711 can be connected to the second source electrode S2 of the second thin film transistor TR2. The first electrode 711 is also connected to the second active layer A2 through a seventh contact hole H7 formed in the gate insulating film 140.

[0216] A bank layer 750 is disposed on the edge of the first electrode 711. The bank layer 750 defines the light-emitting area of ​​the display element 710.

[0217] An organic light emitting layer 712 is disposed on the first electrode 711, and a second electrode 713 is disposed on the organic light emitting layer 712. Thus, a display element 710 is completed. The display element 710 shown in Fig. 17 is an organic light emitting diode (OLED). Thus, the display device 1000 according to the embodiment of the present invention is an organic light emitting display device.

[0218] FIG. 18 is a circuit diagram of one pixel of a display device 1100 according to another embodiment of the present invention.

[0219] FIG. 18 is an equivalent circuit diagram of a pixel P of an organic light-emitting display device.

[0220] 18 includes an organic light emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0221] In the pixel P, signal lines DL, GL, PL, RL, and SCL are arranged to supply signals to a pixel drive circuit PDC.

[0222] A data voltage Vdata is supplied to the data line DL, a scan signal SS is supplied to the gate line GL, a driving voltage Vdd for driving the pixels is supplied to the driving power line PL, a reference voltage Vref is supplied to the reference line RL, and a sensing control signal SCS is supplied to the sensing control line SCL.

[0223] The pixel driving circuit PDC includes, for example, a first thin film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL, a second thin film transistor TR2 (driving transistor) for controlling the magnitude of the current output to the display element 710 according to the data voltage Vdata transmitted through the first thin film transistor TR1, and a third thin film transistor TR3 (sensing transistor) for sensing the characteristics of the second thin film transistor TR2.

[0224] The first thin film transistor TR1 is turned on by a scan signal SS supplied to the gate line GL, thereby transmitting a data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2.

[0225] The third thin film transistor TR3 is connected to the first node n1 between the second thin film transistor TR2 and the display element 710 and to the reference line RL, and is turned on or off by a sensing control signal SCS to sense the characteristics of the second thin film transistor TR2, which is a driving transistor, during the sensing period.

[0226] A second node n2 connected to the gate electrode of the second thin film transistor TR2 is connected to the first thin film transistor TR1 A storage capacitor Cst is formed between the second node n2 and the first node n1.

[0227] When the first thin film transistor TR1 is turned on, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TR2, and the data voltage Vdata is charged in a storage capacitor Cst formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0228] When the second thin film transistor TR2 is turned on, a current is supplied to the display element 710 via the second thin film transistor TR2 by the driving voltage Vdd for driving the pixel, so that the display element 710 outputs light.

[0229] A display device 1100 according to another embodiment of the present invention may include at least one of the thin film transistor substrates 100, 200, 300, 400, and 500.

[0230] FIG. 19 is a circuit diagram of one of pixels P of a display device 1200 according to still another embodiment of the present invention.

[0231] 19 includes an organic light emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0232] The pixel driving circuit PDC includes thin film transistors TR1, TR2, TR3, and TR4.

[0233] In the pixel P, signal lines DL, EL, GL, PL, SCL, and RL are arranged which supply drive signals to a pixel drive circuit PDC.

[0234] The pixel P of Fig. 19 further includes an emission control line EL, which is provided with an emission control signal EM, compared to the pixel P of Fig. 18. Furthermore, the pixel driving circuit PDC of Fig. 19 further includes a fourth thin film transistor TR4, which is an emission control transistor for controlling the emission time point of the second thin film transistor TR2, compared to the pixel driving circuit PDC of Fig. 18.

[0235] The first thin film transistor TR1 is turned on by a scan signal SS supplied to the gate line GL, thereby transmitting a data voltage Vdata supplied to the data line DL to the gate electrode of the second thin film transistor TR2.

[0236] The storage capacitor Cst is located between the gate electrode of the second thin film transistor TR2 and the display element 710.

[0237] The third thin film transistor TR3 is connected to the reference line RL and is turned on or off by a sensing control signal SCS to sense the characteristics of the third thin film transistor TR3, which is a driving transistor, during a sensing period.

[0238] The fourth thin film transistor TR4 transmits the driving voltage Vdd to the second thin film transistor TR2 or blocks the driving voltage Vdd according to the light emission control signal EM. When the fourth thin film transistor TR4 is turned on, a current is supplied to the second thin film transistor TR2, so that light is output from the display element 710.

[0239] The pixel driving circuit PDC according to further embodiments of the present invention may be formed in various other structures than those described above.The pixel driving circuit PDC may include, for example, five or more thin film transistors.

[0240] The present invention described above is not limited to the above-mentioned embodiments and the accompanying drawings, and various substitutions, modifications and changes are possible within the scope of the technical subject matter of the present invention, which will be apparent to those skilled in the art to which the present invention pertains. Therefore, the scope of the present invention is determined by the claims set forth below, and all modifications and changes derived from the meaning, scope and equivalent concept of the claims should be interpreted as being included in the scope of the present invention. [Explanation of symbols]

[0241] 110 Substrate 120 Buffer Layer 130 active layer 130n channel region 130a Source Region 130b Drain region 131 First active layer 132 Second active layer 133 Third active layer 111 Light blocking layer 135 Active Holes 140 Gate insulating film 150 Gate electrode 160 Source Electrode 170 Drain electrode 180 Interlayer insulating film 165 First conductive material layer 175 Second conductive material layer

Claims

1. a substrate; and a thin film transistor on the substrate; The thin film transistor is The active layer, a layer of conductive material on the active layer; a gate electrode spaced apart from the active layer and partially overlapping the active layer; The active layer is a channel region that partially overlaps with the gate electrode in a plane; a source region coupled to one side of the channel region in the plane; a drain region coupled to the other side of the channel region in the plane; The conductive material layer is a first layer of conductive material over the source region; a second layer of conductive material over the drain region; the first conductive material layer overlaps at least a portion of the channel region; the active layer includes an active hole within an area defined by the active layer where the active layer is not disposed; The active hole extends in a plane from the channel region to the drain region.

2. The thin film transistor substrate according to claim 1 , wherein a portion of the active hole overlaps with the gate electrode in the plane.

3. The thin film transistor substrate of claim 1 , wherein the active hole is spaced apart from the first conductive material layer in the plane.

4. The thin film transistor substrate of claim 1 , wherein the second conductive material layer is spaced apart from the channel region in the plane.

5. the source region and the drain region are disposed between a base substrate and the first layer of conductive material and the second layer of conductive material, respectively; The thin film transistor substrate of claim 1 , wherein each of the first and second conductive layers contacts the active layer.

6. a source electrode and a drain electrode spaced apart from each other and in contact with the source region and the drain region, respectively; The thin film transistor substrate of claim 1 , wherein the gate electrode, the source electrode and the drain electrode are disposed on the same layer.

7. The active hole has a plurality of sub-active holes, The plurality of sub-active holes are spaced apart from each other, The thin film transistor substrate according to claim 1 , wherein each of the plurality of sub-active holes has an elongated shape extending from the channel region to the drain region.

8. 2. The thin film transistor substrate of claim 1, wherein the conductive material layer comprises at least one selected from the group consisting of titanium (Ti), molybdenum (Mo), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), tantalum (Ta), neodymium (Nd), calcium (Ca), barium (Ba) and a transparent conductive oxide (TCO).

9. a first length is a shortest distance from the drain region to the first conductive material layer; a second length is a shortest length that the first conductive material layer overlaps with the gate electrode in the plane in a length direction of a channel of the active layer; The thin film transistor substrate of claim 1 , wherein the first length is greater than the second length.

10. a portion of the active hole overlaps with the gate electrode; a third length is a shortest length of an overlap between the active hole and the gate electrode in a longitudinal direction of a channel of the active layer; a fourth length is a shortest distance from the active hole to the first conductive material layer in a length direction of a channel of the active layer; The thin film transistor substrate of claim 1 , wherein the fourth length is greater than the third length.

11. a light blocking layer on the substrate; The thin film transistor substrate of claim 1 , further comprising a storage capacitor in an overlapping region between the light blocking layer and the thin film transistor.

12. the storage capacitor comprises a first storage capacitor; The first storage capacitor is a first capacitor electrode connected to the light blocking layer; a second capacitor electrode coupled to the active layer, The thin film transistor substrate of claim 11 , wherein the first capacitor electrode and the second capacitor electrode are spaced apart from each other and overlap each other to form a first capacitor.

13. the first storage capacitor includes a third capacitor electrode connected to the gate electrode; The thin film transistor substrate of claim 12 , wherein the second capacitor electrode and the third capacitor electrode are spaced apart from each other and overlap each other to form a second capacitor.

14. The second capacitor electrode is a first layer integral with one of the source region and the drain region; 13. The thin film transistor substrate of claim 12, further comprising: a second layer integral with one of the first conductive material layer and the second conductive material layer.

15. the second capacitor electrode is between the first capacitor electrode and the third capacitor electrode; The thin film transistor substrate of claim 13 , wherein the third capacitor electrode is connected to the first capacitor electrode.

16. The thin film transistor substrate of claim 11 , wherein the storage capacitor comprises a second storage capacitor formed by overlapping the gate electrode and the first conductive material layer while being spaced apart from each other.

17. The thin film transistor substrate of claim 11 , wherein the storage capacitor comprises a third storage capacitor formed by overlapping the gate electrode and the light blocking layer while being spaced apart from each other.

18. The thin film transistor substrate of claim 17 , wherein the third storage capacitor is in a region overlapping with the active hole.

19. the active layer comprises an oxide semiconductor material; 2. The thin film transistor substrate of claim 1, wherein the oxide semiconductor material comprises at least one of an IZO (InZnO)-based, an IGO (InGaO)-based, an ITO (InSnO)-based, an IGZO (InGaZnO)-based, an IGZTO (InGaZnSnO)-based, a GZTO (GaZnSnO)-based, a GZO (GaZnO)-based, an ITZO (InSnZnO)-based, and an FIZO (FeInZnO)-based oxide semiconductor material.

20. A display device comprising the thin film transistor substrate according to any one of claims 1 to 19.

Images