Memory system

Abstract

To provide a memory system capable of improving processing capacity.SOLUTION: A memory system includes a memory chip and a memory controller. First and second cell units CU are classified into a first group CU_Gr1, a third cell unit CU is classified into a second group CU_Gr2. When reading first group data, the memory controller uses a first correction amount of a read-out voltage. When reading second group data, the memory controller uses a second correction amount of the read-out voltage. When a time difference from execution of a write operation of the first cell unit to execution of a write operation of the second cell unit exceeds a reference value, the memory controller changes a boundary position between the first group and the second group to between the first cell unit and the second cell unit, and classifies the second cell unit into the second group.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present invention relate to a memory system. [Background technology]

[0002] 2. Description of the Related Art As a memory system, a solid state drive (SSD) equipped with a nonvolatile memory device such as a NAND flash memory is known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Publication No. 2021 / 0326250 [Patent Document 2] U.S. Patent No. 10048863 [Patent Document 3] US Patent Publication No. 2020 / 0225852 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment of the present invention provides a memory system that allows for increased processing power. [Means for solving the problem]

[0005] A memory system according to an embodiment includes a memory chip including a block including a plurality of cell units each including a plurality of memory cells, and a memory controller. A first cell unit and a second cell unit among the plurality of cell units are classified into a first group, and a third cell unit among the plurality of cell units is classified into a second group. The memory controller uses a first correction amount of a read voltage when reading data from a plurality of memory cells of the cell unit classified into the first group among the plurality of cell units, and uses a second correction amount of a read voltage when reading data from a plurality of memory cells of the cell unit classified into the second group among the plurality of cell units. When a time difference between performing a write operation of the first cell unit and performing a write operation of the second cell unit exceeds a reference value, the memory controller is configured to change a boundary position between the first group and the second group to between the first cell unit and the second cell unit and classify the second cell unit into the second group. [Brief description of the drawings]

[0006] [Figure 1] 1 is a block diagram showing an example of an overall configuration of a data processing device including a memory system according to a first embodiment. [Diagram 2] 1 is a block diagram showing an example of the configuration of a memory chip included in a memory system according to a first embodiment. [Diagram 3] 2 is a diagram showing an example of the configuration of a memory area of ​​a bank included in the memory system according to the first embodiment. [Figure 4] 1 is a diagram showing an example of the configuration of a memory area of ​​a nonvolatile memory when the memory system according to the first embodiment is a ZNS-compliant memory system. [Diagram 5] 1 is a circuit diagram showing the configuration of a memory cell array included in a memory system according to a first embodiment. [Figure 6] 3 is a schematic diagram showing an example of threshold voltage distribution of a memory cell transistor in a memory cell array included in the memory system according to the first embodiment. [Figure 7]3 is a cross-sectional view of a NAND string that is a partial area of ​​a block included in the memory system according to the first embodiment. [Figure 8] Cross-sectional view of the memory pillar taken along line VI-VI in Figure 7. [Figure 9] 2 is a schematic diagram showing an example of the configuration of a cell unit group in one block included in the memory system according to the first embodiment. [Figure 10] 4 is a table showing an example of a configuration of Vth information in the memory system according to the first embodiment. [Figure 11] 1 is a table showing an example of CU_Gr conversion information in the memory system according to the first embodiment. [Figure 12] 6 is a flowchart showing an example of the flow of a write operation in the memory system according to the first embodiment. [Figure 13] 10 is a flowchart showing an example of a flow of registering CU_Gr conversion information in the memory system according to the first embodiment. [Figure 14] 5 is a schematic diagram showing a first specific example of boundary line movement in one block included in the memory system according to the first embodiment. FIG. [Figure 15] 11 is a table showing an example of CU_Gr conversion information in a first specific example of boundary line movement in the memory system according to the first embodiment. [Figure 16] FIG. 11 is a schematic diagram showing a second specific example of boundary line movement in one block included in the memory system according to the first embodiment. [Figure 17] 13 is a table showing an example of CU_Gr conversion information in a second specific example of boundary line movement in the memory system according to the first embodiment. [Figure 18] FIG. 11 is a schematic diagram showing an example of a configuration of a cell unit group in one block included in a memory system according to a first modified example of the first embodiment. [Figure 19] FIG. 11 is a schematic diagram showing a first specific example of boundary line movement in one block included in a memory system according to a first modified example of the first embodiment. [Figure 20]FIG. 11 is a schematic diagram showing a second specific example of boundary line movement in one block included in the memory system according to the first modified example of the first embodiment. [Figure 21] 13 is a table showing an example of CU_Gr conversion information and anchor conversion information in the memory system according to the second embodiment. [Figure 22] 13 is a flowchart showing an example of a flow of registration of CU_Gr conversion information and anchor conversion information in a memory system according to the second embodiment. [Figure 23] FIG. 13 is a schematic diagram showing a first specific example of boundary and anchor movement in one block included in the memory system according to the second embodiment. [Figure 24] 13 is a table showing an example of CU_Gr conversion information and anchor conversion information in a first specific example of boundary line and anchor movement in a memory system according to the second embodiment. [Diagram 25] FIG. 13 is a schematic diagram showing a second specific example of boundary and anchor movement in one block included in the memory system according to the second embodiment. [Figure 26] 13 is a table showing an example of Vth information, CU_Gr conversion information, and anchor conversion information in a second specific example of boundary line and anchor movement in a memory system according to the second embodiment. [Figure 27] FIG. 13 is a schematic diagram showing a third specific example of boundary and anchor movement in one block included in the memory system according to the second embodiment. [Figure 28] 13 is a table showing an example of Vth information, CU_Gr conversion information, and anchor conversion information in a third specific example of boundary line and anchor movement in the memory system according to the second embodiment. [Figure 29] FIG. 13 is a schematic diagram showing a fourth specific example of boundary and anchor movement in one block included in the memory system according to the second embodiment. [Diagram 30] 13 is a table showing an example of Vth information, CU_Gr conversion information, and anchor conversion information in a fourth specific example of boundary line and anchor movement in the memory system according to the second embodiment. [Diagram 31]13 is a flowchart showing a flow of registering anchor conversion information in a memory system according to a modified example of the second embodiment. [Diagram 32] 13 is a flowchart showing an example of a flow of registration of CU_Gr conversion information and anchor conversion information in a memory system according to the third embodiment. [Diagram 33] 13 is a schematic diagram showing a specific example of boundary and anchor movement in one block included in the memory system according to the third embodiment. [Diagram 34] 13 is a table showing an example of Vth information, CU_Gr conversion information, and anchor conversion information in a specific example of boundary line and anchor movement in a memory system according to the third embodiment. [Diagram 35] 13 is a flowchart showing a flow of registering anchor conversion information in a memory system according to a modified example of the third embodiment. [Diagram 36] 13 is a flowchart showing an example of a flow of adding a cell unit group and an anchor in a memory system according to the fourth embodiment. [Figure 37] 13 is a schematic diagram showing a specific example of adding a cell unit group and an anchor in one block included in a memory system according to the fourth embodiment. [Figure 38] 13 is a table showing an example of Vth information, CU_Gr conversion information, and anchor conversion information in a specific example of cell unit group and anchor addition in a memory system according to the fourth embodiment. [Figure 39] 13 is a flowchart showing a flow of adding a cell unit group in a memory system according to a modified example of the fourth embodiment. [Diagram 40] FIG. 13 is a schematic diagram showing a specific example of adding a cell unit group in one block included in a memory system according to a modified example of the fourth embodiment. [Diagram 41] 13 is a table showing an example of Vth information, CU_Gr conversion information, and anchor conversion information in a specific example of adding a cell unit group in a memory system according to a modification of the fourth embodiment. [Diagram 42]13 is a flowchart showing an example of the flow of a padding data insertion process in a memory system according to a fifth embodiment. [Diagram 43] 13 is a schematic diagram showing a specific example of inserting padding data in one block included in a memory system according to a fifth embodiment. [Diagram 44] FIG. 13 is a schematic diagram showing a specific example of inserting padding data in one block included in a memory system according to a modification of the fifth embodiment. [Diagram 45] 13 is a flowchart showing an example of a flow of a process of inserting padding data and registering anchor conversion information in a memory system according to a sixth embodiment. [Diagram 46] FIG. 23 is a schematic diagram showing a specific example of inserting padding data and moving an anchor in one block included in a memory system according to a sixth embodiment. [Figure 47] 13 is a table showing an example of Vth information and anchor conversion information in a specific example of padding data insertion and anchor movement in a memory system according to the sixth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment will be described with reference to the drawings. The drawings are schematic. In the following description, components having substantially the same functions and configurations are given the same reference numerals. The numbers following the letters constituting the reference numerals are used to distinguish between elements that are referred to by the reference numerals containing the same letters and have similar configurations. When it is not necessary to distinguish between elements indicated by reference numerals containing the same letters, these elements are referred to by reference numerals containing only the same letters.

[0008] A memory system according to an embodiment will be described below.

[0009] 1 Configuration 1.1 Configuration of information processing device 1.1.1 Data Processing Device Configuration First, an example of the configuration of a data processing device 1 including a memory system will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the overall configuration of the data processing device 1.

[0010] 1, a data processing device 1 includes a host device 2 and a memory system 3. The data processing device 1 may include multiple host devices 2 or multiple memory systems 3. When the data processing device 1 includes multiple host devices 2 and multiple memory systems 3, multiple memory systems 3 may be connected to one host device 2. Also, multiple host devices 2 may be connected to one memory system 3.

[0011] The host device 2 is an information processing device (computing device) that accesses the memory system 3. The host device 2 controls the memory system 3. More specifically, for example, the host device 2 requests (commands) the memory system 3 to perform a data write operation or a data read operation.

[0012] The memory system 3 is, for example, a solid state drive (SSD). The memory system 3 is connected to the host device 2 via a host bus HB. In this embodiment, a case will be described in which PCIe (Peripheral Component Interconnect Express) (registered trademark) is applied as a connection standard for interconnecting the host device 2 and the memory system 3, and NVMe (Non Volatile Memory Express) (registered trademark) is applied as a communication protocol. The memory system 3 of this embodiment may be compatible with ZNS (Zoned Namespace), which is one of the NVMe standards (hereinafter, referred to as a "ZNS-compatible memory system"), or may not be compatible with ZNS (hereinafter, referred to as a "ZNS-incompatible memory system"). When the memory system 3 is a ZNS-compatible memory system, the memory system 3 does not have a function as a flash translation layer (FTL) that associates a logical address received from the host device 2 with a physical address of the non-volatile memory. In this case, the host device 2 assigns hot data (relatively frequently accessed data) or cold data (relatively infrequently accessed data) to each zone in the memory area. A zone is a divided memory area of ​​the non-volatile memory 10. The memory system 3 executes a write operation, an erase operation, etc. for each zone. For example, when multiple host devices 2 are connected to the memory system 3, each host device 2 is assigned a different zone.

[0013] For example, if the memory system 3 is a non-ZNS compliant memory system, the memory system 3 executes garbage collection and padding data insertion processing.

[0014] Garbage collection is a process of reading valid data from multiple blocks and rewriting (copying) it to another block. A block to which all valid data has been copied by garbage collection becomes erasable. For example, data erasure operations in the nonvolatile memory 10 are performed for each data area called a "block". In contrast, data write operations and read operations are performed in data units called a "page". A block includes multiple pages. Therefore, the data erasure unit is different from the data write and read units. When data is rewritten in the nonvolatile memory 10, new data is written to a different page. Therefore, as data rewriting progresses, invalid data increases in the block. If even one valid data remains in a block even if invalid data increases, the block erase operation cannot be performed. For example, garbage collection is performed when the number of erasable blocks decreases.

[0015] The padding data insertion process is a process of writing padding data (invalid data) to an unwritten area of ​​a block (also referred to as a "write block") in the middle of writing data. For example, in a write block, there may be a time gap between the previous (most recent) write operation and the next write operation. In the following description, if the elapsed time between the previous (most recent) write operation and the next write operation exceeds a preset reference value, it is expressed as "a time difference has occurred." The data before and after the time difference occurs have different optimal values ​​for the read voltage. For this reason, when data written after the time difference occurs is read, the number of error bits due to erroneous reading increases. In order to suppress the increase in error bits, when a time difference occurs, a write operation of valid data is not performed in the unwritten area of ​​the write block, and a padding data insertion process is performed. In this case, another block is selected in the next write operation.

[0016] In contrast, ZNS-enabled memory systems do not perform garbage collection and do not insert padding data, which limits the increase in invalid data and therefore the increase in write amplification factor (WAF).

[0017] Connection standards that can be used include Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Advanced Technology Attachment (ATA), Serial ATA (SATA), Ethernet (registered trademark), Fibre channel, etc.

[0018] 1.1.2 Memory System Configuration Continuing with reference to FIG. 1, an example of the configuration of the memory system 3 will be described.

[0019] As shown in FIG. 1, the memory system 3 includes a non-volatile memory 10, a volatile memory 20, and a memory controller 30.

[0020] The nonvolatile memory 10 is a nonvolatile storage medium (semiconductor storage device). The nonvolatile memory 10 stores data received from the memory controller 30 in a nonvolatile manner. In the following, a case where the nonvolatile memory 10 is a NAND type flash memory will be described. Note that the nonvolatile memory 10 may be a nonvolatile storage medium other than a NAND type flash memory.

[0021] The volatile memory 20 is a volatile storage medium (semiconductor storage device). In the following, a case where the volatile memory 20 is a dynamic random access memory (DRAM) will be described. Note that the volatile memory 20 may be a volatile storage medium other than a DRAM.

[0022] The memory controller 30 is, for example, a SoC (System on a Chip). The memory controller 30 issues commands to the nonvolatile memory 10 for read operations, write operations, erase operations, etc. based on requests (commands) from the host device 2. The memory controller 30 also manages the memory area of ​​the nonvolatile memory 10.

[0023] Next, an example of the internal configuration of the non-volatile memory 10 will be described. The non-volatile memory 10 may include multiple memory chips 11 (also simply referred to as "chips"). Each of the multiple memory chips 11 may operate independently. The number of memory chips 11 included in the non-volatile memory 10 is arbitrary.

[0024] The memory chip 11 is, for example, a semiconductor chip equipped with a NAND type flash memory. The memory chip 11 may be another nonvolatile memory. The memory chip 11 stores data in a nonvolatile manner. The memory chip 11 is connected to the memory controller 30 via a NAND bus NB.

[0025] The number of NAND buses NB and the number of memory chips 11 connected to one NAND bus NB are arbitrary.

[0026] Next, an example of the internal configuration of the memory controller 30 will be described. The memory controller 30 includes a control circuit 31, a buffer memory 32, a host interface circuit (host I / F) 33, an ECC (Error Checking and Correcting) circuit 34, a NAND interface circuit (NAND I / F) 35, a read voltage correction circuit 36, a RAM interface circuit (RAM I / F) 37, and a time difference timer 38. These circuits are connected to each other, for example, by an internal bus of the memory controller 30. Note that the functions of the host interface circuit 33, the ECC circuit 34, the NAND interface circuit 35, the read voltage correction circuit 36, the RAM interface circuit 37, and the time difference timer 38 may be realized by a dedicated circuit, or may be realized by the control circuit 31 executing firmware.

[0027] The control circuit 31 is a circuit that controls the entire memory controller 30. For example, the control circuit 31 controls the buffer memory 32, the host interface circuit 33, the ECC circuit 34, the NAND interface circuit 35, the read voltage correction circuit 36, the RAM interface circuit 37, and the time difference timer 38. The control circuit 31 includes, for example, a processor such as a CPU (Central Processing Unit) and a ROM (Read Only Memory). For example, the control circuit 31 commands the nonvolatile memory 10 (memory chip 11) to perform a write operation, a read operation, and an erase operation based on a request from the host device 2. The control circuit 31 controls the nonvolatile memory 10.

[0028] The buffer memory 32 is a volatile semiconductor memory. The buffer memory 32 temporarily stores data read by the memory controller 30 from the nonvolatile memory 10, data received from the host device 2, and the like. In addition, for example, the buffer memory 32 stores block management information. Note that the block management information may be stored in the volatile memory 20.

[0029] The block management information is management information for each block included in the memory chip 11. The block management information includes threshold voltage information (hereinafter also referred to as "Vth information") and cell unit group conversion information (hereinafter also referred to as "CU_Gr conversion information"), etc.

[0030] The Vth information is information about a correction amount of a read voltage set for each cell unit group. A cell unit group is a group of multiple cell units included in one block. A cell unit is a collection of multiple memory cell transistors that are selected collectively in a write operation or a read operation. For example, the Vth information is updated based on the result of a patrol process.

[0031] The patrol process is performed periodically or irregularly to read data stored in the non-volatile memory 10 with a small number of error bits. The patrol process includes, for example, a patrol read process and a correction amount calculation process that calculates a correction amount of a read voltage based on the result of the patrol read process. The control circuit 31 may perform the patrol process on each cell unit in the cell unit group, or may perform the patrol process on any cell unit in the cell unit group.

[0032] The CU_Gr conversion information is conversion information of the grouping of cell unit groups in a block. In other words, the CU_Gr conversion information is information regarding a change (movement) of the boundary position between the cell unit groups. For example, the control circuit 31 changes the grouping of the cell unit groups when a time difference occurs in a write operation in a write block. That is, the control circuit 31 changes the position of the boundary line between the cell unit groups. The control circuit 31 registers the changed information as the CU_Gr conversion information.

[0033] The host interface circuit 33 is an interface circuit connected to the host device 2. The host interface circuit 33 controls communication between the host device 2 and the memory controller 30. The host interface circuit 33 transmits requests and data received from the host device 2 to the control circuit 31 and the buffer memory 32, respectively. In addition, the host interface circuit 33 transmits data in the buffer memory 32 to the host device 2 based on the control of the control circuit 31.

[0034] The ECC circuit 34 performs error detection and error correction processes on data stored in the nonvolatile memory 10. That is, when writing data, the ECC circuit 34 adds an error correction code to the write data. When reading data, the ECC circuit 34 decodes the read data and detects the presence or absence of an error bit. When an error bit is detected, the ECC circuit 34 identifies the column address (error position) of the error bit and corrects the error.

[0035] The NAND interface circuit 35 controls communication between the memory controller 30 and the non-volatile memory 10. More specifically, the NAND interface circuit 35 transmits commands corresponding to a write operation, a read operation, an erase operation, or the like to the memory chip 11. Furthermore, the NAND interface circuit 35 receives read data from the memory chip 11 during a read operation. The NAND interface circuit 35 may have multiple channels CH (CH0, CH1, CH2, ...). Multiple memory chips 11 may be connected to each channel CH via a NAND bus NB.

[0036] In this embodiment, one memory chip 11 connected to each channel CH (NAND bus NB) constitutes a bank BK. The multiple memory chips 11 included in the bank BK can operate in parallel.

[0037] The read voltage correction circuit 36 ​​has a function of calculating a correction amount (Vth information) of the read voltage used when reading data from the nonvolatile memory 10.

[0038] The RAM interface circuit 37 manages communication between the volatile memory 20 and the memory controller 30. The bus RB connecting the volatile memory 20 and the memory controller 30 complies with, for example, the DRAM interface standard.

[0039] The time difference timer 38 measures the elapsed time (time difference) from when the last write operation is executed to when the next write operation is executed in each block.

[0040] 1.1.3 Memory chip configuration Next, an example of the configuration of the memory chip 11 will be described with reference to Fig. 2. Fig. 2 is a block diagram showing an example of the configuration of the memory chip 11. Note that in the example of Fig. 2, some of the connections between the components are indicated by arrows. However, the connections between the components are not limited to these.

[0041] 2, the memory chip 11 transmits and receives a signal DQ and timing signals DQS and bDQS to and from the memory controller 30 (more specifically, a NAND interface circuit 35) via the NAND bus NB. The signal DQ is, for example, data DAT, an address ADD, or a command CMD. The timing signals DQS and bDQS are timing signals used when inputting and outputting data DAT. The timing signal bDQS is an inverted signal of the timing signal DQS.

[0042] In addition, the memory chip 11 receives, for example, a chip enable signal bCE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal bWE, and a read enable signal bRE from the memory controller 30 via the NAND bus NB. In addition, the memory chip 11 transmits a ready / busy signal bRB to the memory controller 30 via the NAND bus NB.

[0043] The chip enable signal bCE is a signal for enabling the memory chip 11. The signal bCE is asserted, for example, at a Low ("L") level.

[0044] The command latch enable signal CLE is a signal indicating that the signal DQ is a command. The signal CLE is asserted, for example, at a High ("H") level.

[0045] The address latch enable signal ALE is a signal indicating that the signal DQ is an address, and is asserted, for example, at an “H” level.

[0046] The write enable signal bWE is a signal for taking in the signal DQ when the signal DQ is a command CMD or an address ADD. The signal bWE is asserted, for example, at the “L” level when the memory chip 11 takes in the command CMD or the address ADD. Therefore, the command CMD or the address ADD is taken in by the memory chip 11 every time the signal bWE is toggled.

[0047] The read enable signal bRE is a signal for the memory controller 30 to read data from the memory chip 11. The signal bRE is asserted, for example, at the “L” level. For example, when outputting data, the memory chip 11 generates signals DQS and bDQS based on the signal bRE.

[0048] The ready / busy signal bRB is a signal that indicates whether the memory chip 11 is in a state where it can or cannot receive a command CMD from the memory controller 30. The ready state is a state where the memory chip 11 can receive a command CMD from the memory controller 30. The busy state is a state where the memory chip 11 cannot receive a command CMD from the memory controller 30. For example, the ready / busy signal bRB is set to an “L” level when the memory chip 11 is in a busy state.

[0049] Next, a description will be given of the internal configuration of the memory chip 11. The memory chip 11 includes an input / output circuit 101, a logic control circuit 102, an address register 103, a command register 104, a status register 105, a sequencer 106, a ready / busy circuit 107, a voltage generating circuit 108, and a plurality of planes PLN.

[0050] The input / output circuit 101 is a circuit that inputs and outputs the signal DQ and timing signals DQS and bDQS to and from the memory controller 30. The input / output circuit 101 is connected to the NAND interface circuit 35 of the memory controller 30. The input / output circuit 101 is also connected to a logic control circuit 102, an address register 103, a command register 104, a status register 105, and a data register 112 of each plane PLN.

[0051] The logic control circuit 102 is a circuit that performs logic control of the memory chip 11. The logic control circuit 102 receives, for example, signals bCE, CLE, ALE, bWE, and bRE from the memory controller 30. The logic control circuit 102 is connected to the input / output circuit 101 and the sequencer 106. The logic control circuit 102 controls the input / output circuit 101 and the sequencer 106 based on the received signals.

[0052] The address register 103 is a register that temporarily stores an address ADD. The address register 103 is connected to the input / output circuit 101, and the row decoder 110 and column decoder 113 of each plane PLN. The address ADD includes a row address RA and a column address CA. The address register 103 transmits the row address RA to the row decoder 110. The address register 103 also transmits the column address CA to the column decoder 113.

[0053] The command register 104 is a register that temporarily stores the command CMD. The command register 104 is connected to the input / output circuit 101 and the sequencer 106. The command register 104 transmits the command CMD to the sequencer 106.

[0054] The status register 105 is a register that temporarily stores the status information STS. For example, the status information STS includes information about the results of a write operation, a read operation, an erase operation, and the like. The status register 105 is connected to the sequencer 106. For example, the status information STS is transmitted to the memory controller 30 as an output signal DQ.

[0055] The sequencer 106 is a circuit that controls the operation of the entire memory chip 11. The sequencer 106 is connected to the logic control circuit 102, the address register 103, the command register 104, the status register 105, the ready / busy circuit 107, the voltage generation circuit 108, the row decoder 110 and the sense amplifier 111 of each plane PLN, etc. The sequencer 106 controls the status register 105, the ready / busy circuit 107, the voltage generation circuit 108, the row decoder 110 and the sense amplifier 111 of each plane PLN, etc. The sequencer 106 executes a write operation, a read operation, an erase operation, etc. based on a command CMD.

[0056] The ready / busy circuit 107 is a circuit that generates a ready / busy signal bRB. The ready / busy circuit 107 is connected to the sequencer 106. The ready / busy circuit 107 generates the ready / busy signal bRB under the control of the sequencer 106. The ready / busy circuit 107 transmits the ready / busy signal bRB to the memory controller 30.

[0057] The voltage generation circuit 108 generates various voltages used in a write operation, a read operation, and an erase operation under the control of the sequencer 106. The voltage generation circuit 108 supplies various voltages to a memory cell array 109, a row decoder 110, a sense amplifier 111, etc. of each plane PLN.

[0058] The plane PLN is a unit that performs data write, read, and erase operations. In the example of FIG. 2, the memory chip 11 includes two planes PLN0 and PLN1. The number of planes PLN is not limited to two. The number of planes PLN may be one or more than two. The planes PLN0 and PLN1 can perform write, read, or erase operations independently of each other. The planes PLN0 and PLN1 can also operate in parallel.

[0059] Next, the internal configuration of the plane PLN will be described. In the following, a case where the planes PLN0 and PLN1 have the same configuration will be described. Note that the configurations of the planes PLN may be different. In the following, when there is no limitation to either the planes PLN0 or PLN1, they will be referred to as "plane PLN". The plane PLN includes a memory cell array 109, a row decoder 110, a sense amplifier 111, a data register 112, and a column decoder 113.

[0060] The memory cell array 109 is a set of multiple memory cell transistors arranged in a row. The memory cell array 109 includes multiple blocks BLK. The block BLK is a set of multiple memory cell transistors from which data is erased collectively, for example. In the example of FIG. 2, the memory cell array 109 includes four blocks BLK0, BLK1, BLK2, and BLK3. The number of blocks BLK in the memory cell array 109 is arbitrary.

[0061] The row decoder 110 is a decode circuit for the row address RA. The row decoder 110 is connected to the address register 103, the sequencer 106, the voltage generating circuit 108, and the memory cell array 109. The row decoder 110 selects one of the blocks BLK based on the result of decoding the row address RA. The row decoder 110 applies a voltage to the row-direction wiring (word lines and select gate lines, which will be described later) of the selected block BLK.

[0062] The sense amplifier 111 is a circuit that writes and reads data DAT. The sense amplifier 111 is connected to the sequencer 106, the voltage generating circuit 108, the memory cell array 109, and the data register 112. The sense amplifier 111 reads data DAT from the memory cell array 109 during a read operation. In addition, the sense amplifier 111 supplies a voltage corresponding to the write data DAT to the memory cell array 109 during a write operation.

[0063] The data register 112 is a register that temporarily stores data DAT. The data register 112 is connected to the input / output circuit 101, the sequencer 106, the sense amplifier 111, and the column decoder 113. The data register 112 includes a plurality of latch circuits. Each latch circuit temporarily stores write data or read data.

[0064] The column decoder 113 is a circuit that decodes a column address CA. The column decoder 113 is connected to the address register 103, the sequencer 106, and the data register 112. The column decoder 113 receives the column address CA from the address register 103. The column decoder 113 selects a latch circuit in the data register 112 based on the decoded result of the column address CA.

[0065] 1.1.4 Organization of memory areas in non-volatile memory Next, an example of the configuration of the memory area of ​​the nonvolatile memory when the memory system 3 is a ZNS-compatible memory system will be described with reference to Figures 3 and 4. Figure 3 is a diagram showing an example of the configuration of the memory area of ​​the bank BK. Figure 4 is a diagram showing an example of the configuration of the memory area of ​​the nonvolatile memory 10.

[0066] 3, the memory area of ​​the memory chip 11 includes a plurality of block units BU each consisting of one block BLK of the plane PLN0 and one block BLK of the plane PLN1. Each block BLK of the block units BU can operate in parallel. A bank BK includes a plurality of super blocks SB each consisting of one block unit BU of each memory chip 11. Each block BLK in the super block SB can operate in parallel. If the memory system 3 is, for example, a ZNS-compatible memory system, the super block SB corresponds to a zone.

[0067] For example, if the NAND interface circuit 35 has three channels CH0 to CH2 and each memory chip 11 has two planes PLN, one super block SB includes six blocks BLK. Note that the configuration of the super block SB is not limited to this. For example, the super block SB may be configured by a plurality of blocks BLK that can operate in parallel in a plurality of banks BK.

[0068] When the memory system 3 is a ZNS-compliant memory system, the control circuit 31 divides and manages the memory area of ​​the nonvolatile memory 10 into a plurality of zones ZN (super blocks SB) as shown in Fig. 4. The memory controller 30 executes a write operation, a read operation, and an erase operation for each zone ZN.

[0069] 1.1.5 Memory cell array circuit configuration Next, an example of a circuit configuration of the memory cell array 109 will be described with reference to Fig. 5. Fig. 5 is an example of a circuit diagram showing the configuration of the memory cell array 109. In the example of Fig. 5, one block BLK is extracted and shown from the memory cell array 109.

[0070] As shown in Fig. 5, the block BLK includes a plurality of string units SU. In the example of Fig. 5, the block BLK includes four string units SU0 to SU3. Note that in Fig. 5, the configurations of the string units SU2 and SU3 are shown in a simplified manner.

[0071] Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). The NAND string NS includes, for example, memory cell transistors MC0 to MC15 and select transistors ST1 and ST2.

[0072] The memory cell transistor MC includes a control gate and a charge storage layer, and stores data in a non-volatile manner. Each of the selection transistors ST1 and ST2 is used to select a string unit SU during various processes.

[0073] In each NAND string NS, the memory cell transistors MC0 to MC15 are connected in series. A select transistor ST1 is connected between one end of the series-connected memory cell transistors MC0 to MC15 and the associated bit line BL. The drain of a select transistor ST2 is connected to the other end of the series-connected memory cell transistors MC0 to MC15. A source line SL is connected to the source of the select transistor ST2.

[0074] In the same block BLK, the gates of the select transistors ST1 included in the string units SU0 to SU3 are commonly connected to select gate lines SGD0 to SGD3, respectively. The control gates of the memory cell transistors MC0 to MC15 are commonly connected to word lines WL0 to WL15, respectively. The gates of the select transistors ST2 are commonly connected to a select gate line SGS.

[0075] The bit lines BL0 to BLm are shared among a plurality of blocks BLK. The same bit line BL is connected to the NAND strings NS corresponding to the same column address. Each of the word lines WL0 to WL15 is provided for each block BLK. The source line SL is shared, for example, among a plurality of blocks BLK.

[0076] In the following, a set of multiple memory cell transistors MC connected to a common word line WL in one string unit SU is referred to as a "cell unit CU." The cell unit CU is used as a unit for writing data. For example, the storage capacity of a cell unit CU including memory cell transistors MC each storing one bit of data is defined as "one page of data." One page of data is used, for example, as a unit for reading data. The cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MC.

[0077] The circuit configuration of the memory cell array 109 described above is merely an example, and is not limited thereto. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MC and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0078] In this embodiment, a case where one memory cell transistor MC stores 2-bit data will be described. That is, the memory cell transistor MC in this embodiment is an MLC (Multi Level Cell) that stores 2-bit data. The 2-bit data stored in the MLC memory cell transistor is expressed as a lower bit and an upper bit, starting from the lower bit. A set of lower bits stored in the memory cell transistors MC included in the same cell unit CU is called a "lower page", and a set of upper bits is expressed as an "upper page". Note that the memory cell transistor MC is not limited to an MLC. The memory cell transistor MC may be an SLC (Single Level Cell) that stores 1-bit data, a TLC (Triple Level Cell) that stores 3-bit data, a QLC (Quad Level Cell) that stores 4-bit data, or a PLC (Penta Level Cell) that stores 5-bit data.

[0079] 1.1.6 Threshold distribution of memory cell transistors Next, an example of a threshold voltage distribution of the memory cell transistors MC will be described with reference to Fig. 6. Fig. 6 is a schematic diagram showing an example of a threshold voltage distribution of the memory cell transistors MC in the memory cell array 109.

[0080] As shown in Figure 6, when a memory cell transistor MC stores two bits of data, its threshold voltage distribution is divided into four. These four threshold voltage distributions are denoted as the "Er" state, "A" state, "B" state, and "C" state, in order from the lowest threshold voltage.

[0081] Voltages VA, VB, and VC shown in FIG. 6 are used to distinguish between two adjacent states during a read process. Voltage VREAD is a voltage applied to unselected word lines during a read process. When voltage VREAD is applied to the gate of a memory cell transistor MC, the memory cell transistor MC is turned on regardless of the data to be stored. The relationship between these voltage values ​​is as follows: VA <VB<VC<VREADである。

[0082] In the above-mentioned threshold voltage distribution, the "Er" state corresponds to the erased state of the memory cell transistor MC. The threshold voltage in the "Er" state is less than the voltage VA. The threshold voltage in the "A" state is equal to or greater than the voltage VA and less than the voltage VB. The threshold voltage in the "B" state is equal to or greater than the voltage VB and less than the voltage VC. The threshold voltage in the "C" state is equal to or greater than the voltage VC and less than the voltage VREAD.

[0083] The above-mentioned four threshold voltage distributions are formed by writing two bits (two pages) of data including a lower bit and an upper bit. The four threshold voltage distributions correspond to different two bits of data. In this embodiment, data is assigned to the "upper bit / lower bit" for the memory cell transistors MC included in each state as shown below.

[0084] The memory cell transistor MC in the "Er" state stores "11" data. The memory cell transistor MC in the "A" state stores "01" data. The memory cell transistor MC in the "B" state stores "00" data. The memory cell transistor MC in the "C" state stores "10" data.

[0085] The lower page read uses a voltage VB, which distinguishes between the “A” state and the “B” state, as a read voltage. The read process using the voltage VB is denoted as a read process BR.

[0086] The upper page read uses a voltage VA that distinguishes between the “Er” state and the “A” state, and a voltage VC that distinguishes between the “B” state and the “C” state as read voltages. The read process using the voltage VA is called the read process AR, and the read process using the voltage VC is called the read process CR.

[0087] 1.1.7 Cross-sectional structure of memory cell array Next, an example of a cross-sectional configuration of the memory cell array 109 will be described with reference to FIGS. 7 and 8. FIG. 7 is a cross-sectional view of a NAND string NS, which is a partial region of a block BLK. FIG. 8 is a cross-sectional view of a memory pillar MP taken along line VI-VI in FIG. 7. In the cross-sectional views referred to below, the X-axis corresponds to the extension direction of the word lines WL, the Y-axis corresponds to the extension direction of the bit lines BL, and the Z-axis corresponds to the extension direction of the memory pillar MP with respect to the semiconductor substrate 40. In addition, components such as an insulating layer (interlayer insulating film) are omitted as appropriate to make the drawings easier to see.

[0088] As shown in FIG. 7, a memory pillar MP formed above a semiconductor substrate 40 corresponds to one NAND string NS.

[0089] A conductor layer 41 is provided above the semiconductor substrate 40 via an insulating layer (not shown). Peripheral circuits such as a sense amplifier 111 may be provided on this insulating layer. The conductor layer 41 is formed in a plate shape extending along the XY plane, for example, and is used as a source line SL.

[0090] A conductive layer 42 is provided via an insulating layer (not shown) above the conductive layer 41. The conductive layer 42 is used as a select gate line SGS.

[0091] A plurality of (eight in FIG. 7) insulating layers (not shown) and conductive layers 43 are alternately stacked above the conductive layer 42. The conductive layers 43 are used as word lines WL0 to WL7, in order from the semiconductor substrate 40 side.

[0092] A plurality of insulating layers (not shown) and conductive layers 44 (eight in FIG. 7) are alternately stacked above the uppermost conductive layer 43. The plurality of conductive layers 44 are used as word lines WL8 to WL15, respectively, in order from the semiconductor substrate 40 side. The distance between the uppermost conductive layer 43 and the lowermost conductive layer 44 is, for example, larger than the distance between adjacent conductive layers 43 or the distance between adjacent conductive layers 44.

[0093] A conductive layer 45 is provided above the uppermost conductive layer 44 via an insulating layer (not shown). The conductive layer 45 is used as a select gate line SGD. The conductive layers 42 to 45 are formed in a plate shape extending along, for example, the XY plane.

[0094] A conductive layer 47 is provided above the conductive layer 45 with an insulating layer (not shown) interposed therebetween. The conductive layers 47 extend along the Y-axis, and a plurality of conductive layers 47 are arranged in lines along the X-axis, each of which is used as a bit line BL.

[0095] The memory pillar MP is provided extending along the Z-axis, penetrates the conductive layers 42 to 45, and has a bottom portion in contact with the conductive layer 41. The memory pillar MP includes a lower pillar LMP, an upper pillar UMP formed on the upper portion of the lower pillar LMP, and a joint portion JT that electrically connects the lower pillar LMP and the upper pillar UMP. The lower pillar LMP and the upper pillar UMP have, for example, a tapered shape whose diameter increases (along the Z-axis) from the semiconductor substrate 40 toward the bit line BL. The diameter of the joint portion JT along the XY plane is, for example, larger than the diameters of the lower pillar LMP and the upper pillar UMP at the contact portion with the joint portion JT.

[0096] The memory pillar MP includes, for example, a core film 50, a semiconductor film 51, a laminated film 52, and a semiconductor portion 53. Each of the core film 50, the semiconductor film 51, and the laminated film 52 is formed as a continuous film in, for example, the lower pillar LMP, the joint portion JT, and the upper pillar UMP.

[0097] Specifically, the core film 50 is provided at approximately the center of the memory pillar MP and extends along the Z-axis. The core film 50 has, for example, an upper end located above the conductive layer 45 and a lower end located below the conductive layer 42. The core film 50 includes, for example, an insulator such as silicon oxide (SiO).

[0098] The semiconductor film 51 covers the bottom and side surfaces of the core film 50 and includes a cylindrical portion formed along the Z-axis. The semiconductor film 51 has an upper end located above the conductive layer 45 and a lower end in contact with the conductive layer 41. The semiconductor film 51 includes, for example, polysilicon.

[0099] The laminated film 52 covers the side surface of the semiconductor film 51 and includes a cylindrical portion formed along the Z axis. The structure of the laminated film 52 will be described in detail below.

[0100] 8, the stacked film 52 includes a tunnel insulating film 52a, a charge storage film 52b, and a block insulating film 52c. The tunnel insulating film 52a covers the side surface of the semiconductor film 51, and the charge storage film 52b covers the side surface of the tunnel insulating film 52a. The block insulating film 52c covers the side surface of the charge storage film 52b and is covered by the conductor layer 43.

[0101] 7, the configuration of the memory pillar MP will be described. The semiconductor portion 53 covers the upper surface of the core film 50 and is in contact with the portion of the semiconductor film 51 above the core film 50. The semiconductor portion 53 is, for example, cylindrical, and is located at the upper end of the upper pillar UMP.

[0102] A conductive layer 46 is provided between the upper surface of the semiconductor portion 53 and the lower surface of the conductive layer 47. The conductive layer 46 is used as a contact CP that electrically connects the memory pillar MP and the bit line BL.

[0103] In the structure of the memory pillar MP described above, the portion where the lower pillar LMP intersects with the conductive layer 42 functions as the select transistor ST2. The portions where the lower pillar LMP intersects with the multiple conductive layers 43 function as the memory cell transistors MC0 to MC7. The portions where the upper pillar UMP intersects with the multiple conductive layers 44 function as the memory cell transistors MC8 to MC15. The portion where the upper pillar UMP intersects with the conductive layer 45 functions as the select transistor ST1. The semiconductor film 51 functions as the channels of the memory cell transistor MC and the select transistors ST1 and ST2.

[0104] With the above-described structure, the memory pillar MP can function as a NAND string NS. A memory cell array 109 is formed by arranging a plurality of the memory pillars MP above the semiconductor substrate 40.

[0105] As described with reference to FIG. 7, the memory cell transistors MC0 to MC15 connected in series in the NAND string NS are stacked along the Z axis and may have different shapes depending on their positions (heights) along the Z axis. Therefore, the memory cell transistors MC0 to MC15 may have different electrical characteristics. In addition, both ends of the upper pillar UMP are electrically connected to the bit line BL and the upper ends of the joint part JT, and therefore may have different electrical characteristics from the center of the upper pillar UMP. Both ends of the lower pillar LMP are electrically connected to the source line SL and the lower ends of the joint part JT, and therefore may have different electrical characteristics from the center of the lower pillar LMP.

[0106] 1.1.8 Cell Unit Group Composition Next, an example of the configuration of the cell unit group CU_Gr in a block BLK will be described with reference to Fig. 9. Fig. 9 is a schematic diagram showing an example of the configuration of the cell unit group CU_Gr in one block BLK. One solid-line rectangular frame shown in Fig. 9 corresponds to one cell unit CU. In Fig. 9, 64 cell units CU in one block BLK are shown separately for each set of corresponding string units SU and word lines WL.

[0107] 9, the cell units CU in the block BLK can be classified into several groups by grouping together cell units CU having similar electrical characteristics. For example, the control circuit 31 can classify the cell units CU in the block BLK into several groups and manage the correction amount of the read voltage for each group.

[0108] The 64 cell units CU are classified into, for example, four cell unit groups CU_Gr (CU_Gr0 to CU_Gr3). Specifically, for example, 16 cell units CU located below the lower pillar LMP and connected to the word lines WL0 to WL3 are classified into a cell unit group CU_Gr0. 16 cell units CU located above the lower pillar LMP and connected to the word lines WL4 to WL7 are classified into a cell unit group CU_Gr1. 16 cell units CU located below the upper pillar UMP and connected to the word lines WL8 to WL11 are classified into a cell unit group CU_Gr2. 16 cell units CU located above the upper pillar UMP and connected to the word lines WL12 to WL15 are classified into a cell unit group CU_Gr3. The grouping of the cell unit groups CU_Gr can be set arbitrarily. The number of cell units CU in each cell unit group CU_Gr may be different.

[0109] A boundary 0 is set between the cell unit group CU_Gr0 and the cell unit group CU_Gr1. More specifically, a boundary 0 is set between the cell unit CU corresponding to the set of the string unit SU3 and the word line WL3 and the cell unit CU corresponding to the set of the string unit SU0 and the word line WL4. A boundary 1 is set between the cell unit group CU_Gr1 and the cell unit group CU_Gr2. More specifically, a boundary 1 is set between the cell unit CU corresponding to the set of the string unit SU3 and the word line WL7 and the cell unit CU corresponding to the set of the string unit SU0 and the word line WL8. A boundary 2 is set between the cell unit group CU_Gr2 and the cell unit group CU_Gr3. More specifically, a boundary 2 is set between the cell unit CU corresponding to the set of the string unit SU3 and the word line WL11 and the cell unit CU corresponding to the set of the string unit SU0 and the word line WL12.

[0110] Moreover, one representative cell unit CU (hereinafter also referred to as "anchor AK") is assigned to each of the cell unit groups CU_Gr0 to CU_Gr3. The anchors AK0 to AK3 assigned to the cell unit groups CU_Gr0 to CU_Gr3 are, for example, cell units CU for which patrol processing is executed. The result of the patrol processing for the anchor AK is stored in the Vth information of the block management information as a representative correction amount. That is, the anchor is a cell unit CU used to calculate the correction amount. Note that when the patrol processing is not executed or when the patrol processing is executed for all cell units CU, the anchor AK is not set.

[0111] 9, the anchor AK0 of the cell unit group CU_Gr0 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL0. The anchor AK1 of the cell unit group CU_Gr1 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL4. The anchor AK2 of the cell unit group CU_Gr2 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL8. The anchor AK3 of the cell unit group CU_Gr3 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL12.

[0112] The above-mentioned method of allocating the anchor AK is merely an example, and is not limited thereto. For example, the anchor AK of a certain cell unit group CU_Gr may be allocated to any cell unit CU within the cell unit group CU_Gr. In addition, in the example of FIG. 9, a case in which one block BLK includes four cell unit groups CU_Gr is shown, but this is not limited thereto. For example, one or more cell unit groups CU_Gr may be included in one block BLK.

[0113] In the following description, the configuration of the cell unit group CU_Gr described with reference to Fig. 9 is applied to all blocks BLK, but is not limited to this. For example, the number of cell unit groups in one block BLK and the range and boundary line position of each cell unit group CU_Gr may be different for each block BLK.

[0114] 1.1.9 Block Management Information Next, an example of block management information will be described with reference to Fig. 10 and Fig. 11. Fig. 10 is a table showing an example of the configuration of Vth information. Fig. 11 is a table showing an example of CU_Gr conversion information. Note that the examples of Fig. 10 and Fig. 11 show an example of block BLK0.

[0115] In this embodiment, a case will be described in which the block management information includes a table relating to Vth information and a table relating to CU_Gr conversion information.

[0116] 10, the Vth information includes information on the correction amount of the read voltage in each cell unit group CU_Gr. Specifically, for example, when the memory cell transistor MC is an MLC, the Vth information includes a correction amount ΔVA of the read voltage VA, a correction amount ΔVB of the read voltage VB, and a correction amount ΔVC of the read voltage VC.

[0117] 10, the correction amounts of the cell unit group CU_Gr0 in the block BLK0 include a set of ΔVA0, ΔVB0, and ΔVC0. Similarly, the correction amounts allocated to the cell unit groups CU_Gr1 to CU_Gr3 in the block BLK0 include a set of ΔVA1, ΔVB1, and ΔVC1, a set of ΔVA2, ΔVB2, and ΔVC2, and a set of ΔVA3, ΔVB3, and ΔVC3, respectively.

[0118] With the above configuration, the cell unit group CU_Gr and the correction amounts ΔVA to ΔVC are uniquely associated with each other.

[0119] Next, the CU_Gr conversion information will be described. For example, in one cell unit group CU_Gr, the elapsed time (time difference) from when the previous write operation is performed until the next write operation is performed may exceed a preset reference value. In this case, the control circuit 31 moves (converts) the position of the boundary line of the cell unit group CU_Gr to the cell unit CU where the time difference exceeding the reference value occurs. That is, the configuration of the cell unit group CU_Gr is changed. The CU_Gr conversion information includes position information of the moved boundary line.

[0120] As shown in FIG. 11, the CU_Gr conversion information includes, for example, boundary information indicating the moved boundary line and position information of the boundary line. The example of FIG. 11 shows a case where the number of boundary line movements (i.e., the number of time differences) is allowed up to one in one block BLK. For example, when the number of boundaries included in one block BLK is four or less, the boundary information is indicated by two-bit data. And, for example, when the cell unit group CU_Gr includes 16 cell units CU, the position information is indicated by five-bit data. Therefore, when the time difference is allowed up to one, the increase in data due to the addition of the CU_Gr conversion information is one byte per block BLK. The increase in data differs depending on the number of boundaries and the number of cell units CU included in the cell unit group CU_Gr, etc.

[0121] The example of FIG. 11 shows a case where no time difference (movement of the boundary line) occurs. In this case, the boundary information is set to "00". For example, the boundary position information is set to the amount of movement from the initial state. If no movement occurs, the boundary position information is set to "00000". For example, if the boundary 0 indicating the boundary line between the cell unit group CU_Gr0 and the cell unit group CU_Gr1 moves in the direction of the cell unit group CU_Gr0, it is considered to be a negative amount of movement, and if it moves in the direction of the cell unit group CU_Gr1, it is considered to be a positive amount of movement. For example, if the amount of movement is -16, the position information is set to "10000". For example, if the amount of movement is -1, the boundary position information is set to "11111". For example, if the amount of movement is +15, the boundary position information is set to "01111".

[0122] 1.2 Write operation flow Next, an example of the flow of a write operation will be described with reference to Fig. 12. Fig. 12 is a flowchart showing an example of the flow of a write operation.

[0123] As shown in FIG. 12, first, the memory system 3 receives a write request from the host device 2 (S10).

[0124] The control circuit 31 checks whether the data write destination is the first page of the block BLK to be written (S11). More specifically, the control circuit 31 checks whether the lower page of the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL0 is selected as the write destination.

[0125] If the data write destination is not the first page of the block BLK (S11_No), the control circuit 31 stops the time difference timer 38 (S12). More specifically, the time difference timer 38 measures the elapsed time from when a write operation is performed on a cell unit CU in the block BLK to be written to until when a write operation is performed on the next cell unit CU to be written to. When the write operation on each cell unit CU is performed in multiple steps, the time difference timer 38 measures the elapsed time from when the last step of the write operation on a cell unit CU in the block BLK to be written to until when the last step of the write operation on the next cell unit CU to be written to is performed. After completing the measurement, the time difference timer 38 transmits the elapsed time in the block BLK to the control circuit 31 as a "time difference."

[0126] The control circuit 31 checks whether the time difference exceeds the reference value (S13). If the time difference exceeds the reference value (S13_Yes), the control circuit 31 sets a time difference occurrence flag (S14). That is, the control circuit 31 sets the time difference occurrence flag to the “H” level.

[0127] After setting the time difference occurrence flag (S14), if the data is to be written to the first page of the block BLK (S11_Yes) or if the time difference is less than or equal to the reference value (S13_No), the control circuit 31 causes the memory chip 11 to which the data is to be written to execute a write operation (S15).

[0128] After the write operation is completed, the control circuit 31 checks whether the data write destination is the last page of the block BLK to be written (S16).

[0129] If the data write destination is not the last page of the block BLK (S16_No), the control circuit 31 resets the time difference timer 38 once and then starts it (S17). More specifically, the time difference timer 38 starts measuring the elapsed time from the end of the write operation to the cell unit CU of the block BLK. If the write operation to each cell unit CU is executed in multiple steps, the time difference timer 38 starts measuring the elapsed time from the end of the last step of the write operation to the cell unit CU of the block BLK.

[0130] After the time difference timer is started (S17), or if the data write destination is the last page of the block BLK (S16_Yes), the control circuit 31 ends the write operation.

[0131] 1.3 Flow of registering CU_Gr conversion information Next, an example of the flow of registering CU_Gr conversion information will be described with reference to Fig. 13. Fig. 13 is a flowchart showing an example of the flow of registering CU_Gr conversion information.

[0132] As shown in FIG. 13, first, the control circuit 31 checks whether or not a time difference occurrence flag is set (S100).

[0133] If there is no time difference occurrence flag (S101_No), the control circuit 31 ends the registration of the CU_Gr conversion information.

[0134] If the time difference occurrence flag is present (set) (S101_Yes), the control circuit 31 checks whether the number of occurrences of the time difference occurrence flag (time difference) in one block BLK is equal to or less than a preset value N (N is an integer that is greater than or equal to 0 and less than or equal to (total number of cell unit groups in block BLK-1)) (S102). For example, if one time difference occurrence (movement of boundary line) is permitted per block BLK, the setting value is set to N=1. Since the number of boundaries is the total number of cell unit groups-1, the maximum value of the setting value N is the total number of cell unit groups-1. In other words, it is a value obtained by subtracting 1 from the total number of cell unit groups CU_Gr. In this case, movement of all boundary lines is permitted.

[0135] If the number of occurrences is equal to or less than the set value N (S102_Yes), the control circuit 31 acquires information on the boundary line to be changed (S103) and checks whether the acquisition was successful (S104). For example, there are two ways to change the boundary line.

[0136] In the first method, the address range to which each boundary line corresponds when a time difference occurs is determined in advance. In the configuration of the cell unit group CU_Gr described with reference to FIG. 9, if a time difference occurs between the cell unit CU corresponding to the set of the string unit SU0 and the word line WL0 and the cell unit CU corresponding to the set of the string unit SU3 and the word line WL4, the control circuit 31 moves the boundary 0. If a time difference occurs between the cell unit CU corresponding to the set of the string unit SU0 and the word line WL5 and the cell unit CU corresponding to the set of the string unit SU3 and the word line WL9, the control circuit 31 moves the boundary 1. If a time difference occurs between the cell unit CU corresponding to the set of the string unit SU0 and the word line WL10 and the cell unit CU corresponding to the set of the string unit SU3 and the word line WL15, the control circuit 31 moves the boundary 2. For example, the changed boundary line is set as boundary k using a variable k (k is an integer that is 0 or more and (the total number of cell unit groups in the block BLK-1) or less). For example, the address range after the boundary k is moved corresponds to the next boundary (k+1). If there is no boundary that can accommodate the time difference occurrence, the control circuit 31 determines that the acquisition has failed.

[0137] In the second method, when a time difference occurs, the location where the time difference occurs is set as the boundary between the cell unit group CU_Gr to which the previous write destination address belongs and the next cell unit group CU_Gr. When a time difference occurs in the last cell unit group CU_Gr (cell unit group CU_Gr3 in the example of FIG. 9), the control circuit 31 determines that the acquisition has failed.

[0138] If the acquisition is successful (S104_Yes), the control circuit 31 updates the position of the boundary line (S105). For example, the control circuit 31 moves the boundary line to a position between the previous write destination address (the corresponding cell unit CU) and the next write destination address (the corresponding cell unit CU).

[0139] The control circuit 31 registers information about the moved boundary line in the CU_Gr conversion information (S106).

[0140] If the occurrence count exceeds the set value N (S102_No) or if the acquisition fails (S104_No), the control circuit 31 sets the block movement flag (S107). That is, the control circuit 31 sets the block movement flag to the “H” level. The block movement flag is a flag that preferentially selects the block BLK as a target for data movement after the write operation to all cell units CU in the block BLK is completed. For example, the control circuit 31 checks the block movement flag when the write operation to all cell units CU in the block BLK is completed. If the block movement flag is set, the control circuit 31 selects the block BLK as a target for data movement. Then, the control circuit 31 reads out valid data from the block BLK, and writes it to another block BLK after the ECC circuit 34 performs error correction processing.

[0141] 1.4 Specific examples of boundary line movement Next, two concrete examples of moving the boundary line are shown.

[0142] 1.4.1 First concrete example First, a first specific example will be described. In the first specific example, N=1, that is, the number of boundary line movements (i.e., the number of time differences) allowed in one block BLK is one. Fig. 14 is a schematic diagram showing a first specific example of boundary line movement in one block BLK. Fig. 15 is a table showing an example of CU_Gr conversion information in the first specific example.

[0143] 14, in this example, a time difference occurs between the cell unit CU corresponding to the set of string unit SU2 and word line WL6 and the cell unit CU corresponding to the set of string unit SU3 and word line WL6. In other words, the elapsed time from when a write operation is performed on the cell unit CU corresponding to the set of string unit SU2 and word line WL6 until when a write operation is performed on the cell unit CU corresponding to the set of string unit SU3 and word line WL6 exceeds a preset reference value. Therefore, the control circuit 31 moves the boundary 1 between these two cell units CU. In this case, the movement amount of the boundary 1 is -5.

[0144] As a result, the cell unit group CU_Gr0 includes the cell unit CU corresponding to the pair of string unit SU0 and word line WL0 through the cell unit CU corresponding to the pair of string unit SU3 and word line WL3. The cell unit group CU_Gr1 includes the cell unit CU corresponding to the pair of string unit SU0 and word line WL4 through the cell unit CU corresponding to the pair of string unit SU2 and word line WL6. The cell unit group CU_Gr2 includes the cell unit CU corresponding to the pair of string unit SU3 and word line WL6 through the cell unit CU corresponding to the pair of string unit SU3 and word line WL11. The cell unit group CU_Gr3 includes the cell unit CU corresponding to the pair of string unit SU0 and word line WL12 through the cell unit CU corresponding to the pair of string unit SU3 and word line WL15.

[0145] 15, boundary information "01" and position information "11011" are registered as CU_Gr conversion information. The boundary information "01" indicates boundary 1. The position information "11011" indicates that the amount of movement is -5.

[0146] 1.4.2 Second Example Next, a second specific example will be described. In the second specific example, N=(total number of cell unit groups-1), that is, the number of times that boundary lines are moved (i.e., the number of times that time differences occur) in one block BLK is allowed up to the total number of boundary lines. In other words, a case in which the control circuit 31 moves all boundary lines will be described. Fig. 16 is a schematic diagram showing a second specific example of boundary line movement in one block BLK. Fig. 17 is a table showing an example of Vth information and CU_Gr conversion information in the second specific example.

[0147] As shown in Fig. 16, in this example, the control circuit 31 moves each of boundary 0 to boundary 2. More specifically, a time difference occurs between the cell unit CU corresponding to the set of string unit SU1 and word line WL2, and the cell unit CU corresponding to the set of string unit SU2 and word line WL2. For this reason, the control circuit 31 moves boundary 0 between these two cell units CU. The amount of movement of boundary 0 is -6.

[0148] A time difference occurs between the cell unit CU corresponding to the set of string unit SU2 and word line WL6 and the cell unit CU corresponding to the set of string unit SU3 and word line WL6. Therefore, the control circuit 31 moves the boundary 1 between these two cell units CU. The movement amount of the boundary 1 is -5.

[0149] A time difference occurs between the cell unit CU corresponding to the set of string unit SU0 and word line WL9 and the cell unit CU corresponding to the set of string unit SU1 and word line WL9. Therefore, the control circuit 31 moves the boundary 2 between these two cell units CU. The amount of movement of the boundary 2 is -11.

[0150] As a result, the cell unit group CU_Gr0 includes the cell unit CU corresponding to the pair of string unit SU0 and word line WL0 through the cell unit CU corresponding to the pair of string unit SU1 and word line WL2. The cell unit group CU_Gr1 includes the cell unit CU corresponding to the pair of string unit SU2 and word line WL2 through the cell unit CU corresponding to the pair of string unit SU2 and word line WL6. The cell unit group CU_Gr2 includes the cell unit CU corresponding to the pair of string unit SU3 and word line WL6 through the cell unit CU corresponding to the pair of string unit SU0 and word line WL9. The cell unit group CU_Gr3 includes the cell unit CU corresponding to the pair of string unit SU1 and word line WL9 through the cell unit CU corresponding to the pair of string unit SU3 and word line WL15.

[0151] As shown in FIG. 17, for example, in the block management information, Vth information and CU_Gr conversion information may be managed in one table. In this case, the CU_Gr conversion information includes boundary line position information corresponding to the cell unit group CU_Gr. For example, the boundary line position information is indicated by 7-bit data (-64≦movement amount≦+63). For example, when the occurrence of time difference is allowed up to three times, the increase in data amount due to the addition of CU_Gr conversion information is 3 bytes per block BLK.

[0152] For example, the position information of the boundary line is set to the amount of movement from the initial state. If no movement has occurred, the position information of the boundary line is set to "0000000". For example, if the amount of movement of the boundary line is -64, the position information of the boundary line is set to "1000000". For example, if the amount of movement of the boundary line is -1, the position information of the boundary line is set to "1111111". For example, if the amount of movement of the boundary line is +63, the position information of the boundary line is set to "0111111". In the example of FIG. 17, "1111010" is registered as the CU_Gr conversion information of boundary 0. "1111010" indicates that the amount of movement is -6. "1111011" is registered as the CU_Gr conversion information of boundary 1. "1111011" indicates that the amount of movement is -5. "1110101" is registered as the CU_Gr conversion information of boundary 2. "1110101" indicates that the amount of movement is -11.

[0153] 1.5 Effects of this embodiment The configuration according to this embodiment makes it possible to improve the processing capacity of the memory system.

[0154] For example, in the case of a ZNS-compatible memory system, even if a time difference occurs in a block BLK during a write operation, the padding data insertion process is not executed. The write operation of valid data continues in the block BLK. Since the optimal value of the read voltage differs before and after the time difference occurs, the number of error bits increases in the cell unit group CU_Gr in which the time difference occurs. This reduces the reliability of data. In addition, the frequency of execution of processes to reduce error bits, such as refresh read or retry read, increases in order to correct errors. A retry read is an operation to shift the read voltage and perform a read operation again. A refresh read is a process to rewrite data to another memory area. This reduces the processing capacity of the memory system.

[0155] In addition, in the case of a memory system that does not support ZNS, when a time difference occurs, padding data is inserted into the cell units CU in the block to which data has not been written. This increases the amount of invalid data and the WAF. In addition, the padding data insertion process reduces the processing power of the memory system.

[0156] In contrast, with the configuration according to this embodiment, when a time difference occurs, the configuration of the cell unit group CU_Gr in the block BLK can be dynamically changed. The boundary line of the cell unit group CU_Gr can be moved to the location where the time difference occurs. Even if the optimal value of the read voltage differs before and after the occurrence of the time difference, the optimal value of the read voltage can be set for each cell unit group CU_Gr, so that an increase in error bits can be suppressed. Therefore, a decrease in the reliability of data can be suppressed. Therefore, the reliability of the memory system 3 can be improved. In addition, since the frequency of executing processing to reduce error bits can be reduced, the processing capacity of the memory system 3 can be improved.

[0157] 1.6 Modification of the first embodiment Next, a modified example of the first embodiment will be described. In this modified example, a case where an anchor AK is not set will be described. Below, the differences from the first embodiment will be mainly described.

[0158] 1.6.1 Cell Unit Group Composition First, the configuration of the cell unit group CU_Gr in the block BLK will be described with reference to Fig. 18. Fig. 18 is a schematic diagram showing the configuration of the cell unit group CU_Gr in one block BLK.

[0159] As shown in FIG. 18, the initial configuration of the cell unit group CU_Gr is the same as that described in FIG. 9 of the first embodiment, except that the anchor AK is not set.

[0160] 1.6.2 Specific examples of boundary line movement Next, two concrete examples of moving the boundary line are shown.

[0161] 1.6.2.1 First concrete example First, a first specific example will be described. In the first specific example, N=1, that is, the number of times the boundary line moves in one block BLK (i.e., the number of times the time difference occurs) is allowed to be up to one time will be described. Fig. 19 is a schematic diagram showing a first specific example of the boundary line movement in one block BLK.

[0162] 19, in this example, as in the first specific example of the first embodiment, a time difference occurs between the cell unit CU corresponding to the set of the string unit SU2 and the word line WL6 and the cell unit CU corresponding to the set of the string unit SU3 and the word line WL6. Therefore, the control circuit 31 moves the boundary 1 between these two cell units CU. The amount of movement of the boundary 1 in this case is -5.

[0163] The configuration of each cell unit group CU_Gr is the same as that explained with reference to FIG.

[0164] 1.6.2.2 Second Example Next, a second specific example will be described. In the second specific example, N=(total number of cell unit groups-1), that is, the number of times that the boundary line is moved (i.e., the number of times that a time difference occurs) in one block BLK is allowed up to the total number of boundary lines. In other words, the case where the control circuit 31 moves all the boundary lines will be described. Figure 20 is a schematic diagram showing a second specific example of boundary line movement in one block BLK.

[0165] 20, in this example, similar to the second specific example of the first embodiment, the control circuit 31 moves each of boundary 0 to boundary 2. More specifically, a time difference occurs between the cell unit CU corresponding to the set of string unit SU1 and word line WL2, and the cell unit CU corresponding to the set of string unit SU2 and word line WL2. For this reason, the control circuit 31 moves boundary 0 between these two cell units CU. The amount of movement of boundary 0 is -6.

[0166] A time difference occurs between the cell unit CU corresponding to the set of string unit SU2 and word line WL6 and the cell unit CU corresponding to the set of string unit SU3 and word line WL6. Therefore, the control circuit 31 moves the boundary 1 between these two cell units CU. The movement amount of the boundary 1 is -5.

[0167] A time difference occurs between the cell unit CU corresponding to the set of string unit SU0 and word line WL9 and the cell unit CU corresponding to the set of string unit SU1 and word line WL9. Therefore, the control circuit 31 moves the boundary 2 between these two cell units CU. The amount of movement of the boundary 2 is -11.

[0168] The configuration of each cell unit group CU_Gr is the same as that explained with reference to FIG.

[0169] 1.6.3 Effects of this modification With the configuration according to this modification, the same effects as those of the first embodiment can be obtained.

[0170] 2. Second embodiment Next, a second embodiment will be described. In the second embodiment, a case in which a boundary line and an anchor AK are moved will be described. Below, the differences from the first embodiment will be mainly described.

[0171] 2.1 CU_Gr conversion information and anchor conversion information First, an example of the CU_Gr conversion information and the anchor conversion information will be described with reference to Fig. 21. Fig. 21 is a table showing an example of the CU_Gr conversion information and the anchor conversion information. The CU_Gr conversion information and the anchor conversion information are included in the block management information.

[0172] As shown in FIG. 21, the CU_Gr conversion information includes boundary information indicating the moved boundary line and position information of the boundary line, similar to the description of FIG. 11 in the first embodiment.

[0173] The anchor conversion information is change information of the cell unit CU set as the anchor AK. The anchor conversion information includes anchor information indicating the moved anchor AK and position information of the anchor AK. For example, when the number of anchors included in one block BLK is four or less, the anchor information is indicated by two-bit data. And, for example, the position information of the anchor AK is indicated by five-bit data, similar to the position information of the boundary line. For example, when the occurrence of a time difference is allowed up to one time, the increase in data due to the addition of the anchor conversion information is one byte per block BLK. In this case, the increase in data due to the CU_Gr conversion information and the anchor conversion information is two bytes per block BLK.

[0174] The example of FIG. 21 shows a case where no time difference (movement of the boundary line) has occurred. The boundary information is set to "00". The boundary line position information is set to "00000". The anchor information is set to "00". The anchor position information is set to "00000". For example, if the movement amount of the anchor AK is -16, the anchor position information is set to "10000". For example, if the movement amount of the anchor AK is -1, the anchor position information is set to "11111". For example, if the movement amount of the anchor AK is +15, the anchor position information is set to "01111".

[0175] 2.2 Flow of registration of CU_Gr conversion information and anchor conversion information Next, an example of the flow of registering CU_Gr conversion information and anchor conversion information will be described with reference to Fig. 22. Fig. 22 is a flowchart showing an example of the flow of registering CU_Gr conversion information and anchor conversion information.

[0176] As shown in FIG. 22, the flow of steps S100 to S107 is similar to that explained using FIG. 13 in the first embodiment.

[0177] After registering the CU_Gr conversion information (S106), the control circuit 31 checks whether the anchor AK is included in the changed cell unit group CU_Gr (S108).

[0178] If the anchor AK is not included (S108_No), the control circuit 31 acquires information on the anchor AK to be changed (S109). For example, the control circuit 31 selects an anchor AK included in the cell unit group CU_Gr to which the previous write destination address (cell unit CU) belongs as a target. More specifically, for example, in a state in which two anchor AKs are included in the cell unit group CU_Gr to which the previous write destination address (cell unit CU) belongs, the anchor AK located near the moved boundary line is selected as a target for movement. On the other hand, if the anchor AK is included (S108_Yes), the control circuit 31 ends the registration.

[0179] The control circuit 31 updates the position information of the anchor AK selected as the change target (S110). The control circuit 31 sets one of the cell units CU included in the cell unit group CU_Gr to which the next write destination address (cell unit CU) belongs as the anchor AK.

[0180] The control circuit 31 registers the information of the moved anchor AK in the anchor conversion information (S111).

[0181] 2.3 Examples of boundary and anchor movement Next, four specific examples of moving the boundary line and the anchor AK will be shown.

[0182] 2.3.1 First concrete example First, a first specific example will be described. In the first specific example, N=1, that is, the number of boundary line movements (i.e., the number of time differences) allowed in one block BLK is one. Fig. 23 is a schematic diagram showing a first specific example of boundary line and anchor AK movements in one block BLK. Fig. 24 is a table showing an example of CU_Gr conversion information and anchor conversion information in the first specific example.

[0183] 23, in this example, a time difference occurs between the cell unit CU corresponding to the set of string unit SU1 and word line WL9 and the cell unit CU corresponding to the set of string unit SU2 and word line WL9. Therefore, the control circuit 31 moves the boundary 1 between these two cell units CU. In this case, the movement amount of the boundary 1 is +6.

[0184] Due to the movement of the boundary 1, the anchor AK2 is included in the cell unit group CU_Gr1. Therefore, the anchor AK2 is selected as a target for movement. For example, a cell unit CU corresponding to a pair of the string unit SU3 and the word line WL10 in the cell unit group CU_Gr2 is assigned as a new anchor AK2. That is, the control circuit 31 moves the anchor AK2 from the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL8 to the cell unit CU corresponding to the pair of the string unit SU3 and the word line WL10. The movement amount of the anchor AK2 in this case is +11. The cell unit CU selected as the anchor AK2 may be any cell unit CU in the cell unit group CU_Gr2.

[0185] As a result, the cell unit group CU_Gr0 includes the cell unit CU corresponding to the pair of string unit SU0 and word line WL0 through the cell unit CU corresponding to the pair of string unit SU3 and word line WL3. The cell unit group CU_Gr1 includes the cell unit CU corresponding to the pair of string unit SU0 and word line WL4 through the cell unit CU corresponding to the pair of string unit SU1 and word line WL9. The cell unit group CU_Gr2 includes the cell unit CU corresponding to the pair of string unit SU2 and word line WL9 through the cell unit CU corresponding to the pair of string unit SU3 and word line WL11. The cell unit group CU_Gr3 includes the cell unit CU corresponding to the pair of string unit SU0 and word line WL12 through the cell unit CU corresponding to the pair of string unit SU3 and word line WL15.

[0186] For example, the anchor AK0 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL0. For example, the anchor AK1 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL4. For example, the anchor AK2 is assigned a cell unit CU corresponding to the set of the string unit SU3 and the word line WL10. For example, the anchor AK3 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL12.

[0187] As shown in FIG. 24, boundary information "01" and position information "00110" are registered as CU_Gr conversion information. Boundary information "01" indicates boundary 1. Boundary line position information "00110" indicates that the amount of movement is +6. Anchor information "10" and anchor position information "01011" are registered as anchor conversion information. Anchor information "10" indicates anchor AK2. Anchor position information "01011" indicates that the amount of movement is +11.

[0188] 2.3.2 Second Example Next, a second specific example will be described. In the second specific example, N=(total number of cell unit groups-1), that is, the number of boundary line movements (i.e., the number of time differences) in one block BLK is allowed up to the total number of boundary lines. Figure 25 is a schematic diagram showing a second specific example of boundary line and anchor AK movement in one block BLK. Figure 26 is a table showing an example of Vth information, CU_Gr conversion information, and anchor conversion information in the second specific example.

[0189] 25, in this example, the control circuit 31 moves each of the boundaries 0 to 2. In conjunction with this, the control circuit 31 moves the anchor AK3.

[0190] More specifically, a time difference occurs between the cell unit CU corresponding to the set of the string unit SU1 and the word line WL2 and the cell unit CU corresponding to the set of the string unit SU2 and the word line WL2. Therefore, the control circuit 31 shifts the boundary 0 between these two cell units CU. The shift amount of the boundary 0 is -6.

[0191] A time difference occurs between the cell unit CU corresponding to the set of string unit SU2 and word line WL6 and the cell unit CU corresponding to the set of string unit SU3 and word line WL6. Therefore, the control circuit 31 moves the boundary 1 between these two cell units CU. The movement amount of the boundary 1 is -5.

[0192] There is a time difference between the cell unit CU corresponding to the pair of string unit SU1 and word line WL12 and the cell unit CU corresponding to the pair of string unit SU2 and word line WL12. Therefore, the control circuit 31 moves the boundary 2 between these two cell units CU. The movement amount of the boundary 2 is +2.

[0193] The control circuit 31 moves the anchor AK3 from the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL12 to the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL14. The amount of movement of the anchor AK3 is +8.

[0194] As a result, the cell unit group CU_Gr0 includes the cell unit CU corresponding to the pair of string unit SU0 and word line WL0 through the cell unit CU corresponding to the pair of string unit SU1 and word line WL2. The cell unit group CU_Gr1 includes the cell unit CU corresponding to the pair of string unit SU2 and word line WL2 through the cell unit CU corresponding to the pair of string unit SU2 and word line WL6. The cell unit group CU_Gr2 includes the cell unit CU corresponding to the pair of string unit SU3 and word line WL6 through the cell unit CU corresponding to the pair of string unit SU1 and word line WL12. The cell unit group CU_Gr3 includes the cell unit CU corresponding to the pair of string unit SU2 and word line WL12 through the cell unit CU corresponding to the pair of string unit SU3 and word line WL15.

[0195] For example, the anchor AK0 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL0. For example, the anchor AK1 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL4. For example, the anchor AK2 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL8. For example, the anchor AK3 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL14.

[0196] As shown in FIG. 26, for example, in the block management information, Vth information, CU_Gr conversion information, and anchor conversion information may be managed in one table. In this case, the anchor conversion information includes the position information of the anchor AK included in the cell unit group CU_Gr. The CU_Gr conversion information includes the position information of the boundary line corresponding to the cell unit group CU_Gr. For example, the anchor position information and the boundary line position information are indicated by 7-bit data (-64≦movement amount≦+63). Therefore, for example, when the occurrence of time difference is allowed up to three times, the increase in the amount of data due to the addition of CU_Gr conversion information is a maximum of 6 bytes per block BLK. Note that data may be omitted for the anchor AK and boundary line that are not moved. For this reason, the example of FIG. 26 shows the addition of 4 bytes of data.

[0197] For example, the position information of the anchor AK and the boundary line is set to the amount of movement from the initial state. If no movement has occurred, the position information is set to "0000000". For example, if the amount of movement is -64, the position information is set to "1000000". For example, if the amount of movement is -1, the position information is set to "1111111". For example, if the amount of movement is +63, the position information of the boundary line is set to "0111111".

[0198] 26, "0001000" is registered as the conversion information of the anchor AK3 included in the cell unit group CU_Gr3 in the anchor conversion information. "0001000" indicates that the movement amount of the anchor AK3 is +8.

[0199] In the CU_Gr conversion information, "1111010" is registered as the CU_Gr conversion information for boundary 0. "1111010" indicates that the movement amount of boundary 0 is -6. "1111011" is registered as the CU_Gr conversion information for boundary 1. "1111011" indicates that the movement amount of boundary 1 is -5. "0000010" is registered as the CU_Gr conversion information for boundary 2. "0000010" indicates that the movement amount of boundary 2 is +2.

[0200] 2.3.3 Third Example Next, a third specific example will be described. In the third specific example, a case will be described in which the boundary lines are concentrated between cell units CU corresponding to the word line WL0. In the third specific example, as in the second specific example of the second embodiment, the number of boundary line movements (i.e., the number of time differences) in one block BLK is allowed up to the total number of boundary lines. FIG. 27 is a schematic diagram showing a third specific example of boundary line and anchor AK movements in one block BLK. FIG. 28 is a table showing an example of Vth information, CU_Gr conversion information, and anchor conversion information in the third specific example.

[0201] 27, in this example, the control circuit 31 moves each of the boundaries 0 to 2. Accordingly, the control circuit 31 moves the anchors AK1 and AK2.

[0202] More specifically, a time difference occurs between the cell unit CU corresponding to the set of string unit SU0 and word line WL0 and the cell unit CU corresponding to the set of string unit SU1 and word line WL0. Therefore, the control circuit 31 shifts the boundary 0 between these two cell units CU. The shift amount of the boundary 0 is -15.

[0203] There is a time difference between the cell unit CU corresponding to the set of string unit SU1 and word line WL0 and the cell unit CU corresponding to the set of string unit SU2 and word line WL0. Therefore, the control circuit 31 moves the boundary 1 between these two cell units CU. The movement amount of the boundary 1 is -30.

[0204] There is a time difference between the cell unit CU corresponding to the set of string unit SU2 and word line WL0 and the cell unit CU corresponding to the set of string unit SU3 and word line WL0. Therefore, the control circuit 31 moves the boundary 2 between these two cell units CU. The movement amount of the boundary 2 is -45.

[0205] The control circuit 31 moves the anchor AK1 from the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL4 to the cell unit CU corresponding to the pair of the string unit SU1 and the word line WL0. The movement amount of the anchor AK1 is -15. The control circuit 31 moves the anchor AK2 from the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL8 to the cell unit CU corresponding to the pair of the string unit SU2 and the word line WL0. The movement amount of the anchor AK1 is -30.

[0206] As a result, the cell unit CU corresponding to the pair of string unit SU0 and word line WL0 belongs to the cell unit group CU_Gr0. The cell unit CU corresponding to the pair of string unit SU1 and word line WL0 belongs to the cell unit group CU_Gr1. The cell unit CU corresponding to the pair of string unit SU2 and word line WL0 belongs to the cell unit group CU_Gr2. And the cell unit CU corresponding to the pair of string unit SU3 and word line WL0 to the pair of string unit SU3 and word line WL15 belong to the cell unit group CU_Gr3.

[0207] For example, the anchor AK0 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL0. For example, the anchor AK1 is assigned a cell unit CU corresponding to the set of the string unit SU1 and the word line WL0. For example, the anchor AK2 is assigned a cell unit CU corresponding to the set of the string unit SU2 and the word line WL0. For example, the anchor AK3 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL12.

[0208] 28, in the anchor conversion information, "1110001" is registered as the conversion information of anchor AK1 included in cell unit group CU_Gr1. "1110001" indicates that the movement amount of anchor AK1 is -15. "1110010" is registered as the conversion information of anchor AK2 included in cell unit group CU_Gr2. "1110010" indicates that the movement amount of anchor AK2 is -30.

[0209] In the CU_Gr conversion information, "1110001" is registered as the CU_Gr conversion information for boundary 0. "1110001" indicates that the movement amount of boundary 0 is -15. "1110010" is registered as the CU_Gr conversion information for boundary 1. "1110010" indicates that the movement amount of boundary 1 is -30. "1010011" is registered as the CU_Gr conversion information for boundary 2. "1010011" indicates that the movement amount of boundary 2 is -45.

[0210] 2.3.4 Fourth Example Next, a fourth specific example will be described. In the fourth specific example, a case will be described in which the boundary lines are concentrated between cell units CU corresponding to the word line WL15. In the fourth specific example, similarly to the second and third specific examples of the second embodiment, the number of boundary line movements (i.e., the number of time differences) in one block BLK is allowed up to the total number of boundary lines. FIG. 29 is a schematic diagram showing a fourth specific example of boundary line and anchor AK movements in one block BLK. FIG. 30 is a table showing an example of Vth information, CU_Gr conversion information, and anchor conversion information in the fourth specific example.

[0211] 29, in this example, the control circuit 31 moves each of the boundaries 0 to 2. Accordingly, the control circuit 31 moves the anchors AK1 to AK3.

[0212] More specifically, a time difference occurs between the cell unit CU corresponding to the set of string unit SU0 and word line WL15 and the cell unit CU corresponding to the set of string unit SU1 and word line WL15. Therefore, the control circuit 31 moves the boundary 0 between these two cell units CU. The amount of movement of the boundary 0 is +45.

[0213] There is a time difference between the cell unit CU corresponding to the set of string unit SU1 and word line WL15 and the cell unit CU corresponding to the set of string unit SU2 and word line WL15. Therefore, the control circuit 31 moves the boundary 1 between these two cell units CU. The movement amount of the boundary 1 is +30.

[0214] There is a time difference between the cell unit CU corresponding to the set of string unit SU2 and word line WL15 and the cell unit CU corresponding to the set of string unit SU3 and word line WL15. Therefore, the control circuit 31 moves the boundary 2 between these two cell units CU. The amount of movement of the boundary 2 is +15.

[0215] The control circuit 31 moves the anchor AK1 from the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL4 to the cell unit CU corresponding to the pair of the string unit SU1 and the word line WL15. The movement amount of the anchor AK1 is +45. The control circuit 31 moves the anchor AK2 from the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL8 to the cell unit CU corresponding to the pair of the string unit SU2 and the word line WL15. The movement amount of the anchor AK1 is +30. The control circuit 31 moves the anchor AK3 from the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL12 to the cell unit CU corresponding to the pair of the string unit SU3 and the word line WL15. The movement amount of the anchor AK3 is +15.

[0216] As a result, the cell unit group CU_Gr0 includes the cell unit CU corresponding to the pair of string unit SU0 and word line WL0 to the cell unit CU corresponding to the pair of string unit SU0 and word line WL15. The cell unit group CU_Gr1 includes the cell unit CU corresponding to the pair of string unit SU1 and word line WL15. The cell unit group CU_Gr2 includes the cell unit CU corresponding to the pair of string unit SU2 and word line WL15. And the cell unit group CU_Gr3 includes the cell unit CU corresponding to the pair of string unit SU3 and word line WL15.

[0217] For example, the anchor AK0 is assigned a cell unit CU corresponding to the set of the string unit SU0 and the word line WL0. For example, the anchor AK1 is assigned a cell unit CU corresponding to the set of the string unit SU1 and the word line WL15. For example, the anchor AK2 is assigned a cell unit CU corresponding to the set of the string unit SU2 and the word line WL15. For example, the anchor AK3 is assigned a cell unit CU corresponding to the set of the string unit SU3 and the word line WL15.

[0218] As shown in Fig. 30, in the anchor conversion information, "0101101" is registered as the conversion information of anchor AK1 included in cell unit group CU_Gr1. "0101101" indicates that the movement amount of anchor AK1 is +45. "0011110" is registered as the conversion information of anchor AK2 included in cell unit group CU_Gr2. "0011110" indicates that the movement amount of anchor AK2 is +30. "0001111" is registered as the conversion information of anchor AK3 included in cell unit group CU_Gr3. "0001111" indicates that the movement amount of anchor AK3 is +15.

[0219] In the CU_Gr conversion information, "0101101" is registered as the CU_Gr conversion information for boundary 0. "0101101" indicates that the movement amount of boundary 0 is +45. "0011110" is registered as the CU_Gr conversion information for boundary 1. "0011110" indicates that the movement amount of boundary 1 is +30. "0001111" is registered as the CU_Gr conversion information for boundary 2. "0001111" indicates that the movement amount of boundary 2 is +15.

[0220] 2.4 Effects of this embodiment With the configuration according to this embodiment, the same effects as those of the first embodiment can be obtained.

[0221] Furthermore, with the configuration according to this embodiment, the anchor AK can be moved, so the range in which the boundary line can be moved can be increased.

[0222] 2.5 Modification of the second embodiment Next, a modified example of the second embodiment will be described. In this modified example, a flow of registering anchor conversion information that differs from that of the second embodiment will be described.

[0223] 2.5.1 Flow of registering anchor conversion information The flow of registering anchor conversion information will be described with reference to Fig. 31. Fig. 31 is a flowchart showing the flow of registering anchor conversion information.

[0224] In this modification, after the write operation to all cell units CU of the block BLK to be written is completed, the anchor conversion information of the block BLK is registered. In the following description, the anchor AK and the cell unit group CU_Gr are expressed as anchor AKi and cell unit group CU_Gri using a variable i (i is an integer that is 0 or more and (total number of cell unit groups-1) or less).

[0225] Note that the flow of the CU_Gr conversion information may be the same as the flow of the CU_Gr conversion information described with reference to FIG. 13 in the first embodiment.

[0226] As shown in FIG. 31, the control circuit 31 confirms that the write operation to all cell units CU in the write target block BLK has been completed (S200).

[0227] First, the control circuit 31 sets a variable i=0 (S201).

[0228] The control circuit 31 refers to the block management information to acquire the position information of the anchor AKi (S202). Then, the control circuit 31 checks whether the anchor AKi is included in the cell unit group CU_Gri (S203).

[0229] If the anchor AKi is not in the cell unit group CU_Gri (S203_No), the control circuit 31 updates the position of the anchor AKi (S204). That is, the control circuit 31 moves the anchor AKi to an arbitrary position within the cell unit group CU_Gri.

[0230] The control circuit 31 registers the updated position of the anchor AKi in the anchor conversion information (S205).

[0231] After registering the anchor conversion information (S205), or if the anchor AKi is in the cell unit group CU_Gri (S203_Yes), the control circuit 31 increments the variable i to i=i+1 (S206). Then, the control circuit 31 checks whether the variable i is less than the total number of the cell unit group CU_Gr (S207).

[0232] If the variable i is less than the total number of cell unit groups CU_Gr (S207_Yes), the control circuit 31 proceeds to step S202. On the other hand, if the variable i is not less than the total number of cell unit groups CU_Gr (S207_No), the control circuit 31 ends the registration of the anchor conversion information for the block BLK.

[0233] 2.5.2 Effects of this modification With the configuration according to this modification, the same effects as those of the second embodiment can be obtained.

[0234] 3. Third embodiment Next, a third embodiment will be described. In the third embodiment, a case where the position of an anchor AK in a cell unit group CU_Gr is moved when a boundary line is moved will be described. Below, the differences from the first and second embodiments will be mainly described.

[0235] 3.1 Flow of registration of CU_Gr conversion information and anchor conversion information First, an example of the flow of registering CU_Gr conversion information and anchor conversion information will be described with reference to Fig. 32. Fig. 32 is a flowchart showing an example of the flow of registering CU_Gr conversion information and anchor conversion information.

[0236] As shown in FIG. 32, the flow of steps S100 to S107 is similar to that explained using FIG. 13 in the first embodiment.

[0237] After registering the CU_Gr conversion information (S106), the control circuit 31 checks whether the anchor AK has been changed (moved) (S120). For example, if there is a cell unit group CU_Gr that does not include an anchor AK, or if there is an anchor AK that needs to be moved even if it is in the cell unit group CU_Gr, the control circuit 31 determines that the anchor AK has been changed.

[0238] If there is a change in the anchor AK (S120_Yes), the control circuit 31 acquires information on the anchor AK to be changed (S121). For example, when moving the position of the anchor AK to the center of the corresponding cell unit group CU_Gr, the control circuit 31 moves the anchor AK in the cell unit group CU_Gr in accordance with the movement of the boundary line. On the other hand, if there is no change in the anchor AK (S120_No), the control circuit 31 ends the registration.

[0239] The control circuit 31 updates the position of the anchor AK selected as the change target (S122).

[0240] The control circuit 31 registers the information of the moved anchor AK in the anchor conversion information (S111).

[0241] 3.2 Examples of boundary and anchor movement Next, a specific example of the case where boundary lines and anchor AK are moved will be described with reference to Fig. 33 and Fig. 34. In this specific example, N=(total number of cell unit groups-1), that is, the number of boundary line movements (i.e., the number of time differences) in one block BLK is allowed up to the total number of boundary lines. Fig. 33 is a schematic diagram showing a specific example of boundary line and anchor AK movement in one block BLK. Fig. 34 is a table showing an example of Vth information, CU_Gr conversion information, and anchor conversion information in the specific example.

[0242] 33, in this example, the control circuit 31 moves each of the boundaries 0 to 2. Accordingly, the control circuit 31 moves each anchor AK to near the center of the corresponding cell unit group CU_Gr.

[0243] More specifically, a time difference occurs between the cell unit CU corresponding to the set of the string unit SU1 and the word line WL2 and the cell unit CU corresponding to the set of the string unit SU2 and the word line WL2. Therefore, the control circuit 31 shifts the boundary 0 between these two cell units CU. The shift amount of the boundary 0 is -6.

[0244] There is a time difference between the cell unit CU corresponding to the pair of string unit SU0 and word line WL9 and the cell unit CU corresponding to the pair of string unit SU1 and word line WL9. Therefore, the control circuit 31 moves the boundary 1 between these two cell units CU. The movement amount of the boundary 1 is +5.

[0245] There is a time difference between the cell unit CU corresponding to the set of string unit SU2 and word line WL14 and the cell unit CU corresponding to the set of string unit SU3 and word line WL14. Therefore, the control circuit 31 moves the boundary 2 between these two cell units CU. The amount of movement of the boundary 2 is +11.

[0246] As a result, the cell unit group CU_Gr0 includes the cell unit CU corresponding to the pair of string unit SU0 and word line WL0 through the cell unit CU corresponding to the pair of string unit SU1 and word line WL2. The cell unit group CU_Gr1 includes the cell unit CU corresponding to the pair of string unit SU2 and word line WL2 through the cell unit CU corresponding to the pair of string unit SU0 and word line WL9. The cell unit group CU_Gr2 includes the cell unit CU corresponding to the pair of string unit SU1 and word line WL9 through the cell unit CU corresponding to the pair of string unit SU2 and word line WL14. The cell unit group CU_Gr3 includes the cell unit CU corresponding to the pair of string unit SU3 and word line WL14 through the cell unit CU corresponding to the pair of string unit SU3 and word line WL15.

[0247] The control circuit 31 moves the anchor AK0 from the cell unit CU corresponding to the set of the string unit SU0 and the word line WL0 to the cell unit CU corresponding to the set of the string unit SU0 and the word line WL1. The movement amount of the anchor AK0 is +4. The control circuit 31 moves the anchor AK1 from the cell unit CU corresponding to the set of the string unit SU0 and the word line WL4 to the cell unit CU corresponding to the set of the string unit SU3 and the word line WL5. The movement amount of the anchor AK1 is +7. The control circuit 31 moves the anchor AK2 from the cell unit CU corresponding to the set of the string unit SU0 and the word line WL8 to the cell unit CU corresponding to the set of the string unit SU0 and the word line WL12. The movement amount of the anchor AK2 is +16. The control circuit 31 moves the anchor AK3 from the cell unit CU corresponding to the set of the string unit SU0 and the word line WL12 to the cell unit CU corresponding to the set of the string unit SU1 and the word line WL15. The movement amount of the anchor AK3 is +13.

[0248] As shown in FIG. 34, in the anchor conversion information, "0000100" is registered as the conversion information of anchor AK0 included in cell unit group CU_Gr0. "0000100" indicates that the movement amount of anchor AK0 is +4. "0000111" is registered as the conversion information of anchor AK1 included in cell unit group CU_Gr1. "0000111" indicates that the movement amount of anchor AK1 is +7. "0010000" is registered as the conversion information of anchor AK2 included in cell unit group CU_Gr2. "0010000" indicates that the movement amount of anchor AK2 is +16. "0001101" is registered as the conversion information of anchor AK3 included in cell unit group CU_Gr3. "0001101" indicates that the movement amount of anchor AK3 is +13.

[0249] In the CU_Gr conversion information, "1111010" is registered as the CU_Gr conversion information for boundary 0. "1111010" indicates that the movement amount of boundary 0 is -6. "0000101" is registered as the CU_Gr conversion information for boundary 1. "0000101" indicates that the movement amount of boundary 1 is +5. "0001011" is registered as the CU_Gr conversion information for boundary 2. "0001011" indicates that the movement amount of boundary 2 is +11.

[0250] 3.3 Configuration according to this embodiment With the configuration according to this embodiment, the same effects as those of the first and second embodiments can be obtained.

[0251] 3.4 Modification of the third embodiment Next, a modified example of the third embodiment will be described. In this modified example, a flow of registering anchor conversion information that differs from that of the third embodiment will be described.

[0252] 3.4.1 Flow of registering anchor conversion information The flow of registering anchor conversion information will be described with reference to Fig. 35. Fig. 35 is a flowchart showing the flow of registering anchor conversion information.

[0253] In this modification, similarly to the modification of the second embodiment, after the write operation to all cell units CU in a write target block BLK is completed, the anchor conversion information of the block BLK is registered.

[0254] Note that the flow of the CU_Gr conversion information may be the same as the flow of the CU_Gr conversion information described with reference to FIG. 13 in the first embodiment.

[0255] As shown in FIG. 35, the flow of steps S200 to S202 is similar to that described with reference to FIG. 31 in the modified example of the second embodiment.

[0256] After acquiring the position information of the anchor AKi (S202), the control circuit 31 checks whether the position of the anchor AKi needs to be changed (S210).

[0257] If the position of anchor AKi needs to be changed (S210_Yes), the control circuit 31 updates the position of anchor AKi (S204). That is, the control circuit 31 moves anchor AKi to any position within the cell unit group CU_Gri. On the other hand, if the position of anchor AKi does not need to be changed (S210_No), the control circuit 31 proceeds to step S206.

[0258] The flow of steps S205 to S207 is similar to that described with reference to FIG. 31 in the modified example of the second embodiment.

[0259] 3.4.2 Effects of this modification With the configuration according to this modification, the same effects as those of the third embodiment can be obtained.

[0260] 4. Fourth embodiment Next, a fourth embodiment will be described. In the fourth embodiment, a case where a cell unit group CU_Gr and an anchor AK are added will be described.

[0261] 4.1 Flow of adding cell unit groups and anchors Next, an example of the flow of adding a cell unit group CU_Gr and an anchor AK will be described with reference to Fig. 36. Fig. 36 is a flowchart showing an example of the flow of adding a cell unit group CU_Gr and an anchor AK. Note that the example of Fig. 36 is a flowchart focusing on the addition of a cell unit group CU_Gr and an anchor AK, and the flow related to the movement of an existing cell unit group CU_Gr and an anchor AK is omitted.

[0262] As shown in FIG. 36, the flow of steps S100 to S104 is similar to that explained using FIG. 13 in the first embodiment.

[0263] If the acquisition is successful (S104_Yes), the control circuit 31 executes registration processing according to any of the flow described using FIG. 13 in the first embodiment, the flow described using FIG. 22 in the second embodiment, or the flow described using FIG. 32 in the third embodiment.

[0264] If the acquisition fails (S104_No) or if the number of times the time difference occurs exceeds the set value N (S102_No), the control circuit 31 checks whether the number of times the cell unit group CU_Gr has been added is equal to or less than a preset judgment value M (M is an integer equal to or greater than 1) (S130). For example, the number of times the cell unit group CU_Gr has been added is a value obtained by subtracting the set value N from the number of times the time difference occurs. For example, the judgment value M is set with reference to the number of cell units CU included in the cell unit group CU_Gr. The control circuit 31 checks whether the number of times the addition is equal to or greater than (N+M). For example, if the number of times the time difference occurs is equal to or greater than the total number of cell unit groups, the control circuit 31 checks whether the cell unit group CU_Gr can be added.

[0265] If the number of times the cell unit group CU_Gr has been added is equal to or less than the judgment value M (S130_Yes), the control circuit 31 judges that the cell unit group CU_Gr can be added, and creates Vth information corresponding to the cell unit group CU_Gr to be added (S131).

[0266] Next, the control circuit creates CU_Gr conversion information corresponding to the cell unit group CU_Gr to be added (S132).

[0267] Next, the control circuit creates anchor conversion information corresponding to the cell unit group CU_Gr to be added (S133). Note that the order of steps S131 to S133 may be changed, or steps may be executed in parallel.

[0268] Moreover, when the number of times the cell unit group CU_Gr is added exceeds the judgment value M (S130_No), the control circuit 31 sets the block movement flag (S107).

[0269] 4.2 Specific examples of cell unit groups and anchor addition Next, a specific example of adding a cell unit group CU_Gr and an anchor AK will be described with reference to Fig. 37 and Fig. 38. In this specific example, N=(total number of cell unit groups-1), that is, the number of boundary line movements (i.e., the number of time differences) in one block BLK is allowed up to the total number of boundary lines. Fig. 37 is a schematic diagram showing a specific example of adding a cell unit group CU_Gr and an anchor AK in one block BLK. Fig. 38 is a table showing an example of Vth information, CU_Gr conversion information, and anchor conversion information in the specific example.

[0270] 37, in this example, the control circuit 31 moves each of boundary 0 to boundary 2. Accordingly, the control circuit 31 moves anchors AK0 to AK3. In addition, the control circuit 31 newly adds a cell unit group CU_Gr4 and an anchor AK4.

[0271] More specifically, a time difference occurs between the cell unit CU corresponding to the set of the string unit SU1 and the word line WL2 and the cell unit CU corresponding to the set of the string unit SU2 and the word line WL2. Therefore, the control circuit 31 shifts the boundary 0 between these two cell units CU. The shift amount of the boundary 0 is -6.

[0272] There is a time difference between the cell unit CU corresponding to the pair of string unit SU0 and word line WL9 and the cell unit CU corresponding to the pair of string unit SU1 and word line WL9. Therefore, the control circuit 31 moves the boundary 1 between these two cell units CU. The movement amount of the boundary 1 is +5.

[0273] There is a time difference between the cell unit CU corresponding to the pair of string unit SU2 and word line WL14 and the cell unit CU corresponding to the pair of string unit SU3 and word line WL14. Therefore, the control circuit 31 moves the boundary 2 between these two cell units CU. The amount of movement of the boundary 2 is +11.

[0274] A time difference occurs between the cell unit CU corresponding to the set of string unit SU1 and word line WL15 and the cell unit CU corresponding to the set of string unit SU2 and word line WL15. For this reason, the control circuit 31 adds a new boundary 3 between these two cell units CU. The control circuit 31 then adds a cell unit group CU_Gr4 and an anchor AK4.

[0275] As a result, the cell unit group CU_Gr0 includes the cell unit CU corresponding to the set of the string unit SU0 and the word line WL0 to the cell unit CU corresponding to the set of the string unit SU1 and the word line WL2. The cell unit group CU_Gr1 includes the cell unit CU corresponding to the set of the string unit SU2 and the word line WL2 to the cell unit CU corresponding to the set of the string unit SU0 and the word line WL9. The cell unit group CU_Gr2 includes the cell unit CU corresponding to the set of the string unit SU1 and the word line WL9 to the cell unit CU corresponding to the set of the string unit SU2 and the word line WL14. The cell unit group CU_Gr3 includes the cell unit CU corresponding to the set of the string unit SU3 and the word line WL14 to the cell unit CU corresponding to the set of the string unit SU1 and the word line WL15. The added cell unit group CU_Gr4 includes the cell unit CU corresponding to the set of the string unit SU2 and the word line WL15 and the cell unit CU corresponding to the set of the string unit SU3 and the word line WL15.

[0276] The control circuit 31 moves the anchor AK0 from the cell unit CU corresponding to the set of the string unit SU0 and the word line WL0 to the cell unit CU corresponding to the set of the string unit SU0 and the word line WL1. The movement amount of the anchor AK0 is +4. The control circuit 31 moves the anchor AK1 from the cell unit CU corresponding to the set of the string unit SU0 and the word line WL4 to the cell unit CU corresponding to the set of the string unit SU3 and the word line WL5. The movement amount of the anchor AK1 is +7. The control circuit 31 moves the anchor AK2 from the cell unit CU corresponding to the set of the string unit SU0 and the word line WL8 to the cell unit CU corresponding to the set of the string unit SU0 and the word line WL12. The movement amount of the anchor AK2 is +16. The control circuit 31 moves the anchor AK3 from the cell unit CU corresponding to the set of the string unit SU0 and the word line WL12 to the cell unit CU corresponding to the set of the string unit SU0 and the word line WL15. The movement amount of the anchor AK3 is +12. Then, the control circuit 31 assigns the anchor AK4 to the cell unit CU corresponding to the pair of the string unit SU2 and the word line WL15.

[0277] As shown in Fig. 38, a cell unit group CU_Gr4 is added to the block BLK0. In the example of Fig. 38, when one addition is allowed, a total of five bytes are added, including three bytes of MCL Vth information (a set of ΔVA, ΔVB, and ΔVC), one byte of anchor conversion information, and one byte of Cu_Gr conversion information. Therefore, when the time difference occurs at four places, the amount of data increase is a maximum of 11 bytes per block.

[0278] A set of ΔVA4, ΔVB4, and ΔVC4 is created as Vth information corresponding to the cell unit group CU_Gr4.

[0279] In the anchor conversion information, "0000100" is registered as the conversion information of anchor AK0 included in cell unit group CU_Gr0. "0000100" indicates that the movement amount of anchor AK0 is +4. "0000111" is registered as the conversion information of anchor AK1 included in cell unit group CU_Gr1. "0000111" indicates that the movement amount of anchor AK1 is +7. "0010000" is registered as the conversion information of anchor AK2 included in cell unit group CU_Gr2. "0010000" indicates that the movement amount of anchor AK2 is +16. "0001100" is registered as the conversion information of anchor AK3 included in cell unit group CU_Gr3. "0001100" indicates that the movement amount of anchor AK3 is +12. For example, "0111010" is registered as the conversion information of anchor AK4 included in cell unit group CU_Gr4. "0111010" indicates that the amount of movement based on anchor AK0 is +58. Note that the amount of movement of anchor AK4 may be based on the cell unit CU corresponding to the set of string unit SU0 and word line WL0, or may be based on the previous anchor AK3.

[0280] In the CU_Gr conversion information, "1111010" is registered as the CU_Gr conversion information of boundary 0. "1111010" indicates that the movement amount of boundary 0 is -6. "0000101" is registered as the CU_Gr conversion information of boundary 1. "0000101" indicates that the movement amount of boundary 1 is +5. "0001011" is registered as the CU_Gr conversion information of boundary 2. "0001011" indicates that the movement amount of boundary 2 is +11. For example, "0111000" is registered as the CU_Gr conversion information of the added boundary 3. "0111000" indicates that the movement amount based on boundary 0 is +56. Note that the movement amount of boundary 3 may be based on, for example, the previous boundary 2.

[0281] 4.3 Effects of this embodiment With the configuration according to this embodiment, the same effects as those of the first to third embodiments can be obtained.

[0282] Furthermore, in the configuration according to the present embodiment, a cell unit group CU_Gr and an anchor AK can be added. Therefore, for example, when the memory system 3 is a ZNS-compliant memory system, even if the number of occurrences of time differences becomes greater than (the total number of cell unit groups CU_Gr minus 1), an increase in error bits due to the occurrence of time differences can be suppressed. Therefore, the reliability of the memory system 3 can be improved. Also, a decrease in processing capacity due to processing for error correction can be suppressed. Also, for example, when the memory system 3 is a ZNS-incompatible memory system, even if the number of occurrences of time differences becomes greater than (the total number of cell unit groups CU_Gr minus 1), a write operation in the block BLK can be continued without performing a padding data insertion process. Therefore, an increase in WAF can be suppressed.

[0283] 4.4 Modification of the fourth embodiment Next, a modified example of the fourth embodiment will be described. In this modified example, as in the modified example of the first embodiment, a case where the anchor AK is not set will be described. Below, the differences from the fourth embodiment will be mainly described.

[0284] 4.4.1 Flow of adding a cell unit group First, the flow of adding a cell unit group CU_Gr will be described with reference to Fig. 39. Fig. 39 is a flowchart showing the flow of adding a cell unit group CU_Gr. Note that the example of Fig. 39 is a flowchart focusing on the addition of a cell unit group CU_Gr, and the flow related to the movement of an existing cell unit group CU_Gr is omitted.

[0285] As shown in FIG. 39, the flow of steps S100 to S104 is similar to that explained using FIG. 13 in the first embodiment.

[0286] If the acquisition is successful (S104_Yes), the control circuit 31 executes the registration process according to the flow described with reference to FIG. 13 in the first embodiment.

[0287] On the other hand, if the acquisition fails (S104_No), the control circuit 31 checks whether the number of times the cell unit group CU_Gr has been added is equal to or less than a preset judgment value M (M is an integer equal to or greater than 1) (S130). That is, the control circuit 31 checks whether the number of times the time difference has occurred is equal to or less than (N+M).

[0288] If the number of times the cell unit group CU_Gr has been added is equal to or less than the judgment value M (S130_Yes), the control circuit 31 creates Vth information corresponding to the cell unit group CU_Gr to be added (S131).

[0289] Next, the control circuit creates CU_Gr conversion information corresponding to the cell unit group CU_Gr to be added (S132). Note that the order of steps S131 and S132 may be changed, or they may be executed in parallel. In this example, the creation of anchor conversion information in step S133 described with reference to FIG. 36 of the fourth embodiment is omitted.

[0290] When the number of times the cell unit group CU_Gr is added exceeds the judgment value M (S130_No), the control circuit 31 sets the block movement flag (S107).

[0291] 4.4.2 Example of adding a cell unit group Next, a specific example of adding a cell unit group CU_Gr will be described with reference to Fig. 40 and Fig. 41. In this specific example, N=(total number of cell unit groups-1), that is, the number of boundary line movements (i.e., the number of time differences) allowed in one block BLK is up to the total number of boundary lines. Fig. 40 is a schematic diagram showing a specific example of adding a cell unit group CU_Gr in one block BLK. Fig. 41 is a table showing an example of Vth information and CU_Gr conversion information in the specific example.

[0292] 40, similarly to the specific example described with reference to FIG 37 of the fourth embodiment, the control circuit 31 moves each of the boundaries 0 to 2. In addition, the control circuit 31 adds a cell unit group CU_Gr4.

[0293] More specifically, a time difference occurs between the cell unit CU corresponding to the set of the string unit SU1 and the word line WL2 and the cell unit CU corresponding to the set of the string unit SU2 and the word line WL2. Therefore, the control circuit 31 shifts the boundary 0 between these two cell units CU. The shift amount of the boundary 0 is -6.

[0294] There is a time difference between the cell unit CU corresponding to the pair of string unit SU0 and word line WL9 and the cell unit CU corresponding to the pair of string unit SU1 and word line WL9. Therefore, the control circuit 31 moves the boundary 1 between these two cell units CU. The movement amount of the boundary 1 is +5.

[0295] There is a time difference between the cell unit CU corresponding to the pair of string unit SU2 and word line WL14 and the cell unit CU corresponding to the pair of string unit SU3 and word line WL14. Therefore, the control circuit 31 moves the boundary 2 between these two cell units CU. The amount of movement of the boundary 2 is +11.

[0296] A time difference occurs between the cell unit CU corresponding to the set of string unit SU1 and word line WL15 and the cell unit CU corresponding to the set of string unit SU2 and word line WL15. For this reason, the control circuit 31 adds a new boundary 3 between these two cell units CU.

[0297] The configuration of each cell unit group CU_Gr is the same as that explained in FIG.

[0298] As shown in FIG. 41, a cell unit group CU_Gr4 is added to the block BLK0.

[0299] A set of ΔVA4, ΔVB4, and ΔVC4 is created as Vth information corresponding to the cell unit group CU_Gr4.

[0300] In the CU_Gr conversion information, "1111010" is registered as the CU_Gr conversion information of boundary 0. "1111010" indicates that the movement amount of boundary 0 is -6. "0000101" is registered as the CU_Gr conversion information of boundary 1. "0000101" indicates that the movement amount of boundary 1 is +5. "0001011" is registered as the CU_Gr conversion information of boundary 2. "0001011" indicates that the movement amount of boundary 2 is +11. "0111000" is registered as the CU_Gr conversion information of the added boundary 3. "0111000" indicates that the movement amount based on boundary 0 is +56. Note that the movement amount of boundary 3 may be based on, for example, the previous boundary 2.

[0301] 4.4.3 Effects of this modification With the configuration according to this modification, the same effects as those of the fourth embodiment can be obtained.

[0302] 5. Fifth embodiment Next, a fifth embodiment will be described. In the fifth embodiment, a case where the memory system 3 is a ZNS non-compliant memory system and a padding data insertion process (hereinafter, simply referred to as "padding process") is performed on a write block will be described. The following mainly describes the differences from the first to fourth embodiments.

[0303] 5.1 Padding data insertion process flow First, an example of the flow of the padding data insertion process will be described with reference to Fig. 42. Fig. 42 is a flowchart showing an example of the flow of the padding data insertion process.

[0304] In this embodiment, when a time difference occurs, padding data is inserted into the remaining (unwritten) cell units CU in the cell unit group CU_Gr in which the time difference occurs.

[0305] As shown in FIG. 42, first, the control circuit 31 checks whether or not a time difference occurrence flag is set (S300).

[0306] If there is no time difference occurrence flag (S301_No), the control circuit 31 ends the padding data insertion process.

[0307] If the time difference occurrence flag is present (set) (S301_Yes), the control circuit 31 acquires a start address for starting the padding data insertion process (S302). For example, the address of the next cell unit CU where a time difference has occurred is acquired as the start address.

[0308] Next, the control circuit 31 acquires an end address at which the padding data insertion process ends (S303). For example, the address of the last cell unit CU of the cell unit group CU_Gr in which a time difference occurs is acquired as the end address.

[0309] The control circuit 31 executes a padding data insertion process (S304). More specifically, the control circuit 31 writes the padding data to the cell units CU between the start address and the end address. In other words, the control circuit 31 writes the padding data to the unwritten cell units CU in the cell unit group CU_Gr where the time difference occurs.

[0310] When the padding data insertion process is completed, the control circuit 31 sets the address of the next write destination (S305). More specifically, for example, the control circuit 31 sets the address of the first cell unit CU of the next cell unit group CU_Gr as the address of the next write destination. Note that if the cell unit group CU_Gr in which the time difference occurs is the last cell unit group CU_Gr in the block BLK, the control circuit 31 sets the address of another block BLK as the address of the next write destination.

[0311] 5.2 Example of inserting padding data Next, a specific example of inserting padding data PD will be described with reference to Fig. 43. Fig. 43 is a schematic diagram showing a specific example of inserting padding data PD in one block BLK.

[0312] As shown in FIG. 43, the configuration of the cell unit group CU_Gr and the arrangement of the anchors AK are similar to those in FIG. 9 of the first embodiment.

[0313] For example, a time difference occurs between the cell unit CU corresponding to the pair of string unit SU0 and word line WL9 in cell unit group CU_Gr2 and the cell unit CU corresponding to the pair of string unit SU1 and word line WL9. In this case, the control circuit 31 executes a process of inserting padding data PD into the remaining cell units CU in cell unit group CU_Gr2. More specifically, padding data PD is written into 11 cell units CU from the cell unit CU corresponding to the pair of string unit SU1 and word line WL9 to the cell unit CU corresponding to the pair of string unit SU3 and word line WL11.

[0314] Then, the control circuit 31 sets the address of the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL12 of the cell unit group CU_Gr3 as the next write destination address.

[0315] 5.3 Effects of this embodiment In the configuration according to the present embodiment, in a memory system 3 capable of inserting padding data PD, i.e., a ZNS-incompatible memory system, the insertion range of the padding data PD can be set to the unwritten cell units CU of the cell unit group CU_Gr in which a time difference has occurred. This allows the insertion range of the padding data PD to be narrower than the case where it is set to all the unwritten cell units CU of the block BLK to be written. This suppresses an increase in invalid data, thereby suppressing an increase in WAF. Therefore, it is possible to suppress a decrease in the effective memory capacity of the memory system 3. In addition, it is possible to suppress an increase in the frequency of writing invalid data, thereby suppressing an increase in the number of repetitions of the write operation and the erase operation. Therefore, it is possible to suppress deterioration of the life of the memory system 3.

[0316] 5.4 Modification of the fifth embodiment Next, a modified example of the fifth embodiment will be described. In this modified example, as in the modified example of the first embodiment, a case where the anchor AK is not set will be described. Below, the differences from the fifth embodiment will be mainly described.

[0317] 5.4.1 Example of inserting padding data Next, a specific example of inserting padding data PD will be described with reference to Fig. 44. Fig. 44 is a schematic diagram showing a specific example of inserting padding data in one block BLK.

[0318] 44, in this example, as in the specific example of the fifth embodiment, a time difference occurs between the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL9 in the cell unit group CU_Gr2 and the cell unit CU corresponding to the pair of the string unit SU1 and the word line WL9 in the cell unit group CU_Gr2. Therefore, the control circuit 31 executes the process of inserting padding data PD into the remaining cell units CU in the cell unit group CU_Gr2.

[0319] Then, the control circuit 31 sets the address of the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL12 of the cell unit group CU_Gr3 as the next write destination address.

[0320] 5.4.2 Effects of this modification With the configuration according to this modification, the same effects as those of the fifth embodiment can be obtained.

[0321] 6. Sixth embodiment Next, a sixth embodiment will be described. In the sixth embodiment, a case will be described in which padding data PD is inserted into a cell unit group CU_Gr in which a time difference occurs, and the position of an anchor AK is also changed. Below, the differences from the first to fifth embodiments will be mainly described.

[0322] 6.1 Flow of inserting padding data and registering anchor conversion information First, an example of the flow of inserting processing of padding data PD and registering anchor conversion information will be described with reference to Fig. 45. Fig. 45 is a flowchart showing an example of the flow of inserting processing of padding data PD and registering anchor conversion information.

[0323] In this embodiment, when a time difference occurs, padding data PD is inserted into the remaining cell units CU in the cell unit group CU_Gr in which the time difference occurs.

[0324] As shown in FIG. 45, the flow of steps S300 to S305 is similar to that explained using FIG. 42 in the fifth embodiment.

[0325] After setting the address of the next write destination (S305), the control circuit 31 checks whether the anchor AK has been changed (moved) (S306). For example, if the cell unit CU into which the padding data PD is to be inserted contains an anchor AK, or if there is an anchor AK to be moved, the control circuit 31 determines that the anchor AK has been changed.

[0326] If there is a change in the anchor AK (S306_Yes), the control circuit 31 acquires information on the anchor AK to be changed (S307). For example, when the position of the anchor AK is set near the center of the cell unit group CU_Gr, the control circuit 31 moves the anchor AK to near the center of the cell unit CU in the cell unit group CU_Gr to which valid data has been written, in accordance with the insertion of the padding data PD. On the other hand, if there is no change in the anchor AK (S306_No), the control circuit 31 ends the registration.

[0327] The control circuit 31 updates the position of the anchor AK selected as the change target (S308).

[0328] The control circuit 31 registers the information of the moved anchor AK in the anchor conversion information (309).

[0329] 6.2 Examples of inserting padding data and moving anchors Next, a specific example of inserting padding data PD and moving anchor AK will be described with reference to Fig. 46 and Fig. 47. Fig. 46 is a schematic diagram showing a specific example of inserting padding data PD and moving anchor AK in one block BLK. Fig. 47 is a table showing an example of Vth information and anchor conversion information in the specific example.

[0330] As shown in FIG. 46, the configuration of the cell unit group CU_Gr and the arrangement of anchors AK before the change are the same as those in FIG. 9 of the first embodiment.

[0331] For example, as in the description of FIG. 43 of the fifth embodiment, a time difference occurs between the cell unit CU corresponding to the pair of string unit SU0 and word line WL9 in cell unit group CU_Gr2 and the cell unit CU corresponding to the pair of string unit SU1 and word line WL9. In this case, the control circuit 31 executes a process of inserting padding data PD into the remaining cell units CU in cell unit group CU_Gr2. More specifically, padding data is written into 11 cell units CU from the cell unit CU corresponding to the pair of string unit SU1 and word line WL9 to the cell unit CU corresponding to the pair of string unit SU3 and word line WL11.

[0332] The control circuit 31 sets the address of the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL12 in the cell unit group CU_Gr3 as the next write destination address.

[0333] Moreover, the control circuit 31 moves the anchor AK2 from the cell unit CU corresponding to the pair of the string unit SU0 and the word line WL8 to the cell unit CU corresponding to the pair of the string unit SU2 and the word line WL8. The movement amount of the anchor AK2 is +2.

[0334] As shown in Fig. 47, the anchor conversion information is represented by, for example, 4-bit data (0≦movement amount≦+15). If no movement of the anchor AK occurs, the anchor position information is set to "0000". For example, if the movement amount is +15, the boundary position information is set to "1111".

[0335] 47, "0010" is registered as the conversion information of the anchor AK2 included in the cell unit group CU_Gr2 in the anchor conversion information. "0010" indicates that the movement amount of the anchor AK2 is +2.

[0336] 6.3 Effects of this embodiment With the configuration according to this embodiment, the same effects as those of the fifth embodiment can be obtained.

[0337] Furthermore, with the configuration according to this embodiment, the anchor AK can be moved, so the range in which padding data PD can be inserted can be increased.

[0338] 7. Modifications, etc. In the configuration according to the above embodiment, the memory system includes a memory chip (11) including a block (BLK) including a plurality of cell units (CU), each including a plurality of memory cells (MC), and a memory controller (30). A first cell unit (CU, SU2_WL6) and a second cell unit (CU, SU3_WL6) of the plurality of cell units are classified into a first group (CU_Gr1), and a third cell unit (CU, SU0_WL8) of the plurality of cell units is classified into a second group (CU_Gr2). The memory controller is configured to use a first correction amount (ΔVA1) of the read voltage when reading data from multiple memory cells of a cell unit classified into a first group among the multiple cell units, and to use a second correction amount (ΔVA2) of the read voltage when reading data from multiple memory cells of a cell unit classified into a second group among the multiple cell units, and to change the boundary position (boundary 1) between the first group and the second group to between the first cell unit and the second cell unit and classify the second cell unit into the second group if the time difference between executing a write operation of the first cell unit and executing a write operation of the second cell unit exceeds a reference value.

[0339] By applying the above-described embodiment, it is possible to provide a semiconductor memory device capable of improving the processing capacity.

[0340] The embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0341] Furthermore, in the above embodiments, "connection" also includes a state in which something else, such as a transistor or a resistor, is interposed between them and indirectly connected.

[0342] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope of the invention and its equivalents described in the claims, as well as in the scope and spirit of the invention. [Explanation of symbols]

[0343] 1...data processing device, 2...host device, 3...memory system, 10...non-volatile memory, 11...memory chip, 20...volatile memory, 30...memory controller, 31...control circuit, 32...buffer memory, 33...host interface circuit, 34...ECC circuit, 35...NAND interface circuit, 36...read voltage correction circuit, 37...RAM interface circuit, 38...time difference timer, 40...semiconductor substrate, 41...conductive layer, 42-47...conductive layer, 50...core film, 51...semiconductor film, 52...laminated film, 52a...tunnel insulating film, 52b...charge storage film, 52c...block insulating film, 53...semiconductor portion, 101...input / output circuit, 102...logic control circuit, 103...address register, 104...command register, 105...status register, 106...sequencer, 107...ready / busy circuit, 108...voltage generation circuit, 109...memory cell array, 110...row decoder, 111...sense amplifier, 112...data register, 113...column decoder, AK0 to AK4...anchors BL0 to BLm... bit lines, BLK... block, CH0 to CH2... channel, MC0 to MC15... memory cell transistor, PLN0, PLN1... plane, SGD0 to SGD3... select gate lines, ST1, ST2... select transistor, SU0 to SU3... string unit, WL0 to WL15... word lines.

Claims

1. a memory chip including a block including a plurality of cell units each including a plurality of memory cells; Memory controller and Equipped with A first cell unit and a second cell unit of the plurality of cell units are classified into a first group, and a third cell unit of the plurality of cell units is classified into a second group; The memory controller includes: When reading data from the plurality of memory cells of the cell units classified into the first group among the plurality of cell units, a first correction amount of a read voltage is used; When reading data from the plurality of memory cells of the cell units classified into the second group among the plurality of cell units, a second correction amount of the read voltage is used; When a time difference between the execution of a write operation of the first cell unit and the execution of the write operation of the second cell unit exceeds a reference value, a boundary position between the first group and the second group is changed to a position between the first cell unit and the second cell unit, and the second cell unit is classified into the second group. It is configured as follows: Memory system.

2. the memory controller is configured to write data to another block in the next write operation when the number of occurrences of the time difference exceeding the reference value in the block exceeds a preset value.

2. The memory system of claim 1.

3. The blocks are classified into a plurality of groups including the first group and the second group, The maximum value of the set value is a value obtained by subtracting 1 from the total number of the groups included in the block.

3. The memory system of claim 2.

4. the memory controller is configured to perform the write operation to the second cell unit after performing the write operation to the first cell unit; 2. The memory system of claim 1.

5. the memory controller is configured to use a fourth cell unit classified into the first group among the plurality of cell units for calculating the first correction amount, and to use the third cell unit for calculating the second correction amount.

2. The memory system of claim 1.

6. A fifth cell unit and a sixth cell unit among the plurality of cell units are classified into the second group, A seventh cell unit of the plurality of cell units is classified into a third group; The memory controller includes: When reading data from the plurality of memory cells of the cell units classified into the third group among the plurality of cell units, a third correction amount of the read voltage is used; If a time difference between the execution of the write operation of the fifth cell unit and the execution of the write operation of the sixth cell unit exceeds the reference value, a boundary position between the second group and the third group is changed to a position between the fifth cell unit and the sixth cell unit, and the sixth cell unit is classified into the third group. It is configured as follows:

2. The memory system of claim 1.

7. An eighth cell unit, a ninth cell unit, a tenth cell unit, and an eleventh cell unit among the plurality of cell units are classified into a third group; The memory controller includes: When reading data from the plurality of memory cells of the cell units classified into the third group among the plurality of cell units, a third correction amount of the read voltage calculated using the eighth cell unit is used; If the time difference between the execution of the write operation of the ninth cell unit and the execution of the write operation of the tenth cell unit exceeds the reference value, the boundary position between the second group and the third group is changed to between the ninth cell unit and the tenth cell unit, and the eighth cell unit and the ninth cell unit are classified into the second group, and the eleventh cell unit is used in the calculation of the third correction amount. It is configured as follows:

6. The memory system of claim 5.

8. A twelfth cell unit of the plurality of cell units is classified into the first group; A thirteenth cell unit of the plurality of cell units is classified into a third group; The memory controller includes: When reading data from the plurality of memory cells of the cell units classified into the third group among the plurality of cell units, a third correction amount of the read voltage calculated using the thirteenth cell unit is used; If a time difference between the execution of the write operation of the second cell unit and the execution of the write operation of the twelfth cell unit exceeds the reference value, a boundary position between the second group and the third group is changed to a position between the second cell unit and the twelfth cell unit, and the twelfth cell unit is classified into the third group. It is configured as follows:

2. The memory system of claim 1.

9. the memory controller uses the first cell unit to calculate the first correction amount, uses the second cell unit to calculate the second correction amount, and uses the twelfth cell unit to calculate the third correction amount; 9. The memory system of claim 8.

10. A 14th cell unit and a 15th cell unit of the plurality of cell units are classified into the first group, The memory controller includes: The 14th cell unit is used to calculate the first correction amount; When the time difference exceeds the reference value, the cell unit used for calculating the first correction amount is changed from the 14th cell unit to the 15th cell unit. It is configured as follows:

2. The memory system of claim 1.

11. The blocks are classified into a plurality of groups including the first group and the second group, the memory controller is configured to add a fourth group to the plurality of groups when the number of occurrences of the time difference exceeding the reference value in the block exceeds a preset value; 2. The memory system of claim 1.

12. A 16th cell unit among the plurality of cell units is classified into the fourth group; the memory controller is configured to generate information on a fourth correction amount of the read voltage corresponding to the fourth group, position information of the fourth group, and information on the 16th cell unit used in calculating the fourth correction amount; 12. The memory system of claim 11.

13. a memory chip including a block including a plurality of cell units each including a plurality of memory cells; Memory controller and Equipped with A first cell unit of the plurality of cell units is classified into a first group, a second cell unit of the plurality of cell units is classified into a second group, and a third cell unit, a fourth cell unit, a fifth cell unit, and a sixth cell unit of the plurality of cell units are classified into a third group; The memory controller includes: When reading data from the plurality of memory cells of the cell units classified into the first group among the plurality of cell units, a first correction amount of a read voltage is used; When reading data from the plurality of memory cells of the cell units classified into the second group among the plurality of cell units, a second correction amount of the read voltage is used; When reading data from the plurality of memory cells of the cell units classified into the third group among the plurality of cell units, a third correction amount of the read voltage is used; If a time difference between the execution of a write operation of the fourth cell unit and the execution of the write operation of the fifth cell unit exceeds a reference value, a boundary position between the first group and the second group is changed to a position between the fourth cell unit and the fifth cell unit, and the fifth cell unit is classified into the second group. It is configured as follows: Memory system.

14. the memory controller is configured to, when a time difference between performing the write operation of the fifth cell unit and performing the write operation of the sixth cell unit exceeds the reference value, change a boundary position between the second group and the third group to a position between the fifth cell unit and the sixth cell unit and classify the sixth cell unit into the third group; 14. The memory system of claim 13.

15. the memory controller is configured to use the fifth cell unit in calculating the second correction amount and to use the sixth cell unit in calculating the third correction amount; 15. The memory system of claim 14.

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