Package and semiconductor device

Abstract

To suppress defects in bonding wires.SOLUTION: A package includes a base 10 having a mounting area where a semiconductor chip is to be mounted, a frame 12 provided on the base surrounding the mounting area, a first portion to which a first bonding wire that electrically connects the semiconductor chip is to be joined, a second portion that is farther from the mounting area than the first portion, and a first connection portion that connects the first portion and the second portion, and is equipped with a first metal layer 14a provided on an upper surface of the frame, a first insulating layer 16a provided on and in contact with the first connection portion and crossing the first metal layer, and a first lead 18a joined onto the second portion.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a package and a semiconductor device. [Background technology]

[0002] It is known to provide a frame on the base that surrounds a semiconductor chip mounted on the base, and to provide a field through on the base and in an opening of the frame for electrically connecting the semiconductor chip to the outside (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-113284 A Summary of the Invention [Problem to be solved by the invention]

[0004] A package with a field through is expensive because of its complex structure. Therefore, a structure in which a metal layer is provided on the upper surface of the frame, and the bonding wires and leads connected to the semiconductor chip are bonded to the metal layer can be considered. However, solder or the like used to mount the leads on an external substrate can wet the metal layer from the leads and reach the bonding wires. This can cause problems such as the bonding wires breaking.

[0005] The present disclosure has been made in consideration of the above problems, and aims to suppress defects in bonding wires. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a package having a base having a mounting area on which a semiconductor chip is to be mounted, a frame body provided on the base surrounding the mounting area, a first portion to which a first bonding wire that electrically connects the semiconductor chip is to be joined, a second portion that is farther from the mounting area than the first portion, and a first connection portion that connects the first portion and the second portion, the package comprising a first metal layer provided on an upper surface of the frame body, a first insulating layer provided on the first connection portion in contact with the first connection portion and crossing the first metal layer, and a first lead joined onto the second portion.

[0007] One embodiment of the present disclosure is a package having a base having a mounting area in which a semiconductor chip is to be mounted, a frame body provided on the base surrounding the mounting area, a first portion to which a first bonding wire electrically connecting the semiconductor chip is to be joined, and a second portion separated from the first portion on an upper surface of the frame body and farther from the mounting area than the first portion, the package comprising a first metal layer provided on the upper surface of the frame body, a first wiring provided within the frame body and electrically connecting the first portion and the second portion, and a first lead joined onto the second portion, wherein the upper surface of the frame body is exposed from the first metal layer so as to cross the first metal layer in the area separating the first portion and the second portion. Effect of the Invention

[0008] According to the present disclosure, defects in bonding wires can be suppressed. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a cross-sectional view taken along line AA of FIG. [Diagram 3] FIG. 3 is a plan view of the semiconductor device of the first embodiment mounted in a housing. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA of FIG. [Figure 5A]FIG. 5A is a diagram showing a manufacturing method of the first embodiment. [Figure 5B] FIG. 5B is a diagram showing a manufacturing method of the first embodiment. [Figure 6A] FIG. 6A is a diagram showing a manufacturing method of the first embodiment. [Figure 6B] FIG. 6B is a diagram showing a manufacturing method of the first embodiment. [Figure 7A] FIG. 7A is a diagram showing a manufacturing method of the first embodiment. [Figure 7B] FIG. 7B is a diagram showing a manufacturing method of the first embodiment. [Figure 8A] FIG. 8A is a diagram showing a manufacturing method of the first embodiment. [Figure 8B] FIG. 8B is a diagram showing a manufacturing method of the first embodiment. [Figure 9] FIG. 9 is a diagram showing a manufacturing method of the first embodiment. [Figure 10] FIG. 10 is an enlarged plan view of the semiconductor device according to the first comparative example. [Figure 11] FIG. 11 is a cross-sectional view taken along line AA in FIG. [Figure 12] FIG. 12 is an enlarged plan view of the semiconductor device in accordance with the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view taken along line AA in FIG. [Figure 14] FIG. 14 is a plan view of a semiconductor device in accordance with a second embodiment. [Figure 15] FIG. 15 is a cross-sectional view taken along line AA in FIG. [Figure 16] FIG. 16 is a cross-sectional view taken along line BB of FIG. [Figure 17] FIG. 17 is an enlarged cross-sectional view of a semiconductor device according to Comparative Example 2. As shown in FIG. [Figure 18] FIG. 18 is an enlarged cross-sectional view of a semiconductor device in accordance with the second embodiment. [Figure 19] FIG. 19 is a plan view of a semiconductor device in accordance with a third embodiment. [Figure 20] FIG. 20 is a cross-sectional view taken along line AA in FIG. [Figure 21] FIG. 21 is a plan view of a semiconductor device in accordance with a fourth embodiment. [Figure 22] FIG. 22 is a cross-sectional view taken along line AA in FIG. [Diagram 23] FIG. 23 is an enlarged plan view of the semiconductor device in accordance with the fourth embodiment. [Figure 24] FIG. 24 is a cross-sectional view taken along line AA in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a package including a base having a mounting area where a semiconductor chip is to be mounted, a frame provided on the base to surround the mounting area, a first portion to which a first bonding wire that electrically connects the semiconductor chip is to be bonded, a second portion farther from the mounting area than the first portion, and a first connection portion that connects the first portion and the second portion, the package including a first metal layer provided on an upper surface of the frame, a first insulating layer provided on the first connection portion in contact with the first connection portion and crossing the first metal layer, and a first lead bonded onto the second portion. This makes it possible to prevent solder from spreading to the first portion and causing a defect in the first bonding wire. (2) In the above item (1), the frame and the first insulating layer may be mainly composed of ceramics, thereby making it possible to suppress thermal stress. (3) In the above (1) or (2), the wettability of the surface of the first insulating layer with solder may be worse than the wettability of the surface of the first metal layer with solder, thereby making it possible to prevent the solder from spreading over the surface of the first insulating layer. (4) In any of the above (1) to (3), the semiconductor chip may further include a second metal layer provided on the upper surface of the frame, the second metal layer having a third portion to which a second bonding wire electrically connecting the semiconductor chip is to be bonded, a fourth portion farther from the mounting area than the third portion, and a second connection portion connecting the third portion and the fourth portion, the second metal layer being provided on the upper surface of the frame, the second insulating layer being provided on the second connection portion in contact with the second connection portion and crossing the second metal layer, and a second lead bonded onto the fourth portion. This can prevent solder from spreading to the third portion and causing a defect in the second bonding wire. (5) One embodiment of the present disclosure is a package including a base having a mounting area where a semiconductor chip is to be mounted, a frame provided on the base surrounding the mounting area, a first portion to which a first bonding wire for electrically connecting the semiconductor chip is to be bonded, and a second portion separated from the first portion on an upper surface of the frame farther from the mounting area than the first portion, the package including a first metal layer provided on the upper surface of the frame, a first wiring provided within the frame for electrically connecting the first portion and the second portion, and a first lead bonded onto the second portion, the upper surface of the frame being exposed from the first metal layer so as to cross the first metal layer in the region separating the first portion and the second portion. This makes it possible to prevent solder from spreading to the first portion and causing a defect in the first bonding wire. (6) In the above (5), the wettability of the surface of the frame with solder may be worse than the wettability of the surface of the first metal layer with solder, thereby making it possible to prevent the solder from spreading over the surface of the frame layer. (7) In the above (5) or (6), the semiconductor device may further include a third portion to which a second bonding wire electrically connecting the semiconductor chip is to be bonded and a fourth portion farther from the mounting area than the third portion, a second metal layer provided on the upper surface of the frame, a second wiring provided within the frame and electrically connecting the third portion and the fourth portion, and a second lead bonded onto the fourth portion, and the upper surface of the frame may be exposed from the second metal layer so as to cross the second metal layer in a region separating the third portion and the fourth portion. This can prevent solder from spreading to the third portion and causing problems with the second bonding wire. (8) One embodiment of the present disclosure is a semiconductor device including the package according to any one of (1) to (7) above, and the semiconductor chip mounted on the base, thereby enabling the semiconductor chip to be mounted. (9) In the above (8), a resin sealing material may be provided that is bonded to an upper surface of the frame and an upper surface of the first metal layer and seals the semiconductor chip, thereby making it possible to prevent solder from flowing between the first metal layer and the resin sealing material. (10) One embodiment of the present disclosure is a semiconductor device including the package described in (2) above, the semiconductor chip mounted on the base, and a lid that is bonded to the upper surface of the frame and the upper surface of the first insulating layer using a resin adhesive to seal the semiconductor chip, thereby making it possible to prevent solder from flowing between the resin adhesive and the first metal layer.

[0011] [Details of the embodiment of the present disclosure] Specific examples of packages and semiconductor devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] [Example 1] Fig. 1 is a plan view of a semiconductor device according to Example 1. Fig. 2 is a cross-sectional view taken along line AA in Fig. 1. The normal direction of base 10 is defined as the Z direction, the extension direction of a straight line connecting leads 18a and 18b is defined as the X direction, and the direction perpendicular to the X direction and Y direction is defined as the Y direction.

[0013] As shown in FIG. 1 and FIG. 2, in the semiconductor device 100 of the first embodiment, a semiconductor chip 20 and passive element chips 25 and 30 are mounted in a package 80. The package 80 includes a base 10, a frame 12, metal layers 14a and 14b, insulating layers 16a and 16b, leads 18a and 18b, and a bonding layer 36. A mounting area 11 is provided on the upper surface of the base 10. The mounting area 11 is an area where chips such as the semiconductor chip 20 and the passive element chips 25 and 30 should be mounted (i.e., an area where mounting is possible). A reference potential such as a ground potential is supplied to the base 10. A frame 12 is provided on the base 10 so as to surround the mounting area 11. Metal layers 14a and 14b are provided on the upper surface of the frame 12. The metal layer 14a is provided at the center in the Y direction of the side of the frame 12 located in the negative direction in the X direction, and the metal layer 14b is provided at the center in the Y direction of the side of the frame 12 located in the positive direction in the X direction.

[0014] Metal layer 14a includes portions 51a to 53a arranged in the X direction, and metal layer 14b includes portions 51b to 53b arranged in the X direction. Portions 51a and 51b are each closer to mounting area 11, and portions 52a and 52b are each farther from mounting area 11 than portions 51a and 51b. Portion 53a is sandwiched between portions 51a and 52a in the X direction. Portion 53b is sandwiched between portions 51b and 52b in the X direction. Insulating layers 16a and 16b extending in the Y direction are provided on portions 53a and 53b, respectively.

[0015] The insulating layer 16a crosses the metal layer 14a in the Y direction and divides the metal layer 14a into portions 51a and 52a. The insulating layer 16b crosses the metal layer 14b in the Y direction and divides the metal layer 14b into portions 51b and 52b. The lead 18a is provided on the portion 52a of the metal layer 14a. The lead 18b is provided on the portion 52b of the metal layer 14b. The conductive bonding layer 36 bonds the metal layers 14a and 14b to the leads 18a and 18b, respectively. The metal layer 14a and the lead 18a are electrically connected and shorted. The metal layer 14b and the lead 18b are electrically connected and shorted. The lead 18a extends from the portion 52a of the metal layer 14a in the negative direction in the X direction, and the lead 18b extends from the portion 52b of the metal layer 14b in the positive direction in the X direction.

[0016] In the mounting area 11, the semiconductor chip 20, the passive element chips 25 and 30 are mounted in this order in the + direction of the X direction. The semiconductor chip 20 includes a substrate 21 and electrodes 22 to 24. The substrate 21 is, for example, a semiconductor substrate. The electrodes 22 and 23 are provided on the upper surface of the substrate 21. The electrode 24 is provided on the lower surface of the substrate 21. The passive element chip 25 includes a substrate 26 and electrodes 27 and 28. The substrate 26 is, for example, a dielectric substrate. The electrode 27 is provided on the upper surface of the substrate 26, and the electrode 28 is provided on the lower surface of the substrate 26. The passive element chip 30 includes a substrate 31 and electrodes 32 and 33. The substrate 31 is, for example, a dielectric substrate. The electrode 32 is provided on the upper surface of the substrate 31, and the electrode 33 is provided on the lower surface of the substrate 31. The conductive bonding layer 34 bonds the base 10 to the electrodes 24, 28 and 33. The electrodes 24, 28, and 33 are electrically connected to and shorted with the base 10. The bonding wire 40 electrically connects the portion 51a of the metal layer 14a to the electrode 27. The bonding wire 42 electrically connects the electrode 27 to the electrode 22. The bonding wire 44 electrically connects the electrode 23 to the electrode 32. The bonding wire 46 electrically connects the electrode 32 to the portion 51b of the metal layer 14b.

[0017] The base 10 is a plate having electrical conductivity, for example, a copper plate, a metal plate having a laminated structure of a copper layer and a molybdenum layer, or a copper-molybdenum alloy plate. The frame 12 is an insulating layer, for example, a ceramic layer. The ceramic layer is an inorganic insulator layer such as a metal oxide or a metal nitride, and is a sintered body mainly composed of, for example, aluminum oxide (for example, Al2O3). The metal layers 14a and 14b are, for example, a single layer, a laminate, or an alloy layer of tungsten, platinum, silver, or copper. The insulating layers 16a and 16b are inorganic insulator layers such as ceramics or organic insulator layers such as resin, and are, for example, sintered bodies mainly composed of, for example, aluminum oxide (for example, Al2O3). The leads 18a and 18b are metal plates such as copper plates, and have a plating layer such as a gold layer. The bonding layer 36 is a brazing material or a metal paste, and for example, a silver-copper alloy. The bonding layer 34 is, for example, a brazing material or a metal paste, and for example, a gold-tin or silver paste.

[0018] The thickness of the base 10 is, for example, 800 μm to 2000 μm. The thickness of the frame 12 is, for example, 500 μm to 1500 μm. The width of the frame 12 (width in the X direction in FIG. 2) is, for example, 600 μm to 2000 μm. The thickness of the metal layers 14a and 14b is, for example, 10 μm to 100 μm. The thickness of the leads 18a and 18b is, for example, 50 μm to 200 μm. The thickness of the insulating layers 16a and 16b is, for example, 10 μm to 200 μm. The width of the insulating layers 16a and 16b (width in the X direction in FIG. 2) is, for example, 50 μm to 700 μm. In order to ensure the area of ​​portions 51a and 51b to which bonding wires 40 and 46 are bonded, and the area of ​​portions 52a and 52b to which leads 18a and 18b are bonded, the width of insulating layers 16a and 16b can be made 1 / 3 or less of the width of frame 12.

[0019] The semiconductor chip 20 includes, for example, a transistor. The transistor is, for example, a FET (Field Effect Transistor), and as an example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or an LDMOS (Laterally Diffused Metal Oxide Semiconductor). The electrodes 22, 23, and 24 are connected, for example, to a gate, a drain, and a source. The electrode 22 is, for example, an input electrode to which a high-frequency signal is input, and the electrode 23 is, for example, an output electrode to which a high-frequency signal is output. When the semiconductor chip 20 has a GaN HEMT, the substrate 21 is, for example, a silicon carbide substrate or a gallium nitride substrate. The electrodes 22 to 24 are, for example, metal layers such as gold layers.

[0020] The passive element chips 25 and 30 are, for example, capacitors. The substrates 26 and 31 are, for example, dielectric substrates, such as an alumina (aluminum oxide) substrate or a high dielectric ceramic substrate having a higher dielectric constant than an alumina substrate. The electrodes 27, 28, 32 and 33 are, for example, metal layers such as gold layers. The substrate 26 and the electrodes 27 and 28 sandwiching the substrate 26 form a capacitor. The substrate 31 and the electrodes 32 and 33 sandwiching the substrate 31 form a capacitor. The bonding wires 40, 42, 44 and 46 form an inductor. The bonding wire 40, the passive element chip 25 and the bonding wire 42 form an input matching circuit. The bonding wire 44, the passive element chip 30 and the bonding wire 46 form an output matching circuit.

[0021] The high frequency signal input to lead 18a passes through an input matching circuit and is input to electrode 22. The high frequency signal amplified by semiconductor chip 20 passes through an output matching circuit from electrode 23 and is output from lead 18b. When semiconductor device 100 is used in an amplifier circuit for a mobile communication base station, the frequency of the high frequency signal is, for example, 0.5 GHz to 10 GHz.

[0022] In the first embodiment, an example was described in which the semiconductor chip 20 and the passive element chips 25 and 30 are mounted in the mounting area 11 as the semiconductor device 100. However, as long as the semiconductor chip 20 is provided, the passive element chips 25 and 30 do not have to be mounted.

[0023] [Implementation method of Example 1] An example in which the semiconductor device 100 is mounted in a housing will be described. FIG. 3 is a plan view of the semiconductor device of the first embodiment mounted in a housing. FIG. 4 is a cross-sectional view taken along the line AA in FIG. 3. As shown in FIGS. 3 and 4, a substrate 62 is provided on a housing 60. A metal layer 61 is provided on the lower surface of the substrate 62. The metal layer 61 and the housing 60 are joined by a conductive joining layer. An opening 63 is provided in the substrate 62. The opening 63 is, for example, a groove extending in the Y direction. The housing 60 is exposed from the opening 63. Metal layers 64a and 64b are provided on the substrate 62, and the metal layers 64a and 64b are lines extending in the X direction. The metal layers 61, 64a, and 64b sandwiching the substrate 62 function as a transmission line (for example, a microstrip line) for transmitting a high-frequency signal. The base 10 of the semiconductor device 100 is joined to the housing 60 in the opening 63 using a solder layer 65. Leads 18a and 18b are joined to metal layers 64a and 64b using solder 66, respectively.

[0024] The housing 60 is a metal plate such as a copper plate, an aluminum plate, or a stainless steel plate. The substrate 62 is an insulating substrate, such as a resin substrate such as a glass epoxy resin substrate. The metal layers 61, 64a, and 64b are, for example, copper layers or gold layers. The solder layer 65 and the solder 66 are, for example, tin-silver-copper or the like.

[0025] A high frequency signal is input from metal layer 64a to lead 18a and output from lead 18b to metal layer 64b. By joining base 10 to housing 60, heat generated in semiconductor chip 20 passes through base 10 and is released to housing 60.

[0026] [Production method of Example 1] Figures 5A to 9 are diagrams showing a manufacturing method of Example 1. Figures 5A to 8A are plan views, and Figures 5B to 8B and 9 are views corresponding to the AA cross section of Figures 5A to 8A.

[0027] As shown in FIG. 5A and FIG. 5B, an opening 58 is formed in a green sheet to form a frame 12. The green sheet is a ceramic sheet before firing. Metal layers 14a and 14b are formed on the frame 12. A pattern printing method is used to form the metal layers 14a and 14b. A metal layer may be formed on the upper surface of the frame 12 as a circuit pattern other than the metal layers 14a and 14b. Also, the opening 58 may be formed after the metal layers 14a and 14b are formed on the green sheet.

[0028] 6A and 6B, insulating layers 16a and 16b are formed on metal layers 14a and 14b on frame 12. Insulating layers 16a and 16b are formed by applying a paste material containing particles of an inorganic insulator such as aluminum oxide onto frame 12. Then, frame 12 and insulating layers 16a and 16b are fired.

[0029] 7A and 7B, a bonding layer 39 is applied to the lower surface of the frame 12. The bonding layer 39 is sandwiched on the base 10, and the frame 12 is then disposed.

[0030] As shown in Figures 8A and 8B, the leads 18a and 18b, with a bonding layer 36 applied to the underside thereof, are placed on the metal layers 14a and 14b. By heating, the bonding layer 39 is hardened to bond the frame 12 onto the base 10, and the bonding layer 36 is hardened to bond the leads 18a and 18b onto the metal layers 14a and 14b, respectively. The bonding temperature is lower than the firing temperature in Figures 6A and 6B.

[0031] As shown in Fig. 9, a metal layer 35 is formed on the exposed surfaces of the metal layers 14a, 14b and the leads 18a and 18b, for example, by plating. The metal layer 35 is a metal with good solder wettability, for example, a gold plating layer. The metal layer 35 is not shown in Figs. 1 and 2. In this manner, the package of Example 1 is manufactured.

[0032] 1 and 2, the semiconductor chip 20 and the passive element chips 25 and 30 are bonded to the mounting area 11 using the bonding layer 34. The temperature at which the semiconductor chip 20 and the passive element chips 25 and 30 are bonded is lower than the bonding temperature in FIGS. 8A and 8B. Then, the bonding wires 40, 42, 44 and 46 are formed. In this manner, the semiconductor device 100 of the first embodiment is manufactured.

[0033] [Comparative Example 1] FIG. 10 is an enlarged plan view of the semiconductor device according to Comparative Example 1, and is an enlarged plan view of the vicinity of the metal layer 14a. FIG. 11 is a cross-sectional view taken along the line AA in FIG. 10. As shown in FIGS. 10 and 11, when mounting the semiconductor device 110 of Comparative Example 1, the lead 18a is soldered to the metal layer 64a in FIGS. 3 and 4, for example. At this time, a metal layer 35 is provided on the surface of the lead 18a and the metal layer 14a. The metal layer 35 is, for example, a gold layer, and the wettability of the solder 66 is good. For this reason, as indicated by the arrow 55, the molten solder 66 may wet and spread over the metal layer 35 on the surface of the lead 18a. Furthermore, the solder 66 wets and spreads over the metal layer 35 on the surface of the metal layer 14a, and reaches the location where the bonding wire 40 is joined. This causes a defect in the bonding wire 40. For example, if the bonding wire 40 is a gold wire, the gold and the solder react with each other, causing the bonding wire 40 to break.

[0034] [Description of Example 1] FIG. 12 is an enlarged plan view of the semiconductor device according to the first embodiment, and is an enlarged plan view of the vicinity of the metal layer 14a. FIG. 13 is a cross-sectional view taken along the line AA in FIG. 12. As shown in FIGS. 12 and 13, in the package 80 according to the first embodiment, a bonding wire 40 (first bonding wire) that electrically connects the semiconductor chip 20 is bonded to a portion 51a (first portion) of the metal layer 14a (first metal layer). That is, the portion 51a is a portion to which the bonding wire 40 should be bonded (a portion that can be bonded). A lead 18a (first lead) is bonded onto a portion 52a (second portion) of the metal layer 14a. A portion 53a (first connection portion) of the metal layer 14a connects the portions 51a and 52a. An insulating layer 16a (first insulating layer) is provided on and in contact with the portion 53a, and crosses the metal layer 14a. As a result, the insulating layer 16a functions as a barrier or dam for the solder 66, which prevents the solder 66 from spreading to the portion 51a and causing a defect in the bonding wire 40, as in Comparative Example 1 in Figures 10 and 11. In addition, the bonding wire 40 and the lead 18a are electrically connected and short-circuited.

[0035] The frame body 12 and the insulating layer 16a are mainly composed of ceramics. This allows the frame body 12 and the insulating layer 16a to have better high-frequency characteristics than resin. Since ceramics has a smaller linear expansion coefficient than resin, the thermal stress between the metal layer 14a and the insulating layer 16a can be reduced. Furthermore, since the linear expansion coefficients of the frame body 12 and the insulating layer 16a are close to each other, the thermal stress can be reduced. The frame body 12 and the insulating layer 16a are mainly composed of the same material. This allows the linear expansion coefficients of the frame body 12 and the insulating layer 16a to be almost the same, and the thermal stress can be reduced. Furthermore, the frame body 12 and the insulating layer 16a are mainly composed of aluminum oxide (alumina). This allows the frame body 12 and the insulating layer 16a to have better high-frequency characteristics. The frame body 12 and the insulating layer 16a may contain an organic insulator or an inorganic insulator other than the main component, such as a binder, in addition to the main component. The content of the main component in the frame 12 and the insulating layer 16a is, for example, 50 mol % or more, and 80 mol % or more.

[0036] The wettability of the surface of the insulating layer 16a with the solder 66 is poorer than the wettability of the surface of the metal layer 14a with the solder 66. This makes it possible to prevent the solder 66 from spreading over the surface of the insulating layer 16a. Thus, the insulating layer 16a can function as a weir or dam for the solder 66.

[0037] As shown in FIG. 1 and FIG. 2, in the metal layer 14b, a bonding wire 46 (second bonding wire) that electrically connects the semiconductor chip 20 is bonded to a portion 51b (third portion) of the metal layer 14b (second metal layer). A lead 18b (second lead) is bonded to a portion 52b (fourth portion) of the metal layer 14b. A portion 53b (second connection portion) of the metal layer 14b connects the portions 51b and 52b. An insulating layer 16b (second insulating layer) is provided on the portion 53b in contact with the portion 53b and crosses the metal layer 14b. This prevents the solder 66 from spreading to the portion 51b and causing a defect in the bonding wire 46, as in the case of the metal layer 14a. In this way, when a plurality of metal layers 14a and 14b are provided, the insulating layers 16a and 16b can be provided on the plurality of metal layers 14a and 14b, respectively.

[0038] [Example 2] FIG. 14 is a plan view of a semiconductor device according to a second embodiment. FIGS. 15 and 16 are a cross-sectional view taken along line AA and a cross-sectional view taken along line BB of FIG. 14, respectively. As shown in FIGS. 14 to 16, a semiconductor device 102 according to a second embodiment includes a package 82. The package 82 includes a lid 38. The lid 38 includes a frame portion 38a and a ceiling portion 38b. The frame portion 38a surrounds the mounting area 11 in a plan view. The bonding layer 37 bonds the lower surface of the frame portion 38a to the upper surface of the frame 12 and the upper surfaces of the insulating layers 16a and 16b. The ceiling portion 38b is provided so as to cover the mounting area 11. The base 10, the frame 12, and the lid 38 hermetically seal the semiconductor chip 20 and the passive element chips 25 and 30 in the gap.

[0039] The lid 38 is an insulating plate made of, for example, ceramics or the like. The lid 38 may also be a metal plate. The bonding layer 37 is a resin adhesive made of, for example, epoxy resin or the like. As shown in Figures 15 and 16, the height of the top surface of the frame 12 and the top surfaces of the insulating layers 16a and 16b are different. The bonding layer 37 can absorb the height difference between the top surface of the frame 12 and the top surfaces of the insulating layers 16a and 16b.

[0040] [Comparative Example 2] Fig. 17 is an enlarged cross-sectional view of a semiconductor device according to Comparative Example 2. As shown in Fig. 17, in a semiconductor device 112 of Comparative Example 2, an insulating layer 16a is not provided, and a lid 38 is bonded onto a metal layer 14a using a bonding layer 37. The other configurations are the same as those of Example 2. As indicated by an arrow 55, solder 66 flows along the surface of the lead 18a and the metal layer 14a. If the adhesion between the metal layer 14a and the bonding layer 37 is high, the bonding layer 37 becomes a weir or dam for the solder 66.

[0041] However, the adhesion between the metal layer 14a, such as a gold layer, and the bonding layer 37, such as a resin adhesive, is low. In particular, the bonding wire 40 is bonded to the upper surface of the metal layer 14a. For this reason, the upper surface of the metal layer 14a is highly flat so as to improve the bonding between the bonding wire 40 and the metal layer 14a. This leads to a further decrease in adhesion between the metal layer 14a and the bonding layer 37. For this reason, when the temperature is repeatedly increased and decreased, the metal layer 14a and the bonding layer 37 may peel off from each other. In particular, the linear expansion coefficient of gold is 14×10 -6 K -1 , the linear expansion coefficient of alumina is 7×10 -6 K -1 , the linear expansion coefficient of epoxy resin adhesive is 30×10 -6 K -1 From 80×10 -6 K -1Thus, the resin adhesive has a larger linear expansion coefficient than metal. As a result, when the temperature rises and falls repeatedly, a large thermal stress is applied between the metal layer 14a and the bonding layer 37, and the bonding layer 37 is likely to peel off from the metal layer 14a. When the bonding layer 37 peels off, the solder 66 spreads between the metal layer 14a and the bonding layer 37 as shown by the dashed ellipse 56, and the solder 66 may reach the bonding portion of the bonding wire 40. This causes the bonding wire 40 to break.

[0042] [Explanation of Example 2] FIG. 18 is an enlarged cross-sectional view of a semiconductor device according to a second embodiment. As shown in FIG. 18, in the semiconductor device 102 of the second embodiment, an insulating layer 16a is provided on a metal layer 14a, and a bonding layer 37 is provided on the insulating layer 16a. The lid 38 is bonded to the upper surface of the frame 12 and the upper surface of the insulating layer 16a using a resin adhesive as the bonding layer 37. The insulating layer 16a is made of ceramics, and when the frame 12 and the insulating layer 16a are fired with the metal layer 14a sandwiched therebetween as shown in FIG. 8A and FIG. 8B, the adhesion between the metal layer 14a and the insulating layer 16a is high. In addition, the upper surface of the insulating layer 16a is highly uneven, and the adhesion between the insulating layer 16a and the bonding layer 37 is high due to the anchor effect. Furthermore, when the main components of the frame body 12 and the insulating layer 16a are the same, the linear expansion coefficients of the frame body 12 and the insulating layer 16a are almost the same, and the difference in the linear expansion coefficients of the metal layer 14a and the insulating layer 16a is smaller than the difference in the linear expansion coefficients between the metal layer 14a and the bonding layer 37. As a result, the thermal stress between the metal layer 14a and the insulating layer 16a is smaller than the thermal stress between the metal layer 14a and the bonding layer 37 in Comparative Example 2. Therefore, the insulating layer 16a is less likely to peel off from the metal layer 14a. As a result, the insulating layer 16a becomes a dam or a barrier for the solder 66. Therefore, it is possible to prevent the solder 66 from reaching the bonding wire 40 and causing the bonding wire 40 to break. In Example 2, as shown in FIG. 14, an example has been described in which the frame body portion 38a and the insulating layers 16a and 16b overlap in a plan view, but the frame body portion 38a and the insulating layers 16a and 16b do not have to overlap.

[0043] The lid 38 may be made of ceramics in order to reduce thermal stress in the frame 12, the insulating layer 16a, and the lid 38. The main component of the lid 38 may be the same as the main components of the frame 12 and the insulating layer 16a. The main component of the lid 38 is, for example, aluminum oxide.

[0044] [Example 3] Example 3 is an example using a potting resin. FIG. 19 is a plan view of the semiconductor device according to Example 3. FIG. 20 is a cross-sectional view taken along the line AA of FIG. 19. In FIG. 19, the resin sealing material 45 is indicated by a broken line. As shown in FIGS. 19 and 20, in the semiconductor device 104 of Example 3, the resin sealing material 45 is potted on the package 80. The resin sealing material 45 is bonded to the upper surface of the frame 12 and the upper surfaces of the metal layers 14a and 14b to seal the semiconductor chip 20. The resin sealing material 45 is, for example, an epoxy resin, a urethane resin, or a silicon resin. The potted resin sealing material 45 is softer than the lid 38 of Example 2. Therefore, the stress between the resin sealing material 45 and the frame 12 is relaxed. However, the adhesion between the resin sealing material 45 and the metal layer 14a is low. Therefore, if the insulating layers 16a and 16b are not provided, the solder 66 will get between the metal layers 14a and 14b and the resin sealing material 45, and the bonding wire 40 will be easily broken. Therefore, by providing the insulating layers 16a and 16b, the solder 66 can be prevented from flowing between the metal layers 14a and 14b and the resin sealing material 45.

[0045] [Example 4] Example 4 is an example in which a multilayer printed circuit board is used for the frame. FIG. 21 is a plan view of the semiconductor device according to Example 4. FIG. 22 is a cross-sectional view taken along line AA of FIG. 21. As shown in FIGS. 21 and 22, the semiconductor device 106 of Example 4 includes a package 84. The package 84 includes a multilayer board 15. The multilayer board 15 includes laminated insulating layers 15a to 15c. The insulating layer 15a is the lowest insulating layer and corresponds to the base 10. A metal plate 15d (copper coin) is embedded in the insulating layer 15a. The metal plate 15d corresponds to the mounting area 11. The semiconductor chip 20 and the passive element chips 25 and 30 are mounted on the metal plate 15d. A metal layer 13 is provided on the lower surface of the insulating layer 15a and the metal plate 15d. The insulating layers 15b and 15c correspond to the frame 12. The metal layers 48a and 48b are provided between the insulating layers 15b and 15c. Metal layers 14a and 14b are provided on the upper surface of insulating layer 15c.

[0046] FIG. 23 is an enlarged plan view of the semiconductor device according to the fourth embodiment. FIG. 24 is a cross-sectional view taken along the line AA in FIG. 23. In FIG. 23, the through-hole 47 is indicated by a broken line. As shown in FIGS. 23 and 24, the metal layer 14a is provided in the portions 51a and 52a, but is not provided in the portion 53a. In the portion 53a, the insulating layer 15c is exposed from the metal layer 14a. In the portion 53a, the metal layer 48a is provided under the insulating layer 15c. Both ends of the metal layer 48a in the X direction are electrically connected and short-circuited to the metal layers 14a of the portions 51a and 52a, respectively, via the metal layer in the through-hole 47 penetrating the insulating layer 15c. As a result, the portions 51a and 52a are electrically connected via the metal layer 48a.

[0047] The wettability of the solder on the surface of insulating layer 15c of portion 53a is poorer than the wettability of the solder on the surface of metal layer 35. As indicated by arrow 55, even if solder 66 spreads over lead 18a and metal layer 35 on the surface of metal layer 14a, solder 66 does not spread over the upper surface of insulating layer 15c. As a result, solder 66 does not spread over portion 51a, and disconnection of bonding wire 40 can be suppressed.

[0048] The insulating layers 15a to 15c are resin layers such as glass epoxy resin. The metal plate 15d is a copper plate. The metal layer 48a is a single layer, a laminated layer, or an alloy layer of silver, gold, or copper. The other configurations are the same as those in the first embodiment, and the description will be omitted.

[0049] According to the fourth embodiment, the portions 51a and 52a of the metal layer 14a are separated on the upper surface of the frame body 12, and the upper surface of the frame body 12 is exposed from the metal layer 14a so as to cross the metal layer 14a in the region separating the portions 51a and 52a. The metal layer 48a (first wiring) electrically connects the portions 51a and 52a. In this manner, by using the upper surface of the frame body 12 as a weir or dam for the solder 66, it is possible to prevent the solder 66 from spreading to the bonding wire 40 and causing a defect in the bonding wire 40. In addition, the metal layer 48a electrically connects the bonding wire 40 and the lead 18a to each other, resulting in a short circuit.

[0050] The wettability of the surface of the frame body 12 with the solder 66 is poorer than the wettability of the surface of the metal layer 14a with the solder 66. This makes it possible to prevent the solder 66 from spreading over the surface of the frame body 12. Thus, the frame body 12 can function as a weir or dam for the solder 66.

[0051] 21 and 22, in the metal layer 14b, the portions 51b and 52b of the metal layer 14b are separated on the upper surface of the frame body 12, and the upper surface of the frame body 12 is exposed from the metal layer 14b so as to cross the metal layer 14b in the region separating the portions 51b and 52b. The metal layer 48b (second wiring) electrically connects the portions 51b and 52b. This prevents the solder 66 from spreading to the portion 51b and causing a defect in the bonding wire 46, as in the case of the metal layer 14a.

[0052] Even when a multilayer printed circuit board is used for the frame as in Example 4, the lid 38 may be bonded to the upper surface of the frame 12 and the upper surface of the insulating layer 15c to seal the semiconductor chip 20 as in Example 2. This makes it possible to prevent the solder 66 from passing between the metal layers 14a and 14b and the lid 38 and reaching the bonding wires 40 and 46.

[0053] Also, when a multilayer printed circuit board is used for the frame body 12, as in Example 3, the resin sealing material 45 may be bonded to the upper surface of the frame body 12 and the upper surfaces of the metal layers 14a and 14b to seal the semiconductor chip 20. This makes it possible to prevent the solder 66 from passing between the metal layers 14a and 14b and the resin sealing material 45 and reaching the bonding wires 40 and 46.

[0054] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the above meaning, and is intended to include all modifications within the scope and meaning equivalent to the claims. [Explanation of symbols]

[0055] 10 Base 11 Mounting area 12 Frame 13, 14a, 14b, 35, 61, 64a, 64b metal layer 15 Multilayer board 15a, 15b, 15c, 16a, 16b Insulating layers 18a, 18b Lead 20. Semiconductor Chips 21, 26, 31 Board 22, 23, 24, 27, 28, 32, 33 electrode 34, 36, 37, 39 Bonding layer 38 Lid 38a Frame body part 38b Ceiling 40, 42, 44, 46 Bonding wire 45 Resin sealing material 47 Through Hole 48a, 48b metal layer 51a, 51b, 52a, 52b, 53a, 53b parts 55 Arrow 58, 63 aperture 65 Solder layer 66 Solder 80, 82, 84 Packages 100, 102, 104, 106, 110, 112 Semiconductor device

Claims

1. a base having a mounting area on which a semiconductor chip is to be mounted; a frame provided on the base to surround the mounting area; a first metal layer provided on an upper surface of the frame body, the first metal layer having a first portion to which a first bonding wire that electrically connects the semiconductor chip is to be bonded, a second portion that is farther from the mounting area than the first portion, and a first connection portion that connects the first portion and the second portion; a first insulating layer provided on and in contact with the first connecting portion and crossing the first metal layer; a first lead bonded onto the second portion; A package comprising:

2. 2. The package according to claim 1, wherein the frame and the first insulating layer are mainly composed of ceramics.

3. 3. The package according to claim 1, wherein the surface of said first insulating layer has poorer wettability with solder than the surface of said first metal layer.

4. a second metal layer provided on an upper surface of the frame body, the second metal layer having a third portion to which a second bonding wire that electrically connects the semiconductor chip is to be bonded, a fourth portion that is farther from the mounting area than the third portion, and a second connection portion that connects the third portion and the fourth portion; a second insulating layer provided on the second connection portion and in contact with the second connection portion and crossing the second metal layer; a second lead bonded onto the fourth portion; 3. The package of claim 1 or claim 2, comprising:

5. a base having a mounting area on which a semiconductor chip is to be mounted; a frame provided on the base to surround the mounting area; a first metal layer provided on the upper surface of the frame body, the first metal layer having a first portion to which a first bonding wire that electrically connects the semiconductor chip is to be bonded, and a second portion that is farther from the mounting area than the first portion and is separated from the first portion on the upper surface of the frame body; a first wiring provided within the frame and electrically connecting the first portion and the second portion; a first lead bonded onto the second portion; Equipped with A package in which an upper surface of the frame is exposed from the first metal layer so as to cross the first metal layer in a region separating the first portion and the second portion.

6. 6. The package according to claim 5, wherein the surface of said frame has poorer wettability with solder than the surface of said first metal layer.

7. a second metal layer provided on an upper surface of the frame, the second metal layer having a third portion to which a second bonding wire that electrically connects the semiconductor chip is to be bonded and a fourth portion that is farther from the mounting area than the third portion; a second wiring provided within the frame and electrically connecting the third portion and the fourth portion; a second lead bonded onto the fourth portion; Equipped with 7. The package according to claim 5, wherein an upper surface of the frame is exposed from the second metal layer so as to cross the second metal layer in a region separating the third portion and the fourth portion.

8. A package according to any one of claims 1, 2, 5 and 6; the semiconductor chip mounted on the base; A semiconductor device comprising:

9. The semiconductor device according to claim 8 , further comprising a resin sealing material bonded to an upper surface of the frame and an upper surface of the first metal layer, sealing the semiconductor chip.

10. A package according to claim 2; the semiconductor chip mounted on the base; a semiconductor device comprising a lid that is bonded to an upper surface of the frame and an upper surface of the first insulating layer by a resin adhesive and seals the semiconductor chip;

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