Display unit

Abstract

To provide a display unit that can prevent flicker from being recognized even when it makes a transition from a low refresh rate state to a high refresh rate state.SOLUTION: A display unit comprises a signal line drive circuit, and a display control circuit. When changing a refresh rate from R1 to R2 at a higher frequency than R1, the display control circuit provides a third period P3 between a first period P1 where the refresh rate is R1 and a second period P2 where the refresh rate is R2. In the third period P3, the display control circuit rewrites an image to be displayed on a display panel while inverting the polarity of pixel voltage Vp between a positive polarity and a negative polarity at a frequency of R3 higher than R2.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a display device. [Background technology]

[0002] The display device described in Patent Document 1 is configured to be able to change a refresh rate, which is a frequency at which the screen of the display unit is rewritten (refreshed). This display device transitions from a normal period, which is a period during which normal driving is performed, to a pause period, which is a period during which pause driving is performed with a refresh rate lower than that of the normal driving. In this display device, a transition period is provided between the normal period and the pause period, during which the screen of the display unit is refreshed at a refresh rate between the refresh rate of the normal driving and the refresh rate of the pause driving. In this display device, the above-mentioned transition period is also provided between the pause period and the normal period when transitioning from the pause period to the normal period. Each of the normal period, the pause period, and the transition period is provided with a period during which positive polarity refreshing is performed and a period during which negative polarity refreshing is performed. The proportion of the period during which positive polarity refreshing is performed in the transition period is equal to the proportion of the period during which negative polarity refreshing is performed in the transition period. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2013 / 115088 Summary of the Invention [Problem to be solved by the invention]

[0004] In the display device described in Patent Document 1, the refresh rate during the idle period is low, so when the display device switches to the transition period at any timing during the idle period, the display unit switches to the transition period in a state in which it is charged to either positive or negative polarity (a state in which the polarity of the charge is biased, hereinafter referred to as "biased charge"). Therefore, in the transition period after the switch, a positive polarity refresh and a negative polarity refresh are performed in a state in which the charge is biased. As a result, a difference occurs between the execution voltage in the positive polarity refresh and the execution voltage in the negative polarity refresh. As a result, when the positive polarity refresh and the negative polarity refresh are performed alternately, the luminance difference becomes large in the interval between two frame periods (a frequency half the refresh rate), and flicker (half flicker) may be visible.

[0005] Therefore, the present disclosure has been made to solve the above-mentioned problems, and aims to provide a display device that is capable of preventing flicker from being noticed even when the refresh rate transitions from a low state to a high state. [Means for solving the problem]

[0006] In order to solve the above problem, a display device according to one embodiment includes a display panel for displaying an image, the display panel including a pixel electrode and a common electrode for forming an electric field between the pixel electrode, a drive circuit for supplying a pixel voltage to the pixel electrode, and a control circuit for controlling a refresh rate, which is a frequency at which the drive circuit supplies the pixel voltage to the pixel electrode and at which an image to be displayed on the display panel is rewritten, wherein when the refresh rate is changed from a first frequency to a second frequency higher than the first frequency, the control circuit provides a third period between a first period in which the image to be displayed on the display panel is rewritten with the first frequency and a second period in which the image to be displayed on the display panel is rewritten with the second frequency, and during the third period, the control circuit rewrites the image to be displayed on the display panel by alternately supplying a pixel voltage having a positive polarity with respect to a common voltage supplied to the common electrode and a pixel voltage having a negative polarity with respect to the common voltage at a third frequency higher than the second frequency, and a third frequency of 60 Hz or more when the second frequency is less than 20 Hz. Effect of the Invention

[0007] Here, in the third period, if the charge bias generated in the first period remains in the display panel, a difference occurs between the execution voltage in the positive polarity refresh and the execution voltage in the negative polarity refresh, and the luminance changes at a frequency half the third frequency. In addition, when the refresh rate is 10 Hz or more, the higher the frequency, the less likely a person is to see the flicker. Therefore, according to the above configuration, when transitioning from the first period, in which the refresh rate is low, to the second period, in which the refresh rate is high, the refresh rate in the third period can be made higher than the refresh rate in the second period. As a result, the frequency half the third frequency is higher than the frequency half the second frequency (a frequency of 10 Hz or more), so that even if the charge bias remains in the display panel in the third period, it is possible to prevent the flicker from being seen. In addition, in the third period, the polarity of the pixel voltage is inverted at a high frequency, so that it is possible to reduce the charge bias in the display panel during the third period. As a result, it is possible to prevent the flicker from being seen during the second period following the third period. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a configuration of a display system 100a including a display device 100 according to an embodiment. [Diagram 2] FIG. 2 is a circuit diagram showing the configuration of a pixel. [Diagram 3] FIG. 3 is a diagram showing the relationship between the common voltage Vcom and the pixel voltage Vp. [Figure 4] FIG. 4 is a diagram showing a schematic diagram of a change in luminance in the third period P3. [Diagram 5] FIG. 5 is a diagram for explaining the relationship between the frequency of the luminance change (light / dark) and the flicker rate. [Figure 6] FIG. 6 is a diagram showing the relationship between the refresh rate in the first period P1 and the human visual sensitivity in the period after the first period P1. [Figure 7]FIG. 7 is a diagram for explaining the relationship between the refresh rate in the second period P2 and the human visual sensitivity in the case where the third period P3 is not provided. [Figure 8] FIG. 8 is a diagram for explaining the relationship between the refresh rate in the third period P3 and the human visual sensitivity and power consumption. [Figure 9] FIG. 9 is a diagram for explaining the relationship between the length of the third period P3 and the human visual sensitivity and power consumption. [Figure 10] FIG. 10 is a diagram showing the relationship between the refresh rate R1 of the first period P1 and the sufficient length of the third period P3. [Figure 11] FIG. 11 is a diagram showing the measurement results of the flicker rate of a display device according to a comparative example. [Figure 12] FIG. 12 is a diagram showing the measurement results of the flicker rate of a display device according to an example of this embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present disclosure will be described based on the drawings. Note that the present disclosure is not limited to the following embodiments, and appropriate design changes can be made within the scope of the configuration of the present disclosure. In the following description, the same parts or parts having similar functions are commonly designated by the same reference numerals in different drawings, and repeated description thereof will be omitted. In addition, each configuration described in the embodiment and the modified example may be appropriately combined or modified within the scope of the gist of the present disclosure. In addition, in order to make the description easier to understand, in the drawings referred to below, the configuration is shown simplified or schematic, and some components are omitted.

[0010] [Overall configuration of the display system] FIG. 1 is a block diagram showing a configuration of a display system 100a including a display device 100 in this embodiment. As shown in FIG. 1, the display system 100a includes the display device 100 and a system control circuit 101. The system control circuit 101 is a host controller. The system control circuit 101 supplies power to the display device 100 and also supplies a video signal and a control signal. The display device 100 is a device that displays a video based on a video signal. The video signal includes information on the pixel values ​​(grayscales) of R, G, and B. The control signal includes a signal that instructs the display panel 1 to be driven in a normal mode or to be driven in a low-frequency mode. The display device 100 is, for example, a display monitor, a personal computer, a tablet terminal, a smartphone, a smart watch, or a television device. The display device 100 is, for example, a liquid crystal display, a micro LED display, or an organic EL display. The system control circuit 101 may be configured as a device integrated with the display device 100, or may be configured as a device separate from the display device 100. Furthermore, the display device 100 may employ any of the driving methods such as the FFS method, the IPS method, the TN method, or the VA method.

[0011] The "normal mode" is a state in which the display device 100 displays an image and provides the displayed image to the user, and in this embodiment, it means a state in which the refresh rate is 60 Hz (R2). The "low frequency mode" is a mode in which the refresh rate is lower than the frequency in the normal mode when the display device 100 displays a still image or when the display device 100 does not detect a user (for example, when there is no input operation from the user for a predetermined period of time, or when the user is not present within the shooting range of the camera (not shown) of the display system 100a). The "refresh rate" is the frequency at which the pixel voltage Vp (see FIG. 3) is supplied to the pixel electrode 16 (see FIG. 2), and is the frequency at which the image displayed on the display panel 1 is rewritten. By lowering the refresh rate, the number of times the image is rewritten can be reduced, and power consumption can be reduced. In this embodiment, the refresh rate in the low frequency mode is 1 Hz (R1).

[0012] As shown in FIG. 1, the display device 100 includes a display panel 1, a display control circuit 2, and a power supply circuit 3. The display panel 1 uses power from the power supply circuit 3 to display an image based on a command from the display control circuit 2. The display control circuit 2 includes a processor (integrated circuit) that executes each control process of the display device 100. The display control circuit 2 receives a video signal and a control signal from the system control circuit 101, and generates a gate control signal GC and a source control signal SC based on the video signal. The display control circuit 2 supplies a common voltage Vcom to a common electrode 17 (see FIG. 2), which will be described later. The power supply circuit 3 converts the voltage of the power supplied from the system control circuit 101 into a voltage suitable for the display control circuit 2, and supplies the converted power to the display control circuit 2.

[0013] The display panel 1 includes a scanning line driving circuit 11, a signal line driving circuit 12, a plurality of gate lines 13, and a plurality of source lines 14. The number of the plurality of gate lines 13 is a natural number m. The number of the plurality of source lines 14 is a natural number n. The plurality of gate lines 13 are arranged to intersect with the plurality of source lines 14. As shown in FIG. 2, a thin film transistor 15 and a pixel electrode 16 are arranged in an area (pixel) defined by the plurality of gate lines 13 and the plurality of source lines 14. The gate line 13 is connected to a gate electrode of the thin film transistor 15. The source line 14 is connected to a source electrode of the thin film transistor 15. The pixel electrode 16 is connected to a drain electrode of the thin film transistor 15. The display panel 1 is provided with a common electrode 17 that forms an electric field between the pixel electrode 16 and the gate line 13. The common electrode 17 is arranged corresponding to the plurality of pixel electrodes 16 (provided in common). The display panel 1 is provided with a common wiring 18 that connects the common electrode 17 to the display control circuit 2.

[0014] The scanning line driving circuit 11 sequentially supplies gate signals to the m gate lines 13 (in the order of GL1, GL2, GL3, . . . GLm-1, and GLm) within one frame period. "One frame period" is a period synchronized (matching) with the time interval at which a vertical synchronization signal is output from the display control circuit 2. The signal line driving circuit 12 supplies source signals to the n source lines 14, respectively. The signal line driving circuit 12 inverts the polarity of the source signals supplied to the source lines 14 for each frame period. For example, when the polarity of the source signals supplied to the odd-numbered source lines 14 (SL1, SL3, . . . ) of the n source lines 14 is positive, the signal line driving circuit 12 sets the polarity of the source signals supplied to the even-numbered source lines 14 (SL2, SL4, . . . ) of the n source lines 14 to negative. In the next frame period, the polarity of the source signal supplied to the odd-numbered source lines 14 is negative, and the polarity of the source signal supplied to the even-numbered source lines 14 is positive. Note that in this disclosure, "polarity" is described as meaning the polarity of the voltage (either a positive voltage or a negative voltage) based on the voltage Vcom (see FIG. 3).

[0015] Fig. 3 is a diagram showing the relationship between the common voltage Vcom and the pixel voltage Vp. When a gate signal is supplied to the gate electrode of the thin film transistor 15, the source signal supplied to the source electrode of the thin film transistor 15 is supplied to the pixel electrode 16 via the drain electrode. As a result, as shown in Fig. 3, the polarity of the pixel voltage Vp, which is the voltage supplied to the pixel electrode 16, is inverted every frame period (Tf1, Tf2, or Tf3). In Fig. 3, positive polarity is indicated as "+" and negative polarity is indicated as "-".

[0016] 3, the display control circuit 2 controls the refresh rate. In this embodiment, when the display control circuit 2 receives a control signal from the system control circuit 101 to switch from the low-frequency mode to the normal mode, the display control circuit 2 inserts a third period P3, which is a transition period, between a first period P1 in which the display control circuit 2 operates in the low-frequency mode (refresh rate is R1) and a second period P2 in which the display control circuit 2 operates in the normal mode (refresh rate is R2). In the third period P3, the display control circuit 2 rewrites the image displayed on the display panel 1 while inverting the polarity of the pixel voltage Vp between positive polarity "+" and negative polarity "-" at a refresh rate R3 that is a higher frequency than the refresh rate R2 of the second period P2. In this embodiment, the refresh rate R3 is 120 Hz.

[0017] The display control circuit 2 supplies a voltage Vcom to the common electrode 17 via the common wiring 18. When the pixel voltage Vp is supplied to the common electrode 17, electric charges of the polarity of the pixel voltage Vp are accumulated. This causes the voltage Vcom of the common electrode 17 to change (electric charge bias occurs) as shown in Fig. 3. The amount of change in the voltage Vcom of the common electrode 17 is larger as one frame period is longer (electric charge bias becomes larger).

[0018] 3, in the third period P3, if the charge imbalance that occurred in the first period P1 remains in the display panel 1, a difference occurs between the effective voltage Ve1 in the positive polarity refresh and the effective voltage Ve2 in the negative polarity refresh. This causes a change in luminance with a cycle twice the frame period Tf2 of the third period P3 (half the frequency of the refresh rate R3), as shown in FIG.

[0019] FIG. 5 is a diagram for explaining the relationship between the frequency of the luminance change (light and dark) and the flicker rate. For the relationship between the light and dark frequency and the flicker rate, for example, the International Electrotechnical Commission (IEC) standard 62341-6-3:2017 errata 1 is referred to. The "flicker rate" is a value indicating that the higher the value, the easier it is for a person to see the flicker, and the lower the value, the harder it is for a person to see the flicker. Here, the frequency of half the refresh rate R3 (120 Hz) is 60 Hz, and the flicker rate is low (low enough that a person cannot recognize the flicker). Thus, in this embodiment, when transitioning from the first period P1 in which the refresh rate R1 is low to the second period P2 in which the refresh rate R2 is high, the third period P3 in which the refresh rate R3 is higher than R2 is inserted between the first period P1 and the second period P2. This makes it possible to prevent flicker from being seen even if the charge imbalance remains in the display panel 1 in the third period P3. 3, in the third period P3, the polarity of the pixel voltage Vp is inverted at a high frequency, so that it is possible to reduce the bias of the electric charges in the display panel 1 during the third period P3. As a result, it is possible to prevent flicker from being visible in the second period P2.

[0020] Moreover, the refresh rate R2 is not limited to 60 Hz, and the refresh rate R3 is not limited to 120 Hz. As shown in Fig. 5, when the frequency of the change in luminance is 10 Hz or more, the flicker rate decreases as the frequency increases. Therefore, if the refresh rate R2 is 20 Hz or more and the refresh rate R3 is higher than 20 Hz, it is possible to prevent flicker from being seen, compared to the case where the third period is not provided.

[0021] FIG. 6 is a diagram showing the relationship between the refresh rate of the first period P1 and the human visual sensitivity in the period after the first period P1. The "human visual sensitivity" indicates the magnitude of flickering that a person perceives when viewing light and dark at a constant cycle. The higher the human visual sensitivity, the greater the flickering that the person perceives. FIG. 6 shows the human visual sensitivity immediately after the first period P1 is shifted to a period with a refresh rate of 60 Hz. As shown in FIG. 6, when the refresh rate of the first period P1 is a frequency of 10 Hz or less, the human visual sensitivity increases immediately after the period with a refresh rate of 60 Hz. Therefore, when the technology disclosed herein is applied (the third period is provided) when the refresh rate R1 is 10 Hz or less, the effect of preventing flickering from being viewed is increased.

[0022] 7 is a diagram for explaining the relationship between the refresh rate of the second period P2 and human visibility when the third period P3 is not provided. As shown in FIG. 7, when the third period P3 is not provided, when the refresh rate of the second period P2 is a frequency of 90 Hz or less, the human visibility of the second period P2 is high. Therefore, when the technology disclosed herein is applied when the refresh rate R2 is 90 Hz or less, the effect of preventing flicker from being visible is increased.

[0023] FIG. 8 is a diagram for explaining the relationship between the refresh rate of the third period P3 and the human visual sensitivity and power consumption. As shown in FIG. 8, in the range in which the refresh rate of the third period P3 is 120 Hz or less, the higher the refresh rate, the lower the human visual sensitivity. On the other hand, in the range in which the refresh rate of the third period P3 is higher than 120 Hz, the human visual sensitivity is constant regardless of the refresh rate. Note that, even in the range in which the refresh rate of the third period P3 is higher than 120 Hz, the higher the refresh rate, the lower the flicker rate. Also, the higher the refresh rate of the third period P3, the higher the power consumption. From these results, when the refresh rate R2 is 60 Hz, if the refresh rate R3 of the third period P3 is a frequency higher than 60 Hz, it is possible to prevent flicker from being seen, compared to the case in which the third period P3 is not provided. And, if the refresh rate R3 of the third period P3 is 120 Hz or more and 240 Hz or less, it is possible to lower (minimize) the human visual sensitivity while suppressing power consumption. If the refresh rate R3 in the third period P3 is 120 Hz, it is possible to reduce power consumption to the greatest extent while keeping the human visual sensitivity low (minimum).

[0024] FIG. 9 is a diagram for explaining the relationship between the length of the third period P3 and the human visual sensitivity and power consumption. FIG. 9 shows the human visual sensitivity at the start of the second period P2 and the power consumption in the third period P3 when the refresh rate R3 of the third period P3 is 120 Hz, the refresh rate R2 of the second period P2 is 60 Hz, and the refresh rate R1 of the first period P1 is 1 Hz. As shown in FIG. 9, if the length T3 of the third period P3 is 20 seconds or more, the human visual sensitivity can be lowered (minimum). Also, if the length T3 of the third period P3 is 18 seconds or more and 22 seconds or less, the flicker rate can be lowered while reducing the power consumption. Also, if the length T3 of the third period P3 is 20 seconds, the power consumption can be reduced to the maximum while reducing the flicker rate (minimum).

[0025] FIG. 10 is a diagram showing the relationship between the refresh rate R1 of the first period P1 and the sufficient length of the third period P3. The length T3 of the third period P3 that can reduce power consumption the most while lowering (minimizing) human visibility is defined as the "sufficient length of the third period P3." In the example of FIG. 9, the sufficient length of the third period P3 is 20 seconds. As shown in FIG. 10, the higher the refresh rate R1 of the first period P1, the shorter the sufficient length of the third period P3. For example, the sufficient length of the third period P3 is the length obtained by dividing the refresh rate R1 by 20 seconds.

[0026] [Comparison results between display devices according to the embodiment and the comparative example] Next, a comparison result between the display device 100 according to the example of this embodiment and a display device according to a comparative example will be described with reference to Fig. 11 and Fig. 12. Fig. 11 is a diagram showing the measurement result of the flicker rate of the display device according to the comparative example. Fig. 12 is a diagram showing the measurement result of the flicker rate of the display device according to the example of this embodiment.

[0027] The measurement device for the flicker rate measurement results can be a luminance measuring device CA-410 manufactured by Konica Minolta, Inc. The "flicker rate" shown in Fig. 11 and Fig. 12 was measured by the "JEITA Flicker Measurement" described in "Technical Document 2nd Edition" (September 1, 2018) of the luminance measuring device CA-410 manufactured by Konica Minolta, Inc.

[0028] As shown in Fig. 11, the measurement result of the display device according to the comparative example is a flicker rate measured from 10 seconds before to 30 seconds after the point of transition from a refresh rate of 1 Hz to a refresh rate of 60 Hz. As shown in Fig. 12, the measurement result of the display device 100 according to the embodiment is a flicker rate measured over a first period P1 in which the refresh rate R1 is 1 Hz, a second period P2 in which the refresh rate R2 is 60 Hz, and a third period P3 in which the refresh rate R3 between the first period P1 and the second period P2 is 120 Hz. The standard of the flicker rate at which flicker is recognized by humans is set to -55 dB, and when the flicker rate is -55 dB or less, it is judged as pass (indicated as "OK" in Figs. 11 and 12), and when the flicker rate is more than -55 dB, it is judged as fail (indicated as "NG" in Figs. 11 and 12).

[0029] As shown in Fig. 11, in the display device according to the comparative example, the flicker rate exceeded -55 dB for 9 seconds after the refresh rate transitioned to 60 Hz, and the display device failed. In contrast, in the display device according to the embodiment, the flicker rate was -55 dB or less in all of the first period P1, the second period P2, and the third period P3, and the display device passed the test, as shown in Fig. 12. As a result, it was found that in the embodiment, it is possible to prevent flicker from being visible when the refresh rate transitions from 1 Hz to 60 Hz.

[0030] [Variations] Although the embodiment of the invention has been described above, the above-mentioned embodiment is merely an example for carrying out the invention. Therefore, the present invention is not limited to the above-mentioned embodiment, and can be appropriately modified and carried out without departing from the spirit of the invention. Below, a modified example of the above-mentioned embodiment will be described.

[0031] (1) In the above embodiment, as an example, the refresh rate R1 is 10 Hz or less, the refresh rate R2 is 20 Hz or more and 90 Hz or less, the refresh rate R3 is 60 Hz or more and 240 Hz or less, and the length T3 of the third period P3 is 18 seconds or more and 22 seconds or less, but the present disclosure is not limited to this. The refresh rate R1 may be a frequency higher than 10 Hz. The refresh rate R2 may be a frequency lower than 20 Hz or higher than 90 Hz. As long as the refresh rate R3 is a frequency higher than the refresh rate R2, it may be a frequency lower than 60 Hz or higher than 240 Hz. The length T3 of the third period P3 may be less than 18 seconds or longer than 22 seconds.

[0032] (2) In the above embodiment, the system control circuit and the display control circuit are configured separately, but the present disclosure is not limited to this. That is, the system control circuit and the display control circuit may be configured as a single circuit (integrated circuit).

[0033] (3) In the above embodiment, the polarity of the pixel voltage Vp is inverted between positive and negative polarities for each frame during the first period P1 and the second period P2, but the present disclosure is not limited to this. The pixel voltage Vp of the same polarity may be supplied during the first period P1, or the pixel voltage Vp of the same polarity may be supplied during a part of the second period P2.

[0034] (4) In the above embodiment, the polarity of the source signal supplied to the odd-numbered source lines is opposite to that of the source signal supplied to the even-numbered source lines, but the present disclosure is not limited to this. For example, source signals of the same polarity may be supplied to all source lines.

[0035] The above-mentioned display device can also be explained as follows.

[0036] A display device according to a first configuration includes a display panel for displaying an image, the display panel including a pixel electrode and a common electrode for forming an electric field between the pixel electrode, a drive circuit for supplying a pixel voltage to the pixel electrode, and a control circuit for controlling a refresh rate, which is a frequency at which the drive circuit supplies the pixel voltage to the pixel electrode and at which an image to be displayed on the display panel is rewritten, and when the refresh rate is changed from a first frequency to a second frequency higher than the first frequency, the control circuit provides a third period between a first period in which the image to be displayed on the display panel is rewritten with the first frequency and a second period in which the image to be displayed on the display panel is rewritten with the second frequency, and during the third period, rewrites the image to be displayed on the display panel by alternately supplying a pixel voltage having a positive polarity with respect to the common voltage supplied to the common electrode and a pixel voltage having a negative polarity with respect to the common voltage at a third frequency higher than the second frequency, and which is 60 Hz or higher when the second frequency is less than 20 Hz (first configuration).

[0037] Here, in the third period, if the charge bias generated in the first period remains in the display panel, a difference occurs between the execution voltage in the positive polarity refresh and the execution voltage in the negative polarity refresh, and the luminance changes at a frequency half the third frequency. In addition, when the refresh rate is 10 Hz or more, the higher the frequency, the less likely a person is to see the flicker. Therefore, according to the first configuration, when transitioning from the first period, in which the refresh rate is low, to the second period, in which the refresh rate is high, the refresh rate in the third period can be made higher than the refresh rate in the second period. As a result, the frequency half the third frequency is higher than the frequency half the second frequency (a frequency of 10 Hz or more), so that even if the charge bias remains in the display panel in the third period, it is possible to prevent the flicker from being seen. In addition, in the third period, the polarity of the pixel voltage is inverted at a high frequency, so that it is possible to reduce the charge bias in the display panel during the third period. As a result, in the second period following the third period, it is possible to prevent flicker from being visible.

[0038] In the first configuration, the third frequency may be higher than 60 Hz and lower than or equal to 240 Hz (second configuration).

[0039] Here, even if the frequency of the luminance change is higher than 10 Hz, if it is 30 Hz or less, humans may perceive flicker. Also, the higher the refresh rate, the greater the power consumption in the display device. Therefore, according to the second configuration, half the third frequency is higher than 30 Hz, so that flicker becomes even less perceivable. And, since the third frequency is 240 Hz or less, power consumption can be reduced. As a result, it is possible to prevent flicker from being perceived while reducing power consumption.

[0040] In the second configuration, the third frequency may be a frequency equal to or greater than 120 Hz and equal to or less than 240 Hz (third configuration).

[0041] Here, if the frequency of the luminance change is 60 Hz or more, humans will be unable to see the flicker. Therefore, according to the third configuration, it is possible to more reliably prevent the flicker from being seen while reducing power consumption.

[0042] In any one of the first to third configurations, the first frequency may be a frequency equal to or greater than 1 Hz and less than 60 Hz. The second frequency may be a frequency equal to or greater than 60 Hz. The length of the third period may be equal to or greater than 18 seconds and equal to or less than 22 seconds (fourth configuration).

[0043] According to the fourth configuration, when the first frequency is equal to or greater than 1 Hz and less than 60 Hz, and the second frequency is equal to or greater than 60 Hz, if the length of the third period is equal to or greater than 18 seconds and equal to or less than 22 seconds, the bias of charge in the display panel can be sufficiently reduced during the third period. [Explanation of symbols]

[0044] 1: display panel, 2: display control circuit, 3: power supply circuit, 11: scanning line drive circuit, 12: signal line drive circuit, 13: gate line, 14: source line, 15: thin film transistor, 16: pixel electrode, 17: common electrode, 18: common wiring, 100: display device, 100a: display system, 101: system control circuit

Claims

1. A display panel for displaying an image, the display panel including pixel electrodes and a common electrode for forming an electric field between the pixel electrodes and a common electrode; A drive circuit for supplying a pixel voltage to the pixel electrode; a control circuit for controlling a refresh rate, which is a frequency at which the drive circuit supplies the pixel voltage to the pixel electrodes and is a frequency at which an image displayed on the display panel is rewritten; The control circuit includes: When changing the refresh rate from a first frequency to a second frequency higher than the first frequency, a third period is provided between a first period in which an image to be displayed on the display panel is rewritten by the first frequency and a second period in which an image to be displayed on the display panel is rewritten by the second frequency; a display device which rewrites an image displayed on the display panel by alternately supplying a pixel voltage having a positive polarity with respect to a common voltage supplied to the common electrode and a pixel voltage having a negative polarity with respect to the common voltage at a third frequency higher than the second frequency, and which is 60 Hz or higher when the second frequency is less than 20 Hz, during the third period.

2. The display device according to claim 1 , wherein the third frequency is higher than 60 Hz and is equal to or lower than 240 Hz.

3. The display device according to claim 2 , wherein the third frequency is equal to or higher than 120 Hz and equal to or lower than 240 Hz.

4. The first frequency is equal to or greater than 1 Hz and less than 60 Hz, The second frequency is equal to or greater than 60 Hz, 4. The display device according to claim 1, wherein the length of the third period is not less than 18 seconds and not more than 22 seconds.

Images